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MLK-23002 ARM: imx: Make sure system counter frequency change success…
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…fully

During system counter frequency change, the counter will stop, it
takes several mS even up to 20mS to finish the frequency change, if
system enters STOP mode before the frequency change done, system
counter will NOT run during STOP mode, then it will case system time
inaccurate and sometimes cause below RCU stall, so system can ONLY
enter STOP mode after the system counter frequency change done by
checking the ACK of frequency change.

rtc_testapp_6    0  TINFO  :    Waiting 50 seconds for alarm.......
fec 30be0000.ethernet eth0: Link is Down
PM: suspend devices took 0.670 seconds
Disabling non-boot CPUs ...
Enabling non-boot CPUs ...
rcu: INFO: rcu_sched self-detected stall on CPU
rcu:     0-...!: (1 ticks this GP) idle=1f6/1/0x40000002 softirq=5240/5240 fqs=0
 (t=4903 jiffies g=3737 q=4)
rcu: rcu_sched kthread starved for 4903 jiffies! g3737 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402 ->0
rcu: RCU grace-period kthread stack dump:
rcu_sched       I    0    10      2 0x00000000
[<c0d85a9c>] (__schedule) from [<c0d85e64>] (schedule+0x50/0xc4)
[<c0d85e64>] (schedule) from [<c0d8b8fc>] (schedule_timeout+0x1b8/0x37c)
[<c0d8b8fc>] (schedule_timeout) from [<c01b9f2c>] (rcu_gp_kthread+0x8cc/0x1678)
[<c01b9f2c>] (rcu_gp_kthread) from [<c015f12c>] (kthread+0x114/0x14c)
[<c015f12c>] (kthread) from [<c01010b4>] (ret_from_fork+0x14/0x20)
Exception stack(0xd80fdfb0 to 0xd80fdff8)
dfa0:                                     00000000 00000000 00000000 00000000
dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
NMI backtrace for cpu 0
CPU: 0 PID: 834 Comm: rtc_testapp_6 Not tainted 5.4.0-rc7-03214-g56a9ca3 Freescale#105
Hardware name: Freescale i.MX7 Dual (Device Tree)
[<c01126e4>] (unwind_backtrace) from [<c010cf3c>] (show_stack+0x10/0x14)
[<c010cf3c>] (show_stack) from [<c0d691dc>] (dump_stack+0xe4/0x118)
[<c0d691dc>] (dump_stack) from [<c0d70678>] (nmi_cpu_backtrace+0xac/0xbc)
[<c0d70678>] (nmi_cpu_backtrace) from [<c0d70768>] (nmi_trigger_cpumask_backtrace+0xe0/0x130)
[<c0d70768>] (nmi_trigger_cpumask_backtrace) from [<c01be188>] (rcu_dump_cpu_stacks+0x9c/0xd8)
[<c01be188>] (rcu_dump_cpu_stacks) from [<c01bd254>] (rcu_sched_clock_irq+0x940/0xbec)
[<c01bd254>] (rcu_sched_clock_irq) from [<c01c5758>] (update_process_times+0x2c/0x54)
[<c01c5758>] (update_process_times) from [<c01d9cf0>] (tick_sched_timer+0x5c/0xc0)
[<c01d9cf0>] (tick_sched_timer) from [<c01c6bf8>] (__hrtimer_run_queues+0x140/0x548)
[<c01c6bf8>] (__hrtimer_run_queues) from [<c01c792c>] (hrtimer_interrupt+0x134/0x2bc)
[<c01c792c>] (hrtimer_interrupt) from [<c097eb00>] (arch_timer_handler_phys+0x2c/0x34)
[<c097eb00>] (arch_timer_handler_phys) from [<c01a6b1c>] (handle_percpu_devid_irq+0xd4/0x384)
[<c01a6b1c>] (handle_percpu_devid_irq) from [<c01a072c>] (generic_handle_irq+0x20/0x34)
[<c01a072c>] (generic_handle_irq) from [<c01a0d34>] (__handle_domain_irq+0x64/0xe0)
[<c01a0d34>] (__handle_domain_irq) from [<c0548510>] (gic_handle_irq+0x4c/0xa0)
[<c0548510>] (gic_handle_irq) from [<c0101a70>] (__irq_svc+0x70/0x98)
Exception stack(0xd8cedd00 to 0xd8cedd48)
dd00: 00000001 d88a5d20 00000000 200a0013 00000000 00000000 c1b3f6f0 0000002a
dd20: d8cec000 00000000 c1b3dbf8 c1b3d6f8 c16c82bc d8cedd50 c018fe50 c019dd68
dd40: 200a0013 ffffffff
[<c0101a70>] (__irq_svc) from [<c019dd68>] (console_unlock+0x4e0/0x634)
[<c019dd68>] (console_unlock) from [<c019f6c8>] (vprintk_emit+0xf4/0x2d0)
[<c019f6c8>] (vprintk_emit) from [<c019f8c8>] (vprintk_default+0x24/0x2c)
[<c019f8c8>] (vprintk_default) from [<c019fe9c>] (printk+0x2c/0x54)
[<c019fe9c>] (printk) from [<c013b560>] (enable_nonboot_cpus+0x38/0x2cc)
[<c013b560>] (enable_nonboot_cpus) from [<c019b4d0>] (suspend_devices_and_enter+0x374/0xa44)
[<c019b4d0>] (suspend_devices_and_enter) from [<c019be8c>] (pm_suspend+0x2ec/0x3d0)
[<c019be8c>] (pm_suspend) from [<c019a088>] (state_store+0x68/0xc8)
[<c019a088>] (state_store) from [<c033305c>] (kernfs_fop_write+0xfc/0x1e0)
[<c033305c>] (kernfs_fop_write) from [<c029d278>] (__vfs_write+0x2c/0x1d0)
[<c029d278>] (__vfs_write) from [<c02a0184>] (vfs_write+0xa0/0x180)
[<c02a0184>] (vfs_write) from [<c02a03e0>] (ksys_write+0x5c/0xd8)
[<c02a03e0>] (ksys_write) from [<c0101000>] (ret_fast_syscall+0x0/0x28)
Exception stack(0xd8cedfa8 to 0xd8cedff0)
dfa0:                   00036294 00021590 00000004 bef5cd29 00000007 00000000
dfc0: 00036294 00021590 b6fc0d20 00000004 00000000 00000000 b6fc2fa4 00000000
dfe0: 00000004 bef5c8e8 b6f35d4f b6ec1d16
CPU1 is up
imx6q-pcie 33800000.pcie: Phy link never came up
imx6q-pcie 33800000.pcie: pcie link is down after resume.
mmc1: queuing unknown CIS tuple 0x80 (2 bytes)
mmc1: queuing unknown CIS tuple 0x80 (7 bytes)
mmc1: queuing unknown CIS tuple 0x80 (6 bytes)
PM: resume devices took 0.220 seconds
OOM killer enabled.
Restarting tasks ... done.
PM: suspend exit

Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Jacky Bai <[email protected]>
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Anson-Huang authored and rehsack committed May 30, 2020
1 parent d27e0b1 commit 99c521a
Showing 1 changed file with 9 additions and 0 deletions.
9 changes: 9 additions & 0 deletions arch/arm/mach-imx/pm-imx7.c
Original file line number Diff line number Diff line change
Expand Up @@ -90,6 +90,9 @@
#define BM_CCM_ROOT_MUX 0x7000000
#define BM_CCM_ROOT_ENABLE 0x10000000

#define SYS_COUNTER_CNTSR 0x4
#define BM_SYS_COUNTER_CNTSR_FCR1 0x200
#define BM_SYS_COUNTER_CNTSR_FCR0 0x100
#define BM_SYS_COUNTER_CNTCR_FCR1 0x200
#define BM_SYS_COUNTER_CNTCR_FCR0 0x100

Expand Down Expand Up @@ -743,6 +746,9 @@ static int imx7_pm_enter(suspend_state_t state)
val &= ~BM_SYS_COUNTER_CNTCR_FCR0;
val |= BM_SYS_COUNTER_CNTCR_FCR1;
writel_relaxed(val, system_counter_ctrl_base);
while (!(readl_relaxed(system_counter_ctrl_base + SYS_COUNTER_CNTSR)
& BM_SYS_COUNTER_CNTSR_FCR1))
;

switch (state) {
case PM_SUSPEND_STANDBY:
Expand Down Expand Up @@ -848,6 +854,9 @@ static int imx7_pm_enter(suspend_state_t state)
val &= ~BM_SYS_COUNTER_CNTCR_FCR1;
val |= BM_SYS_COUNTER_CNTCR_FCR0;
writel_relaxed(val, system_counter_ctrl_base);
while (!(readl_relaxed(system_counter_ctrl_base + SYS_COUNTER_CNTSR)
& BM_SYS_COUNTER_CNTSR_FCR0))
;

return 0;
}
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