-
Notifications
You must be signed in to change notification settings - Fork 5k
/
vc4_firmware_kms.c
1897 lines (1615 loc) · 51 KB
/
vc4_firmware_kms.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Copyright (C) 2016 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/**
* DOC: VC4 firmware KMS module.
*
* As a hack to get us from the current closed source driver world
* toward a totally open stack, implement KMS on top of the Raspberry
* Pi's firmware display stack.
*/
#include "drm/drm_atomic_helper.h"
#include "drm/drm_gem_framebuffer_helper.h"
#include "drm/drm_plane_helper.h"
#include "drm/drm_crtc_helper.h"
#include "drm/drm_fourcc.h"
#include "linux/clk.h"
#include "linux/debugfs.h"
#include "drm/drm_fb_cma_helper.h"
#include "linux/component.h"
#include "linux/of_device.h"
#include "vc4_drv.h"
#include "vc4_regs.h"
#include "vc_image_types.h"
#include <soc/bcm2835/raspberrypi-firmware.h>
struct get_display_cfg {
u32 max_pixel_clock[2]; //Max pixel clock for each display
};
struct vc4_fkms {
struct get_display_cfg cfg;
};
#define PLANES_PER_CRTC 3
struct set_plane {
u8 display;
u8 plane_id;
u8 vc_image_type;
s8 layer;
u16 width;
u16 height;
u16 pitch;
u16 vpitch;
u32 src_x; /* 16p16 */
u32 src_y; /* 16p16 */
u32 src_w; /* 16p16 */
u32 src_h; /* 16p16 */
s16 dst_x;
s16 dst_y;
u16 dst_w;
u16 dst_h;
u8 alpha;
u8 num_planes;
u8 is_vu;
u8 color_encoding;
u32 planes[4]; /* DMA address of each plane */
u32 transform;
};
/* Values for the transform field */
#define TRANSFORM_NO_ROTATE 0
#define TRANSFORM_ROTATE_180 BIT(1)
#define TRANSFORM_FLIP_HRIZ BIT(16)
#define TRANSFORM_FLIP_VERT BIT(17)
struct mailbox_set_plane {
struct rpi_firmware_property_tag_header tag;
struct set_plane plane;
};
struct mailbox_blank_display {
struct rpi_firmware_property_tag_header tag1;
u32 display;
struct rpi_firmware_property_tag_header tag2;
u32 blank;
};
struct mailbox_display_pwr {
struct rpi_firmware_property_tag_header tag1;
u32 display;
u32 state;
};
struct mailbox_get_edid {
struct rpi_firmware_property_tag_header tag1;
u32 block;
u32 display_number;
u8 edid[128];
};
struct set_timings {
u8 display;
u8 padding;
u16 video_id_code;
u32 clock; /* in kHz */
u16 hdisplay;
u16 hsync_start;
u16 hsync_end;
u16 htotal;
u16 hskew;
u16 vdisplay;
u16 vsync_start;
u16 vsync_end;
u16 vtotal;
u16 vscan;
u16 vrefresh;
u16 padding2;
u32 flags;
#define TIMINGS_FLAGS_H_SYNC_POS BIT(0)
#define TIMINGS_FLAGS_H_SYNC_NEG 0
#define TIMINGS_FLAGS_V_SYNC_POS BIT(1)
#define TIMINGS_FLAGS_V_SYNC_NEG 0
#define TIMINGS_FLAGS_INTERLACE BIT(2)
#define TIMINGS_FLAGS_ASPECT_MASK GENMASK(7, 4)
#define TIMINGS_FLAGS_ASPECT_NONE (0 << 4)
#define TIMINGS_FLAGS_ASPECT_4_3 (1 << 4)
#define TIMINGS_FLAGS_ASPECT_16_9 (2 << 4)
#define TIMINGS_FLAGS_ASPECT_64_27 (3 << 4)
#define TIMINGS_FLAGS_ASPECT_256_135 (4 << 4)
/* Limited range RGB flag. Not set corresponds to full range. */
#define TIMINGS_FLAGS_RGB_LIMITED BIT(8)
/* DVI monitor, therefore disable infoframes. Not set corresponds to HDMI. */
#define TIMINGS_FLAGS_DVI BIT(9)
};
struct mailbox_set_mode {
struct rpi_firmware_property_tag_header tag1;
struct set_timings timings;
};
static const struct vc_image_format {
u32 drm; /* DRM_FORMAT_* */
u32 vc_image; /* VC_IMAGE_* */
u32 is_vu;
} vc_image_formats[] = {
{
.drm = DRM_FORMAT_XRGB8888,
.vc_image = VC_IMAGE_XRGB8888,
},
{
.drm = DRM_FORMAT_ARGB8888,
.vc_image = VC_IMAGE_ARGB8888,
},
/*
* FIXME: Need to resolve which DRM format goes to which vc_image format
* for the remaining RGBA and RGBX formats.
* {
* .drm = DRM_FORMAT_ABGR8888,
* .vc_image = VC_IMAGE_RGBA8888,
* },
* {
* .drm = DRM_FORMAT_XBGR8888,
* .vc_image = VC_IMAGE_RGBA8888,
* },
*/
{
.drm = DRM_FORMAT_RGB565,
.vc_image = VC_IMAGE_RGB565,
},
{
.drm = DRM_FORMAT_RGB888,
.vc_image = VC_IMAGE_BGR888,
},
{
.drm = DRM_FORMAT_BGR888,
.vc_image = VC_IMAGE_RGB888,
},
{
.drm = DRM_FORMAT_YUV422,
.vc_image = VC_IMAGE_YUV422PLANAR,
},
{
.drm = DRM_FORMAT_YUV420,
.vc_image = VC_IMAGE_YUV420,
},
{
.drm = DRM_FORMAT_YVU420,
.vc_image = VC_IMAGE_YUV420,
.is_vu = 1,
},
{
.drm = DRM_FORMAT_NV12,
.vc_image = VC_IMAGE_YUV420SP,
},
{
.drm = DRM_FORMAT_NV21,
.vc_image = VC_IMAGE_YUV420SP,
.is_vu = 1,
},
};
static const struct vc_image_format *vc4_get_vc_image_fmt(u32 drm_format)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(vc_image_formats); i++) {
if (vc_image_formats[i].drm == drm_format)
return &vc_image_formats[i];
}
return NULL;
}
/* The firmware delivers a vblank interrupt to us through the SMI
* hardware, which has only this one register.
*/
#define SMICS 0x0
#define SMIDSW0 0x14
#define SMIDSW1 0x1C
#define SMICS_INTERRUPTS (BIT(9) | BIT(10) | BIT(11))
/* Flag to denote that the firmware is giving multiple display callbacks */
#define SMI_NEW 0xabcd0000
#define vc4_crtc vc4_kms_crtc
#define to_vc4_crtc to_vc4_kms_crtc
struct vc4_crtc {
struct drm_crtc base;
struct drm_encoder *encoder;
struct drm_connector *connector;
void __iomem *regs;
struct drm_pending_vblank_event *event;
bool vblank_enabled;
u32 display_number;
u32 display_type;
};
static inline struct vc4_crtc *to_vc4_crtc(struct drm_crtc *crtc)
{
return container_of(crtc, struct vc4_crtc, base);
}
struct vc4_crtc_state {
struct drm_crtc_state base;
struct {
unsigned int left;
unsigned int right;
unsigned int top;
unsigned int bottom;
} margins;
};
static inline struct vc4_crtc_state *
to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
{
return (struct vc4_crtc_state *)crtc_state;
}
struct vc4_fkms_encoder {
struct drm_encoder base;
bool hdmi_monitor;
bool rgb_range_selectable;
int display_num;
};
static inline struct vc4_fkms_encoder *
to_vc4_fkms_encoder(struct drm_encoder *encoder)
{
return container_of(encoder, struct vc4_fkms_encoder, base);
}
/* "Broadcast RGB" property.
* Allows overriding of HDMI full or limited range RGB
*/
#define VC4_BROADCAST_RGB_AUTO 0
#define VC4_BROADCAST_RGB_FULL 1
#define VC4_BROADCAST_RGB_LIMITED 2
/* VC4 FKMS connector KMS struct */
struct vc4_fkms_connector {
struct drm_connector base;
/* Since the connector is attached to just the one encoder,
* this is the reference to it so we can do the best_encoder()
* hook.
*/
struct drm_encoder *encoder;
struct vc4_dev *vc4_dev;
u32 display_number;
u32 display_type;
struct drm_property *broadcast_rgb_property;
};
static inline struct vc4_fkms_connector *
to_vc4_fkms_connector(struct drm_connector *connector)
{
return container_of(connector, struct vc4_fkms_connector, base);
}
/* VC4 FKMS connector state */
struct vc4_fkms_connector_state {
struct drm_connector_state base;
int broadcast_rgb;
};
#define to_vc4_fkms_connector_state(x) \
container_of(x, struct vc4_fkms_connector_state, base)
static u32 vc4_get_display_type(u32 display_number)
{
const u32 display_types[] = {
/* The firmware display (DispmanX) IDs map to specific types in
* a fixed manner.
*/
DRM_MODE_ENCODER_DSI, /* MAIN_LCD - DSI or DPI */
DRM_MODE_ENCODER_DSI, /* AUX_LCD */
DRM_MODE_ENCODER_TMDS, /* HDMI0 */
DRM_MODE_ENCODER_TVDAC, /* VEC */
DRM_MODE_ENCODER_NONE, /* FORCE_LCD */
DRM_MODE_ENCODER_NONE, /* FORCE_TV */
DRM_MODE_ENCODER_NONE, /* FORCE_OTHER */
DRM_MODE_ENCODER_TMDS, /* HDMI1 */
DRM_MODE_ENCODER_NONE, /* FORCE_TV2 */
};
return display_number > ARRAY_SIZE(display_types) - 1 ?
DRM_MODE_ENCODER_NONE : display_types[display_number];
}
/* Firmware's structure for making an FB mbox call. */
struct fbinfo_s {
u32 xres, yres, xres_virtual, yres_virtual;
u32 pitch, bpp;
u32 xoffset, yoffset;
u32 base;
u32 screen_size;
u16 cmap[256];
};
struct vc4_fkms_plane {
struct drm_plane base;
struct fbinfo_s *fbinfo;
dma_addr_t fbinfo_bus_addr;
u32 pitch;
struct mailbox_set_plane mb;
};
static inline struct vc4_fkms_plane *to_vc4_fkms_plane(struct drm_plane *plane)
{
return (struct vc4_fkms_plane *)plane;
}
static int vc4_plane_set_blank(struct drm_plane *plane, bool blank)
{
struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
struct vc4_fkms_plane *vc4_plane = to_vc4_fkms_plane(plane);
struct mailbox_set_plane blank_mb = {
.tag = { RPI_FIRMWARE_SET_PLANE, sizeof(struct set_plane), 0 },
.plane = {
.display = vc4_plane->mb.plane.display,
.plane_id = vc4_plane->mb.plane.plane_id,
}
};
static const char * const plane_types[] = {
"overlay",
"primary",
"cursor"
};
int ret;
DRM_DEBUG_ATOMIC("[PLANE:%d:%s] %s plane %s",
plane->base.id, plane->name, plane_types[plane->type],
blank ? "blank" : "unblank");
if (blank)
ret = rpi_firmware_property_list(vc4->firmware, &blank_mb,
sizeof(blank_mb));
else
ret = rpi_firmware_property_list(vc4->firmware, &vc4_plane->mb,
sizeof(vc4_plane->mb));
WARN_ONCE(ret, "%s: firmware call failed. Please update your firmware",
__func__);
return ret;
}
static void vc4_fkms_crtc_get_margins(struct drm_crtc_state *state,
unsigned int *left, unsigned int *right,
unsigned int *top, unsigned int *bottom)
{
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
*left = vc4_state->margins.left;
*right = vc4_state->margins.right;
*top = vc4_state->margins.top;
*bottom = vc4_state->margins.bottom;
/* We have to interate over all new connector states because
* vc4_fkms_crtc_get_margins() might be called before
* vc4_fkms_crtc_atomic_check() which means margins info in
* vc4_crtc_state might be outdated.
*/
for_each_new_connector_in_state(state->state, conn, conn_state, i) {
if (conn_state->crtc != state->crtc)
continue;
*left = conn_state->tv.margins.left;
*right = conn_state->tv.margins.right;
*top = conn_state->tv.margins.top;
*bottom = conn_state->tv.margins.bottom;
break;
}
}
static int vc4_fkms_margins_adj(struct drm_plane_state *pstate,
struct set_plane *plane)
{
unsigned int left, right, top, bottom;
int adjhdisplay, adjvdisplay;
struct drm_crtc_state *crtc_state;
crtc_state = drm_atomic_get_new_crtc_state(pstate->state,
pstate->crtc);
vc4_fkms_crtc_get_margins(crtc_state, &left, &right, &top, &bottom);
if (!left && !right && !top && !bottom)
return 0;
if (left + right >= crtc_state->mode.hdisplay ||
top + bottom >= crtc_state->mode.vdisplay)
return -EINVAL;
adjhdisplay = crtc_state->mode.hdisplay - (left + right);
plane->dst_x = DIV_ROUND_CLOSEST(plane->dst_x * adjhdisplay,
(int)crtc_state->mode.hdisplay);
plane->dst_x += left;
if (plane->dst_x > (int)(crtc_state->mode.hdisplay - left))
plane->dst_x = crtc_state->mode.hdisplay - left;
adjvdisplay = crtc_state->mode.vdisplay - (top + bottom);
plane->dst_y = DIV_ROUND_CLOSEST(plane->dst_y * adjvdisplay,
(int)crtc_state->mode.vdisplay);
plane->dst_y += top;
if (plane->dst_y > (int)(crtc_state->mode.vdisplay - top))
plane->dst_y = crtc_state->mode.vdisplay - top;
plane->dst_w = DIV_ROUND_CLOSEST(plane->dst_w * adjhdisplay,
crtc_state->mode.hdisplay);
plane->dst_h = DIV_ROUND_CLOSEST(plane->dst_h * adjvdisplay,
crtc_state->mode.vdisplay);
if (!plane->dst_w || !plane->dst_h)
return -EINVAL;
return 0;
}
static void vc4_plane_atomic_update(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
struct drm_plane_state *state = plane->state;
/*
* Do NOT set now, as we haven't checked if the crtc is active or not.
* Set from vc4_plane_set_blank instead.
*
* If the CRTC is on (or going to be on) and we're enabled,
* then unblank. Otherwise, stay blank until CRTC enable.
*/
if (state->crtc->state->active)
vc4_plane_set_blank(plane, false);
}
static void vc4_plane_atomic_disable(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
struct drm_plane_state *state = plane->state;
struct vc4_fkms_plane *vc4_plane = to_vc4_fkms_plane(plane);
DRM_DEBUG_ATOMIC("[PLANE:%d:%s] plane disable %dx%d@%d +%d,%d\n",
plane->base.id, plane->name,
state->crtc_w,
state->crtc_h,
vc4_plane->mb.plane.vc_image_type,
state->crtc_x,
state->crtc_y);
vc4_plane_set_blank(plane, true);
}
static bool plane_enabled(struct drm_plane_state *state)
{
return state->fb && state->crtc;
}
static int vc4_plane_to_mb(struct drm_plane *plane,
struct mailbox_set_plane *mb,
struct drm_plane_state *state)
{
struct drm_framebuffer *fb = state->fb;
struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
const struct drm_format_info *drm_fmt = fb->format;
const struct vc_image_format *vc_fmt =
vc4_get_vc_image_fmt(drm_fmt->format);
int num_planes = fb->format->num_planes;
unsigned int rotation;
mb->plane.vc_image_type = vc_fmt->vc_image;
mb->plane.width = fb->width;
mb->plane.height = fb->height;
mb->plane.pitch = fb->pitches[0];
mb->plane.src_w = state->src_w;
mb->plane.src_h = state->src_h;
mb->plane.src_x = state->src_x;
mb->plane.src_y = state->src_y;
mb->plane.dst_w = state->crtc_w;
mb->plane.dst_h = state->crtc_h;
mb->plane.dst_x = state->crtc_x;
mb->plane.dst_y = state->crtc_y;
mb->plane.alpha = state->alpha >> 8;
mb->plane.layer = state->normalized_zpos ?
state->normalized_zpos : -127;
mb->plane.num_planes = num_planes;
mb->plane.is_vu = vc_fmt->is_vu;
mb->plane.planes[0] = bo->paddr + fb->offsets[0];
rotation = drm_rotation_simplify(state->rotation,
DRM_MODE_ROTATE_0 |
DRM_MODE_REFLECT_X |
DRM_MODE_REFLECT_Y);
mb->plane.transform = TRANSFORM_NO_ROTATE;
if (rotation & DRM_MODE_REFLECT_X)
mb->plane.transform |= TRANSFORM_FLIP_HRIZ;
if (rotation & DRM_MODE_REFLECT_Y)
mb->plane.transform |= TRANSFORM_FLIP_VERT;
vc4_fkms_margins_adj(state, &mb->plane);
if (num_planes > 1) {
/* Assume this must be YUV */
/* Makes assumptions on the stride for the chroma planes as we
* can't easily plumb in non-standard pitches.
*/
mb->plane.planes[1] = bo->paddr + fb->offsets[1];
if (num_planes > 2)
mb->plane.planes[2] = bo->paddr + fb->offsets[2];
else
mb->plane.planes[2] = 0;
/* Special case the YUV420 with U and V as line interleaved
* planes as we have special handling for that case.
*/
if (num_planes == 3 &&
(fb->offsets[2] - fb->offsets[1]) == fb->pitches[1])
mb->plane.vc_image_type = VC_IMAGE_YUV420_S;
switch (state->color_encoding) {
default:
case DRM_COLOR_YCBCR_BT601:
if (state->color_range == DRM_COLOR_YCBCR_LIMITED_RANGE)
mb->plane.color_encoding =
VC_IMAGE_YUVINFO_CSC_ITUR_BT601;
else
mb->plane.color_encoding =
VC_IMAGE_YUVINFO_CSC_JPEG_JFIF;
break;
case DRM_COLOR_YCBCR_BT709:
/* Currently no support for a full range BT709 */
mb->plane.color_encoding =
VC_IMAGE_YUVINFO_CSC_ITUR_BT709;
break;
case DRM_COLOR_YCBCR_BT2020:
/* Currently no support for a full range BT2020 */
mb->plane.color_encoding =
VC_IMAGE_YUVINFO_CSC_REC_2020;
break;
}
} else {
mb->plane.planes[1] = 0;
mb->plane.planes[2] = 0;
}
mb->plane.planes[3] = 0;
switch (fourcc_mod_broadcom_mod(fb->modifier)) {
case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
switch (mb->plane.vc_image_type) {
case VC_IMAGE_XRGB8888:
mb->plane.vc_image_type = VC_IMAGE_TF_RGBX32;
break;
case VC_IMAGE_ARGB8888:
mb->plane.vc_image_type = VC_IMAGE_TF_RGBA32;
break;
case VC_IMAGE_RGB565:
mb->plane.vc_image_type = VC_IMAGE_TF_RGB565;
break;
}
break;
case DRM_FORMAT_MOD_BROADCOM_SAND128:
mb->plane.vc_image_type = VC_IMAGE_YUV_UV;
/* Note that the column pitch is passed across in lines, not
* bytes.
*/
mb->plane.pitch = fourcc_mod_broadcom_param(fb->modifier);
break;
}
DRM_DEBUG_ATOMIC("[PLANE:%d:%s] plane update %dx%d@%d +dst(%d,%d, %d,%d) +src(%d,%d, %d,%d) 0x%08x/%08x/%08x/%d, alpha %u zpos %u\n",
plane->base.id, plane->name,
mb->plane.width,
mb->plane.height,
mb->plane.vc_image_type,
state->crtc_x,
state->crtc_y,
state->crtc_w,
state->crtc_h,
mb->plane.src_x,
mb->plane.src_y,
mb->plane.src_w,
mb->plane.src_h,
mb->plane.planes[0],
mb->plane.planes[1],
mb->plane.planes[2],
fb->pitches[0],
state->alpha,
state->normalized_zpos);
return 0;
}
static int vc4_plane_atomic_check(struct drm_plane *plane,
struct drm_plane_state *state)
{
struct vc4_fkms_plane *vc4_plane = to_vc4_fkms_plane(plane);
if (!plane_enabled(state))
return 0;
return vc4_plane_to_mb(plane, &vc4_plane->mb, state);
}
static void vc4_plane_destroy(struct drm_plane *plane)
{
drm_plane_helper_disable(plane, NULL);
drm_plane_cleanup(plane);
}
static bool vc4_fkms_format_mod_supported(struct drm_plane *plane,
uint32_t format,
uint64_t modifier)
{
/* Support T_TILING for RGB formats only. */
switch (format) {
case DRM_FORMAT_XRGB8888:
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_RGB565:
switch (modifier) {
case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
case DRM_FORMAT_MOD_LINEAR:
case DRM_FORMAT_MOD_BROADCOM_UIF:
return true;
default:
return false;
}
case DRM_FORMAT_NV12:
switch (fourcc_mod_broadcom_mod(modifier)) {
case DRM_FORMAT_MOD_LINEAR:
case DRM_FORMAT_MOD_BROADCOM_SAND128:
return true;
default:
return false;
}
case DRM_FORMAT_NV21:
case DRM_FORMAT_RGB888:
case DRM_FORMAT_BGR888:
case DRM_FORMAT_YUV422:
case DRM_FORMAT_YUV420:
case DRM_FORMAT_YVU420:
default:
return (modifier == DRM_FORMAT_MOD_LINEAR);
}
}
static const struct drm_plane_funcs vc4_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
.destroy = vc4_plane_destroy,
.set_property = NULL,
.reset = drm_atomic_helper_plane_reset,
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
.format_mod_supported = vc4_fkms_format_mod_supported,
};
static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {
.prepare_fb = drm_gem_fb_prepare_fb,
.cleanup_fb = NULL,
.atomic_check = vc4_plane_atomic_check,
.atomic_update = vc4_plane_atomic_update,
.atomic_disable = vc4_plane_atomic_disable,
};
static struct drm_plane *vc4_fkms_plane_init(struct drm_device *dev,
enum drm_plane_type type,
u8 display_num,
u8 plane_id)
{
struct drm_plane *plane = NULL;
struct vc4_fkms_plane *vc4_plane;
u32 formats[ARRAY_SIZE(vc_image_formats)];
unsigned int default_zpos;
u32 num_formats = 0;
int ret = 0;
static const uint64_t modifiers[] = {
DRM_FORMAT_MOD_LINEAR,
/* VC4_T_TILED should come after linear, because we
* would prefer to scan out linear (less bus traffic).
*/
DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
DRM_FORMAT_MOD_BROADCOM_SAND128,
DRM_FORMAT_MOD_INVALID,
};
int i;
vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane),
GFP_KERNEL);
if (!vc4_plane) {
ret = -ENOMEM;
goto fail;
}
for (i = 0; i < ARRAY_SIZE(vc_image_formats); i++)
formats[num_formats++] = vc_image_formats[i].drm;
plane = &vc4_plane->base;
ret = drm_universal_plane_init(dev, plane, 0xff,
&vc4_plane_funcs,
formats, num_formats, modifiers,
type, NULL);
/* FIXME: Do we need to be checking return values from all these calls?
*/
drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
drm_plane_create_alpha_property(plane);
drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
DRM_MODE_ROTATE_0 |
DRM_MODE_ROTATE_180 |
DRM_MODE_REFLECT_X |
DRM_MODE_REFLECT_Y);
drm_plane_create_color_properties(plane,
BIT(DRM_COLOR_YCBCR_BT601) |
BIT(DRM_COLOR_YCBCR_BT709) |
BIT(DRM_COLOR_YCBCR_BT2020),
BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
BIT(DRM_COLOR_YCBCR_FULL_RANGE),
DRM_COLOR_YCBCR_BT709,
DRM_COLOR_YCBCR_LIMITED_RANGE);
/*
* Default frame buffer setup is with FB on -127, and raspistill etc
* tend to drop overlays on layer 2. Cursor plane was on layer +127.
*
* For F-KMS the mailbox call allows for a s8.
* Remap zpos 0 to -127 for the background layer, but leave all the
* other layers as requested by KMS.
*/
switch (type) {
default:
case DRM_PLANE_TYPE_PRIMARY:
default_zpos = 0;
break;
case DRM_PLANE_TYPE_OVERLAY:
default_zpos = 1;
break;
case DRM_PLANE_TYPE_CURSOR:
default_zpos = 2;
break;
}
drm_plane_create_zpos_property(plane, default_zpos, 0, 127);
/* Prepare the static elements of the mailbox structure */
vc4_plane->mb.tag.tag = RPI_FIRMWARE_SET_PLANE;
vc4_plane->mb.tag.buf_size = sizeof(struct set_plane);
vc4_plane->mb.tag.req_resp_size = 0;
vc4_plane->mb.plane.display = display_num;
vc4_plane->mb.plane.plane_id = plane_id;
vc4_plane->mb.plane.layer = default_zpos ? default_zpos : -127;
return plane;
fail:
if (plane)
vc4_plane_destroy(plane);
return ERR_PTR(ret);
}
static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
struct vc4_fkms_encoder *vc4_encoder =
to_vc4_fkms_encoder(vc4_crtc->encoder);
struct mailbox_set_mode mb = {
.tag1 = { RPI_FIRMWARE_SET_TIMING,
sizeof(struct set_timings), 0},
};
union hdmi_infoframe frame;
int ret;
ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode, false);
if (ret < 0) {
DRM_ERROR("couldn't fill AVI infoframe\n");
return;
}
DRM_DEBUG_KMS("Setting mode for display num %u mode name %s, clk %d, h(disp %d, start %d, end %d, total %d, skew %d) v(disp %d, start %d, end %d, total %d, scan %d), vrefresh %d, par %u, flags 0x%04x\n",
vc4_crtc->display_number, mode->name, mode->clock,
mode->hdisplay, mode->hsync_start, mode->hsync_end,
mode->htotal, mode->hskew, mode->vdisplay,
mode->vsync_start, mode->vsync_end, mode->vtotal,
mode->vscan, drm_mode_vrefresh(mode),
mode->picture_aspect_ratio, mode->flags);
mb.timings.display = vc4_crtc->display_number;
mb.timings.clock = mode->clock;
mb.timings.hdisplay = mode->hdisplay;
mb.timings.hsync_start = mode->hsync_start;
mb.timings.hsync_end = mode->hsync_end;
mb.timings.htotal = mode->htotal;
mb.timings.hskew = mode->hskew;
mb.timings.vdisplay = mode->vdisplay;
mb.timings.vsync_start = mode->vsync_start;
mb.timings.vsync_end = mode->vsync_end;
mb.timings.vtotal = mode->vtotal;
mb.timings.vscan = mode->vscan;
mb.timings.vrefresh = drm_mode_vrefresh(mode);
mb.timings.flags = 0;
if (mode->flags & DRM_MODE_FLAG_PHSYNC)
mb.timings.flags |= TIMINGS_FLAGS_H_SYNC_POS;
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
mb.timings.flags |= TIMINGS_FLAGS_V_SYNC_POS;
switch (frame.avi.picture_aspect) {
default:
case HDMI_PICTURE_ASPECT_NONE:
mb.timings.flags |= TIMINGS_FLAGS_ASPECT_NONE;
break;
case HDMI_PICTURE_ASPECT_4_3:
mb.timings.flags |= TIMINGS_FLAGS_ASPECT_4_3;
break;
case HDMI_PICTURE_ASPECT_16_9:
mb.timings.flags |= TIMINGS_FLAGS_ASPECT_16_9;
break;
case HDMI_PICTURE_ASPECT_64_27:
mb.timings.flags |= TIMINGS_FLAGS_ASPECT_64_27;
break;
case HDMI_PICTURE_ASPECT_256_135:
mb.timings.flags |= TIMINGS_FLAGS_ASPECT_256_135;
break;
}
if (!vc4_encoder->hdmi_monitor) {
mb.timings.flags |= TIMINGS_FLAGS_DVI;
mb.timings.video_id_code = frame.avi.video_code;
} else {
struct vc4_fkms_connector_state *conn_state =
to_vc4_fkms_connector_state(vc4_crtc->connector->state);
/* Do not provide a VIC as the HDMI spec requires that we do not
* signal the opposite of the defined range in the AVI
* infoframe.
*/
mb.timings.video_id_code = 0;
if (conn_state->broadcast_rgb == VC4_BROADCAST_RGB_AUTO) {
/* See CEA-861-E - 5.1 Default Encoding Parameters */
if (drm_default_rgb_quant_range(mode) ==
HDMI_QUANTIZATION_RANGE_LIMITED)
mb.timings.flags |= TIMINGS_FLAGS_RGB_LIMITED;
} else {
if (conn_state->broadcast_rgb ==
VC4_BROADCAST_RGB_LIMITED)
mb.timings.flags |= TIMINGS_FLAGS_RGB_LIMITED;
}
}
/*
FIXME: To implement
switch(mode->flag & DRM_MODE_FLAG_3D_MASK) {
case DRM_MODE_FLAG_3D_NONE:
case DRM_MODE_FLAG_3D_FRAME_PACKING:
case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
case DRM_MODE_FLAG_3D_L_DEPTH:
case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
}
*/
ret = rpi_firmware_property_list(vc4->firmware, &mb, sizeof(mb));
}
static void vc4_crtc_disable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
{
struct drm_device *dev = crtc->dev;
struct drm_plane *plane;
DRM_DEBUG_KMS("[CRTC:%d] vblanks off.\n",
crtc->base.id);
drm_crtc_vblank_off(crtc);
/* Always turn the planes off on CRTC disable. In DRM, planes
* are enabled/disabled through the update/disable hooks
* above, and the CRTC enable/disable independently controls
* whether anything scans out at all, but the firmware doesn't
* give us a CRTC-level control for that.
*/
drm_atomic_crtc_for_each_plane(plane, crtc)
vc4_plane_atomic_disable(plane, plane->state);
/*
* Make sure we issue a vblank event after disabling the CRTC if
* someone was waiting it.
*/
if (crtc->state->event) {
unsigned long flags;
spin_lock_irqsave(&dev->event_lock, flags);
drm_crtc_send_vblank_event(crtc, crtc->state->event);
crtc->state->event = NULL;
spin_unlock_irqrestore(&dev->event_lock, flags);
}
}
static void vc4_crtc_consume_event(struct drm_crtc *crtc)
{
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
struct drm_device *dev = crtc->dev;
unsigned long flags;
if (!crtc->state->event)
return;
crtc->state->event->pipe = drm_crtc_index(crtc);
WARN_ON(drm_crtc_vblank_get(crtc) != 0);
spin_lock_irqsave(&dev->event_lock, flags);
vc4_crtc->event = crtc->state->event;
crtc->state->event = NULL;
spin_unlock_irqrestore(&dev->event_lock, flags);
}
static void vc4_crtc_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
{
struct drm_plane *plane;
DRM_DEBUG_KMS("[CRTC:%d] vblanks on.\n",
crtc->base.id);
drm_crtc_vblank_on(crtc);
vc4_crtc_consume_event(crtc);
/* Unblank the planes (if they're supposed to be displayed). */
drm_atomic_crtc_for_each_plane(plane, crtc)
if (plane->state->fb)
vc4_plane_set_blank(plane, plane->state->visible);
}
static enum drm_mode_status
vc4_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
{