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plugin_cs.c
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/* radare2 - LGPL - Copyright 2013-2023 - pancake */
#include <r_arch.h>
#include <sdb/ht_uu.h>
#include <capstone/capstone.h>
#include <capstone/arm.h>
#include <r_util/r_assert.h>
#include "arm_hacks.inc.c"
#include "asm_arm_hacks.inc.c"
#include "arm_regprofile.inc.c"
typedef char RStringShort[32];
typedef struct plugin_data_t {
bool bigendian;
int bits;
char *cpu;
csh cs_handle;
HtUU *ht_itblock;
HtUU *ht_it;
} PluginData;
static inline csh *cs_handle_for_session(RArchSession *as) {
r_return_val_if_fail (as && as->data, NULL);
PluginData *pd = (PluginData*) as->data;
return &(pd->cs_handle);
}
static inline HtUU *ht_itblock_for_session (RArchSession *as) {
r_return_val_if_fail (as && as->data, NULL);
PluginData *pd = (PluginData*) as->data;
return pd->ht_itblock;
}
static inline HtUU *ht_it_for_session (RArchSession *as) {
r_return_val_if_fail (as && as->data, NULL);
PluginData *pd = (PluginData*) as->data;
return pd->ht_it;
}
/* arm64 */
#define IMM64(x) (ut64)(insn->detail->arm64.operands[x].imm)
#define INSOP64(x) insn->detail->arm64.operands[x]
/* arm32 */
#define REG(x) r_str_getf (cs_reg_name (*handle, insn->detail->arm.operands[x].reg))
#define REG64(x) r_str_getf (cs_reg_name (*handle, insn->detail->arm64.operands[x].reg))
#define REGID64(x) insn->detail->arm64.operands[x].reg
#define REGID(x) insn->detail->arm.operands[x].reg
#define IMM(x) (ut32)(insn->detail->arm.operands[x].imm)
#define INSOP(x) insn->detail->arm.operands[x]
#define MEMBASE(x) r_str_getf (cs_reg_name (*handle, insn->detail->arm.operands[x].mem.base))
#define MEMBASE64(x) r_str_getf (cs_reg_name (*handle, insn->detail->arm64.operands[x].mem.base))
#define REGBASE(x) insn->detail->arm.operands[x].mem.base
#define REGBASE64(x) insn->detail->arm64.operands[x].mem.base
// s/index/base|reg/
#define MEMINDEX(x) r_str_getf (cs_reg_name (*handle, insn->detail->arm.operands[x].mem.index))
#define HASMEMINDEX(x) (insn->detail->arm.operands[x].mem.index != ARM_REG_INVALID)
#define MEMINDEX64(x) r_str_getf (cs_reg_name (*handle, insn->detail->arm64.operands[x].mem.index))
#define HASMEMINDEX64(x) (insn->detail->arm64.operands[x].mem.index != ARM64_REG_INVALID)
#define ISMEMINDEXSUB(x) insn->detail->arm.operands[x].subtracted
#define MEMDISP(x) insn->detail->arm.operands[x].mem.disp
#define MEMDISP64(x) (ut64)insn->detail->arm64.operands[x].mem.disp
#define ISIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_IMM)
#define ISIMM64(x) (insn->detail->arm64.operands[x].type & (ARM64_OP_IMM | ARM64_OP_CIMM | ARM64_OP_FP))
#define ISREG(x) (insn->detail->arm.operands[x].type == ARM_OP_REG)
#define ISREG64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_REG)
#define ISMEM(x) (insn->detail->arm.operands[x].type == ARM_OP_MEM)
#define ISMEM64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_MEM)
#define EXT64(x) decode_sign_ext (insn->detail->arm64.operands[x].ext)
#if CS_API_MAJOR > 3
#define LSHIFT(x) insn->detail->arm.operands[x].mem.lshift
#define LSHIFT2(x) insn->detail->arm.operands[x].shift.value // Dangerous, returns value even if isn't LSL
#define LSHIFT2_64(x) insn->detail->arm64.operands[x].shift.value
#else
#define LSHIFT(x) 0
#define LSHIFT2(x) 0
#define LSHIFT2_64(x) 0
#endif
#define OPCOUNT() insn->detail->arm.op_count
#define OPCOUNT64() insn->detail->arm64.op_count
#define ISSHIFTED(x) (insn->detail->arm.operands[x].shift.type != ARM_SFT_INVALID && insn->detail->arm.operands[x].shift.value != 0)
#define ISSHIFTED64(x) (insn->detail->arm64.operands[x].shift.type != ARM64_SFT_INVALID && insn->detail->arm64.operands[x].shift.value != 0)
#define SHIFTTYPE(x) insn->detail->arm.operands[x].shift.type
#define SHIFTTYPEREG(x) (\
SHIFTTYPE(x) == ARM_SFT_ASR_REG || SHIFTTYPE(x) == ARM_SFT_LSL_REG || \
SHIFTTYPE(x) == ARM_SFT_LSR_REG || SHIFTTYPE(x) == ARM_SFT_ROR_REG || \
SHIFTTYPE(x) == ARM_SFT_RRX_REG)
#define SHIFTVALUE(x) insn->detail->arm.operands[x].shift.value
#define ISWRITEBACK32() insn->detail->arm.writeback
#define ISPREINDEX32() (((OPCOUNT () == 2) && (ISMEM (1)) && (ISWRITEBACK32 ())) || ((OPCOUNT () == 3) && (ISMEM (2)) && (ISWRITEBACK32 ())))
#define ISPOSTINDEX32() (((OPCOUNT () == 3) && (ISIMM (2) || ISREG (2)) && (ISWRITEBACK32 ())) || ((OPCOUNT () == 4) && (ISIMM (3) || ISREG (3)) && (ISWRITEBACK32 ())))
#define ISWRITEBACK64() (insn->detail->arm64.writeback == true)
#define ISPREINDEX64() (((OPCOUNT64() == 2) && (ISMEM64(1)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 3) && (ISMEM64(2)) && (ISWRITEBACK64())))
#define ISPOSTINDEX64() (((OPCOUNT64() == 3) && (ISIMM64(2)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 4) && (ISIMM64(3)) && (ISWRITEBACK64())))
#define BITMASK_BY_WIDTH_COUNT 64
static const ut64 bitmask_by_width[BITMASK_BY_WIDTH_COUNT] = {
0x1, 0x3, 0x7, 0xf, 0x1f, 0x3f, 0x7f, 0xff, 0x1ff, 0x3ff, 0x7ff,
0xfff, 0x1fff, 0x3fff, 0x7fff, 0xffff, 0x1ffff, 0x3ffff, 0x7ffff,
0xfffff, 0x1fffff, 0x3fffff, 0x7fffff, 0xffffff, 0x1ffffffLL, 0x3ffffffLL,
0x7ffffffLL, 0xfffffffLL, 0x1fffffffLL, 0x3fffffffLL, 0x7fffffffLL, 0xffffffffLL,
0x1ffffffffLL, 0x3ffffffffLL, 0x7ffffffffLL, 0xfffffffffLL, 0x1fffffffffLL,
0x3fffffffffLL, 0x7fffffffffLL, 0xffffffffffLL, 0x1ffffffffffLL, 0x3ffffffffffLL,
0x7ffffffffffLL, 0xfffffffffffLL, 0x1fffffffffffLL, 0x3fffffffffffLL, 0x7fffffffffffLL,
0xffffffffffffLL, 0x1ffffffffffffLL, 0x3ffffffffffffLL, 0x7ffffffffffffLL,
0xfffffffffffffLL, 0x1fffffffffffffLL, 0x3fffffffffffffLL, 0x7fffffffffffffLL,
0xffffffffffffffLL, 0x1ffffffffffffffLL, 0x3ffffffffffffffLL, 0x7ffffffffffffffLL,
0xfffffffffffffffLL, 0x1fffffffffffffffLL, 0x3fffffffffffffffLL, 0x7fffffffffffffffLL, 0xffffffffffffffffLL
};
static const char *shift_type_name(arm_shifter type) {
switch (type) {
case ARM_SFT_ASR:
return "asr";
case ARM_SFT_LSL:
return "lsl";
case ARM_SFT_LSR:
return "lsr";
case ARM_SFT_ROR:
return "ror";
case ARM_SFT_RRX:
return "rrx";
case ARM_SFT_ASR_REG:
return "asr_reg";
case ARM_SFT_LSL_REG:
return "lsl_reg";
case ARM_SFT_LSR_REG:
return "lsr_reg";
case ARM_SFT_ROR_REG:
return "ror_reg";
case ARM_SFT_RRX_REG:
return "rrx_reg";
default:
return "";
}
}
static const char *vector_data_type_name(arm_vectordata_type type) {
switch (type) {
case ARM_VECTORDATA_I8:
return "i8";
case ARM_VECTORDATA_I16:
return "i16";
case ARM_VECTORDATA_I32:
return "i32";
case ARM_VECTORDATA_I64:
return "i64";
case ARM_VECTORDATA_S8:
return "s8";
case ARM_VECTORDATA_S16:
return "s16";
case ARM_VECTORDATA_S32:
return "s32";
case ARM_VECTORDATA_S64:
return "s64";
case ARM_VECTORDATA_U8:
return "u8";
case ARM_VECTORDATA_U16:
return "u16";
case ARM_VECTORDATA_U32:
return "u32";
case ARM_VECTORDATA_U64:
return "u64";
case ARM_VECTORDATA_P8:
return "p8";
case ARM_VECTORDATA_F32:
return "f32";
case ARM_VECTORDATA_F64:
return "f64";
case ARM_VECTORDATA_F16F64:
return "f16.f64";
case ARM_VECTORDATA_F64F16:
return "f64.f16";
case ARM_VECTORDATA_F32F16:
return "f32.f16";
case ARM_VECTORDATA_F16F32:
return "f16.f32";
case ARM_VECTORDATA_F64F32:
return "f64.f32";
case ARM_VECTORDATA_F32F64:
return "f32.f64";
case ARM_VECTORDATA_S32F32:
return "s32.f32";
case ARM_VECTORDATA_U32F32:
return "u32.f32";
case ARM_VECTORDATA_F32S32:
return "f32.s32";
case ARM_VECTORDATA_F32U32:
return "f32.u32";
case ARM_VECTORDATA_F64S16:
return "f64.s16";
case ARM_VECTORDATA_F32S16:
return "f32.s16";
case ARM_VECTORDATA_F64S32:
return "f64.s32";
case ARM_VECTORDATA_S16F64:
return "s16.f64";
case ARM_VECTORDATA_S16F32:
return "s16.f64";
case ARM_VECTORDATA_S32F64:
return "s32.f64";
case ARM_VECTORDATA_U16F64:
return "u16.f64";
case ARM_VECTORDATA_U16F32:
return "u16.f32";
case ARM_VECTORDATA_U32F64:
return "u32.f64";
case ARM_VECTORDATA_F64U16:
return "f64.u16";
case ARM_VECTORDATA_F32U16:
return "f32.u16";
case ARM_VECTORDATA_F64U32:
return "f64.u32";
default:
return "";
}
}
static const char *cc_name(arm_cc cc) {
switch (cc) {
case ARM_CC_EQ: // Equal Equal
return "eq";
case ARM_CC_NE: // Not equal Not equal, or unordered
return "ne";
case ARM_CC_HS: // Carry set >, ==, or unordered
return "hs";
case ARM_CC_LO: // Carry clear Less than
return "lo";
case ARM_CC_MI: // Minus, negative Less than
return "mi";
case ARM_CC_PL: // Plus, positive or zero >, ==, or unordered
return "pl";
case ARM_CC_VS: // Overflow Unordered
return "vs";
case ARM_CC_VC: // No overflow Not unordered
return "vc";
case ARM_CC_HI: // Unsigned higher Greater than, or unordered
return "hi";
case ARM_CC_LS: // Unsigned lower or same Less than or equal
return "ls";
case ARM_CC_GE: // Greater than or equal Greater than or equal
return "ge";
case ARM_CC_LT: // Less than Less than, or unordered
return "lt";
case ARM_CC_GT: // Greater than Greater than
return "gt";
case ARM_CC_LE: // Less than or equal <, ==, or unordered
return "le";
default:
return "";
}
}
static void opex(RStrBuf *buf, csh handle, cs_insn *insn) {
int i;
PJ *pj = pj_new ();
if (!pj) {
return;
}
pj_o (pj);
pj_ka (pj, "operands");
cs_arm *x = &insn->detail->arm;
for (i = 0; i < x->op_count; i++) {
cs_arm_op *op = x->operands + i;
pj_o (pj);
switch (op->type) {
case ARM_OP_REG:
pj_ks (pj, "type", "reg");
pj_ks (pj, "value", cs_reg_name (handle, op->reg));
break;
case ARM_OP_IMM:
pj_ks (pj, "type", "imm");
pj_ki (pj, "value", op->imm);
break;
case ARM_OP_MEM:
pj_ks (pj, "type", "mem");
if (op->mem.base != ARM_REG_INVALID) {
pj_ks (pj, "base", cs_reg_name (handle, op->mem.base));
}
if (op->mem.index != ARM_REG_INVALID) {
pj_ks (pj, "index", cs_reg_name (handle, op->mem.index));
}
pj_ki (pj, "scale", op->mem.scale);
pj_ki (pj, "disp", op->mem.disp);
break;
case ARM_OP_FP:
pj_ks (pj, "type", "fp");
pj_kd (pj, "value", op->fp);
break;
case ARM_OP_CIMM:
pj_ks (pj, "type", "cimm");
pj_ki (pj, "value", op->imm);
break;
case ARM_OP_PIMM:
pj_ks (pj, "type", "pimm");
pj_ki (pj, "value", op->imm);
break;
case ARM_OP_SETEND:
pj_ks (pj, "type", "setend");
switch (op->setend) {
case ARM_SETEND_BE:
pj_ks (pj, "value", "be");
break;
case ARM_SETEND_LE:
pj_ks (pj, "value", "le");
break;
default:
pj_ks (pj, "value", "invalid");
break;
}
break;
case ARM_OP_SYSREG:
pj_ks (pj, "type", "sysreg");
pj_ks (pj, "value", r_str_get_fail (cs_reg_name (handle, op->reg), ""));
break;
default:
pj_ks (pj, "type", "invalid");
break;
}
if (op->shift.type != ARM_SFT_INVALID) {
pj_ko (pj, "shift");
switch (op->shift.type) {
case ARM_SFT_ASR:
case ARM_SFT_LSL:
case ARM_SFT_LSR:
case ARM_SFT_ROR:
case ARM_SFT_RRX:
pj_ks (pj, "type", shift_type_name (op->shift.type));
pj_kn (pj, "value", (ut64)op->shift.value);
break;
case ARM_SFT_ASR_REG:
case ARM_SFT_LSL_REG:
case ARM_SFT_LSR_REG:
case ARM_SFT_ROR_REG:
case ARM_SFT_RRX_REG:
pj_ks (pj, "type", shift_type_name (op->shift.type));
pj_ks (pj, "value", cs_reg_name (handle, op->shift.value));
break;
default:
break;
}
pj_end (pj); /* o shift */
}
if (op->vector_index != -1) {
pj_ki (pj, "vector_index", op->vector_index);
}
if (op->subtracted) {
pj_kb (pj, "subtracted", true);
}
pj_end (pj); /* o operand */
}
pj_end (pj); /* a operands */
if (x->usermode) {
pj_kb (pj, "usermode", true);
}
if (x->update_flags) {
pj_kb (pj, "update_flags", true);
}
if (x->writeback) {
pj_kb (pj, "writeback", true);
}
if (x->vector_size) {
pj_ki (pj, "vector_size", x->vector_size);
}
if (x->vector_data != ARM_VECTORDATA_INVALID) {
pj_ks (pj, "vector_data", vector_data_type_name (x->vector_data));
}
if (x->cps_mode != ARM_CPSMODE_INVALID) {
pj_ki (pj, "cps_mode", x->cps_mode);
}
if (x->cps_flag != ARM_CPSFLAG_INVALID) {
pj_ki (pj, "cps_flag", x->cps_flag);
}
if (x->cc != ARM_CC_INVALID && x->cc != ARM_CC_AL) {
pj_ks (pj, "cc", cc_name (x->cc));
}
if (x->mem_barrier != ARM_MB_INVALID) {
pj_ki (pj, "mem_barrier", x->mem_barrier - 1);
}
pj_end (pj);
r_strbuf_init (buf);
r_strbuf_append (buf, pj_string (pj));
pj_free (pj);
}
static int arm64_reg_width(int reg) {
switch (reg) {
case ARM64_REG_W0:
case ARM64_REG_W1:
case ARM64_REG_W2:
case ARM64_REG_W3:
case ARM64_REG_W4:
case ARM64_REG_W5:
case ARM64_REG_W6:
case ARM64_REG_W7:
case ARM64_REG_W8:
case ARM64_REG_W9:
case ARM64_REG_W10:
case ARM64_REG_W11:
case ARM64_REG_W12:
case ARM64_REG_W13:
case ARM64_REG_W14:
case ARM64_REG_W15:
case ARM64_REG_W16:
case ARM64_REG_W17:
case ARM64_REG_W18:
case ARM64_REG_W19:
case ARM64_REG_W20:
case ARM64_REG_W21:
case ARM64_REG_W22:
case ARM64_REG_W23:
case ARM64_REG_W24:
case ARM64_REG_W25:
case ARM64_REG_W26:
case ARM64_REG_W27:
case ARM64_REG_W28:
case ARM64_REG_W29:
case ARM64_REG_W30:
case ARM64_REG_S0:
case ARM64_REG_S1:
case ARM64_REG_S2:
case ARM64_REG_S3:
case ARM64_REG_S4:
case ARM64_REG_S5:
case ARM64_REG_S6:
case ARM64_REG_S7:
case ARM64_REG_S8:
case ARM64_REG_S9:
case ARM64_REG_S10:
case ARM64_REG_S11:
case ARM64_REG_S12:
case ARM64_REG_S13:
case ARM64_REG_S14:
case ARM64_REG_S15:
case ARM64_REG_S16:
case ARM64_REG_S17:
case ARM64_REG_S18:
case ARM64_REG_S19:
case ARM64_REG_S20:
case ARM64_REG_S21:
case ARM64_REG_S22:
case ARM64_REG_S23:
case ARM64_REG_S24:
case ARM64_REG_S25:
case ARM64_REG_S26:
case ARM64_REG_S27:
case ARM64_REG_S28:
case ARM64_REG_S29:
case ARM64_REG_S30:
case ARM64_REG_S31:
return 32;
break;
default:
break;
}
return 64;
}
static const char *cc_name64(arm64_cc cc) {
switch (cc) {
case ARM64_CC_EQ: // Equal
return "eq";
case ARM64_CC_NE: // Not equal: Not equal, or unordered
return "ne";
case ARM64_CC_HS: // Unsigned higher or same: >, ==, or unordered
return "hs";
case ARM64_CC_LO: // Unsigned lower or same: Less than
return "lo";
case ARM64_CC_MI: // Minus, negative: Less than
return "mi";
case ARM64_CC_PL: // Plus, positive or zero: >, ==, or unordered
return "pl";
case ARM64_CC_VS: // Overflow: Unordered
return "vs";
case ARM64_CC_VC: // No overflow: Ordered
return "vc";
case ARM64_CC_HI: // Unsigned higher: Greater than, or unordered
return "hi";
case ARM64_CC_LS: // Unsigned lower or same: Less than or equal
return "ls";
case ARM64_CC_GE: // Greater than or equal: Greater than or equal
return "ge";
case ARM64_CC_LT: // Less than: Less than, or unordered
return "lt";
case ARM64_CC_GT: // Signed greater than: Greater than
return "gt";
case ARM64_CC_LE: // Signed less than or equal: <, ==, or unordered
return "le";
default:
return "";
}
}
static const char *extender_name(arm64_extender extender) {
switch (extender) {
case ARM64_EXT_UXTB:
return "uxtb";
case ARM64_EXT_UXTH:
return "uxth";
case ARM64_EXT_UXTW:
return "uxtw";
case ARM64_EXT_UXTX:
return "uxtx";
case ARM64_EXT_SXTB:
return "sxtb";
case ARM64_EXT_SXTH:
return "sxth";
case ARM64_EXT_SXTW:
return "sxtw";
case ARM64_EXT_SXTX:
return "sxtx";
default:
return "";
}
}
static const char *vas_name(arm64_vas vas) {
switch (vas) {
case ARM64_VAS_8B:
return "8b";
case ARM64_VAS_16B:
return "16b";
case ARM64_VAS_4H:
return "4h";
case ARM64_VAS_8H:
return "8h";
case ARM64_VAS_2S:
return "2s";
case ARM64_VAS_4S:
return "4s";
case ARM64_VAS_2D:
return "2d";
case ARM64_VAS_1D:
return "1d";
case ARM64_VAS_1Q:
return "1q";
#if CS_API_MAJOR > 4
case ARM64_VAS_1B:
return "8b";
case ARM64_VAS_4B:
return "8b";
case ARM64_VAS_2H:
return "2h";
case ARM64_VAS_1H:
return "1h";
case ARM64_VAS_1S:
return "1s";
#endif
default:
return "";
}
}
static int vas_size(arm64_vas vas) {
switch (vas) {
case ARM64_VAS_8B:
case ARM64_VAS_16B:
return 8;
case ARM64_VAS_4H:
case ARM64_VAS_8H:
return 16;
case ARM64_VAS_2S:
case ARM64_VAS_4S:
return 32;
case ARM64_VAS_2D:
case ARM64_VAS_1D:
return 64;
case ARM64_VAS_1Q:
return 128;
#if CS_API_MAJOR > 4
case ARM64_VAS_1B:
case ARM64_VAS_4B:
return 8;
case ARM64_VAS_2H:
case ARM64_VAS_1H:
return 16;
case ARM64_VAS_1S:
return 32;
#endif
default:
return 64;
}
}
static int vas_count(arm64_vas vas) {
switch (vas) {
case ARM64_VAS_16B:
return 16;
case ARM64_VAS_8B:
case ARM64_VAS_8H:
return 8;
case ARM64_VAS_4S:
case ARM64_VAS_4H:
return 4;
case ARM64_VAS_2D:
case ARM64_VAS_2S:
return 2;
case ARM64_VAS_1D:
case ARM64_VAS_1Q:
return 1;
#if CS_API_MAJOR > 4
case ARM64_VAS_4B:
return 4;
case ARM64_VAS_2H:
return 2;
case ARM64_VAS_1B:
case ARM64_VAS_1H:
case ARM64_VAS_1S:
return 1;
#endif
default:
return 64;
}
}
#if CS_API_MAJOR == 4
static const char *vess_name(arm64_vess vess) {
switch (vess) {
case ARM64_VESS_B:
return "b";
case ARM64_VESS_H:
return "h";
case ARM64_VESS_S:
return "s";
case ARM64_VESS_D:
return "d";
default:
return "";
}
}
#endif
#if CS_API_MAJOR == 4
static int vess_size(arm64_vess vess) {
switch (vess) {
case ARM64_VESS_B:
return 8;
case ARM64_VESS_H:
return 16;
case ARM64_VESS_S:
return 32;
case ARM64_VESS_D:
return 64;
default:
return 64;
}
}
#endif
static void opex64(RStrBuf *buf, csh handle, cs_insn *insn) {
int i;
PJ *pj = pj_new ();
if (!pj) {
return;
}
pj_o (pj);
pj_ka (pj, "operands");
cs_arm64 *x = &insn->detail->arm64;
for (i = 0; i < x->op_count; i++) {
cs_arm64_op *op = x->operands + i;
pj_o (pj);
switch (op->type) {
case ARM64_OP_REG:
{
pj_ks (pj, "type", "reg");
const char *rn = cs_reg_name (handle, op->reg);
if (rn) {
pj_ks (pj, "value", rn);
}
}
break;
case ARM64_OP_REG_MRS:
pj_ks (pj, "type", "reg_mrs");
// TODO value
break;
case ARM64_OP_REG_MSR:
pj_ks (pj, "type", "reg_msr");
// TODO value
break;
case ARM64_OP_IMM:
pj_ks (pj, "type", "imm");
pj_kN (pj, "value", op->imm);
break;
case ARM64_OP_MEM:
pj_ks (pj, "type", "mem");
if (op->mem.base != ARM64_REG_INVALID) {
pj_ks (pj, "base", cs_reg_name (handle, op->mem.base));
}
if (op->mem.index != ARM64_REG_INVALID) {
pj_ks (pj, "index", cs_reg_name (handle, op->mem.index));
}
pj_ki (pj, "disp", op->mem.disp);
break;
case ARM64_OP_FP:
pj_ks (pj, "type", "fp");
pj_kd (pj, "value", op->fp);
break;
case ARM64_OP_CIMM:
pj_ks (pj, "type", "cimm");
pj_kN (pj, "value", op->imm);
break;
case ARM64_OP_PSTATE:
pj_ks (pj, "type", "pstate");
switch (op->pstate) {
case ARM64_PSTATE_SPSEL:
pj_ks (pj, "value", "spsel");
break;
case ARM64_PSTATE_DAIFSET:
pj_ks (pj, "value", "daifset");
break;
case ARM64_PSTATE_DAIFCLR:
pj_ks (pj, "value", "daifclr");
break;
default:
pj_ki (pj, "value", op->pstate);
}
break;
case ARM64_OP_SYS:
pj_ks (pj, "type", "sys");
pj_kn (pj, "value", (ut64)op->sys);
break;
case ARM64_OP_PREFETCH:
pj_ks (pj, "type", "prefetch");
pj_ki (pj, "value", op->prefetch - 1);
break;
case ARM64_OP_BARRIER:
pj_ks (pj, "type", "prefetch");
pj_ki (pj, "value", op->barrier - 1);
break;
default:
pj_ks (pj, "type", "invalid");
break;
}
if (op->shift.type != ARM64_SFT_INVALID) {
pj_ko (pj, "shift");
switch (op->shift.type) {
case ARM64_SFT_LSL:
pj_ks (pj, "type", "lsl");
break;
case ARM64_SFT_MSL:
pj_ks (pj, "type", "msl");
break;
case ARM64_SFT_LSR:
pj_ks (pj, "type", "lsr");
break;
case ARM64_SFT_ASR:
pj_ks (pj, "type", "asr");
break;
case ARM64_SFT_ROR:
pj_ks (pj, "type", "ror");
break;
default:
break;
}
pj_kn (pj, "value", (ut64)op->shift.value);
pj_end (pj);
}
if (op->ext != ARM64_EXT_INVALID) {
pj_ks (pj, "ext", extender_name (op->ext));
}
if (op->vector_index != -1) {
pj_ki (pj, "vector_index", op->vector_index);
}
if (op->vas != ARM64_VAS_INVALID) {
pj_ks (pj, "vas", vas_name (op->vas));
}
#if CS_API_MAJOR == 4
if (op->vess != ARM64_VESS_INVALID) {
pj_ks (pj, "vess", vess_name (op->vess));
}
#endif
pj_end (pj);
}
pj_end (pj);
if (x->update_flags) {
pj_kb (pj, "update_flags", true);
}
if (x->writeback) {
pj_kb (pj, "writeback", true);
}
if (x->cc != ARM64_CC_INVALID && x->cc != ARM64_CC_AL && x->cc != ARM64_CC_NV) {
pj_ks (pj, "cc", cc_name64 (x->cc));
}
pj_end (pj);
r_strbuf_init (buf);
r_strbuf_append (buf, pj_string (pj));
pj_free (pj);
}
static int decode_sign_ext(arm64_extender extender) {
switch (extender) {
case ARM64_EXT_UXTB:
case ARM64_EXT_UXTH:
case ARM64_EXT_UXTW:
case ARM64_EXT_UXTX:
return 0; // nothing needs to be done for unsigned
case ARM64_EXT_SXTB:
return 8;
case ARM64_EXT_SXTH:
return 16;
case ARM64_EXT_SXTW:
return 32;
case ARM64_EXT_SXTX:
return 64;
default:
break;
}
return 0;
}
static const char *E_OP_SR = ">>";
static const char *E_OP_SL = "<<";
static const char *E_OP_RR = ">>>";
static const char *E_OP_ASR = ">>>>";
static const char *E_OP_AR = ">>>>";
static const char *E_OP_VOID = "";
static const char *decode_shift(arm_shifter shift) {
switch (shift) {
case ARM_SFT_ASR:
case ARM_SFT_ASR_REG:
return E_OP_ASR;
case ARM_SFT_LSR:
case ARM_SFT_LSR_REG:
return E_OP_SR;
case ARM_SFT_LSL:
case ARM_SFT_LSL_REG:
return E_OP_SL;
case ARM_SFT_ROR:
case ARM_SFT_RRX:
case ARM_SFT_ROR_REG:
case ARM_SFT_RRX_REG:
return E_OP_RR;
default:
break;
}
return E_OP_VOID;
}
static const char *decode_shift_64(arm64_shifter shift) {
switch (shift) {
case ARM64_SFT_ASR:
return E_OP_AR;
case ARM64_SFT_LSR:
return E_OP_SR;
case ARM64_SFT_LSL:
case ARM64_SFT_MSL:
return E_OP_SL;
case ARM64_SFT_ROR:
return E_OP_RR;
default:
break;
}
return E_OP_VOID;
}
#define DECODE_SHIFT(x) decode_shift(insn->detail->arm.operands[x].shift.type)
#define DECODE_SHIFT64(x) decode_shift_64(insn->detail->arm64.operands[x].shift.type)
static unsigned int regsize32(cs_insn *insn, int n) {
r_return_val_if_fail(n >= 0 && n < insn->detail->arm.op_count, 0);
unsigned int reg = insn->detail->arm.operands[n].reg;
if (reg >= ARM_REG_D0 && reg <= ARM_REG_D31) {
return 8;
}
if (reg >= ARM_REG_Q0 && reg <= ARM_REG_Q15) {
return 16;
}
return 4; // s0-s31, r0-r15
}
static int regsize64(cs_insn *insn, int n) {
unsigned int reg = insn->detail->arm64.operands[n].reg;
if ((reg >= ARM64_REG_S0 && reg <= ARM64_REG_S31) ||
(reg >= ARM64_REG_W0 && reg <= ARM64_REG_W30) ||
reg == ARM64_REG_WZR) {
return 4;
}
if (reg >= ARM64_REG_B0 && reg <= ARM64_REG_B31) {
return 1;
}
if (reg >= ARM64_REG_H0 && reg <= ARM64_REG_H31) {
return 2;
}
if ((reg >= ARM64_REG_Q0 && reg <= ARM64_REG_Q31) ||
(reg >= ARM64_REG_V0 && reg <= ARM64_REG_V31) ) {
return 16;
}
return 8;
}
#define REGSIZE64(x) regsize64 (insn, x)
#define REGSIZE32(x) regsize32 (insn, x)
#define REGBITS64(x) (8 * regsize64 (insn, x))
#define REGBITS32(x) (8 * regsize32 (insn, x))
#define SET_FLAGS() r_strbuf_appendf (&op->esil, ",$z,zf,:=,%d,$s,nf,:=,%d,$c,cf,:=,%d,$o,vf,:=", REGBITS64 (0) - 1, REGBITS64 (0), REGBITS64 (0) -1);
static int vector_size(cs_arm64_op *op) {
#if CS_API_MAJOR == 4
if (op->vess) {
return vess_size (op->vess);
}
#endif
if (op->vas) {
return vas_size (op->vas);
}
return 64;
}
// return postfix
const char* arm_prefix_cond(RAnalOp *op, int cond_type) {
const char *close_cond[2];
close_cond[0] = "\0";
close_cond[1] = ",}\0";
int close_type = 0;
switch (cond_type) {
case ARM_CC_EQ:
close_type = 1;
r_strbuf_append (&op->esil, "zf,?{,");
break;
case ARM_CC_NE:
close_type = 1;
r_strbuf_append (&op->esil, "zf,!,?{,");
break;
case ARM_CC_HS:
close_type = 1;
r_strbuf_append (&op->esil, "cf,?{,");
break;
case ARM_CC_LO:
close_type = 1;
r_strbuf_append (&op->esil, "cf,!,?{,");
break;
case ARM_CC_MI:
close_type = 1;
r_strbuf_append (&op->esil, "nf,?{,");
break;
case ARM_CC_PL:
close_type = 1;
r_strbuf_append (&op->esil, "nf,!,?{,");
break;
case ARM_CC_VS:
close_type = 1;
r_strbuf_append (&op->esil, "vf,?{,");
break;
case ARM_CC_VC:
close_type = 1;
r_strbuf_append (&op->esil, "vf,!,?{,");
break;
case ARM_CC_HI:
close_type = 1;
r_strbuf_append (&op->esil, "cf,zf,!,&,?{,");
break;
case ARM_CC_LS:
close_type = 1;
r_strbuf_append (&op->esil, "cf,!,zf,|,?{,");
break;
case ARM_CC_GE:
close_type = 1;
r_strbuf_append (&op->esil, "nf,vf,^,!,?{,");
break;
case ARM_CC_LT:
close_type = 1;
r_strbuf_append (&op->esil, "nf,vf,^,?{,");
break;
case ARM_CC_GT:
// zf == 0 && nf == vf
close_type = 1;
r_strbuf_append (&op->esil, "zf,!,nf,vf,^,!,&,?{,");
break;
case ARM_CC_LE:
// zf == 1 || nf != vf
close_type = 1;
r_strbuf_append (&op->esil, "zf,nf,vf,^,|,?{,");
break;
case ARM_CC_AL:
// always executed
break;
default:
break;
}
return close_cond[close_type];
}
/* arm64 */
static const char *arg(RArchSession *as, csh *handle, cs_insn *insn, char *buf, size_t buf_sz, int n) {
buf[0] = 0;
switch (insn->detail->arm.operands[n].type) {
case ARM_OP_REG:
if (ISSHIFTED (n)) {
if (SHIFTTYPEREG (n)) {
snprintf (buf, buf_sz, "%s,%s,%s",
cs_reg_name(*handle, LSHIFT2(n)),