Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Support separate flash erase and write page sizes #452

Closed
flit opened this issue Nov 15, 2018 · 3 comments
Closed

Support separate flash erase and write page sizes #452

flit opened this issue Nov 15, 2018 · 3 comments
Assignees
Milestone

Comments

@flit
Copy link
Member

flit commented Nov 15, 2018

Some flash memories, such as QSPI, have different erase and write block sizes, with the erase block size being larger than the write block size. Most MCU internal flash controllers allow programming granularity of somewhere between 1 and 16 bytes (depends on flash technology and controller IP). But some flash technologies, particularly smaller geometries and external flash memories, have much larger minimum write sizes such as 512 bytes. Current flash algos have always handled this by simply accepting multiple blocks to write in the ProgramPage() API, which fit well with the 1-16 byte write granularity. However, not all flash algos work this way..

In addition, some targets, notably some STM32 devices, have crazy large erase sector sizes (up to 128 kB!). This can prevent double buffering from being enabled since there is not enough RAM to fit two of these sectors. The solution is to support a flash write page size that is smaller than the sector size. The main constraint is that you want to have as large programming buffers as possible to reduce buffer swap and command issuing latency.

@flit flit added the to do label Nov 15, 2018
@flit flit changed the title Support flash write page sizes smaller than the sector size Support separate flash erase and write page sizes Jan 5, 2019
@flit flit added the bug label Jan 10, 2019
@flit flit added this to the v1.0 milestone Mar 7, 2019
@flit flit removed the bug label Mar 13, 2019
@stppgit
Copy link

stppgit commented Mar 28, 2019

This also impacts external memory programming using QSPI interface in Cypress PSoC 6 devices.
S25FL512S memory, for example, has erase page == 256K, what requires 256K of PSoC 6 SRAM to be allocated as the data buffer. Algorithms data + stack also requires up to 32Kbytes of SRAM.

This tightly works for PSoC6A-BLE2 devices with 288 Kbytes of SRAM but does not work for PSoC6 devices with SRAM size < 288KBytes and for secure devices where SRAM access is limited to specific regions.
In addition, we cannot use double-buffering to speed-up programming, what is critical for large QSPI memory devices such as S25FL512S (64M).

@flit
Copy link
Member Author

flit commented Mar 28, 2019

Exactly right. Please see my feature/flash_erase_program_size branch. It's mostly done, except that the flash_test.py functional test fails. This is most likely due to assumptions the test makes that are no longer valid, rather than real bugs, but of course it must be fixed before the branch can be merged.

@flit flit added in progress and removed to do labels Mar 28, 2019
@stppgit
Copy link

stppgit commented Mar 28, 2019 via email

@flit flit self-assigned this Apr 1, 2019
@flit flit closed this as completed in #602 Apr 2, 2019
@flit flit removed the in progress label Apr 2, 2019
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

2 participants