From b094823a44aa76638785867ae978f7c333ec6957 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 7 Jan 2021 11:37:20 -0600 Subject: [PATCH] platform: move interrupt configuration Technically speaking, the SysTick interrupt is enabled when clocks are configured so configuration related to interrupts should happen before then. --- lib/pbio/platform/city_hub/platform.c | 24 ++++++++++++------------ lib/pbio/platform/debug/platform.c | 18 +++++++++--------- lib/pbio/platform/move_hub/platform.c | 24 ++++++++++++------------ lib/pbio/platform/prime_hub/platform.c | 21 +++++++++------------ lib/pbio/platform/technic_hub/platform.c | 20 +++++++++----------- 5 files changed, 51 insertions(+), 56 deletions(-) diff --git a/lib/pbio/platform/city_hub/platform.c b/lib/pbio/platform/city_hub/platform.c index eeabf2198..f863d11df 100644 --- a/lib/pbio/platform/city_hub/platform.c +++ b/lib/pbio/platform/city_hub/platform.c @@ -200,15 +200,23 @@ extern uint32_t _fw_isr_vector_dst[48]; // this function is a mash up of ports/stm32/system_stm32f0.c from MicroPython // and the official LEGO firmware void SystemInit(void) { + // since the firmware starts at 0x08005000, we need to relocate the + // interrupt vector table to a place where the CPU knows about it. + // The space at the start of SRAM is reserved in via the linker script. + memcpy(_fw_isr_vector_dst, _fw_isr_vector_src, sizeof(_fw_isr_vector_dst)); + + // this maps SRAM to 0x00000000 + SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE_Msk) | (3 << SYSCFG_CFGR1_MEM_MODE_Pos); + + // enable 8-byte stack alignment for IRQ handlers, in accord with EABI + SCB->CCR |= SCB_CCR_STKALIGN_Msk; + // normally, the system clock would be setup here, but it is already // configured by the bootloader, so no need to do it again. // SysTick set for 1ms ticks SysTick_Config(PBDRV_CONFIG_SYS_CLOCK_RATE / 1000); - // enable 8-byte stack alignment for IRQ handlers, in accord with EABI - SCB->CCR |= SCB_CCR_STKALIGN_Msk; - // Enable all of the hardware modules we are using RCC->AHBENR |= RCC_AHBENR_DMAEN | RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | RCC_AHBENR_GPIOFEN; @@ -224,7 +232,7 @@ void SystemInit(void) { GPIOB->MODER = (GPIOB->MODER & ~GPIO_MODER_MODER2_Msk) | (1 << GPIO_MODER_MODER2_Pos); GPIOB->BSRR = GPIO_BSRR_BS_2; - // not sure what the rest of these pins do + // Unused pins // PA5 output, low GPIOA->MODER = (GPIOA->MODER & ~GPIO_MODER_MODER5_Msk) | (1 << GPIO_MODER_MODER5_Pos); @@ -265,12 +273,4 @@ void SystemInit(void) { // PF1 output, low GPIOF->MODER = (GPIOF->MODER & ~GPIO_MODER_MODER1_Msk) | (1 << GPIO_MODER_MODER1_Pos); GPIOF->BSRR = GPIO_BSRR_BR_1; - - // since the firmware starts at 0x08005000, we need to relocate the - // interrupt vector table to a place where the CPU knows about it. - // The space at the start of SRAM is reserved in via the linker script. - memcpy(_fw_isr_vector_dst, _fw_isr_vector_src, sizeof(_fw_isr_vector_dst)); - - // this maps SRAM to 0x00000000 - SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE_Msk) | (3 << SYSCFG_CFGR1_MEM_MODE_Pos); } diff --git a/lib/pbio/platform/debug/platform.c b/lib/pbio/platform/debug/platform.c index ae3a1e476..3c2a9b3ff 100644 --- a/lib/pbio/platform/debug/platform.c +++ b/lib/pbio/platform/debug/platform.c @@ -265,10 +265,16 @@ const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; void SystemInit(void) { - RCC_OscInitTypeDef osc_init; - RCC_ClkInitTypeDef clk_init; + + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ + #endif + + // enable 8-byte stack alignment for IRQ handlers, in accord with EABI + SCB->CCR |= SCB_CCR_STKALIGN_Msk; // Using internal 16Mhz oscillator + RCC_OscInitTypeDef osc_init; osc_init.OscillatorType = RCC_OSCILLATORTYPE_HSE; osc_init.HSEState = RCC_HSE_ON; osc_init.HSIState = RCC_HSI_OFF; @@ -281,6 +287,7 @@ void SystemInit(void) { HAL_RCC_OscConfig(&osc_init); + RCC_ClkInitTypeDef clk_init; clk_init.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; clk_init.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; clk_init.AHBCLKDivider = RCC_SYSCLK_DIV1; // HCLK 48MHz (max 180MHz) @@ -289,13 +296,6 @@ void SystemInit(void) { HAL_RCC_ClockConfig(&clk_init, FLASH_LATENCY_5); - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ - #endif - - // enable 8-byte stack alignment for IRQ handlers, in accord with EABI - SCB->CCR |= SCB_CCR_STKALIGN_Msk; - // enable all of the hardware modules we are using RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | diff --git a/lib/pbio/platform/move_hub/platform.c b/lib/pbio/platform/move_hub/platform.c index 698fdebcc..6ddf6de8e 100644 --- a/lib/pbio/platform/move_hub/platform.c +++ b/lib/pbio/platform/move_hub/platform.c @@ -252,15 +252,23 @@ extern uint32_t _fw_isr_vector_dst[48]; // this function is a mash up of ports/stm32/system_stm32f0.c from MicroPython // and the official LEGO firmware void SystemInit(void) { + // since the firmware starts at 0x08005000, we need to relocate the + // interrupt vector table to a place where the CPU knows about it. + // The space at the start of SRAM is reserved in via the linker script. + memcpy(_fw_isr_vector_dst, _fw_isr_vector_src, sizeof(_fw_isr_vector_dst)); + + // this maps SRAM to 0x00000000 + SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE_Msk) | (3 << SYSCFG_CFGR1_MEM_MODE_Pos); + + // enable 8-byte stack alignment for IRQ handlers, in accord with EABI + SCB->CCR |= SCB_CCR_STKALIGN_Msk; + // normally, the system clock would be setup here, but it is already // configured by the bootloader, so no need to do it again. // SysTick set for 1ms ticks SysTick_Config(PBDRV_CONFIG_SYS_CLOCK_RATE / 1000); - // enable 8-byte stack alignment for IRQ handlers, in accord with EABI - SCB->CCR |= SCB_CCR_STKALIGN_Msk; - // Enable all of the hardware modules we are using RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | RCC_AHBENR_GPIOFEN; @@ -276,7 +284,7 @@ void SystemInit(void) { GPIOB->BSRR = GPIO_BSRR_BS_2; GPIOB->MODER = (GPIOB->MODER & ~GPIO_MODER_MODER2_Msk) | (1 << GPIO_MODER_MODER2_Pos); - // not sure what the rest of these pins do + // Unused pins // PF0 output, high GPIOF->BSRR = GPIO_BSRR_BS_0; @@ -301,12 +309,4 @@ void SystemInit(void) { // PF1 output, high GPIOF->BSRR = GPIO_BSRR_BS_1; GPIOF->MODER = (GPIOF->MODER & ~GPIO_MODER_MODER1_Msk) | (1 << GPIO_MODER_MODER1_Pos); - - // since the firmware starts at 0x08005000, we need to relocate the - // interrupt vector table to a place where the CPU knows about it. - // The space at the start of SRAM is reserved in via the linker script. - memcpy(_fw_isr_vector_dst, _fw_isr_vector_src, sizeof(_fw_isr_vector_dst)); - - // this maps SRAM to 0x00000000 - SYSCFG->CFGR1 = (SYSCFG->CFGR1 & ~SYSCFG_CFGR1_MEM_MODE_Msk) | (3 << SYSCFG_CFGR1_MEM_MODE_Pos); } diff --git a/lib/pbio/platform/prime_hub/platform.c b/lib/pbio/platform/prime_hub/platform.c index 4cc3c9a62..fa48c482b 100644 --- a/lib/pbio/platform/prime_hub/platform.c +++ b/lib/pbio/platform/prime_hub/platform.c @@ -696,14 +696,19 @@ extern uint32_t *_fw_isr_vector_src; // Called from assembly code in startup.s void SystemInit(void) { + // enable 8-byte stack alignment for IRQ handlers, in accord with EABI + SCB->CCR |= SCB_CCR_STKALIGN_Msk; + + // since the firmware starts at 0x08008000, we need to set the vector table offset + SCB->VTOR = (uint32_t)&_fw_isr_vector_src; - RCC_OscInitTypeDef osc_init; - RCC_ClkInitTypeDef clk_init; + // bootloader disables interrupts + __enable_irq(); // Using external 16Mhz oscillator + RCC_OscInitTypeDef osc_init = { 0 }; osc_init.OscillatorType = RCC_OSCILLATORTYPE_HSE; osc_init.HSEState = RCC_HSE_ON; - osc_init.HSIState = RCC_HSI_OFF; osc_init.PLL.PLLState = RCC_PLL_ON; osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSE; osc_init.PLL.PLLM = 8; // VCO_IN 2MHz (16MHz / 8) @@ -713,6 +718,7 @@ void SystemInit(void) { HAL_RCC_OscConfig(&osc_init); + RCC_ClkInitTypeDef clk_init = { 0 }; clk_init.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; clk_init.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; clk_init.AHBCLKDivider = RCC_SYSCLK_DIV1; // HCLK 96MHz @@ -721,15 +727,6 @@ void SystemInit(void) { HAL_RCC_ClockConfig(&clk_init, FLASH_LATENCY_5); - // enable 8-byte stack alignment for IRQ handlers, in accord with EABI - SCB->CCR |= SCB_CCR_STKALIGN_Msk; - - // since the firmware starts at 0x08008000, we need to set the vector table offset - SCB->VTOR = (uint32_t)&_fw_isr_vector_src; - - // bootloader disables interrupts - __enable_irq(); - // If we are running dual boot, jump to other firmware if no buttons are pressed pbio_platform_dual_boot(); diff --git a/lib/pbio/platform/technic_hub/platform.c b/lib/pbio/platform/technic_hub/platform.c index 89ec9a7f7..a299328d8 100644 --- a/lib/pbio/platform/technic_hub/platform.c +++ b/lib/pbio/platform/technic_hub/platform.c @@ -449,15 +449,18 @@ extern uint32_t *_fw_isr_vector_src; // Called from assembly code in startup.s void SystemInit(void) { - RCC_OscInitTypeDef osc_init = { 0 }; - RCC_ClkInitTypeDef clk_init = { 0 }; - GPIO_InitTypeDef gpio_init = { 0 }; - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif + // enable 8-byte stack alignment for IRQ handlers, in accord with EABI + SCB->CCR |= SCB_CCR_STKALIGN_Msk; + + // since the firmware starts at 0x08008000, we need to set the vector table offset + SCB->VTOR = (uint32_t)&_fw_isr_vector_src; + // Using external 16Mhz oscillator + RCC_OscInitTypeDef osc_init = { 0 }; osc_init.OscillatorType = RCC_OSCILLATORTYPE_MSI; osc_init.MSIState = RCC_MSI_ON; osc_init.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; @@ -472,6 +475,7 @@ void SystemInit(void) { HAL_RCC_OscConfig(&osc_init); + RCC_ClkInitTypeDef clk_init = { 0 }; clk_init.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; clk_init.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; clk_init.AHBCLKDivider = RCC_SYSCLK_DIV1; // HCLK 80MHz @@ -481,9 +485,6 @@ void SystemInit(void) { HAL_RCC_ClockConfig(&clk_init, FLASH_LATENCY_4); - // enable 8-byte stack alignment for IRQ handlers, in accord with EABI - SCB->CCR |= SCB_CCR_STKALIGN_Msk; - // enable clocks RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN | RCC_AHB1ENR_DMA2EN | RCC_AHB1ENR_FLASHEN | RCC_AHB1ENR_CRCEN; @@ -495,8 +496,8 @@ void SystemInit(void) { RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_TIM1EN | RCC_APB2ENR_SPI1EN | RCC_APB2ENR_USART1EN | RCC_APB2ENR_TIM15EN | RCC_APB2ENR_TIM16EN; - // Keep main power on (PC12) + GPIO_InitTypeDef gpio_init = { 0 }; gpio_init.Pin = GPIO_PIN_12; gpio_init.Mode = GPIO_MODE_OUTPUT_PP; HAL_GPIO_WritePin(GPIOC, GPIO_PIN_12, GPIO_PIN_SET); @@ -505,7 +506,4 @@ void SystemInit(void) { // Turn VCC_PORT on (PB12) HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); HAL_GPIO_Init(GPIOB, &gpio_init); - - // since the firmware starts at 0x08008000, we need to set the vector table offset - SCB->VTOR = (uint32_t)&_fw_isr_vector_src; }