legacy_genus:/> read_hdl -sv "$RTL " Reading Verilog file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/fpga/pad_functional_xilinx.sv' (* PULLDOWN = "YES" *) | Warning : Unused attribute. [VLOGPT-506] : Attribute 'PULLDOWN' in file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/fpga/pad_functional_xilinx.sv' on line 21, column 6. (* PULLUP = "YES" *) | Warning : Unused attribute. [VLOGPT-506] : Attribute 'PULLUP' in file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/fpga/pad_functional_xilinx.sv' on line 40, column 6. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/fpga/tc_clk_xilinx.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/fpga/tc_sram_xilinx.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/deprecated/pulp_clock_gating_async.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/deprecated/cluster_clk_cells.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/deprecated/pulp_clk_cells.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/binary_to_gray.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cb_filter_pkg.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cc_onehot.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cf_math_pkg.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/clk_int_div.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/delta_counter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/ecc_pkg.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/edge_propagator_tx.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/exp_backoff.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/fifo_v3.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/gray_to_binary.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/isochronous_4phase_handshake.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/isochronous_spill_register.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/lfsr.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/lfsr_16bit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/lfsr_8bit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/mv_filter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/onehot_to_bin.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/plru_tree.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/popcount.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/rr_arb_tree.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/rstgen_bypass.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/serial_deglitch.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/shift_reg.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/spill_register_flushable.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/stream_demux.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/stream_filter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/stream_fork.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/stream_intf.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/stream_join.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/stream_mux.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/sub_per_hash.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/sync.sv' (* dont_touch = "true" *) | Warning : Unused attribute. [VLOGPT-506] : Attribute 'dont_touch' in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/sync.sv' on line 23, column 7. (* async_reg = "true" *) | Warning : Unused attribute. [VLOGPT-506] : Attribute 'async_reg' in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/sync.sv' on line 24, column 7. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/sync_wedge.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/unread.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_reset_ctrlr_pkg.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_2phase.sv' (* dont_touch = "true" *) logic async_req; | Warning : Unused attribute. [VLOGPT-506] : Attribute 'dont_touch' in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_2phase.sv' on line 60, column 6. (* dont_touch = "true" *) logic async_ack; | Warning : Unused attribute. [VLOGPT-506] : Attribute 'dont_touch' in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_2phase.sv' on line 61, column 6. (* dont_touch = "true" *) T async_data; | Warning : Unused attribute. [VLOGPT-506] : Attribute 'dont_touch' in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_2phase.sv' on line 62, column 6. (* dont_touch = "true" *) | Warning : Unused attribute. [VLOGPT-506] : Attribute 'dont_touch' in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_2phase.sv' on line 105, column 6. (* dont_touch = "true" *) | Warning : Unused attribute. [VLOGPT-506] : Attribute 'dont_touch' in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_2phase.sv' on line 107, column 6. (* dont_touch = "true" *) | Warning : Unused attribute. [VLOGPT-506] : Attribute 'dont_touch' in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_2phase.sv' on line 155, column 6. (* async_reg = "true" *) | Warning : Unused attribute. [VLOGPT-506] : Attribute 'async_reg' in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_2phase.sv' on line 156, column 6. (* dont_touch = "true" *) | Warning : Unused attribute. [VLOGPT-506] : Attribute 'dont_touch' in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_2phase.sv' on line 158, column 6. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_4phase.sv' (* dont_touch = "true" *) logic async_req; | Warning : Unused attribute. [VLOGPT-506] : Attribute 'dont_touch' in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_4phase.sv' on line 56, column 6. (* dont_touch = "true" *) logic async_ack; | Warning : Unused attribute. [VLOGPT-506] : Attribute 'dont_touch' in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_4phase.sv' on line 57, column 6. (* dont_touch = "true" *) T async_data; | Warning : Unused attribute. [VLOGPT-506] : Attribute 'dont_touch' in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_4phase.sv' on line 58, column 6. (* dont_touch = "true" *) | Warning : Unused attribute. [VLOGPT-506] : Attribute 'dont_touch' in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_4phase.sv' on line 109, column 6. (* dont_touch = "true" *) | Warning : Unused attribute. [VLOGPT-506] : Attribute 'dont_touch' in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_4phase.sv' on line 111, column 6. (* dont_touch = "true" *) | Warning : Unused attribute. [VLOGPT-506] : Attribute 'dont_touch' in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_4phase.sv' on line 113, column 6. (* dont_touch = "true" *) | Warning : Unused attribute. [VLOGPT-506] : Attribute 'dont_touch' in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_4phase.sv' on line 220, column 6. (* dont_touch = "true" *) | Warning : Unused attribute. [VLOGPT-506] : Attribute 'dont_touch' in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_4phase.sv' on line 222, column 6. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/addr_decode.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cb_filter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_2phase.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/counter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/ecc_decode.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/ecc_encode.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/edge_detect.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/lzc.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/max_counter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/rstgen.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/spill_register.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/stream_delay.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/stream_fifo.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/stream_fork_dynamic.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_reset_ctrlr.sv' Warning : Maximum message print count reached. [MESG-11] : Maximum print count of '20' reached for message 'VLOGPT-506'. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/fall_through_register.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/id_queue.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/stream_to_mem.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/stream_arbiter_flushable.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/stream_register.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/stream_xbar.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray_clearable.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_2phase_clearable.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/stream_arbiter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/stream_omega_net.sv' initial begin : proc_selw | Warning : Ignoring unsynthesizable construct. [VLOGPT-37] : Initial in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/stream_omega_net.sv' on line 142, column 11. : For example, the following constructs will be ignored: - initial block - final block - program block - property block - sequence block - covergroup - checker block - gate drive strength - system task enable - reg declaration with initial value - specify block. initial begin : proc_debug_print | Warning : Ignoring unsynthesizable construct. [VLOGPT-37] : Initial in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/stream_omega_net.sv' on line 252, column 11. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/deprecated/clock_divider_counter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/deprecated/find_first_one.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/deprecated/generic_LFSR_8bit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/deprecated/generic_fifo.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/deprecated/prioarbiter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/deprecated/pulp_sync.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/deprecated/pulp_sync_wedge.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/deprecated/rrarbiter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/deprecated/clock_divider.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/deprecated/fifo_v2.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/deprecated/fifo_v1.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/edge_propagator_ack.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/edge_propagator.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/edge_propagator_rx.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_div_sqrt_mvp-ad7a655d31deb2af/hdl/defs_div_sqrt_mvp.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_div_sqrt_mvp-ad7a655d31deb2af/hdl/iteration_div_sqrt_mvp.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_div_sqrt_mvp-ad7a655d31deb2af/hdl/control_mvp.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_div_sqrt_mvp-ad7a655d31deb2af/hdl/norm_div_sqrt_mvp.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_div_sqrt_mvp-ad7a655d31deb2af/hdl/preprocess_mvp.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_div_sqrt_mvp-ad7a655d31deb2af/hdl/nrbd_nrsc_mvp.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_div_sqrt_mvp-ad7a655d31deb2af/hdl/div_sqrt_top_mvp.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_div_sqrt_mvp-ad7a655d31deb2af/hdl/div_sqrt_mvp_wrapper.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/tcdm_interconnect/addr_dec_resp_mux.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/tcdm_interconnect/amo_shim.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/variable_latency_interconnect/addr_decoder.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/tcdm_interconnect/xbar.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/variable_latency_interconnect/simplex_xbar.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/tcdm_interconnect/clos_net.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/tcdm_interconnect/bfly_net.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/variable_latency_interconnect/full_duplex_xbar.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/tcdm_interconnect/tcdm_interconnect.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/variable_latency_interconnect/variable_latency_bfly_net.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/variable_latency_interconnect/variable_latency_interconnect.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/low_latency_interco/FanInPrimitive_Req.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/low_latency_interco/ArbitrationTree.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/low_latency_interco/MUX2_REQ.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/low_latency_interco/AddressDecoder_Resp.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/low_latency_interco/TestAndSet.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/low_latency_interco/RequestBlock2CH.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/low_latency_interco/RequestBlock1CH.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/low_latency_interco/FanInPrimitive_Resp.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/low_latency_interco/ResponseTree.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/low_latency_interco/ResponseBlock.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/low_latency_interco/AddressDecoder_Req.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/low_latency_interco/XBAR_TCDM.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/low_latency_interco/XBAR_TCDM_WRAPPER.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/low_latency_interco/TCDM_PIPE_REQ.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/low_latency_interco/TCDM_PIPE_RESP.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/low_latency_interco/grant_mask.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/low_latency_interco/priority_Flag_Req.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/peripheral_interco/AddressDecoder_PE_Req.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/peripheral_interco/AddressDecoder_Resp_PE.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/peripheral_interco/ArbitrationTree_PE.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/peripheral_interco/FanInPrimitive_Req_PE.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/peripheral_interco/RR_Flag_Req_PE.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/peripheral_interco/MUX2_REQ_PE.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/peripheral_interco/FanInPrimitive_PE_Resp.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/peripheral_interco/RequestBlock1CH_PE.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/peripheral_interco/RequestBlock2CH_PE.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/peripheral_interco/ResponseBlock_PE.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/peripheral_interco/ResponseTree_PE.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_interconnect-abcda71a83f4333c/rtl/peripheral_interco/XBAR_PE.sv' Reading Verilog file '../RTL/pulp/include/parameters.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpnew-3f06cec0e0e04d73/src/fpnew_pkg.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpnew-3f06cec0e0e04d73/src/fpnew_cast_multi.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpnew-3f06cec0e0e04d73/src/fpnew_classifier.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpnew-3f06cec0e0e04d73/src/fpnew_divsqrt_multi.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpnew-3f06cec0e0e04d73/src/fpnew_fma.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpnew-3f06cec0e0e04d73/src/fpnew_fma_multi.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpnew-3f06cec0e0e04d73/src/fpnew_noncomp.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpnew-3f06cec0e0e04d73/src/fpnew_opgroup_block.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpnew-3f06cec0e0e04d73/src/fpnew_opgroup_fmt_slice.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpnew-3f06cec0e0e04d73/src/fpnew_opgroup_multifmt_slice.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpnew-3f06cec0e0e04d73/src/fpnew_rounding.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpnew-3f06cec0e0e04d73/src/fpnew_top.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/hwpe_stream_interfaces.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/hwpe_stream_package.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/basic/hwpe_stream_assign.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/basic/hwpe_stream_buffer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/basic/hwpe_stream_demux_static.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/basic/hwpe_stream_deserialize.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/basic/hwpe_stream_fence.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/basic/hwpe_stream_merge.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/basic/hwpe_stream_mux_static.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/basic/hwpe_stream_serialize.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/basic/hwpe_stream_split.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/fifo/hwpe_stream_fifo_ctrl.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/fifo/hwpe_stream_fifo_scm.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/streamer/hwpe_stream_addressgen.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/streamer/hwpe_stream_addressgen_v2.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/streamer/hwpe_stream_addressgen_v3.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/streamer/hwpe_stream_sink_realign.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/streamer/hwpe_stream_source_realign.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/streamer/hwpe_stream_strbgen.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/streamer/hwpe_stream_streamer_queue.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/tcdm/hwpe_stream_tcdm_assign.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/tcdm/hwpe_stream_tcdm_mux.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/tcdm/hwpe_stream_tcdm_mux_static.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/tcdm/hwpe_stream_tcdm_reorder.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/tcdm/hwpe_stream_tcdm_reorder_static.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/fifo/hwpe_stream_fifo_earlystall.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/fifo/hwpe_stream_fifo_earlystall_sidech.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/fifo/hwpe_stream_fifo_scm_test_wrap.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/fifo/hwpe_stream_fifo_sidech.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/fifo/hwpe_stream_fifo.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/tcdm/hwpe_stream_tcdm_fifo_load_sidech.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/streamer/hwpe_stream_source.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/tcdm/hwpe_stream_tcdm_fifo.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/tcdm/hwpe_stream_tcdm_fifo_load.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/tcdm/hwpe_stream_tcdm_fifo_store.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-stream-2efec61d39f03cd2/rtl/streamer/hwpe_stream_sink.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/l2_tcdm_demux.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/lint_2_apb.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/lint_2_axi.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/axi_2_lint/axi64_2_lint32.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/axi_2_lint/axi_read_ctrl.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/axi_2_lint/axi_write_ctrl.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/axi_2_lint/lint64_to_32.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_L2/AddressDecoder_Req_L2.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_L2/AddressDecoder_Resp_L2.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_L2/ArbitrationTree_L2.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_L2/FanInPrimitive_Req_L2.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_L2/FanInPrimitive_Resp_L2.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_L2/MUX2_REQ_L2.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_L2/RequestBlock_L2_1CH.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_L2/RequestBlock_L2_2CH.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_L2/ResponseBlock_L2.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_L2/ResponseTree_L2.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_L2/RR_Flag_Req_L2.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_L2/XBAR_L2.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_BRIDGE/AddressDecoder_Req_BRIDGE.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_BRIDGE/AddressDecoder_Resp_BRIDGE.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_BRIDGE/ArbitrationTree_BRIDGE.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_BRIDGE/FanInPrimitive_Req_BRIDGE.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_BRIDGE/FanInPrimitive_Resp_BRIDGE.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_BRIDGE/MUX2_REQ_BRIDGE.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_BRIDGE/RequestBlock1CH_BRIDGE.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_BRIDGE/RequestBlock2CH_BRIDGE.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_BRIDGE/ResponseBlock_BRIDGE.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_BRIDGE/ResponseTree_BRIDGE.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_BRIDGE/RR_Flag_Req_BRIDGE.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/l2_tcdm_hybrid_interco-f03a86a7ac111e77/RTL/XBAR_BRIDGE/XBAR_BRIDGE.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb-e9f5172fecd19b49/src/apb_intf.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_pkg.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_intf.sv' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_atop_filter.sv' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_burst_splitter.sv' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' function bit txn_supported(axi_pkg::atop_t atop, axi_pkg::burst_t burst, axi_pkg::cache_t cache, | Warning : Usage of non-static tasks or functions might result in simulation-synthesis mismatch. [VLOGPT-692] : in file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_burst_splitter.sv' on line 99, column 14. : Use the 'automatic' keyword for declaring functions and tasks. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_cdc_dst.sv' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_cdc_src.sv' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_cut.sv' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_delayer.sv' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_demux.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_dw_downsizer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_dw_upsizer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_id_prepend.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_isolate.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_join.sv' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_lite_demux.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_lite_join.sv' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_lite_mailbox.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_lite_mux.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_lite_regs.sv' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_lite_to_apb.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_lite_to_axi.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_modify_address.sv' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_mux.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_serializer.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_cdc.sv' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_err_slv.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_dw_converter.sv' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_multicut.sv' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_to_axi_lite.sv' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_lite_xbar.sv' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_xbar.sv' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi_slice-4e4299f122d8400c/src/axi_single_slice.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi_slice-4e4299f122d8400c/src/axi_ar_buffer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi_slice-4e4299f122d8400c/src/axi_aw_buffer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi_slice-4e4299f122d8400c/src/axi_b_buffer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi_slice-4e4299f122d8400c/src/axi_r_buffer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi_slice-4e4299f122d8400c/src/axi_slice.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi_slice-4e4299f122d8400c/src/axi_w_buffer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi_slice-4e4299f122d8400c/src/axi_slice_wrap.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/include/apu_core_package.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/include/riscv_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/include/riscv_tracer_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_alu.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_alu_basic.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_alu_div.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_compressed_decoder.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_controller.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_cs_registers.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_decoder.sv' Reading Verilog file '../RTL/pulp/include/apu_macros.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_int_controller.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_ex_stage.sv' Reading Verilog file '../RTL/pulp/include/apu_macros.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_hwloop_controller.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_hwloop_regs.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/register_file_test_wrap.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_id_stage.sv' @(posedge clk) (branch_in_ex_o) |-> (branch_decision_i !== 1'bx) ) else begin $display("%t, Branch decision is X in module %m", $time); $stop; end | Warning : Ignoring unsynthesizable construct. [VLOGPT-37] : Call to system task '$stop' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_id_stage.sv' on line 1631, column 148. property p_branch_taken_ex; | Warning : Ignoring unsynthesizable construct. [VLOGPT-37] : Property declaration in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_id_stage.sv' on line 1639, column 30. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_if_stage.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_load_store_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_mult.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_prefetch_buffer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_prefetch_L0_buffer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_core.sv' Reading Verilog file '../RTL/pulp/include/riscv_config.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_apu_disp.sv' Reading Verilog file '../RTL/pulp/include/apu_macros.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_fetch_fifo.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_L0_buffer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_pmp.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_register_file.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/common/hci_package.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/common/hci_interfaces.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/core/hci_core_assign.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/core/hci_core_cmd_queue.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/core/hci_core_fifo.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/core/hci_core_memmap_demux_interl.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/core/hci_core_memmap_filter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/core/hci_core_mux_dynamic.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/core/hci_core_mux_static.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/core/hci_core_r_valid_filter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/core/hci_core_source.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/core/hci_core_split.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/interco/hci_log_interconnect.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/interco/hci_log_interconnect_l2.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/interco/hci_new_log_interconnect.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/interco/hci_shallow_interconnect.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/mem/hci_mem_assign.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/core/hci_core_sink.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/interco/hci_hwpe_interconnect.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hci-fdec9f801a620ca3/rtl/hci_interconnect.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-ctrl-aaea72c1bd54a7f4/rtl/hwpe_ctrl_interfaces.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-ctrl-aaea72c1bd54a7f4/rtl/hwpe_ctrl_package.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-ctrl-aaea72c1bd54a7f4/rtl/hwpe_ctrl_regfile_latch.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-ctrl-aaea72c1bd54a7f4/rtl/hwpe_ctrl_seq_mult.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-ctrl-aaea72c1bd54a7f4/rtl/hwpe_ctrl_uloop.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-ctrl-aaea72c1bd54a7f4/rtl/hwpe_ctrl_regfile_latch_test_wrap.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-ctrl-aaea72c1bd54a7f4/rtl/hwpe_ctrl_regfile.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-ctrl-aaea72c1bd54a7f4/rtl/hwpe_ctrl_slave.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/icache-intc-442aeb937a2acea0/Req_Arb_Node_icache_intc.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/icache-intc-442aeb937a2acea0/Resp_Arb_Node_icache_intc.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/icache-intc-442aeb937a2acea0/lint_mux.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/icache-intc-442aeb937a2acea0/DistributedArbitrationNetwork_Req_icache_intc.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/icache-intc-442aeb937a2acea0/DistributedArbitrationNetwork_Resp_icache_intc.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/icache-intc-442aeb937a2acea0/RoutingBlock_Req_icache_intc.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/icache-intc-442aeb937a2acea0/RoutingBlock_2ch_Req_icache_intc.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/icache-intc-442aeb937a2acea0/RoutingBlock_Resp_icache_intc.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/icache-intc-442aeb937a2acea0/icache_intc.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/scm-4e831bf16b340475/fpga_scm/register_file_1r_1w_all.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/scm-4e831bf16b340475/fpga_scm/register_file_1r_1w_be.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/scm-4e831bf16b340475/fpga_scm/register_file_1r_1w.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/scm-4e831bf16b340475/fpga_scm/register_file_1r_1w_1row.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/scm-4e831bf16b340475/fpga_scm/register_file_1r_1w_raw.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/scm-4e831bf16b340475/fpga_scm/register_file_1w_multi_port_read.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/scm-4e831bf16b340475/fpga_scm/register_file_1w_64b_multi_port_read_32b.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/scm-4e831bf16b340475/fpga_scm/register_file_1w_64b_1r_32b.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/scm-4e831bf16b340475/fpga_scm/register_file_2r_1w_asymm.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/scm-4e831bf16b340475/fpga_scm/register_file_2r_1w_asymm_test_wrap.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/scm-4e831bf16b340475/fpga_scm/register_file_2r_2w.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/scm-4e831bf16b340475/fpga_scm/register_file_3r_2w.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/common/io_clk_gen.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/common/io_event_counter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/common/io_generic_fifo.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/common/io_shiftreg.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/common/udma_apb_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/common/udma_clk_div_cnt.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/common/udma_ctrl.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/common/udma_dc_fifo.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_arbiter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_ch_addrgen.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/common/io_tx_fifo.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/common/io_tx_fifo_dc.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/common/io_tx_fifo_mark.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/common/udma_clkgen.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_stream_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_rx_channels.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_core.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_axi_module.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_defines.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_axi_defines.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_lint_biu.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_lint_module.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_defines.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_lint_defines.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_crc32.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_or1k_biu.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_or1k_module.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_defines.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_or1k_defines.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_or1k_status_reg.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_or1k_defines.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_top.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_defines.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/bytefifo.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/syncflop.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/syncreg.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_tap_top.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_tap_defines.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adv_dbg_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_axionly_top.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_defines.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_lintonly_top.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/adv_dbg_if-4a8e8ee83fb515d2/rtl/adbg_defines.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb2per-d066b0686e04a03e/apb2per.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb_adv_timer-ad83d91be9875631/rtl/adv_timer_apb_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb_adv_timer-ad83d91be9875631/rtl/comparator.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb_adv_timer-ad83d91be9875631/rtl/input_stage.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb_adv_timer-ad83d91be9875631/rtl/lut_4x4.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb_adv_timer-ad83d91be9875631/rtl/out_filter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb_adv_timer-ad83d91be9875631/rtl/prescaler.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb_adv_timer-ad83d91be9875631/rtl/timer_cntrl.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb_adv_timer-ad83d91be9875631/rtl/up_down_counter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb_adv_timer-ad83d91be9875631/rtl/timer_module.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb_adv_timer-ad83d91be9875631/rtl/apb_adv_timer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb_fll_if-30645ac88ad7542f/src/fll_intf.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb_fll_if-30645ac88ad7542f/src/apb_fll_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb_fll_if-30645ac88ad7542f/src/apb_to_fll.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb_interrupt_cntrl-dd2e5ce27b208df0/apb_interrupt_cntrl.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb_node-38396597780c7975/src/apb_node.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/apb_node-38396597780c7975/src/apb_node_wrap.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi2mem-e6a6085b4dfb755a/axi2mem_busy_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi2mem-e6a6085b4dfb755a/axi2mem_rd_channel.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi2mem-e6a6085b4dfb755a/axi2mem.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi2mem-e6a6085b4dfb755a/axi2mem_tcdm_rd_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi2mem-e6a6085b4dfb755a/axi2mem_tcdm_synch.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi2mem-e6a6085b4dfb755a/axi2mem_tcdm_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi2mem-e6a6085b4dfb755a/axi2mem_tcdm_wr_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi2mem-e6a6085b4dfb755a/axi2mem_trans_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi2mem-e6a6085b4dfb755a/axi2mem_wr_channel.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi2per-73355017779c4307/axi2per_req_channel.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi2per-73355017779c4307/axi2per_res_channel.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/axi2per-73355017779c4307/axi2per.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/cluster_control_unit/cluster_control_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/event_unit/HW_barrier_logic.sv' Reading Verilog file '../RTL/pulp/include/old_event_unit_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/event_unit/event_unit_arbiter.sv' Reading Verilog file '../RTL/pulp/include/old_event_unit_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/event_unit/event_unit_mux.sv' Reading Verilog file '../RTL/pulp/include/old_event_unit_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/event_unit/event_unit_sm.sv' Reading Verilog file '../RTL/pulp/include/old_event_unit_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/event_unit/interrupt_mask.sv' Reading Verilog file '../RTL/pulp/include/old_event_unit_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/event_unit/HW_barrier.sv' Reading Verilog file '../RTL/pulp/include/old_event_unit_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/event_unit/event_unit_input.sv' Reading Verilog file '../RTL/pulp/include/old_event_unit_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/event_unit/event_unit.sv' Reading Verilog file '../RTL/pulp/include/old_event_unit_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/icache_ctrl_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/mp_icache_ctrl_unit.sv' `define CLEAR_CNTS 6'b00_0100 | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'CLEAR_CNTS' in file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/mp_icache_ctrl_unit.sv' on line 37, column 40. : The latest definition of the macro will be used. `define ENABLE_CNTS 6'b00_0101 | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'ENABLE_CNTS' in file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/mp_icache_ctrl_unit.sv' on line 38, column 40. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/mp_pf_icache_ctrl_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/new_icache_ctrl_unit.sv' `define ENABLE_ICACHE 6'b00_0000 // W only --> Enable or Disable icache (use wdata[0]) | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'ENABLE_ICACHE' in file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/new_icache_ctrl_unit.sv' on line 34, column 94. `define FLUSH_ICACHE 6'b00_0001 // W only --> Full FLUSH icache | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'FLUSH_ICACHE' in file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/new_icache_ctrl_unit.sv' on line 35, column 73. `define SEL_FLUSH_ICACHE 6'b00_0010 // W Only --> Selective FLush (use wdata for address) | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'SEL_FLUSH_ICACHE' in file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/new_icache_ctrl_unit.sv' on line 36, column 94. `define CLEAR_CNTS 6'b00_0100 // W Only | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'CLEAR_CNTS' in file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/new_icache_ctrl_unit.sv' on line 40, column 58. `define ENABLE_CNTS 6'b00_0101 // W and R | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'ENABLE_CNTS' in file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/new_icache_ctrl_unit.sv' on line 41, column 59. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/pri_icache_ctrl_unit.sv' `define ENABLE_ICACHE 6'b00_0000 | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'ENABLE_ICACHE' in file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/pri_icache_ctrl_unit.sv' on line 34, column 36. `define FLUSH_ICACHE 6'b00_0001 | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'FLUSH_ICACHE' in file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/pri_icache_ctrl_unit.sv' on line 35, column 36. `define CLEAR_CNTS 6'b00_0011 | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'CLEAR_CNTS' in file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/pri_icache_ctrl_unit.sv' on line 36, column 37. `define ENABLE_CNTS 6'b00_0100 | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'ENABLE_CNTS' in file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/pri_icache_ctrl_unit.sv' on line 37, column 36. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/sp_icache_ctrl_unit.sv' `define SEL_FLUSH_ICACHE 6'b00_0011 | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'SEL_FLUSH_ICACHE' in file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/sp_icache_ctrl_unit.sv' on line 37, column 40. `define CLEAR_CNTS 6'b00_0100 | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'CLEAR_CNTS' in file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/sp_icache_ctrl_unit.sv' on line 39, column 40. `define ENABLE_CNTS 6'b00_0101 | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'ENABLE_CNTS' in file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/icache_ctrl_unit/sp_icache_ctrl_unit.sv' on line 40, column 40. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/mmu_config_unit/mmu_config_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/perf_counters_unit/perf_counters_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/cluster_peripherals-cc771700129bb934/tcdm_pipe_unit/tcdm_pipe_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/event_unit_flex-385402acb0ace331/rtl/event_unit_core.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/event_unit_flex-385402acb0ace331/rtl/hw_barrier_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/event_unit_flex-385402acb0ace331/rtl/hw_dispatch.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/event_unit_flex-385402acb0ace331/rtl/hw_mutex_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/event_unit_flex-385402acb0ace331/rtl/interc_sw_evt_trig.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/event_unit_flex-385402acb0ace331/rtl/periph_FIFO_id.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/event_unit_flex-385402acb0ace331/rtl/soc_periph_fifo.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/event_unit_flex-385402acb0ace331/rtl/event_unit_interface_mux.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/event_unit_flex-385402acb0ace331/rtl/event_unit_top.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_interco-f206baa74ecb3390/FP_WRAP/fp_iter_divsqrt_msv_wrapper_2_STAGE.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_interco-f206baa74ecb3390/FP_WRAP/fpnew_wrapper.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_interco-f206baa74ecb3390/RTL/AddressDecoder_Resp_FPU.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_interco-f206baa74ecb3390/RTL/FanInPrimitive_Req_FPU.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_interco-f206baa74ecb3390/RTL/FanInPrimitive_Resp_FPU.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_interco-f206baa74ecb3390/RTL/FPU_clock_gating.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_interco-f206baa74ecb3390/RTL/fpu_demux.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_interco-f206baa74ecb3390/RTL/LFSR_FPU.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_interco-f206baa74ecb3390/RTL/optimal_alloc.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_interco-f206baa74ecb3390/RTL/RR_Flag_Req_FPU.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_interco-f206baa74ecb3390/RTL/AddressDecoder_Req_FPU.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_interco-f206baa74ecb3390/RTL/ArbitrationTree_FPU.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_interco-f206baa74ecb3390/RTL/RequestBlock_FPU.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_interco-f206baa74ecb3390/RTL/ResponseTree_FPU.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_interco-f206baa74ecb3390/RTL/ResponseBlock_FPU.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_interco-f206baa74ecb3390/RTL/XBAR_FPU.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/fpu_interco-f206baa74ecb3390/RTL/shared_fpu_cluster.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/CTRL_UNIT/hier_icache_ctrl_unit.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' `define ENABLE_ICACHE 6'b00_0000 //0x00 | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'ENABLE_ICACHE' in file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/CTRL_UNIT/hier_icache_ctrl_unit.sv' on line 47, column 55. `define FLUSH_ICACHE 6'b00_0001 //0x04 | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'FLUSH_ICACHE' in file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/CTRL_UNIT/hier_icache_ctrl_unit.sv' on line 48, column 55. `define SEL_FLUSH_ICACHE 6'b00_0011 //0x0C | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'SEL_FLUSH_ICACHE' in file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/CTRL_UNIT/hier_icache_ctrl_unit.sv' on line 50, column 55. `define CLEAR_CNTS 6'b00_0100 //0x10 | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'CLEAR_CNTS' in file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/CTRL_UNIT/hier_icache_ctrl_unit.sv' on line 53, column 55. `define ENABLE_CNTS 6'b00_0101 //0x14 | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'ENABLE_CNTS' in file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/CTRL_UNIT/hier_icache_ctrl_unit.sv' on line 54, column 55. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/RTL/L1.5_CACHE/ram_ws_rs_data_scm.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/RTL/L1.5_CACHE/ram_ws_rs_tag_scm.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/RTL/L1.5_CACHE/RefillTracker_4.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/RTL/L1.5_CACHE/REP_buffer_4.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/RTL/L1_CACHE/pri_icache_controller.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/RTL/L1_CACHE/refill_arbiter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/RTL/L1_CACHE/register_file_1w_multi_port_read.sv' module register_file_1w_multi_port_read | Warning : Replacing previously read Verilog description. [VLOGPT-6] : Replacing Verilog description 'register_file_1w_multi_port_read' with Verilog module in file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/RTL/L1_CACHE/register_file_1w_multi_port_read.sv' on line 11, column 39. : A Verilog description is replaced when a new description of the same name and same library is read again. Verilog descriptions are: module macromodule configuration SystemVerilog adds the following descriptions: interface program package. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/CTRL_UNIT/hier_icache_ctrl_unit_wrap.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/RTL/L1.5_CACHE/AXI4_REFILL_Resp_Deserializer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/RTL/L1.5_CACHE/share_icache_controller.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/RTL/L1_CACHE/register_file_1w_multi_port_read_test_wrap.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/RTL/L1.5_CACHE/share_icache.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/RTL/L1_CACHE/pri_icache.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/RTL/TOP/icache_hier_top.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' initial begin | Warning : Ignoring unsynthesizable construct. [VLOGPT-37] : Initial in file '../RTL/pulp/.bender/git/checkouts/hier-icache-fa9462fd6a0f0398/RTL/TOP/icache_hier_top.sv' on line 548, column 9. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-datamover-example-a9b2d6689c13b9f9/rtl/datamover_engine.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-datamover-example-a9b2d6689c13b9f9/rtl/datamover_package.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-datamover-example-a9b2d6689c13b9f9/rtl/datamover_streamer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-datamover-example-a9b2d6689c13b9f9/rtl/datamover_top.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-mac-engine-51b68cfc401cd47c/rtl/mac_package.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-mac-engine-51b68cfc401cd47c/rtl/mac_engine.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-mac-engine-51b68cfc401cd47c/rtl/mac_fsm.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-mac-engine-51b68cfc401cd47c/rtl/mac_streamer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-mac-engine-51b68cfc401cd47c/rtl/mac_ctrl.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-mac-engine-51b68cfc401cd47c/rtl/mac_top.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/hwpe-mac-engine-51b68cfc401cd47c/wrap/mac_top_wrap.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_register_file_latch.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_register_file_fpga.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_pkg.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/vendor/lowrisc_ip/ip/prim/rtl/prim_assert.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/vendor/lowrisc_ip/ip/prim/rtl/prim_assert_dummy_macros.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_alu.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_compressed_decoder.sv' Reading Verilog file '../RTL/pulp/include/prim_assert.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_controller.sv' Reading Verilog file '../RTL/pulp/include/prim_assert.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_counter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_csr.sv' Reading Verilog file '../RTL/pulp/include/prim_assert.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_decoder.sv' Reading Verilog file '../RTL/pulp/include/prim_assert.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_fetch_fifo.sv' Reading Verilog file '../RTL/pulp/include/prim_assert.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_load_store_unit.sv' Reading Verilog file '../RTL/pulp/include/prim_assert.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_multdiv_fast.sv' Reading Verilog file '../RTL/pulp/include/prim_assert.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_multdiv_slow.sv' Reading Verilog file '../RTL/pulp/include/prim_assert.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_pmp.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_wb_stage.sv' Reading Verilog file '../RTL/pulp/include/prim_assert.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_cs_registers.sv' Reading Verilog file '../RTL/pulp/include/prim_assert.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_ex_block.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_id_stage.sv' Reading Verilog file '../RTL/pulp/include/prim_assert.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_prefetch_buffer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_if_stage.sv' Reading Verilog file '../RTL/pulp/include/prim_assert.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/ibex-71db63ed1d9e7444/rtl/ibex_core.sv' Reading Verilog file '../RTL/pulp/include/prim_assert.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/icache_mp_128_pf-39146432607e09be/RTL/icache_bank_mp_128.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/icache_mp_128_pf-39146432607e09be/RTL/icache_bank_mp_PF.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/icache_mp_128_pf-39146432607e09be/RTL/merge_refill_cam_128_16.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/icache_mp_128_pf-39146432607e09be/RTL/pf_miss_mux.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/icache_mp_128_pf-39146432607e09be/RTL/prefetcher_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/icache_mp_128_pf-39146432607e09be/RTL/central_controller_128.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/icache_mp_128_pf-39146432607e09be/RTL/cache_controller_to_axi_128_PF.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/icache_mp_128_pf-39146432607e09be/RTL/icache_top_mp_128_PF.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/jtag_pulp-5deebd21d33ee03d/src/bscell.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/jtag_pulp-5deebd21d33ee03d/src/jtag_axi_wrap.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/jtag_pulp-5deebd21d33ee03d/src/jtag_enable.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/jtag_pulp-5deebd21d33ee03d/src/jtag_enable_synch.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/jtag_pulp-5deebd21d33ee03d/src/jtagreg.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/jtag_pulp-5deebd21d33ee03d/src/jtag_rst_synch.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/jtag_pulp-5deebd21d33ee03d/src/jtag_sync.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/jtag_pulp-5deebd21d33ee03d/src/tap_top.v' `define IDCODE_VALUE 32'h10102001 | Warning : Redefinition of macro. [VLOGPT-647] : Macro 'IDCODE_VALUE' in file '../RTL/pulp/.bender/git/checkouts/jtag_pulp-5deebd21d33ee03d/src/tap_top.v' on line 16, column 34. Warning : Maximum message print count reached. [MESG-11] : Maximum print count of '20' reached for message 'VLOGPT-647'. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/misc/mchan_arbiter.sv' Reading Verilog file '../RTL/pulp/include/mchan_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/misc/mchan_arb_primitive.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/misc/mchan_rr_flag_req.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ctrl_unit/ctrl_fsm.sv' Reading Verilog file '../RTL/pulp/include/mchan_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ctrl_unit/ctrl_if.sv' Reading Verilog file '../RTL/pulp/include/mchan_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ctrl_unit/ctrl_unit.sv' Reading Verilog file '../RTL/pulp/include/mchan_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ctrl_unit/synch_unit.sv' Reading Verilog file '../RTL/pulp/include/mchan_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ctrl_unit/trans_allocator.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ctrl_unit/trans_queue.sv' Reading Verilog file '../RTL/pulp/include/mchan_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ctrl_unit/trans_arbiter_wrap.sv' Reading Verilog file '../RTL/pulp/include/mchan_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ctrl_unit/trans_unpack.sv' Reading Verilog file '../RTL/pulp/include/mchan_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ctrl_unit/twd_trans_queue.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ctrl_unit/twd_trans_splitter.sv' Reading Verilog file '../RTL/pulp/include/mchan_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ext_unit/ext_ar_buffer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ext_unit/ext_aw_buffer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ext_unit/ext_b_buffer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ext_unit/ext_buffer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ext_unit/ext_opc_buf.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ext_unit/ext_r_buffer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ext_unit/ext_rx_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ext_unit/ext_tid_gen.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ext_unit/ext_tx_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ext_unit/ext_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/ext_unit/ext_w_buffer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/tcdm_unit/tcdm_cmd_unpack.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/tcdm_unit/tcdm_rx_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/tcdm_unit/tcdm_synch.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/tcdm_unit/tcdm_tx_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/tcdm_unit/tcdm_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/trans_unit/trans_aligner.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/trans_unit/trans_buffers.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/trans_unit/trans_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/mchan-1903412f92cb4b0c/rtl/top/mchan.sv' Reading Verilog file '../RTL/pulp/include/mchan_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/per2axi-09e2f0897050514a/src/per2axi_busy_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/per2axi-09e2f0897050514a/src/per2axi_req_channel.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/per2axi-09e2f0897050514a/src/per2axi_res_channel.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/per2axi-09e2f0897050514a/src/per2axi.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/register_interface-1e5f22ae6b2b5b5d/src/reg_intf.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/register_interface-1e5f22ae6b2b5b5d/vendor/lowrisc_opentitan/src/prim_subreg_arb.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/register_interface-1e5f22ae6b2b5b5d/vendor/lowrisc_opentitan/src/prim_subreg_ext.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/register_interface-1e5f22ae6b2b5b5d/src/apb_to_reg.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/register_interface-1e5f22ae6b2b5b5d/src/axi_to_reg.sv' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/register_interface-1e5f22ae6b2b5b5d/src/periph_to_reg.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/register_interface-1e5f22ae6b2b5b5d/src/reg_cdc.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/register_interface-1e5f22ae6b2b5b5d/src/reg_demux.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/register_interface-1e5f22ae6b2b5b5d/src/reg_mux.sv' Reading Verilog file '../RTL/pulp/include/register_interface/typedef.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/register_interface-1e5f22ae6b2b5b5d/src/reg_to_mem.sv' Reading Verilog file '../RTL/pulp/include/common_cells/registers.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/register_interface-1e5f22ae6b2b5b5d/src/reg_uniform.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/register_interface-1e5f22ae6b2b5b5d/vendor/lowrisc_opentitan/src/prim_subreg_shadow.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/register_interface-1e5f22ae6b2b5b5d/vendor/lowrisc_opentitan/src/prim_subreg.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/register_interface-1e5f22ae6b2b5b5d/src/axi_lite_to_reg.sv' Reading Verilog file '../RTL/pulp/include/register_interface/typedef.svh' Reading Verilog file '../RTL/pulp/include/register_interface/assign.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/riscv-dbg-d1510f6d3bbea38a/src/dm_pkg.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/riscv-dbg-d1510f6d3bbea38a/debug_rom/debug_rom.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/riscv-dbg-d1510f6d3bbea38a/debug_rom/debug_rom_one_scratch.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/riscv-dbg-d1510f6d3bbea38a/src/dm_csrs.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/riscv-dbg-d1510f6d3bbea38a/src/dm_mem.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/riscv-dbg-d1510f6d3bbea38a/src/dm_top.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/riscv-dbg-d1510f6d3bbea38a/src/dm_obi_top.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/riscv-dbg-d1510f6d3bbea38a/src/dmi_cdc.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/riscv-dbg-d1510f6d3bbea38a/src/dmi_jtag.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/riscv-dbg-d1510f6d3bbea38a/src/dmi_jtag_tap.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/riscv-dbg-d1510f6d3bbea38a/src/dm_sba.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/timer_unit-7ee4cd321dafe5e2/rtl/timer_unit_counter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/timer_unit-7ee4cd321dafe5e2/rtl/timer_unit_counter_presc.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/timer_unit-7ee4cd321dafe5e2/rtl/apb_timer_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/timer_unit-7ee4cd321dafe5e2/rtl/timer_unit.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_camera-86b8118519db0f98/rtl/camera_reg_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_camera-86b8118519db0f98/rtl/camera_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_external_per-3d0c2cf4ffbe1df6/rtl/udma_external_per_reg_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_external_per-3d0c2cf4ffbe1df6/rtl/udma_traffic_gen_rx.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_external_per-3d0c2cf4ffbe1df6/rtl/udma_traffic_gen_tx.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_external_per-3d0c2cf4ffbe1df6/rtl/udma_external_per_top.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_external_per-3d0c2cf4ffbe1df6/rtl/udma_external_per_wrapper.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_filter-a40516c05ed4bf59/rtl/udma_filter_au.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_filter-a40516c05ed4bf59/rtl/udma_filter_bincu.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_filter-a40516c05ed4bf59/rtl/udma_filter_reg_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_filter-a40516c05ed4bf59/rtl/udma_filter_rx_dataout.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_filter-a40516c05ed4bf59/rtl/udma_filter_tx_datafetch.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_filter-a40516c05ed4bf59/rtl/udma_filter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/cdc_fifo_gray_hyper.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/graycode_hyper.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/clock_diff_out.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/clk_gen_hyper.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/onehot_to_bin_hyper.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/ddr_out.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/hyperbus_delay_line.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/read_clk_rwds.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/hyperbus_phy.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/cmd_addr_gen.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/ddr_in.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/udma_hyper_reg_if_common.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/udma_hyper_reg_if_mulid.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/udma_rxbuffer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/udma_txbuffer.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/udma_hyper_ctrl.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/udma_hyperbus_mulid.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/hyper_unpack.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/udma_cfg_outbuff.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/hyperbus_mux_generic.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/hyper_twd_trans_spliter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/hyper_rr_flag_req.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/hyper_arbiter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/hyper_arb_primitive.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/io_generic_fifo_hyper.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/udma_dc_fifo_hyper.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/dc_token_ring_fifo_din_hyper.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/dc_token_ring_fifo_dout_hyper.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/dc_token_ring_hyper.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/dc_data_buffer_hyper.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/dc_full_detector_hyper.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/dc_synchronizer_hyper.v' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/udma_cmd_queue.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/udma_hyper_busy.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/udma_hyper_busy_phy.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/udma_hyper_top.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2c-86169ce0b4173d19/rtl/udma_i2c_bus_ctrl.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2c-86169ce0b4173d19/rtl/udma_i2c_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2c-86169ce0b4173d19/rtl/udma_i2c_reg_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2c-86169ce0b4173d19/rtl/udma_i2c_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2c-86169ce0b4173d19/rtl/udma_i2c_control.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2c-86169ce0b4173d19/rtl/udma_i2c_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2c-86169ce0b4173d19/rtl/udma_i2c_top.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2c-86169ce0b4173d19/rtl/udma_i2c_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2s-4c2d946afbfb2209/rtl/cic_comb.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2s-4c2d946afbfb2209/rtl/cic_integrator.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2s-4c2d946afbfb2209/rtl/i2s_clk_gen.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2s-4c2d946afbfb2209/rtl/i2s_rx_channel.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2s-4c2d946afbfb2209/rtl/i2s_tx_channel.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2s-4c2d946afbfb2209/rtl/i2s_ws_gen.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2s-4c2d946afbfb2209/rtl/udma_i2s_reg_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2s-4c2d946afbfb2209/rtl/cic_top.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2s-4c2d946afbfb2209/rtl/i2s_clkws_gen.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2s-4c2d946afbfb2209/rtl/pdm_top.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2s-4c2d946afbfb2209/rtl/i2s_txrx.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_i2s-4c2d946afbfb2209/rtl/udma_i2s_top.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_ctrl.sv' Reading Verilog file '../RTL/pulp/include/udma_spim_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_reg_if.sv' Reading Verilog file '../RTL/pulp/include/udma_spim_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_txrx.sv' Reading Verilog file '../RTL/pulp/include/udma_spim_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_top.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_sdio-eb03ff2eeab7e6c0/rtl/sdio_crc16.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_sdio-eb03ff2eeab7e6c0/rtl/sdio_crc7.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_sdio-eb03ff2eeab7e6c0/rtl/udma_sdio_reg_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_sdio-eb03ff2eeab7e6c0/rtl/sdio_txrx_cmd.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_sdio-eb03ff2eeab7e6c0/rtl/sdio_txrx_data.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_sdio-eb03ff2eeab7e6c0/rtl/sdio_txrx.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_sdio-eb03ff2eeab7e6c0/rtl/udma_sdio_top.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_uart-987a5c3aaae1cf57/rtl/udma_uart_reg_if.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_uart-987a5c3aaae1cf57/rtl/udma_uart_rx.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_uart-987a5c3aaae1cf57/rtl/udma_uart_tx.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/udma_uart-987a5c3aaae1cf57/rtl/udma_uart_top.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/packages/pulp_cluster_package.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/axi2mem_wrap.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/axi2per_wrap.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/cluster_bus_wrap.sv' Reading Verilog file '../RTL/pulp/include/cluster_bus_defines.sv' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/cluster_clock_gate.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/cluster_event_map.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/cluster_timer_wrap.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/dmac_wrap.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/hwpe_subsystem.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/instr_width_converter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/per2axi_wrap.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/periph_demux.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/per_demux_wrap.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/periph_FIFO.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/tcdm_banks_wrap.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/xbar_pe_wrap.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' logic cluster_alias=1'b1; | Warning : Ignoring unsynthesizable construct. [VLOGPT-37] : Initial value assignment to reg in file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/xbar_pe_wrap.sv' on line 51, column 58. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/cluster_interconnect_wrap.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/cluster_peripherals.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/core_demux.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/core_region.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/include/periph_bus_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_cluster-48721e3ce381c984/rtl/pulp_cluster.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/include/cluster_bus_defines.sv' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/pkg_soc_interconnect.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/axi64_2_lint32_wrap.sv' Reading Verilog file '../RTL/pulp/include/tcdm_macros.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/lint_2_axi_wrap.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/contiguous_crossbar.sv' Reading Verilog file '../RTL/pulp/include/tcdm_macros.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/interleaved_crossbar.sv' Reading Verilog file '../RTL/pulp/include/tcdm_macros.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/tcdm_demux.sv' Reading Verilog file '../RTL/pulp/include/tcdm_macros.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/boot_rom.sv' Reading Verilog file '../RTL/pulp/include/soc_mem_map.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/l2_ram_multi_bank.sv' Reading Verilog file '../RTL/pulp/include/soc_mem_map.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/lint_jtag_wrap.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/periph_bus_wrap.sv' Reading Verilog file '../RTL/pulp/include/periph_bus_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/soc_clk_rst_gen.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/soc_event_arbiter.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/soc_event_generator.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/soc_event_queue.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/tcdm_error_slave.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/soc_interconnect.sv' Reading Verilog file '../RTL/pulp/include/tcdm_macros.svh' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' assign demux_slaves[0].r_valid = l2_demux_2_axi_bridge[i].r_valid ;; | Warning : Ignoring unexpected semicolon. [VLOGPT-670] : in file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/soc_interconnect.sv' on line 95, column 68. assign demux_slaves[1].r_valid = l2_demux_2_contiguous_xbar[i].r_valid ;; | Warning : Ignoring unexpected semicolon. [VLOGPT-670] : in file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/soc_interconnect.sv' on line 96, column 73. assign demux_slaves[2].r_valid = l2_demux_2_interleaved_xbar[i].r_valid ;; | Warning : Ignoring unexpected semicolon. [VLOGPT-670] : in file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/soc_interconnect.sv' on line 97, column 74. assign err_demux_slaves[1].r_valid = master_ports_interleaved_only_checked[i].r_valid ;; | Warning : Ignoring unexpected semicolon. [VLOGPT-670] : in file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/soc_interconnect.sv' on line 123, column 88. assign err_demux_slaves[0].r_valid = err_slave.r_valid ;; | Warning : Ignoring unexpected semicolon. [VLOGPT-670] : in file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/soc_interconnect.sv' on line 127, column 57. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/soc_interconnect_wrap.sv' Reading Verilog file '../RTL/pulp/include/soc_mem_map.svh' Reading Verilog file '../RTL/pulp/include/tcdm_macros.svh' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/soc_peripherals.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/pulp_soc.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/include/axi/typedef.svh' Reading Verilog file '../RTL/pulp/include/axi/assign.svh' function logic [NrHarts-1:0] SEL_HARTS_FX(); | Warning : Usage of non-static tasks or functions might result in simulation-synthesis mismatch. [VLOGPT-692] : in file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/pulp_soc.sv' on line 243, column 18. Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/udma_subsystem/udma_subsystem.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/fc/fc_demux.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/fc/fc_subsystem.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/fc/fc_hwpe.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/components/apb_clkdiv.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/components/apb_soc_ctrl.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/components/memory_models.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/components/pulp_interfaces.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/components/glitch_free_clk_mux.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/components/scm_2048x32.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/components/scm_512x32.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/components/tcdm_arbiter_2x1.sv' Reading Verilog file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/components/obi_pulp_adapter.sv' Reading Verilog file '../RTL/pulp/fpga/pulp/rtl/fpga_clk_gen.sv' Reading Verilog file '../RTL/pulp/fpga/pulp/rtl/fpga_slow_clk_gen.sv' Reading Verilog file '../RTL/pulp/fpga/pulp/rtl/fpga_bootrom.sv' Reading Verilog file '../RTL/pulp/rtl/pulp/cluster_domain.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/include/cluster_bus_defines.sv' Reading Verilog file '../RTL/pulp/rtl/pulp/jtag_tap_top.sv' Reading Verilog file '../RTL/pulp/rtl/pulp/pad_control.sv' Reading Verilog file '../RTL/pulp/rtl/pulp/pad_frame.sv' Reading Verilog file '../RTL/pulp/rtl/pulp/rtc_clock.sv' Reading Verilog file '../RTL/pulp/rtl/pulp/rtc_date.sv' Reading Verilog file '../RTL/pulp/rtl/pulp/soc_domain.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/rtl/pulp/safe_domain.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/rtl/pulp/pulp.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' Reading Verilog file '../RTL/pulp/include/soc_bus_defines.sv' Reading Verilog file '../RTL/pulp/include/pulp_soc_defines.sv' legacy_genus:/> elaborate $DESIGN Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'S' and 'Z' in libcell 'CKMUX2D0BWP7T40P140'. : Setting the 'timing_sense' to non_unate. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'S' and 'Z' in libcell 'CKMUX2D1BWP7T40P140'. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'S' and 'Z' in libcell 'CKMUX2D2BWP7T40P140'. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'S' and 'Z' in libcell 'CKMUX2D4BWP7T40P140'. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'A2' and 'Z' in libcell 'CKXOR2D0BWP7T40P140'. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'A1' and 'Z' in libcell 'CKXOR2D0BWP7T40P140'. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'A2' and 'Z' in libcell 'CKXOR2D1BWP7T40P140'. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'A1' and 'Z' in libcell 'CKXOR2D1BWP7T40P140'. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'A2' and 'Z' in libcell 'CKXOR2D2BWP7T40P140'. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'A1' and 'Z' in libcell 'CKXOR2D2BWP7T40P140'. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'A2' and 'Z' in libcell 'CKXOR2D4BWP7T40P140'. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'A1' and 'Z' in libcell 'CKXOR2D4BWP7T40P140'. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'CI' and 'S' in libcell 'FA1D0BWP7T40P140'. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'B' and 'S' in libcell 'FA1D0BWP7T40P140'. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'A' and 'S' in libcell 'FA1D0BWP7T40P140'. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'CI' and 'S' in libcell 'FA1D1BWP7T40P140'. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'B' and 'S' in libcell 'FA1D1BWP7T40P140'. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'A' and 'S' in libcell 'FA1D1BWP7T40P140'. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'CI' and 'S' in libcell 'FA1D2BWP7T40P140'. Info : Both 'pos_unate' and 'neg_unate' timing_sense arcs have been processed. [LBR-162] : Non_unate 'timing_sense' inferred between pin 'B' and 'S' in libcell 'FA1D2BWP7T40P140'. Warning : Maximum message print count reached. [MESG-11] : Maximum print count of '20' reached for message 'LBR-162'. Libraries have 455 usable logic and 268 usable sequential lib-cells. Info : Unusable library cells found at the time of loading a library. [LBR-415] : Library: 'tcbn22ulpbwp7t40p140ffg0p88v0c.lib', Total cells: 846, Unusable cells: 94. List of unusable cells: 'ANTENNABWP7T40P140 BHDBWP7T40P140 BOUNDARY_LEFTBWP7T40P140 BOUNDARY_RIGHTBWP7T40P140 BUFFD20BWP7T40P140 CKBD20BWP7T40P140 CKLNQD20BWP7T40P140 CKLNQOPPSAD20BWP7T40P140 CKND20BWP7T40P140 DCAP16BWP7T40P140 DCAP32BWP7T40P140 DCAP4BWP7T40P140 DCAP64BWP7T40P140 DCAP8BWP7T40P140 DCCKND20BWP7T40P140 FILL16BWP7T40P140 FILL2BWP7T40P140 FILL32BWP7T40P140 FILL3BWP7T40P140 FILL4BWP7T40P140 FILL64BWP7T40P140 FILL8BWP7T40P140 GAN2D1BWP7T30P140 GAN2D2BWP7T30P140 GAOI21D1BWP7T30P140 GAOI21D2BWP7T30P140 GAOI22D1BWP7T30P140 GBUFFD1BWP7T30P140 GBUFFD2BWP7T30P140 GBUFFD3BWP7T30P140 GBUFFD4BWP7T30P140 GBUFFD8BWP7T30P140 GDCAP10BWP7T30P140 GDCAP11BWP7T30P140 GDCAP12BWP7T30P140 GDCAP13BWP7T30P140 GDCAP14BWP7T30P140 GDCAP2BWP7T30P140 GDCAP3BWP7T30P140 GDCAP4BWP7T30P140 GDCAP5BWP7T30P140 GDCAP6BWP7T30P140 GDCAP7BWP7T30P140 GDCAP8BWP7T30P140 GDCAP9BWP7T30P140 GDCAPBWP7T30P140 GDFCNQD1BWP7T30P140 GDFQD1BWP7T30P140 GFILL10BWP7T30P140 GFILL11BWP7T30P140 GFILL12BWP7T30P140 GFILL13BWP7T30P140 GFILL14BWP7T30P140 GFILL2BWP7T30P140 GFILL3BWP7T30P140 GFILL4BWP7T30P140 GFILL5BWP7T30P140 GFILL6BWP7T30P140 GFILL7BWP7T30P140 GFILL8BWP7T30P140 GFILL9BWP7T30P140 GFILLBWP7T30P140 GINVD1BWP7T30P140 GINVD2BWP7T30P140 GINVD3BWP7T30P140 GINVD4BWP7T30P140 GINVD8BWP7T30P140 GMUX2D1BWP7T30P140 GMUX2D2BWP7T30P140 GMUX2ND1BWP7T30P140 GMUX2ND2BWP7T30P140 GND2D1BWP7T30P140 GND2D2BWP7T30P140 GND2D3BWP7T30P140 GND2D4BWP7T30P140 GND3D1BWP7T30P140 GND3D2BWP7T30P140 GNR2D1BWP7T30P140 GNR2D2BWP7T30P140 GNR3D1BWP7T30P140 GNR3D2BWP7T30P140 GOAI21D1BWP7T30P140 GOAI21D2BWP7T30P140 GOR2D1BWP7T30P140 GOR2D2BWP7T30P140 GSDFCNQD1BWP7T30P140 GTIEHBWP7T30P140 GTIELBWP7T30P140 GXNR2D1BWP7T30P140 GXNR2D2BWP7T30P140 GXOR2D1BWP7T30P140 GXOR2D2BWP7T30P140 INVD20BWP7T40P140 TAPCELLBWP7T40P140 .' : For more information, refer to 'Cells Identified as Unusable' in the 'User Guide'. To know the reason why a cell is considered as unusable, check 'unusable_reason' libcell attribute. INLINE_INFO: Skipping marking small hierarchies inline as the variable 'hdl_dissolve_primitive_instance_hierarchy_threshold' has not been set to a positive value. Info : Elaborating Design. [ELAB-1] : Elaborating top-level block 'pulp' from file '../RTL/pulp/rtl/pulp/pulp.sv'. Warning : Using default parameter value for module elaboration. [CDFG-818] : Elaborating block 'pulp' with default parameters value. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 's_pad_cfg' in module 'pulp' in file '../RTL/pulp/rtl/pulp/pulp.sv' on line 123. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 's_spi_csn' in module 'pulp' in file '../RTL/pulp/rtl/pulp/pulp.sv' on line 426. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 's_spi_oen' in module 'pulp' in file '../RTL/pulp/rtl/pulp/pulp.sv' on line 427. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 's_spi_sdo' in module 'pulp' in file '../RTL/pulp/rtl/pulp/pulp.sv' on line 428. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 's_spi_sdi' in module 'pulp' in file '../RTL/pulp/rtl/pulp/pulp.sv' on line 429. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 's_event_dataasync' in module 'pulp' in file '../RTL/pulp/rtl/pulp/pulp.sv' on line 463. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 's_cluster_soc_bus_aw_data' in module 'pulp' in file '../RTL/pulp/rtl/pulp/pulp.sv' on line 468. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 's_cluster_soc_bus_ar_data' in module 'pulp' in file '../RTL/pulp/rtl/pulp/pulp.sv' on line 472. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 's_cluster_soc_bus_w_data' in module 'pulp' in file '../RTL/pulp/rtl/pulp/pulp.sv' on line 476. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 's_cluster_soc_bus_r_data' in module 'pulp' in file '../RTL/pulp/rtl/pulp/pulp.sv' on line 480. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 's_cluster_soc_bus_b_data' in module 'pulp' in file '../RTL/pulp/rtl/pulp/pulp.sv' on line 484. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 's_soc_cluster_bus_aw_data' in module 'pulp' in file '../RTL/pulp/rtl/pulp/pulp.sv' on line 489. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 's_soc_cluster_bus_ar_data' in module 'pulp' in file '../RTL/pulp/rtl/pulp/pulp.sv' on line 493. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 's_soc_cluster_bus_w_data' in module 'pulp' in file '../RTL/pulp/rtl/pulp/pulp.sv' on line 497. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 's_soc_cluster_bus_r_data' in module 'pulp' in file '../RTL/pulp/rtl/pulp/pulp.sv' on line 501. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 's_soc_cluster_bus_b_data' in module 'pulp' in file '../RTL/pulp/rtl/pulp/pulp.sv' on line 505. Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'pad_frame' from file '../RTL/pulp/rtl/pulp/pad_frame.sv'. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 'pad_cfg_i' in module 'pad_frame' in file '../RTL/pulp/rtl/pulp/pad_frame.sv' on line 15. Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'pad_functional_pd' from file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/fpga/pad_functional_xilinx.sv'. Warning : In legacy_ui mode, Genus creates a blackbox as description for a module is not found. Black boxes represent unresolved references in the design and are usually not expected. Another possible reason is, some libraries are not read and the tool could not get the content for some macros or lib_cells. [CDFG-428] : A blackbox was created for instance 'iobuf_i' in file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/fpga/pad_functional_xilinx.sv' on line 22. : Check the kind of module a black box is. If it is a lib_cell or a macro, check why the corresponding .lib was not read in. This could be either due to a missing or faulty file or due to an incomplete init_lib_search_path attribute value making restricting access to the missing file. If it is a module of your design, verify whether the path to this module is a part of the files you read or else check that the init_hdl_search_path attribute is not missing some paths. Info : Unused module input port. [CDFG-500] : Input port 'PEN' is not used in module 'pad_functional_pd' in file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/fpga/pad_functional_xilinx.sv' on line 17. : (In port definition within the module, the input port is not used in any assignment statements or conditional expressions for decision statements. Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'pad_functional_pu' from file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/fpga/pad_functional_xilinx.sv'. Info : Unused module input port. [CDFG-500] : Input port 'PEN' is not used in module 'pad_functional_pu' in file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/fpga/pad_functional_xilinx.sv' on line 36. Info : Unused instance port. [ELABUTL-132] : Unused Port 'I' of instance 'padinst_bootsel0' of module 'pad_functional_pu' inside module 'pad_frame' in file '../RTL/pulp/rtl/pulp/pad_frame.sv' on line 306. : Please check the reported scenario of unconnected instance port to ensure that it matches the design intent. Info : Unused instance port. [ELABUTL-132] : Unused Port 'I' of instance 'padinst_bootsel1' of module 'pad_functional_pu' inside module 'pad_frame' in file '../RTL/pulp/rtl/pulp/pad_frame.sv' on line 307. Info : Unused instance port. [ELABUTL-132] : Unused Port 'I' of instance 'padinst_ref_clk' of module 'pad_functional_pu' inside module 'pad_frame' in file '../RTL/pulp/rtl/pulp/pad_frame.sv' on line 312. Info : Unused instance port. [ELABUTL-132] : Unused Port 'I' of instance 'padinst_reset_n' of module 'pad_functional_pu' inside module 'pad_frame' in file '../RTL/pulp/rtl/pulp/pad_frame.sv' on line 313. Info : Unused instance port. [ELABUTL-132] : Unused Port 'I' of instance 'padinst_jtag_tck' of module 'pad_functional_pu' inside module 'pad_frame' in file '../RTL/pulp/rtl/pulp/pad_frame.sv' on line 314. Info : Unused instance port. [ELABUTL-132] : Unused Port 'I' of instance 'padinst_jtag_tms' of module 'pad_functional_pu' inside module 'pad_frame' in file '../RTL/pulp/rtl/pulp/pad_frame.sv' on line 315. Info : Unused instance port. [ELABUTL-132] : Unused Port 'I' of instance 'padinst_jtag_tdi' of module 'pad_functional_pu' inside module 'pad_frame' in file '../RTL/pulp/rtl/pulp/pad_frame.sv' on line 316. Info : Unused instance port. [ELABUTL-132] : Unused Port 'I' of instance 'padinst_jtag_trstn' of module 'pad_functional_pu' inside module 'pad_frame' in file '../RTL/pulp/rtl/pulp/pad_frame.sv' on line 317. Info : Unused instance port. [ELABUTL-132] : Unused Port 'O' of instance 'padinst_jtag_tdo' of module 'pad_functional_pd' inside module 'pad_frame' in file '../RTL/pulp/rtl/pulp/pad_frame.sv' on line 318. Info : Unused module input port. [CDFG-500] : Input port 'pad_cfg_i[28]' is not used in module 'pad_frame' in file '../RTL/pulp/rtl/pulp/pad_frame.sv' on line 15. Info : Unused module input port. [CDFG-500] : Input port 'pad_cfg_i[29]' is not used in module 'pad_frame' in file '../RTL/pulp/rtl/pulp/pad_frame.sv' on line 15. Info : Unused module input port. [CDFG-500] : Input port 'pad_cfg_i[30]' is not used in module 'pad_frame' in file '../RTL/pulp/rtl/pulp/pad_frame.sv' on line 15. Info : Unused module input port. [CDFG-500] : Input port 'pad_cfg_i[31]' is not used in module 'pad_frame' in file '../RTL/pulp/rtl/pulp/pad_frame.sv' on line 15. Info : Unused module input port. [CDFG-500] : Input port 'pad_cfg_i[32]' is not used in module 'pad_frame' in file '../RTL/pulp/rtl/pulp/pad_frame.sv' on line 15. Info : Unused module input port. [CDFG-500] : Input port 'pad_cfg_i[39]' is not used in module 'pad_frame' in file '../RTL/pulp/rtl/pulp/pad_frame.sv' on line 15. Info : Unused module input port. [CDFG-500] : Input port 'pad_cfg_i[40]' is not used in module 'pad_frame' in file '../RTL/pulp/rtl/pulp/pad_frame.sv' on line 15. Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'safe_domain' from file '../RTL/pulp/rtl/pulp/safe_domain.sv'. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 'pad_cfg_o' in module 'safe_domain' in file '../RTL/pulp/rtl/pulp/safe_domain.sv' on line 39. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 'spi_csn_i' in module 'safe_domain' in file '../RTL/pulp/rtl/pulp/safe_domain.sv' on line 71. Info : Processing multi-dimensional arrays. [CDFG-250] : Variable 'spi_oen_i' in module 'safe_domain' in file '../RTL/pulp/rtl/pulp/safe_domain.sv' on line 72. Warning : Maximum message print count reached. [MESG-11] : Maximum print count of '20' reached for message 'CDFG-250'. Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'pad_control' from file '../RTL/pulp/rtl/pulp/pad_control.sv'. Info : Unused module input port. [CDFG-500] : Input port 'pad_cfg_i[41]' is not used in module 'pad_control' in file '../RTL/pulp/rtl/pulp/pad_control.sv' on line 28. Info : Unused module input port. [CDFG-500] : Input port 'pad_cfg_i[42]' is not used in module 'pad_control' in file '../RTL/pulp/rtl/pulp/pad_control.sv' on line 28. Info : Unused module input port. [CDFG-500] : Input port 'pad_cfg_i[43]' is not used in module 'pad_control' in file '../RTL/pulp/rtl/pulp/pad_control.sv' on line 28. Info : Unused module input port. [CDFG-500] : Input port 'pad_cfg_i[44]' is not used in module 'pad_control' in file '../RTL/pulp/rtl/pulp/pad_control.sv' on line 28. Info : Unused module input port. [CDFG-500] : Input port 'pad_cfg_i[45]' is not used in module 'pad_control' in file '../RTL/pulp/rtl/pulp/pad_control.sv' on line 28. Info : Unused module input port. [CDFG-500] : Input port 'pad_cfg_i[46]' is not used in module 'pad_control' in file '../RTL/pulp/rtl/pulp/pad_control.sv' on line 28. Info : Unused module input port. [CDFG-500] : Input port 'pad_cfg_i[47]' is not used in module 'pad_control' in file '../RTL/pulp/rtl/pulp/pad_control.sv' on line 28. Info : Unused module input port. [CDFG-500] : Input port 'pad_cfg_i[48]' is not used in module 'pad_control' in file '../RTL/pulp/rtl/pulp/pad_control.sv' on line 28. Info : Unused module input port. [CDFG-500] : Input port 'pad_cfg_i[49]' is not used in module 'pad_control' in file '../RTL/pulp/rtl/pulp/pad_control.sv' on line 28. Info : Unused module input port. [CDFG-500] : Input port 'pad_cfg_i[50]' is not used in module 'pad_control' in file '../RTL/pulp/rtl/pulp/pad_control.sv' on line 28. Info : Unused module input port. [CDFG-500] : Input port 'pad_cfg_i[51]' is not used in module 'pad_control' in file '../RTL/pulp/rtl/pulp/pad_control.sv' on line 28. Warning : Maximum message print count reached. [MESG-11] : Maximum print count of '20' reached for message 'CDFG-500'. Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'rstgen' from file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/rstgen.sv'. Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'rstgen_bypass' from file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/rstgen_bypass.sv'. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'synch_regs_q' [4] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/rstgen_bypass.sv' on line 45. : Review and make sure the mismatch is intentional. Genus can possibly issue bitwidth mismatch warning for explicit assignments present in RTL as-well-as for implicit assignments inferred by the tool. For example, in case of enum declaration without value, the tool will implicitly assign value to the enum variables. It also issues the warning for any bitwidth mismatch that appears in this implicit assignment. Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=1 B=1 Z=1) at line 32 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/rstgen_bypass.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=1 B=1 Z=1) at line 32 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/rstgen_bypass.sv' will be considered in the following order: {'/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' (priority 1)} Info : Unused instance port. [ELABUTL-132] : Unused Port 'init_no' of instance 'i_rstgen' of module 'rstgen' inside module 'safe_domain' in file '../RTL/pulp/rtl/pulp/safe_domain.sv' on line 496. Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'soc_domain_CORE_TYPE0_USE_FPU1_USE_HWPE1_NB_CL_CORES8_AXI_ADDR_WIDTH32_AXI_DATA_IN_WIDTH64_AXI_DATA_OUT_WIDTH32_AXI_ID_IN_WIDTH32h00000007_AXI_ID_OUT_WIDTH32h00000005_AXI_USER_WIDTH6_AXI_STRB_IN_WIDTH8_AXI_STRB_OUT_WIDTH4_C2S_AW_WIDTH32h00000050_C2S_W_WIDTH79_C2S_B_WIDTH32h0000000f_C2S_AR_WIDTH32h0000004a_C2S_R_WIDTH32h00000050_S2C_AW_WIDTH32h0000004e_S2C_W_WIDTH43_S2C_B_WIDTH32h0000000d_S2C_AR_WIDTH32h00000048_S2C_R_WIDTH32h0000002e_BUFFER_WIDTH8_EVNT_WIDTH8_N_UART1_N_SPI1_N_I2C2' from file '../RTL/pulp/rtl/pulp/soc_domain.sv'. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'SEL_HARTS_FX' [1024] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/pulp_soc.sv' on line 244. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 'SEL_HARTS_FX' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/pulp_soc.sv' on line 244. Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'pulp_soc_CORE_TYPE0_USE_FPU1_USE_HWPE1_AXI_ADDR_WIDTH32_AXI_DATA_IN_WIDTH64_AXI_DATA_OUT_WIDTH32_AXI_ID_IN_WIDTH32h00000007_AXI_USER_WIDTH6_EVNT_WIDTH8_NB_CORES8_NGPIO32_NPAD64_NBIT_PADCFG6_NBIT_PADMUX2_N_UART1_N_SPI1_N_I2C2' from file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/pulp_soc.sv'. Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'axi_cdc_dst_LogDepth3_aw_chan_ttype_2_c2s_aw_chan_t_419_26_w_chan_ttype_2_c2s_w_chan_t_420_26_b_chan_ttype_2_c2s_b_chan_t_421_26_ar_chan_ttype_2_c2s_ar_chan_t_422_26_r_chan_ttype_2_c2s_r_chan_t_423_26_axi_req_ttype_2_c2s_req_t_438_25_axi_resp_ttype_2_c2s_resp_t_439_25' from file '../RTL/pulp/.bender/git/checkouts/axi-d42e23417b564294/src/axi_cdc_dst.sv'. Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'cdc_fifo_gray_dst_T_$t23_79_downto_0_unsigned_array_$unit_1__$t23_m3_0_LOG_DEPTH3' from file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'rptr_next' [4] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' on line 256. Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'gray_to_binary_N4' from file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/gray_to_binary.sv'. Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'binary_to_gray_N4' from file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/binary_to_gray.sv'. Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'sync_STAGES2' from file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/sync.sv'. Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'spill_register_T_$t23_79_downto_0_unsigned_array_$unit_1__$t23_m3_0' from file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/spill_register.sv'. Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'spill_register_flushable_T_$t23_79_downto_0_unsigned_array_$unit_1__$t23_m3_0_Bypass0' from file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/spill_register_flushable.sv'. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'a_full_q' [1] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/spill_register_flushable.sv' on line 51. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'b_full_q' [1] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/spill_register_flushable.sv' on line 70. Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/nequal_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'NE_UNS_OP' (pin widths: A=4 B=1 Z=1) at line 277 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'NE_UNS_OP' (pin widths: A=4 B=1 Z=1) at line 277 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/nequal_unsigned/implementations/very_fast' (priority 1)} Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/add_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'ADD_UNS_OP' (pin widths: A=4 B=1 Z=4) at line 256 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'ADD_UNS_OP' (pin widths: A=4 B=1 Z=4) at line 256 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/add_unsigned/implementations/very_fast' (priority 1), '/hdl_libraries/GB/components/add_unsigned/implementations/medium' (priority 1), '/hdl_libraries/GB/components/add_unsigned/implementations/slow' (priority 1)} Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'cdc_fifo_gray_dst_T_$t24_78_downto_0_unsigned_array_$unit_1__$t24_m3_0_LOG_DEPTH3' from file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'rptr_next' [4] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' on line 256. Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'spill_register_T_$t24_78_downto_0_unsigned_array_$unit_1__$t24_m3_0' from file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/spill_register.sv'. Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'spill_register_flushable_T_$t24_78_downto_0_unsigned_array_$unit_1__$t24_m3_0_Bypass0' from file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/spill_register_flushable.sv'. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'a_full_q' [1] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/spill_register_flushable.sv' on line 51. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'b_full_q' [1] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/spill_register_flushable.sv' on line 70. Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/nequal_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'NE_UNS_OP' (pin widths: A=4 B=1 Z=1) at line 277 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'NE_UNS_OP' (pin widths: A=4 B=1 Z=1) at line 277 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/nequal_unsigned/implementations/very_fast' (priority 1)} Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/add_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'ADD_UNS_OP' (pin widths: A=4 B=1 Z=4) at line 256 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'ADD_UNS_OP' (pin widths: A=4 B=1 Z=4) at line 256 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/add_unsigned/implementations/very_fast' (priority 1), '/hdl_libraries/GB/components/add_unsigned/implementations/medium' (priority 1), '/hdl_libraries/GB/components/add_unsigned/implementations/slow' (priority 1)} Info : Elaborating Subdesign. [ELAB-2] : Elaborating block 'cdc_fifo_gray_src_T_$t25_14_downto_0_unsigned_array_$unit_1__$t25_m3_0_LOG_DEPTH3' from file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'wptr_next' [4] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' on line 213. Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/nequal_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'NE_UNS_OP' (pin widths: A=4 B=4 Z=1) at line 223 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'NE_UNS_OP' (pin widths: A=4 B=4 Z=1) at line 223 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/nequal_unsigned/implementations/very_fast' (priority 1)} Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=1 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=1 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' (priority 1)} Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=1 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=1 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' (priority 1)} Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=2 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=2 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' (priority 1)} Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=2 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=2 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' (priority 1)} Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=3 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=3 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' (priority 1)} Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=3 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=3 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' (priority 1)} Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=3 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=3 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' (priority 1)} Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=3 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=3 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' (priority 1)} Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/add_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'ADD_UNS_OP' (pin widths: A=4 B=1 Z=4) at line 213 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'ADD_UNS_OP' (pin widths: A=4 B=1 Z=4) at line 213 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/add_unsigned/implementations/very_fast' (priority 1), '/hdl_libraries/GB/components/add_unsigned/implementations/medium' (priority 1), '/hdl_libraries/GB/components/add_unsigned/implementations/slow' (priority 1)} Warning : Maximum message print count reached. [MESG-11] : Maximum print count of '20' reached for message 'ELAB-2'. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'rptr_next' [4] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' on line 256. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'a_full_q' [1] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/spill_register_flushable.sv' on line 51. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'b_full_q' [1] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/spill_register_flushable.sv' on line 70. Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/nequal_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'NE_UNS_OP' (pin widths: A=4 B=1 Z=1) at line 277 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'NE_UNS_OP' (pin widths: A=4 B=1 Z=1) at line 277 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/nequal_unsigned/implementations/very_fast' (priority 1)} Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/add_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'ADD_UNS_OP' (pin widths: A=4 B=1 Z=4) at line 256 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'ADD_UNS_OP' (pin widths: A=4 B=1 Z=4) at line 256 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/add_unsigned/implementations/very_fast' (priority 1), '/hdl_libraries/GB/components/add_unsigned/implementations/medium' (priority 1), '/hdl_libraries/GB/components/add_unsigned/implementations/slow' (priority 1)} Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'wptr_next' [4] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' on line 213. Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/nequal_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'NE_UNS_OP' (pin widths: A=4 B=4 Z=1) at line 223 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'NE_UNS_OP' (pin widths: A=4 B=4 Z=1) at line 223 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/nequal_unsigned/implementations/very_fast' (priority 1)} Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=1 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=1 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' (priority 1)} Info : An implementation was inferred. [CWD-19] : The implementation '/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=1 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv'. Info : Sorted the set of valid implementations for synthetic operator. [CWD-36] : The implementations for the call to synthetic operator 'EQ_UNS_OP' (pin widths: A=3 B=1 Z=1) at line 197 in the file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' will be considered in the following order: {'/hdl_libraries/GB/components/equal_unsigned/implementations/very_fast' (priority 1)} Warning : Maximum message print count reached. [MESG-11] : Maximum print count of '20' reached for message 'CWD-19'. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'wptr_next' [4] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' on line 213. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'wptr_next' [4] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' on line 213. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'rptr_next' [4] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' on line 256. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'a_full_q' [1] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/spill_register_flushable.sv' on line 51. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'b_full_q' [1] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/spill_register_flushable.sv' on line 70. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'wptr_next' [4] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' on line 213. Info : Bitwidth mismatch in assignment. [CDFG-372] : Width of left hand side 'rptr_next' [4] doesn't match the width of right hand side [32] in assignment in file '../RTL/pulp/.bender/git/checkouts/common_cells-f18d75f6d6d026a5/src/cdc_fifo_gray.sv' on line 256. Warning : Maximum message print count reached. [MESG-11] : Maximum print count of '20' reached for message 'CDFG-372'. Renamed blackbox module 'xpm_memory_spram' of instance 'i_xpm_memory_spram' to 'xpm_memory_spram_ADDR_WIDTH_A15_AUTO_SLEEP_TIME0_BYTE_WRITE_WIDTH_A8_ECC_MODEx6e6f5f656363_MEMORY_INIT_FILE1852796517_MEMORY_INIT_PARAM48_MEMORY_OPTIMIZATION1953658213_MEMORY_PRIMITIVE1635087471_MEMORY_SIZE1048576_MESSAGE_CONTROL0_READ_DATA_WIDTH_A32_READ_LATENCY_A1_READ_RESET_VALUE_A48_USE_MEM_INIT1_WAKEUP_TIMEx64697361626c655f736c656570_WRITE_DATA_WIDTH_A32_WRITE_MODE_Ax6e6f5f6368616e6765' to include generic names. This is different from LEC behavior which does not include generic names for blackbox modules. Warning : In legacy_ui mode, Genus creates a blackbox as description for a module is not found. Black boxes represent unresolved references in the design and are usually not expected. Another possible reason is, some libraries are not read and the tool could not get the content for some macros or lib_cells. [CDFG-428] : A blackbox was created for instance 'i_xpm_memory_spram' in file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/fpga/tc_sram_xilinx.sv' on line 92. Info : Unused instance port. [ELABUTL-132] : Unused Port 'dbiterra' of instance 'gen_1_ports.i_xpm_memory_spram' of module 'xpm_memory_spram_ADDR_WIDTH_A15_AUTO_SLEEP_TIME0_BYTE_WRITE_WIDTH_A8_ECC_MODEx6e6f5f656363_MEMORY_INIT_FILE1852796517_MEMORY_INIT_PARAM48_MEMORY_OPTIMIZATION1953658213_MEMORY_PRIMITIVE1635087471_MEMORY_SIZE1048576_MESSAGE_CONTROL0_READ_DATA_WIDTH_A32_READ_LATENCY_A1_READ_RESET_VALUE_A48_USE_MEM_INIT1_WAKEUP_TIMEx64697361626c655f736c656570_WRITE_DATA_WIDTH_A32_WRITE_MODE_Ax6e6f5f6368616e6765' inside module 'tc_sram_NumWords32768_DataWidth32_NumPorts1' in file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/fpga/tc_sram_xilinx.sv' on line 92. Info : Unused instance port. [ELABUTL-132] : Unused Port 'sbiterra' of instance 'gen_1_ports.i_xpm_memory_spram' of module 'xpm_memory_spram_ADDR_WIDTH_A15_AUTO_SLEEP_TIME0_BYTE_WRITE_WIDTH_A8_ECC_MODEx6e6f5f656363_MEMORY_INIT_FILE1852796517_MEMORY_INIT_PARAM48_MEMORY_OPTIMIZATION1953658213_MEMORY_PRIMITIVE1635087471_MEMORY_SIZE1048576_MESSAGE_CONTROL0_READ_DATA_WIDTH_A32_READ_LATENCY_A1_READ_RESET_VALUE_A48_USE_MEM_INIT1_WAKEUP_TIMEx64697361626c655f736c656570_WRITE_DATA_WIDTH_A32_WRITE_MODE_Ax6e6f5f6368616e6765' inside module 'tc_sram_NumWords32768_DataWidth32_NumPorts1' in file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/fpga/tc_sram_xilinx.sv' on line 92. Renamed blackbox module 'xpm_memory_spram' of instance 'i_xpm_memory_spram' to 'xpm_memory_spram_ADDR_WIDTH_A13_AUTO_SLEEP_TIME0_BYTE_WRITE_WIDTH_A8_ECC_MODEx6e6f5f656363_MEMORY_INIT_FILE1852796517_MEMORY_INIT_PARAM48_MEMORY_OPTIMIZATION1953658213_MEMORY_PRIMITIVE1635087471_MEMORY_SIZE262144_MESSAGE_CONTROL0_READ_DATA_WIDTH_A32_READ_LATENCY_A1_READ_RESET_VALUE_A48_USE_MEM_INIT1_WAKEUP_TIMEx64697361626c655f736c656570_WRITE_DATA_WIDTH_A32_WRITE_MODE_Ax6e6f5f6368616e6765' to include generic names. This is different from LEC behavior which does not include generic names for blackbox modules. Warning : In legacy_ui mode, Genus creates a blackbox as description for a module is not found. Black boxes represent unresolved references in the design and are usually not expected. Another possible reason is, some libraries are not read and the tool could not get the content for some macros or lib_cells. [CDFG-428] : A blackbox was created for instance 'i_xpm_memory_spram' in file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/fpga/tc_sram_xilinx.sv' on line 92. Info : Unused instance port. [ELABUTL-132] : Unused Port 'dbiterra' of instance 'gen_1_ports.i_xpm_memory_spram' of module 'xpm_memory_spram_ADDR_WIDTH_A13_AUTO_SLEEP_TIME0_BYTE_WRITE_WIDTH_A8_ECC_MODEx6e6f5f656363_MEMORY_INIT_FILE1852796517_MEMORY_INIT_PARAM48_MEMORY_OPTIMIZATION1953658213_MEMORY_PRIMITIVE1635087471_MEMORY_SIZE262144_MESSAGE_CONTROL0_READ_DATA_WIDTH_A32_READ_LATENCY_A1_READ_RESET_VALUE_A48_USE_MEM_INIT1_WAKEUP_TIMEx64697361626c655f736c656570_WRITE_DATA_WIDTH_A32_WRITE_MODE_Ax6e6f5f6368616e6765' inside module 'tc_sram_NumWords8192_DataWidth32_NumPorts1_Latency1' in file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/fpga/tc_sram_xilinx.sv' on line 92. Info : Unused instance port. [ELABUTL-132] : Unused Port 'sbiterra' of instance 'gen_1_ports.i_xpm_memory_spram' of module 'xpm_memory_spram_ADDR_WIDTH_A13_AUTO_SLEEP_TIME0_BYTE_WRITE_WIDTH_A8_ECC_MODEx6e6f5f656363_MEMORY_INIT_FILE1852796517_MEMORY_INIT_PARAM48_MEMORY_OPTIMIZATION1953658213_MEMORY_PRIMITIVE1635087471_MEMORY_SIZE262144_MESSAGE_CONTROL0_READ_DATA_WIDTH_A32_READ_LATENCY_A1_READ_RESET_VALUE_A48_USE_MEM_INIT1_WAKEUP_TIMEx64697361626c655f736c656570_WRITE_DATA_WIDTH_A32_WRITE_MODE_Ax6e6f5f6368616e6765' inside module 'tc_sram_NumWords8192_DataWidth32_NumPorts1_Latency1' in file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/fpga/tc_sram_xilinx.sv' on line 92. Renamed blackbox module 'generic_rom' of instance 'rom_mem_i' to 'generic_rom_ADDR_WIDTH11_DATA_WIDTH32' to include generic names. This is different from LEC behavior which does not include generic names for blackbox modules. Warning : In legacy_ui mode, Genus creates a blackbox as description for a module is not found. Black boxes represent unresolved references in the design and are usually not expected. Another possible reason is, some libraries are not read and the tool could not get the content for some macros or lib_cells. [CDFG-428] : A blackbox was created for instance 'rom_mem_i' in file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/boot_rom.sv' on line 46. Info : Unused instance port. [ELABUTL-132] : Unused Port 'serial_o' of instance 'i_ref_clk_sync' of module 'pulp_sync_wedge' inside module 'soc_peripherals_MEM_ADDR_WIDTH17_APB_ADDR_WIDTH32_APB_DATA_WIDTH32_NB_CORES8_NB_CLUSTERS1_EVNT_WIDTH8_NGPIO32_NPAD64_NBIT_PADCFG6_NBIT_PADMUX2_N_UART32h00000001_N_SPI32h00000001_N_I2C32h00000002_apb_slave_APB_BUS_Slave_apb_eu_master_APB_BUS_Master_apb_hwpe_master_APB_BUS_Master_apb_debug_master_APB_BUS_Master_l2_rx_master_XBAR_TCDM_BUS_Master_l2_tx_master_XBAR_TCDM_BUS_Master_soc_fll_master_FLL_BUS_out_per_fll_master_FLL_BUS_out_cluster_fll_master_FLL_BUS_out' in file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/soc_peripherals.sv' on line 250. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_fll_if-30645ac88ad7542f/src/apb_fll_if.sv' on line 412. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_fll_if-30645ac88ad7542f/src/apb_fll_if.sv' on line 408. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_fll_if-30645ac88ad7542f/src/apb_fll_if.sv' on line 416. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_fll_if-30645ac88ad7542f/src/apb_fll_if.sv' on line 408. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_fll_if-30645ac88ad7542f/src/apb_fll_if.sv' on line 349. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_fll_if-30645ac88ad7542f/src/apb_fll_if.sv' on line 294. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'apb_fll_if_APB_ADDR_WIDTH32' in file '../RTL/pulp/.bender/git/checkouts/apb_fll_if-30645ac88ad7542f/src/apb_fll_if.sv' on line 349. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'apb_fll_if_APB_ADDR_WIDTH32' in file '../RTL/pulp/.bender/git/checkouts/apb_fll_if-30645ac88ad7542f/src/apb_fll_if.sv' on line 294. Info : Unused instance port. [ELABUTL-132] : Unused Port 'bbgen_req_o' of instance 'apb_fll_if_i' of module 'apb_fll_if_APB_ADDR_WIDTH32' inside module 'soc_peripherals_MEM_ADDR_WIDTH17_APB_ADDR_WIDTH32_APB_DATA_WIDTH32_NB_CORES8_NB_CLUSTERS1_EVNT_WIDTH8_NGPIO32_NPAD64_NBIT_PADCFG6_NBIT_PADMUX2_N_UART32h00000001_N_SPI32h00000001_N_I2C32h00000002_apb_slave_APB_BUS_Slave_apb_eu_master_APB_BUS_Master_apb_hwpe_master_APB_BUS_Master_apb_debug_master_APB_BUS_Master_l2_rx_master_XBAR_TCDM_BUS_Master_l2_tx_master_XBAR_TCDM_BUS_Master_soc_fll_master_FLL_BUS_out_per_fll_master_FLL_BUS_out_cluster_fll_master_FLL_BUS_out' in file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/soc_peripherals.sv' on line 306. Info : Unused instance port. [ELABUTL-132] : Unused Port 'bbgen_wrn_o' of instance 'apb_fll_if_i' of module 'apb_fll_if_APB_ADDR_WIDTH32' inside module 'soc_peripherals_MEM_ADDR_WIDTH17_APB_ADDR_WIDTH32_APB_DATA_WIDTH32_NB_CORES8_NB_CLUSTERS1_EVNT_WIDTH8_NGPIO32_NPAD64_NBIT_PADCFG6_NBIT_PADMUX2_N_UART32h00000001_N_SPI32h00000001_N_I2C32h00000002_apb_slave_APB_BUS_Slave_apb_eu_master_APB_BUS_Master_apb_hwpe_master_APB_BUS_Master_apb_debug_master_APB_BUS_Master_l2_rx_master_XBAR_TCDM_BUS_Master_l2_tx_master_XBAR_TCDM_BUS_Master_soc_fll_master_FLL_BUS_out_per_fll_master_FLL_BUS_out_cluster_fll_master_FLL_BUS_out' in file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/soc_peripherals.sv' on line 306. Info : Unused instance port. [ELABUTL-132] : Unused Port 'bbgen_sel_o' of instance 'apb_fll_if_i' of module 'apb_fll_if_APB_ADDR_WIDTH32' inside module 'soc_peripherals_MEM_ADDR_WIDTH17_APB_ADDR_WIDTH32_APB_DATA_WIDTH32_NB_CORES8_NB_CLUSTERS1_EVNT_WIDTH8_NGPIO32_NPAD64_NBIT_PADCFG6_NBIT_PADMUX2_N_UART32h00000001_N_SPI32h00000001_N_I2C32h00000002_apb_slave_APB_BUS_Slave_apb_eu_master_APB_BUS_Master_apb_hwpe_master_APB_BUS_Master_apb_debug_master_APB_BUS_Master_l2_rx_master_XBAR_TCDM_BUS_Master_l2_tx_master_XBAR_TCDM_BUS_Master_soc_fll_master_FLL_BUS_out_per_fll_master_FLL_BUS_out_cluster_fll_master_FLL_BUS_out' in file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/soc_peripherals.sv' on line 306. Info : Unused instance port. [ELABUTL-132] : Unused Port 'bbgen_data_o' of instance 'apb_fll_if_i' of module 'apb_fll_if_APB_ADDR_WIDTH32' inside module 'soc_peripherals_MEM_ADDR_WIDTH17_APB_ADDR_WIDTH32_APB_DATA_WIDTH32_NB_CORES8_NB_CLUSTERS1_EVNT_WIDTH8_NGPIO32_NPAD64_NBIT_PADCFG6_NBIT_PADMUX2_N_UART32h00000001_N_SPI32h00000001_N_I2C32h00000002_apb_slave_APB_BUS_Slave_apb_eu_master_APB_BUS_Master_apb_hwpe_master_APB_BUS_Master_apb_debug_master_APB_BUS_Master_l2_rx_master_XBAR_TCDM_BUS_Master_l2_tx_master_XBAR_TCDM_BUS_Master_soc_fll_master_FLL_BUS_out_per_fll_master_FLL_BUS_out_cluster_fll_master_FLL_BUS_out' in file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/soc_peripherals.sv' on line 306. Info : Unused instance port. [ELABUTL-132] : Unused Port 'bbgen_ack_i' of instance 'apb_fll_if_i' of module 'apb_fll_if_APB_ADDR_WIDTH32' inside module 'soc_peripherals_MEM_ADDR_WIDTH17_APB_ADDR_WIDTH32_APB_DATA_WIDTH32_NB_CORES8_NB_CLUSTERS1_EVNT_WIDTH8_NGPIO32_NPAD64_NBIT_PADCFG6_NBIT_PADMUX2_N_UART32h00000001_N_SPI32h00000001_N_I2C32h00000002_apb_slave_APB_BUS_Slave_apb_eu_master_APB_BUS_Master_apb_hwpe_master_APB_BUS_Master_apb_debug_master_APB_BUS_Master_l2_rx_master_XBAR_TCDM_BUS_Master_l2_tx_master_XBAR_TCDM_BUS_Master_soc_fll_master_FLL_BUS_out_per_fll_master_FLL_BUS_out_cluster_fll_master_FLL_BUS_out' in file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/pulp_soc/soc_peripherals.sv' on line 306. Warning : Maximum message print count reached. [MESG-11] : Maximum print count of '20' reached for message 'ELABUTL-132'. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[32]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. : Genus removes the flip-flop or latch inferred for an unused signal or variable. To preserve the flip-flop or latch, set the hdl_preserve_unused_registers attribute to true or use a pragma in the RTL. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[33]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[34]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[35]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[36]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[37]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[38]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[39]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[40]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[41]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[42]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[43]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[44]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[45]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[46]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[47]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[48]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[49]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[50]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Removing unused register. [CDFG-508] : Removing unused latch register 's_gpio_inttype[51]' in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 72. Warning : Maximum message print count reached. [MESG-11] : Maximum print count of '20' reached for message 'CDFG-508'. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 181. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 215. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 547. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 190. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 567. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 216. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 587. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 217. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 607. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 637. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 647. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 218. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 158. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 667. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 687. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 737. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 747. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 757. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 767. Info : Replaced logic with a constant value. [CDFG-771] : Constant Replacement in Module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 191. Warning : Maximum message print count reached. [MESG-11] : Maximum print count of '20' reached for message 'CDFG-771'. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 316. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 302. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 316. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 302. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 316. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 302. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 316. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 302. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 316. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 302. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 316. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 302. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 316. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 302. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 316. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 302. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 316. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 302. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 316. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 302. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 316. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 302. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 316. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 302. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 316. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 302. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 316. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 302. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 316. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 302. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 316. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 302. Info : Common subexpression eliminated. [CDFG-738] : Eliminated '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 316. Info : Common subexpression kept. [CDFG-739] : Kept '%bit-select%' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 302. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'apb_gpio_APB_ADDR_WIDTH32_PAD_NUM32_NBIT_PADCFG6' in file '../RTL/pulp/.bender/git/checkouts/apb_gpio-9fda9c183aaff2a3/rtl/apb_gpio.sv' on line 276. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'udma_ch_addrgen_L2_AWIDTH_NOAL19_TRANS_SIZE20_STREAM_ID_WIDTH1' in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_ch_addrgen.sv' on line 123. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Sign mismatch in assignment. [CDFG-373] : Assignment has unsigned left hand side 's_grant_log' and signed right hand side in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 259. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'udma_tx_channels_L2_AWIDTH_NOAL19_L2_DATA_WIDTH32_DATA_WIDTH32_N_LIN_CHANNELS32h00000012_N_EXT_CHANNELS3_TRANS_SIZE20' in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 258. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'udma_tx_channels_L2_AWIDTH_NOAL19_L2_DATA_WIDTH32_DATA_WIDTH32_N_LIN_CHANNELS32h00000012_N_EXT_CHANNELS3_TRANS_SIZE20' in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_tx_channels.sv' on line 384. Warning : Unreachable statements for case item. [CDFG-472] : Case item 'default' in module 'udma_stream_unit_L2_AWIDTH_NOAL19_STREAM_ID_WIDTH1_INST_ID0' in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_stream_unit.sv' on line 154. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'udma_stream_unit_L2_AWIDTH_NOAL19_STREAM_ID_WIDTH1_INST_ID0' in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_stream_unit.sv' on line 154. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'udma_rx_channels_TRANS_SIZE20_L2_DATA_WIDTH32_L2_AWIDTH_NOAL19_DATA_WIDTH32_STREAM_ID_WIDTH1_N_STREAMS1_N_LIN_CHANNELS32h00000010_N_EXT_CHANNELS1' in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_rx_channels.sv' on line 603. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'udma_rx_channels_TRANS_SIZE20_L2_DATA_WIDTH32_L2_AWIDTH_NOAL19_DATA_WIDTH32_STREAM_ID_WIDTH1_N_STREAMS1_N_LIN_CHANNELS32h00000010_N_EXT_CHANNELS1' in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_rx_channels.sv' on line 484. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'udma_rx_channels_TRANS_SIZE20_L2_DATA_WIDTH32_L2_AWIDTH_NOAL19_DATA_WIDTH32_STREAM_ID_WIDTH1_N_STREAMS1_N_LIN_CHANNELS32h00000010_N_EXT_CHANNELS1' in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/core/udma_rx_channels.sv' on line 385. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'udma_uart_reg_if_L2_AWIDTH_NOAL19_TRANS_SIZE20' in file '../RTL/pulp/.bender/git/checkouts/udma_uart-987a5c3aaae1cf57/rtl/udma_uart_reg_if.sv' on line 271. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'udma_uart_tx' in file '../RTL/pulp/.bender/git/checkouts/udma_uart-987a5c3aaae1cf57/rtl/udma_uart_tx.sv' on line 81. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'udma_uart_tx' in file '../RTL/pulp/.bender/git/checkouts/udma_uart-987a5c3aaae1cf57/rtl/udma_uart_tx.sv' on line 59. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'udma_uart_rx' in file '../RTL/pulp/.bender/git/checkouts/udma_uart-987a5c3aaae1cf57/rtl/udma_uart_rx.sv' on line 72. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'udma_uart_rx' in file '../RTL/pulp/.bender/git/checkouts/udma_uart-987a5c3aaae1cf57/rtl/udma_uart_rx.sv' on line 99. Warning : In legacy_ui mode, Genus creates a blackbox as description for a module is not found. Black boxes represent unresolved references in the design and are usually not expected. Another possible reason is, some libraries are not read and the tool could not get the content for some macros or lib_cells. [CDFG-428] : A blackbox was created for instance 'i_BUFGMUX' in file '../RTL/pulp/.bender/git/checkouts/tech_cells_generic-6a4b27e0e56cbcda/src/fpga/tc_clk_xilinx.sv' on line 60. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'udma_clkgen' in file '../RTL/pulp/.bender/git/checkouts/udma_core-25b62500cd51a5c6/rtl/common/udma_clkgen.sv' on line 116. Warning : Unreachable statements for case item. [CDFG-472] : Case item 'default' in module 'udma_spim_ctrl_REPLAY_BUFFER_DEPTH6' in file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_ctrl.sv' on line 637. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'udma_spim_ctrl_REPLAY_BUFFER_DEPTH6' in file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_ctrl.sv' on line 483. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'udma_spim_ctrl_REPLAY_BUFFER_DEPTH6' in file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_ctrl.sv' on line 222. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'udma_spim_ctrl_REPLAY_BUFFER_DEPTH6' in file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_ctrl.sv' on line 422. Info : Identified sum-of-products logic to be optimized during syn_generic. [CDFG-769] : Sum-of-products logic in module 'udma_spim_ctrl_REPLAY_BUFFER_DEPTH6' in file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_ctrl.sv' on line 296. Info : Concatenated adjacent array write data. [CDFG-914] : Concatenated data nodes 'spi_sdi1_i' and 'spi_sdi2_i' in file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_txrx.sv' on line 247. Info : Merged adjacent array writes. [CDFG-896] : Merged adjacent writes to array 's_data_rx' in module 'udma_spim_txrx' in file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_txrx.sv' on line 250. Info : Concatenated adjacent array write data. [CDFG-914] : Concatenated data nodes 'spi_sdi1_i' and 'spi_sdi3_i' in file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_txrx.sv' on line 247. Info : Merged adjacent array writes. [CDFG-896] : Merged adjacent writes to array 's_data_rx' in module 'udma_spim_txrx' in file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_txrx.sv' on line 250. Info : Concatenated adjacent array write data. [CDFG-914] : Concatenated data nodes 'spi_sdi1_i' and 'spi_sdi2_i' in file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_txrx.sv' on line 247. Info : Merged adjacent array writes. [CDFG-896] : Merged adjacent writes to array 's_data_rx' in module 'udma_spim_txrx' in file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_txrx.sv' on line 257. Info : Concatenated adjacent array write data. [CDFG-914] : Concatenated data nodes 'spi_sdi1_i' and 'spi_sdi3_i' in file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_txrx.sv' on line 247. Info : Merged adjacent array writes. [CDFG-896] : Merged adjacent writes to array 's_data_rx' in module 'udma_spim_txrx' in file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_txrx.sv' on line 257. Info : The optimization to merge adjacent array writes was done. [CDFG-897] : Merging of adjacent array writes done in module 'udma_spim_txrx' source file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_txrx.sv'. Info : Optimized the MUX created for array read / write or variable shifter. [CDFG-893] : Optimized mux for Array Write for variable 'N173846' at line 250 col 17, in Module 'udma_spim_txrx' in file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_txrx.sv' on line 250. Info : Optimized the MUX created for array read / write or variable shifter. [CDFG-893] : Optimized mux for Array Write for variable 'N173911' at line 257 col 17, in Module 'udma_spim_txrx' in file '../RTL/pulp/.bender/git/checkouts/udma_qspi-ad1b15dd0651b0f6/rtl/udma_spim_txrx.sv' on line 257. Warning : Unreachable statements for case item. [CDFG-472] : Case item 'default' in module 'varcic_STAGES5_ACC_WIDTH51' in file '../RTL/pulp/.bender/git/checkouts/udma_i2s-4c2d946afbfb2209/rtl/cic_top.sv' on line 138. Info : Skipping an invalid binding for a subprogram call. [CWD-21] : The binding '/hdl_libraries/CW/components/CW_mult_unsigned/bindings/b1' is invalid for the call to synthetic operator 'MULT_UNS_OP' (pin widths: A=8 B=8 Z=16) at line 129 in the file '../RTL/pulp/.bender/git/checkouts/udma_camera-86b8118519db0f98/rtl/camera_if.sv' because the 'avoid' attribute on the binding is set to 'true'. Info : Skipping an invalid binding for a subprogram call. [CWD-21] : The binding '/hdl_libraries/CW/components/CW_mult_signed/bindings/b1' is invalid for the call to synthetic operator 'MULT_TC_OP' (pin widths: A=32 B=32 Z=64) at line 148 in the file '../RTL/pulp/.bender/git/checkouts/udma_filter-a40516c05ed4bf59/rtl/udma_filter_au.sv' because the 'avoid' attribute on the binding is set to 'true'. Info : Skip related conditional write and read sequence. [CDFG-773] : For variable 'cur_length' in Module 'hyper_twd_trans_spliter_L2_AWIDTH_NOAL19_ID_WIDTH3_DELAY_BIT_WIDTH3_TRANS_SIZE20' in file '../RTL/pulp/.bender/git/checkouts/udma_hyper-0e2eefc5c5ed37ee/udma-hyperbus/src/hyper_twd_trans_spliter.sv' on line 228. Warning : Generated logic differs from the expected logic. [CDFG2G-615] : Signal 'r_sel_hyper_axi' in module 'apb_soc_ctrl_APB_ADDR_WIDTH32_NB_CLUSTERS1_NB_CORES8_NBIT_PADCFG6' modeled as latch instead of flip-flop in file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/components/apb_soc_ctrl.sv' on line 183, column 9. : The logic generated for an always_comb, always_latch or always_ff process may not match the behavior specified in the input HDL. Info : Latch inferred. Check and revisit your RTL if this is not the intended behavior. [CDFG2G-616] : Latch inferred for variable 'r_sel_hyper_axi' in file '../RTL/pulp/.bender/git/checkouts/pulp_soc-c519334bd3ac5582/rtl/components/apb_soc_ctrl.sv' on line 183, column 9. : Use the attributes 'set_attribute hdl_error_on_latch true'(LUI) or 'set_db hdl_error_on_latch true' (CUI) to issue an error when a latch is inferred. Use the attributes 'set_attributes hdl_latch_keep_feedback true'(LUI) or 'set_db hdl_latch_keep_feedback true'(CUI) to infer combinational logic rather than a latch in case a variable is explicitly assigned to itself. Info : A negative value is used for the bounds in an array declaration. [CDFG-488] : Negative value used in the bounds while declaring 'apu_master_type_o' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_core.sv' on line 101. : Some tools may not support negative values in array bounds. Info : A negative value is used for the bounds in an array declaration. [CDFG-488] : Negative value used in the bounds while declaring 'apu_type_ex' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_core.sv' on line 212. Warning : Unreachable statements for case item. [CDFG-472] : Case item 'default' in module 'riscv_if_stage_N_HWLP2_RDATA_WIDTH32_FPU1_DM_HaltAddress32h1a110800' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_if_stage.sv' on line 134. Warning : Unreachable statements for case item. [CDFG-472] : Case item 'default' in module 'riscv_if_stage_N_HWLP2_RDATA_WIDTH32_FPU1_DM_HaltAddress32h1a110800' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_if_stage.sv' on line 153. Warning : Unreachable statements for case item. [CDFG-472] : Case item 'default' in module 'riscv_if_stage_N_HWLP2_RDATA_WIDTH32_FPU1_DM_HaltAddress32h1a110800' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_if_stage.sv' on line 258. Info : Skip related conditional write and read sequence. [CDFG-773] : For variable 'hwlp_targ_addr_o' in Module 'riscv_hwloop_controller_N_REGS2' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_hwloop_controller.sv' on line 93. Info : Skip related conditional write and read sequence. [CDFG-773] : For variable 'hwlp_targ_addr_o' in Module 'riscv_hwloop_controller_N_REGS2' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_hwloop_controller.sv' on line 87. Info : A negative value is used for the bounds in an array declaration. [CDFG-488] : Negative value used in the bounds while declaring 'apu_type_ex_o' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_id_stage.sv' on line 154. Info : A negative value is used for the bounds in an array declaration. [CDFG-488] : Negative value used in the bounds while declaring 'apu_type' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_id_stage.sv' on line 361. Info : A negative value is used for the bounds in an array declaration. [CDFG-488] : Negative value used in the bounds while declaring 'apu_flags_src' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_id_stage.sv' on line 373. Warning : Unreachable statements for case item. [CDFG-472] : Case item 'default' in module 'riscv_id_stage_N_HWLP2_PULP_SECURE1_APU1_FPU1_Zfinx1_FP_DIVSQRT1_SHARED_FP0_SHARED_DSP_MULT0_SHARED_INT_MULT0_SHARED_INT_DIV0_SHARED_FP_DIVSQRT2_WAPUTYPE0_APU_NARGS_CPU3_APU_WOP_CPU6_APU_NDSFLAGS_CPU15_APU_NUSFLAGS_CPU5' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_id_stage.sv' on line 503. Warning : Unreachable statements for case item. [CDFG-472] : Case item 'default' in module 'riscv_id_stage_N_HWLP2_PULP_SECURE1_APU1_FPU1_Zfinx1_FP_DIVSQRT1_SHARED_FP0_SHARED_DSP_MULT0_SHARED_INT_MULT0_SHARED_INT_DIV0_SHARED_FP_DIVSQRT2_WAPUTYPE0_APU_NARGS_CPU3_APU_WOP_CPU6_APU_NDSFLAGS_CPU15_APU_NUSFLAGS_CPU5' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_id_stage.sv' on line 642. Warning : Unreachable statements for case item. [CDFG-472] : Case item 'default' in module 'riscv_id_stage_N_HWLP2_PULP_SECURE1_APU1_FPU1_Zfinx1_FP_DIVSQRT1_SHARED_FP0_SHARED_DSP_MULT0_SHARED_INT_MULT0_SHARED_INT_DIV0_SHARED_FP_DIVSQRT2_WAPUTYPE0_APU_NARGS_CPU3_APU_WOP_CPU6_APU_NDSFLAGS_CPU15_APU_NUSFLAGS_CPU5' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_id_stage.sv' on line 781. Warning : Unreachable statements for case item. [CDFG-472] : Case item 'default' in module 'riscv_id_stage_N_HWLP2_PULP_SECURE1_APU1_FPU1_Zfinx1_FP_DIVSQRT1_SHARED_FP0_SHARED_DSP_MULT0_SHARED_INT_MULT0_SHARED_INT_DIV0_SHARED_FP_DIVSQRT2_WAPUTYPE0_APU_NARGS_CPU3_APU_WOP_CPU6_APU_NDSFLAGS_CPU15_APU_NUSFLAGS_CPU5' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_id_stage.sv' on line 788. Warning : Unreachable statements for case item. [CDFG-472] : Case item 'default' in module 'riscv_id_stage_N_HWLP2_PULP_SECURE1_APU1_FPU1_Zfinx1_FP_DIVSQRT1_SHARED_FP0_SHARED_DSP_MULT0_SHARED_INT_MULT0_SHARED_INT_DIV0_SHARED_FP_DIVSQRT2_WAPUTYPE0_APU_NARGS_CPU3_APU_WOP_CPU6_APU_NDSFLAGS_CPU15_APU_NUSFLAGS_CPU5' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_id_stage.sv' on line 798. Warning : Unreachable statements for case item. [CDFG-472] : Case item 'default' in module 'riscv_id_stage_N_HWLP2_PULP_SECURE1_APU1_FPU1_Zfinx1_FP_DIVSQRT1_SHARED_FP0_SHARED_DSP_MULT0_SHARED_INT_MULT0_SHARED_INT_DIV0_SHARED_FP_DIVSQRT2_WAPUTYPE0_APU_NARGS_CPU3_APU_WOP_CPU6_APU_NDSFLAGS_CPU15_APU_NUSFLAGS_CPU5' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_id_stage.sv' on line 805. Warning : Unreachable statements for case item. [CDFG-472] : Case item 'default' in module 'riscv_id_stage_N_HWLP2_PULP_SECURE1_APU1_FPU1_Zfinx1_FP_DIVSQRT1_SHARED_FP0_SHARED_DSP_MULT0_SHARED_INT_MULT0_SHARED_INT_DIV0_SHARED_FP_DIVSQRT2_WAPUTYPE0_APU_NARGS_CPU3_APU_WOP_CPU6_APU_NDSFLAGS_CPU15_APU_NUSFLAGS_CPU5' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_id_stage.sv' on line 816. Warning : Unreachable statements for case item. [CDFG-472] : Case item 'default' in module 'riscv_id_stage_N_HWLP2_PULP_SECURE1_APU1_FPU1_Zfinx1_FP_DIVSQRT1_SHARED_FP0_SHARED_DSP_MULT0_SHARED_INT_MULT0_SHARED_INT_DIV0_SHARED_FP_DIVSQRT2_WAPUTYPE0_APU_NARGS_CPU3_APU_WOP_CPU6_APU_NDSFLAGS_CPU15_APU_NUSFLAGS_CPU5' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_id_stage.sv' on line 842. Error : Index out of range. [CDFG-220] [elaborate] : Index 'we_b_dec[32]' is not within the valid range of the declaration '[31:0] we_b_dec' in module 'riscv_register_file_ADDR_WIDTH6_DATA_WIDTH32_FPU1_Zfinx1' in file '../RTL/pulp/.bender/git/checkouts/cv32e40p-0a3884e05ea5a482/rtl/riscv_register_file.sv' on line 171. : Correct the index or the range in the HDL. Info : Deleting HDL design. [CDFG-305] : Design 'riscv_register_file_ADDR_WIDTH6_DATA_WIDTH32_FPU1_Zfinx1'. : Designs are often deleted because of elaboration errors. Look for previous errors and try to resolve them. Info : Deleting HDL design. [CDFG-305] : Design 'register_file_test_wrap_ADDR_WIDTH6_FPU1_Zfinx1'. Info : Deleting HDL design. [CDFG-305] : Design 'riscv_id_stage_N_HWLP2_PULP_SECURE1_APU1_FPU1_Zfinx1_FP_DIVSQRT1_SHARED_FP0_SHARED_DSP_MULT0_SHARED_INT_MULT0_SHARED_INT_DIV0_SHARED_FP_DIVSQRT2_WAPUTYPE0_APU_NARGS_CPU3_APU_WOP_CPU6_APU_NDSFLAGS_CPU15_APU_NUSFLAGS_CPU5'. Info : Deleting HDL design. [CDFG-305] : Design 'riscv_core_N_EXT_PERF_COUNTERS1_PULP_SECURE1_PULP_CLUSTER0_FPU1_Zfinx1_FP_DIVSQRT1_SHARED_FP0_SHARED_FP_DIVSQRT2'. Info : Deleting HDL design. [CDFG-305] : Design 'riscv_if_stage_N_HWLP2_RDATA_WIDTH32_FPU1_DM_HaltAddress32h1a110800'. Info : Deleting HDL design. [CDFG-305] : Design 'fc_subsystem_CORE_TYPE0_USE_FPU1_USE_HWPE1_CORE_ID4h0_CLUSTER_ID6h1f_USE_ZFINX1_l2_data_master_XBAR_TCDM_BUS_Master_l2_instr_master_XBAR_TCDM_BUS_Master_l2_hwpe_master_XBAR_TCDM_BUS_Master_apb_slave_eu_APB_BUS_Slave_apb_slave_hwpe_APB_BUS_Slave'. Info : Deleting HDL design. [CDFG-305] : Design 'pulp_soc_CORE_TYPE0_USE_FPU1_USE_HWPE1_AXI_ADDR_WIDTH32_AXI_DATA_IN_WIDTH64_AXI_DATA_OUT_WIDTH32_AXI_ID_IN_WIDTH32h00000007_AXI_USER_WIDTH6_EVNT_WIDTH8_NB_CORES8_NGPIO32_NPAD64_NBIT_PADCFG6_NBIT_PADMUX2_N_UART1_N_SPI1_N_I2C2'. Info : Deleting HDL design. [CDFG-305] : Design 'axi_cdc_dst_LogDepth3_aw_chan_ttype_2_c2s_aw_chan_t_419_26_w_chan_ttype_2_c2s_w_chan_t_420_26_b_chan_ttype_2_c2s_b_chan_t_421_26_ar_chan_ttype_2_c2s_ar_chan_t_422_26_r_chan_ttype_2_c2s_r_chan_t_423_26_axi_req_ttype_2_c2s_req_t_438_25_axi_resp_ttype_2_c2s_resp_t_439_25'. Info : Deleting HDL design. [CDFG-305] : Design 'axi_cdc_src_LogDepth3_aw_chan_ttype_2_s2c_aw_chan_t_480_26_w_chan_ttype_2_s2c_w_chan_t_481_26_b_chan_ttype_2_s2c_b_chan_t_482_26_ar_chan_ttype_2_s2c_ar_chan_t_483_26_r_chan_ttype_2_s2c_r_chan_t_484_26_axi_req_ttype_2_s2c_req_t_498_25_axi_resp_ttype_2_s2c_resp_t_499_25'. Info : Deleting HDL design. [CDFG-305] : Design 'l2_ram_multi_bank_NB_BANKS4_BANK_SIZE_INTL_SRAM32768_mem_slave_XBAR_TCDM_BUS_Slave_mem_pri_slave_XBAR_TCDM_BUS_Slave'. Info : Deleting HDL design. [CDFG-305] : Design 'boot_rom_ROM_ADDR_WIDTH13_mem_slave_XBAR_TCDM_BUS_Slave'. Warning : Ignored attempt to delete blackbox or cell. [CDFG-313] : Blackbox 'generic_rom_ADDR_WIDTH11_DATA_WIDTH32'. Info : Deleting HDL design. [CDFG-305] : Design 'soc_peripherals_MEM_ADDR_WIDTH17_APB_ADDR_WIDTH32_APB_DATA_WIDTH32_NB_CORES8_NB_CLUSTERS1_EVNT_WIDTH8_NGPIO32_NPAD64_NBIT_PADCFG6_NBIT_PADMUX2_N_UART32h00000001_N_SPI32h00000001_N_I2C32h00000002_apb_slave_APB_BUS_Slave_apb_eu_master_APB_BUS_Master_apb_hwpe_master_APB_BUS_Master_apb_debug_master_APB_BUS_Master_l2_rx_master_XBAR_TCDM_BUS_Master_l2_tx_master_XBAR_TCDM_BUS_Master_soc_fll_master_FLL_BUS_out_per_fll_master_FLL_BUS_out_cluster_fll_master_FLL_BUS_out'. Info : Deleting HDL design. [CDFG-305] : Design 'periph_bus_wrap_APB_ADDR_WIDTH32_APB_DATA_WIDTH32_apb_slave_APB_BUS_Slave_fll_master_APB_BUS_Master_gpio_master_APB_BUS_Master_udma_master_APB_BUS_Master_soc_ctrl_master_APB_BUS_Master_adv_timer_master_APB_BUS_Master_soc_evnt_gen_master_APB_BUS_Master_eu_master_APB_BUS_Master_mmap_debug_master_APB_BUS_Master_timer_master_APB_BUS_Master_hwpe_master_APB_BUS_Master_stdout_master_APB_BUS_Master'. Info : Deleting HDL design. [CDFG-305] : Design 'apb_soc_ctrl_APB_ADDR_WIDTH32_NB_CLUSTERS1_NB_CORES8_NBIT_PADCFG6'. Info : Deleting HDL design. [CDFG-305] : Design 'cdc_fifo_gray_src_T_$t200_7_downto_0_unsigned_array_$unit_1__$t200_m3_0_LOG_DEPTH3_SYNC_STAGES2'. Info : Deleting HDL design. [CDFG-305] : Design 'soc_domain_CORE_TYPE0_USE_FPU1_USE_HWPE1_NB_CL_CORES8_AXI_ADDR_WIDTH32_AXI_DATA_IN_WIDTH64_AXI_DATA_OUT_WIDTH32_AXI_ID_IN_WIDTH32h00000007_AXI_ID_OUT_WIDTH32h00000005_AXI_USER_WIDTH6_AXI_STRB_IN_WIDTH8_AXI_STRB_OUT_WIDTH4_C2S_AW_WIDTH32h00000050_C2S_W_WIDTH79_C2S_B_WIDTH32h0000000f_C2S_AR_WIDTH32h0000004a_C2S_R_WIDTH32h00000050_S2C_AW_WIDTH32h0000004e_S2C_W_WIDTH43_S2C_B_WIDTH32h0000000d_S2C_AR_WIDTH32h00000048_S2C_R_WIDTH32h0000002e_BUFFER_WIDTH8_EVNT_WIDTH8_N_UART1_N_SPI1_N_I2C2'. Info : Deleting HDL design. [CDFG-305] : Design 'pulp'. Info : Deleting HDL design. [CDFG-305] : Design 'safe_domain'. Info : Unable to elaborate the design. [ELAB-4] : Module 'pulp' contains errors and cannot be elaborated. 1 legacy_genus:/> exit Lic Summary: [18:26:19.174488] Cdslmd servers: vlsitutor [18:26:19.174512] Feature usage summary: [18:26:19.174514] Genus_Synthesis Normal exit.