From 5628e5ad8f025fa70524a16862c215c08dac7f5e Mon Sep 17 00:00:00 2001 From: Aleksandar Markovic Date: Mon, 18 Apr 2016 18:03:42 +0200 Subject: [PATCH] target-mips: Clean up position of abs2008/nan2008 cases in genfarith() This patch slightly reorders cases in genfarith() so that abs2008/nan2008- dependant cases are grouped together, for easier maintenantce (code becomes less prone to errors). Signed-off-by: Aleksandar Markovic --- target-mips/translate.c | 152 ++++++++++++++++++++-------------------- 1 file changed, 76 insertions(+), 76 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 2f7fb5c2d123..8a0795c64c56 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -8972,25 +8972,25 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i32(fp0); } break; - case OPC_ABS_S: + case OPC_MOV_S: { TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); - if (ctx->abs2008) { - tcg_gen_andi_i32(fp0, fp0, 0x7fffffffUL); - } else { - gen_helper_float_abs_s(fp0, fp0); - } gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } break; - case OPC_MOV_S: + case OPC_ABS_S: { TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); + if (ctx->abs2008) { + tcg_gen_andi_i32(fp0, fp0, 0x7fffffffUL); + } else { + gen_helper_float_abs_s(fp0, fp0); + } gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } @@ -9009,6 +9009,23 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i32(fp0); } break; + case OPC_CVT_L_S: + check_cp1_64bitmode(ctx); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr32(ctx, fp32, fs); + if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->nan2008)) { + gen_helper_float_cvt_2008_l_s(fp64, cpu_env, fp32); + } else { + gen_helper_float_cvt_l_s(fp64, cpu_env, fp32); + } + tcg_temp_free_i32(fp32); + gen_store_fpr64(ctx, fp64, fd); + tcg_temp_free_i64(fp64); + } + break; case OPC_ROUND_L_S: check_cp1_64bitmode(ctx); { @@ -9077,6 +9094,20 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i64(fp64); } break; + case OPC_CVT_W_S: + { + TCGv_i32 fp0 = tcg_temp_new_i32(); + + gen_load_fpr32(ctx, fp0, fs); + if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->nan2008)) { + gen_helper_float_cvt_2008_w_s(fp0, cpu_env, fp0); + } else { + gen_helper_float_cvt_w_s(fp0, cpu_env, fp0); + } + gen_store_fpr32(ctx, fp0, fd); + tcg_temp_free_i32(fp0); + } + break; case OPC_ROUND_W_S: { TCGv_i32 fp0 = tcg_temp_new_i32(); @@ -9372,37 +9403,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i64(fp64); } break; - case OPC_CVT_W_S: - { - TCGv_i32 fp0 = tcg_temp_new_i32(); - - gen_load_fpr32(ctx, fp0, fs); - if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->nan2008)) { - gen_helper_float_cvt_2008_w_s(fp0, cpu_env, fp0); - } else { - gen_helper_float_cvt_w_s(fp0, cpu_env, fp0); - } - gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); - } - break; - case OPC_CVT_L_S: - check_cp1_64bitmode(ctx); - { - TCGv_i32 fp32 = tcg_temp_new_i32(); - TCGv_i64 fp64 = tcg_temp_new_i64(); - - gen_load_fpr32(ctx, fp32, fs); - if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->nan2008)) { - gen_helper_float_cvt_2008_l_s(fp64, cpu_env, fp32); - } else { - gen_helper_float_cvt_l_s(fp64, cpu_env, fp32); - } - tcg_temp_free_i32(fp32); - gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); - } - break; case OPC_CVT_PS_S: check_ps(ctx); { @@ -9509,6 +9509,16 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i64(fp0); } break; + case OPC_MOV_D: + check_cp1_registers(ctx, fs | fd); + { + TCGv_i64 fp0 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp0, fs); + gen_store_fpr64(ctx, fp0, fd); + tcg_temp_free_i64(fp0); + } + break; case OPC_ABS_D: check_cp1_registers(ctx, fs | fd); { @@ -9524,26 +9534,31 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i64(fp0); } break; - case OPC_MOV_D: + case OPC_NEG_D: check_cp1_registers(ctx, fs | fd); { TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); + if (ctx->abs2008) { + tcg_gen_xori_i64(fp0, fp0, 1ULL << 63); + } else { + gen_helper_float_chs_d(fp0, fp0); + } gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } break; - case OPC_NEG_D: - check_cp1_registers(ctx, fs | fd); + case OPC_CVT_L_D: + check_cp1_64bitmode(ctx); { TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - if (ctx->abs2008) { - tcg_gen_xori_i64(fp0, fp0, 1ULL << 63); + if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->nan2008)) { + gen_helper_float_cvt_2008_l_d(fp0, cpu_env, fp0); } else { - gen_helper_float_chs_d(fp0, fp0); + gen_helper_float_cvt_l_d(fp0, cpu_env, fp0); } gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); @@ -9609,6 +9624,23 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i64(fp0); } break; + case OPC_CVT_W_D: + check_cp1_registers(ctx, fs); + { + TCGv_i32 fp32 = tcg_temp_new_i32(); + TCGv_i64 fp64 = tcg_temp_new_i64(); + + gen_load_fpr64(ctx, fp64, fs); + if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->nan2008)) { + gen_helper_float_cvt_2008_w_d(fp32, cpu_env, fp64); + } else { + gen_helper_float_cvt_w_d(fp32, cpu_env, fp64); + } + tcg_temp_free_i64(fp64); + gen_store_fpr32(ctx, fp32, fd); + tcg_temp_free_i32(fp32); + } + break; case OPC_ROUND_W_D: check_cp1_registers(ctx, fs); { @@ -9937,38 +9969,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i32(fp32); } break; - case OPC_CVT_W_D: - check_cp1_registers(ctx, fs); - { - TCGv_i32 fp32 = tcg_temp_new_i32(); - TCGv_i64 fp64 = tcg_temp_new_i64(); - - gen_load_fpr64(ctx, fp64, fs); - if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->nan2008)) { - gen_helper_float_cvt_2008_w_d(fp32, cpu_env, fp64); - } else { - gen_helper_float_cvt_w_d(fp32, cpu_env, fp64); - } - tcg_temp_free_i64(fp64); - gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); - } - break; - case OPC_CVT_L_D: - check_cp1_64bitmode(ctx); - { - TCGv_i64 fp0 = tcg_temp_new_i64(); - - gen_load_fpr64(ctx, fp0, fs); - if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->nan2008)) { - gen_helper_float_cvt_2008_l_d(fp0, cpu_env, fp0); - } else { - gen_helper_float_cvt_l_d(fp0, cpu_env, fp0); - } - gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); - } - break; case OPC_CVT_S_W: { TCGv_i32 fp0 = tcg_temp_new_i32();