DDR3 DM are a complete mess (multiple problems).

[oskirby]

While trying to synthesize using LiteDram, we get an error that pin DDR3_DM1 is not located in the same DQS group as the rest of the high DQS bank (it appears to be using a DQSBUFM hard IP to control this signal). This presumeably means that the data mask signals also need to be length matched with their DQS groups too.

[oskirby]

We also found a more serious issue in the DDR3 package diagram which has DM/~TDQS and NF/TDQS swapped. This means that the DM pins have been floating all along which are causing LiteDram to fail its memory test.

I have been able to deploy a workaround by assigning the DM signals to NC pins on the FPGA so that they aren't driven anywhere and then hacking the MR1 register to enable the TDQS feature, which effectively disables the DM pins on the DDR chips.

So it seems that we got a ton of things wrong with the DM pins and they'll need to get cleaned up in a future revision.