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The 25MHz crystal used to generate the PCIe and DDR3 clocks is coprime with the desired frequency needed for the USB bootloader (48MHz) which leads to some awkwardness in the PLL configuration. In retrospect it may have made more sense to just include a spare 12-ish MHz oscillator for assorted programming uses.
The text was updated successfully, but these errors were encountered:
A better solution might be to use a programmable clock generator instead of the dedicated PCIe clock generator, such as the Si5351A, which can take a 25MHz crystal input and produce a wide variety of frequencies. The downside of the Si5351A is that we loose the convenient 25MHz reference clock output at boot.
The 25MHz crystal used to generate the PCIe and DDR3 clocks is coprime with the desired frequency needed for the USB bootloader (48MHz) which leads to some awkwardness in the PLL configuration. In retrospect it may have made more sense to just include a spare 12-ish MHz oscillator for assorted programming uses.
The text was updated successfully, but these errors were encountered: