From 9e8e8a2646768fa9ba9e09845fb185b1187a70d5 Mon Sep 17 00:00:00 2001 From: Sho Uemura Date: Wed, 28 Feb 2024 12:15:01 -0600 Subject: [PATCH] update description of register assignment --- qick_lib/qick/asm_v1.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/qick_lib/qick/asm_v1.py b/qick_lib/qick/asm_v1.py index 1d357cfb..ebbfa4fc 100644 --- a/qick_lib/qick/asm_v1.py +++ b/qick_lib/qick/asm_v1.py @@ -594,13 +594,13 @@ class QickProgram(AbsQickProgram): "upper": 0b1010, "lower": 0b0101 } - # To make it easier to configure pulses these special registers are reserved for each channel's pulse configuration. + # To make it easier to configure pulses, special registers are reserved for each channel's pulse configuration. # In each page, register 0 is hard-wired with the value 0. - # In page 0 we reserve the following additional registers: - # 13, 14 and 15 for loop counters, 16 for the trigger bits. - # Pairs of channels share a register page. - # The flat_top pulse uses some extra registers. - + # Each channel reserves 10 registers (the flat_top pulse uses some extra registers). + # All registers for a channel go on the same page, with registers assigned at the end of the page: + # so a page with 2 channels will assign registers 12 through 21 and 22 through 31. + # In page 0 we only put one channel, to make space for the following additional registers: + # 13, 14 and 15 for loop and shot counters, 16 for the trigger bits, 17 through 21 for NDAveragerProgram loop counters. gentypes = {'axis_signal_gen_v4': FullSpeedGenManager, 'axis_signal_gen_v5': FullSpeedGenManager,