From bf2f6859e48099548e312dd8e448dbcba25b05d0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 20 Apr 2024 11:27:54 -0700 Subject: [PATCH 01/31] Changed Verilog makefile to print transcript to stdout by default like Questa; redirected to logfile elsewhere --- sim/verilator/Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile index 4042326a8c..51f64f2754 100644 --- a/sim/verilator/Makefile +++ b/sim/verilator/Makefile @@ -23,8 +23,9 @@ profile: obj_dir_profiling/Vtestbench_$(WALLYCONF) run: obj_dir_non_profiling/Vtestbench_$(WALLYCONF) mkdir -p $(WORKING_DIR)/logs - time $(WORKING_DIR)/obj_dir_non_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) 2>&1 > $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log - echo "Please check $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log for logs and output files." +# time $(WORKING_DIR)/obj_dir_non_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) 2>&1 > $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log + time $(WORKING_DIR)/obj_dir_non_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) +# echo "Please check $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log for logs and output files." obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(SOURCE) mkdir -p obj_dir_non_profiling From 0fc66268f80fdf09a6f629b6b6d75200a12781cf Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 20 Apr 2024 12:44:44 -0700 Subject: [PATCH 02/31] coremark sweep cleanup --- benchmarks/coremark/Makefile | 1 + benchmarks/coremark/coremark_sweep.py | 19 ++++++++++++------- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile index 7c8cc9b8b0..527868eac0 100644 --- a/benchmarks/coremark/Makefile +++ b/benchmarks/coremark/Makefile @@ -27,6 +27,7 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \ all: $(work_dir)/coremark.bare.riscv.elf.memfile run: +# time wsim rv$(XLEN)gc coremark --sim verilator 2>&1 | tee $(work_dir)/coremark.sim.log time wsim rv$(XLEN)gc coremark 2>&1 | tee $(work_dir)/coremark.sim.log $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv diff --git a/benchmarks/coremark/coremark_sweep.py b/benchmarks/coremark/coremark_sweep.py index 555c514017..caf2ac1e94 100755 --- a/benchmarks/coremark/coremark_sweep.py +++ b/benchmarks/coremark/coremark_sweep.py @@ -37,24 +37,26 @@ "rv32i_zicsr", "rv32im_zicsr", "rv32imc_zicsr", - "rv32im_zicsr_zba_zbb_zbc", + "rv32im_zicsr_zba_zbb_zbs", "rv32gc", - "rv32gc_zba_zbb_zbc", + "rv32gc_zba_zbb_zbs", "rv64i_zicsr", "rv64im_zicsr", "rv64imc_zicsr", - "rv64im_zicsr_zba_zbb_zbc", + "rv64im_zicsr_zba_zbb_zbs", "rv64gc", - "rv64gc_zba_zbb_zbc" + "rv64gc_zba_zbb_zbs" ] str="32" + # Define regular expressions to match the desired fields mt_regex = r"Elapsed MTIME: (\d+).*?Elapsed MINSTRET: (\d+).*?COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+).*?CPI: \d+ / \d+ = (\d+\.\d+).*?Load Stalls (\d+).*?Store Stalls (\d+).*?D-Cache Accesses (\d+).*?D-Cache Misses (\d+).*?I-Cache Accesses (\d+).*?I-Cache Misses (\d+).*?Branches (\d+).*?Branches Miss Predictions (\d+).*?BTB Misses (\d+).*?Jump and JR (\d+).*?RAS Wrong (\d+).*?Returns (\d+).*?BP Class Wrong (\d+)" #cpi_regex = r"CPI: \d+ / \d+ = (\d+\.\d+)" #cmhz_regex = r"COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+)" # Open a CSV file to write the results -with open('coremark_results.csv', mode='w', newline='') as csvfile: - fieldnames = ['Architecture', 'MTIME','MINSTRET','CM / MHz','CPI','Load Stalls','Store Stalls','D$ Accesses', +resultfile = 'coremark_results.csv' +with open(resultfile, mode='w', newline='') as csvfile: + fieldnames = ['Architecture', 'CM / MHz','CPI','MTIME','MINSTRET','Load Stalls','Store Stalls','D$ Accesses', 'D$ Misses','I$ Accesses','I$ Misses','Branches','Branch Mispredicts','BTB Misses', 'Jump/JR','RAS Wrong','Returns','BP Class Pred Wrong'] writer = csv.DictWriter(csvfile, fieldnames=fieldnames) @@ -101,7 +103,10 @@ ret= mt_match.group(16) bpc= mt_match.group(17) #minstret = mt_instret_match.group(2) - writer.writerow({'Architecture': arch, 'MTIME': mtime,'MINSTRET':minstret,'CM / MHz':cmhz,'CPI':cpi, + writer.writerow({'Architecture': arch, 'CM / MHz':cmhz,'CPI':cpi, 'MTIME': mtime,'MINSTRET':minstret, 'Load Stalls':lstalls, 'Store Stalls':swtalls,'D$ Accesses':dacc,'D$ Misses':dmiss,'I$ Accesses':iacc,'I$ Misses':imiss, 'Branches':br,'Branch Mispredicts':brm,'BTB Misses':btb,'Jump/JR':jmp,'RAS Wrong':ras,'Returns':ret,'BP Class Pred Wrong':bpc}) + csvfile.close() + + From 9ec4c752f1fc87c5ad90186e398e7f4ffa2ad9f4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 20 Apr 2024 13:16:31 -0700 Subject: [PATCH 03/31] Fixed bugs in Zcb compressed loads and stores --- src/ifu/decompress.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index e6c4fcd9ab..359d6e3ad4 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -107,16 +107,16 @@ module decompress import cvw::*; #(parameter cvw_t P) ( InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld; 5'b00100: if (P.ZCB_SUPPORTED) if (instr16[12:10] == 3'b000) - InstrD = {10'b0, instr16[6:5], rs1p, 3'b100, rdp, 7'b0000011}; // c.lbu + InstrD = {10'b0, instr16[5], instr16[6], rs1p, 3'b100, rdp, 7'b0000011}; // c.lbu else if (instr16[12:10] == 3'b001) begin if (instr16[6]) InstrD = {10'b0, instr16[5], 1'b0, rs1p, 3'b001, rdp, 7'b0000011}; // c.lh else InstrD = {10'b0, instr16[5], 1'b0, rs1p, 3'b101, rdp, 7'b0000011}; // c.lhu end else if (instr16[12:10] == 3'b010) - InstrD = {7'b0, rs2p, rs1p, 3'b000, 3'b000, instr16[6:5], 7'b0000011}; // c.sb + InstrD = {7'b0, rs2p, rs1p, 3'b000, 3'b000, instr16[5], instr16[6], 7'b0100011}; // c.sb else if (instr16[12:10] == 3'b011 & instr16[6] == 1'b0) - InstrD = {7'b0, rs2p, rs1p, 3'b001, 3'b000, instr16[5], 1'b0, 7'b0000011}; // c.sh + InstrD = {7'b0, rs2p, rs1p, 3'b001, 3'b000, instr16[5], 1'b0, 7'b0100011}; // c.sh else begin IllegalCompInstrD = 1; InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap From d9ebfdfc4f90f8d90fa25ef534bd670cbbd1e5ff Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 20 Apr 2024 13:16:54 -0700 Subject: [PATCH 04/31] Enabled Zcb tests --- testbench/tests.vh | 2 -- 1 file changed, 2 deletions(-) diff --git a/testbench/tests.vh b/testbench/tests.vh index 8dfd69415e..1499c169a2 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1737,7 +1737,6 @@ string arch64zcb[] = '{ "rv64i_m/C/src/clbu-01.S", "rv64i_m/C/src/clh-01.S", "rv64i_m/C/src/clhu-01.S", - "rv64i_m/C/src/clbu-01.S", "rv64i_m/C/src/csb-01.S", "rv64i_m/C/src/csh-01.S", "rv64i_m/C/src/csext.b-01.S", @@ -1754,7 +1753,6 @@ string arch32zcb[] = '{ "rv32i_m/C/src/clbu-01.S", "rv32i_m/C/src/clh-01.S", "rv32i_m/C/src/clhu-01.S", - "rv32i_m/C/src/clbu-01.S", "rv32i_m/C/src/csb-01.S", "rv32i_m/C/src/csh-01.S", "rv32i_m/C/src/csext.b-01.S", From b7e66ec7d6f8272deddf5499f67ae9fc935a9144 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 20 Apr 2024 13:17:33 -0700 Subject: [PATCH 05/31] Added Zcb tests to riscof --- tests/riscof/sail_cSim/riscof_sail_cSim.py | 6 +++++- tests/riscof/spike/spike_rv32gc_isa.yaml | 6 ++---- tests/riscof/spike/spike_rv64gc_isa.yaml | 4 +--- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py index 878e25d4fd..eeb024d361 100644 --- a/tests/riscof/sail_cSim/riscof_sail_cSim.py +++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py @@ -52,6 +52,7 @@ def build(self, isa_yaml, platform_yaml): ispec = utils.load_yaml(isa_yaml)['hart0'] self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32') self.isa = 'rv' + self.xlen + self.sailargs = ' ' self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 ')) if "I" in ispec["ISA"]: self.isa += 'i' @@ -67,6 +68,8 @@ def build(self, isa_yaml, platform_yaml): self.isa += 'f' if "D" in ispec["ISA"]: self.isa += 'd' + if "Zcb" in ispec["ISA"]: # for some strange reason, Sail requires a command line argument to enable Zcb + self.sailargs += "--enable-zcb" objdump = "riscv64-unknown-elf-objdump".format(self.xlen) if shutil.which(objdump) is None: logger.error(objdump+": executable not found. Please check environment setup.") @@ -112,7 +115,8 @@ def runTests(self, testList, cgf_file=None): reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test)) execute += 'cut -c-{0:g} {1} > {2}'.format(8, reference_output, sig_file) #use cut to remove comments when copying else: - execute += self.sail_exe[self.xlen] + ' -z268435455 -i --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) + execute += self.sail_exe[self.xlen] + ' -z268435455 -i ' + self.sailargs + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) +# execute += self.sail_exe[self.xlen] + ' -z268435455 -i --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) cov_str = ' ' for label in testentry['coverage_labels']: diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index 1879440ed2..1e2474023c 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -1,8 +1,6 @@ hart_ids: [0] hart0: - ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh -# ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs -# ISA: RV32IMAFDCZicsr_Zicboz_Zifencei_Zca_Zba_Zbb_Zbc_Zbs # _Zbkb_Zcb + ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] @@ -27,4 +25,4 @@ hart0: legal: - extensions[25:0] bitmask [0x000112D, 0x0000000] wr_illegal: - - Unchanged \ No newline at end of file + - Unchangedcd \ No newline at end of file diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index b8fabebde3..5b3f2f47d7 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -1,8 +1,6 @@ hart_ids: [0] hart0: -# ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb -# ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb - ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh + ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64] From 800bdc290f3d8d8fd65e90373efaa584df2e6dde Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 20 Apr 2024 13:40:30 -0700 Subject: [PATCH 06/31] Increased ulimit for Verilator --- setup.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/setup.sh b/setup.sh index d8063b2aab..656fed5a67 100644 --- a/setup.sh +++ b/setup.sh @@ -24,7 +24,7 @@ echo \$WALLY set to ${WALLY} export PATH=$WALLY/bin:$PATH # Verilator needs a larger stack to simulate CORE-V Wally -ulimit -s 100000 +ulimit -c 234613 # load site licenses and tool locations if [ -f ${RISCV}/site-setup.sh ]; then From 3cb5cd0cb1deeb4ef25ba1921b3ed5c68cf88f3c Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 20 Apr 2024 14:12:55 -0700 Subject: [PATCH 07/31] simulator cleanup --- bin/regression-wally | 13 +++++++------ sim/vcs/{run_vcs.sh => run_vcs} | 15 +++++++++++---- sim/verilator/Makefile | 4 ++++ 3 files changed, 22 insertions(+), 10 deletions(-) rename sim/vcs/{run_vcs.sh => run_vcs} (52%) diff --git a/bin/regression-wally b/bin/regression-wally index a73f937a56..bf85b82257 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -32,18 +32,18 @@ tests = [ ["rv32gc", ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma", - "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", - "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], # "arch32zcb", "arch32zfad", + "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", "arch32zcb", + "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], # "arch32zfad" # fcvtmod.w.d not working because of Sail flag bug. Jordan has PR in to fix Sail ["rv64i", ["arch64i"]], ["buildroot", ["buildroot"], [f"+INSTR_LIMIT={INSTR_LIMIT}"], str(INSTR_LIMIT)+" instructions"] ] # Separate out floating-point tests for RV64 to speed up coverage tests64gc_nofp = [ - ["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", + ["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zcb", "arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv", "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh", - "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"]] # add when working: "arch64zcb", "arch64zicboz" + "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"]] # add when working: "arch64zicboz" ] tests64gc_fp = [ @@ -261,7 +261,8 @@ testfloat = '--testfloat' in sys.argv if (nightly): nightMode = "--nightly"; - sims = ["questa", "verilator", "vcs"] +# sims = ["questa", "verilator", "vcs"] + sims = ["verilator"] # *** uncomment to exercise all simulators else: nightMode = ""; sims = [defaultsim] @@ -386,7 +387,7 @@ def main(): TIMEOUT_DUR = 60*1440 # 1 day #configs.append(getBuildrootTC(boot=False)) elif '--testfloat' in sys.argv: - TIMEOUT_DUR = 60*60 # seconds + TIMEOUT_DUR = 5*60 # seconds else: TIMEOUT_DUR = 10*60 # seconds #configs.append(getBuildrootTC(boot=False)) diff --git a/sim/vcs/run_vcs.sh b/sim/vcs/run_vcs similarity index 52% rename from sim/vcs/run_vcs.sh rename to sim/vcs/run_vcs index ef9d84e452..334dbe43d2 100755 --- a/sim/vcs/run_vcs.sh +++ b/sim/vcs/run_vcs @@ -1,15 +1,22 @@ #!/bin/bash +# VCS Compilation for WALLY +# Divya Kohli, Rose Thompson, David Harris 2024 +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 - +CFG=${WALLY}/config +SRC=${WALLY}/src +TB=${WALLY}/testbench # Set CONFIG_VARIANT from the first script argument #CONFIG_VARIANT=${1:-rv64i} CONFIG_VARIANT=${1} # Set TESTSUITE from the second script argument TESTSUITE=$2 -INCLUDE_DIRS=$(find ../src -type d | xargs -I {} echo -n "{} ") -SOURCE_PATH="+incdir+../config/${CONFIG_VARIANT} +incdir+../config/deriv/${CONFIG_VARIANT} +incdir+../config/shared +define+ +define+P.XLEN=64 +define+FPGA=0 +incdir+../testbench ../src/cvw.sv +incdir+../src" -SIMFILES="$INCLUDE_DIRS $(find ../src -name "*.sv" ! -path "../src/generic/clockgater.sv" ! -path "../src/generic/mem/rom1p1r_128x64.sv" ! -path "../src/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "../src/generic/mem/rom1p1r_128x32.sv" ! -path "../src/generic/mem/ram2p1r1wbe_512x64.sv") ../testbench/testbench.sv $(find ../testbench/common -name "*.sv" ! -path "../testbench/common/wallyTracer.sv")" + +INCLUDE_DIRS=$(find ${SRC} -type d | xargs -I {} echo -n "{} ") +SOURCE_PATH="+incdir+${CFG}/${CONFIG_VARIANT} +incdir+${CFG}/deriv/${CONFIG_VARIANT} +incdir+${CFG}/shared +define+ +define+P.XLEN=64 +define+FPGA=0 +incdir+${TB} ${SRC}/cvw.sv +incdir+${SRC}" + +SIMFILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/clockgater.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x64.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x32.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_512x64.sv") ${TB}/testbench.sv $(find ${TB}/common -name "*.sv" ! -path "${TB}/common/wallyTracer.sv")" OUTPUT="sim_out" clean() { diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile index 47f5fb15f7..deacdf5c26 100644 --- a/sim/verilator/Makefile +++ b/sim/verilator/Makefile @@ -1,3 +1,7 @@ +# Verilator Makefile for WALLY +# Kunlin Han, Rose Thompson, David Harris 2024 +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + SHELL := /bin/bash .PHONY: profile run questa clean From f639cf4d47367014d737997d4cfd1132292a0fa1 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 20 Apr 2024 14:23:21 -0700 Subject: [PATCH 08/31] wsim invokes vcs --- bin/wsim | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/bin/wsim b/bin/wsim index 0796c51cd4..05edd515f9 100755 --- a/bin/wsim +++ b/bin/wsim @@ -67,6 +67,21 @@ if (args.sim == "questa"): elif (args.sim == "verilator"): # PWD=${WALLY}/sim CONFIG=rv64gc TESTSUITE=arch64i print(f"Running Verilator on {args.config} {args.testsuite}") + if (args.coverage): + print("Coverage option not available for Verilator") + exit(1) + if (args.gui): + print("GUI option not available for Verilator") + exit(1) os.system(f"/usr/bin/make -C {regressionDir}/verilator WALLYCONF={args.config} TEST={args.testsuite}") elif (args.sim == "vcs"): - print("Running VCS on %s %s", args.config, args.testsuite) + print(f"Running VCS on " + args.config + " " + args.testsuite) + if (args.coverage): + print("Coverage option not available for VCS") + exit(1) + if (args.gui): + print("GUI option not available for VCS") + exit(1) + cmd = cd + "; ./run_vcs " + args.config + " " + args.testsuite + print(cmd) + os.system(cmd) \ No newline at end of file From ea344fe2faf4af1cd05865473fe1629aac1798d0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 20 Apr 2024 15:55:52 -0700 Subject: [PATCH 09/31] Fixed getenvval lint error in rom1p1r --- src/generic/mem/rom1p1r.sv | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index 7a53c529e2..0c0c83b98a 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -26,6 +26,13 @@ // This model actually works correctly with vivado. +`ifdef VERILATOR +import "DPI-C" function string getenvval(input string env_name); +`else +import "DPI-C" function string getenv(input string env_name); +`endif +import "DPI-C" function int system(input string env_name); + module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0) (input logic clk, input logic ce, From 338f37b5704268403356dfdee4dfb406a2c5295e Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 20 Apr 2024 17:19:42 -0700 Subject: [PATCH 10/31] Moved getenv/getenvval declaration to config-shared so lint and regression both run --- config/shared/config-shared.vh | 6 ++++++ src/generic/mem/rom1p1r.sv | 6 ------ testbench/testbench.sv | 5 ----- 3 files changed, 6 insertions(+), 11 deletions(-) diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index 25d0d8c656..3c316958d2 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -129,3 +129,9 @@ localparam CORRSHIFTSZ = NORMSHIFTSZ-2; // Drop lead /* verilator lint_off STMTDLY */ /* verilator lint_off ASSIGNDLY */ /* verilator lint_off PINCONNECTEMPTY */ + +`ifdef VERILATOR +import "DPI-C" function string getenvval(input string env_name); +`else +import "DPI-C" function string getenv(input string env_name); +`endif \ No newline at end of file diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index 5bb82f6426..7a53c529e2 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -26,12 +26,6 @@ // This model actually works correctly with vivado. -`ifdef VERILATOR -import "DPI-C" function string getenvval(input string env_name); -`else -import "DPI-C" function string getenv(input string env_name); -`endif - module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0) (input logic clk, input logic ce, diff --git a/testbench/testbench.sv b/testbench/testbench.sv index b748271659..190ea64b4f 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -34,11 +34,6 @@ `endif import cvw::*; -`ifdef VERILATOR -import "DPI-C" function string getenvval(input string env_name); -`else -import "DPI-C" function string getenv(input string env_name); -`endif module testbench; /* verilator lint_off WIDTHTRUNC */ From a1876b1e7c9d04a9ec29823f2172acae6db7b368 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 20 Apr 2024 17:22:31 -0700 Subject: [PATCH 11/31] script cleanup --- bin/wsim | 2 +- sim/vcs/run_vcs | 3 ++- testbench/common/DCacheFlushFSM.sv | 1 - testbench/testbench.sv | 16 ++++++++-------- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/bin/wsim b/bin/wsim index 05edd515f9..268785a34e 100755 --- a/bin/wsim +++ b/bin/wsim @@ -82,6 +82,6 @@ elif (args.sim == "vcs"): if (args.gui): print("GUI option not available for VCS") exit(1) - cmd = cd + "; ./run_vcs " + args.config + " " + args.testsuite + cmd = cd + "; ./run_vcs " + args.config + " " + "\""+args.testsuite+"\"" print(cmd) os.system(cmd) \ No newline at end of file diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs index 334dbe43d2..a78939ac46 100755 --- a/sim/vcs/run_vcs +++ b/sim/vcs/run_vcs @@ -27,6 +27,7 @@ clean() { # Clean and run simulation with VCS clean #vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} +define+TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV -vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} -pvalue+testbench.TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV +# lint ignores Unused Inputs (UI), Unnamed Assertipons (SVA-UA), Dynamic Type Sensitivty [IDTS] +vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} -pvalue+testbench.TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV ./$OUTPUT | tee program.out diff --git a/testbench/common/DCacheFlushFSM.sv b/testbench/common/DCacheFlushFSM.sv index 152aaa1735..ed9d563421 100644 --- a/testbench/common/DCacheFlushFSM.sv +++ b/testbench/common/DCacheFlushFSM.sv @@ -29,7 +29,6 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) (input logic clk, - input logic reset, input logic start, output logic done); diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 190ea64b4f..41a183a8fe 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -508,17 +508,17 @@ module testbench; //////////////////////////////////////////////////////////////////////////////// // instantiate device to be tested - assign GPIOIN = 0; - assign UARTSin = 1; - assign SPIIn = 0; + assign GPIOIN = '0; + assign UARTSin = 1'b1; + assign SPIIn = 1'b0; if(P.EXT_MEM_SUPPORTED) begin ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB); end else begin - assign HREADYEXT = 1; - assign {HRESPEXT, HRDATAEXT} = 0; + assign HREADYEXT = 1'b1; + assign {HRESPEXT, HRDATAEXT} = '0; end if(P.SDC_SUPPORTED) begin : sdcard @@ -534,9 +534,9 @@ module testbench; assign SDCDat = sd_dat_reg_t ? sd_dat_reg_o : sd_dat_i; assign SDCDatIn = SDCDat; -----/\----- EXCLUDED -----/\----- */ - assign SDCIntr = 0; + assign SDCIntr = 1'b0; end else begin - assign SDCIntr = 0; + assign SDCIntr = 1'b0; end wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, @@ -621,7 +621,7 @@ module testbench; //assign DCacheFlushStart = TestComplete; end - DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone)); + DCacheFlushFSM #(P) DCacheFlushFSM(.clk, .start(DCacheFlushStart), .done(DCacheFlushDone)); if(P.ZICSR_SUPPORTED) begin logic [P.XLEN-1:0] Minstret; From 25a26656b6dd2ce7907d31970f10285903f588b6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 20 Apr 2024 20:53:14 -0700 Subject: [PATCH 12/31] Removed unnecessary ZBB from BMU extract mux --- src/ieu/alu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index ae573ca70e..4126f4ae1a 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -81,7 +81,7 @@ module alu import cvw::*; #(parameter cvw_t P) ( 3'b010: FullResult = {{(P.XLEN-1){1'b0}}, LT}; // slt 3'b011: FullResult = {{(P.XLEN-1){1'b0}}, LTU}; // sltu 3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv - 3'b101: FullResult = (P.ZBS_SUPPORTED | P.ZBB_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(A & CondMaskB)}} : Shift; // bext (or IEU shift when BMU not supported) + 3'b101: FullResult = (P.ZBS_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(A & CondMaskB)}} : Shift; // bext (or IEU shift when BMU not supported) 3'b110: FullResult = A | CondMaskInvB; // or, orn, bset 3'b111: FullResult = A & ZeroCondMaskInvB; // and, bclr, czero.* endcase From f39e24008247310aa5a237ba6c97b28bd8e9fe77 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 20 Apr 2024 20:53:49 -0700 Subject: [PATCH 13/31] Spacing cleanup --- src/ieu/alu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 4126f4ae1a..0b19e57579 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -87,7 +87,7 @@ module alu import cvw::*; #(parameter cvw_t P) ( endcase // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits - if (P.XLEN == 64) assign PreALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; + if (P.XLEN == 64) assign PreALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; else assign PreALUResult = FullResult; // Bit manipulation muxing From fd6a6b224959bc29f131558695945aee88d97579 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 20 Apr 2024 22:52:08 -0700 Subject: [PATCH 14/31] environment variable cleanup --- config/shared/config-shared.vh | 11 +++++++--- sim/vcs/run_vcs | 6 ++++-- src/generic/flop/flopens.sv | 38 ---------------------------------- src/generic/mem/rom1p1r.sv | 17 ++++----------- testbench/testbench.sv | 18 +++++----------- 5 files changed, 21 insertions(+), 69 deletions(-) delete mode 100644 src/generic/flop/flopens.sv diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index 3c316958d2..db2a62377b 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -131,7 +131,12 @@ localparam CORRSHIFTSZ = NORMSHIFTSZ-2; // Drop lead /* verilator lint_off PINCONNECTEMPTY */ `ifdef VERILATOR -import "DPI-C" function string getenvval(input string env_name); + import "DPI-C" function string getenvval(input string env_name); + string RISCV_DIR = getenvval("RISCV"); // "/opt/riscv"; + string WALLY_DIR = getenvval("WALLY"); `else -import "DPI-C" function string getenv(input string env_name); -`endif \ No newline at end of file +// import "DPI-C" function string getenv(input string env_name); +// string RISCV_DIR = getenv("RISCV"); // "/opt/riscv"; + string RISCV_DIR = "$RISCV"; // "/opt/riscv"; + string WALLY_DIR = "$WALLY"; +`endif diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs index a78939ac46..cde1c50d79 100755 --- a/sim/vcs/run_vcs +++ b/sim/vcs/run_vcs @@ -1,6 +1,7 @@ #!/bin/bash # VCS Compilation for WALLY # Divya Kohli, Rose Thompson, David Harris 2024 +# Note: VCS produces warning about unsupported Linux Version, but runs successfully # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 CFG=${WALLY}/config @@ -27,7 +28,8 @@ clean() { # Clean and run simulation with VCS clean #vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} +define+TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV -# lint ignores Unused Inputs (UI), Unnamed Assertipons (SVA-UA), Dynamic Type Sensitivty [IDTS] -vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} -pvalue+testbench.TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV +# lint ignores Unused Inputs (UI), Unnamed Assertipons (SVA-UA), Dynamic Type Sensitivty [IDTS], Null Statement [NS], Unequal Length in Comparison Operation [ULCO] +# ,noOBSV2G +vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse ${SOURCE_PATH} -pvalue+testbench.TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV ./$OUTPUT | tee program.out diff --git a/src/generic/flop/flopens.sv b/src/generic/flop/flopens.sv deleted file mode 100644 index d5969128c5..0000000000 --- a/src/generic/flop/flopens.sv +++ /dev/null @@ -1,38 +0,0 @@ -/////////////////////////////////////////// -// flopens.sv -// -// Written: David_Harris@hmc.edu 9 January 2021 -// Modified: -// -// Purpose: D flip-flop with enable, synchronous set -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module flopens #(parameter WIDTH = 8) ( - input logic clk, set, en, - input logic [WIDTH-1:0] d, - output logic [WIDTH-1:0] q); - - always_ff @(posedge clk) - if (set) q <= 1; - else if (en) q <= d; -endmodule - - diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index 7a53c529e2..832de8fd8e 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -46,20 +46,11 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0) end else begin */ - initial begin - if (PRELOAD_ENABLED) begin -`ifdef VERILATOR - $readmemh({getenvval("WALLY"), "/fpga/src/boot.mem"}, ROM, 0); -`else - $readmemh("$WALLY/fpga/src/boot.mem", ROM, 0); -`endif - end - end - - always_ff @ (posedge clk) begin + initial + if (PRELOAD_ENABLED) $readmemh({WALLY_DIR,"/fpga/src/boot.mem"}, ROM, 0); + + always_ff @ (posedge clk) if(ce) dout <= ROM[addr]; - end - // for FPGA, initialize with zero-stage bootloader /*if(PRELOAD_ENABLED) begin diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 41a183a8fe..5778972714 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -33,9 +33,7 @@ `include "idv/idv.svh" `endif -import cvw::*; - -module testbench; +module testbench import cvw::*; (); /* verilator lint_off WIDTHTRUNC */ /* verilator lint_off WIDTHEXPAND */ parameter DEBUG=0; @@ -59,12 +57,6 @@ module testbench; // Variables that can be overwritten with $value$plusargs at start of simulation string TEST; integer INSTR_LIMIT; -`ifdef VERILATOR - string RISCV_DIR = getenvval("RISCV"); // "/opt/riscv"; -`else - string RISCV_DIR = getenv("RISCV"); // "/opt/riscv"; -`endif - // string RISCV_DIR = "/opt/riscv"; // DUT signals logic [P.AHBW-1:0] HRDATAEXT; @@ -255,9 +247,9 @@ module testbench; assign ResetThreshold = 3'd5; initial begin - TestBenchReset = 1; + TestBenchReset = 1'b1; # 100; - TestBenchReset = 0; + TestBenchReset = 1'b0; end always_ff @(posedge clk) @@ -501,7 +493,7 @@ module testbench; always @(posedge clk) if (ResetMem) // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory) for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) - dut.uncoregen.uncore.ram.ram.memory.RAM[adrindex] = 0; + dut.uncoregen.uncore.ram.ram.memory.RAM[adrindex] = '0; //////////////////////////////////////////////////////////////////////////////// // Actual hardware @@ -546,7 +538,7 @@ module testbench; // generate clock to sequence tests always begin - clk = 1; # 5; clk = 0; # 5; + clk = 1'b1; # 5; clk = 1'b0; # 5; end /* From 1817ab2e119f9bcdb01a64dc40493ec2013a7284 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 20 Apr 2024 23:13:13 -0700 Subject: [PATCH 15/31] testbench import is happy now for Questa, but throws lint warning for VCS --- testbench/testbench.sv | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 5778972714..4086b20857 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -33,7 +33,9 @@ `include "idv/idv.svh" `endif -module testbench import cvw::*; (); +import cvw::*; + +module testbench; /* verilator lint_off WIDTHTRUNC */ /* verilator lint_off WIDTHEXPAND */ parameter DEBUG=0; From 00a1c0fc57a33d27d2c98e31a16da3423e262075 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 21 Apr 2024 00:02:15 -0700 Subject: [PATCH 16/31] Fixed WALLY/RISCV paths in testbench/rom1p1r; search log files for warnings and errors --- bin/regression-wally | 4 ++++ config/shared/config-shared.vh | 11 ----------- sim/vcs/run_vcs | 3 +-- src/cvw.sv | 1 - src/generic/mem/rom1p1r.sv | 14 +++++++++++++- testbench/testbench.sv | 7 +++++++ 6 files changed, 25 insertions(+), 15 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 9194ca9bfc..7622e7aea0 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -237,6 +237,10 @@ def addTests(tests, sim): def search_log_for_text(text, grepfile): """Search through the given log file for text, returning True if it is found or False if it is not""" + grepwarn = "grep -H Warning: " + grepfile + os.system(grepwarn) + greperr = "grep -H Error: " + grepfile + os.system(greperr) grepcmd = "grep -a -e '%s' '%s' > /dev/null" % (text, grepfile) # print(" search_log_for_text invoking %s" % grepcmd) return os.system(grepcmd) == 0 diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index db2a62377b..25d0d8c656 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -129,14 +129,3 @@ localparam CORRSHIFTSZ = NORMSHIFTSZ-2; // Drop lead /* verilator lint_off STMTDLY */ /* verilator lint_off ASSIGNDLY */ /* verilator lint_off PINCONNECTEMPTY */ - -`ifdef VERILATOR - import "DPI-C" function string getenvval(input string env_name); - string RISCV_DIR = getenvval("RISCV"); // "/opt/riscv"; - string WALLY_DIR = getenvval("WALLY"); -`else -// import "DPI-C" function string getenv(input string env_name); -// string RISCV_DIR = getenv("RISCV"); // "/opt/riscv"; - string RISCV_DIR = "$RISCV"; // "/opt/riscv"; - string WALLY_DIR = "$WALLY"; -`endif diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs index cde1c50d79..27ffff8f09 100755 --- a/sim/vcs/run_vcs +++ b/sim/vcs/run_vcs @@ -29,7 +29,6 @@ clean() { clean #vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} +define+TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV # lint ignores Unused Inputs (UI), Unnamed Assertipons (SVA-UA), Dynamic Type Sensitivty [IDTS], Null Statement [NS], Unequal Length in Comparison Operation [ULCO] -# ,noOBSV2G -vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse ${SOURCE_PATH} -pvalue+testbench.TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV +vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse ${SOURCE_PATH} -pvalue+testbench.TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV ./$OUTPUT | tee program.out diff --git a/src/cvw.sv b/src/cvw.sv index 21b55c55e5..75ff3f7e74 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -293,7 +293,6 @@ typedef struct packed { int DURLEN ; int DIVb ; int DIVBLEN ; - } cvw_t; endpackage diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index 832de8fd8e..229e481eb3 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -26,6 +26,13 @@ // This model actually works correctly with vivado. +`ifdef VERILATOR + import "DPI-C" function string getenvval(input string env_name); + string WALLY_DIR = getenvval("WALLY"); +`else + string WALLY_DIR = "$WALLY"; +`endif + module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0) (input logic clk, input logic ce, @@ -47,7 +54,12 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0) end else begin */ initial - if (PRELOAD_ENABLED) $readmemh({WALLY_DIR,"/fpga/src/boot.mem"}, ROM, 0); + if (PRELOAD_ENABLED) begin + if (DATA_WIDTH == 64) $readmemh({WALLY_DIR,"/fpga/src/boot.mem"}, ROM, 0); // load boot ROM for FPGA + else begin // put something in the ROM so it is not optimized away + ROM[0] = 'h00002197; + end + end always_ff @ (posedge clk) if(ce) dout <= ROM[addr]; diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 4086b20857..a126b42095 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -33,6 +33,13 @@ `include "idv/idv.svh" `endif +`ifdef VERILATOR + import "DPI-C" function string getenvval(input string env_name); + string RISCV_DIR = getenvval("RISCV"); // "/opt/riscv"; +`else + string RISCV_DIR = "$RISCV"; // "/opt/riscv"; +`endif + import cvw::*; module testbench; From 0419b5484a81aa61fed7a3f16a1973d4ddd53a00 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 21 Apr 2024 07:43:01 -0700 Subject: [PATCH 17/31] parameterized register names in peripherals --- src/uncore/clint_apb.sv | 33 ++++---- src/uncore/gpio_apb.sv | 113 +++++++++++++++------------ src/uncore/plic_apb.sv | 70 ++++++++++------- src/uncore/ram_ahb.sv | 4 +- src/uncore/spi_apb.sv | 109 ++++++++++++++------------ src/uncore/uartPC16550D.sv | 152 ++++++++++++++++++++----------------- 6 files changed, 271 insertions(+), 210 deletions(-) diff --git a/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv index 997c1bd391..c416f29382 100644 --- a/src/uncore/clint_apb.sv +++ b/src/uncore/clint_apb.sv @@ -42,6 +42,11 @@ module clint_apb import cvw::*; #(parameter cvw_t P) ( output logic MTimerInt, MSwInt ); + // register map + localparam CLINT_MSIP = 16'h0000; + localparam CLINT_MTIMECMP = 16'h4000; + localparam CLINT_MTIME = 16'hBFF8; + logic MSIP; logic [15:0] entry; logic memwrite; @@ -65,19 +70,19 @@ module clint_apb import cvw::*; #(parameter cvw_t P) ( if (P.XLEN==64) begin:clint // 64-bit always_ff @(posedge PCLK) begin case(entry) - 16'h0000: PRDATA <= {63'b0, MSIP}; - 16'h4000: PRDATA <= MTIMECMP; - 16'hBFF8: PRDATA <= MTIME; - default: PRDATA <= 0; + CLINT_MSIP: PRDATA <= {63'b0, MSIP}; + CLINT_MTIMECMP: PRDATA <= MTIMECMP; + CLINT_MTIME: PRDATA <= MTIME; + default: PRDATA <= '0; endcase end always_ff @(posedge PCLK or negedge PRESETn) if (~PRESETn) begin - MSIP <= 0; + MSIP <= 1'b0; MTIMECMP <= 64'hFFFFFFFFFFFFFFFF; // Spec says MTIMECMP is not reset, but we reset to maximum value to prevent spurious timer interrupts end else if (memwrite) begin - if (entry == 16'h0000) MSIP <= PWDATA[0]; - if (entry == 16'h4000) begin + if (entry == CLINT_MSIP) MSIP <= PWDATA[0]; + if (entry == CLINT_MTIMECMP) begin for(i=0;i1 cycle to respond assign entry = {PADDR[23:2],2'b0}; - assign One[P.PLIC_NUM_SRC-1:1] = 0; assign One[0] = 1'b1; // Vivado does not like this as a single assignment. + assign One[P.PLIC_NUM_SRC-1:1] = '0; assign One[0] = 1'b1; // Vivado does not like this as a single assignment. // account for subword read/write circuitry // -- Note PLIC registers are 32 bits no matter what; access them with LW SW. @@ -107,48 +120,49 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( always_ff @(posedge PCLK) begin // resetting if (~PRESETn) begin - intPriority <= 0; - intEn <= 0; - intThreshold <= 0; - intInProgress <= 0; + intPriority <= '0; + intEn <= '0; + intThreshold <= '0; + intInProgress <= '0; // writing end else begin if (memwrite) casez(entry) - 24'h0000??: intPriority[entry[7:2]] <= Din[2:0]; - 24'h002000: intEn[0][PLIC_NUM_SRC_MIN_32:1] <= Din[PLIC_NUM_SRC_MIN_32:1]; - 24'h002080: intEn[1][PLIC_NUM_SRC_MIN_32:1] <= Din[PLIC_NUM_SRC_MIN_32:1]; - 24'h002004: if (P.PLIC_NUM_SRC >= 32) intEn[0][PLIC_SRC_TOP:PLIC_SRC_BOT] <= Din[PLIC_SRC_DINTOP:0]; - 24'h002084: if (P.PLIC_NUM_SRC >= 32) intEn[1][PLIC_SRC_TOP:PLIC_SRC_BOT] <= Din[PLIC_SRC_DINTOP:0]; - 24'h200000: intThreshold[0] <= Din[2:0]; - 24'h200004: intInProgress <= intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion - 24'h201000: intThreshold[1] <= Din[2:0]; - 24'h201004: intInProgress <= intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion + 24'h0000??: intPriority[entry[7:2]] <= Din[2:0]; + PLIC_INTEN00: intEn[0][PLIC_NUM_SRC_MIN_32:1] <= Din[PLIC_NUM_SRC_MIN_32:1]; + PLIC_INTEN10: intEn[1][PLIC_NUM_SRC_MIN_32:1] <= Din[PLIC_NUM_SRC_MIN_32:1]; + PLIC_INTEN01: if (P.PLIC_NUM_SRC >= 32) intEn[0][PLIC_SRC_TOP:PLIC_SRC_BOT] <= Din[PLIC_SRC_DINTOP:0]; + PLIC_INTEN11: if (P.PLIC_NUM_SRC >= 32) intEn[1][PLIC_SRC_TOP:PLIC_SRC_BOT] <= Din[PLIC_SRC_DINTOP:0]; + PLIC_THRESHOLD0: intThreshold[0] <= Din[2:0]; + PLIC_CLAIMCOMPLETE0: intInProgress <= intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion + PLIC_THRESHOLD1: intThreshold[1] <= Din[2:0]; + PLIC_CLAIMCOMPLETE1: intInProgress <= intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion endcase + // Read synchronously because a read can have side effect of changing intInProgress if (memread) begin casez(entry) - 24'h000000: Dout <= 32'b0; // there is no intPriority[0] - 24'h0000??: Dout <= {29'b0,intPriority[entry[7:2]]}; - 24'h001000: Dout <= {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intPending[PLIC_NUM_SRC_MIN_32:1],1'b0}; - 24'h002000: Dout <= {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[0][PLIC_NUM_SRC_MIN_32:1],1'b0}; - 24'h001004: if (P.PLIC_NUM_SRC >= 32) Dout <= {{(PLIC_SRC_EXT){1'b0}},intPending[PLIC_SRC_TOP:PLIC_SRC_BOT]}; - 24'h002004: if (P.PLIC_NUM_SRC >= 32) Dout <= {{(PLIC_SRC_EXT){1'b0}},intEn[0][PLIC_SRC_TOP:PLIC_SRC_BOT]}; - 24'h002080: Dout <= {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[1][PLIC_NUM_SRC_MIN_32:1],1'b0}; - 24'h002084: if (P.PLIC_NUM_SRC >= 32) Dout <= {{(PLIC_SRC_EXT){1'b0}},intEn[1][PLIC_SRC_TOP:PLIC_SRC_BOT]}; - 24'h200000: Dout <= {29'b0,intThreshold[0]}; - 24'h200004: begin + PLIC_INTPRIORITY0: Dout <= 32'b0; // there is no intPriority[0] + 24'h0000??: Dout <= {29'b0,intPriority[entry[7:2]]}; + PLIC_INTPENDING0: Dout <= {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intPending[PLIC_NUM_SRC_MIN_32:1],1'b0}; + PLIC_INTEN00: Dout <= {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[0][PLIC_NUM_SRC_MIN_32:1],1'b0}; + PLIC_INTPENDING1: if (P.PLIC_NUM_SRC >= 32) Dout <= {{(PLIC_SRC_EXT){1'b0}},intPending[PLIC_SRC_TOP:PLIC_SRC_BOT]}; + PLIC_INTEN01: if (P.PLIC_NUM_SRC >= 32) Dout <= {{(PLIC_SRC_EXT){1'b0}},intEn[0][PLIC_SRC_TOP:PLIC_SRC_BOT]}; + PLIC_INTEN10: Dout <= {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[1][PLIC_NUM_SRC_MIN_32:1],1'b0}; + PLIC_INTEN11: if (P.PLIC_NUM_SRC >= 32) Dout <= {{(PLIC_SRC_EXT){1'b0}},intEn[1][PLIC_SRC_TOP:PLIC_SRC_BOT]}; + PLIC_THRESHOLD0: Dout <= {29'b0,intThreshold[0]}; + PLIC_CLAIMCOMPLETE0: begin Dout <= {26'b0,intClaim[0]}; intInProgress <= intInProgress | (One << (intClaim[0]-1)); // claimed requests are currently in progress of being serviced until they are completed end - 24'h201000: Dout <= {29'b0,intThreshold[1]}; - 24'h201004: begin + PLIC_THRESHOLD1: Dout <= {29'b0,intThreshold[1]}; + PLIC_CLAIMCOMPLETE1: begin Dout <= {26'b0,intClaim[1]}; intInProgress <= intInProgress | (One << (intClaim[1]-1)); // claimed requests are currently in progress of being serviced until they are completed end - default: Dout <= 32'h0; // invalid access + default: Dout <= 32'h0; // invalid access endcase - end else Dout <= 32'h0; + end else Dout <= 32'h0; end end diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index d26161f4f0..ed4b4d9ecd 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -64,7 +64,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, assign nextHREADYRam = (~(memwriteD & memread)) & ~DelayReady; flopr #(1) readyreg(HCLK, ~HRESETn, nextHREADYRam, HREADYRam); - assign HRESPRam = 0; // OK + assign HRESPRam = 1'b0; // OK // On writes or during a wait state, use address delayed by one cycle to sync RamAddr with HWDATA or hold stalled address mux2 #(P.PA_BITS) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr); @@ -104,7 +104,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, assign DelayReady = NextState == DELAY; assign CntRst = NextState == READY; end else begin - assign DelayReady = 0; + assign DelayReady = 1'b0; end endmodule diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv index 3f34e938e6..b54480de38 100644 --- a/src/uncore/spi_apb.sv +++ b/src/uncore/spi_apb.sv @@ -45,6 +45,22 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( output logic SPIIntr ); + // register map + localparam SPI_SCKDIV = 8'h00; + localparam SPI_SCKMODE = 8'h04; + localparam SPI_CSID = 8'h10; + localparam SPI_CSDEF = 8'h14; + localparam SPI_CSMODE = 8'h18; + localparam SPI_DELAY0 = 8'h28; + localparam SPI_DELAY1 = 8'h2C; + localparam SPI_FMT = 8'h40; + localparam SPI_TXDATA = 8'h48; + localparam SPI_RXDATA = 8'h4C; + localparam SPI_TXMARK = 8'h50; + localparam SPI_RXMARK = 8'h54; + localparam SPI_IE = 8'h70; + localparam SPI_IP = 8'h74; + // SPI control registers. Refer to SiFive FU540-C000 manual logic [11:0] SckDiv; logic [1:0] SckMode; @@ -61,7 +77,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( // Bus interface signals logic [7:0] Entry; logic Memwrite; - logic [31:0] Din, Dout; + logic [31:0] Din, Dout; logic TransmitInactive; // High when there is no transmission, used as hardware interlock signal // FIFO FSM signals @@ -130,8 +146,8 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( // -- Note SPI registers are 32 bits no matter what; access them with LW SW. assign Din = PWDATA[31:0]; - if (P.XLEN == 64) assign PRDATA = {Dout, Dout}; - else assign PRDATA = Dout; + if (P.XLEN == 64) assign PRDATA = { Dout, Dout}; + else assign PRDATA = Dout; // Register access always_ff@(posedge PCLK, negedge PRESETn) @@ -140,7 +156,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( SckMode <= 2'b0; ChipSelectID <= 2'b0; ChipSelectDef <= 4'b1111; - ChipSelectMode <= 0; + ChipSelectMode <= 2'b0; Delay0 <= {8'b1,8'b1}; Delay1 <= {8'b0,8'b1}; Format <= {5'b10000}; @@ -155,18 +171,18 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( /* verilator lint_off CASEINCOMPLETE */ if (Memwrite & TransmitInactive) case(Entry) // flop to sample inputs - 8'h00: SckDiv <= Din[11:0]; - 8'h04: SckMode <= Din[1:0]; - 8'h10: ChipSelectID <= Din[1:0]; - 8'h14: ChipSelectDef <= Din[3:0]; - 8'h18: ChipSelectMode <= Din[1:0]; - 8'h28: Delay0 <= {Din[23:16], Din[7:0]}; - 8'h2C: Delay1 <= {Din[23:16], Din[7:0]}; - 8'h40: Format <= {Din[19:16], Din[2]}; - 8'h48: if (~TransmitFIFOWriteFull) TransmitData[7:0] <= Din[7:0]; - 8'h50: TransmitWatermark <= Din[2:0]; - 8'h54: ReceiveWatermark <= Din[2:0]; - 8'h70: InterruptEnable <= Din[1:0]; + SPI_SCKDIV: SckDiv <= Din[11:0]; + SPI_SCKMODE: SckMode <= Din[1:0]; + SPI_CSID: ChipSelectID <= Din[1:0]; + SPI_CSDEF: ChipSelectDef <= Din[3:0]; + SPI_CSMODE: ChipSelectMode <= Din[1:0]; + SPI_DELAY0: Delay0 <= {Din[23:16], Din[7:0]}; + SPI_DELAY1: Delay1 <= {Din[23:16], Din[7:0]}; + SPI_FMT: Format <= {Din[19:16], Din[2]}; + SPI_TXDATA: if (~TransmitFIFOWriteFull) TransmitData[7:0] <= Din[7:0]; + SPI_TXMARK: TransmitWatermark <= Din[2:0]; + SPI_RXMARK: ReceiveWatermark <= Din[2:0]; + SPI_IE: InterruptEnable <= Din[1:0]; endcase /* verilator lint_off CASEINCOMPLETE */ @@ -176,21 +192,21 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( InterruptPending[1] <= RecieveWriteMark; case(Entry) // Flop to sample inputs - 8'h00: Dout <= {20'b0, SckDiv}; - 8'h04: Dout <= {30'b0, SckMode}; - 8'h10: Dout <= {30'b0, ChipSelectID}; - 8'h14: Dout <= {28'b0, ChipSelectDef}; - 8'h18: Dout <= {30'b0, ChipSelectMode}; - 8'h28: Dout <= {8'b0, Delay0[15:8], 8'b0, Delay0[7:0]}; - 8'h2C: Dout <= {8'b0, Delay1[15:8], 8'b0, Delay1[7:0]}; - 8'h40: Dout <= {12'b0, Format[4:1], 13'b0, Format[0], 2'b0}; - 8'h48: Dout <= {23'b0, TransmitFIFOWriteFull, 8'b0}; - 8'h4C: Dout <= {23'b0, ReceiveFIFOReadEmpty, ReceiveData[7:0]}; - 8'h50: Dout <= {29'b0, TransmitWatermark}; - 8'h54: Dout <= {29'b0, ReceiveWatermark}; - 8'h70: Dout <= {30'b0, InterruptEnable}; - 8'h74: Dout <= {30'b0, InterruptPending}; - default: Dout <= 32'b0; + SPI_SCKDIV: Dout <= {20'b0, SckDiv}; + SPI_SCKMODE: Dout <= {30'b0, SckMode}; + SPI_CSID: Dout <= {30'b0, ChipSelectID}; + SPI_CSDEF: Dout <= {28'b0, ChipSelectDef}; + SPI_CSMODE: Dout <= {30'b0, ChipSelectMode}; + SPI_DELAY0: Dout <= {8'b0, Delay0[15:8], 8'b0, Delay0[7:0]}; + SPI_DELAY1: Dout <= {8'b0, Delay1[15:8], 8'b0, Delay1[7:0]}; + SPI_FMT: Dout <= {12'b0, Format[4:1], 13'b0, Format[0], 2'b0}; + SPI_TXDATA: Dout <= {23'b0, TransmitFIFOWriteFull, 8'b0}; + SPI_RXDATA: Dout <= {23'b0, ReceiveFIFOReadEmpty, ReceiveData[7:0]}; + SPI_TXMARK: Dout <= {29'b0, TransmitWatermark}; + SPI_RXMARK: Dout <= {29'b0, ReceiveWatermark}; + SPI_IE: Dout <= {30'b0, InterruptEnable}; + SPI_IP: Dout <= {30'b0, InterruptPending}; + default: Dout <= 32'b0; endcase end @@ -200,8 +216,8 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( assign SCLKenable = (DivCounter == SckDiv); assign SCLKenableEarly = ((DivCounter + 12'b1) == SckDiv); always_ff @(posedge PCLK, negedge PRESETn) - if (~PRESETn) DivCounter <= 0; - else if (SCLKenable) DivCounter <= 0; + if (~PRESETn) DivCounter <= '0; + else if (SCLKenable) DivCounter <= 12'b0; else DivCounter <= DivCounter + 12'b1; // Asserts when transmission is one frame before complete @@ -219,11 +235,11 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( // Calculate tx/rx fifo write and recieve increment signals always_ff @(posedge PCLK, negedge PRESETn) - if (~PRESETn) TransmitFIFOWriteIncrement <= 0; + if (~PRESETn) TransmitFIFOWriteIncrement <= 1'b0; else TransmitFIFOWriteIncrement <= (Memwrite & (Entry == 8'h48) & ~TransmitFIFOWriteFull & TransmitInactive); always_ff @(posedge PCLK, negedge PRESETn) - if (~PRESETn) ReceiveFIFOReadIncrement <= 0; + if (~PRESETn) ReceiveFIFOReadIncrement <= 1'b0; else ReceiveFIFOReadIncrement <= ((Entry == 8'h4C) & ~ReceiveFIFOReadEmpty & PSEL & ~ReceiveFIFOReadIncrement); // Tx/Rx FIFOs @@ -233,14 +249,14 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( ReceiveData[7:0], ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty, RecieveWriteMark, RecieveReadMark); always_ff @(posedge PCLK, negedge PRESETn) - if (~PRESETn) TransmitFIFOReadEmptyDelay <= 1; + if (~PRESETn) TransmitFIFOReadEmptyDelay <= 1'b1; else if (SCLKenable) TransmitFIFOReadEmptyDelay <= TransmitFIFOReadEmpty; always_ff @(posedge PCLK, negedge PRESETn) - if (~PRESETn) ReceiveShiftFullDelay <= 0; + if (~PRESETn) ReceiveShiftFullDelay <= 1'b0; else if (SCLKenable) ReceiveShiftFullDelay <= ReceiveShiftFull; always_ff @(posedge PCLK, negedge PRESETn) - if (~PRESETn) ReceiveShiftFullDelayPCLK <= 0; + if (~PRESETn) ReceiveShiftFullDelayPCLK <= 1'b0; else if (SCLKenableEarly) ReceiveShiftFullDelayPCLK <= ReceiveShiftFull; assign TransmitShiftRegLoad = ~TransmitShiftEmpty & ~Active | (((ChipSelectMode == 2'b10) & ~|(Delay1[15:8])) & ((ReceiveShiftFullDelay | ReceiveShiftFull) & ~SampleEdge & ~TransmitFIFOReadEmpty)); @@ -399,12 +415,11 @@ module SynchFIFO #(parameter M=3, N=8)( // 2^M entries of N bits // write and read are enabled always_ff @(posedge PCLK, negedge PRESETn) if (~PRESETn) begin - rptr <= 0; - wptr <= 0; + rptr <= '0; + wptr <= '0; wfull <= 1'b0; rempty <= 1'b1; - end - else begin + end else begin if (wen) begin wfull <= ({~wptrnext[M], wptrnext[M-1:0]} == rptr); wptr <= wptrnext; @@ -429,13 +444,13 @@ module TransmitShiftFSM( output logic TransmitShiftEmpty); always_ff @(posedge PCLK, negedge PRESETn) - if (~PRESETn) TransmitShiftEmpty <= 1; + if (~PRESETn) TransmitShiftEmpty <= 1'b1; else if (TransmitShiftEmpty) begin - if (TransmitFIFOReadEmpty | (~TransmitFIFOReadEmpty & (ReceivePenultimateFrame & Active0))) TransmitShiftEmpty <= 1; - else if (~TransmitFIFOReadEmpty) TransmitShiftEmpty <= 0; + if (TransmitFIFOReadEmpty | (~TransmitFIFOReadEmpty & (ReceivePenultimateFrame & Active0))) TransmitShiftEmpty <= 1'b1; + else if (~TransmitFIFOReadEmpty) TransmitShiftEmpty <= 1'b0; end else begin - if (ReceivePenultimateFrame & Active0) TransmitShiftEmpty <= 1; - else TransmitShiftEmpty <= 0; + if (ReceivePenultimateFrame & Active0) TransmitShiftEmpty <= 1'b1; + else TransmitShiftEmpty <= 1'b0; end endmodule diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv index 94a587d9f6..f93795be53 100644 --- a/src/uncore/uartPC16550D.sv +++ b/src/uncore/uartPC16550D.sv @@ -52,6 +52,16 @@ module uartPC16550D #(parameter UART_PRESCALE) ( output logic SOUT, RTSb, DTRb, OUT1b, OUT2b // UART external serial and flow-control outputs ); + // register map + localparam UART_DLL_RBR = 3'b000; + localparam UART_DLM_IER = 3'b001; + localparam UART_IIR = 3'b010; + localparam UART_LCR = 3'b011; + localparam UART_MCR = 3'b100; + localparam UART_LSR = 3'b101; + localparam UART_MSR = 3'b110; + localparam UART_SCR = 3'b111; + // transmit and receive states typedef enum logic [1:0] {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype; @@ -150,35 +160,35 @@ module uartPC16550D #(parameter UART_PRESCALE) ( if (~MEMWb) begin /* verilator lint_off CASEINCOMPLETE */ case (A) - 3'b000: if (DLAB) DLL <= Din; // else TXHR <= Din; // TX handled in TX register/FIFO section - 3'b001: if (DLAB) DLM <= Din; else IER <= Din[3:0]; - 3'b010: FCR <= {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing - 3'b011: LCR <= Din; - 3'b100: MCR <= Din[4:0]; - 3'b111: SCR <= Din; + UART_DLL_RBR: if (DLAB) DLL <= Din; // else TXHR <= Din; // TX handled in TX register/FIFO section + UART_DLM_IER: if (DLAB) DLM <= Din; else IER <= Din[3:0]; + UART_IIR: FCR <= {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing + UART_LCR: LCR <= Din; + UART_MCR: MCR <= Din[4:0]; + UART_SCR: SCR <= Din; endcase /* verilator lint_on CASEINCOMPLETE */ end // Line Status Register (8.6.3) // Ben 6/9/21 I don't like how this is a register. A lot of the individual bits have clocked components, so this just adds unecessary delay. - if (~MEMWb & (A == 3'b101)) + if (~MEMWb & (A == UART_LSR)) LSR[6:1] <= Din[6:1]; // recommended only for test, see 8.6.3 else begin LSR[0] <= rxdataready; // Data ready - LSR[1] <= (LSR[1] | RXBR[10]) & ~squashRXerrIP;; // overrun error - LSR[2] <= (LSR[2] | RXBR[9]) & ~squashRXerrIP; // parity error - LSR[3] <= (LSR[3] | RXBR[8]) & ~squashRXerrIP; // framing error - LSR[4] <= (LSR[4] | rxbreak) & ~squashRXerrIP; // break indicator + LSR[1] <= (LSR[1] | RXBR[10]) & ~squashRXerrIP; // overrun error + LSR[2] <= (LSR[2] | RXBR[9]) & ~squashRXerrIP; // parity error + LSR[3] <= (LSR[3] | RXBR[8]) & ~squashRXerrIP; // framing error + LSR[4] <= (LSR[4] | rxbreak) & ~squashRXerrIP; // break indicator LSR[5] <= THRE; // THRE LSR[6] <= ~txsrfull & THRE; // TEMT - if (rxfifohaserr) LSR[7] <= 1; // any bits in FIFO have error + if (rxfifohaserr) LSR[7] <= 1'b1; // any bits in FIFO have error end // Modem Status Register (8.6.8) - if (~MEMWb & (A == 3'b110)) + if (~MEMWb & (A == UART_MSR)) MSR <= Din[3:0]; - else if (~MEMRb & (A == 3'b110)) + else if (~MEMRb & (A == UART_MSR)) MSR <= 4'b0; // Reading MSR clears the flags in MSR bits 3:0 else begin MSR[0] <= MSR[0] | CTSb2 ^ CTSbsync; // Delta Clear to Send @@ -187,18 +197,18 @@ module uartPC16550D #(parameter UART_PRESCALE) ( MSR[3] <= MSR[3] | DCDb2 ^ DCDbsync; // Delta Data Carrier Detect end end + always_comb if (~MEMRb) case (A) - 3'b000: if (DLAB) Dout = DLL; else Dout = RBR[7:0]; - 3'b001: if (DLAB) Dout = DLM; else Dout = {4'b0, IER[3:0]}; - 3'b010: Dout = {{2{fifoenabled}}, 2'b00, intrID[2:0], ~intrpending}; // Read only Interupt Ident Register - 3'b011: Dout = LCR; - 3'b100: Dout = {3'b000, MCR}; - 3'b101: Dout = LSR; - // 3'b110: Dout = {~CTSbsync, ~DSRbsync, ~RIbsync, ~DCDbsync, MSR[3:0]}; - 3'b110: Dout = {~DCDbsync, ~RIbsync, ~DSRbsync, ~CTSbsync, MSR[3:0]}; - 3'b111: Dout = SCR; + UART_DLL_RBR: if (DLAB) Dout = DLL; else Dout = RBR[7:0]; + UART_DLM_IER: if (DLAB) Dout = DLM; else Dout = {4'b0, IER[3:0]}; + UART_IIR: Dout = {{2{fifoenabled}}, 2'b00, intrID[2:0], ~intrpending}; // Read only Interupt Ident Register + UART_LCR: Dout = LCR; + UART_MCR: Dout = {3'b000, MCR}; + UART_LSR: Dout = LSR; + UART_MSR: Dout = {~DCDbsync, ~RIbsync, ~DSRbsync, ~CTSbsync, MSR[3:0]}; + UART_SCR: Dout = SCR; endcase else Dout = 8'b0; @@ -215,7 +225,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( always_ff @(posedge PCLK, negedge PRESETn) if (~PRESETn) begin baudcount <= 1; - baudpulse <= 0; + baudpulse <= 1'b0; end else if (~MEMWb & DLAB & (A == 3'b0 | A == 3'b1)) begin baudcount <= 1; end else begin @@ -240,18 +250,18 @@ module uartPC16550D #(parameter UART_PRESCALE) ( always_ff @(posedge PCLK, negedge PRESETn) if (~PRESETn) begin - rxoversampledcnt <= 0; + rxoversampledcnt <= '0; rxstate <= UART_IDLE; - rxbitsreceived <= 0; - rxtimeoutcnt <= 0; + rxbitsreceived <= '0; + rxtimeoutcnt <= '0; end else begin if (rxstate == UART_IDLE & ~SINsync) begin // got start bit rxstate <= UART_ACTIVE; - rxoversampledcnt <= 0; - rxbitsreceived <= 0; - if (~rxfifotimeout) rxtimeoutcnt <= 0; // reset timeout when new character is arriving. Jacob Pease: Only if the timeout was not already reached. p.16 PC16550D.pdf + rxoversampledcnt <= '0; + rxbitsreceived <= '0; + if (~rxfifotimeout) rxtimeoutcnt <= '0; // reset timeout when new character is arriving. Jacob Pease: Only if the timeout was not already reached. p.16 PC16550D.pdf end else if (rxbaudpulse & (rxstate == UART_ACTIVE)) begin - rxoversampledcnt <= rxoversampledcnt + 1; // 16x oversampled counter + rxoversampledcnt <= rxoversampledcnt + 4'b1; // 16x oversampled counter if (rxcentered) rxbitsreceived <= rxbitsreceived + 1; if (rxbitsreceived == rxbitsexpected) rxstate <= UART_DONE; // pulse rxdone for a cycle end else if (rxstate == UART_DONE | rxstate == UART_BREAK) begin @@ -259,7 +269,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( else rxstate <= UART_IDLE; end // timeout counting - if (~MEMRb & A == 3'b000 & ~DLAB) rxtimeoutcnt <= 0; // reset timeout on read + if (~MEMRb & A == 3'b000 & ~DLAB) rxtimeoutcnt <= '0; // reset timeout on read else if (fifoenabled & ~rxfifoempty & rxbaudpulse & ~rxfifotimeout) rxtimeoutcnt <= rxtimeoutcnt+1; // may not be right end @@ -295,32 +305,32 @@ module uartPC16550D #(parameter UART_PRESCALE) ( // receive FIFO and register always_ff @(posedge PCLK) if (~PRESETn) begin - rxfifohead <= 0; rxfifotail <= 0; rxdataready <= 0; RXBR <= 0; + rxfifohead <= '0; rxfifotail <= '0; rxdataready <= 1'b0; RXBR <= '0; end else begin if (~MEMWb & (A == 3'b010) & Din[1]) begin - rxfifohead <= 0; rxfifotail <= 0; rxdataready <= 0; + rxfifohead <= '0; rxfifotail <= '0; rxdataready <= 1'b0; end else if (rxstate == UART_DONE) begin RXBR <= {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; // load recevive buffer register - if (rxoverrunerr) $warning("UART RX Overrun Err\n"); - if (rxparityerr) $warning("UART RX Parity Err\n"); - if (rxframingerr) $warning("UART RX Framing Err\n"); +// if (rxoverrunerr) $warning("UART RX Overrun Err\n"); +// if (rxparityerr) $warning("UART RX Parity Err\n"); +// if (rxframingerr) $warning("UART RX Framing Err\n"); if (fifoenabled) begin rxfifo[rxfifohead] <= {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; - rxfifohead <= rxfifohead + 1; + rxfifohead <= rxfifohead + 1'b1; end - rxdataready <= 1; + rxdataready <= 1'b1; end else if (~MEMRb & A == 3'b000 & ~DLAB) begin // reading RBR updates ready / pops fifo if (fifoenabled) begin if (~rxfifoempty) rxfifotail <= rxfifotail + 1; - // if (rxfifoempty) rxdataready <= 0; - if (rxfifoentries == 1) rxdataready <= 0; // When reading the last entry, data ready becomes zero + // if (rxfifoempty) rxdataready <= 1'b0; + if (rxfifoentries == 1) rxdataready <= 1'b0; // When reading the last entry, data ready becomes zero end else begin - rxdataready <= 0; + rxdataready <= 1'b0; RXBR <= {1'b0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode) end end else if (~MEMWb & A == 3'b010) // writes to FIFO Control Register if (Din[1] | ~Din[0]) begin // rx FIFO reset or FIFO disable clears FIFO contents - rxfifohead <= 0; rxfifotail <= 0; + rxfifohead <= '0; rxfifotail <= '0; end end @@ -354,9 +364,9 @@ module uartPC16550D #(parameter UART_PRESCALE) ( // receive buffer register and ready bit always_ff @(posedge PCLK, negedge PRESETn) // track rxrdy for DMA mode (FCR3 = FCR0 = 1) - if (~PRESETn) rxfifodmaready <= 0; - else if (rxfifotriggered | rxfifotimeout) rxfifodmaready <= 1; - else if (rxfifoempty) rxfifodmaready <= 0; + if (~PRESETn) rxfifodmaready <= 1'b0; + else if (rxfifotriggered | rxfifotimeout) rxfifodmaready <= 1'b1; + else if (rxfifoempty) rxfifodmaready <= 1'b0; always_comb if (fifoenabled) begin @@ -375,17 +385,17 @@ module uartPC16550D #(parameter UART_PRESCALE) ( always_ff @(posedge PCLK, negedge PRESETn) if (~PRESETn) begin - txoversampledcnt <= 0; + txoversampledcnt <= '0; txstate <= UART_IDLE; - txbitssent <= 0; + txbitssent <= '0; end else if ((txstate == UART_IDLE) & txsrfull) begin // start transmitting txstate <= UART_ACTIVE; - txoversampledcnt <= 1; - txbitssent <= 0; + txoversampledcnt <= 4'b1; + txbitssent <= '0; end else if (txbaudpulse & (txstate == UART_ACTIVE)) begin - txoversampledcnt <= txoversampledcnt + 1; + txoversampledcnt <= txoversampledcnt + 1'b1; if (txnextbit) begin // transmit at end of phase - txbitssent <= txbitssent+1; + txbitssent <= txbitssent + 1'b1; if (txbitssent == txbitsexpected) txstate <= UART_DONE; end end else if (txstate == UART_DONE) begin @@ -423,17 +433,17 @@ module uartPC16550D #(parameter UART_PRESCALE) ( // registers & FIFO always_ff @(posedge PCLK, negedge PRESETn) if (~PRESETn) begin - txfifohead <= 0; txfifotail <= 0; txhrfull <= 0; txsrfull <= 0; TXHR <= 0; txsr <= 12'hfff; + txfifohead <= '0; txfifotail <= '0; txhrfull <= 1'b0; txsrfull <= 1'b0; TXHR <= '0; txsr <= 12'hfff; end else if (~MEMWb & (A == 3'b010) & Din[2]) begin - txfifohead <= 0; txfifotail <= 0; + txfifohead <= '0; txfifotail <= '0; end else begin if (~MEMWb & A == 3'b000 & ~DLAB) begin // writing transmit holding register or fifo if (fifoenabled) begin txfifo[txfifohead] <= Din; - txfifohead <= txfifohead + 1; + txfifohead <= txfifohead + 4'b1; end else begin TXHR <= Din; - txhrfull <= 1; + txhrfull <= 1'b1; end $write("%c",Din); // for testbench end @@ -442,18 +452,18 @@ module uartPC16550D #(parameter UART_PRESCALE) ( if (~txfifoempty & ~txsrfull) begin txsr <= txdata; txfifotail <= txfifotail+1; - txsrfull <= 1; + txsrfull <= 1'b1; end end else if (txhrfull) begin txsr <= txdata; - txhrfull <= 0; - txsrfull <= 1; + txhrfull <= 1'b0; + txsrfull <= 1'b1; end - end else if (txstate == UART_DONE) txsrfull <= 0; // done transmitting shift register + end else if (txstate == UART_DONE) txsrfull <= 1'b0; // done transmitting shift register else if (txstate == UART_ACTIVE & txnextbit) txsr <= {txsr[10:0], 1'b1}; // shift txhr if (!MEMWb & A == 3'b010) // writes to FIFO control register if (Din[2] | ~Din[0]) begin // tx FIFO reste or FIFO disable clears FIFO contents - txfifohead <= 0; txfifotail <= 0; + txfifohead <= '0; txfifotail <= '0; end end @@ -483,9 +493,9 @@ module uartPC16550D #(parameter UART_PRESCALE) ( // transmit buffer ready bit always_ff @(posedge PCLK, negedge PRESETn) // track txrdy for DMA mode (FCR3 = FCR0 = 1) - if (~PRESETn) txfifodmaready <= 0; - else if (txfifoempty) txfifodmaready <= 1; - else if (txfifofull) txfifodmaready <= 0; + if (~PRESETn) txfifodmaready <= 1'b0; + else if (txfifoempty) txfifodmaready <= 1'b1; + else if (txfifofull) txfifodmaready <= 1'b0; always_comb if (fifoenabled & fifodmamodesel) TXRDYb = ~txfifodmaready; @@ -493,7 +503,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( // Transmitter pin assign SOUTbit = txsr[11]; // transmit most significant bit - assign SOUT = loop ? 1 : (LCR[6] ? 0 : SOUTbit); // tied to 1 during loopback or 0 during break + assign SOUT = loop ? 1 : (LCR[6] ? '0 : SOUTbit); // tied to 1 during loopback or 0 during break /////////////////////////////////////////// // interrupts @@ -509,7 +519,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( // IIR: interrupt priority (Table 5) // set intrID based on highest priority pending interrupt source; otherwise, no interrupt is pending always_comb begin - intrpending = 1; + intrpending = 1'b1; if (RXerrIP & IER[2]) intrID = 3'b011; else if (rxdataavailintr & IER[0]) intrID = 3'b010; else if (rxfifotimeout & fifoenabled & IER[0]) intrID = 3'b110; @@ -517,7 +527,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( else if (modemstatusintr & IER[3]) intrID = 3'b000; else begin intrID = 3'b000; - intrpending = 0; + intrpending = 1'b0; end end always_ff @(posedge PCLK) INTR <= intrpending; // prevent glitches on interrupt pin @@ -549,10 +559,10 @@ module uartPC16550D #(parameter UART_PRESCALE) ( assign fifodmamodesel = FCR[3]; always_comb case (FCR[7:6]) - 2'b00: rxfifotriggerlevel = 1; - 2'b01: rxfifotriggerlevel = 4; - 2'b10: rxfifotriggerlevel = 8; - 2'b11: rxfifotriggerlevel = 14; + 2'b00: rxfifotriggerlevel = 4'd1; + 2'b01: rxfifotriggerlevel = 4'd4; + 2'b10: rxfifotriggerlevel = 4'd8; + 2'b11: rxfifotriggerlevel = 4'd14; endcase endmodule From be15a11622325f1b666ba1a7c5638e55302e0e30 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 21 Apr 2024 08:38:13 -0700 Subject: [PATCH 18/31] Fixed conflicts on getenv --- src/generic/mem/rom1p1r.sv | 15 ++++++++------- testbench/testbench.sv | 15 ++++++++------- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index 229e481eb3..17485af8a9 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -26,13 +26,6 @@ // This model actually works correctly with vivado. -`ifdef VERILATOR - import "DPI-C" function string getenvval(input string env_name); - string WALLY_DIR = getenvval("WALLY"); -`else - string WALLY_DIR = "$WALLY"; -`endif - module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0) (input logic clk, input logic ce, @@ -40,6 +33,14 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0) output logic [DATA_WIDTH-1:0] dout ); +`ifdef VERILATOR + import "DPI-C" function string getenvval(input string env_name); +// string WALLY_DIR = getenvval("WALLY"); + string WALLY_DIR = "~/cvw"; +`else + string WALLY_DIR = "$WALLY"; +`endif + // Core Memory bit [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; diff --git a/testbench/testbench.sv b/testbench/testbench.sv index a126b42095..a92af4a081 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -33,12 +33,6 @@ `include "idv/idv.svh" `endif -`ifdef VERILATOR - import "DPI-C" function string getenvval(input string env_name); - string RISCV_DIR = getenvval("RISCV"); // "/opt/riscv"; -`else - string RISCV_DIR = "$RISCV"; // "/opt/riscv"; -`endif import cvw::*; @@ -57,7 +51,14 @@ module testbench; import idvApiPkg::*; `endif -`include "parameter-defs.vh" + `ifdef VERILATOR + import "DPI-C" function string getenvval(input string env_name); + string RISCV_DIR = getenvval("RISCV"); // "/opt/riscv"; + `else + string RISCV_DIR = "$RISCV"; // "/opt/riscv"; + `endif + + `include "parameter-defs.vh" logic clk; logic reset_ext, reset; From 1759c920bbba29f9a312a0d654b56203f923bc9d Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 21 Apr 2024 08:38:59 -0700 Subject: [PATCH 19/31] improved regression comments --- bin/regression-wally | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 7622e7aea0..c67366ee16 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -35,13 +35,13 @@ tests = [ ["rv64i", ["arch64i"]] ] - -# Separate test for full buildroot run +# Separate test for short buildroot run through OpenSBI UART output tests_buildrootshort = [ ["buildroot", ["buildroot"], [f"+INSTR_LIMIT=1400000"], # Instruction limit gets to first OpenSBI UART output "OpenSBI v", "buildroot_uart.out"] ] +# Separate test for full buildroot run tests_buildrootboot = [ ["buildroot", ["buildroot"], [f"+INSTR_LIMIT=600000000"], # boot entire buildroot Linux to login prompt "WallyHostname login: ", "buildroot_uart.out"] From 3f195884e9c00fd0e96e628a396df1c5c78e436d Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 21 Apr 2024 08:40:11 -0700 Subject: [PATCH 20/31] Defined bit sizes more precisely to help VCS lint and conform to coding style --- src/cache/cache.sv | 7 +- src/cache/cacheLRU.sv | 2 +- src/cache/cacheway.sv | 8 +- src/ebu/ahbinterface.sv | 4 +- src/ebu/ebu.sv | 12 +-- src/fpu/fctrl.sv | 4 +- src/fpu/fdivsqrt/fdivsqrtexpcalc.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtfgen2.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtfgen4.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtiter.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtstage2.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtstage4.sv | 2 +- src/fpu/fli.sv | 6 +- src/fpu/fma/fmaalign.sv | 2 +- src/fpu/fma/fmaexpadd.sv | 2 +- src/fpu/fpu.sv | 4 +- src/fpu/fregfile.sv | 2 +- src/fpu/fround.sv | 108 +++++++++++++++++++++++++++ src/fpu/postproc/cvtshiftcalc.sv | 2 +- src/fpu/postproc/divshiftcalc.sv | 2 +- src/fpu/postproc/fmashiftcalc.sv | 4 +- src/fpu/postproc/round.sv | 6 +- src/fpu/postproc/specialcase.sv | 2 +- src/fpu/unpackinput.sv | 30 ++++---- src/generic/binencoder.sv | 2 +- src/generic/flop/flopenr.sv | 2 +- src/generic/flop/flopenrc.sv | 4 +- src/generic/flop/flopr.sv | 2 +- src/generic/mem/ram2p1r1wbe.sv | 2 +- src/generic/onehotdecoder.sv | 2 +- src/hazard/hazard.sv | 2 +- src/ieu/bmu/bitmanipalu.sv | 10 +-- src/ieu/bmu/cnt.sv | 4 +- src/ieu/bmu/popcnt.sv | 2 +- src/ieu/controller.sv | 34 ++++----- src/ieu/datapath.sv | 2 +- src/ieu/extend.sv | 2 +- src/ieu/regfile.sv | 2 +- src/ieu/sha/sha512_32.sv | 4 +- src/ifu/bpred/bpred.sv | 2 +- src/ifu/bpred/icpred.sv | 6 +- src/ifu/bpred/localrepairbp.sv | 2 +- src/ifu/decompress.sv | 32 ++++---- src/ifu/ifu.sv | 35 ++++----- src/lsu/align.sv | 12 +-- src/lsu/lrsc.sv | 4 +- src/lsu/lsu.sv | 43 ++++++----- src/lsu/subwordwrite.sv | 1 + src/lsu/swbytemask.sv | 7 +- src/mdu/mdu.sv | 6 +- src/mmu/hptw.sv | 6 +- src/mmu/mmu.sv | 16 ++-- src/mmu/pmachecker.sv | 2 +- src/mmu/pmpadrdec.sv | 2 +- src/mmu/tlb/vm64check.sv | 4 +- src/privileged/csr.sv | 28 +++---- src/privileged/csrc.sv | 23 +++--- src/privileged/csrm.sv | 22 +++--- src/privileged/csrs.sv | 24 +++--- src/privileged/csrsr.sv | 51 ++++++------- src/privileged/csru.sv | 10 +-- src/privileged/privdec.sv | 2 +- src/privileged/trap.sv | 46 ++++++------ src/uncore/ahbapbbridge.sv | 4 +- src/uncore/rom_ahb.sv | 2 +- src/uncore/uncore.sv | 14 ++-- src/wally/wallypipelinedcore.sv | 40 +++++----- 69 files changed, 429 insertions(+), 316 deletions(-) create mode 100644 src/fpu/fround.sv diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 2edf867e2e..e1a0f3556a 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -215,9 +215,10 @@ module cache import cvw::*; #(parameter cvw_t P, assign FlushWayFlag = FlushWay[NUMWAYS-1]; end // block: flushlogic else begin:flushlogic // I$ is never flushed because it is never dirty - assign FlushWay = 0; - assign FlushWayFlag = 0; - assign FlushAdrFlag = 0; + assign FlushWay = '0; + assign FlushWayFlag = 1'b0; + assign FlushAdrFlag = 1'b0; + assign FlushAdr = '0; end ///////////////////////////////////////////////////////////////////////////////////////////// diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 0af178c94b..48f5bb5860 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -146,7 +146,7 @@ module cacheLRU // Move to = to keep Verilator happy and simulator running fast always_ff @(posedge clk) begin if (reset | (InvalidateCache & ~FlushStage)) - for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = 0; // exclusion-tag: initialize + for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = '0; // exclusion-tag: initialize else if(CacheEn) begin // Because we are using blocking assignments, change to LRUMemory must occur after LRUMemory is used so we get the proper value if(LRUWriteEn & (PAdr == CacheSetTag)) CurrLRU = NextLRU; diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 8f647fff27..44092b0423 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -149,19 +149,19 @@ module cacheway import cvw::*; #(parameter cvw_t P, end // AND portion of distributed read multiplexers - assign ReadDataLineWay = SelectedWay ? ReadDataLine : 0; // AND part of AO mux. + assign ReadDataLineWay = SelectedWay ? ReadDataLine : '0; // AND part of AO mux. ///////////////////////////////////////////////////////////////////////////////////////////// // Valid Bits ///////////////////////////////////////////////////////////////////////////////////////////// always_ff @(posedge clk) begin // Valid bit array, - if (reset) ValidBits <= 0; + if (reset) ValidBits <= '0; if(CacheEn) begin ValidWay <= ValidBits[CacheSetTag]; - if(InvalidateCache) ValidBits <= 0; // exclusion-tag: dcache invalidateway + if(InvalidateCache) ValidBits <= '0; // exclusion-tag: dcache invalidateway else if (SetValidEN) ValidBits[CacheSetData] <= SetValidWay; - else if (ClearValidEN) ValidBits[CacheSetData] <= 0; // exclusion-tag: icache ClearValidBits + else if (ClearValidEN) ValidBits[CacheSetData] <= '0; // exclusion-tag: icache ClearValidBits end end diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv index 2f4944303a..8852b52c30 100644 --- a/src/ebu/ahbinterface.sv +++ b/src/ebu/ahbinterface.sv @@ -62,8 +62,8 @@ module ahbinterface #( flop #(XLEN) wdreg(HCLK, WriteData, HWDATA); flop #(XLEN/8) HWSTRBReg(HCLK, ByteMask, HWSTRB); end else begin - assign HWDATA = 0; - assign HWSTRB = 0; + assign HWDATA = '0; + assign HWSTRB = '0; end busfsm #(~LSU) busfsm(.HCLK, .HRESETn, .Flush, .BusRW, .BusAtomic, diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index 356f955f34..1b6c0a1fae 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -111,13 +111,13 @@ module ebu import cvw::*; #(parameter cvw_t P) ( .HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYIn(HREADY)); // output mux //*** switch to structural implementation - assign HADDR = LSUSelect ? LSUHADDROut : IFUSelect ? IFUHADDROut : 0; - assign HSIZE = LSUSelect ? LSUHSIZEOut : IFUSelect ? IFUHSIZEOut: 0; - assign HBURST = LSUSelect ? LSUHBURSTOut : IFUSelect ? IFUHBURSTOut : 0; // If doing memory accesses, use LSUburst, else use Instruction burst. - assign HTRANS = LSUSelect ? LSUHTRANSOut : IFUSelect ? IFUHTRANSOut: 0; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise - assign HWRITE = LSUSelect ? LSUHWRITEOut : 0; + assign HADDR = LSUSelect ? LSUHADDROut : IFUSelect ? IFUHADDROut : '0; + assign HSIZE = LSUSelect ? LSUHSIZEOut : IFUSelect ? IFUHSIZEOut: '0; + assign HBURST = LSUSelect ? LSUHBURSTOut : IFUSelect ? IFUHBURSTOut : '0; // If doing memory accesses, use LSUburst, else use Instruction burst. + assign HTRANS = LSUSelect ? LSUHTRANSOut : IFUSelect ? IFUHTRANSOut: '0; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise + assign HWRITE = LSUSelect ? LSUHWRITEOut : '0; assign HPROT = 4'b0011; // not used; see Section 3.7 - assign HMASTLOCK = 0; // no locking supported + assign HMASTLOCK = 1'b0; // no locking supported // data phase muxing. This would be a mux if IFU wrote data. assign HWDATA = LSUHWDATA; diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index a6c7614944..e9efc8e764 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -268,7 +268,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( // 11 - quad if (P.FPSIZES == 1) - assign FmtD = 0; + assign FmtD = 1'b0; else if (P.FPSIZES == 2)begin logic [1:0] FmtTmp; assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : (~OpD[6]&(&OpD[2:0])) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : Funct7D[1:0]; @@ -359,7 +359,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( // Integer division on FPU divider if (P.M_SUPPORTED & P.IDIV_ON_FPU) assign IDivStartE = IntDivE; - else assign IDivStartE = 0; + else assign IDivStartE = 1'b0; // E/M pipleine register flopenrc #(14+int'(P.FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM, diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index d24b490ab0..a20d1871d6 100644 --- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -31,7 +31,7 @@ module fdivsqrtexpcalc import cvw::*; #(parameter cvw_t P) ( input logic [P.FMTBITS-1:0] Fmt, input logic [P.NE-1:0] Xe, Ye, // input exponents input logic Sqrt, - input logic [P.DIVBLEN-1:0] ell, m, // number of leading 0s in Xe and Ye + input logic [P.DIVBLEN-1:0] ell, m, // number of leading 0s in Xe and Ye output logic [P.NE+1:0] Ue // result exponent ); diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv index 732bd6f51b..bc9dce536f 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv @@ -37,7 +37,7 @@ module fdivsqrtfgen2 import cvw::*; #(parameter cvw_t P) ( // Generate for both positive and negative quotient digits assign FP = ~(U << 1) & C; assign FN = (UM << 1) | (C & ~(C << 2)); - assign FZ = 0; + assign FZ = '0; always_comb // Choose which adder input will be used if (up) F = FP; diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv index f1c2e3281a..a04523e582 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv @@ -37,7 +37,7 @@ module fdivsqrtfgen4 import cvw::*; #(parameter cvw_t P) ( // Generate for both positive and negative digits assign F2 = (~U << 2) & (C << 2); // assign F1 = ~(U << 1) & C; - assign F0 = 0; + assign F0 = '0; assign FN1 = (UM << 1) | (C & ~(C << 3)); assign FN2 = (UM << 2) | ((C << 2) & ~(C << 4)); diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv index c942db450d..4bfcebcd15 100644 --- a/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -81,7 +81,7 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) ( // C register/initialization mux: C = -R: // C = -4 = 00.000000... (in Q2.DIVb) for radix 4, C = -2 = 10.000000... for radix2 - if(P.RADIX == 4) assign initC = 0; + if(P.RADIX == 4) assign initC = '0; else assign initC = {2'b10, {{P.DIVb{1'b0}}}}; mux2 #(P.DIVb+2) cmux(C[P.DIVCOPIES], initC, IFDivStartE, NextC); flopen #(P.DIVb+2) creg(clk, FDivBusyE, NextC, C[0]); diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 78a50d0c35..c3954bc0a9 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -121,7 +121,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( else IntDivResultM = {(P.XLEN){1'b1}}; end else if (ALTBM) begin // Numerator is small if (RemOpM) IntDivResultM = AM; - else IntDivResultM = 0; + else IntDivResultM = '0; end else IntDivResultM = PreIntResultM[P.XLEN-1:0]; // sign extend result for W64 diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 0f0273c250..45d50dac3f 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -145,7 +145,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( assign DivXShifted = DivX; end end else begin - assign ISpecialCaseE = 0; + assign ISpecialCaseE = 1'b0; end ////////////////////////////////////////////////////// diff --git a/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv index a0a552ac85..c3d6e210cd 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -58,7 +58,7 @@ module fdivsqrtstage2 import cvw::*; #(parameter cvw_t P) ( // Divisor multiple always_comb if (up) Dsel = DBar; - else if (uz) Dsel = 0; + else if (uz) Dsel = '0; else Dsel = D; // un // Residual Update diff --git a/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv index d879e0f902..856273a5e1 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -68,7 +68,7 @@ module fdivsqrtstage4 import cvw::*; #(parameter cvw_t P) ( case (udigit) 4'b1000: Dsel = DBar2; 4'b0100: Dsel = DBar; - 4'b0000: Dsel = 0; + 4'b0000: Dsel = '0; 4'b0010: Dsel = D; 4'b0001: Dsel = D2; default: Dsel = 'x; diff --git a/src/fpu/fli.sv b/src/fpu/fli.sv index c352d7a5ca..cf3b736d7d 100644 --- a/src/fpu/fli.sv +++ b/src/fpu/fli.sv @@ -80,7 +80,7 @@ module fli import cvw::*; #(parameter cvw_t P) ( endcase end assign HImmBox = {{(P.FLEN-16){1'b1}}, HImm}; // NaN-box HImm - end else assign HImmBox = 0; + end else assign HImmBox = '0; //////////////////////////// // single @@ -168,7 +168,7 @@ module fli import cvw::*; #(parameter cvw_t P) ( endcase end assign DImmBox = {{(P.FLEN-64){1'b1}}, DImm}; // NaN-box DImm - end else assign DImmBox = 0; + end else assign DImmBox = '0; //////////////////////////// // double @@ -213,7 +213,7 @@ module fli import cvw::*; #(parameter cvw_t P) ( endcase end assign QImmBox = QImm; // NaN-box QImm trivial because Q is longest format - end else assign QImmBox = 0; + end else assign QImmBox = '0; mux4 #(P.FLEN) flimux(SImmBox, DImmBox, HImmBox, QImmBox, Fmt, Imm); // select immediate based on format diff --git a/src/fpu/fma/fmaalign.sv b/src/fpu/fma/fmaalign.sv index 9001742e48..c1d22ec48f 100644 --- a/src/fpu/fma/fmaalign.sv +++ b/src/fpu/fma/fmaalign.sv @@ -74,7 +74,7 @@ module fmaalign import cvw::*; #(parameter cvw_t P) ( // | 53'b0 | 106'b(product) | 1'b0 | // | addnend | end else if (KillZ) begin - ZmShifted = 0; + ZmShifted = '0; ASticky = ~ZZero; // If the Addend is shifted right diff --git a/src/fpu/fma/fmaexpadd.sv b/src/fpu/fma/fmaexpadd.sv index 50b85ded0a..06ac7e2906 100644 --- a/src/fpu/fma/fmaexpadd.sv +++ b/src/fpu/fma/fmaexpadd.sv @@ -37,6 +37,6 @@ module fmaexpadd import cvw::*; #(parameter cvw_t P) ( // kill the exponent if the product is zero - either X or Y is 0 assign PZero = XZero | YZero; - assign Pe = PZero ? 0 : ({2'b0, Xe} + {2'b0, Ye} - {2'b0, (P.NE)'(P.BIAS)}); + assign Pe = PZero ? '0 : ({2'b0, Xe} + {2'b0, Ye} - {2'b0, (P.NE)'(P.BIAS)}); endmodule diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index c97a12d327..36cc0be3b8 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -218,7 +218,7 @@ module fpu import cvw::*; #(parameter cvw_t P) ( // Select NAN-boxed value of Z = 0.0 in proper format for FMA for multiply X*Y+Z // For add and subtract, Z comes from second source operand - if(P.FPSIZES == 1) assign BoxedZeroE = 0; + if(P.FPSIZES == 1) assign BoxedZeroE = '0; else if(P.FPSIZES == 2) mux2 #(P.FLEN) fmulzeromux ({{P.FLEN-P.LEN1{1'b1}}, {P.LEN1{1'b0}}}, (P.FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes else if(P.FPSIZES == 3 | P.FPSIZES == 4) @@ -275,7 +275,7 @@ module fpu import cvw::*; #(parameter cvw_t P) ( flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, InstrD[19:15], Rs1E); flopenrc #(2) Fmt2EReg(clk, reset, FlushE, ~StallE, InstrD[26:25], Fmt2E); fli #(P) fli(.Rs1(Rs1E), .Fmt(Fmt2E), .Imm(FliResE)); - end else assign FliResE = 0; + end else assign FliResE = '0; // fmv.*.x: NaN Box SrcA to extend integer to requested FP size if(P.FPSIZES == 1) diff --git a/src/fpu/fregfile.sv b/src/fpu/fregfile.sv index 38a9da25e0..e907875a21 100644 --- a/src/fpu/fregfile.sv +++ b/src/fpu/fregfile.sv @@ -44,7 +44,7 @@ module fregfile #(parameter FLEN) ( // write occurs on falling edge of clock always_ff @(negedge clk) // or posedge reset) - if (reset) for(i=0; i<32; i++) rf[i] <= 0; + if (reset) for(i=0; i<32; i++) rf[i] <= '0; else if (we4) rf[a4] <= wd4; assign rd1 = rf[a1]; diff --git a/src/fpu/fround.sv b/src/fpu/fround.sv new file mode 100644 index 0000000000..7c4c9084bc --- /dev/null +++ b/src/fpu/fround.sv @@ -0,0 +1,108 @@ +/////////////////////////////////////////// +// fround.sv +// +// Written: David_Harris@hmc.edu +// Modified: 4/21/2024 +// +// Purpose: Floating-point round to integer for Zfa +// +// Documentation: RISC-V System on Chip Design Chapter 16 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module fround import cvw::*; #(parameter cvw_t P) ( + input logic Xs, // input's sign + input logic [P.NE-1:0] Xe, // input's exponent + input logic [P.NF:0] Xm, // input's fraction + input logic [P.FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half) +); + + logic [P.NE-2:0] Bias; + logic [P.NE-1:0] E; + + ////////////////////////////////////////// + // Determine exponent bias according to the format + ////////////////////////////////////////// + // *** replicated from fdivsqrt; find a way to share + + if (P.FPSIZES == 1) begin + assign Bias = (P.NE-1)'(P.BIAS); + + end else if (P.FPSIZES == 2) begin + assign Bias = Fmt ? (P.NE-1)'(P.BIAS) : (P.NE-1)'(P.BIAS1); + + end else if (P.FPSIZES == 3) begin + always_comb + case (Fmt) + P.FMT: Bias = (P.NE-1)'(P.BIAS); + P.FMT1: Bias = (P.NE-1)'(P.BIAS1); + P.FMT2: Bias = (P.NE-1)'(P.BIAS2); + default: Bias = 'x; + endcase + + end else if (P.FPSIZES == 4) begin + always_comb + case (Fmt) + 2'h3: Bias = (P.NE-1)'(P.Q_BIAS); + 2'h1: Bias = (P.NE-1)'(P.D_BIAS); + 2'h0: Bias = (P.NE-1)'(P.S_BIAS); + 2'h2: Bias = (P.NE-1)'(P.H_BIAS); + endcase + end + + // Unbiased exponent + assign E = Xe - Bias; + + ////////////////////////////////////////// + // Compute LSB, rounding bit and Sticky bit mask (TMask) + // if (E < 0) // negative exponents round to 0 or 1. + // L' = 0 // LSB = 0 + // if (E = -1) R' = 1, TMask = 0.1111...111 // if (E = -1) 0.5  X < 1. Round bit is 1 + // else R' = 0; TMask = 1.1111...111 // if (E < -1), X < 0.5. Round bit is 0 + // else // positive exponents truncate fraction and may add 1 + // IMask = 1.0000…000 >>> E // (in U1.Nf form); implies thermometer code generator + // TMask = ~(IMask >>> 1) // 0.01111…111 >> E + // HotE = IMask & ~(IMask << 1) // a 1 in column E, where 0 is the integer bit, + // // 1 is the most significant fractional bit, etc. + // HotEP1 = HotE >> 1 // a 1 in column E+1 + // L' = OR(Xm & HotE) // Xm[E], where Xm[0] is the integer bit, + // // Xm[1] is the most significant fractional bit, etc. + // R' = OR(Xm & HotEP1) // Xm[E+1] + // TRUNC = Xm & IMask // Truncated fraction, corresponds to truncated integer value + // RND = TRUNC + HotE // TRUNC + (1 >> E), corresponds to next integer + // T' = OR(Xm & TMask) // T’ = OR(Xm[E+2:Nf]) if E >= 0, OR(Xf) if E = -1, 1 if E < -1 + ////////////////////////////////////////// + + // Check if exponent is negative and -1 + assign Elt0 = (E < 0); + assign Eeqm1 = (E == -1); + + assign Rneg = Elt0; + mux2 + + // + // if (E = -1) R' = 1, TMask = 0.1111...111 // if (E = -1) 0.5  X < 1. Round bit is 1 + else R' = 0; TMask = 1.1111...111 // if (E < -1), X < 0.5. Round bit is 0 + + + mux + + +endmodule diff --git a/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv index 8b7587e49d..19993a996f 100644 --- a/src/fpu/postproc/cvtshiftcalc.sv +++ b/src/fpu/postproc/cvtshiftcalc.sv @@ -83,7 +83,7 @@ module cvtshiftcalc import cvw::*; #(parameter cvw_t P) ( P.FMT: ResNegNF = -($clog2(P.NF)+1)'(P.NF); P.FMT1: ResNegNF = -($clog2(P.NF)+1)'(P.NF1); P.FMT2: ResNegNF = -($clog2(P.NF)+1)'(P.NF2); - default: ResNegNF = 0; // Not used for floating-point so don't care, but convert to unsigned long has OutFmt = 11. + default: ResNegNF = '0; // Not used for floating-point so don't care, but convert to unsigned long has OutFmt = 11. endcase end else if (P.FPSIZES == 4) begin diff --git a/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv index b0335c7809..0a222d7249 100644 --- a/src/fpu/postproc/divshiftcalc.sv +++ b/src/fpu/postproc/divshiftcalc.sv @@ -65,7 +65,7 @@ module divshiftcalc import cvw::*; #(parameter cvw_t P) ( // if the shift amount is negative then don't shift (keep sticky bit) // need to multiply the early termination shift by LOGR*DIVCOPIES = left shift of log2(LOGR*DIVCOPIES) - assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[P.LOGNORMSHIFTSZ-1:0] : 0; + assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[P.LOGNORMSHIFTSZ-1:0] : '0; assign DivShiftAmt = DivResSubnorm ? DivSubnormShiftAmt : NormShift; // pre-shift the divider result for normalization diff --git a/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv index d6d9cec151..5c611a7e34 100644 --- a/src/fpu/postproc/fmashiftcalc.sv +++ b/src/fpu/postproc/fmashiftcalc.sv @@ -60,7 +60,7 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) ( end else if (P.FPSIZES == 3) begin always_comb begin case (Fmt) - P.FMT: BiasCorr = 0; + P.FMT: BiasCorr = '0; P.FMT1: BiasCorr = (P.NE+2)'(P.BIAS1-P.BIAS); P.FMT2: BiasCorr = (P.NE+2)'(P.BIAS2-P.BIAS); default: BiasCorr = 'x; @@ -70,7 +70,7 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) ( end else if (P.FPSIZES == 4) begin always_comb begin case (Fmt) - 2'h3: BiasCorr = 0; + 2'h3: BiasCorr = '0; 2'h1: BiasCorr = (P.NE+2)'(P.D_BIAS-P.Q_BIAS); 2'h0: BiasCorr = (P.NE+2)'(P.S_BIAS-P.Q_BIAS); 2'h2: BiasCorr = (P.NE+2)'(P.H_BIAS-P.Q_BIAS); diff --git a/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv index 9e2de23204..15c9b4538a 100644 --- a/src/fpu/postproc/round.sv +++ b/src/fpu/postproc/round.sv @@ -255,7 +255,7 @@ module round import cvw::*; #(parameter cvw_t P) ( // Determine if you add 1 case (Frm) 3'b000: CalcPlus1 = Guard & (Round|Sticky|LsbRes);//round to nearest even - 3'b001: CalcPlus1 = 0;//round to zero + 3'b001: CalcPlus1 = 1'b0;//round to zero 3'b010: CalcPlus1 = Ms;//round down 3'b011: CalcPlus1 = ~Ms;//round up 3'b100: CalcPlus1 = Guard;//round to nearest max magnitude @@ -264,7 +264,7 @@ module round import cvw::*; #(parameter cvw_t P) ( // Determine if you add 1 (for underflow flag) case (Frm) 3'b000: UfCalcPlus1 = Round & (Sticky|Guard);//round to nearest even - 3'b001: UfCalcPlus1 = 0;//round to zero + 3'b001: UfCalcPlus1 = 1'b0;//round to zero 3'b010: UfCalcPlus1 = Ms;//round down 3'b011: UfCalcPlus1 = ~Ms;//round up 3'b100: UfCalcPlus1 = Round;//round to nearest max magnitude @@ -305,7 +305,7 @@ module round import cvw::*; #(parameter cvw_t P) ( 2'b00: Me = {CvtCe[P.NE], CvtCe}&{P.NE+2{~CvtResSubnormUf|CvtResUf}}; // cvt // 2'b01: Me = DivDone ? Ue : 0; // divide 2'b01: Me = Ue; // divide - default: Me = 0; + default: Me = '0; endcase diff --git a/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv index e9ba573e1a..b9dbf4b9ea 100644 --- a/src/fpu/postproc/specialcase.sv +++ b/src/fpu/postproc/specialcase.sv @@ -339,7 +339,7 @@ module specialcase import cvw::*; #(parameter cvw_t P) ( if (P.ZFA_SUPPORTED & P.D_SUPPORTED) // fcvtmod.w.d support always_comb begin - if (Zfa) OfIntRes2 = 0; // fcvtmod.w.d produces 0 on overflow + if (Zfa) OfIntRes2 = '0; // fcvtmod.w.d produces 0 on overflow else OfIntRes2 = OfIntRes; if (Zfa) Int64Res = {{(P.XLEN-32){CvtNegRes[P.XLEN-1]}}, CvtNegRes[31:0]}; else Int64Res = CvtNegRes[P.XLEN-1:0]; diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv index e5c5f3deb9..a6c421e5c5 100644 --- a/src/fpu/unpackinput.sv +++ b/src/fpu/unpackinput.sv @@ -54,7 +54,7 @@ module unpackinput import cvw::*; #(parameter cvw_t P) ( assign In = A & {P.FLEN{FPUActive}}; if (P.FPSIZES == 1) begin // if there is only one floating point format supported - assign BadNaNBox = 0; + assign BadNaNBox = 1'b0; assign Sgn = In[P.FLEN-1]; // sign bit assign Frac = In[P.NF-1:0]; // fraction (no assumed 1) assign ExpNonZero = |In[P.FLEN-2:P.NF]; // is the exponent non-zero @@ -133,7 +133,7 @@ module unpackinput import cvw::*; #(parameter cvw_t P) ( // Check NaN boxing always_comb case (Fmt) - P.FMT: BadNaNBox = 0; + P.FMT: BadNaNBox = 1'b0; P.FMT1: BadNaNBox = ~&In[P.FLEN-1:P.LEN1]; P.FMT2: BadNaNBox = ~&In[P.FLEN-1:P.LEN2]; default: BadNaNBox = 1'bx; @@ -149,30 +149,30 @@ module unpackinput import cvw::*; #(parameter cvw_t P) ( // extract the sign bit always_comb - if (BadNaNBox) Sgn = 0; // improperly boxed NaNs are treated as positive + if (BadNaNBox) Sgn = 1'b0; // improperly boxed NaNs are treated as positive else case (Fmt) - P.FMT: Sgn = In[P.FLEN-1]; - P.FMT1: Sgn = In[P.LEN1-1]; - P.FMT2: Sgn = In[P.LEN2-1]; + P.FMT: Sgn = In[P.FLEN-1]; + P.FMT1: Sgn = In[P.LEN1-1]; + P.FMT2: Sgn = In[P.LEN2-1]; default: Sgn = 1'bx; endcase // extract the fraction always_comb case (Fmt) - P.FMT: Frac = In[P.NF-1:0]; - P.FMT1: Frac = {In[P.NF1-1:0], (P.NF-P.NF1)'(0)}; - P.FMT2: Frac = {In[P.NF2-1:0], (P.NF-P.NF2)'(0)}; + P.FMT: Frac = In[P.NF-1:0]; + P.FMT1: Frac = {In[P.NF1-1:0], (P.NF-P.NF1)'(0)}; + P.FMT2: Frac = {In[P.NF2-1:0], (P.NF-P.NF2)'(0)}; default: Frac = {P.NF{1'bx}}; endcase // is the exponent non-zero always_comb case (Fmt) - P.FMT: ExpNonZero = |In[P.FLEN-2:P.NF]; // if input is largest precision (P.FLEN - ie quad or double) - P.FMT1: ExpNonZero = |In[P.LEN1-2:P.NF1]; // if input is larger precsion (P.LEN1 - double or single) - P.FMT2: ExpNonZero = |In[P.LEN2-2:P.NF2]; // if input is smallest precsion (P.LEN2 - single or half) + P.FMT: ExpNonZero = |In[P.FLEN-2:P.NF]; // if input is largest precision (P.FLEN - ie quad or double) + P.FMT1: ExpNonZero = |In[P.LEN1-2:P.NF1]; // if input is larger precsion (P.LEN1 - double or single) + P.FMT2: ExpNonZero = |In[P.LEN2-2:P.NF2]; // if input is smallest precsion (P.LEN2 - single or half) default: ExpNonZero = 1'bx; endcase @@ -209,13 +209,13 @@ module unpackinput import cvw::*; #(parameter cvw_t P) ( // P.Q_LEN | P.D_LEN | P.S_LEN | P.H_LEN length of floating point number // P.Q_NE | P.D_NE | P.S_NE | P.H_NE length of exponent // P.Q_NF | P.D_NF | P.S_NF | P.H_NF length of fraction - // P.Q_BIAS | P.D_BIAS | P.S_BIAS | P.H_BIAS exponent's bias value + // P.Q_BIAS | P.D_= 1'b1; | P.S_BIAS | P.H_BIAS exponent's bias value // P.Q_FMT | P.D_FMT | P.S_FMT | P.H_FMT precision's format value - Q=11 D=01 Sticky=00 H=10 // Check NaN boxing always_comb case (Fmt) - 2'b11: BadNaNBox = 0; + 2'b11: BadNaNBox = 1'b0; 2'b01: BadNaNBox = ~&In[P.Q_LEN-1:P.D_LEN]; 2'b00: BadNaNBox = ~&In[P.Q_LEN-1:P.S_LEN]; 2'b10: BadNaNBox = ~&In[P.Q_LEN-1:P.H_LEN]; @@ -234,7 +234,7 @@ module unpackinput import cvw::*; #(parameter cvw_t P) ( // extract sign bit always_comb - if (BadNaNBox) Sgn = 0; // improperly boxed NaNs are treated as positive + if (BadNaNBox) Sgn = 1'b0; // improperly boxed NaNs are treated as positive else case (Fmt) 2'b11: Sgn = In[P.Q_LEN-1]; diff --git a/src/generic/binencoder.sv b/src/generic/binencoder.sv index a9349879ab..83b2454852 100644 --- a/src/generic/binencoder.sv +++ b/src/generic/binencoder.sv @@ -34,7 +34,7 @@ module binencoder #(parameter N = 8) ( // this is coded as a priority encoder // consider redesigning to take advanteage of one-hot nature of input always_comb begin - Y = 0; + Y = '0; for(index = 0; index < N; index++) if(A[index] == 1'b1) Y = index[$clog2(N)-1:0]; end diff --git a/src/generic/flop/flopenr.sv b/src/generic/flop/flopenr.sv index 1973b444b1..1e92ac5131 100644 --- a/src/generic/flop/flopenr.sv +++ b/src/generic/flop/flopenr.sv @@ -31,7 +31,7 @@ module flopenr #(parameter WIDTH = 8) ( output logic [WIDTH-1:0] q); always_ff @(posedge clk) - if (reset) q <= 0; + if (reset) q <= '0; else if (en) q <= d; endmodule diff --git a/src/generic/flop/flopenrc.sv b/src/generic/flop/flopenrc.sv index 64d5761a61..45811db6e4 100644 --- a/src/generic/flop/flopenrc.sv +++ b/src/generic/flop/flopenrc.sv @@ -31,9 +31,9 @@ module flopenrc #(parameter WIDTH = 8) ( output logic [WIDTH-1:0] q); always_ff @(posedge clk) - if (reset) q <= 0; + if (reset) q <= '0; else if (en) - if (clear) q <= 0; + if (clear) q <= '0; else q <= d; endmodule diff --git a/src/generic/flop/flopr.sv b/src/generic/flop/flopr.sv index 538d29f3cc..15deb5d54b 100644 --- a/src/generic/flop/flopr.sv +++ b/src/generic/flop/flopr.sv @@ -31,7 +31,7 @@ module flopr #(parameter WIDTH = 8) ( output logic [WIDTH-1:0] q); always_ff @(posedge clk) - if (reset) q <= 0; + if (reset) q <= '0; else q <= d; endmodule diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index 831ad97c81..d711fce7a2 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -114,7 +114,7 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68) initial begin // initialize memory for simulation only; not needed because done in the testbench now integer j; for (j=0; j < DEPTH; j++) - mem[j] = 0; + mem[j] = '0; end */ diff --git a/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv index 433e12d375..9b25feb651 100644 --- a/src/generic/onehotdecoder.sv +++ b/src/generic/onehotdecoder.sv @@ -31,7 +31,7 @@ module onehotdecoder #(parameter WIDTH = 2) ( ); always_comb begin - decoded = 0; + decoded = '0; decoded[bin] = 1'b1; end diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index fa731bac85..5d2611ddae 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -82,7 +82,7 @@ module hazard import cvw::*; #(parameter cvw_t P) ( // The IFU and LSU stall the entire pipeline on a cache miss, bus access, or other long operation. // The IFU stalls the entire pipeline rather than just Fetch to avoid complications with instructions later in the pipeline causing Exceptions // A trap could be asserted at the start of a IFU/LSU stall, and should flush the memory operation - assign StallFCause = 0; + assign StallFCause = 1'b0; assign StallDCause = (StructuralStallD | FPUStallD) & ~FlushDCause; assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause; assign StallMCause = WFIStallM & ~FlushMCause; diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 244a5b4463..adb5291e28 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -94,22 +94,22 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( // ZBC and ZBKCUnit if (P.ZBC_SUPPORTED | P.ZBKC_SUPPORTED) begin: zbc zbc #(P.XLEN) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3, .ZBCResult); - end else assign ZBCResult = 0; + end else assign ZBCResult = '0; // ZBB Unit if (P.ZBB_SUPPORTED) begin: zbb zbb #(P.XLEN) ZBB(.A(ABMU), .RevA, .B(BBMU), .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect(ZBBSelect[2:0]), .ZBBResult); - end else assign ZBBResult = 0; + end else assign ZBBResult = '0; // ZBKB Unit if (P.ZBKB_SUPPORTED) begin: zbkb zbkb #(P.XLEN) ZBKB(.A(ABMU), .B(BBMU), .RevA, .W64, .Funct3, .ZBKBSelect(ZBBSelect[2:0]), .ZBKBResult); - end else assign ZBKBResult = 0; + end else assign ZBKBResult = '0; // ZBKX Unit if (P.ZBKX_SUPPORTED) begin: zbkx zbkx #(P.XLEN) ZBKX(.A(ABMU), .B(BBMU), .ZBKXSelect(ZBBSelect[2:0]), .ZBKXResult); - end else assign ZBKXResult = 0; + end else assign ZBKXResult = '0; // ZKND and ZKNE AES decryption and encryption if (P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED) @@ -120,7 +120,7 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( if (P.ZKNH_SUPPORTED) begin: zknh if (P.XLEN == 32) zknh32 ZKNH32(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult)); else zknh64 ZKNH64(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult)); - end else assign ZKNHResult = 0; + end else assign ZKNHResult = '0; // Result Select Mux always_comb diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index 3650f14caa..dff468257d 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -56,8 +56,8 @@ module cnt #(parameter WIDTH = 32) ( lzc #(WIDTH) lzc(.num(lzcA), .ZeroCnt(czResult[$clog2(WIDTH):0])); popcnt #(WIDTH) popcntw(.num(popcntA), .PopCnt(cpopResult[$clog2(WIDTH):0])); // zero extend these results to fit into width - assign czResult[WIDTH-1:$clog2(WIDTH)+1] = 0; - assign cpopResult[WIDTH-1:$clog2(WIDTH)+1] = 0; + assign czResult[WIDTH-1:$clog2(WIDTH)+1] = '0; + assign cpopResult[WIDTH-1:$clog2(WIDTH)+1] = '0; mux2 #(WIDTH) cntresultmux(czResult, cpopResult, B[1], CntResult); endmodule diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index 8f57598737..838468fa14 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -34,7 +34,7 @@ module popcnt #(parameter WIDTH = 32) ( logic [$clog2(WIDTH):0] sum; always_comb begin - sum = 0; + sum = '0; for (int i=0;i> 8; assign x[0][3] = B << 31; assign x[0][4] = B << 24; - assign x[0][5] = 0; + assign x[0][5] = '0; // sha512sig0l assign x[1][0] = A >> 1; @@ -58,7 +58,7 @@ module sha512_32 ( assign x[2][2] = A >> 19; assign x[2][3] = B >> 29; assign x[2][4] = B << 13; - assign x[2][5] = 0; + assign x[2][5] = '0; // sha512sig1l assign x[3][0] = A << 3; diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 568eeecb5a..166fba3def 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -164,7 +164,7 @@ module bpred import cvw::*; #(parameter cvw_t P) ( .InstrClassM({CallM, ReturnM, JumpM, BranchM}), .InstrClassW({CallW, ReturnW, JumpW, BranchW})); - icpred #(P, `INSTR_CLASS_PRED) icpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + icpred #(P, `INSTR_CLASS_PRED) icpred(.clk, .reset, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .PostSpillInstrRawF, .InstrD, .BranchD, .BranchE, .JumpD, .JumpE, .BranchM, .BranchW, .JumpM, .JumpW, .CallD, .CallE, .CallM, .CallW, .ReturnD, .ReturnE, .ReturnM, .ReturnW, .BTBCallF, .BTBReturnF, .BTBJumpF, .BTBBranchF, .BPCallF, .BPReturnF, .BPJumpF, .BPBranchF, .IClassWrongM, .IClassWrongE, .BPReturnWrongD); diff --git a/src/ifu/bpred/icpred.sv b/src/ifu/bpred/icpred.sv index 8d0ecc8902..2cc85a74bc 100644 --- a/src/ifu/bpred/icpred.sv +++ b/src/ifu/bpred/icpred.sv @@ -30,8 +30,8 @@ module icpred import cvw::*; #(parameter cvw_t P, parameter INSTR_CLASS_PRED = 1)( input logic clk, reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, + input logic StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, input logic [31:0] PostSpillInstrRawF, InstrD, // Instruction input logic BranchD, BranchE, input logic JumpD, JumpE, @@ -65,7 +65,7 @@ module icpred import cvw::*; #(parameter cvw_t P, assign CJumpF = cjal | cj | cjr | cjalr; assign CBranchF = CompressedOpcF[4:1] == 4'h7; end else begin - assign {cjal, cj, cjr, cjalr, CJumpF, CBranchF} = 0; + assign {cjal, cj, cjr, cjalr, CJumpF, CBranchF} = '0; end assign NCJumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F; diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv index 46819fcb7f..f953da0ded 100644 --- a/src/ifu/bpred/localrepairbp.sv +++ b/src/ifu/bpred/localrepairbp.sv @@ -116,7 +116,7 @@ module localrepairbp import cvw::*; #(parameter cvw_t P, SpeculativeFlushedF <= FlushedBits[IndexLHRNextF]; if (reset | FlushD) FlushedBits <= '1; if(BranchD & ~StallE & ~FlushE) begin - FlushedBits[IndexLHRD] <= 0; + FlushedBits[IndexLHRD] <= 1'b0; end end diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index 359d6e3ad4..6b38c9e56f 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -80,19 +80,19 @@ module decompress import cvw::*; #(parameter cvw_t P) ( always_comb if (op == 2'b11) begin // noncompressed instruction InstrD = InstrRawD; - IllegalCompInstrD = 0; + IllegalCompInstrD = '0; end else begin // convert compressed instruction into uncompressed - IllegalCompInstrD = 0; + IllegalCompInstrD = '0; case ({op, instr16[15:13]}) 5'b00000: if (immCIW != 0) InstrD = {immCIW, 5'b00010, 3'b000, rdp, 7'b0010011}; // c.addi4spn else begin // illegal instruction - IllegalCompInstrD = 1; + IllegalCompInstrD = 1'b1; InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap end 5'b00001: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED) InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld else begin // unsupported instruction - IllegalCompInstrD = 1; + IllegalCompInstrD = 1'b1; InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap end 5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw @@ -100,7 +100,7 @@ module decompress import cvw::*; #(parameter cvw_t P) ( if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED) InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw else begin - IllegalCompInstrD = 1; + IllegalCompInstrD = 1'b1; InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap end else @@ -118,17 +118,17 @@ module decompress import cvw::*; #(parameter cvw_t P) ( else if (instr16[12:10] == 3'b011 & instr16[6] == 1'b0) InstrD = {7'b0, rs2p, rs1p, 3'b001, 3'b000, instr16[5], 1'b0, 7'b0100011}; // c.sh else begin - IllegalCompInstrD = 1; + IllegalCompInstrD = 1'b1; InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap end else begin - IllegalCompInstrD = 1; + IllegalCompInstrD = 1'b1; InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap end 5'b00101: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED) InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd else begin // unsupported instruction - IllegalCompInstrD = 1; + IllegalCompInstrD = 1'b1; InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap end 5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw @@ -136,7 +136,7 @@ module decompress import cvw::*; #(parameter cvw_t P) ( if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED) InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw else begin - IllegalCompInstrD = 1; + IllegalCompInstrD = 1'b1; InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap end else @@ -186,11 +186,11 @@ module decompress import cvw::*; #(parameter cvw_t P) ( else if (instr16[6:5] == 2'b10 & P.ZCB_SUPPORTED) InstrD = {7'b0000001, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.mul else begin // reserved - IllegalCompInstrD = 1; + IllegalCompInstrD = 1'b1; InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap end /** end else begin // illegal instruction - IllegalCompInstrD = 1; + IllegalCompInstrD = 1'b1; InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap **/ end 5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j @@ -200,7 +200,7 @@ module decompress import cvw::*; #(parameter cvw_t P) ( 5'b10001: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED) InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp else begin // unsupported instruction - IllegalCompInstrD = 1; + IllegalCompInstrD = 1'b1; InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap end 5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp @@ -208,7 +208,7 @@ module decompress import cvw::*; #(parameter cvw_t P) ( if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED) InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp else begin - IllegalCompInstrD = 1; + IllegalCompInstrD = 1'b1; InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap end else @@ -229,7 +229,7 @@ module decompress import cvw::*; #(parameter cvw_t P) ( 5'b10101: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED) InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp else begin // unsupported instruction - IllegalCompInstrD = 1; + IllegalCompInstrD = 1'b1; InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap end 5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp @@ -237,13 +237,13 @@ module decompress import cvw::*; #(parameter cvw_t P) ( if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED) InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp else begin - IllegalCompInstrD = 1; + IllegalCompInstrD = 1'b1; InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap end else InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp default: begin // illegal instruction - IllegalCompInstrD = 1; + IllegalCompInstrD = 1'b1; InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap end endcase diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index f12e02ec9a..811d53e215 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -154,7 +154,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( assign PCSpillNextF = PCNextF; assign PCSpillF = PCF; assign PostSpillInstrRawF = InstrRawF; - assign {SelSpillNextF, CompressedF} = 0; + assign {SelSpillNextF, CompressedF} = '0; end //////////////////////////////////////////////////////////////////////////////////////////////// @@ -194,10 +194,10 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW); end else begin - assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrUpdateDAF} = 0; + assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrUpdateDAF} = '0; assign PCPF = PCFExt[P.PA_BITS-1:0]; - assign CacheableF = 1; - assign SelIROM = 0; + assign CacheableF = 1'b1; + assign SelIROM = '0; end //////////////////////////////////////////////////////////////////////////////////////////////// @@ -216,12 +216,13 @@ module ifu import cvw::*; #(parameter cvw_t P) ( // The IROM uses untranslated addresses, so it is not compatible with virtual memory. if (P.IROM_SUPPORTED) begin : irom - logic IROMce; - assign IROMce = ~GatedStallD | reset; + logic IROMce; + assign IROMce = ~GatedStallD | reset; assign IFURWF = 2'b10; irom #(P) irom(.clk, .ce(IROMce), .Adr(PCSpillNextF[P.XLEN-1:0]), .IROMInstrF); end else begin assign IFURWF = 2'b10; + assign IROMInstrF = '0; end if (P.BUS_SUPPORTED) begin : bus // **** must fix words per line vs beats per line as in lsu. @@ -234,8 +235,8 @@ module ifu import cvw::*; #(parameter cvw_t P) ( logic ICacheBusAck; logic [1:0] CacheBusRW, BusRW, CacheRWF; - assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : 0; - assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : 0; + assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0; + assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0; // *** RT: PAdr and NextSet are replaced with mux between PCPF/IEUAdrM and PCSpillNextF/IEUAdrE. cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS), .NUMLINES(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS), @@ -279,15 +280,15 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .HWSTRB(), .BusRW, .BusAtomic('0), .ByteMask(), .WriteData('0), .Stall(GatedStallD), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer)); - assign CacheCommittedF = 0; + assign CacheCommittedF = '0; if(P.IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(ShiftUncachedInstr, IROMInstrF, SelIROM, InstrRawF); else assign InstrRawF = ShiftUncachedInstr; assign IFUHBURST = 3'b0; - assign {ICacheMiss, ICacheAccess, ICacheStallF} = 0; + assign {ICacheMiss, ICacheAccess, ICacheStallF} = '0; end end else begin : nobus // block: bus - assign {BusStall, CacheCommittedF} = 0; - assign {ICacheStallF, ICacheMiss, ICacheAccess} = 0; + assign {BusStall, CacheCommittedF} = '0; + assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0; assign InstrRawF = IROMInstrF; end @@ -348,14 +349,14 @@ module ifu import cvw::*; #(parameter cvw_t P) ( logic CallD, CallE, CallM, CallW; logic ReturnD, ReturnE, ReturnM, ReturnW; assign BPWrongE = PCSrcE; - icpred #(P, 0) icpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + icpred #(P, 0) icpred(.clk, .reset, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .PostSpillInstrRawF, .InstrD, .BranchD, .BranchE, .JumpD, .JumpE, .BranchM, .BranchW, .JumpM, .JumpW, .CallD, .CallE, .CallM, .CallW, .ReturnD, .ReturnE, .ReturnM, .ReturnW, .BTBCallF(1'b0), .BTBReturnF(1'b0), .BTBJumpF(1'b0), .BTBBranchF(1'b0), .BPCallF(), .BPReturnF(), .BPJumpF(), .BPBranchF(), .IClassWrongM, .IClassWrongE(), .BPReturnWrongD()); flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, BPWrongM); - assign RASPredPCWrongM = 0; + assign RASPredPCWrongM = 1'b0; assign BPDirPredWrongM = BPWrongM; assign BTAWrongM = BPWrongM; assign InstrClassM = {CallM, ReturnM, JumpM, BranchM}; @@ -402,11 +403,11 @@ module ifu import cvw::*; #(parameter cvw_t P) ( if (P.ZICSR_SUPPORTED | P.A_SUPPORTED) begin mux2 #(32) FlushInstrMMux(InstrE, nop, FlushM, NextInstrE); flopenr #(32) InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM); - end else assign InstrM = 0; + end else assign InstrM = '0; // PCM is only needed with CSRs or branch prediction if (P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED) flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM); - else assign PCM = 0; + else assign PCM = '0; // If compressed instructions are supported, increment PCLink by 2 or 4 for a jal. Otherwise, just by 4 if (P.COMPRESSED_SUPPORTED) begin @@ -415,7 +416,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE); assign PCLinkE = PCE + (CompressedE ? 'd2 : 'd4); // 'd4 means 4 but stops Design Compiler complaining about signed to unsigned conversion end else begin - assign CompressedE = 0; + assign CompressedE = 1'b0; assign PCLinkE = PCE + 'd4; end diff --git a/src/lsu/align.sv b/src/lsu/align.sv index 476e77c282..c28c1b9cfe 100644 --- a/src/lsu/align.sv +++ b/src/lsu/align.sv @@ -95,21 +95,21 @@ module align import cvw::*; #(parameter cvw_t P) ( // compute misalignement always_comb begin case (Funct3M & {FpLoadStoreM, 2'b11}) - 3'b000: AccessByteOffsetM = 0; // byte access + 3'b000: AccessByteOffsetM = '0; // byte access 3'b001: AccessByteOffsetM = {{OFFSET_LEN-1{1'b0}}, IEUAdrM[0]}; // half access 3'b010: AccessByteOffsetM = {{OFFSET_LEN-2{1'b0}}, IEUAdrM[1:0]}; // word access 3'b011: if(P.LLEN >= 64) AccessByteOffsetM = {{OFFSET_LEN-3{1'b0}}, IEUAdrM[2:0]}; // double access - else AccessByteOffsetM = 0; // shouldn't happen + else AccessByteOffsetM = '0; // shouldn't happen 3'b100: if(P.LLEN == 128) AccessByteOffsetM = IEUAdrM[OFFSET_LEN-1:0]; // quad access else AccessByteOffsetM = IEUAdrM[OFFSET_LEN-1:0]; - default: AccessByteOffsetM = 0; // shouldn't happen + default: AccessByteOffsetM = '0; // shouldn't happen endcase case (Funct3M[1:0]) - 2'b00: PotentialSpillM = 0; // byte access + 2'b00: PotentialSpillM = 1'b0; // byte access 2'b01: PotentialSpillM = IEUAdrM[OFFSET_BIT_POS-1:1] == '1; // half access 2'b10: PotentialSpillM = IEUAdrM[OFFSET_BIT_POS-1:2] == '1; // word access 2'b11: PotentialSpillM = IEUAdrM[OFFSET_BIT_POS-1:3] == '1; // double access - default: PotentialSpillM = 0; + default: PotentialSpillM = 1'b0; endcase end assign MisalignedM = (|MemRWM) & (AccessByteOffsetM != 0); @@ -148,7 +148,7 @@ module align import cvw::*; #(parameter cvw_t P) ( // shifter (4:1 mux for 32 bit, 8:1 mux for 64 bit) // 8 * is for shifting by bytes not bits - assign ShiftAmount = SelHPTW ? 0 : {AccessByteOffsetM, 3'b0}; // AND gate + assign ShiftAmount = SelHPTW ? '0 : {AccessByteOffsetM, 3'b0}; // AND gate assign ReadDataWordSpillShiftedM = ReadDataWordSpillAllM >> ShiftAmount; assign DCacheReadDataWordSpillM = ReadDataWordSpillShiftedM[P.LLEN-1:0]; diff --git a/src/lsu/lrsc.sv b/src/lsu/lrsc.sv index f7d1d47995..5981035c16 100644 --- a/src/lsu/lrsc.sv +++ b/src/lsu/lrsc.sv @@ -58,9 +58,9 @@ module lrsc import cvw::*; #(parameter cvw_t P) ( assign SquashSCM = scM & ~WriteAdrMatchM; assign LSURWM = SquashSCM ? 2'b00 : PreLSURWM; always_comb begin // ReservationValidM (next value of valid reservation) - if (lrM) ReservationValidM = 1; // set valid on load reserve + if (lrM) ReservationValidM = 1'b1; // set valid on load reserve // if we implement multiple harts invalidate reservation if another hart stores to this reservation. - else if (scM) ReservationValidM = 0; // clear valid on store to same address or any sc + else if (scM) ReservationValidM = 1'b0; // clear valid on store to same address or any sc else ReservationValidM = ReservationValidW; // otherwise don't change valid end diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 9618e2cae8..c4e0e009e3 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -173,12 +173,12 @@ module lsu import cvw::*; #(parameter cvw_t P) ( end else begin : no_ziccslm_align assign IEUAdrExtM = {2'b00, IEUAdrM}; assign IEUAdrExtE = {2'b00, IEUAdrE}; - assign SelSpillE = 0; + assign SelSpillE = 1'b0; assign DCacheReadDataWordSpillM = DCacheReadDataWordM; assign ByteMaskSpillM = ByteMaskM; assign LSUWriteDataSpillM = LSUWriteDataM; assign MemRWSpillM = MemRWM; - assign {SpillStallM} = 0; + assign {SpillStallM} = 1'b0; end if(P.ZICBOZ_SUPPORTED) begin : cboz @@ -216,8 +216,8 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM; assign LoadPageFaultM = LSULoadPageFaultM; assign StoreAmoPageFaultM = LSUStoreAmoPageFaultM; - assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = 0; - assign {HPTWInstrAccessFaultF, HPTWInstrPageFaultF} = 0; + assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0; + assign {HPTWInstrAccessFaultF, HPTWInstrPageFaultF} = '0; end // CommittedM indicates the cache, bus, or HPTW are busy with a multiple cycle operation. @@ -253,8 +253,8 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW); end else begin // No MMU, so no PMA/page faults and no address translation - assign {DTLBMissM, LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = 0; - assign {LSULoadPageFaultM, LSUStoreAmoPageFaultM} = 0; + assign {DTLBMissM, LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0; + assign {LSULoadPageFaultM, LSUStoreAmoPageFaultM} = '0; assign PAdrM = IHAdrM[P.PA_BITS-1:0]; assign CacheableM = 1'b1; assign SelDTIM = P.DTIM_SUPPORTED & ~P.BUS_SUPPORTED; // if no PMA then select dtim if there is a DTIM. If there is @@ -287,7 +287,8 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .MemRWM(DTIMMemRWM), .DTIMAdr, .FlushW, .WriteDataM(LSUWriteDataM), .ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM)); - end + end else + assign DTIMReadDataWordM = '0; if (P.BUS_SUPPORTED) begin : bus if(P.DCACHE_SUPPORTED) begin : dcache localparam LLENWORDSPERLINE = P.DCACHE_LINELENINBITS/P.LLEN; // Number of LLEN words in cacheline @@ -316,16 +317,16 @@ module lsu import cvw::*; #(parameter cvw_t P) ( if(P.ZICBOZ_SUPPORTED) begin assign BusCMOZero = CMOpM[3] & ~CacheableM; - assign CacheCMOpM = (CacheableM & ~SelHPTW) ? CMOpM : 0; + assign CacheCMOpM = (CacheableM & ~SelHPTW) ? CMOpM : '0; assign BusAtomic = AtomicM[1] & ~CacheableM; end else begin - assign BusCMOZero = 0; - assign CacheCMOpM = 0; - assign BusAtomic = 0; + assign BusCMOZero = 1'b0; + assign CacheCMOpM = '0; + assign BusAtomic = 1'b0; end - assign BusRW = (~CacheableM & ~SelDTIM )? LSURWM : 0; + assign BusRW = (~CacheableM & ~SelDTIM )? LSURWM : '0; assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM; - assign CacheRWM = (CacheableM & ~SelDTIM) ? LSURWM : 0; + assign CacheRWM = (CacheableM & ~SelDTIM) ? LSURWM : '0; assign FlushDCache = FlushDCacheM & ~(SelHPTW); cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN), @@ -379,14 +380,14 @@ module lsu import cvw::*; #(parameter cvw_t P) ( if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]); else assign ReadDataWordMuxM[P.XLEN-1:0] = FetchBuffer[P.XLEN-1:0]; // *** bus only does not support double wide floats. assign LSUHBURST = 3'b0; - assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = 0; - end + assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0; + end end else begin: nobus // block: bus, only DTIM - assign LSUHWDATA = 0; + assign LSUHWDATA = '0; assign ReadDataWordMuxM = DTIMReadDataWordM; - assign {BusStall, BusCommittedM} = 0; - assign {DCacheMiss, DCacheAccess} = 0; - assign {DCacheStallM, DCacheCommittedM} = 0; + assign {BusStall, BusCommittedM} = '0; + assign {DCacheMiss, DCacheAccess} = '0; + assign {DCacheStallM, DCacheCommittedM} = '0; end assign LSUBusStallM = BusStall & ~IgnoreRequestTLB; @@ -400,7 +401,9 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, .IMAWriteDataM, .SquashSCW, .LSURWM); end else begin:lrsc - assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign IMAWriteDataM = IHWriteDataM; + assign SquashSCW = 1'b0; + assign LSURWM = PreLSURWM; + assign IMAWriteDataM = IHWriteDataM; end if (P.F_SUPPORTED) diff --git a/src/lsu/subwordwrite.sv b/src/lsu/subwordwrite.sv index 659d6d9c78..eec6fe0203 100644 --- a/src/lsu/subwordwrite.sv +++ b/src/lsu/subwordwrite.sv @@ -35,6 +35,7 @@ module subwordwrite #(parameter LLEN) ( ); // Replicate data for subword writes + if (LLEN == 128) begin:sww always_comb case(LSUFunct3M[2:0]) diff --git a/src/lsu/swbytemask.sv b/src/lsu/swbytemask.sv index d8db91cbc0..fc1f95c4e0 100644 --- a/src/lsu/swbytemask.sv +++ b/src/lsu/swbytemask.sv @@ -34,6 +34,7 @@ module swbytemask #(parameter WORDLEN, EXTEND = 0)( output logic [WORDLEN/8-1:0] ByteMask, output logic [WORDLEN/8-1:0] ByteMaskExtended ); + if(EXTEND) begin logic [WORDLEN*2/8-1:0] ExtendedByteMask; // 'd2 means 2, but stops Design Compiler from complaining about signed to unsigned conversion @@ -42,7 +43,7 @@ module swbytemask #(parameter WORDLEN, EXTEND = 0)( assign ByteMaskExtended = ExtendedByteMask[WORDLEN*2/8-1:WORDLEN/8]; end else begin assign ByteMask = (('d2**('d2**Size))-'d1) << Adr; - assign ByteMaskExtended = 0; + assign ByteMaskExtended = '0; end /* Equivalent to the following @@ -50,7 +51,7 @@ module swbytemask #(parameter WORDLEN, EXTEND = 0)( if(WORDLEN == 64) begin always_comb begin case(Size[1:0]) - 2'b00: begin ByteMask = 8'b00000000; ByteMask[Adr[2:0]] = 1; end // sb + 2'b00: begin ByteMask = 8'b00000000; ByteMask[Adr[2:0]] = 1'b1; end // sb 2'b01: case (Adr[2:1]) 2'b00: ByteMask = 8'b0000_0011; 2'b01: ByteMask = 8'b0000_1100; @@ -65,7 +66,7 @@ module swbytemask #(parameter WORDLEN, EXTEND = 0)( end else begin always_comb begin case(Size[1:0]) - 2'b00: begin ByteMask = 4'b0000; ByteMask[Adr[1:0]] = 1; end // sb + 2'b00: begin ByteMask = 4'b0000; ByteMask[Adr[1:0]] = 1'b1; end // sb 2'b01: if (Adr[1]) ByteMask = 4'b1100; else ByteMask = 4'b0011; 2'b10: ByteMask = 4'b1111; diff --git a/src/mdu/mdu.sv b/src/mdu/mdu.sv index 886eaf2b3d..dff56797e2 100644 --- a/src/mdu/mdu.sv +++ b/src/mdu/mdu.sv @@ -59,9 +59,9 @@ module mdu import cvw::*; #(parameter cvw_t P) ( // When IDIV_ON_FPU is set, use the FPU divider instead // In ZMMUL, with M_SUPPORTED = 0, omit the divider if ((P.IDIV_ON_FPU & P.F_SUPPORTED) || (!P.M_SUPPORTED)) begin:nodiv - assign QuotM = 0; - assign RemM = 0; - assign DivBusyE = 0; + assign QuotM = '0; + assign RemM = '0; + assign DivBusyE = 1'b0; end else begin:div div #(P) div(.clk, .reset, .StallM, .FlushE, .DivSignedE(~Funct3E[0]), .W64E, .IntDivE, .ForwardedSrcAE, .ForwardedSrcBE, .DivBusyE, .QuotM, .RemM); diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 77e73e696b..32eef1bf61 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -213,9 +213,9 @@ module hptw import cvw::*; #(parameter cvw_t P) ( end else begin // block: hptwwrites assign NextPTE = ReadDataNoXM; assign HPTWAdr = HPTWReadAdr; - assign HPTWUpdateDA = 0; - assign UpdatePTE = 0; - assign HPTWRW[0] = 0; + assign HPTWUpdateDA = 1'b0; + assign UpdatePTE = 1'b0; + assign HPTWRW[0] = 1'b0; end // Enable and select signals based on states diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index e842016a2e..ec41773a81 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -93,10 +93,10 @@ module mmu import cvw::*; #(parameter cvw_t P, .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit, .Translate, .TLBPageFault, .UpdateDA, .PBMemoryType); end else begin:tlb // just pass address through as physical - assign Translate = 0; - assign TLBMiss = 0; - assign TLBHit = 1; // *** is this necessary - assign TLBPageFault = 0; + assign Translate = 1'b0; + assign TLBMiss = 1'b0; + assign TLBHit = 1'b1; // *** is this necessary + assign TLBPageFault = 1'b0; assign PBMemoryType = 2'b00; end @@ -121,9 +121,9 @@ module mmu import cvw::*; #(parameter cvw_t P, .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .CMOpM, .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM); end else begin - assign PMPInstrAccessFaultF = 0; - assign PMPStoreAmoAccessFaultM = 0; - assign PMPLoadAccessFaultM = 0; + assign PMPInstrAccessFaultF = 1'b0; + assign PMPStoreAmoAccessFaultM = 1'b0; + assign PMPLoadAccessFaultM = 1'b0; end assign ReadNoAmoAccessM = ReadAccessM & ~WriteAccessM;// AMO causes StoreAmo rather than Load fault @@ -132,7 +132,7 @@ module mmu import cvw::*; #(parameter cvw_t P, // Misaligned faults always_comb // exclusion-tag: immu-wordaccess case(Size[1:0]) - 2'b00: DataMisalignedM = 0; // lb, sb, lbu + 2'b00: DataMisalignedM = 1'b0; // lb, sb, lbu 2'b01: DataMisalignedM = VAdr[0]; // lh, sh, lhu 2'b10: DataMisalignedM = VAdr[1] | VAdr[0]; // lw, sw, flw, fsw, lwu 2'b11: DataMisalignedM = |VAdr[2:0]; // ld, sd, fld, fsd diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv index 84e41ba655..b1953cb9be 100644 --- a/src/mmu/pmachecker.sv +++ b/src/mmu/pmachecker.sv @@ -60,7 +60,7 @@ module pmachecker import cvw::*; #(parameter cvw_t P) ( // Only non-core RAM/ROM memory regions are cacheable. PBMT can override cachable; NC and IO are uncachable assign CacheableRegion = SelRegions[3] | SelRegions[4] | SelRegions[5]; // exclusion-tag: unused-cachable - assign Cacheable = (PBMemoryType == 2'b00) ? CacheableRegion : 0; + assign Cacheable = (PBMemoryType == 2'b00) ? CacheableRegion : 1'b0; // Nonidemdempotent means access could have side effect and must not be done speculatively or redundantly // I/O is nonidempotent. PBMT can override PMA; NC is idempotent and IO is non-idempotent diff --git a/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv index 7226237f61..9f5245081c 100644 --- a/src/mmu/pmpadrdec.sv +++ b/src/mmu/pmpadrdec.sv @@ -77,7 +77,7 @@ module pmpadrdec import cvw::*; #(parameter cvw_t P) ( assign Match = (AdrMode == TOR) ? TORMatch : (AdrMode == NA4 | AdrMode == NAPOT) ? NAMatch : - 0; + 1'b0; assign L = PMPCfg[7]; assign X = PMPCfg[2]; diff --git a/src/mmu/tlb/vm64check.sv b/src/mmu/tlb/vm64check.sv index 4a4e963877..d8168dac21 100644 --- a/src/mmu/tlb/vm64check.sv +++ b/src/mmu/tlb/vm64check.sv @@ -43,7 +43,7 @@ module vm64check import cvw::*; #(parameter cvw_t P) ( assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]); assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47; end else begin - assign SV39Mode = 0; - assign UpperBitsUnequal = 0; + assign SV39Mode = 1'b0; + assign UpperBitsUnequal = 1'b0; end endmodule diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 4be12e383f..7571fc2fcd 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -138,12 +138,12 @@ module csr import cvw::*; #(parameter cvw_t P) ( /////////////////////////////////////////// always_comb - if (InterruptM) NextFaultMtvalM = 0; + if (InterruptM) NextFaultMtvalM = '0; else case (CauseM) 12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint 2: NextFaultMtvalM = {{(P.XLEN-32){1'b0}}, InstrOrigM}; // Illegal instruction fault 0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults - default: NextFaultMtvalM = 0; // Ecall, interrupts + default: NextFaultMtvalM = '0; // Ecall, interrupts endcase /////////////////////////////////////////// @@ -252,13 +252,13 @@ module csr import cvw::*; #(parameter cvw_t P) ( .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MTIME_CLINT, .STCE, .WriteSSTATUSM, .IllegalCSRSAccessM, .STimerInt, .SENVCFG_REGW); end else begin - assign WriteSSTATUSM = 0; - assign CSRSReadValM = 0; - assign SEPC_REGW = 0; - assign STVEC_REGW = 0; - assign SCOUNTEREN_REGW = 0; - assign SATP_REGW = 0; - assign IllegalCSRSAccessM = 1; + assign WriteSSTATUSM = 1'b0; + assign CSRSReadValM = '0; + assign SEPC_REGW = '0; + assign STVEC_REGW = '0; + assign SCOUNTEREN_REGW = '0; + assign SATP_REGW = '0; + assign IllegalCSRSAccessM = 1'b1; end // Floating Point CSRs in User Mode only needed if Floating Point is supported @@ -268,9 +268,9 @@ module csr import cvw::*; #(parameter cvw_t P) ( .SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM, .IllegalCSRUAccessM); end else begin - assign FRM_REGW = 0; - assign CSRUReadValM = 0; - assign IllegalCSRUAccessM = 1; + assign FRM_REGW = '0; + assign CSRUReadValM = '0; + assign IllegalCSRUAccessM = 1'b1; end if (P.ZICNTR_SUPPORTED) begin:counters @@ -283,8 +283,8 @@ module csr import cvw::*; #(parameter cvw_t P) ( .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW, .MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM); end else begin - assign CSRCReadValM = 0; - assign IllegalCSRCAccessM = 1; // counters aren't enabled + assign CSRCReadValM = '0; + assign IllegalCSRCAccessM = 1'b1; // counters aren't enabled end // Broadcast appropriate environment configuration based on privilege mode diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index 463e3368ca..a816291fa6 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -120,9 +120,9 @@ module csrc import cvw::*; #(parameter cvw_t P) ( // DivBusyE will never be assert high since this configuration uses the FPU to do integer division assign CounterEvent[24] = DivBusyE | FDivBusyE; // division cycles *** RT: might need to be delay until the next cycle // coverage on - assign CounterEvent[P.COUNTERS-1:25] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions + assign CounterEvent[P.COUNTERS-1:25] = '0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions end else begin: cevent - assign CounterEvent[P.COUNTERS-1:3] = 0; + assign CounterEvent[P.COUNTERS-1:3] = '0; end // Counter update and write logic @@ -130,7 +130,7 @@ module csrc import cvw::*; #(parameter cvw_t P) ( assign WriteHPMCOUNTERM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERBASE + i); assign NextHPMCOUNTERM[i][P.XLEN-1:0] = WriteHPMCOUNTERM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][P.XLEN-1:0]; always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop - if (reset) HPMCOUNTER_REGW[i][P.XLEN-1:0] <= 0; + if (reset) HPMCOUNTER_REGW[i][P.XLEN-1:0] <= '0; else HPMCOUNTER_REGW[i][P.XLEN-1:0] <= NextHPMCOUNTERM[i]; if (P.XLEN==32) begin // write high and low separately @@ -140,10 +140,11 @@ module csrc import cvw::*; #(parameter cvw_t P) ( assign WriteHPMCOUNTERHM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERHBASE + i); assign NextHPMCOUNTERHM[i] = WriteHPMCOUNTERHM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][63:32]; always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop - if (reset) HPMCOUNTERH_REGW[i][P.XLEN-1:0] <= 0; + if (reset) HPMCOUNTERH_REGW[i][P.XLEN-1:0] <= '0; else HPMCOUNTERH_REGW[i][P.XLEN-1:0] <= NextHPMCOUNTERHM[i]; end else begin // XLEN=64; write entire register assign HPMCOUNTERPlusM[i] = HPMCOUNTER_REGW[i] + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]}; + assign HPMCOUNTERH_REGW[i] = '0; // disregard for RV64 end end @@ -152,7 +153,7 @@ module csrc import cvw::*; #(parameter cvw_t P) ( always_comb if (PrivilegeModeW == P.M_MODE | MCOUNTEREN_REGW[CounterNumM] & (!P.S_SUPPORTED | PrivilegeModeW == P.S_MODE | SCOUNTEREN_REGW[CounterNumM])) begin - IllegalCSRCAccessM = 0; + IllegalCSRCAccessM = 1'b0; if (P.XLEN==64) begin // 64-bit counter reads // Veri lator doesn't realize this only occurs for XLEN=64 /* verilator lint_off WIDTH */ @@ -163,8 +164,8 @@ module csrc import cvw::*; #(parameter cvw_t P) ( else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; else begin - CSRCReadValM = 0; - IllegalCSRCAccessM = 1; // requested CSR doesn't exist + CSRCReadValM = '0; + IllegalCSRCAccessM = 1'b1; // requested CSR doesn't exist end end else begin // 32-bit counter reads // Veril ator doesn't realize this only occurs for XLEN=32 @@ -181,13 +182,13 @@ module csrc import cvw::*; #(parameter cvw_t P) ( else if (CSRAdrM >= HPMCOUNTERHBASE & CSRAdrM < HPMCOUNTERHBASE+P.COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM]; else begin - CSRCReadValM = 0; - IllegalCSRCAccessM = 1; // requested CSR doesn't exist + CSRCReadValM = '0; + IllegalCSRCAccessM = 1'b1; // requested CSR doesn't exist end end end else begin - CSRCReadValM = 0; - IllegalCSRCAccessM = 1; // no privileges for this csr + CSRCReadValM = '0; + IllegalCSRCAccessM = 1'b1; // no privileges for this csr end endmodule diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 35c27736cd..500ad2a056 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -132,7 +132,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( assign MISA_REGW = {(P.XLEN == 32 ? 2'b01 : 2'b10), {(P.XLEN-28){1'b0}}, MISA_26[25:0]}; // MHARTID is hardwired. It only exists as a signal so that the testbench can easily see it. - assign MHARTID_REGW = 0; + assign MHARTID_REGW = '0; // Write machine Mode CSRs assign WriteMSTATUSM = CSRMWriteM & (CSRAdrM == MSTATUS); @@ -154,7 +154,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( if (P.S_SUPPORTED) begin:deleg // DELEG registers should exist flopenr #(16) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM[15:0] & MEDELEG_MASK, MEDELEG_REGW); flopenr #(12) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM[11:0] & MIDELEG_MASK, MIDELEG_REGW); - end else assign {MEDELEG_REGW, MIDELEG_REGW} = 0; + end else assign {MEDELEG_REGW, MIDELEG_REGW} = '0; flopenr #(P.XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW); flopenr #(P.XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); @@ -163,7 +163,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW); if (P.U_SUPPORTED) begin: mcounteren // MCOUNTEREN only exists when user mode is supported flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW); - end else assign MCOUNTEREN_REGW = 0; + end else assign MCOUNTEREN_REGW = '0; // MENVCFG register if (P.U_SUPPORTED) begin // menvcfg only exists if there is a lower privilege to control @@ -184,7 +184,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( if (P.XLEN == 64) begin assign MENVCFG_PreWriteValM = CSRWriteValM; flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM, MENVCFG_REGW); - assign MENVCFGH_REGW = 0; + assign MENVCFGH_REGW = '0; end else begin // RV32 has high and low halves logic WriteMENVCFGHM; assign MENVCFG_PreWriteValM = {CSRWriteValM, CSRWriteValM}; @@ -199,8 +199,8 @@ module csrm import cvw::*; #(parameter cvw_t P) ( // verilator lint_off WIDTH logic [5:0] entry; always_comb begin - entry = 0; - CSRMReadValM = 0; + entry = '0; + CSRMReadValM = '0; IllegalCSRMAccessM = !(P.S_SUPPORTED) & (CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + P.PMP_ENTRIES) // reading a PMP entry CSRMReadValM = {{(P.XLEN-(P.PA_BITS-2)){1'b0}}, PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0]}; @@ -221,10 +221,10 @@ module csrm import cvw::*; #(parameter cvw_t P) ( MARCHID: CSRMReadValM = {{(P.XLEN-32){1'b0}}, 32'h24}; // 36 for CV-Wally MIMPID: CSRMReadValM = {{P.XLEN-12{1'b0}}, 12'h100}; // pipelined implementation MHARTID: CSRMReadValM = MHARTID_REGW; // hardwired to 0 - MCONFIGPTR: CSRMReadValM = 0; // hardwired to 0 + MCONFIGPTR: CSRMReadValM = '0; // hardwired to 0 MSTATUS: CSRMReadValM = MSTATUS_REGW; MSTATUSH: if (P.XLEN==32) CSRMReadValM = MSTATUSH_REGW; - else IllegalCSRMAccessM = 1; + else IllegalCSRMAccessM = 1'b1; MTVEC: CSRMReadValM = MTVEC_REGW; MEDELEG: CSRMReadValM = {{(P.XLEN-16){1'b0}}, MEDELEG_REGW}; MIDELEG: CSRMReadValM = {{(P.XLEN-12){1'b0}}, MIDELEG_REGW}; @@ -236,11 +236,11 @@ module csrm import cvw::*; #(parameter cvw_t P) ( MTVAL: CSRMReadValM = MTVAL_REGW; MCOUNTEREN: CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTEREN_REGW}; MENVCFG: if (P.U_SUPPORTED) CSRMReadValM = MENVCFG_REGW[P.XLEN-1:0]; - else IllegalCSRMAccessM = 1; + else IllegalCSRMAccessM = 1'b1; MENVCFGH: if (P.U_SUPPORTED & P.XLEN==32) CSRMReadValM = MENVCFGH_REGW; - else IllegalCSRMAccessM = 1; + else IllegalCSRMAccessM = 1'b1; MCOUNTINHIBIT: CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW}; - default: IllegalCSRMAccessM = 1; + default: IllegalCSRMAccessM = 1'b1; endcase end // verilator lint_on WIDTH diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 2357fc131f..9623aa8b50 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -108,7 +108,7 @@ module csrs import cvw::*; #(parameter cvw_t P) ( if (P.VIRTMEM_SUPPORTED) flopenr #(P.XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW); else - assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported + assign SATP_REGW = '0; // hardwire to zero if virtual memory not supported flopenr #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW); if (P.SSTC_SUPPORTED) begin : sstc if (P.XLEN == 64) begin : sstc64 @@ -117,14 +117,14 @@ module csrs import cvw::*; #(parameter cvw_t P) ( flopenr #(P.XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, STIMECMP_REGW[31:0]); flopenr #(P.XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, STIMECMP_REGW[63:32]); end - end else assign STIMECMP_REGW = 0; + end else assign STIMECMP_REGW = '0; // Supervisor timer interrupt logic // Spec is a bit peculiar - Machine timer interrupts are produced in CLINT, while Supervisor timer interrupts are in CSRs if (P.SSTC_SUPPORTED) assign STimerInt = ({1'b0, MTIME_CLINT} >= {1'b0, STIMECMP_REGW}); // unsigned comparison else - assign STimerInt = 0; + assign STimerInt = 1'b0; assign SENVCFG_WriteValM = { {(P.XLEN-8){1'b0}}, @@ -138,7 +138,7 @@ module csrs import cvw::*; #(parameter cvw_t P) ( // CSR Reads always_comb begin:csrr - IllegalCSRSAccessM = 0; + IllegalCSRSAccessM = 1'b0; case (CSRAdrM) SSTATUS: CSRSReadValM = SSTATUS_REGW; STVEC: CSRSReadValM = STVEC_REGW; @@ -150,26 +150,26 @@ module csrs import cvw::*; #(parameter cvw_t P) ( STVAL: CSRSReadValM = STVAL_REGW; SATP: if (P.VIRTMEM_SUPPORTED & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW; else begin - CSRSReadValM = 0; - IllegalCSRSAccessM = 1; + CSRSReadValM = '0; + IllegalCSRSAccessM = 1'b1; end SCOUNTEREN:CSRSReadValM = {{(P.XLEN-32){1'b0}}, SCOUNTEREN_REGW}; SENVCFG: CSRSReadValM = SENVCFG_REGW; STIMECMP: if (STCE) CSRSReadValM = STIMECMP_REGW[P.XLEN-1:0]; else begin - CSRSReadValM = 0; - IllegalCSRSAccessM = 1; + CSRSReadValM = '0; + IllegalCSRSAccessM = 1'b1; end STIMECMPH: if (STCE & P.XLEN == 32) // not supported for RV64 CSRSReadValM = {{(P.XLEN-32){1'b0}}, STIMECMP_REGW[63:32]}; else begin - CSRSReadValM = 0; - IllegalCSRSAccessM = 1; + CSRSReadValM = '0; + IllegalCSRSAccessM = 1'b1; end default: begin - CSRSReadValM = 0; - IllegalCSRSAccessM = 1; + CSRSReadValM = '0; + IllegalCSRSAccessM = 1'b1; end endcase end diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 58e4aac613..161bf521c4 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -66,7 +66,7 @@ module csrsr import cvw::*; #(parameter cvw_t P) ( STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0, STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE, /*1'b0, STATUS_MIE, 1'b0*/ 3'b0, STATUS_SIE, 1'b0}; - assign MSTATUSH_REGW = 0; // *** does not exist when XLEN=64, but don't want it to have an undefined value. Spec is not clear what it should be. + assign MSTATUSH_REGW = '0; // *** does not exist when XLEN=64, but don't want it to have an undefined value. Spec is not clear what it should be. end else begin: csrsr32 // RV32 assign MSTATUS_REGW = {STATUS_SD, 8'b0, STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV, @@ -89,14 +89,11 @@ module csrsr import cvw::*; #(parameter cvw_t P) ( assign nextSBE = STATUS_SBE; end - // harwired STATUS bits + // hardwired STATUS bits assign STATUS_TSR = P.S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported assign STATUS_TW = (P.S_SUPPORTED | P.U_SUPPORTED) & STATUS_TW_INT; // override register with 0 if only machine mode supported assign STATUS_TVM = P.S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported assign STATUS_MXR = P.S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported -/* assign STATUS_UBE = 0; // little-endian - assign STATUS_SBE = 0; // little-endian - assign STATUS_MBE = 0; // little-endian */ // SXL and UXL bits only matter for RV64. Set to 10 for RV64 if mode is supported, or 0 if not assign STATUS_SXL = P.S_SUPPORTED ? 2'b10 : 2'b00; // 10 if supervisor mode supported assign STATUS_UXL = P.U_SUPPORTED ? 2'b10 : 2'b00; // 10 if user mode supported @@ -133,29 +130,29 @@ module csrsr import cvw::*; #(parameter cvw_t P) ( endcase end end else begin: endianmux - assign BigEndianM = 0; + assign BigEndianM = 1'b0; end // registers for STATUS bits // complex register with reset, write enable, and the ability to update other bits in certain cases always_ff @(posedge clk) //, posedge reset) if (reset) begin - STATUS_TSR_INT <= 0; - STATUS_TW_INT <= 0; - STATUS_TVM_INT <= 0; - STATUS_MXR_INT <= 0; - STATUS_SUM_INT <= 0; - STATUS_MPRV_INT <= 0; // Per Priv 3.3 - STATUS_FS_INT <= P.F_SUPPORTED ? 2'b00 : 2'b00; // leave floating-point off until activated, even if F_SUPPORTED - STATUS_MPP <= 0; - STATUS_SPP <= 0; - STATUS_MPIE <= 0; - STATUS_SPIE <= 0; - STATUS_MIE <= 0; - STATUS_SIE <= 0; - STATUS_MBE <= 0; - STATUS_SBE <= 0; - STATUS_UBE <= 0; + STATUS_TSR_INT <= 1'b0; + STATUS_TW_INT <= 1'b0; + STATUS_TVM_INT <= 1'b0; + STATUS_MXR_INT <= 1'b0; + STATUS_SUM_INT <= 1'b0; + STATUS_MPRV_INT <= 1'b0; // Per Priv 3.3 + STATUS_FS_INT <= 2'b00; // leave floating-point off until activated, even if F_SUPPORTED + STATUS_MPP <= 2'b00; + STATUS_SPP <= 1'b0; + STATUS_MPIE <= 1'b0; + STATUS_SPIE <= 1'b0; + STATUS_MIE <= 1'b0; + STATUS_SIE <= 1'b0; + STATUS_MBE <=1'b 0; + STATUS_SBE <= 1'b0; + STATUS_UBE <= 1'b0; end else if (~StallW) begin if (TrapM) begin // Update interrupt enables per Privileged Spec p. 21 @@ -164,23 +161,23 @@ module csrsr import cvw::*; #(parameter cvw_t P) ( // Modes: 11 = Machine, 01 = Supervisor, 00 = User if (NextPrivilegeModeM == P.M_MODE) begin STATUS_MPIE <= STATUS_MIE; - STATUS_MIE <= 0; + STATUS_MIE <= 1'b0; STATUS_MPP <= PrivilegeModeW; end else begin // supervisor mode STATUS_SPIE <= STATUS_SIE; - STATUS_SIE <= 0; + STATUS_SIE <= 1'b0; STATUS_SPP <= PrivilegeModeW[0]; end end else if (mretM) begin // Privileged 3.1.6.1 STATUS_MIE <= STATUS_MPIE; // restore global interrupt enable - STATUS_MPIE <= 1; // + STATUS_MPIE <= 1'b1; // STATUS_MPP <= P.U_SUPPORTED ? P.U_MODE : P.M_MODE; // set MPP to lowest supported privilege level STATUS_MPRV_INT <= STATUS_MPRV_INT & (STATUS_MPP == P.M_MODE); // page 21 of privileged spec. end else if (sretM) begin STATUS_SIE <= STATUS_SPIE; // restore global interrupt enable STATUS_SPIE <= P.S_SUPPORTED; - STATUS_SPP <= 0; // set SPP to lowest supported privilege level to catch bugs - STATUS_MPRV_INT <= 0; // always clear MPRV + STATUS_SPP <= 1'b0; // set SPP to lowest supported privilege level to catch bugs + STATUS_MPRV_INT <= 1'b0; // always clear MPRV end else if (WriteMSTATUSM) begin STATUS_TSR_INT <= CSRWriteValM[22]; STATUS_TW_INT <= CSRWriteValM[21]; diff --git a/src/privileged/csru.sv b/src/privileged/csru.sv index 37891d0094..62ac86c8d6 100644 --- a/src/privileged/csru.sv +++ b/src/privileged/csru.sv @@ -66,17 +66,17 @@ module csru import cvw::*; #(parameter cvw_t P) ( // CSR Reads always_comb begin if (STATUS_FS == 2'b00) begin // fpu disabled, trap - IllegalCSRUAccessM = 1; - CSRUReadValM = 0; + IllegalCSRUAccessM = 1'b1; + CSRUReadValM = '0; end else begin - IllegalCSRUAccessM = 0; + IllegalCSRUAccessM = 1'b0; case (CSRAdrM) FFLAGS: CSRUReadValM = {{(P.XLEN-5){1'b0}}, FFLAGS_REGW}; FRM: CSRUReadValM = {{(P.XLEN-3){1'b0}}, FRM_REGW}; FCSR: CSRUReadValM = {{(P.XLEN-8){1'b0}}, FRM_REGW, FFLAGS_REGW}; default: begin - CSRUReadValM = 0; - IllegalCSRUAccessM = 1; + CSRUReadValM = '0; + IllegalCSRUAccessM = 1'b1; end endcase end diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv index cf32c1f28d..60828a3f25 100644 --- a/src/privileged/privdec.sv +++ b/src/privileged/privdec.sv @@ -86,7 +86,7 @@ module privdec import cvw::*; #(parameter cvw_t P) ( // WFI Timout trap will not occur when STATUS_TW is low while in supervisor mode, so the system gets stuck waiting for an interrupt and triggers a watchdog timeout. assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != P.M_MODE) | (P.S_SUPPORTED & PrivilegeModeW == P.U_MODE)) & WFICount[P.WFI_TIMEOUT_BIT]; // coverage on - end else assign WFITimeoutM = 0; + end else assign WFITimeoutM = 1'b0; flopenrc #(1) wfiWReg(clk, reset, FlushW, ~StallW, wfiM, wfiW); diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv index db31afa697..788b396184 100644 --- a/src/privileged/trap.sv +++ b/src/privileged/trap.sv @@ -65,8 +65,8 @@ module trap import cvw::*; #(parameter cvw_t P) ( assign PendingIntsM = MIP_REGW & MIE_REGW; assign IntPendingM = |PendingIntsM; assign Committed = CommittedM | CommittedF; - assign EnabledIntsM = (MIntGlobalEnM ? PendingIntsM & ~MIDELEG_REGW : 0) | (SIntGlobalEnM ? PendingIntsM & MIDELEG_REGW : 0); - assign ValidIntsM = Committed ? 0 : EnabledIntsM; + assign EnabledIntsM = (MIntGlobalEnM ? PendingIntsM & ~MIDELEG_REGW : '0) | (SIntGlobalEnM ? PendingIntsM & MIDELEG_REGW : '0); + assign ValidIntsM = Committed ? '0 : EnabledIntsM; assign InterruptM = (|ValidIntsM) & InstrValidM & (~wfiM | wfiW); // suppress interrupt if the memory system has partially processed a request. Delay interrupt until wfi is in the W stage. // wfiW is to support possible but unlikely back to back wfi instructions. wfiM would be high in the M stage, while also in the W stage. assign DelegateM = P.S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) & @@ -95,29 +95,29 @@ module trap import cvw::*; #(parameter cvw_t P) ( /////////////////////////////////////////// always_comb - if (reset) CauseM = 0; // hard reset 3.3 - else if (ValidIntsM[11]) CauseM = 11; // Machine External Int - else if (ValidIntsM[3]) CauseM = 3; // Machine Sw Int - else if (ValidIntsM[7]) CauseM = 7; // Machine Timer Int - else if (ValidIntsM[9]) CauseM = 9; // Supervisor External Int - else if (ValidIntsM[1]) CauseM = 1; // Supervisor Sw Int - else if (ValidIntsM[5]) CauseM = 5; // Supervisor Timer Int - else if (BothInstrPageFaultM) CauseM = 12; - else if (BothInstrAccessFaultM) CauseM = 1; - else if (IllegalInstrFaultM) CauseM = 2; + if (reset) CauseM = 4'd0; // hard reset 3.3 + else if (ValidIntsM[11]) CauseM = 4'd11; // Machine External Int + else if (ValidIntsM[3]) CauseM = 4'd3; // Machine Sw Int + else if (ValidIntsM[7]) CauseM = 4'd7; // Machine Timer Int + else if (ValidIntsM[9]) CauseM = 4'd9; // Supervisor External Int + else if (ValidIntsM[1]) CauseM = 4'd1; // Supervisor Sw Int + else if (ValidIntsM[5]) CauseM = 4'd5; // Supervisor Timer Int + else if (BothInstrPageFaultM) CauseM = 4'd12; + else if (BothInstrAccessFaultM) CauseM = 4'd1; + else if (IllegalInstrFaultM) CauseM = 4'd2; // coverage off // Misaligned instructions cannot occur in rv64gc - else if (InstrMisalignedFaultM) CauseM = 0; + else if (InstrMisalignedFaultM) CauseM = 4'd0; // coverage on - else if (BreakpointFaultM) CauseM = 3; + else if (BreakpointFaultM) CauseM = 4'd3; else if (EcallFaultM) CauseM = {2'b10, PrivilegeModeW}; - else if (StoreAmoMisalignedFaultM & ~P.ZICCLSM_SUPPORTED) CauseM = 6; // misaligned faults are higher priority if they always are taken - else if (LoadMisalignedFaultM & ~P.ZICCLSM_SUPPORTED) CauseM = 4; - else if (StoreAmoPageFaultM) CauseM = 15; - else if (LoadPageFaultM) CauseM = 13; - else if (StoreAmoAccessFaultM) CauseM = 7; - else if (LoadAccessFaultM) CauseM = 5; - else if (StoreAmoMisalignedFaultM & P.ZICCLSM_SUPPORTED) CauseM = 6; // See priority in Privileged Spec 3.1.15 - else if (LoadMisalignedFaultM & P.ZICCLSM_SUPPORTED) CauseM = 4; - else CauseM = 0; + else if (StoreAmoMisalignedFaultM & ~P.ZICCLSM_SUPPORTED) CauseM = 4'd6; // misaligned faults are higher priority if they always are taken + else if (LoadMisalignedFaultM & ~P.ZICCLSM_SUPPORTED) CauseM = 4'd4; + else if (StoreAmoPageFaultM) CauseM = 4'd15; + else if (LoadPageFaultM) CauseM = 4'd13; + else if (StoreAmoAccessFaultM) CauseM = 4'd7; + else if (LoadAccessFaultM) CauseM = 4'd5; + else if (StoreAmoMisalignedFaultM & P.ZICCLSM_SUPPORTED) CauseM = 4'd6; // See priority in Privileged Spec 3.1.15 + else if (LoadMisalignedFaultM & P.ZICCLSM_SUPPORTED) CauseM = 4'd4; + else CauseM = 4'd0; endmodule diff --git a/src/uncore/ahbapbbridge.sv b/src/uncore/ahbapbbridge.sv index dc7ceeab35..df41c95415 100644 --- a/src/uncore/ahbapbbridge.sv +++ b/src/uncore/ahbapbbridge.sv @@ -89,7 +89,7 @@ module ahbapbbridge import cvw::*; #(parameter cvw_t P, int i; always_comb begin // default: no peripheral selected: read 0, indicate ready during access phase so bus doesn't hang - HRDATA = 0; + HRDATA = '0; PREADYOUT = 1'b1; for (i=0; i Date: Sun, 21 Apr 2024 19:45:09 -0700 Subject: [PATCH 21/31] regression printing improvements --- bin/regression-wally | 9 ++--- src/fpu/fround.sv | 80 +++++++++++++++++++++++++++++++++++++----- testbench/testbench.sv | 5 ++- 3 files changed, 81 insertions(+), 13 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index c67366ee16..95bf17ae95 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -253,7 +253,8 @@ def run_test_case(config): # print(" run_test_case invoking %s" % cmd) os.system(cmd) if search_log_for_text(config.grepstr, grepfile): - print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name)) +# print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name)) + print(f"{bcolors.OKGREEN}%s: Success{bcolors.ENDC}" % (config.cmd)) return 0 else: print(f"{bcolors.FAIL}%s_%s: Failures detected in output{bcolors.ENDC}" % (config.variant, config.name)) @@ -280,8 +281,8 @@ buildroot = '--buildroot' in sys.argv if (nightly): nightMode = "--nightly"; -# sims = ["questa", "verilator", "vcs"] - sims = ["verilator"] # *** uncomment to exercise all simulators + sims = [defaultsim] +# sims = ["questa", "verilator", "vcs"] # *** uncomment to exercise all simulators else: nightMode = "" sims = [defaultsim] @@ -314,8 +315,8 @@ else: # run derivative configurations in nightly regression if (nightly): - addTests(derivconfigtests, defaultsim) addTests(tests_buildrootboot, defaultsim) + addTests(derivconfigtests, defaultsim) else: addTests(tests_buildrootshort, defaultsim) diff --git a/src/fpu/fround.sv b/src/fpu/fround.sv index 7c4c9084bc..e70e25df84 100644 --- a/src/fpu/fround.sv +++ b/src/fpu/fround.sv @@ -31,11 +31,17 @@ module fround import cvw::*; #(parameter cvw_t P) ( input logic Xs, // input's sign input logic [P.NE-1:0] Xe, // input's exponent input logic [P.NF:0] Xm, // input's fraction - input logic [P.FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half) + input logic XNaN, // X is NaN + input logic XSNaN, // X is Signalling NaN + input logic XZero, // X is Zero + input logic [P.FMTBITS-1:0] Fmt // the input's precision (11=quad 01=double 00=single 10=half) ); + logic [P.NE-2:0] Bias; logic [P.NE-1:0] E; + logic [P.NF:0] Imask, Tmasknonneg, Tmaskneg, Tmask, HotE, HotEP1, Trunc, Rnd; + logic Lnonneg, Lp, Rnonneg, Rp, Tp; ////////////////////////////////////////// // Determine exponent bias according to the format @@ -67,11 +73,13 @@ module fround import cvw::*; #(parameter cvw_t P) ( endcase end +/* + // Unbiased exponent assign E = Xe - Bias; ////////////////////////////////////////// - // Compute LSB, rounding bit and Sticky bit mask (TMask) + // Compute LSB L', rounding bit R' and Sticky bit T' // if (E < 0) // negative exponents round to 0 or 1. // L' = 0 // LSB = 0 // if (E = -1) R' = 1, TMask = 0.1111...111 // if (E = -1) 0.5  X < 1. Round bit is 1 @@ -94,15 +102,71 @@ module fround import cvw::*; #(parameter cvw_t P) ( assign Elt0 = (E < 0); assign Eeqm1 = (E == -1); - assign Rneg = Elt0; - mux2 + // Logic for nonnegative mask and rounding bits + assign Imask = {1'b1, {P.NF{1'b0}}} >>> E; + assign Tmasknonneg = ~(IMask >>> 1'b1); + assign HotE = IMask & !(IMask << 1'b1); + assign HotEP1 = HotE >> 1'b1; + assign Lnonneg = |(Xm & HotE); + assign Rnonneg = |(Xm & HotEP1); + assign Trunc = Xm & Imask; + assign Rnd = Trunc + HotE; - // - // if (E = -1) R' = 1, TMask = 0.1111...111 // if (E = -1) 0.5  X < 1. Round bit is 1 - else R' = 0; TMask = 1.1111...111 // if (E < -1), X < 0.5. Round bit is 0 + // mux and AND-OR logic to select final rounding bits + mux2 #(1) Lmux(Lnonneg, 1'b0, Elt0, Lp); + mux2 #(1) Rmux(Rnonneg, Eeqm1, Elt0, Rp); + assign Tmaskneg = {~Eeqm1, {P.NF{1'b1}}}; // 1.11111 or 0.11111 + mux2 #(P.NF+1) Tmaskmux(Tmasknonneg, Tmaskneg, Elt0, Tmask); + assign T' = |(Xm & Tmask); + + + /////////////////////////// + // Rounding, flags, special Cases + // Flags = 0 // unless overridden later + // if (X is NaN) + // W = Canonical NaN + // Invalid = (X is signaling NaN) + // else if (E >= Nf or X is +/- 0) + // W = X // is exact; this also handles infinity + // else + // RoundUp = RoundingLogic(Xs, L', R', T', rm) // Table 16.4 + // if (E < 0) // 0 <= X < 1 rounds to 0 or 1 + // if (RoundUp) {Ws, We, Wf} = {Xs, bias, 0} // +/- 1.0 + // else {Ws, We, Wf} = {Xs, 0, 0} // +/- 0 + // else // // X  1 rounds to an integer or overflows to infinity + // if (RoundUp) Rm = RND else Rm = TRUNC // Round up to RND or down to TRUNC + // if (Rm = 2.0) // rounding requires incrementing exponent + // if (Xe = emax) {Ws, We, Wf} = {Xs, 111..11, 0} // overflow to W = Infinity with sign of Xs + // else {Ws, We, Wf} = {Xs, Xe+1, 0} // 1.0 x 2E+1 + // else {Ws, We, Wf} = {Xs, Xe, Rf} // Rounded fraction, retain sign and exponent + // If (FroundNX instruction) Inexact = R' | T' + /////////////////////////// + + // Exact logic + assign Exact = (E >= Nf | XZero); // result will be exact; no need to round + // Rounding logic: determine whether to round up in magnitude + always_comb + case (Rm) // *** make sure this includes dynamic + 3'b000: // RNE + 3'b001: RoundUp = 0; // RZ + 3'b010: // RN + 3'b011: // RU + 3'b101: // RNTA + default: // + endcase - mux + // output logic + if (XNaN) W = CanonicalNan; // *** + else if (Exact) W = X; + else if (Elt0) + if (RoundUp) W = {Xs, bias, {P.NF}} // *** format conversions + + always_comb + // Flags + assign Invalid = XSNaN; + assign Inexact = FRoundNX & ~(XNaN | Exact) & (Rp | T'); + */ endmodule diff --git a/testbench/testbench.sv b/testbench/testbench.sv index a92af4a081..37f96f1397 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -350,7 +350,8 @@ module testbench; memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"}; bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; uartoutfilename = {"logs/", TEST, "_uart.out"}; - uartoutfile = $fopen(uartoutfilename, "wb"); + uartoutfile = $fopen(uartoutfilename, "wb"); // delete UART output file + $fclose(uartoutfilename); end else memfilename = {pathname, tests[test], ".elf.memfile"}; if (riscofTest) begin @@ -598,7 +599,9 @@ module testbench; always @(posedge clk) begin if (TEST == "buildroot") begin if (~dut.uncoregen.uncore.uartgen.uart.MEMWb & dut.uncoregen.uncore.uartgen.uart.uartPC.A == 3'b000 & ~dut.uncoregen.uncore.uartgen.uart.uartPC.DLAB) begin + uartoutfile = $fopen(uartoutfilename, "a"); // append characters one at a time so we see a consistent log appearing during the run $fwrite(uartoutfile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din); + $fclose(uartoutfilename); end end end From 45196a9959f9c1a3498b463cf28d32598c3cfd0c Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 21 Apr 2024 19:49:55 -0700 Subject: [PATCH 22/31] ignore VCS junk files --- .gitignore | 7 +++++++ sim/verilator/sim-wally-batch | 1 + 2 files changed, 8 insertions(+) create mode 100755 sim/verilator/sim-wally-batch diff --git a/.gitignore b/.gitignore index fb2d17e9bb..c235713a4b 100644 --- a/.gitignore +++ b/.gitignore @@ -203,3 +203,10 @@ benchmarks/coremark/coremark_results.csv fpga/zsbl/OBJ/* fpga/zsbl/bin/* sim/*.svg +sim/vcs/csrc +sim/vcs/profileReport* +sim/vcs/program.out +sim/vcs/sim_out* +sim/vcs/simprofile_dir +sim/vcs/ucli.key +sim/vcs/verdi_config_file diff --git a/sim/verilator/sim-wally-batch b/sim/verilator/sim-wally-batch new file mode 100755 index 0000000000..63b4a4cba3 --- /dev/null +++ b/sim/verilator/sim-wally-batch @@ -0,0 +1 @@ +wsim -s verilator rv64gc arch64i From 26711083dfbf28f1f251c599fffa895556a1fd20 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 21 Apr 2024 20:08:35 -0700 Subject: [PATCH 23/31] Flushing uart.out file to observe progress --- testbench/testbench.sv | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 37f96f1397..493816daaf 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -350,8 +350,7 @@ module testbench; memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"}; bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; uartoutfilename = {"logs/", TEST, "_uart.out"}; - uartoutfile = $fopen(uartoutfilename, "wb"); // delete UART output file - $fclose(uartoutfilename); + uartoutfile = $fopen(uartoutfilename, "w"); // delete UART output file end else memfilename = {pathname, tests[test], ".elf.memfile"}; if (riscofTest) begin @@ -599,9 +598,8 @@ module testbench; always @(posedge clk) begin if (TEST == "buildroot") begin if (~dut.uncoregen.uncore.uartgen.uart.MEMWb & dut.uncoregen.uncore.uartgen.uart.uartPC.A == 3'b000 & ~dut.uncoregen.uncore.uartgen.uart.uartPC.DLAB) begin - uartoutfile = $fopen(uartoutfilename, "a"); // append characters one at a time so we see a consistent log appearing during the run - $fwrite(uartoutfile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din); - $fclose(uartoutfilename); + $fwrite(uartoutfile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din); // append characters one at a time so we see a consistent log appearing during the run + $fflush(uartoutfile); end end end From bd1afa53f8f801877ce85320586c328e522023a3 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 22 Apr 2024 12:28:16 -0700 Subject: [PATCH 24/31] simulation cleanup --- benchmarks/coremark/coremark_sweep.py | 1 + bin/regression-wally | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/benchmarks/coremark/coremark_sweep.py b/benchmarks/coremark/coremark_sweep.py index caf2ac1e94..d912349dc4 100755 --- a/benchmarks/coremark/coremark_sweep.py +++ b/benchmarks/coremark/coremark_sweep.py @@ -107,6 +107,7 @@ 'Load Stalls':lstalls, 'Store Stalls':swtalls,'D$ Accesses':dacc,'D$ Misses':dmiss,'I$ Accesses':iacc,'I$ Misses':imiss, 'Branches':br,'Branch Mispredicts':brm,'BTB Misses':btb,'Jump/JR':jmp,'RAS Wrong':ras,'Returns':ret,'BP Class Pred Wrong':bpc}) + csvfile.flush() csvfile.close() diff --git a/bin/regression-wally b/bin/regression-wally index 95bf17ae95..eac4a294e8 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -257,7 +257,7 @@ def run_test_case(config): print(f"{bcolors.OKGREEN}%s: Success{bcolors.ENDC}" % (config.cmd)) return 0 else: - print(f"{bcolors.FAIL}%s_%s: Failures detected in output{bcolors.ENDC}" % (config.variant, config.name)) + print(f"{bcolors.FAIL}%s: Failures detected in output{bcolors.ENDC}" % (config.cmd)) print(" Check %s" % grepfile) return 1 From 6415bfc3c26d32860201959a664b96685d4d8948 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 23 Apr 2024 10:17:44 -0700 Subject: [PATCH 25/31] Code and testbench cleanup --- src/cache/cacheway.sv | 14 +++++++------- testbench/testbench.sv | 1 - 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 44092b0423..eba64a173f 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -135,17 +135,17 @@ module cacheway import cvw::*; #(parameter cvw_t P, localparam LOGNUMSRAM = $clog2(NUMSRAM); for(words = 0; words < NUMSRAM; words++) begin: word - if (!READ_ONLY_CACHE) begin:wordram - ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData), - .dout(ReadDataLine[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]), - .din(LineWriteData[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]), - .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words])); - end else begin:wordram // no byte-enable needed for i$. + if (READ_ONLY_CACHE) begin:wordram // no byte-enable needed for i$. ram1p1rwe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData), .dout(ReadDataLine[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]), .din(LineWriteData[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]), .we(SelectedWriteWordEn)); - end + end else begin:wordram // D$ needs byte enables + ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData), + .dout(ReadDataLine[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]), + .din(LineWriteData[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]), + .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words])); + end end // AND portion of distributed read multiplexers diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 4cbdd29890..f6a07b29ca 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -625,7 +625,6 @@ module testbench; dut.core.ieu.dp.regf.wd3 == 1)) | ((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) | ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); - //assign DCacheFlushStart = TestComplete; end DCacheFlushFSM #(P) DCacheFlushFSM(.clk, .start(DCacheFlushStart), .done(DCacheFlushDone)); From 2f5680b7a618335a67a98e7d756d94a69700325f Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 23 Apr 2024 10:18:00 -0700 Subject: [PATCH 26/31] Silencing new version of Verilator in lint --- bin/lint-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/lint-wally b/bin/lint-wally index 08d189ec75..d1fdc7dccd 100755 --- a/bin/lint-wally +++ b/bin/lint-wally @@ -26,7 +26,7 @@ fi for config in ${configs[@]}; do # echo "$config linting..." - if !($verilator --no-timing --lint-only --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then + if !($verilator --no-timing --lint-only --quiet --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then if [ "$1" == "-nightly" ]; then echo -e "${RED}$config failed lint${NC}" fails=$((fails+1)) From 2dd54b36127dd5d67533982038d71145cdfa9fb6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 23 Apr 2024 10:18:28 -0700 Subject: [PATCH 27/31] adding ssmtp for nightly regression emails --- bin/wally-tool-chain-install.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 336ce33e4d..954b1d9898 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -46,7 +46,7 @@ sudo mkdir -p $RISCV # Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/) sudo apt update -y sudo apt upgrade -y -sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils bc mutt +sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils bc mutt ssmtp # Other python libraries used through the book. sudo pip3 install sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown From 0dc2c7d16a28174d62841c2e3089f463a2e62a6d Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 23 Apr 2024 10:19:08 -0700 Subject: [PATCH 28/31] Fixed deriv path in Verilator makefile --- sim/verilator/Makefile | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile index 505818f302..7acce82b87 100644 --- a/sim/verilator/Makefile +++ b/sim/verilator/Makefile @@ -10,7 +10,7 @@ OPT= PARAMS?=-DVERILATOR=1 --no-trace-top NONPROF?=--stats VERILATOR_DIR=${WALLY}/sim/verilator -SOURCE=${WALLY}/config/shared/*.vh ${WALLY}/config/${WALLYCONF} ${WALLY}/src/cvw.sv ${WALLY}/testbench/*.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv +SOURCE=${WALLY}/config/shared/*.vh ${WALLY}/config/${WALLYCONF} ${WALLY}/config/deriv/${WALLYCONF} ${WALLY}/src/cvw.sv ${WALLY}/testbench/*.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv EXTRA_ARGS= @@ -41,23 +41,19 @@ profile: obj_dir_profiling/Vtestbench_$(WALLYCONF) run: wkdir/$(WALLYCONF)_$(TEST)/Vtestbench mkdir -p $(VERILATOR_DIR)/logs -# wkdir/$(WALLYCONF)_$(TEST)/Vtestbench +TEST=$(TEST) 2>&1 > $(VERILATOR_DIR)/logs/$(WALLYCONF)_$(TEST).log wkdir/$(WALLYCONF)_$(TEST)/Vtestbench +TEST=$(TEST) -# echo "Please check $(VERILATOR_DIR)/logs/$(WALLYCONF)_$(TEST).log for logs and output files." - -wkdir/$(WALLYCONF)_$(TEST)/Vtestbench: $(SOURCE) +wkdir/$(WALLYCONF)_$(TEST)/Vtestbench: $(DEPENDENCIES) verilator \ --Mdir wkdir/$(WALLYCONF)_$(TEST) -o Vtestbench \ --binary --trace \ $(OPT) $(PARAMS) $(NONPROF) \ $(EXTRA_ARGS) \ --timescale "1ns/1ns" --timing --top-module testbench --relative-includes \ - "-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" \ + $(INCLUDE_PATH) \ ${WALLY}/sim/verilator/wrapper.c \ - ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv + $(SOURCES) - obj_dir_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES) mkdir -p obj_dir_profiling verilator \ @@ -67,7 +63,7 @@ obj_dir_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES) $(EXTRA_ARGS) \ --timescale "1ns/1ns" --timing --top-module testbench --relative-includes \ $(INCLUDE_PATH) \ - wrapper.c \ + ${WALLY}/sim/verilator/wrapper.c \ $(SOURCES) questa: From a722c7cd08cef7c1d8e6a0f036f4bc70994dadfe Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 23 Apr 2024 10:19:53 -0700 Subject: [PATCH 29/31] Ignoring vcd output --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index c235713a4b..0d84180688 100644 --- a/.gitignore +++ b/.gitignore @@ -210,3 +210,4 @@ sim/vcs/sim_out* sim/vcs/simprofile_dir sim/vcs/ucli.key sim/vcs/verdi_config_file +sim/verilator/testbench.vcd From e2894ed278c9bc3db41fbb0e013820b7eec84181 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 24 Apr 2024 04:41:25 -0700 Subject: [PATCH 30/31] derived nobpred_rv32gc config for coremark test --- .gitignore | 2 +- benchmarks/coremark/Makefile | 5 +++-- config/derivlist.txt | 3 +++ 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/.gitignore b/.gitignore index 0d84180688..a056d82f86 100644 --- a/.gitignore +++ b/.gitignore @@ -210,4 +210,4 @@ sim/vcs/sim_out* sim/vcs/simprofile_dir sim/vcs/ucli.key sim/vcs/verdi_config_file -sim/verilator/testbench.vcd +sim/*/testbench.vcd diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile index 527868eac0..63afc34bf6 100644 --- a/benchmarks/coremark/Makefile +++ b/benchmarks/coremark/Makefile @@ -12,6 +12,7 @@ sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \ $(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32) ARCH := rv$(XLEN)im_zicsr_zba_zbb_zbs +CONFIG := rv$(XLEN)gc #ARCH := rv$(XLEN)gc #ARCH := rv$(XLEN)imc_zicsr #ARCH := rv$(XLEN)im_zicsr @@ -26,9 +27,9 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \ all: $(work_dir)/coremark.bare.riscv.elf.memfile -run: +run: $(work_dir)/coremark.bare.riscv.elf.memfile # time wsim rv$(XLEN)gc coremark --sim verilator 2>&1 | tee $(work_dir)/coremark.sim.log - time wsim rv$(XLEN)gc coremark 2>&1 | tee $(work_dir)/coremark.sim.log + time wsim ${CONFIG} coremark 2>&1 | tee $(work_dir)/coremark.sim.log $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv riscv64-unknown-elf-objdump -D $< > $<.elf.objdump diff --git a/config/derivlist.txt b/config/derivlist.txt index 3f6a869d96..66c61f426c 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -237,6 +237,9 @@ BURST_EN 1 # Branch predictor simulations +deriv nobpred_rv32gc rv32gc +BPRED_SUPPORTED 0 + deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc BPRED_SIZE 32'd6 From 32b6e6a8abb30bcc5dca4d1c623ce95cadf8ca06 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 24 Apr 2024 04:42:47 -0700 Subject: [PATCH 31/31] fround progress --- src/fpu/fround.sv | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/src/fpu/fround.sv b/src/fpu/fround.sv index e70e25df84..195f446846 100644 --- a/src/fpu/fround.sv +++ b/src/fpu/fround.sv @@ -117,7 +117,7 @@ module fround import cvw::*; #(parameter cvw_t P) ( mux2 #(1) Rmux(Rnonneg, Eeqm1, Elt0, Rp); assign Tmaskneg = {~Eeqm1, {P.NF{1'b1}}}; // 1.11111 or 0.11111 mux2 #(P.NF+1) Tmaskmux(Tmasknonneg, Tmaskneg, Elt0, Tmask); - assign T' = |(Xm & Tmask); + assign Tp = |(Xm & Tmask); /////////////////////////// @@ -133,7 +133,7 @@ module fround import cvw::*; #(parameter cvw_t P) ( // if (E < 0) // 0 <= X < 1 rounds to 0 or 1 // if (RoundUp) {Ws, We, Wf} = {Xs, bias, 0} // +/- 1.0 // else {Ws, We, Wf} = {Xs, 0, 0} // +/- 0 - // else // // X  1 rounds to an integer or overflows to infinity + // else // // X >= 1 rounds to an integer or overflows to infinity // if (RoundUp) Rm = RND else Rm = TRUNC // Round up to RND or down to TRUNC // if (Rm = 2.0) // rounding requires incrementing exponent // if (Xe = emax) {Ws, We, Wf} = {Xs, 111..11, 0} // overflow to W = Infinity with sign of Xs @@ -148,12 +148,12 @@ module fround import cvw::*; #(parameter cvw_t P) ( // Rounding logic: determine whether to round up in magnitude always_comb case (Rm) // *** make sure this includes dynamic - 3'b000: // RNE - 3'b001: RoundUp = 0; // RZ - 3'b010: // RN - 3'b011: // RU - 3'b101: // RNTA - default: // + 3'b000: RoundUp = Rp & (Lp | Tp); // RNE + 3'b001: RoundUp = 0; // RZ + 3'b010: RoundUp = Xs & (Rp | Tp); // RN + 3'b011: RoundUp = ~Xs & (Rp | Tp); // RP + 3'b101: RoundUp = Rp; // RNTA + default: RoundUp = 0; // should never happen endcase // output logic @@ -162,6 +162,8 @@ module fround import cvw::*; #(parameter cvw_t P) ( else if (Elt0) if (RoundUp) W = {Xs, bias, {P.NF}} // *** format conversions + *** may not need to round to infinity; update docs and pseudocode above + always_comb // Flags