[BUG] External supervisor mode interrupt

[AyoubJalali]

Is there an existing CVA6 bug for this?

• I have searched the existing bug issues

Bug Description

Hello,
This a CV32A65X RTL bug, as the core configuration does not support S-mode, so should not support S-mode interrupt, but the CV32A65X has an input irq_i[0] for Supervisor external interrupt, when irq_i[0] is assert the MIP.SEIP is asserted, that the normal behavior if we support the S-mode, but the CV32A65X does not.

[JeanRochCoulon]

Great !

[Gchauvon]

I can't reproduce this issue. Asserting irq_i[0] only raise MIP.MEIP and MIP.SEIP stay at 0.
The RTL seems fine since PR #2017 which was merged few weeks before your issue.

Can we close this issue ?

[AyoubJalali]

You should assert irq_i[1] in UVM TB so that you can see that MIP.SEIP is asserted.