From b28545ef7899b69a7d72267623e179973b356b31 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Wed, 15 Jan 2025 20:29:18 +1100 Subject: [PATCH 1/5] id_stage/pmp_entry: Fix formatting (#2705) Run verible verilog format to fix upstream formatting. --- core/id_stage.sv | 64 +++++++++++++++++++-------------------- core/pmp/src/pmp_entry.sv | 4 +-- 2 files changed, 34 insertions(+), 34 deletions(-) diff --git a/core/id_stage.sv b/core/id_stage.sv index 6bed74bd4e..1ead6b9347 100644 --- a/core/id_stage.sv +++ b/core/id_stage.sv @@ -161,22 +161,22 @@ module id_stage #( .x_compressed_req_t(x_compressed_req_t), .x_compressed_resp_t(x_compressed_resp_t) ) i_cvxif_compressed_if_driver_i ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .hart_id_i (hart_id_i), - .is_compressed_i (is_compressed_cvxif), - .is_illegal_i (is_illegal_cvxif), - .instruction_i (instruction_cvxif), - .instruction_valid_i (fetch_entry_valid_i), - .is_compressed_o (is_compressed_cmp), - .is_illegal_o (is_illegal_cmp), - .instruction_o (instruction), - .stall_i (stall_macro_deco), - .stall_o (stall_instr_fetch), - .compressed_ready_i(compressed_ready_i), - .compressed_resp_i (compressed_resp_i), - .compressed_valid_o(compressed_valid_o), - .compressed_req_o (compressed_req_o) + .clk_i (clk_i), + .rst_ni (rst_ni), + .hart_id_i (hart_id_i), + .is_compressed_i (is_compressed_cvxif), + .is_illegal_i (is_illegal_cvxif), + .instruction_i (instruction_cvxif), + .instruction_valid_i(fetch_entry_valid_i), + .is_compressed_o (is_compressed_cmp), + .is_illegal_o (is_illegal_cmp), + .instruction_o (instruction), + .stall_i (stall_macro_deco), + .stall_o (stall_instr_fetch), + .compressed_ready_i (compressed_ready_i), + .compressed_resp_i (compressed_resp_i), + .compressed_valid_o (compressed_valid_o), + .compressed_req_o (compressed_req_o) ); end else begin cvxif_compressed_if_driver #( @@ -184,22 +184,22 @@ module id_stage #( .x_compressed_req_t(x_compressed_req_t), .x_compressed_resp_t(x_compressed_resp_t) ) i_cvxif_compressed_if_driver_i ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .hart_id_i (hart_id_i), - .is_compressed_i (is_compressed), - .is_illegal_i (is_illegal), - .instruction_valid_i (fetch_entry_valid_i), - .instruction_i (compressed_instr), - .is_compressed_o (is_compressed_cmp), - .is_illegal_o (is_illegal_cmp), - .instruction_o (instruction), - .stall_i (1'b0), - .stall_o (stall_instr_fetch), - .compressed_ready_i(compressed_ready_i), - .compressed_resp_i (compressed_resp_i), - .compressed_valid_o(compressed_valid_o), - .compressed_req_o (compressed_req_o) + .clk_i (clk_i), + .rst_ni (rst_ni), + .hart_id_i (hart_id_i), + .is_compressed_i (is_compressed), + .is_illegal_i (is_illegal), + .instruction_valid_i(fetch_entry_valid_i), + .instruction_i (compressed_instr), + .is_compressed_o (is_compressed_cmp), + .is_illegal_o (is_illegal_cmp), + .instruction_o (instruction), + .stall_i (1'b0), + .stall_o (stall_instr_fetch), + .compressed_ready_i (compressed_ready_i), + .compressed_resp_i (compressed_resp_i), + .compressed_valid_o (compressed_valid_o), + .compressed_req_o (compressed_req_o) ); assign is_last_macro_instr_o = '0; assign is_double_rd_macro_instr_o = '0; diff --git a/core/pmp/src/pmp_entry.sv b/core/pmp/src/pmp_entry.sv index 8ae956b28f..d024a9a09f 100644 --- a/core/pmp/src/pmp_entry.sv +++ b/core/pmp/src/pmp_entry.sv @@ -78,8 +78,8 @@ module pmp_entry #( assert (size >= 2); if (conf_addr_mode_i == riscv::NAPOT) begin assert (size > 2); - if (size < CVA6Cfg.PLEN-2) assert (conf_addr_i[size-3] == 0); - for (int i = 0; i < CVA6Cfg.PLEN-2; i++) begin + if (size < CVA6Cfg.PLEN - 2) assert (conf_addr_i[size-3] == 0); + for (int i = 0; i < CVA6Cfg.PLEN - 2; i++) begin if (size > 3 && i <= size - 4) begin assert (conf_addr_i[i] == 1); // check that all the rest are ones end From cb5c623e5083656fd6bead45c6a7128e891f121a Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Wed, 15 Jan 2025 21:17:37 +1100 Subject: [PATCH 2/5] mmu: Fix pmpcfg, pmpaddr width (#2707) PR #2692 changed the bus width for `pmpcfg` and `pmpaddr` in most modules. Do the same in `cva6_mmu` and `cva6_ptw` to fix port width mismatches. --- core/cva6_mmu/cva6_mmu.sv | 4 ++-- core/cva6_mmu/cva6_ptw.sv | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/core/cva6_mmu/cva6_mmu.sv b/core/cva6_mmu/cva6_mmu.sv index 8c1791bbf0..5382279938 100644 --- a/core/cva6_mmu/cva6_mmu.sv +++ b/core/cva6_mmu/cva6_mmu.sv @@ -100,8 +100,8 @@ module cva6_mmu // PMP - input riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries-1:0] pmpcfg_i, - input logic [CVA6Cfg.NrPMPEntries-1:0][CVA6Cfg.PLEN-3:0] pmpaddr_i + input riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg_i, + input logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr_i ); // memory management, pte for cva6 diff --git a/core/cva6_mmu/cva6_ptw.sv b/core/cva6_mmu/cva6_ptw.sv index 0700891db0..a5fef76fcc 100644 --- a/core/cva6_mmu/cva6_ptw.sv +++ b/core/cva6_mmu/cva6_ptw.sv @@ -83,8 +83,8 @@ module cva6_ptw output logic shared_tlb_miss_o, // PMP - input riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries-1:0] pmpcfg_i, - input logic [CVA6Cfg.NrPMPEntries-1:0][CVA6Cfg.PLEN-3:0] pmpaddr_i, + input riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg_i, + input logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr_i, output logic [CVA6Cfg.PLEN-1:0] bad_paddr_o, output logic [CVA6Cfg.GPLEN-1:0] bad_gpaddr_o ); From 86c53c53345e17630e10e872058ffe650148a275 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Thu, 16 Jan 2025 03:47:07 +1100 Subject: [PATCH 3/5] config_pkg: Update configurations with new flush parameter (#2704) #2691 extended the cva6_user_cfg_t struct by two new parameters to control the cache's flush behaviour. Add these new parameters to all configs to fix compilation errors due to incomplete struct literals. --- core/include/cv32a6_embedded_config_pkg_deprecated.sv | 5 +++++ core/include/cv32a6_ima_sv32_fpga_config_pkg.sv | 2 ++ core/include/cv32a6_imac_sv0_config_pkg.sv | 2 ++ core/include/cv32a6_imafc_sv32_config_pkg.sv | 4 +++- core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv | 5 +++++ core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv | 5 +++++ core/include/cv64a6_imafdch_sv39_config_pkg.sv | 5 +++++ core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv | 5 +++++ core/include/cv64a6_imafdcv_sv39_config_pkg.sv | 5 +++++ core/include/cv64a6_mmu_config_pkg.sv | 2 ++ 10 files changed, 39 insertions(+), 1 deletion(-) diff --git a/core/include/cv32a6_embedded_config_pkg_deprecated.sv b/core/include/cv32a6_embedded_config_pkg_deprecated.sv index ce5e635107..bfff31d25f 100644 --- a/core/include/cv32a6_embedded_config_pkg_deprecated.sv +++ b/core/include/cv32a6_embedded_config_pkg_deprecated.sv @@ -42,6 +42,9 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheSetAssoc = 8; localparam CVA6ConfigDcacheLineWidth = 128; + localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; + localparam CVA6ConfigDcacheIdWidth = 1; localparam CVA6ConfigMemTidWidth = 2; @@ -139,6 +142,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: bit'(CVA6ConfigDcacheFlushOnFence), + DcacheInvalidateOnFlush: bit'(CVA6ConfigDcacheInvalidateOnFlush), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index f459765708..7c680172fc 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -140,6 +140,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: bit'(0), + DcacheInvalidateOnFlush: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index 6ab85d509d..0cc82debb8 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -140,6 +140,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: bit'(0), + DcacheInvalidateOnFlush: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index 2575d7ac3b..3801eda239 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -136,10 +136,12 @@ package cva6_config_pkg; IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth), + DCacheType: CVA6ConfigDcacheType, DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), - DCacheType: CVA6ConfigDcacheType, + DcacheFlushOnFence: bit'(0), + DcacheInvalidateOnFlush: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv index 2622377d8f..8cb0f17bad 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -43,6 +43,9 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheSetAssoc = 8; localparam CVA6ConfigDcacheLineWidth = 128; + localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; + localparam CVA6ConfigDcacheIdWidth = 1; localparam CVA6ConfigMemTidWidth = 2; @@ -140,6 +143,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: bit'(CVA6ConfigDcacheFlushOnFence), + DcacheInvalidateOnFlush: bit'(CVA6ConfigDcacheInvalidateOnFlush), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index 5b785232c0..82be807aab 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -43,6 +43,9 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheSetAssoc = 8; localparam CVA6ConfigDcacheLineWidth = 128; + localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; + localparam CVA6ConfigDcacheIdWidth = 1; localparam CVA6ConfigMemTidWidth = 2; @@ -140,6 +143,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence), + DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv64a6_imafdch_sv39_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_config_pkg.sv index dcdb20691e..87500e7124 100644 --- a/core/include/cv64a6_imafdch_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_config_pkg.sv @@ -43,6 +43,9 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheSetAssoc = 8; localparam CVA6ConfigDcacheLineWidth = 128; + localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; + localparam CVA6ConfigDcacheIdWidth = 1; localparam CVA6ConfigMemTidWidth = 2; @@ -140,6 +143,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence), + DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv index 8603bb1926..09de6d9993 100644 --- a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv @@ -43,6 +43,9 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheSetAssoc = 8; localparam CVA6ConfigDcacheLineWidth = 128; + localparam CVA6ConfigDcacheFlushOnFence = 1'b1; + localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; + localparam CVA6ConfigDcacheIdWidth = 1; localparam CVA6ConfigMemTidWidth = 2; @@ -140,6 +143,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence), + DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index e2a9add4a6..5b0917fed2 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -43,6 +43,9 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheSetAssoc = 4; localparam CVA6ConfigDcacheLineWidth = 128; + localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; + localparam CVA6ConfigDcacheIdWidth = 1; localparam CVA6ConfigMemTidWidth = 2; @@ -139,6 +142,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence), + DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv64a6_mmu_config_pkg.sv b/core/include/cv64a6_mmu_config_pkg.sv index 50e4131d4f..603593c11f 100644 --- a/core/include/cv64a6_mmu_config_pkg.sv +++ b/core/include/cv64a6_mmu_config_pkg.sv @@ -95,6 +95,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(32768), DcacheSetAssoc: unsigned'(8), DcacheLineWidth: unsigned'(128), + DcacheFlushOnFence: bit'(0), + DcacheInvalidateOnFlush: bit'(0), DataUserEn: unsigned'(0), WtDcacheWbufDepth: int'(2), FetchUserWidth: unsigned'(64), From 21b247dca7f35a7897af28456cb3df37aaa4d87e Mon Sep 17 00:00:00 2001 From: Guillaume Chauvon <94678394+Gchauvon@users.noreply.github.com> Date: Wed, 15 Jan 2025 17:48:01 +0100 Subject: [PATCH 4/5] CI: copy seeds in artifacts for generated tests (#2708) Save seeds in artifacts for generated tests. It will help to reproduce the test in case of failure. --- .gitlab-ci.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index c3f0a6a391..cc62fda9cd 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -170,6 +170,7 @@ smoke-gen: SPIKE_TANDEM: 1 script: - bash verif/regress/smoke-gen_tests.sh + - cp verif/sim/seedlist.yaml artifacts/logs/ - !reference [.simu_after_script] smoke-bench: From 5518a41c08a1949c606d54b9ac631e8f7635e7f3 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Wed, 15 Jan 2025 19:57:00 +0100 Subject: [PATCH 5/5] Bump verif/core-v-verif from `464bf7a` to `19b5a3f` (#2703) --- verif/core-v-verif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verif/core-v-verif b/verif/core-v-verif index 464bf7a0d7..19b5a3f94d 160000 --- a/verif/core-v-verif +++ b/verif/core-v-verif @@ -1 +1 @@ -Subproject commit 464bf7a0d730eaf614acac258b412829217b6465 +Subproject commit 19b5a3f94d9b091701f020146072dd214b93d34d