diff --git a/rtl/cv32e40x_controller_bypass.sv b/rtl/cv32e40x_controller_bypass.sv
index fd04c42d..7fef35f8 100644
--- a/rtl/cv32e40x_controller_bypass.sv
+++ b/rtl/cv32e40x_controller_bypass.sv
@@ -92,7 +92,6 @@ module cv32e40x_controller_bypass import cv32e40x_pkg::*;
   rf_addr_t                          rf_waddr_wb;               // WB rf_waddr
 
   logic                              sys_mret_unqual_id;        // MRET in ID (not qualified with sys_en)
-  logic                              csr_exp_unqual_id;         // Explicit CSR in ID (not qualified with csr_en)
   logic                              csr_impl_rd_unqual_id;     // Implicit CSR read in ID (not qualified)
   logic                              jmpr_unqual_id;            // JALR in ID (not qualified with alu_en)
   logic                              tbljmp_unqual_id;          // Table jump in ID (not qualified with alu_en)
@@ -116,7 +115,6 @@ module cv32e40x_controller_bypass import cv32e40x_pkg::*;
   // eventually empty out removing that reasons for stall conditions.
 
   assign sys_mret_unqual_id = sys_mret_id_i && if_id_pipe_i.instr_valid;
-  assign csr_exp_unqual_id = csr_en_raw_id_i && if_id_pipe_i.instr_valid;
   assign jmpr_unqual_id = alu_jmpr_id_i && if_id_pipe_i.instr_valid;
   assign tbljmp_unqual_id = if_id_pipe_i.instr_meta.tbljmp && if_id_pipe_i.instr_valid;
 
diff --git a/rtl/cv32e40x_controller_fsm.sv b/rtl/cv32e40x_controller_fsm.sv
index f379f474..29d5ed0b 100644
--- a/rtl/cv32e40x_controller_fsm.sv
+++ b/rtl/cv32e40x_controller_fsm.sv
@@ -686,7 +686,6 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*;
     ctrl_fsm_o.debug_csr_save   = 1'b0;
     ctrl_fsm_o.debug_trigger_hit = '0;          // Mask of which triggers did hit.
     ctrl_fsm_o.debug_trigger_hit_update = 1'b0; // Signal that hit bits of mcontrol6 shall be written.
-    ctrl_fsm_o.block_data_addr  = 1'b0;
 
     // Single step halting of IF
     single_step_halt_if_n       = single_step_halt_if_q;
diff --git a/rtl/cv32e40x_cs_registers.sv b/rtl/cv32e40x_cs_registers.sv
index 3caec7e8..aaec4730 100644
--- a/rtl/cv32e40x_cs_registers.sv
+++ b/rtl/cv32e40x_cs_registers.sv
@@ -1520,7 +1520,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
   assign mconfigptr_rdata   = 32'h0;
 
   // Only machine mode is supported
-  assign priv_lvl_rdata     = PRIV_LVL_M;
+  assign priv_lvl_rdata     = priv_lvl_q;
   assign priv_lvl_q         = PRIV_LVL_M;
   assign priv_lvl_lsu_o     = PRIV_LVL_M;
   assign priv_lvl_if_ctrl_o.priv_lvl     = PRIV_LVL_M;
diff --git a/rtl/include/cv32e40x_pkg.sv b/rtl/include/cv32e40x_pkg.sv
index 5c6eefbf..1fcc9de6 100644
--- a/rtl/include/cv32e40x_pkg.sv
+++ b/rtl/include/cv32e40x_pkg.sv
@@ -1348,10 +1348,6 @@ typedef struct packed {
                                       // Setting to 11 bits (max), unused bits will be tied off
   logic [4:0]  nmi_mtvec_index;       // Offset into mtvec when taking an NMI
 
-  // To WB stage
-  logic        block_data_addr;       // To LSU to prevent data_addr_wb_i updates between error and taken NMI
-
-
   logic        irq_ack;               // Irq has been taken
   logic [9:0]  irq_id;                // Id of taken irq. Max width (1024 interrupts), unused bits will be tied off
   logic [7:0]  irq_level;             // Level of taken irq (CLIC only)