From 4ec810d33b4b98b41b5865f675349510e6e5b526 Mon Sep 17 00:00:00 2001 From: Arjan Bink Date: Tue, 21 Feb 2023 17:05:08 +0100 Subject: [PATCH] Renamed CLIC related parameters (removed SM prefix) Signed-off-by: Arjan Bink --- bhv/cv32e40x_rvfi.sv | 6 +-- bhv/cv32e40x_wrapper.sv | 32 ++++++------- rtl/cv32e40x_clic_int_controller.sv | 10 ++--- rtl/cv32e40x_controller.sv | 8 ++-- rtl/cv32e40x_controller_fsm.sv | 12 ++--- rtl/cv32e40x_core.sv | 40 ++++++++--------- rtl/cv32e40x_cs_registers.sv | 70 ++++++++++++++--------------- rtl/cv32e40x_decoder.sv | 4 +- rtl/cv32e40x_i_decoder.sv | 6 +-- rtl/cv32e40x_id_stage.sv | 4 +- rtl/cv32e40x_if_stage.sv | 8 ++-- rtl/cv32e40x_prefetch_unit.sv | 4 +- rtl/cv32e40x_prefetcher.sv | 2 +- sva/cv32e40x_controller_fsm_sva.sv | 6 +-- sva/cv32e40x_core_sva.sv | 14 +++--- sva/cv32e40x_cs_registers_sva.sv | 6 +-- sva/cv32e40x_prefetch_unit_sva.sv | 6 +-- sva/cv32e40x_prefetcher_sva.sv | 6 +-- sva/cv32e40x_rvfi_sva.sv | 6 +-- yaml/csr.yaml.m4 | 2 +- 20 files changed, 126 insertions(+), 126 deletions(-) diff --git a/bhv/cv32e40x_rvfi.sv b/bhv/cv32e40x_rvfi.sv index 7bb43ae2..eb6af374 100644 --- a/bhv/cv32e40x_rvfi.sv +++ b/bhv/cv32e40x_rvfi.sv @@ -22,9 +22,9 @@ module cv32e40x_rvfi import cv32e40x_pkg::*; import cv32e40x_rvfi_pkg::*; #( - parameter bit SMCLIC = 0, - parameter int DEBUG = 1, - parameter a_ext_e A_EXT = A_NONE + parameter bit CLIC = 0, + parameter int DEBUG = 1, + parameter a_ext_e A_EXT = A_NONE ) ( input logic clk_i, diff --git a/bhv/cv32e40x_wrapper.sv b/bhv/cv32e40x_wrapper.sv index c50ad779..ac24a203 100644 --- a/bhv/cv32e40x_wrapper.sv +++ b/bhv/cv32e40x_wrapper.sv @@ -64,9 +64,9 @@ module cv32e40x_wrapper parameter logic [31:0] X_MISA = 32'h00000000, parameter logic [1:0] X_ECS_XS = 2'b00, parameter int NUM_MHPMCOUNTERS = 1, - parameter bit SMCLIC = 0, - parameter int SMCLIC_ID_WIDTH = 5, - parameter int SMCLIC_INTTHRESHBITS = 8, + parameter bit CLIC = 0, + parameter int CLIC_ID_WIDTH = 5, + parameter int CLIC_INTTHRESHBITS = 8, parameter int DBG_NUM_TRIGGERS = 1, parameter int PMA_NUM_REGIONS = 0, parameter pma_cfg_t PMA_CFG[PMA_NUM_REGIONS-1:0] = '{default:PMA_R_DEFAULT}, @@ -142,7 +142,7 @@ module cv32e40x_wrapper // CLIC Interface input logic clic_irq_i, - input logic [SMCLIC_ID_WIDTH-1:0] clic_irq_id_i, + input logic [CLIC_ID_WIDTH-1:0] clic_irq_id_i, input logic [ 7:0] clic_irq_level_i, input logic [ 1:0] clic_irq_priv_i, input logic clic_irq_shv_i, @@ -228,7 +228,7 @@ module cv32e40x_wrapper cv32e40x_controller_fsm_sva #(.X_EXT(X_EXT), .DEBUG(DEBUG), - .SMCLIC(SMCLIC)) + .CLIC(CLIC)) controller_fsm_sva ( .lsu_outstanding_cnt (core_i.load_store_unit_i.cnt_q), .rf_we_wb_i (core_i.wb_stage_i.rf_we_wb_o ), @@ -251,7 +251,7 @@ module cv32e40x_wrapper bind cv32e40x_cs_registers: core_i.cs_registers_i cv32e40x_cs_registers_sva - #(.SMCLIC(SMCLIC), + #(.CLIC (CLIC), .DEBUG (DEBUG)) cs_registers_sva (.wb_valid_i (core_i.wb_valid ), .ctrl_fsm_cs (core_i.controller_i.controller_fsm_i.ctrl_fsm_cs), @@ -298,7 +298,7 @@ module cv32e40x_wrapper bind cv32e40x_prefetch_unit: core_i.if_stage_i.prefetch_unit_i cv32e40x_prefetch_unit_sva - #(.SMCLIC(SMCLIC)) + #(.CLIC(CLIC)) prefetch_unit_sva ( .ctrl_fsm_cs (core_i.controller_i.controller_fsm_i.ctrl_fsm_cs), .debug_req_i (core_i.debug_req_i), @@ -319,16 +319,16 @@ module cv32e40x_wrapper bind cv32e40x_prefetcher: core_i.if_stage_i.prefetch_unit_i.prefetcher_i cv32e40x_prefetcher_sva - #(.SMCLIC(SMCLIC)) + #(.CLIC(CLIC)) prefetcher_sva ( .prefetch_is_clic_ptr (core_i.if_stage_i.prefetch_unit_i.prefetch_is_clic_ptr_o), .*); bind cv32e40x_core: core_i cv32e40x_core_sva #(.A_EXT(A_EXT), - .DEBUG (DEBUG), + .DEBUG(DEBUG), .PMA_NUM_REGIONS(PMA_NUM_REGIONS), - .SMCLIC(SMCLIC)) + .CLIC(CLIC)) core_sva (// probed cs_registers signals .cs_registers_mie_q (core_i.cs_registers_i.mie_q), .cs_registers_mepc_n (core_i.cs_registers_i.mepc_n), @@ -366,7 +366,7 @@ module cv32e40x_wrapper .lsu_exokay_wb (core_i.data_exokay_i), // todo: Could poke into LSU, but this signal is fed directly through the LSU .*); generate -if (SMCLIC) begin : clic_asserts +if (CLIC) begin : clic_asserts bind cv32e40x_clic_int_controller: core_i.gen_clic_interrupt.clic_int_controller_i cv32e40x_clic_int_controller_sva @@ -473,7 +473,7 @@ endgenerate bind cv32e40x_rvfi: rvfi_i cv32e40x_rvfi_sva - #(.SMCLIC(SMCLIC), + #(.CLIC (CLIC), .DEBUG (DEBUG), .A_EXT (A_EXT)) rvfi_sva(.irq_ack(core_i.irq_ack), @@ -503,7 +503,7 @@ endgenerate ); cv32e40x_rvfi - #(.SMCLIC(SMCLIC), + #(.CLIC (CLIC), .DEBUG (DEBUG), .A_EXT (A_EXT)) rvfi_i @@ -785,9 +785,9 @@ endgenerate .X_MISA ( X_MISA ), .X_ECS_XS ( X_ECS_XS ), .NUM_MHPMCOUNTERS ( NUM_MHPMCOUNTERS ), - .SMCLIC ( SMCLIC ), - .SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ), - .SMCLIC_INTTHRESHBITS ( SMCLIC_INTTHRESHBITS ), + .CLIC ( CLIC ), + .CLIC_ID_WIDTH ( CLIC_ID_WIDTH ), + .CLIC_INTTHRESHBITS ( CLIC_INTTHRESHBITS ), .DEBUG ( DEBUG ), .DM_REGION_START ( DM_REGION_START ), .DM_REGION_END ( DM_REGION_END ), diff --git a/rtl/cv32e40x_clic_int_controller.sv b/rtl/cv32e40x_clic_int_controller.sv index 778aa752..8440c10e 100644 --- a/rtl/cv32e40x_clic_int_controller.sv +++ b/rtl/cv32e40x_clic_int_controller.sv @@ -28,7 +28,7 @@ module cv32e40x_clic_int_controller import cv32e40x_pkg::*; #( - parameter int SMCLIC_ID_WIDTH = 5 + parameter int CLIC_ID_WIDTH = 5 ) ( input logic clk, @@ -36,7 +36,7 @@ module cv32e40x_clic_int_controller import cv32e40x_pkg::*; // CLIC interface input logic clic_irq_i, // CLIC interrupt pending - input logic [SMCLIC_ID_WIDTH-1:0] clic_irq_id_i, // ID of pending interrupt + input logic [CLIC_ID_WIDTH-1:0] clic_irq_id_i, // ID of pending interrupt input logic [7:0] clic_irq_level_i, // Level of pending interrupt input logic [1:0] clic_irq_priv_i, // Privilege level of pending interrupt (always machine mode) (not used) input logic clic_irq_shv_i, // Is pending interrupt vectored? @@ -58,7 +58,7 @@ module cv32e40x_clic_int_controller import cv32e40x_pkg::*; // To cs_registers output logic mnxti_irq_pending_o, // An interrupt is available to the mnxti CSR read - output logic [SMCLIC_ID_WIDTH-1:0] mnxti_irq_id_o, // The id of the availble mnxti interrupt + output logic [CLIC_ID_WIDTH-1:0] mnxti_irq_id_o, // The id of the availble mnxti interrupt output logic [7:0] mnxti_irq_level_o // Level of the available interrupt ); @@ -67,7 +67,7 @@ module cv32e40x_clic_int_controller import cv32e40x_pkg::*; // Flops for breaking timing path to instruction interface logic clic_irq_q; - logic [SMCLIC_ID_WIDTH-1:0] clic_irq_id_q; + logic [CLIC_ID_WIDTH-1:0] clic_irq_id_q; logic [7:0] clic_irq_level_q; logic clic_irq_shv_q; @@ -159,7 +159,7 @@ module cv32e40x_clic_int_controller import cv32e40x_pkg::*; // If mnxti_irq_pending is true, the currently flopped ID and level will be sent to cs_registers // for use in the function pointer and CSR side effects. - // Using native SMCLIC_ID_WIDTH for cleaner pointer concatenation in cs_registers. + // Using native CLIC_ID_WIDTH for cleaner pointer concatenation in cs_registers. assign mnxti_irq_id_o = clic_irq_id_q; assign mnxti_irq_level_o = clic_irq_level_q; diff --git a/rtl/cv32e40x_controller.sv b/rtl/cv32e40x_controller.sv index 7ede73a8..8c60e9fd 100644 --- a/rtl/cv32e40x_controller.sv +++ b/rtl/cv32e40x_controller.sv @@ -34,8 +34,8 @@ module cv32e40x_controller import cv32e40x_pkg::*; parameter bit X_EXT = 0, parameter a_ext_e A_EXT = A_NONE, parameter int unsigned REGFILE_NUM_READ_PORTS = 2, - parameter bit SMCLIC = 0, - parameter int SMCLIC_ID_WIDTH = 5, + parameter bit CLIC = 0, + parameter int CLIC_ID_WIDTH = 5, parameter int DEBUG = 1 ) ( @@ -147,8 +147,8 @@ module cv32e40x_controller import cv32e40x_pkg::*; cv32e40x_controller_fsm #( .X_EXT ( X_EXT ), - .SMCLIC ( SMCLIC ), - .SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ), + .CLIC ( CLIC ), + .CLIC_ID_WIDTH ( CLIC_ID_WIDTH ), .DEBUG ( DEBUG ) ) controller_fsm_i diff --git a/rtl/cv32e40x_controller_fsm.sv b/rtl/cv32e40x_controller_fsm.sv index 2c22c63d..1fbd9789 100644 --- a/rtl/cv32e40x_controller_fsm.sv +++ b/rtl/cv32e40x_controller_fsm.sv @@ -31,10 +31,10 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*; #( - parameter bit X_EXT = 0, - parameter int DEBUG = 1, - parameter bit SMCLIC = 0, - parameter int SMCLIC_ID_WIDTH = 5 + parameter bit X_EXT = 0, + parameter int DEBUG = 1, + parameter bit CLIC = 0, + parameter int CLIC_ID_WIDTH = 5 ) ( // Clocks and reset @@ -461,7 +461,7 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*; // Detect if there is a live CLIC pointer in the pipeline // This should block debug and interrupts generate - if (SMCLIC) begin : gen_clic_pointer_flag + if (CLIC) begin : gen_clic_pointer_flag // A CLIC pointer may be in the pipeline from the moment we start fetching (clic_ptr_in_progress_id == 1) // or while a pointer is in the EX or WB stages. assign clic_ptr_in_pipeline = (id_ex_pipe_i.instr_valid && id_ex_pipe_i.instr_meta.clic_ptr) || @@ -776,7 +776,7 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*; ctrl_fsm_o.csr_cause.minhv = mcause_i.minhv; - if (SMCLIC) begin + if (CLIC) begin ctrl_fsm_o.csr_cause.exception_code = {1'b0, irq_id_ctrl_i}; ctrl_fsm_o.irq_level = irq_clic_level_i; ctrl_fsm_o.irq_priv = irq_clic_priv_i; diff --git a/rtl/cv32e40x_core.sv b/rtl/cv32e40x_core.sv index cd7c7a04..c83ec8e2 100644 --- a/rtl/cv32e40x_core.sv +++ b/rtl/cv32e40x_core.sv @@ -42,9 +42,9 @@ module cv32e40x_core import cv32e40x_pkg::*; parameter int DBG_NUM_TRIGGERS = 1, parameter int PMA_NUM_REGIONS = 0, parameter pma_cfg_t PMA_CFG[PMA_NUM_REGIONS-1:0] = '{default:PMA_R_DEFAULT}, - parameter bit SMCLIC = 0, - parameter int SMCLIC_ID_WIDTH = 5, - parameter int SMCLIC_INTTHRESHBITS = 8, + parameter bit CLIC = 0, + parameter int CLIC_ID_WIDTH = 5, + parameter int CLIC_INTTHRESHBITS = 8, parameter bit X_EXT = 0, parameter int X_NUM_RS = 2, parameter int X_ID_WIDTH = 4, @@ -117,9 +117,9 @@ module cv32e40x_core import cv32e40x_pkg::*; input logic wu_wfe_i, // Wait-for-event wakeup input logic wu_wrs_i, // Wait-for-reservation-set wakeup - // Smclic interrupt architecture + // CLIC interrupt architecture input logic clic_irq_i, - input logic [SMCLIC_ID_WIDTH-1:0] clic_irq_id_i, + input logic [CLIC_ID_WIDTH-1:0] clic_irq_id_i, input logic [ 7:0] clic_irq_level_i, input logic [ 1:0] clic_irq_priv_i, input logic clic_irq_shv_i, @@ -151,7 +151,7 @@ module cv32e40x_core import cv32e40x_pkg::*; // Determine alignedness of mtvt // mtvt[31:N] holds mtvt table entry // mtvt[N-1:0] is tied to zero. - localparam int unsigned MTVT_LSB = ((SMCLIC_ID_WIDTH + 2) < 6) ? 6 : (SMCLIC_ID_WIDTH + 2); + localparam int unsigned MTVT_LSB = ((CLIC_ID_WIDTH + 2) < 6) ? 6 : (CLIC_ID_WIDTH + 2); localparam int unsigned MTVT_ADDR_WIDTH = 32 - MTVT_LSB; logic clk; // Gated clock @@ -339,15 +339,15 @@ module cv32e40x_core import cv32e40x_pkg::*; logic [7:0] irq_clic_level; logic [1:0] irq_clic_priv; logic mnxti_irq_pending; - logic [SMCLIC_ID_WIDTH-1:0] mnxti_irq_id; + logic [CLIC_ID_WIDTH-1:0] mnxti_irq_id; logic [7:0] mnxti_irq_level; // Used (only) by verification environment logic irq_ack; logic [9:0] irq_id; - logic [7:0] irq_level; // Only applicable if SMCLIC = 1 - logic [1:0] irq_priv; // Only applicable if SMCLIC = 1 - logic irq_shv; // Only applicable if SMCLIC = 1 + logic [7:0] irq_level; // Only applicable if CLIC = 1 + logic [1:0] irq_priv; // Only applicable if CLIC = 1 + logic irq_shv; // Only applicable if CLIC = 1 logic dbg_ack; // eXtension interface signals @@ -456,8 +456,8 @@ module cv32e40x_core import cv32e40x_pkg::*; .PMA_NUM_REGIONS ( PMA_NUM_REGIONS ), .PMA_CFG ( PMA_CFG ), .MTVT_ADDR_WIDTH ( MTVT_ADDR_WIDTH ), - .SMCLIC ( SMCLIC ), - .SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ), + .CLIC ( CLIC ), + .CLIC_ID_WIDTH ( CLIC_ID_WIDTH ), .ZC_EXT ( ZC_EXT ), .M_EXT ( M_EXT ), .DEBUG ( DEBUG ), @@ -523,7 +523,7 @@ module cv32e40x_core import cv32e40x_pkg::*; .M_EXT ( M_EXT ), .X_EXT ( X_EXT ), .REGFILE_NUM_READ_PORTS ( REGFILE_NUM_READ_PORTS ), - .SMCLIC ( SMCLIC ) + .CLIC ( CLIC ) ) id_stage_i ( @@ -794,9 +794,9 @@ module cv32e40x_core import cv32e40x_pkg::*; .X_MISA ( X_MISA ), .X_ECS_XS ( X_ECS_XS ), .ZC_EXT ( ZC_EXT ), - .SMCLIC ( SMCLIC ), - .SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ), - .SMCLIC_INTTHRESHBITS ( SMCLIC_INTTHRESHBITS ), + .CLIC ( CLIC ), + .CLIC_ID_WIDTH ( CLIC_ID_WIDTH ), + .CLIC_INTTHRESHBITS ( CLIC_INTTHRESHBITS ), .DEBUG ( DEBUG ), .DBG_NUM_TRIGGERS ( DBG_NUM_TRIGGERS ), .NUM_MHPMCOUNTERS ( NUM_MHPMCOUNTERS ), @@ -891,8 +891,8 @@ module cv32e40x_core import cv32e40x_pkg::*; .X_EXT ( X_EXT ), .A_EXT ( A_EXT ), .REGFILE_NUM_READ_PORTS ( REGFILE_NUM_READ_PORTS ), - .SMCLIC ( SMCLIC ), - .SMCLIC_ID_WIDTH ( SMCLIC_ID_WIDTH ), + .CLIC ( CLIC ), + .CLIC_ID_WIDTH ( CLIC_ID_WIDTH ), .DEBUG ( DEBUG ) ) controller_i @@ -1013,12 +1013,12 @@ module cv32e40x_core import cv32e40x_pkg::*; //////////////////////////////////////////////////////////////////////// generate - if (SMCLIC) begin : gen_clic_interrupt + if (CLIC) begin : gen_clic_interrupt assign mip = '0; cv32e40x_clic_int_controller #( - .SMCLIC_ID_WIDTH (SMCLIC_ID_WIDTH) + .CLIC_ID_WIDTH (CLIC_ID_WIDTH) ) clic_int_controller_i ( diff --git a/rtl/cv32e40x_cs_registers.sv b/rtl/cv32e40x_cs_registers.sv index 5b414532..3f49ea4d 100644 --- a/rtl/cv32e40x_cs_registers.sv +++ b/rtl/cv32e40x_cs_registers.sv @@ -36,9 +36,9 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; parameter logic [31:0] X_MISA = 32'h00000000, parameter logic [1:0] X_ECS_XS = 2'b00, // todo: implement related mstatus bitfields (but only if X_EXT = 1) parameter bit ZC_EXT = 0, - parameter bit SMCLIC = 0, - parameter int SMCLIC_ID_WIDTH = 5, - parameter int SMCLIC_INTTHRESHBITS = 8, + parameter bit CLIC = 0, + parameter int CLIC_ID_WIDTH = 5, + parameter int CLIC_INTTHRESHBITS = 8, parameter int NUM_MHPMCOUNTERS = 1, parameter int DEBUG = 1, parameter int DBG_NUM_TRIGGERS = 1, // todo: implement support for DBG_NUM_TRIGGERS != 1 @@ -93,7 +93,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; // Interrupts input logic [31:0] mip_i, input logic mnxti_irq_pending_i, - input logic [SMCLIC_ID_WIDTH-1:0] mnxti_irq_id_i, + input logic [CLIC_ID_WIDTH-1:0] mnxti_irq_id_i, input logic [7:0] mnxti_irq_level_i, output logic clic_pa_valid_o, // CSR read data is an address to a function pointer output logic [31:0] clic_pa_o, // Address to CLIC function pointer @@ -131,8 +131,8 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; localparam logic [31:0] MISA_VALUE = CORE_MISA | (X_EXT ? X_MISA : 32'h0000_0000); - // Set mask for minththresh based on number of bits implemented (SMCLIC_INTTHRESHBITS) - localparam CSR_MINTTHRESH_MASK = ((2 ** SMCLIC_INTTHRESHBITS )-1) << (8 - SMCLIC_INTTHRESHBITS); + // Set mask for minththresh based on number of bits implemented (CLIC_INTTHRESHBITS) + localparam CSR_MINTTHRESH_MASK = ((2 ** CLIC_INTTHRESHBITS )-1) << (8 - CLIC_INTTHRESHBITS); // CSR update logic logic [31:0] csr_wdata_int; @@ -366,7 +366,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; // mtvt: machine trap-handler vector table base address CSR_MTVT: begin - if (SMCLIC) begin + if (CLIC) begin csr_rdata_int = mtvt_rdata; end else begin csr_rdata_int = '0; @@ -406,7 +406,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; // mnxti: Next Interrupt Handler Address and Interrupt Enable CSR_MNXTI: begin - if (SMCLIC) begin + if (CLIC) begin // The data read here is what will be used in the read-modify-write portion of the CSR access. // For mnxti, this is actually mstatus. The value written back to the GPR will be the address of // the function pointer to the interrupt handler. This is muxed in the WB stage. @@ -420,7 +420,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; // mintstatus: Interrupt Status CSR_MINTSTATUS: begin - if (SMCLIC) begin + if (CLIC) begin csr_rdata_int = mintstatus_rdata; end else begin csr_rdata_int = '0; @@ -430,7 +430,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; // mintthresh: Interrupt-Level Threshold CSR_MINTTHRESH: begin - if (SMCLIC) begin + if (CLIC) begin csr_rdata_int = mintthresh_rdata; end else begin csr_rdata_int = '0; @@ -440,7 +440,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; // mscratchcsw: Scratch Swap for Multiple Privilege Modes CSR_MSCRATCHCSW: begin - if (SMCLIC) begin + if (CLIC) begin // CLIC spec 13.2 // Depending on mstatus.MPP, we return either mscratch_rdata or rs1 to rd. // Safe to use mstatus_rdata here (EX timing), as there is a generic stall of the ID stage @@ -461,7 +461,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; // mscratchcswl: Scratch Swap for Interrupt Levels CSR_MSCRATCHCSWL: begin - if (SMCLIC) begin + if (CLIC) begin // CLIC spec 14.1 // Depending on mcause.pil and mintstatus.mil, either mscratch or rs1 is returned to rd. // Safe to use mcause_rdata and mintstatus_rdata here (EX timing), as there is a generic stall of the ID stage @@ -729,7 +729,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; mtvec_n.submode = mtvec_rdata.submode; mtvec_we = csr_mtvec_init_i; - if (SMCLIC) begin + if (CLIC) begin mtvec_n.mode = mtvec_mode_clic_resolve(mtvec_rdata.mode, csr_wdata_int[MTVEC_MODE_BIT_HIGH:MTVEC_MODE_BIT_LOW]); // mode is WARL 0x3 when using CLIC mtvt_n = {csr_wdata_int[31:(32-MTVT_ADDR_WIDTH)], {(32-MTVT_ADDR_WIDTH){1'b0}}}; @@ -766,7 +766,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; }; mcause_we = 1'b0; mcause_alias_we = 1'b0; - end else begin // !SMCLIC + end else begin // !CLIC mtvec_n.mode = csr_mtvec_init_i ? mtvec_rdata.mode : mtvec_mode_clint_resolve(mtvec_rdata.mode, csr_wdata_int[MTVEC_MODE_BIT_HIGH:MTVEC_MODE_BIT_LOW]); mtvt_n = '0; @@ -833,10 +833,10 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; // mstatus CSR_MSTATUS: begin mstatus_we = 1'b1; - // CLIC mode is assumed when SMCLIC = 1 + // CLIC mode is assumed when CLIC = 1 // For CLIC, a write to mstatus.mpp or mstatus.mpie will write to the // corresponding bits in mstatus as well. - if (SMCLIC) begin + if (CLIC) begin mcause_alias_we = 1'b1; end end @@ -857,7 +857,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; // mtvt: machine trap-handler vector table base address CSR_MTVT: begin - if (SMCLIC) begin + if (CLIC) begin mtvt_we = 1'b1; end end @@ -879,10 +879,10 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; // mcause CSR_MCAUSE: begin mcause_we = 1'b1; - // CLIC mode is assumed when SMCLIC = 1 + // CLIC mode is assumed when CLIC = 1 // For CLIC, a write to mcause.mpp or mcause.mpie will write to the // corresponding bits in mstatus as well. - if (SMCLIC) begin + if (CLIC) begin mstatus_alias_we = 1'b1; end end @@ -897,7 +897,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; end CSR_MNXTI: begin - if (SMCLIC) begin + if (CLIC) begin mnxti_we = 1'b1; // Writes to mnxti also writes to mstatus (uses mstatus in the RMW operation) @@ -918,19 +918,19 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; end CSR_MINTSTATUS: begin - if (SMCLIC) begin + if (CLIC) begin mintstatus_we = 1'b1; end end CSR_MINTTHRESH: begin - if (SMCLIC) begin + if (CLIC) begin mintthresh_we = 1'b1; end end CSR_MSCRATCHCSW: begin - if (SMCLIC) begin + if (CLIC) begin // mscratchcsw operates on mscratch // Writing only when mstatus.mpp != PRIV_LVL_M if (mstatus_rdata.mpp != PRIV_LVL_M) begin @@ -941,7 +941,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; end CSR_MSCRATCHCSWL: begin - if (SMCLIC) begin + if (CLIC) begin // mscratchcswl operates on mscratch if ((mcause_rdata.mpil == '0) != (mintstatus_rdata.mil == '0)) begin mscratchcswl_we = 1'b1; @@ -1001,8 +1001,8 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; // CSR side effects from other CSRs - // CLIC mode is assumed when SMCLIC = 1 - if (SMCLIC) begin + // CLIC mode is assumed when CLIC = 1 + if (CLIC) begin if (mnxti_we) begin // Mstatus is written as part of an mnxti access // Make sure we alias the mpp/mpie to mcause @@ -1096,7 +1096,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; mcause_we = 1'b1; - if (SMCLIC) begin + if (CLIC) begin // mpil is saved from mintstatus mcause_n.mpil = mintstatus_rdata.mil; @@ -1135,7 +1135,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; mstatus_n.mpp = PRIV_LVL_LOWEST; mstatus_we = 1'b1; - if (SMCLIC) begin + if (CLIC) begin mintstatus_n.mil = mcause_rdata.mpil; mintstatus_we = 1'b1; @@ -1162,7 +1162,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; mstatus_n.mprv = (privlvl_t'(dcsr_rdata.prv) == PRIV_LVL_M) ? mstatus_rdata.mprv : 1'b0; mstatus_we = 1'b1; - if (SMCLIC) begin + if (CLIC) begin // Not really needed, but allows for asserting mstatus_we == mcause_we to check aliasing formally mcause_n = mcause_rdata; mcause_we = 1'b1; @@ -1175,7 +1175,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; // In the case of mret restarting CLIC pointer fetches, minhv is cleared while // ctrl_fsm_i.csr_restore_mret_ptr is asserted. ctrl_fsm_i.csr_clear_minhv: begin - if (SMCLIC) begin + if (CLIC) begin // Keep mcause values, only clear minhv bit. mcause_n = mcause_rdata; mcause_n.minhv = 1'b0; @@ -1346,9 +1346,9 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; generate - if (SMCLIC) begin : smclic_csrs + if (CLIC) begin : clic_csrs - assign mie_q = 32'h0; // CLIC mode is assumed when SMCLIC = 1 + assign mie_q = 32'h0; // CLIC mode is assumed when CLIC = 1 cv32e40x_csr #( @@ -1491,9 +1491,9 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; // Implemented threshold bits are left justified, unimplemented bits are tied to 1. // Special case when all 8 bits are implemented to avoid zero-replication generate - if (SMCLIC_INTTHRESHBITS < 8) begin : gen_partial_thresh + if (CLIC_INTTHRESHBITS < 8) begin : gen_partial_thresh // Unimplemented bits within [7:0] are tied to 1. Bits 31:8 always tied to 0. - assign mintthresh_rdata = {mintthresh_q[31:(7-(SMCLIC_INTTHRESHBITS-1))], {(8-SMCLIC_INTTHRESHBITS) {1'b1}}}; + assign mintthresh_rdata = {mintthresh_q[31:(7-(CLIC_INTTHRESHBITS-1))], {(8-CLIC_INTTHRESHBITS) {1'b1}}}; end else begin : gen_full_thresh // Bits 31:8 tied to 0, all bits within [7:0] are implemented in flipflops. assign mintthresh_rdata = mintthresh_q[31:0]; @@ -1550,7 +1550,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*; // Signal when an interrupt may become enabled due to a CSR write generate - if (SMCLIC) begin : smclic_irq_en + if (CLIC) begin : clic_irq_en assign csr_irq_enable_write_o = mstatus_we || priv_lvl_we || mintthresh_we || mintstatus_we; end else begin : basic_irq_en assign csr_irq_enable_write_o = mie_we || mstatus_we || priv_lvl_we; diff --git a/rtl/cv32e40x_decoder.sv b/rtl/cv32e40x_decoder.sv index a2a9f2aa..7ef07cfa 100644 --- a/rtl/cv32e40x_decoder.sv +++ b/rtl/cv32e40x_decoder.sv @@ -33,7 +33,7 @@ module cv32e40x_decoder import cv32e40x_pkg::*; parameter b_ext_e B_EXT = B_NONE, parameter m_ext_e M_EXT = M, parameter DEBUG_TRIGGER_EN = 1, - parameter bit SMCLIC = 1 + parameter bit CLIC = 1 ) ( // singals running to/from controller @@ -143,7 +143,7 @@ module cv32e40x_decoder import cv32e40x_pkg::*; cv32e40x_i_decoder #( .DEBUG_TRIGGER_EN (DEBUG_TRIGGER_EN), - .SMCLIC (SMCLIC ) + .CLIC (CLIC ) ) i_decoder_i ( diff --git a/rtl/cv32e40x_i_decoder.sv b/rtl/cv32e40x_i_decoder.sv index 4ad2f5b3..7ee5535b 100644 --- a/rtl/cv32e40x_i_decoder.sv +++ b/rtl/cv32e40x_i_decoder.sv @@ -30,7 +30,7 @@ module cv32e40x_i_decoder import cv32e40x_pkg::*; #( parameter DEBUG_TRIGGER_EN = 1, - parameter bit SMCLIC = 1 + parameter bit CLIC = 1 ) ( // from IF/ID pipeline @@ -369,7 +369,7 @@ module cv32e40x_i_decoder import cv32e40x_pkg::*; default: decoder_ctrl_o = DECODER_CTRL_ILLEGAL_INSN; endcase - if (SMCLIC) begin + if (CLIC) begin // The mscratchcsw[l] CSRs are only accessible using CSRRW with neither rd nor rs1 set to x0 if ((instr_rdata_i[31:20] == CSR_MSCRATCHCSW) || (instr_rdata_i[31:20] == CSR_MSCRATCHCSWL)) begin if (instr_rdata_i[14:12] == 3'b001) begin // CSRRW @@ -404,7 +404,7 @@ module cv32e40x_i_decoder import cv32e40x_pkg::*; end end end - end // SMCLIC + end // CLIC end end diff --git a/rtl/cv32e40x_id_stage.sv b/rtl/cv32e40x_id_stage.sv index 5b62475f..6acfdfe0 100644 --- a/rtl/cv32e40x_id_stage.sv +++ b/rtl/cv32e40x_id_stage.sv @@ -39,7 +39,7 @@ module cv32e40x_id_stage import cv32e40x_pkg::*; parameter bit X_EXT = 0, parameter DEBUG_TRIGGER_EN = 1, parameter int unsigned REGFILE_NUM_READ_PORTS = 2, - parameter bit SMCLIC = 1 + parameter bit CLIC = 1 ) ( input logic clk, // Gated clock @@ -423,7 +423,7 @@ module cv32e40x_id_stage import cv32e40x_pkg::*; .B_EXT ( B_EXT ), .M_EXT ( M_EXT ), .DEBUG_TRIGGER_EN ( DEBUG_TRIGGER_EN ), - .SMCLIC ( SMCLIC ) + .CLIC ( CLIC ) ) decoder_i ( diff --git a/rtl/cv32e40x_if_stage.sv b/rtl/cv32e40x_if_stage.sv index dc9fd81d..b894be14 100644 --- a/rtl/cv32e40x_if_stage.sv +++ b/rtl/cv32e40x_if_stage.sv @@ -36,8 +36,8 @@ module cv32e40x_if_stage import cv32e40x_pkg::*; parameter int PMA_NUM_REGIONS = 0, parameter pma_cfg_t PMA_CFG[PMA_NUM_REGIONS-1:0] = '{default:PMA_R_DEFAULT}, parameter int unsigned MTVT_ADDR_WIDTH = 26, - parameter bit SMCLIC = 1'b0, - parameter int SMCLIC_ID_WIDTH = 5, + parameter bit CLIC = 1'b0, + parameter int CLIC_ID_WIDTH = 5, parameter bit ZC_EXT = 0, parameter m_ext_e M_EXT = M_NONE, parameter int DEBUG = 1, @@ -167,7 +167,7 @@ module cv32e40x_if_stage import cv32e40x_pkg::*; PC_TRAP_DBD: branch_addr_n = {dm_halt_addr_i[31:2], 2'b0}; PC_TRAP_DBE: branch_addr_n = {dm_exception_addr_i[31:2], 2'b0}; PC_TRAP_NMI: branch_addr_n = {mtvec_addr_i, ctrl_fsm_i.nmi_mtvec_index, 2'b00}; - PC_TRAP_CLICV: branch_addr_n = {mtvt_addr_i, ctrl_fsm_i.mtvt_pc_mux[SMCLIC_ID_WIDTH-1:0], 2'b00}; + PC_TRAP_CLICV: branch_addr_n = {mtvt_addr_i, ctrl_fsm_i.mtvt_pc_mux[CLIC_ID_WIDTH-1:0], 2'b00}; // CLIC and Zc* spec requires to clear bit 0. This clearing is done in the alignment buffer. PC_POINTER : branch_addr_n = if_id_pipe_o.ptr; // JVT + (index << 2) @@ -183,7 +183,7 @@ module cv32e40x_if_stage import cv32e40x_pkg::*; // prefetch buffer, caches a fixed number of instructions cv32e40x_prefetch_unit #( - .SMCLIC (SMCLIC), + .CLIC (CLIC), .ALBUF_DEPTH (ALBUF_DEPTH), .ALBUF_CNT_WIDTH (ALBUF_CNT_WIDTH) ) diff --git a/rtl/cv32e40x_prefetch_unit.sv b/rtl/cv32e40x_prefetch_unit.sv index 939f09db..ec48ea3d 100644 --- a/rtl/cv32e40x_prefetch_unit.sv +++ b/rtl/cv32e40x_prefetch_unit.sv @@ -28,7 +28,7 @@ module cv32e40x_prefetch_unit import cv32e40x_pkg::*; #( - parameter bit SMCLIC = 1'b0, + parameter bit CLIC = 1'b0, parameter int unsigned ALBUF_DEPTH = 3, parameter int unsigned ALBUF_CNT_WIDTH = $clog2(ALBUF_DEPTH) ) @@ -82,7 +82,7 @@ module cv32e40x_prefetch_unit import cv32e40x_pkg::*; cv32e40x_prefetcher #( - .SMCLIC (SMCLIC) + .CLIC (CLIC) ) prefetcher_i ( diff --git a/rtl/cv32e40x_prefetcher.sv b/rtl/cv32e40x_prefetcher.sv index c2ad1b4e..c2c80516 100644 --- a/rtl/cv32e40x_prefetcher.sv +++ b/rtl/cv32e40x_prefetcher.sv @@ -39,7 +39,7 @@ module cv32e40x_prefetcher import cv32e40x_pkg::*; #( - parameter bit SMCLIC = 1'b0 + parameter bit CLIC = 1'b0 ) ( input logic clk, diff --git a/sva/cv32e40x_controller_fsm_sva.sv b/sva/cv32e40x_controller_fsm_sva.sv index 2d8c94e8..a51df250 100644 --- a/sva/cv32e40x_controller_fsm_sva.sv +++ b/sva/cv32e40x_controller_fsm_sva.sv @@ -30,7 +30,7 @@ module cv32e40x_controller_fsm_sva import cv32e40x_pkg::*; #( parameter bit X_EXT = 1'b0, parameter int DEBUG = 0, - parameter bit SMCLIC = 1'b0 + parameter bit CLIC = 1'b0 ) ( input logic clk, @@ -594,7 +594,7 @@ endgenerate (valid_cnt < (retire_at_error ? 2'b10 : 2'b11))) else `uvm_error("controller", "NMI handler not taken within two instruction retirements") -if (SMCLIC) begin +if (CLIC) begin // After a pc_set to PC_TRAP_CLICV, only the following jump targets are allowed: // PC_POINTER : Normal execution, the pointer target is being fetched @@ -624,7 +624,7 @@ if (SMCLIC) begin !ctrl_fsm_o.kill_id) else `uvm_error("controller", "ID stage killed while clic_ptr_in_progress_id is high") -end else begin // SMCLIC +end else begin // CLIC // Check that CLIC related signals are inactive when CLIC is not configured. a_clic_inactive: assert property (@(posedge clk) disable iff (!rst_n) diff --git a/sva/cv32e40x_core_sva.sv b/sva/cv32e40x_core_sva.sv index 67e4d3b7..f6d8952d 100644 --- a/sva/cv32e40x_core_sva.sv +++ b/sva/cv32e40x_core_sva.sv @@ -29,7 +29,7 @@ module cv32e40x_core_sva parameter a_ext_e A_EXT = A_NONE, parameter int DEBUG = 1, parameter int PMA_NUM_REGIONS = 0, - parameter bit SMCLIC = 0 + parameter bit CLIC = 0 ) ( input logic clk, @@ -112,7 +112,7 @@ module cv32e40x_core_sva input mcause_t cs_registers_mcause_q, // From cs_registers, flopped mcause input mstatus_t cs_registers_mstatus_q); -if (SMCLIC) begin +if (CLIC) begin property p_clic_mie_tieoff; @(posedge clk) |mie == 1'b0; @@ -127,7 +127,7 @@ if (SMCLIC) begin //todo: add CLIC related assertions (level thresholds etc) end else begin - // SMCLIC == 0 + // CLIC == 0 // Check that a taken IRQ is actually enabled (e.g. that we do not react to an IRQ that was just disabled in MIE) // The actual mie_n value may be different from mie_q if mie is not // written to. @@ -148,7 +148,7 @@ end else begin a_irq_enabled_1 : assert property(p_irq_enabled_1) else `uvm_error("core", "Assertion a_irq_enabled_1 failed") - // Assert that no pointer can be in any pipeline stage when SMCLIC == 0 + // Assert that no pointer can be in any pipeline stage when CLIC == 0 property p_clic_noptr_in_pipeline; @(posedge clk) disable iff (!rst_ni) 1'b1 @@ -158,7 +158,7 @@ end else begin endproperty a_clic_noptr_in_pipeline : assert property(p_clic_noptr_in_pipeline) else `uvm_error("core", "CLIC pointer in pipeline when CLIC is not configured.") -end // SMCLIC +end // CLIC // First illegal instruction decoded logic first_illegal_found; @@ -353,7 +353,7 @@ always_ff @(posedge clk , negedge rst_ni) end -if (SMCLIC) begin +if (CLIC) begin if (DEBUG) begin // Non-SHV interrupt taken during single stepping. // If this happens, no instructions should retire until the core is in debug mode. @@ -601,7 +601,7 @@ end a_tbljmp_stall: assert property(p_tbljmp_stall) else `uvm_error("core", "Table jump not stalled while CSR is written"); -if (!SMCLIC) begin +if (!CLIC) begin // Check that a pending interrupt is taken as soon as possible after being enabled property p_mip_mie_write_enable; @(posedge clk) disable iff (!rst_ni) diff --git a/sva/cv32e40x_cs_registers_sva.sv b/sva/cv32e40x_cs_registers_sva.sv index 9a90ea07..e77b9230 100644 --- a/sva/cv32e40x_cs_registers_sva.sv +++ b/sva/cv32e40x_cs_registers_sva.sv @@ -26,8 +26,8 @@ module cv32e40x_cs_registers_sva import uvm_pkg::*; import cv32e40x_pkg::*; #( - parameter bit SMCLIC = 0, - parameter int DEBUG = 1 + parameter bit CLIC = 0, + parameter int DEBUG = 1 ) ( @@ -86,7 +86,7 @@ module cv32e40x_cs_registers_sva |-> !csr_we_int) else `uvm_error("wb_stage", "Register file written while WB is halted or killed") - if (SMCLIC) begin + if (CLIC) begin // Assert that mtvec[1:0] are always 2'b11 a_mtvec_mode_clic: assert property (@(posedge clk) disable iff (!rst_n) diff --git a/sva/cv32e40x_prefetch_unit_sva.sv b/sva/cv32e40x_prefetch_unit_sva.sv index fb0850af..51e1edef 100644 --- a/sva/cv32e40x_prefetch_unit_sva.sv +++ b/sva/cv32e40x_prefetch_unit_sva.sv @@ -21,7 +21,7 @@ module cv32e40x_prefetch_unit_sva import cv32e40x_pkg::*; import uvm_pkg::*; #( - parameter SMCLIC = 1'b0 + parameter CLIC = 1'b0 ) ( input logic clk, @@ -58,7 +58,7 @@ module cv32e40x_prefetch_unit_sva import cv32e40x_pkg::*; a_branch_implies_req : assert property(p_branch_implies_req) else `uvm_error("prefetch_buffer", "Assertion a_branch_implies_req failed") -if (SMCLIC) begin +if (CLIC) begin // Shall not fetch anything between pointer fetch and the actual instruction fetch // based on the pointer. property p_single_ptr_fetch; @@ -70,7 +70,7 @@ if (SMCLIC) begin assert property(p_single_ptr_fetch) else `uvm_error("Alignment buffer SVA", "Multiple fetches for CLIC/Zc pointer") -end // SMCLIC +end // CLIC endmodule // cv32e40x_prefetch_unit diff --git a/sva/cv32e40x_prefetcher_sva.sv b/sva/cv32e40x_prefetcher_sva.sv index caf5e1f7..aa4f46c1 100644 --- a/sva/cv32e40x_prefetcher_sva.sv +++ b/sva/cv32e40x_prefetcher_sva.sv @@ -29,7 +29,7 @@ module cv32e40x_prefetcher_sva import cv32e40x_pkg::*; #( - parameter bit SMCLIC = 1'b0 + parameter bit CLIC = 1'b0 ) ( input logic clk, @@ -172,7 +172,7 @@ module cv32e40x_prefetcher_sva import cv32e40x_pkg::*; `uvm_error("Prefetcher SVA", $sformatf("First fetch after reset is not a branch")) -if (SMCLIC) begin +if (CLIC) begin // We cannot have a new fetch_branch when a CLIC pointer fetch is outstanding. If that happens, the core will lose track of // which which address to return to (mepc, dpc) as the pointer is not associated with an actual instruction. // For Zc pointer fetches, we can allow this (for instance debug entry or exception while the pointer is outstanding). @@ -186,5 +186,5 @@ if (SMCLIC) begin assert property(p_data_q_no_branch) else `uvm_error("Prefetcher SVA", "data_q is set on branch.") -end // SMCLIC +end // CLIC endmodule: cv32e40x_prefetcher_sva diff --git a/sva/cv32e40x_rvfi_sva.sv b/sva/cv32e40x_rvfi_sva.sv index b7783959..f4e9abd0 100644 --- a/sva/cv32e40x_rvfi_sva.sv +++ b/sva/cv32e40x_rvfi_sva.sv @@ -28,9 +28,9 @@ module cv32e40x_rvfi_sva import cv32e40x_pkg::*; import cv32e40x_rvfi_pkg::*; #( - parameter bit SMCLIC = 0, - parameter int DEBUG = 1, - parameter a_ext_e A_EXT = A_NONE + parameter bit CLIC = 0, + parameter int DEBUG = 1, + parameter a_ext_e A_EXT = A_NONE ) ( input logic clk_i, diff --git a/yaml/csr.yaml.m4 b/yaml/csr.yaml.m4 index 54ba810f..c5402df2 100644 --- a/yaml/csr.yaml.m4 +++ b/yaml/csr.yaml.m4 @@ -3141,7 +3141,7 @@ ifelse(eval(CLIC != 0), 1, [[[ rv32: - field_name: BASE_31_N description: > - Trap-handler vector base address. Alignment depends on SMCLIC_ID_WIDTH parameter. + Trap-handler vector base address. Alignment depends on CLIC_ID_WIDTH parameter. type: WARL reset_val: 0 msb: 31