Which FPGA ?

[SoCScholar]

Hi,

Which FPGA do you suggest for running CV 32 E 40 X ? While compiling with genesys 2 (XC7K325T-2FFG900C), it says area over utilization. The design contain 724 I/0 Ports but my fpga only has 500 Usable I/O Port.

After running implementation

After running synthesis

[Silabs-ArjanB]

We have no FPGA recommendations. You could reduce the pressure on FPGA port usage by connecting many of the CV32E40X ports to buses, memories, etc. that you model inside the FPGA (instead of outside). You would have to provide such system level components yourself.

[SoCScholar]

I try it as mentioned here

https://docs.openhwgroup.org/projects/cv32e40x-user-manual/en/latest/intro.html#synthesis-guidelines

https://docs.openhwgroup.org/projects/cv32e40x-user-manual/en/latest/getting_started.html#clock-gating-cell

i get this result unfortunately.

cv32e40x_core_drc_opted.zip

cv32e40x_core_utilization_synthesis.zip