From 7c23d9e85ef328081f7d9836ebfffda755f4b496 Mon Sep 17 00:00:00 2001
From: "Chereshnev, Eugene" <eugene.chereshnev@intel.com>
Date: Fri, 14 Apr 2023 13:12:34 -0700
Subject: [PATCH] gpu: jit: codegen: handle 64-bit reg/imm addition

---
 src/gpu/jit/codegen/kernel.hpp | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/gpu/jit/codegen/kernel.hpp b/src/gpu/jit/codegen/kernel.hpp
index 8de1ad35f07..2fba20db907 100644
--- a/src/gpu/jit/codegen/kernel.hpp
+++ b/src/gpu/jit/codegen/kernel.hpp
@@ -390,7 +390,14 @@ class ir_kernel_t : public jit_generator<hw> {
         if (src1.is_reg_data()) {
             eadd(mod, dst.reg_data(), src0.reg_data(), src1.reg_data());
         } else {
-            eadd(mod, dst.reg_data(), src0.reg_data(), src1.immediate());
+            if (ngen_is_qw(src1.type())) {
+                auto tmp = ra_.alloc_sub(src1.type());
+                emov(1, tmp, src1.immediate());
+                eadd(mod, dst.reg_data(), src0.reg_data(), tmp);
+                ra_.safeRelease(tmp);
+            } else {
+                eadd(mod, dst.reg_data(), src0.reg_data(), src1.immediate());
+            }
         }
     }