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[SYCLomatic] Update intrinsic and mnemonics names (#2677)
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Signed-off-by: chenwei.sun <[email protected]>
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@tomflinda
tomflinda authored Feb 24, 2025
1 parent 592cfa3 commit 87a5336
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Showing 62 changed files with 12,236 additions and 12,248 deletions.
114 changes: 57 additions & 57 deletions clang/include/clang/Basic/BuiltinsX86.def
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Original file line number Diff line number Diff line change
Expand Up @@ -2180,9 +2180,9 @@ TARGET_BUILTIN(__builtin_ia32_vsm4rnds4128, "V4UiV4UiV4Ui", "nV:128:", "sm4")
TARGET_BUILTIN(__builtin_ia32_vsm4rnds4256, "V8UiV8UiV8Ui", "nV:256:", "sm4")

// AVX10 MINMAX
TARGET_BUILTIN(__builtin_ia32_vminmaxnepbf16128, "V8yV8yV8yIi", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vminmaxnepbf16256, "V16yV16yV16yIi", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vminmaxnepbf16512, "V32yV32yV32yIi", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vminmaxbf16128, "V8yV8yV8yIi", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vminmaxbf16256, "V16yV16yV16yIi", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vminmaxbf16512, "V32yV32yV32yIi", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vminmaxpd128_mask, "V2dV2dV2dIiV2dUc", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vminmaxpd256_round_mask, "V4dV4dV4dIiV4dUcIi", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vminmaxpd512_round_mask, "V8dV8dV8dIiV8dUcIi", "nV:512:", "avx10.2-512")
Expand All @@ -2197,12 +2197,12 @@ TARGET_BUILTIN(__builtin_ia32_vminmaxsh_round_mask, "V8xV8xV8xIiV8xUcIi", "nV:12
TARGET_BUILTIN(__builtin_ia32_vminmaxss_round_mask, "V4fV4fV4fIiV4fUcIi", "nV:128:", "avx10.2-256")

// AVX10.2 SATCVT
TARGET_BUILTIN(__builtin_ia32_vcvtnebf162ibs128, "V8UsV8y", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtnebf162ibs256, "V16UsV16y", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtnebf162ibs512, "V32UsV32y", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvtnebf162iubs128, "V8UsV8y", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtnebf162iubs256, "V16UsV16y", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtnebf162iubs512, "V32UsV32y", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvtbf162ibs128, "V8UsV8y", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtbf162ibs256, "V16UsV16y", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtbf162ibs512, "V32UsV32y", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvtbf162iubs128, "V8UsV8y", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtbf162iubs256, "V16UsV16y", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtbf162iubs512, "V32UsV32y", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvtph2ibs128_mask, "V8UsV8xV8UsUc", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtph2ibs256_mask, "V16UsV16xV16UsUsIi", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtph2ibs512_mask, "V32UsV32xV32UsUiIi", "nV:512:", "avx10.2-512")
Expand Down Expand Up @@ -2250,52 +2250,52 @@ TARGET_BUILTIN(__builtin_ia32_vcvtbiasph2hf8_512_mask, "V32cV64cV32xV32cUi", "nV
TARGET_BUILTIN(__builtin_ia32_vcvtbiasph2hf8s_128_mask, "V16cV16cV8xV16cUc", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtbiasph2hf8s_256_mask, "V16cV32cV16xV16cUs", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtbiasph2hf8s_512_mask, "V32cV64cV32xV32cUi", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvtne2ph2bf8_128, "V16cV8xV8x", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtne2ph2bf8_256, "V32cV16xV16x", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtne2ph2bf8_512, "V64cV32xV32x", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvtne2ph2bf8s_128, "V16cV8xV8x", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtne2ph2bf8s_256, "V32cV16xV16x", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtne2ph2bf8s_512, "V64cV32xV32x", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvtne2ph2hf8_128, "V16cV8xV8x", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtne2ph2hf8_256, "V32cV16xV16x", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtne2ph2hf8_512, "V64cV32xV32x", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvt2ph2bf8_128, "V16cV8xV8x", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvt2ph2bf8_256, "V32cV16xV16x", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvt2ph2bf8_512, "V64cV32xV32x", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvt2ph2bf8s_128, "V16cV8xV8x", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvt2ph2bf8s_256, "V32cV16xV16x", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvt2ph2bf8s_512, "V64cV32xV32x", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvt2ph2hf8_128, "V16cV8xV8x", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvt2ph2hf8_256, "V32cV16xV16x", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvt2ph2hf8_512, "V64cV32xV32x", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvt2ph2hf8s_128, "V16cV8xV8x", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvt2ph2hf8s_256, "V32cV16xV16x", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvt2ph2hf8s_512, "V64cV32xV32x", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvthf8_2ph128_mask, "V8xV16cV8xUc", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvthf8_2ph256_mask, "V16xV16cV16xUs", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvthf8_2ph512_mask, "V32xV32cV32xUi", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvtneph2bf8_128_mask, "V16cV8xV16cUc", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtneph2bf8_256_mask, "V16cV16xV16cUs", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtneph2bf8_512_mask, "V32cV32xV32cUi", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvtneph2bf8s_128_mask, "V16cV8xV16cUc", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtneph2bf8s_256_mask, "V16cV16xV16cUs", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtneph2bf8s_512_mask, "V32cV32xV32cUi", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvtneph2hf8_128_mask, "V16cV8xV16cUc", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtneph2hf8_256_mask, "V16cV16xV16cUs", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtneph2hf8_512_mask, "V32cV32xV32cUi", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvtneph2hf8s_128_mask, "V16cV8xV16cUc", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtneph2hf8s_256_mask, "V16cV16xV16cUs", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtneph2hf8s_512_mask, "V32cV32xV32cUi", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvtph2bf8512_128_mask, "V16cV8xV16cUc", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtph2bf8512_256_mask, "V16cV16xV16cUs", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtph2bf8512_512_mask, "V32cV32xV32cUi", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvtph2bf8512s_128_mask, "V16cV8xV16cUc", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtph2bf8512s_256_mask, "V16cV16xV16cUs", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtph2bf8512s_512_mask, "V32cV32xV32cUi", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvtph2hf8_128_mask, "V16cV8xV16cUc", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtph2hf8_256_mask, "V16cV16xV16cUs", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtph2hf8_512_mask, "V32cV32xV32cUi", "nV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vcvtph2hf8s_128_mask, "V16cV8xV16cUc", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtph2hf8s_256_mask, "V16cV16xV16cUs", "nV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vcvtph2hf8s_512_mask, "V32cV32xV32cUi", "nV:512:", "avx10.2-512")

// AVX10.2 BF16
TARGET_BUILTIN(__builtin_ia32_loadsbf16128_mask, "V8yV8yC*V8yUc", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_storesbf16128_mask, "vV8y*V8yUc", "nV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vaddnepbf16128, "V8yV8yV8y", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vaddnepbf16256, "V16yV16yV16y", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vaddnepbf16512, "V32yV32yV32y", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vdivnepbf16128, "V8yV8yV8y", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vdivnepbf16256, "V16yV16yV16y", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vdivnepbf16512, "V32yV32yV32y", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vmaxpbf16128, "V8yV8yV8y", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vmaxpbf16256, "V16yV16yV16y", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vmaxpbf16512, "V32yV32yV32y", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vminpbf16128, "V8yV8yV8y", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vminpbf16256, "V16yV16yV16y", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vminpbf16512, "V32yV32yV32y", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vmulnepbf16128, "V8yV8yV8y", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vmulnepbf16256, "V16yV16yV16y", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vmulnepbf16512, "V32yV32yV32y", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vaddbf16128, "V8yV8yV8y", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vaddbf16256, "V16yV16yV16y", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vaddbf16512, "V32yV32yV32y", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vdivbf16128, "V8yV8yV8y", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vdivbf16256, "V16yV16yV16y", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vdivbf16512, "V32yV32yV32y", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vmaxbf16128, "V8yV8yV8y", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vmaxbf16256, "V16yV16yV16y", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vmaxbf16512, "V32yV32yV32y", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vminbf16128, "V8yV8yV8y", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vminbf16256, "V16yV16yV16y", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vminbf16512, "V32yV32yV32y", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vmulbf16128, "V8yV8yV8y", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vmulbf16256, "V16yV16yV16y", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vmulbf16512, "V32yV32yV32y", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vsubbf16128, "V8yV8yV8y", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vsubbf16256, "V16yV16yV16y", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vsubbf16512, "V32yV32yV32y", "ncV:512:", "avx10.2-512")
Expand All @@ -2314,12 +2314,12 @@ TARGET_BUILTIN(__builtin_ia32_vfpclassbf16512_mask, "UiV32yIiUi", "ncV:512:", "a
TARGET_BUILTIN(__builtin_ia32_vscalefpbf16128_mask, "V8yV8yV8yV8yUc", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vscalefpbf16256_mask, "V16yV16yV16yV16yUs", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vscalefpbf16512_mask, "V32yV32yV32yV32yUi", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vrcppbf16128_mask, "V8yV8yV8yUc", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vrcppbf16256_mask, "V16yV16yV16yUs", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vrcppbf16512_mask, "V32yV32yV32yUi", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vgetexppbf16128_mask, "V8yV8yV8yUc", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vgetexppbf16256_mask, "V16yV16yV16yUs", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vgetexppbf16512_mask, "V32yV32yV32yUi", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vrcpbf16128_mask, "V8yV8yV8yUc", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vrcpbf16256_mask, "V16yV16yV16yUs", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vrcpbf16512_mask, "V32yV32yV32yUi", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vgetexpbf16128_mask, "V8yV8yV8yUc", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vgetexpbf16256_mask, "V16yV16yV16yUs", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vgetexpbf16512_mask, "V32yV32yV32yUi", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vrsqrtbf16128_mask, "V8yV8yV8yUc", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vrsqrtbf16256_mask, "V16yV16yV16yUs", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vrsqrtbf16512_mask, "V32yV32yV32yUi", "ncV:512:", "avx10.2-512")
Expand All @@ -2329,12 +2329,12 @@ TARGET_BUILTIN(__builtin_ia32_vreducebf16512_mask, "V32yV32yIiV32yUi", "ncV:512:
TARGET_BUILTIN(__builtin_ia32_vrndscalebf16_128_mask, "V8yV8yIiV8yUc", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vrndscalebf16_256_mask, "V16yV16yIiV16yUs", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vrndscalebf16_mask, "V32yV32yIiV32yUi", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vgetmantpbf16128_mask, "V8yV8yIiV8yUc", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vgetmantpbf16256_mask, "V16yV16yIiV16yUs", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vgetmantpbf16512_mask, "V32yV32yIiV32yUi", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vsqrtnepbf16, "V8yV8y", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vsqrtnepbf16256, "V16yV16y", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vsqrtnepbf16512, "V32yV32y", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vgetmantbf16128_mask, "V8yV8yIiV8yUc", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vgetmantbf16256_mask, "V16yV16yIiV16yUs", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vgetmantbf16512_mask, "V32yV32yIiV32yUi", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vsqrtbf16, "V8yV8y", "ncV:128:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vsqrtbf16256, "V16yV16y", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vsqrtbf16512, "V32yV32y", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vfmaddnepbh512, "V32yV32yV32yV32y", "ncV:512:", "avx10.2-512")
TARGET_BUILTIN(__builtin_ia32_vfmaddnepbh256, "V16yV16yV16yV16y", "ncV:256:", "avx10.2-256")
TARGET_BUILTIN(__builtin_ia32_vfmaddnepbh128, "V8yV8yV8yV8y", "ncV:128:", "avx10.2-256")
Expand Down
12 changes: 6 additions & 6 deletions clang/lib/CodeGen/CGBuiltin.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16300,9 +16300,9 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
case X86::BI__builtin_ia32_sqrtph256:
case X86::BI__builtin_ia32_sqrtph:
case X86::BI__builtin_ia32_sqrtph512:
case X86::BI__builtin_ia32_vsqrtnepbf16256:
case X86::BI__builtin_ia32_vsqrtnepbf16:
case X86::BI__builtin_ia32_vsqrtnepbf16512:
case X86::BI__builtin_ia32_vsqrtbf16256:
case X86::BI__builtin_ia32_vsqrtbf16:
case X86::BI__builtin_ia32_vsqrtbf16512:
case X86::BI__builtin_ia32_sqrtps512:
case X86::BI__builtin_ia32_sqrtpd512: {
if (Ops.size() == 2) {
Expand Down Expand Up @@ -16540,13 +16540,13 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
switch (BuiltinID) {
default: llvm_unreachable("Unsupported intrinsic!");
case X86::BI__builtin_ia32_vfpclassbf16128_mask:
ID = Intrinsic::x86_avx10_fpclass_nepbf16_128;
ID = Intrinsic::x86_avx10_fpclass_bf16_128;
break;
case X86::BI__builtin_ia32_vfpclassbf16256_mask:
ID = Intrinsic::x86_avx10_fpclass_nepbf16_256;
ID = Intrinsic::x86_avx10_fpclass_bf16_256;
break;
case X86::BI__builtin_ia32_vfpclassbf16512_mask:
ID = Intrinsic::x86_avx10_fpclass_nepbf16_512;
ID = Intrinsic::x86_avx10_fpclass_bf16_512;
break;
case X86::BI__builtin_ia32_fpclassph128_mask:
ID = Intrinsic::x86_avx512fp16_fpclass_ph_128;
Expand Down
24 changes: 12 additions & 12 deletions clang/lib/Headers/avx10_2_512bf16intrin.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -252,7 +252,7 @@ _mm512_maskz_divne_pbh(__mmask32 __U, __m512bh __A, __m512bh __B) {

static __inline__ __m512bh __DEFAULT_FN_ATTRS512 _mm512_max_pbh(__m512bh __A,
__m512bh __B) {
return (__m512bh)__builtin_ia32_vmaxpbf16512((__v32bf)__A, (__v32bf)__B);
return (__m512bh)__builtin_ia32_vmaxbf16512((__v32bf)__A, (__v32bf)__B);
}

static __inline__ __m512bh __DEFAULT_FN_ATTRS512
Expand All @@ -270,7 +270,7 @@ _mm512_maskz_max_pbh(__mmask32 __U, __m512bh __A, __m512bh __B) {

static __inline__ __m512bh __DEFAULT_FN_ATTRS512 _mm512_min_pbh(__m512bh __A,
__m512bh __B) {
return (__m512bh)__builtin_ia32_vminpbf16512((__v32bf)__A, (__v32bf)__B);
return (__m512bh)__builtin_ia32_vminbf16512((__v32bf)__A, (__v32bf)__B);
}

static __inline__ __m512bh __DEFAULT_FN_ATTRS512
Expand Down Expand Up @@ -325,37 +325,37 @@ _mm512_maskz_scalef_pbh(__mmask32 __U, __m512bh __A, __m512bh __B) {
}

static __inline__ __m512bh __DEFAULT_FN_ATTRS512 _mm512_rcp_pbh(__m512bh __A) {
return (__m512bh)__builtin_ia32_vrcppbf16512_mask(
return (__m512bh)__builtin_ia32_vrcpbf16512_mask(
(__v32bf)__A, (__v32bf)_mm512_undefined_pbh(), (__mmask32)-1);
}

static __inline__ __m512bh __DEFAULT_FN_ATTRS512
_mm512_mask_rcp_pbh(__m512bh __W, __mmask32 __U, __m512bh __A) {
return (__m512bh)__builtin_ia32_vrcppbf16512_mask((__v32bf)__A, (__v32bf)__W,
return (__m512bh)__builtin_ia32_vrcpbf16512_mask((__v32bf)__A, (__v32bf)__W,
(__mmask32)__U);
}

static __inline__ __m512bh __DEFAULT_FN_ATTRS512
_mm512_maskz_rcp_pbh(__mmask32 __U, __m512bh __A) {
return (__m512bh)__builtin_ia32_vrcppbf16512_mask(
return (__m512bh)__builtin_ia32_vrcpbf16512_mask(
(__v32bf)__A, (__v32bf)_mm512_setzero_pbh(), (__mmask32)__U);
}

static __inline__ __m512bh __DEFAULT_FN_ATTRS512
_mm512_getexp_pbh(__m512bh __A) {
return (__m512bh)__builtin_ia32_vgetexppbf16512_mask(
return (__m512bh)__builtin_ia32_vgetexpbf16512_mask(
(__v32bf)__A, (__v32bf)_mm512_undefined_pbh(), (__mmask32)-1);
}

static __inline__ __m512bh __DEFAULT_FN_ATTRS512
_mm512_mask_getexp_pbh(__m512bh __W, __mmask32 __U, __m512bh __A) {
return (__m512bh)__builtin_ia32_vgetexppbf16512_mask(
return (__m512bh)__builtin_ia32_vgetexpbf16512_mask(
(__v32bf)__A, (__v32bf)__W, (__mmask32)__U);
}

static __inline__ __m512bh __DEFAULT_FN_ATTRS512
_mm512_maskz_getexp_pbh(__mmask32 __U, __m512bh __A) {
return (__m512bh)__builtin_ia32_vgetexppbf16512_mask(
return (__m512bh)__builtin_ia32_vgetexpbf16512_mask(
(__v32bf)__A, (__v32bf)_mm512_setzero_pbh(), (__mmask32)__U);
}

Expand Down Expand Up @@ -408,22 +408,22 @@ _mm512_maskz_rsqrt_pbh(__mmask32 __U, __m512bh __A) {
(__mmask32)(__U)))

#define _mm512_getmant_pbh(__A, __B, __C) \
((__m512bh)__builtin_ia32_vgetmantpbf16512_mask( \
((__m512bh)__builtin_ia32_vgetmantbf16512_mask( \
(__v32bf)(__m512bh)(__A), (int)(((__C) << 2) | (__B)), \
(__v32bf)_mm512_undefined_pbh(), (__mmask32) - 1))

#define _mm512_mask_getmant_pbh(__W, __U, __A, __B, __C) \
((__m512bh)__builtin_ia32_vgetmantpbf16512_mask( \
((__m512bh)__builtin_ia32_vgetmantbf16512_mask( \
(__v32bf)(__m512bh)(__A), (int)(((__C) << 2) | (__B)), \
(__v32bf)(__m512bh)(__W), (__mmask32)(__U)))

#define _mm512_maskz_getmant_pbh(__U, __A, __B, __C) \
((__m512bh)__builtin_ia32_vgetmantpbf16512_mask( \
((__m512bh)__builtin_ia32_vgetmantbf16512_mask( \
(__v32bf)(__m512bh)(__A), (int)(((__C) << 2) | (__B)), \
(__v32bf)_mm512_setzero_pbh(), (__mmask32)(__U)))

static __inline__ __m512bh __DEFAULT_FN_ATTRS512 _mm512_sqrt_pbh(__m512bh __A) {
return (__m512bh)__builtin_ia32_vsqrtnepbf16512((__v32bf)__A);
return (__m512bh)__builtin_ia32_vsqrtbf16512((__v32bf)__A);
}

static __inline__ __m512bh __DEFAULT_FN_ATTRS512
Expand Down
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