Read Data Channel should not require 2 cycles of Rvalid

[e19293001]

I created a testbench for the mriscvcore to verify the RTL code on my
own. During my setup of the testbench, I noticed RReady requires two
cycles. This is unusual since RReady had already gone low after the
first cycle of Rvalid.

Here's a snapshot when Rvalid is turned high on a single cycle:

image1

Notice that AWdata throws an 'x value which seems to be a bug to the
internal circuit of mriscvcore.

Now here's a snapshot when Rvalid is turned high at two cycles:

image2

Here AWdata eventually throws 0'h04 value which seems to be correct.

[onchipuis]

Excuse me, can you please attach the testbench that are you using?
We can't reproduce the issue.
Maybe this has to be with the AXI_TEST definition. This makes random possible issues (like long timing on the AXI signals). Maybe you want to disable this.
Thank you.

[e19293001]

mriscvcore_env.zip

I've attached my testbench. Just edit the files to point to the
correct location of the mriscvcore code.

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Also, by running your testbench[0], I've noticed that AWready and
Wready[1] are not synchronized with the clock. I don't think that
this is a correct behavior since both signals are high for only
half of the clock cycle.

image1

[0] - mriscvcore/mriscvcore_tb.v
[1] - both ARready and Rvalid are also not sync'd with the clock,
though this is not shown on the image