-
Notifications
You must be signed in to change notification settings - Fork 149
/
fsl_enet_qos.h
1865 lines (1690 loc) · 79.8 KB
/
fsl_enet_qos.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Copyright 2020-2024 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef FSL_ENET_QOS_H_
#define FSL_ENET_QOS_H_
#include "fsl_common.h"
#if defined(FSL_ETH_ENABLE_CACHE_CONTROL)
#include "fsl_cache.h"
#endif
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
#include "fsl_memory.h"
#endif
#if !defined(ENET_QOS)
/* Keep reusing ENET_QOS for platforms which renames it to Ethernet Controller with TSN (EQoS-TSN) */
#if defined(ENET_QOS_TSN)
#define ENET_QOS ENET_QOS_TSN
#endif
#endif
/*!
* @addtogroup enet_qos_qos
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*! @{ */
/*! @brief Defines the driver version. */
#define FSL_ENET_QOS_DRIVER_VERSION (MAKE_VERSION(2, 6, 4))
/*! @} */
/*! @name Control and status region bit masks of the receive buffer descriptor. */
/*! @{ */
/*! @brief Defines for read format. */
#define ENET_QOS_RXDESCRIP_RD_BUFF1VALID_MASK (1UL << 24U) /*!< Buffer1 address valid. */
#define ENET_QOS_RXDESCRIP_RD_BUFF2VALID_MASK (1UL << 25U) /*!< Buffer2 address valid. */
#define ENET_QOS_RXDESCRIP_RD_IOC_MASK (1UL << 30U) /*!< Interrupt enable on complete. */
#define ENET_QOS_RXDESCRIP_RD_OWN_MASK (1UL << 31U) /*!< Own bit. */
/*! @brief Defines for write back format. */
#define ENET_QOS_RXDESCRIP_WR_ERR_MASK ((1UL << 3U) | (1UL << 7U))
#define ENET_QOS_RXDESCRIP_WR_PYLOAD_MASK (0x7UL)
#define ENET_QOS_RXDESCRIP_WR_PTPMSGTYPE_MASK (0xF00UL)
#define ENET_QOS_RXDESCRIP_WR_PTPTYPE_MASK (1UL << 12U)
#define ENET_QOS_RXDESCRIP_WR_PTPVERSION_MASK (1UL << 13U)
#define ENET_QOS_RXDESCRIP_WR_PTPTSA_MASK (1UL << 14U)
#define ENET_QOS_RXDESCRIP_WR_PACKETLEN_MASK (0x7FFFUL)
#define ENET_QOS_RXDESCRIP_WR_ERRSUM_MASK (1UL << 15U)
#define ENET_QOS_RXDESCRIP_WR_TYPE_MASK (0x30000UL)
#define ENET_QOS_RXDESCRIP_WR_DE_MASK (1UL << 19U)
#define ENET_QOS_RXDESCRIP_WR_RE_MASK (1UL << 20U)
#define ENET_QOS_RXDESCRIP_WR_OE_MASK (1UL << 21U)
#define ENET_QOS_RXDESCRIP_WR_RWT_MASK (1UL << 22U)
#define ENET_QOS_RXDESCRIP_WR_GP_MASK (1UL << 22U)
#define ENET_QOS_RXDESCRIP_WR_CRC_MASK (1UL << 23U)
#define ENET_QOS_RXDESCRIP_WR_RS0V_MASK (1UL << 25U)
#define ENET_QOS_RXDESCRIP_WR_RS1V_MASK (1UL << 26U)
#define ENET_QOS_RXDESCRIP_WR_RS2V_MASK (1UL << 27U)
#define ENET_QOS_RXDESCRIP_WR_LD_MASK (1UL << 28U)
#define ENET_QOS_RXDESCRIP_WR_FD_MASK (1UL << 29U)
#define ENET_QOS_RXDESCRIP_WR_CTXT_MASK (1UL << 30U)
#define ENET_QOS_RXDESCRIP_WR_OWN_MASK (1UL << 31U)
#define ENET_QOS_RXDESCRIP_WR_SA_FAILURE_MASK (1UL << 16U)
#define ENET_QOS_RXDESCRIP_WR_DA_FAILURE_MASK (1UL << 17U)
/*! @} */
/*! @name Control and status bit masks of the transmit buffer descriptor. */
/*! @{ */
/*! @brief Defines for read format. */
#define ENET_QOS_TXDESCRIP_RD_BL1_MASK (0x3fffUL)
#define ENET_QOS_TXDESCRIP_RD_BL2_MASK (ENET_QOS_TXDESCRIP_RD_BL1_MASK << 16U)
#define ENET_QOS_TXDESCRIP_RD_BL1(n) ((uint32_t)(n) & ENET_QOS_TXDESCRIP_RD_BL1_MASK)
#define ENET_QOS_TXDESCRIP_RD_BL2(n) (((uint32_t)(n) & ENET_QOS_TXDESCRIP_RD_BL1_MASK) << 16)
#define ENET_QOS_TXDESCRIP_RD_TTSE_MASK (1UL << 30UL)
#define ENET_QOS_TXDESCRIP_RD_IOC_MASK (1UL << 31UL)
#define ENET_QOS_TXDESCRIP_RD_FL_MASK (0x7FFFUL)
#define ENET_QOS_TXDESCRIP_RD_FL(n) ((uint32_t)(n) & ENET_QOS_TXDESCRIP_RD_FL_MASK)
#define ENET_QOS_TXDESCRIP_RD_CIC(n) (((uint32_t)(n) & 0x3U) << 16U)
#define ENET_QOS_TXDESCRIP_RD_TSE_MASK (1UL << 18U)
#define ENET_QOS_TXDESCRIP_RD_SLOT(n) (((uint32_t)(n) & 0x0fU) << 19U)
#define ENET_QOS_TXDESCRIP_RD_SAIC(n) (((uint32_t)(n) & 0x07U) << 23U)
#define ENET_QOS_TXDESCRIP_RD_CPC(n) (((uint32_t)(n) & 0x03U) << 26U)
#define ENET_QOS_TXDESCRIP_RD_LDFD(n) (((uint32_t)(n) & 0x03U) << 28U)
#define ENET_QOS_TXDESCRIP_RD_LD_MASK (1UL << 28U)
#define ENET_QOS_TXDESCRIP_RD_FD_MASK (1UL << 29U)
#define ENET_QOS_TXDESCRIP_RD_CTXT_MASK (1UL << 30U)
#define ENET_QOS_TXDESCRIP_RD_OWN_MASK (1UL << 31U)
/*! @brief Defines for write back format. */
#define ENET_QOS_TXDESCRIP_WB_TTSS_MASK (1UL << 17U)
/*! @} */
/*! @name Bit mask for interrupt enable type. */
/*! @{ */
#define ENET_QOS_ABNORM_INT_MASK \
(ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK | ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK | ENET_QOS_DMA_CHX_INT_EN_RSE_MASK | \
ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK | ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK | ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK)
#define ENET_QOS_NORM_INT_MASK \
(ENET_QOS_DMA_CHX_INT_EN_TIE_MASK | ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK | ENET_QOS_DMA_CHX_INT_EN_RIE_MASK | \
ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK)
/*! @} */
/*! @name Defines some Ethernet parameters. */
/*! @{ */
#ifndef ENET_QOS_RING_NUM_MAX
#define ENET_QOS_RING_NUM_MAX (5U) /*!< The Maximum number of tx/rx descriptor rings. */
#endif
#define ENET_QOS_FRAME_MAX_FRAMELEN (1518U) /*!< Default maximum Ethernet frame size. */
#define ENET_QOS_FCS_LEN (4U) /*!< Ethernet FCS length. */
#define ENET_QOS_ADDR_ALIGNMENT (0x3U) /*!< Recommended Ethernet buffer alignment. */
#define ENET_QOS_BUFF_ALIGNMENT (8U) /*!< Receive buffer alignment shall be 4bytes-aligned. */
#define ENET_QOS_MTL_RXFIFOSIZE (8192U) /*!< The rx fifo size. */
#define ENET_QOS_MTL_TXFIFOSIZE (8192U) /*!< The tx fifo size. */
#define ENET_QOS_MACINT_ENUM_OFFSET (16U) /*!< The offest for mac interrupt in enum type. */
#define ENET_QOS_RXP_ENTRY_COUNT (256U) /*!< RXP table entry count, implied by FRPES in MAC_HW_FEATURE3 */
#define ENET_QOS_RXP_BUFFER_SIZE (256U) /*!< RXP Buffer size, implied by FRPBS in MAC_HW_FEATURE3 */
#define ENET_QOS_EST_WID (24U) /*!< Width of the time interval in Gate Control List */
#define ENET_QOS_EST_DEP (512U) /*!< Maxmimum depth of Gate Control List */
/*! @} */
/*! @brief Defines the status return codes for transaction. */
enum
{
kStatus_ENET_QOS_InitMemoryFail =
MAKE_STATUS(kStatusGroup_ENET_QOS, 0U), /*!< Init fails since buffer memory is not enough. */
kStatus_ENET_QOS_RxFrameError =
MAKE_STATUS(kStatusGroup_ENET_QOS, 1U), /*!< A frame received but data error happen. */
kStatus_ENET_QOS_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET_QOS, 2U), /*!< Failed to receive a frame. */
kStatus_ENET_QOS_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET_QOS, 3U), /*!< No frame arrive. */
kStatus_ENET_QOS_RxFrameDrop =
MAKE_STATUS(kStatusGroup_ENET_QOS, 4U), /*!< Rx frame is dropped since no buffer memory. */
kStatus_ENET_QOS_TxFrameBusy =
MAKE_STATUS(kStatusGroup_ENET_QOS, 5U), /*!< Transmit descriptors are under process. */
kStatus_ENET_QOS_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET_QOS, 6U), /*!< Transmit frame fail. */
kStatus_ENET_QOS_TxFrameOverLen = MAKE_STATUS(kStatusGroup_ENET_QOS, 7U), /*!< Transmit oversize. */
kStatus_ENET_QOS_Est_SwListBusy =
MAKE_STATUS(kStatusGroup_ENET_QOS, 8U), /*!< SW Gcl List not yet processed by HW. */
kStatus_ENET_QOS_Est_SwListWriteAbort = MAKE_STATUS(kStatusGroup_ENET_QOS, 9U), /*!< SW Gcl List write aborted .*/
kStatus_ENET_QOS_Est_InvalidParameter =
MAKE_STATUS(kStatusGroup_ENET_QOS, 10U), /*!< Invalid parameter in Gcl List .*/
kStatus_ENET_QOS_Est_BtrError = MAKE_STATUS(kStatusGroup_ENET_QOS, 11U), /*!< Base Time Error when loading list.*/
kStatus_ENET_QOS_TrgtBusy = MAKE_STATUS(kStatusGroup_ENET_QOS, 12U), /*!< Target time register busy.*/
kStatus_ENET_QOS_Timeout = MAKE_STATUS(kStatusGroup_ENET_QOS, 13U), /*!< Target time register busy.*/
kStatus_ENET_QOS_PpsBusy = MAKE_STATUS(kStatusGroup_ENET_QOS, 14U) /*!< Pps command busy.*/
};
/*! @brief Defines the MII/RGMII mode for data interface between the MAC and the PHY. */
typedef enum _enet_qos_mii_mode
{
kENET_QOS_MiiMode = 0U, /*!< MII mode for data interface. */
kENET_QOS_RgmiiMode = 1U, /*!< RGMII mode for data interface. */
kENET_QOS_RmiiMode = 4U /*!< RMII mode for data interface. */
} enet_qos_mii_mode_t;
/*! @brief Defines the 10/100/1000 Mbps speed for the MII data interface. */
typedef enum _enet_qos_mii_speed
{
kENET_QOS_MiiSpeed10M =
ENET_QOS_MAC_CONFIGURATION_PS(1U) | ENET_QOS_MAC_CONFIGURATION_FES(0U), /*!< Speed 10 Mbps. */
kENET_QOS_MiiSpeed100M =
ENET_QOS_MAC_CONFIGURATION_PS(1U) | ENET_QOS_MAC_CONFIGURATION_FES(1U), /*!< Speed 100 Mbps. */
kENET_QOS_MiiSpeed1000M =
ENET_QOS_MAC_CONFIGURATION_PS(0U) | ENET_QOS_MAC_CONFIGURATION_FES(0U), /*!< Speed 1000 Mbps. */
kENET_QOS_MiiSpeed2500M =
ENET_QOS_MAC_CONFIGURATION_PS(0U) | ENET_QOS_MAC_CONFIGURATION_FES(1U) /*!< Speed 2500 Mbps. */
} enet_qos_mii_speed_t;
/*! @brief Defines the half or full duplex for the MII data interface. */
typedef enum _enet_qos_mii_duplex
{
kENET_QOS_MiiHalfDuplex = 0U, /*!< Half duplex mode. */
kENET_QOS_MiiFullDuplex /*!< Full duplex mode. */
} enet_qos_mii_duplex_t;
/*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */
typedef enum _enet_qos_mii_normal_opcode
{
kENET_QOS_MiiWriteFrame =
ENET_QOS_MAC_MDIO_ADDRESS_GOC_1(0U) |
ENET_QOS_MAC_MDIO_ADDRESS_GOC_0(1U), /*!< Write frame operation for a valid MII management frame. */
kENET_QOS_MiiReadFrame =
ENET_QOS_MAC_MDIO_ADDRESS_GOC_1(1U) |
ENET_QOS_MAC_MDIO_ADDRESS_GOC_0(1U) /*!< Read frame operation for a valid MII management frame. */
} enet_qos_mii_normal_opcode;
/*! @brief Define the DMA maximum transmit burst length. */
typedef enum _enet_qos_dma_burstlen
{
kENET_QOS_BurstLen1 = 0x00001U, /*!< DMA burst length 1. */
kENET_QOS_BurstLen2 = 0x00002U, /*!< DMA burst length 2. */
kENET_QOS_BurstLen4 = 0x00004U, /*!< DMA burst length 4. */
kENET_QOS_BurstLen8 = 0x00008U, /*!< DMA burst length 8. */
kENET_QOS_BurstLen16 = 0x00010U, /*!< DMA burst length 16. */
kENET_QOS_BurstLen32 = 0x00020U, /*!< DMA burst length 32. */
kENET_QOS_BurstLen64 = 0x10008U, /*!< DMA burst length 64. eight times enabled. */
kENET_QOS_BurstLen128 = 0x10010U, /*!< DMA burst length 128. eight times enabled. */
kENET_QOS_BurstLen256 = 0x10020U, /*!< DMA burst length 256. eight times enabled. */
} enet_qos_dma_burstlen;
/*! @brief Define the flag for the descriptor. */
typedef enum _enet_qos_desc_flag
{
kENET_QOS_MiddleFlag = 0, /*!< It's a middle descriptor of the frame. */
kENET_QOS_LastFlagOnly, /*!< It's the last descriptor of the frame. */
kENET_QOS_FirstFlagOnly, /*!< It's the first descriptor of the frame. */
kENET_QOS_FirstLastFlag /*!< It's the first and last descriptor of the frame. */
} enet_qos_desc_flag;
/*! @brief Define the system time adjust operation control. */
typedef enum _enet_qos_systime_op
{
kENET_QOS_SystimeAdd = 0U, /*!< System time add to. */
kENET_QOS_SystimeSubtract = 1U /*!< System time subtract. */
} enet_qos_systime_op;
/*! @brief Define the system time rollover control. */
typedef enum _enet_qos_ts_rollover_type
{
kENET_QOS_BinaryRollover = 0, /*!< System time binary rollover.*/
kENET_QOS_DigitalRollover = 1 /*!< System time digital rollover.*/
} enet_qos_ts_rollover_type;
/*! @brief Defines some special configuration for ENET.
*
* These control flags are provided for special user requirements.
* Normally, these is no need to set this control flags for ENET initialization.
* But if you have some special requirements, set the flags to specialControl
* in the enet_qos_config_t.
* @note "kENET_QOS_StoreAndForward" is recommended to be set.
*/
typedef enum _enet_qos_special_config
{
/***********************DMA CONFIG**********************************************/
kENET_QOS_DescDoubleBuffer = 0x0001U, /*!< The double buffer is used in the tx/rx descriptor. */
/**************************MTL************************************/
kENET_QOS_StoreAndForward = 0x0002U, /*!< The rx/tx store and forward enable. */
/***********************MAC****************************************/
kENET_QOS_PromiscuousEnable = 0x0004U, /*!< The promiscuous enabled. */
kENET_QOS_FlowControlEnable = 0x0008U, /*!< The flow control enabled. */
kENET_QOS_BroadCastRxDisable = 0x0010U, /*!< The broadcast disabled. */
kENET_QOS_MulticastAllEnable = 0x0020U, /*!< All multicast are passed. */
kENET_QOS_8023AS2KPacket = 0x0040U, /*!< 8023as support for 2K packets. */
kENET_QOS_HashMulticastEnable = 0x0080U, /*!< The multicast packets are filtered through hash table. */
kENET_QOS_RxChecksumOffloadEnable = 0x0100U, /*!< The Rx checksum offload enabled. */
} enet_qos_special_config_t;
/*! @brief List of DMA interrupts supported by the ENET interrupt. This
* enumeration uses one-bot encoding to allow a logical OR of multiple
* members.
*/
typedef enum _enet_qos_dma_interrupt_enable
{
kENET_QOS_DmaTx = ENET_QOS_DMA_CHX_INT_EN_TIE_MASK, /*!< Tx interrupt. */
kENET_QOS_DmaTxStop = ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK, /*!< Tx stop interrupt. */
kENET_QOS_DmaTxBuffUnavail = ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK, /*!< Tx buffer unavailable. */
kENET_QOS_DmaRx = ENET_QOS_DMA_CHX_INT_EN_RIE_MASK, /*!< Rx interrupt. */
kENET_QOS_DmaRxBuffUnavail = ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK, /*!< Rx buffer unavailable. */
kENET_QOS_DmaRxStop = ENET_QOS_DMA_CHX_INT_EN_RSE_MASK, /*!< Rx stop. */
kENET_QOS_DmaRxWatchdogTimeout = ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK, /*!< Rx watchdog timeout. */
kENET_QOS_DmaEarlyTx = ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK, /*!< Early transmit. */
kENET_QOS_DmaEarlyRx = ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK, /*!< Early receive. */
kENET_QOS_DmaBusErr = ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK, /*!< Fatal bus error. */
} enet_qos_dma_interrupt_enable_t;
/*! @brief List of mac interrupts supported by the ENET interrupt. This
* enumeration uses one-bot encoding to allow a logical OR of multiple
* members.
*/
typedef enum _enet_qos_mac_interrupt_enable
{
kENET_QOS_MacPmt = (ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK << ENET_QOS_MACINT_ENUM_OFFSET),
kENET_QOS_MacTimestamp = (ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK << ENET_QOS_MACINT_ENUM_OFFSET),
} enet_qos_mac_interrupt_enable_t;
/*! @brief Defines the common interrupt event for callback use. */
typedef enum _enet_qos_event
{
kENET_QOS_RxIntEvent, /*!< Receive interrupt event. */
kENET_QOS_TxIntEvent, /*!< Transmit interrupt event. */
kENET_QOS_WakeUpIntEvent, /*!< Wake up interrupt event. */
kENET_QOS_TimeStampIntEvent, /*!< Time stamp interrupt event. */
} enet_qos_event_t;
/*! @brief Define the MTL mode for multiple queues/rings. */
typedef enum _enet_qos_queue_mode
{
kENET_QOS_AVB_Mode = 1U, /*!< Enable queue in AVB mode. */
kENET_QOS_DCB_Mode = 2U, /*!< Enable queue in DCB mode. */
} enet_qos_queue_mode_t;
/*! @brief Define the MTL tx scheduling algorithm for multiple queues/rings. */
typedef enum _enet_qos_mtl_multiqueue_txsche
{
kENET_QOS_txWeightRR = 0U, /*!< Tx weight round-robin. */
kENET_QOS_txWeightFQ = 1U, /*!< Tx weight fair queuing. */
kENET_QOS_txDefictWeightRR = 2U, /*!< Tx deficit weighted round-robin. */
kENET_QOS_txStrPrio = 3U, /*!< Tx strict priority. */
} enet_qos_mtl_multiqueue_txsche;
/*! @brief Define the MTL rx scheduling algorithm for multiple queues/rings. */
typedef enum _enet_qos_mtl_multiqueue_rxsche
{
kENET_QOS_rxStrPrio = 0U, /*!< Rx strict priority, Queue 0 has the lowest priority. */
kENET_QOS_rxWeightStrPrio, /*!< Weighted Strict Priority. */
} enet_qos_mtl_multiqueue_rxsche;
/*! @brief Define the MTL rx queue and DMA channel mapping. */
typedef enum _enet_qos_mtl_rxqueuemap
{
kENET_QOS_StaticDirctMap = 0x100U, /*!< The received fame in rx Qn(n = 0,1) directly map to dma channel n. */
kENET_QOS_DynamicMap =
0x1010U, /*!< The received frame in rx Qn(n = 0,1) map to the dma channel m(m = 0,1) related with the same Mac.
*/
} enet_qos_mtl_rxqueuemap_t;
/*! @brief Defines the package type for receive queue routing. */
typedef enum _enet_qos_rx_queue_route
{
kENET_QOS_PacketNoQ = 0x0, /* Not specific queue */
kENET_QOS_PacketAVCPQ = (1U << 0U), /* AV Untagged Control Packets Queue */
kENET_QOS_PacketPTPQ = (1U << 1U), /* PTP Packets Queue */
kENET_QOS_PacketDCBCPQ = (1U << 2U), /* DCB Control Packets Queue */
kENET_QOS_PacketUPQ = (1U << 3U), /* Untagged Packets Queue */
kENET_QOS_PacketMCBCQ = (1U << 4U), /* Multicast & Broadcast Packets Queue */
} enet_qos_rx_queue_route_t;
/*! @brief Defines the ENET PTP message related constant. */
typedef enum _enet_qos_ptp_event_type
{
kENET_QOS_PtpEventMsgType = 3U, /*!< PTP event message type. */
kENET_QOS_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */
kENET_QOS_PtpEventPort = 319U, /*!< PTP event port number. */
kENET_QOS_PtpGnrlPort = 320U /*!< PTP general port number. */
} enet_qos_ptp_event_type_t;
/*! @brief Defines the PPS instance numbers. */
typedef enum _enet_qos_ptp_pps_instance
{
kENET_QOS_PtpPpsIstance0 = 0U, /*!< PPS instance 0. */
kENET_QOS_PtpPpsIstance1, /*!< PPS instance 1. */
kENET_QOS_PtpPpsIstance2, /*!< PPS instance 2. */
kENET_QOS_PtpPpsIstance3 /*!< PPS instance 3. */
} enet_qos_ptp_pps_instance_t;
/*! @brief Defines the Target Time register mode. */
typedef enum _enet_qos_ptp_pps_trgt_mode
{
kENET_QOS_PtpPpsTrgtModeOnlyInt = 0U, /*!< Only interrupts. */
kENET_QOS_PtpPpsTrgtModeIntSt = 2, /*!< Both interrupt and output signal. */
kENET_QOS_PtpPpsTrgtModeOnlySt = 3, /*!< Only output signal. */
} enet_qos_ptp_pps_trgt_mode_t;
/*! @brief Defines commands for ppscmd register. */
typedef enum _enet_qos_ptp_pps_cmd
{
kENET_QOS_PtpPpsCmdNC = 0U, /*!< No Command. */
kENET_QOS_PtpPpsCmdSSP = 1U, /*!< Start Single Pulse. */
kENET_QOS_PtpPpsCmdSPT = 2U, /*!< Start Pulse Train. */
kENET_QOS_PtpPpsCmdCS = 3U, /*!< Cancel Start. */
kENET_QOS_PtpPpsCmdSPTAT = 4U, /*!< Stop Pulse Train At Time. */
kENET_QOS_PtpPpsCmdSPTI = 5U, /*!< Stop Pulse Train Immediately. */
kENET_QOS_PtpPpsCmdCSPT = 6U, /*!< Cancel Stop Pulse Train. */
} enet_qos_ptp_pps_cmd_t;
/*! @brief Defines the enmueration of ETS list length.
*/
typedef enum _enet_qos_ets_list_length
{
kENET_QOS_Ets_List_64 = 7U, /*!< List length of 64 */
kENET_QOS_Ets_List_128 = 8U, /*!< List length of 128 */
kENET_QOS_Ets_List_256 = 9U, /*!< List length of 256 */
kENET_QOS_Ets_List_512 = 10U, /*!< List length of 512 */
kENET_QOS_Ets_List_1024 = 11U, /*!< List length of 1024 */
} enet_qos_ets_list_length_t;
/*! @brief Defines the enmueration of ETS gate control address.
*/
typedef enum _enet_qos_ets_gccr_addr
{
kENET_QOS_Ets_btr_low = 0U, /*!< BTR Low */
kENET_QOS_Ets_btr_high = 1U, /*!< BTR High */
kENET_QOS_Ets_ctr_low = 2U, /*!< CTR Low */
kENET_QOS_Ets_ctr_high = 3U, /*!< CTR High */
kENET_QOS_Ets_ter = 4U, /*!< TER */
kENET_QOS_Ets_llr = 5U, /*!< LLR */
} enet_qos_ets_gccr_addr_t;
/*! @brief Defines the enmueration of DMA channel used
* for rx parser entry.
*/
typedef enum _enet_qos_rxp_dma_chn
{
kENET_QOS_Rxp_DMAChn0 = 1U, /*!< DMA Channel 0 used for RXP entry match */
kENET_QOS_Rxp_DMAChn1 = 2U, /*!< DMA Channel 1 used for RXP entry match */
kENET_QOS_Rxp_DMAChn2 = 4U, /*!< DMA Channel 2 used for RXP entry match */
kENET_QOS_Rxp_DMAChn3 = 8U, /*!< DMA Channel 3 used for RXP entry match */
kENET_QOS_Rxp_DMAChn4 = 16U, /*!< DMA Channel 4 used for RXP entry match */
} enet_qos_rxp_dma_chn_t;
/*! @brief Define the Tx checksum offload options. */
typedef enum _enet_qos_tx_offload
{
kENET_QOS_TxOffloadDisable = 0U, /*!< Disable Tx checksum offload. */
kENET_QOS_TxOffloadIPHeader = 1U, /*!< Enable IP header checksum calculation and insertion. */
kENET_QOS_TxOffloadIPHeaderPlusPayload =
2U, /*!< Enable IP header and payload checksum calculation and insertion. */
kENET_QOS_TxOffloadAll = 3U, /*!< Enable IP header, payload and pseudo header checksum calculation and insertion. */
} enet_qos_tx_offload_t;
/*! @brief Defines the receive descriptor structure
* has the read-format and write-back format structure. They both
* has the same size with different region definition. so
* we define the read-format region as the receive descriptor structure
* Use the read-format region mask bits in the descriptor initialization
* Use the write-back format region mask bits in the receive data process.
*/
typedef struct _enet_qos_rx_bd_struct
{
__IO uint32_t buff1Addr; /*!< Buffer 1 address */
__IO uint32_t reserved; /*!< Reserved */
__IO uint32_t buff2Addr; /*!< Buffer 2 or next descriptor address */
__IO uint32_t control; /*!< Buffer 1/2 byte counts and control */
} enet_qos_rx_bd_struct_t;
/*! @brief Defines the transmit descriptor structure
* has the read-format and write-back format structure. They both
* has the same size with different region definition. so
* we define the read-format region as the transmit descriptor structure
* Use the read-format region mask bits in the descriptor initialization
* Use the write-back format region mask bits in the transmit data process.
*/
typedef struct _enet_qos_tx_bd_struct
{
__IO uint32_t buff1Addr; /*!< Buffer 1 address */
__IO uint32_t buff2Addr; /*!< Buffer 2 address */
__IO uint32_t buffLen; /*!< Buffer 1/2 byte counts */
__IO uint32_t controlStat; /*!< TDES control and status word */
} enet_qos_tx_bd_struct_t;
/*! @brief Defines the Tx BD configuration structure. */
typedef struct _enet_qos_tx_bd_config_struct
{
void *buffer1; /*!< The first buffer address in the descriptor. */
uint32_t bytes1; /*!< The bytes in the fist buffer. */
void *buffer2; /*!< The second buffer address in the descriptor. */
uint32_t bytes2; /*!< The bytes in the second buffer. */
uint32_t framelen; /*!< The length of the frame to be transmitted. */
bool intEnable; /*!< Interrupt enable flag. */
bool tsEnable; /*!< The timestamp enable. */
enet_qos_tx_offload_t txOffloadOps; /*!< The Tx checksum offload option. */
enet_qos_desc_flag flag; /*!< The flag of this tx desciriptor, see "enet_qos_desc_flag". */
} enet_qos_tx_bd_config_struct_t;
/*! @brief Defines the ENET PTP time stamp structure. */
typedef struct _enet_qos_ptp_time
{
uint64_t second; /*!< Second. */
uint32_t nanosecond; /*!< Nanosecond. */
} enet_qos_ptp_time_t;
/*! @brief Defines the frame info structure. */
typedef struct enet_qos_frame_info
{
void *context; /*!< User specified data, could be buffer address for free */
bool isTsAvail; /*!< Flag indicates timestamp available status */
enet_qos_ptp_time_t timeStamp; /*!< Timestamp of frame */
} enet_qos_frame_info_t;
/*! @brief Defines the ENET transmit dirty addresses ring/queue structure. */
typedef struct _enet_qos_tx_dirty_ring
{
enet_qos_frame_info_t *txDirtyBase; /*!< Dirty buffer descriptor base address pointer. */
uint16_t txGenIdx; /*!< tx generate index. */
uint16_t txConsumIdx; /*!< tx consume index. */
uint16_t txRingLen; /*!< tx ring length. */
bool isFull; /*!< tx ring is full flag, add this parameter to avoid waste one element. */
} enet_qos_tx_dirty_ring_t;
/*! @brief Defines the ENET PTP configuration structure. */
typedef struct _enet_qos_ptp_config
{
bool fineUpdateEnable; /*!< Use the fine update. */
uint32_t defaultAddend; /*!< Default addend value when fine update is enable, could be 2^32 / (refClk_Hz /
ENET_QOS_MICRSECS_ONESECOND / ENET_QOS_SYSTIME_REQUIRED_CLK_MHZ). */
uint32_t systemTimeClock_Hz; /*! The desired system time frequency. Must be lower than reference clock. (Only used
with fine correction method). */
bool ptp1588V2Enable; /*!< ptp 1588 version 2 is used. */
enet_qos_ts_rollover_type tsRollover; /*!< 1588 time nanosecond rollover. */
} enet_qos_ptp_config_t;
/*! @brief Defines the EST gate operation structure. */
typedef struct _enet_qos_est_gate_op
{
uint32_t gate;
uint32_t interval;
} enet_qos_est_gate_op_t;
/*! @brief Defines the EST gate control list structure. */
typedef struct _enet_qos_est_gcl
{
bool enable; /*!< Enable or disable EST */
uint64_t baseTime; /*! Base Time 32 bits seconds 32 bits nanoseconds */
uint64_t cycleTime; /*! Cycle Time 32 bits seconds 32 bits nanoseconds */
uint32_t extTime; /*! Time Extension 32 bits seconds 32 bits nanoseconds */
uint32_t numEntries; /*! Number of entries */
enet_qos_est_gate_op_t *opList; /*! Pointer to GCL list size */
} enet_qos_est_gcl_t;
/*! @brief Defines the ENET_QOS Rx parser configuration structure.*/
typedef struct _enet_qos_rxp_config
{
uint32_t matchData; /*! 4-byte match data used for comparing with incoming packet */
uint32_t matchEnable; /*! When matchEnable is set to 1, the matchData is used for comparing */
uint8_t acceptFrame : 1; /*! When acceptFrame = 1 and data is matched, the frame will be sent to DMA channel */
uint8_t rejectFrame : 1; /*! When rejectFrame = 1 and data is matched, the frame will be dropped */
uint8_t inverseMatch : 1; /*! Inverse match */
uint8_t nextControl : 1; /*! Next instruction indexing control */
uint8_t reserved : 4; /*! Reserved control fields */
uint8_t frameOffset; /*! Frame offset in the packet data to be compared for match, in terms of 4 bytes. */
uint8_t okIndex; /*! Memory Index to be used next. */
uint8_t dmaChannel; /*! The DMA channel enet_qos_rxp_dma_chn_t used for receiving the frame when frame match and
acceptFrame = 1 */
uint32_t reserved2; /*! Reserved for future enhancements */
} enet_qos_rxp_config_t;
/*! @brief Defines the buffer descriptor configure structure.
*
* @note
* 1. The receive and transmit descriptor start address pointer and tail pointer must be word-aligned.
* 2. The recommended minimum tx/rx ring length is 4.
* 3. The tx/rx descriptor tail address shall be the address pointer to the address just after the end
* of the last last descriptor. because only the descriptors between the start address and the
* tail address will be used by DMA.
* 4. The descriptor address is the start address of all used contiguous memory.
* for example, the rxDescStartAddrAlign is the start address of rxRingLen contiguous descriptor memories
* for rx descriptor ring 0.
* 5. The "*rxBufferstartAddr" is the first element of rxRingLen (2*rxRingLen for double buffers)
* rx buffers. It means the *rxBufferStartAddr is the rx buffer for the first descriptor
* the *rxBufferStartAddr + 1 is the rx buffer for the second descriptor or the rx buffer for
* the second buffer in the first descriptor. so please make sure the rxBufferStartAddr is the
* address of a rxRingLen or 2*rxRingLen array.
*/
typedef struct _enet_qos_buffer_config
{
uint8_t rxRingLen; /*!< The length of receive buffer descriptor ring. */
uint8_t txRingLen; /*!< The length of transmit buffer descriptor ring. */
enet_qos_tx_bd_struct_t *txDescStartAddrAlign; /*!< Aligned transmit descriptor start address. */
enet_qos_tx_bd_struct_t *txDescTailAddrAlign; /*!< Aligned transmit descriptor tail address. */
enet_qos_frame_info_t *txDirtyStartAddr; /*!< Start address of the dirty tx frame information. */
enet_qos_rx_bd_struct_t *rxDescStartAddrAlign; /*!< Aligned receive descriptor start address. */
enet_qos_rx_bd_struct_t *rxDescTailAddrAlign; /*!< Aligned receive descriptor tail address. */
uint32_t *rxBufferStartAddr; /*!< Start address of the rx buffers. */
uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */
bool rxBuffNeedMaintain; /*!< Whether receive data buffer need cache maintain. */
} enet_qos_buffer_config_t;
/*! @brief Defines the CBS configuration for queue. */
typedef struct _enet_qos_cbs_config
{
uint16_t sendSlope; /*!< Send slope configuration. */
uint16_t idleSlope; /*!< Idle slope configuration. */
uint32_t highCredit; /*!< High credit. */
uint32_t lowCredit; /*!< Low credit. */
} enet_qos_cbs_config_t;
/*! @brief Defines the queue configuration structure. */
typedef struct enet_qos_tx_queue_config
{
enet_qos_queue_mode_t mode; /*!< tx queue mode configuration. */
uint32_t weight; /*!< Refer to the MTL TxQ Quantum Weight register. */
uint32_t priority; /*!< Refer to Transmit Queue Priority Mapping register. */
enet_qos_cbs_config_t *cbsConfig; /*!< CBS configuration if queue use AVB mode. */
} enet_qos_queue_tx_config_t;
/*! @brief Defines the queue configuration structure. */
typedef struct enet_qos_rx_queue_config
{
enet_qos_queue_mode_t mode; /*!< rx queue mode configuration. */
uint8_t mapChannel; /*!< tx queue map dma channel. */
uint32_t priority; /*!< Rx queue priority. */
enet_qos_rx_queue_route_t packetRoute; /*!< Receive packet routing. */
} enet_qos_queue_rx_config_t;
/*! @brief Defines the configuration when multi-queue is used. */
typedef struct enet_qos_multiqueue_config
{
enet_qos_dma_burstlen burstLen; /*!< Burst len for the multi-queue. */
uint8_t txQueueUse; /*!< Used Tx queue count. */
enet_qos_mtl_multiqueue_txsche mtltxSche; /*!< Transmit schedule for multi-queue. */
enet_qos_queue_tx_config_t txQueueConfig[ENET_QOS_RING_NUM_MAX]; /*!< Tx Queue configuration. */
uint8_t rxQueueUse; /*!< Used Rx queue count. */
enet_qos_mtl_multiqueue_rxsche mtlrxSche; /*!< Receive schedule for multi-queue. */
enet_qos_queue_rx_config_t rxQueueConfig[ENET_QOS_RING_NUM_MAX]; /*!< Rx Queue configuration. */
} enet_qos_multiqueue_config_t;
/*! @brief Defines the Rx memory buffer alloc function pointer. */
typedef void *(*enet_qos_rx_alloc_callback_t)(ENET_QOS_Type *base, void *userData, uint8_t channel);
/*! @brief Defines the Rx memory buffer free function pointer. */
typedef void (*enet_qos_rx_free_callback_t)(ENET_QOS_Type *base, void *buffer, void *userData, uint8_t channel);
/*! @brief Defines the basic configuration structure for the ENET device.
*
* @note Default the signal queue is used so the "*multiqueueCfg" is set default
* with NULL. Set the pointer with a valid configuration pointer if the multiple
* queues are required. If multiple queue is enabled, please make sure the
* buffer configuration for all are prepared also.
*/
typedef struct _enet_qos_config
{
uint16_t specialControl; /*!< The logic or of enet_qos_special_config_t */
enet_qos_multiqueue_config_t *multiqueueCfg; /*!< Use multi-queue. */
/* -----------------MAC block-------------------------------*/
enet_qos_mii_mode_t miiMode; /*!< MII mode. */
enet_qos_mii_speed_t miiSpeed; /*!< MII Speed. */
enet_qos_mii_duplex_t miiDuplex; /*!< MII duplex. */
uint16_t
pauseDuration; /*!< Used in the tx flow control frame, only valid when kENET_QOS_FlowControlEnable is set. */
/* -----------------Timestamp -------------------------------*/
enet_qos_ptp_config_t *ptpConfig; /*!< PTP 1588 feature configuration */
uint32_t csrClock_Hz; /*!< CSR clock frequency in HZ. */
enet_qos_rx_alloc_callback_t rxBuffAlloc; /*!< Callback to alloc memory, must be provided for zero-copy Rx. */
enet_qos_rx_free_callback_t rxBuffFree; /*!< Callback to free memory, must be provided for zero-copy Rx. */
} enet_qos_config_t;
/* Forward declaration of the handle typedef. */
typedef struct _enet_qos_handle enet_qos_handle_t;
/*! @brief ENET callback function. */
typedef void (*enet_qos_callback_t)(
ENET_QOS_Type *base, enet_qos_handle_t *handle, enet_qos_event_t event, uint8_t channel, void *userData);
/*! @brief Defines the ENET transmit buffer descriptor ring/queue structure. */
typedef struct _enet_qos_tx_bd_ring
{
enet_qos_tx_bd_struct_t *txBdBase; /*!< Buffer descriptor base address pointer. */
uint16_t txGenIdx; /*!< tx generate index. */
uint16_t txConsumIdx; /*!< tx consume index. */
volatile uint16_t txDescUsed; /*!< tx descriptor used number. */
uint16_t txRingLen; /*!< tx ring length. */
} enet_qos_tx_bd_ring_t;
/*! @brief Defines the ENET receive buffer descriptor ring/queue structure. */
typedef struct _enet_qos_rx_bd_ring
{
enet_qos_rx_bd_struct_t *rxBdBase; /*!< Buffer descriptor base address pointer. */
uint16_t rxGenIdx; /*!< The current available receive buffer descriptor pointer. */
uint16_t rxRingLen; /*!< Receive ring length. */
uint32_t rxBuffSizeAlign; /*!< Receive buffer size. */
} enet_qos_rx_bd_ring_t;
/*! @brief Defines the ENET handler structure. */
struct _enet_qos_handle
{
uint8_t txQueueUse; /*!< Used tx queue count. */
uint8_t rxQueueUse; /*!< Used rx queue count. */
bool doubleBuffEnable; /*!< The double buffer is used in the descriptor. */
bool rxintEnable; /*!< Rx interrupt enabled. */
bool rxMaintainEnable[ENET_QOS_RING_NUM_MAX]; /*!< Rx buffer cache maintain enabled. */
enet_qos_rx_bd_ring_t rxBdRing[ENET_QOS_RING_NUM_MAX]; /*!< Receive buffer descriptor. */
enet_qos_tx_bd_ring_t txBdRing[ENET_QOS_RING_NUM_MAX]; /*!< Transmit buffer descriptor. */
enet_qos_tx_dirty_ring_t txDirtyRing[ENET_QOS_RING_NUM_MAX]; /*!< Transmit dirty buffers addresses. */
uint32_t *rxBufferStartAddr[ENET_QOS_RING_NUM_MAX]; /*!< Rx buffer start address for reInitialize. */
enet_qos_callback_t callback; /*!< Callback function. */
void *userData; /*!< Callback function parameter.*/
uint8_t multicastCount[64]; /*!< Multicast collisions counter */
enet_qos_rx_alloc_callback_t rxBuffAlloc; /*!< Callback to alloc memory, must be provided for zero-copy Rx. */
enet_qos_rx_free_callback_t rxBuffFree; /*!< Callback to free memory, must be provided for zero-copy Rx. */
};
/*! @brief Defines the ENET state structure.
*
* @note The structure contains saved state for the instance.
* It could be stored in enet_qos_handle_t, but that's used
* only with the transactional API.
*/
typedef struct _enet_qos_state
{
enet_qos_mii_mode_t miiMode; /*!< MII mode. */
} enet_qos_state_t;
/*! @brief Defines the frame buffer structure. */
typedef struct _enet_qos_buffer_struct
{
void *buffer; /*!< The buffer store the whole or partial frame. */
uint16_t length; /*!< The byte length of this buffer. */
} enet_qos_buffer_struct_t;
/*! @brief Defines the Rx frame error structure. */
typedef struct _enet_qos_rx_frame_error
{
bool rxDstAddrFilterErr : 1; /*!< Destination Address Filter Fail. */
bool rxSrcAddrFilterErr : 1; /*!< SA Address Filter Fail. */
bool rxDribbleErr : 1; /*!< Dribble error. */
bool rxReceiveErr : 1; /*!< Receive error. */
bool rxOverFlowErr : 1; /*!< Receive over flow. */
bool rxWatchDogErr : 1; /*!< Watch dog timeout. */
bool rxGaintPacketErr : 1; /*!< Receive gaint packet. */
bool rxCrcErr : 1; /*!< Receive CRC error. */
} enet_qos_rx_frame_error_t;
typedef struct _enet_qos_rx_frame_attribute_struct
{
bool isTsAvail; /*!< Rx frame timestamp is available or not. */
enet_qos_ptp_time_t timestamp; /*!< The nanosecond part timestamp of this Rx frame. */
} enet_qos_rx_frame_attribute_t;
/*! @brief Defines the Rx frame data structure. */
typedef struct _enet_qos_rx_frame_struct
{
enet_qos_buffer_struct_t *rxBuffArray; /*!< Rx frame buffer structure. */
uint16_t totLen; /*!< Rx frame total length. */
enet_qos_rx_frame_attribute_t rxAttribute; /*!< Rx frame attribute structure. */
enet_qos_rx_frame_error_t rxFrameError; /*!< Rx frame error. */
} enet_qos_rx_frame_struct_t;
/*! @brief Defines the ENET QOS transfer statistics structure. */
typedef struct _enet_qos_transfer_stats
{
uint32_t statsRxFrameCount; /*!< Rx frame number. */
uint32_t statsRxCrcErr; /*!< Rx frame number with CRC error. */
uint32_t statsRxAlignErr; /*!< Rx frame number with alignment error. */
uint32_t statsRxLengthErr; /*!< Rx frame length field doesn't equal to packet size. */
uint32_t statsRxFifoOverflowErr; /*!< Rx FIFO overflow count. */
uint32_t statsTxFrameCount; /*!< Tx frame number. */
uint32_t statsTxFifoUnderRunErr; /*!< Tx FIFO underrun count. */
} enet_qos_transfer_stats_t;
/* Typedef for interrupt handler. */
typedef void (*enet_qos_isr_t)(ENET_QOS_Type *base, enet_qos_handle_t *handle);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to enet clocks for each instance. */
extern const clock_ip_name_t s_enetqosClock[];
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*!
* @brief Set ENET system configuration.
* @note User needs to provide the implementation because the implementation is SoC specific.
* This function set the phy selection and enable clock.
* It should be called before any other ethernet operation.
*
* @param miiMode The MII/RGMII/RMII mode for interface between the phy and Ethernet.
*/
extern void ENET_QOS_SetSYSControl(enet_qos_mii_mode_t miiMode);
/*!
* @brief Enable/Disable ENET qos clock.
* @note User needs to provide the implementation because the implementation is SoC specific.
* This function should be called before config RMII mode.
*
*/
extern void ENET_QOS_EnableClock(bool enable);
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name Initialization and De-initialization
* @{
*/
/*!
* @brief Gets the ENET default configuration structure.
*
* The purpose of this API is to get the default ENET configure
* structure for @ref ENET_QOS_Init(). User may use the initialized
* structure unchanged in @ref ENET_QOS_Init(), or modify some fields of the
* structure before calling @ref ENET_QOS_Init().
* Example:
@code
enet_qos_config_t config;
ENET_QOS_GetDefaultConfig(&config);
@endcode
* @param config The ENET mac controller configuration structure pointer.
*/
void ENET_QOS_GetDefaultConfig(enet_qos_config_t *config);
/*!
* @brief Initializes the ENET module.
*
* This function initializes it with the ENET basic
* configuration.
*
* @param base ENET peripheral base address.
* @param config ENET mac configuration structure pointer.
* The "enet_qos_config_t" type mac configuration return from ENET_QOS_GetDefaultConfig
* can be used directly. It is also possible to verify the Mac configuration using other methods.
* @param macAddr Pointer to ENET mac address array of Ethernet device. This MAC address should be
* provided.
* @param macCount Count of macAddr in the ENET mac address array
* @param refclkSrc_Hz ENET input reference clock.
*/
status_t ENET_QOS_Up(
ENET_QOS_Type *base, const enet_qos_config_t *config, uint8_t *macAddr, uint8_t macCount, uint32_t refclkSrc_Hz);
/*!
* @brief Initializes the ENET module.
*
* This function ungates the module clock and initializes it with the ENET basic
* configuration.
*
* @param base ENET peripheral base address.
* @param config ENET mac configuration structure pointer.
* The "enet_qos_config_t" type mac configuration return from ENET_QOS_GetDefaultConfig
* can be used directly. It is also possible to verify the Mac configuration using other methods.
* @param macAddr Pointer to ENET mac address array of Ethernet device. This MAC address should be
* provided.
* @param macCount Count of macAddr in the ENET mac address array
* @param refclkSrc_Hz ENET input reference clock.
*/
status_t ENET_QOS_Init(
ENET_QOS_Type *base, const enet_qos_config_t *config, uint8_t *macAddr, uint8_t macCount, uint32_t refclkSrc_Hz);
/*!
* @brief Stops the ENET module.
* This function disables the ENET module.
*
* @param base ENET peripheral base address.
*/
void ENET_QOS_Down(ENET_QOS_Type *base);
/*!
* @brief Deinitializes the ENET module.
* This function gates the module clock and disables the ENET module.
*
* @param base ENET peripheral base address.
*/
void ENET_QOS_Deinit(ENET_QOS_Type *base);
/*!
* @brief Get the ENET instance from peripheral base address.
*
* @param base ENET peripheral base address.
* @return ENET instance.
*/
uint32_t ENET_QOS_GetInstance(ENET_QOS_Type *base);
/*!
* @brief Initialize for all ENET descriptors.
*
* @note This function is do all tx/rx descriptors initialization. Because this API
* read all interrupt registers first and then set the interrupt flag for all descriptors,
* if the interrupt register is set. so the descriptor initialization should be called
* after ENET_QOS_Init(), ENET_QOS_EnableInterrupts() and ENET_QOS_CreateHandle()(if transactional APIs
* are used).
*
* @param base ENET peripheral base address.
* @param config The configuration for ENET.
* @param bufferConfig All buffers configuration.
*/
status_t ENET_QOS_DescriptorInit(ENET_QOS_Type *base,
enet_qos_config_t *config,
enet_qos_buffer_config_t *bufferConfig);
/*!
* @brief Allocates Rx buffers for all BDs.
* It's used for zero copy Rx. In zero copy Rx case, Rx buffers are dynamic. This function
* will populate initial buffers in all BDs for receiving. Then ENET_QOS_GetRxFrame() is used
* to get Rx frame with zero copy, it will allocate new buffer to replace the buffer in BD taken
* by application application should free those buffers after they're used.
*
* @note This function should be called after ENET_QOS_CreateHandler() and buffer allocating callback
* function should be ready.
*
* @param base ENET_QOS peripheral base address.
* @param handle The ENET_QOS handler structure. This is the same handler pointer used in the ENET_QOS_Init.
*/
status_t ENET_QOS_RxBufferAllocAll(ENET_QOS_Type *base, enet_qos_handle_t *handle);
/*!
* @brief Frees Rx buffers in all BDs.
* It's used for zero copy Rx. In zero copy Rx case, Rx buffers are dynamic. This function
* will free left buffers in all BDs.
*
* @param base ENET_QOS peripheral base address.
* @param handle The ENET_QOS handler structure. This is the same handler pointer used in the ENET_QOS_Init.
*/
void ENET_QOS_RxBufferFreeAll(ENET_QOS_Type *base, enet_qos_handle_t *handle);
/*!
* @brief Starts the ENET rx/tx.
* This function enable the tx/rx and starts the rx/tx DMA.
* This shall be set after ENET initialization and before
* starting to receive the data.
*
* @param base ENET peripheral base address.
* @param rxRingNum The number of the used rx rings. It shall not be
* larger than the ENET_QOS_RING_NUM_MAX(2). If the ringNum is set with
* 1, the ring 0 will be used.
* @param txRingNum The number of the used tx rings. It shall not be
* larger than the ENET_QOS_RING_NUM_MAX(2). If the ringNum is set with
* 1, the ring 0 will be used.
*
* @note This must be called after all the ENET initialization.
* And should be called when the ENET receive/transmit is required.
*/
void ENET_QOS_StartRxTx(ENET_QOS_Type *base, uint8_t txRingNum, uint8_t rxRingNum);
/*! @} */
/*!
* @name MII interface operation
* @{
*/
/*!
* @brief Sets the ENET MII speed and duplex.
*
* This API is provided to dynamically change the speed and duplex for MAC.
*
* @param base ENET peripheral base address.
* @param speed The speed of the RMII mode.
* @param duplex The duplex of the RMII mode.
* @return kStatus_Success The ENET MII speed and duplex has been set successfully.
* @return kStatus_InvalidArgument Could not set the desired ENET MII speed and duplex combination.
*/
status_t ENET_QOS_SetMII(ENET_QOS_Type *base, enet_qos_mii_speed_t speed, enet_qos_mii_duplex_t duplex);
/*!
* @brief Sets the ENET SMI(serial management interface)- MII management interface.
*
* @param base ENET peripheral base address.
* @param csrClock_Hz CSR clock frequency in HZ
*/
void ENET_QOS_SetSMI(ENET_QOS_Type *base, uint32_t csrClock_Hz);
/*!
* @brief Checks if the SMI is busy.
*
* @param base ENET peripheral base address.
* @return The status of MII Busy status.
*/
static inline bool ENET_QOS_IsSMIBusy(ENET_QOS_Type *base)
{
return ((base->MAC_MDIO_ADDRESS & ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK) != 0U) ? true : false;
}
/*!
* @brief Reads data from the PHY register through SMI interface.
*
* @param base ENET peripheral base address.
* @return The data read from PHY
*/
static inline uint16_t ENET_QOS_ReadSMIData(ENET_QOS_Type *base)
{
return (uint16_t)(base->MAC_MDIO_DATA & ENET_QOS_MAC_MDIO_DATA_GD_MASK);
}
/*!
* @brief Sends the MDIO IEEE802.3 Clause 22 format write command.
* After send command, user needs to check whether the transmission is over
* with ENET_QOS_IsSMIBusy().
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param regAddr The PHY register address.
* @param data The data written to PHY.
*/
void ENET_QOS_StartSMIWrite(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data);
/*!
* @brief Sends the MDIO IEEE802.3 Clause 22 format read command.
* After send command, user needs to check whether the transmission is over
* with ENET_QOS_IsSMIBusy().
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param regAddr The PHY register address.
*/
void ENET_QOS_StartSMIRead(ENET_QOS_Type *base, uint8_t phyAddr, uint8_t regAddr);
/*!
* @brief Sends the MDIO IEEE802.3 Clause 45 format write command.
* After send command, user needs to check whether the transmission is over
* with ENET_QOS_IsSMIBusy().
*
* @param base ENET peripheral base address.
* @param portAddr The MDIO port address(PHY address).
* @param devAddr The device address.
* @param regAddr The PHY register address.
* @param data The data written to PHY.
*/
void ENET_QOS_StartExtC45SMIWrite(
ENET_QOS_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data);