From 8eb3cba30bf8e39a9ca395e11217052f8efbacd1 Mon Sep 17 00:00:00 2001 From: Jakub Zymelka Date: Mon, 25 Nov 2024 14:14:40 +0100 Subject: [PATCH] [nrf noup] drivers: pinctrl: Add SDP MSPI pin configuration Configure SDP MSPI pins to switch their control to VPR core Signed-off-by: Jakub Zymelka --- drivers/pinctrl/pinctrl_nrf.c | 29 +++++++++++++++++++ .../zephyr/dt-bindings/pinctrl/nrf-pinctrl.h | 28 ++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/drivers/pinctrl/pinctrl_nrf.c b/drivers/pinctrl/pinctrl_nrf.c index 1e80de8fe67..6fe7e3eaf73 100644 --- a/drivers/pinctrl/pinctrl_nrf.c +++ b/drivers/pinctrl/pinctrl_nrf.c @@ -94,6 +94,13 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = { #define NRF_PSEL_QSPI(reg, line) ((NRF_QSPI_Type *)reg)->PSEL.line #endif +#if defined(CONFIG_SOC_NRF54L15_CPUAPP) +#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) || defined(CONFIG_MSPI_NRFE) +#define NRF_PSEL_SDP_MSPI(psel) \ + nrf_gpio_pin_control_select(psel, NRF_GPIO_PIN_SEL_VPR); +#endif +#endif + int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) { @@ -347,6 +354,28 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, input = NRF_GPIO_PIN_INPUT_CONNECT; break; #endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_can) */ +#if defined(CONFIG_SOC_NRF54L15_CPUAPP) +#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) + case NRF_FUN_SDP_MSPI_CS0: + case NRF_FUN_SDP_MSPI_CS1: + case NRF_FUN_SDP_MSPI_CS2: + case NRF_FUN_SDP_MSPI_CS3: + case NRF_FUN_SDP_MSPI_CS4: + case NRF_FUN_SDP_MSPI_SCK: + case NRF_FUN_SDP_MSPI_DQ0: + case NRF_FUN_SDP_MSPI_DQ1: + case NRF_FUN_SDP_MSPI_DQ2: + case NRF_FUN_SDP_MSPI_DQ3: + case NRF_FUN_SDP_MSPI_DQ4: + case NRF_FUN_SDP_MSPI_DQ5: + case NRF_FUN_SDP_MSPI_DQ6: + case NRF_FUN_SDP_MSPI_DQ7: + NRF_PSEL_SDP_MSPI(psel); + dir = NRF_GPIO_PIN_DIR_OUTPUT; + input = NRF_GPIO_PIN_INPUT_CONNECT; + break; +#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) */ +#endif /* CONFIG_SOC_NRF54L15_CPUAPP */ default: return -ENOTSUP; } diff --git a/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h index 4611baef95c..9f2ab8632aa 100644 --- a/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h @@ -162,6 +162,34 @@ #define NRF_FUN_CAN_TX 46U /** CAN RX */ #define NRF_FUN_CAN_RX 47U +/** SDP_MSPI CK */ +#define NRF_FUN_SDP_MSPI_SCK 48U +/** SDP_MSPI DQ0 */ +#define NRF_FUN_SDP_MSPI_DQ0 49U +/** SDP_MSPI DQ1 */ +#define NRF_FUN_SDP_MSPI_DQ1 50U +/** SDP_MSPI DQ2 */ +#define NRF_FUN_SDP_MSPI_DQ2 51U +/** SDP_MSPI DQ3 */ +#define NRF_FUN_SDP_MSPI_DQ3 52U +/** SDP_MSPI DQ4 */ +#define NRF_FUN_SDP_MSPI_DQ4 53U +/** SDP_MSPI DQ5 */ +#define NRF_FUN_SDP_MSPI_DQ5 54U +/** SDP_MSPI DQ6 */ +#define NRF_FUN_SDP_MSPI_DQ6 55U +/** SDP_MSPI DQ7 */ +#define NRF_FUN_SDP_MSPI_DQ7 56U +/** SDP_MSPI CS0 */ +#define NRF_FUN_SDP_MSPI_CS0 57U +/** SDP_MSPI CS1 */ +#define NRF_FUN_SDP_MSPI_CS1 58U +/** SDP_MSPI CS2 */ +#define NRF_FUN_SDP_MSPI_CS2 59U +/** SDP_MSPI CS3 */ +#define NRF_FUN_SDP_MSPI_CS3 60U +/** SDP_MSPI CS4 */ +#define NRF_FUN_SDP_MSPI_CS4 61U /** @} */