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Wrong trace when multiple rear(multi position) cable. #16571

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joaolucasmacedo opened this issue Jun 14, 2024 · 3 comments
Closed

Wrong trace when multiple rear(multi position) cable. #16571

joaolucasmacedo opened this issue Jun 14, 2024 · 3 comments
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type: bug A confirmed report of unexpected behavior in the application

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@joaolucasmacedo
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joaolucasmacedo commented Jun 14, 2024

Deployment Type

Self-hosted

NetBox Version

v4.0.5

Python Version

3.10

Steps to Reproduce

  1. Create 2 devices with 2 module bays each. Each device is a fiber patch panel capable to accept fiber splice cassettes.
  2. Create a module type (a fiber cassette) with 1 rear port with 12 position (to represent a fiber cable splice for 12 fibers), and 12 front ports (to represent 6 LC connectors).
  3. Add 2 cassettes as modules on devices.
  4. Connect 2 cables on both rear ports on devices. As 2 12 fiber cables connecting 2 fiber patch panels.
  5. Connect any regular device's interface using one front (LC) port from one cassette and other from other cassette. Think if you need to use a pair of fibers to connect 2 switches thorough these 2 fiber patch panels but using different rear cables.

Expected Behavior

To trace the 2 interfaces properly.

Observed Behavior

It says "Asymmetric path!" showing a non related switch's interface.

See 2 fiber patch panels with 2 cassettes each, "DIO X1" and "DIO X2".
Each cassette gives a 12 position rear port and 12 LC front ports.
The patch panels are connected by 2 12 fiber cables on both cassettes.
image

Lets connect 2 switches, each on a different patch panel.
image

The image above shows a switch "SW X1A" interface connecting to 2 LC ports, and the switch on the other side is using the same ports on the other patch panel by the same interface "GigabitEthernet1/0/4".
image

The trace is not completed and the interfaces can't see each other.

image

Furthermore, if I use other single LC front port on each patch panel to connect interface "GigabitEthernet1/0/1" it show up on "Gi1/0/4" trace saying "Asymmetric Path!", and Gi1/0/1 is shown as Gi1/0/4 peer.

image

image

Is I delete the cables connecting both Gi1/0/1 interfaces and do the same with any other interfaces this last behavior does not show up.

@joaolucasmacedo joaolucasmacedo added status: needs triage This issue is awaiting triage by a maintainer type: bug A confirmed report of unexpected behavior in the application labels Jun 14, 2024
@arthanson arthanson added status: revisions needed This issue requires additional information to be actionable and removed status: needs triage This issue is awaiting triage by a maintainer labels Jun 17, 2024
@arthanson
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@joaolucasmacedo The repro is a bit hard to follow, so I'm not sure if doing exactly the same as you. If possible please make the repro steps as simple as possible, something like:

  1. Create Device "A1"
  2. Create Module "M1" on Device A1...

Below is what i think your repro is:

  • Create 1 Device Type
    • CommScope DIO
    • 2 rear ports (RP[1-2]
    • 24 front ports (FP[1-2]-[1-6][A-B])
  • Create 2 patch panel devices (DIO, named DIO X1 and DIO X2)
  • Connect DIO X1:RP1 to DIO X2:RP1 and DIO X1:RP2 to DIO X2:RP2
  • Create 2 switches (Name SW X1A and SW X2A
  • Connect SW X1A G1/0/1 to DIO X1:FP1-1A and DIO X1:FP2-1A
  • Connect SW X2A G1/0/1 to DIO X2:FP1-1A and DIO X2:FP2-1A
  • View the trace

The following was tested:
https://demo.netbox.dev/dcim/devices/126/interfaces/
https://demo.netbox.dev/dcim/devices/125/interfaces/
https://demo.netbox.dev/dcim/devices/123/
https://demo.netbox.dev/dcim/devices/124/
https://demo.netbox.dev/dcim/interfaces/1887/trace/

The trace looks good, I think so I'm not sure if you are doing something beyond that or special. Can you please double-check and if still encountering the issue try to post a simpler repro steps.

@joaolucasmacedo
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@arthanson I tested many scenarios and now I found it looks like a bug. I did the steps as you said and everything looks fine, but then I tried using modules rather than direct rear ports.
You can see at:
https://demo.netbox.dev/dcim/interfaces/928/trace/

Below is what i think the repro is:
Create 1 MODULE Type
Cassete G2 12fo 6 LC
1 rear port splice {module}
12 front ports (LC port - splice {module} - [1-6][A-B])
Create 2 patch panel devices (DIO, named DIO X1 and DIO X2) with 2 module bays (splice [1-2])
Add 2 modules to each patch panels
Connect DIO X1:splice 1 to DIO X2:splice 1 and DIO X1:splice 2 to DIO X2:splice 2
Create 2 switches (Name SW X1A and SW X2A)
Connect SW X1A G1/0/1 to DIO X1:"LC port - splice 1 - 1A" and DIO X1:"LC port - splice 1 - 1B"
Connect SW X2A G1/0/1 to DIO X2:"LC port - splice 1 - 1A" and DIO X2:"LC port - splice 1 - 1B"
View the trace
Now,
Connect SW X1A G1/0/2 to DIO X1:"LC port - splice 1 - 6B" and DIO X1:"LC port - splice 2 - 1A"
Connect SW X2A G1/0/2 to DIO X2:"LC port - splice 1 - 6B" and DIO X2:"LC port - splice 2 - 1A"

If it is not clear, please let me know.

image

@DanSheps
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Duplicate of #10602

@DanSheps DanSheps marked this as a duplicate of #10602 Jun 18, 2024
@DanSheps DanSheps closed this as not planned Won't fix, can't repro, duplicate, stale Jun 18, 2024
@DanSheps DanSheps removed the status: revisions needed This issue requires additional information to be actionable label Jun 18, 2024
@github-actions github-actions bot locked as resolved and limited conversation to collaborators Sep 17, 2024
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