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vivado_11960.backup.jou
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#-----------------------------------------------------------
# Vivado v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Tue Jul 10 14:13:38 2018
# Process ID: 11960
# Current directory: F:/LDR
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent10996 F:\LDR\LDR.xpr
# Log file: F:/LDR/vivado.log
# Journal file: F:/LDR\vivado.jou
#-----------------------------------------------------------
start_gui
open_project F:/LDR/LDR.xpr
update_compile_order -fileset sources_1
open_run synth_1 -name synth_1
reset_run synth_1
launch_runs synth_1 -jobs 2
wait_on_run synth_1
update_compile_order -fileset sources_1
set_property source_mgmt_mode DisplayOnly [current_project]
reset_run synth_1
launch_runs synth_1 -jobs 2
wait_on_run synth_1
open_run synth_1 -name synth_1
place_ports reset P15
save_constraints
reset_run synth_1
launch_runs synth_1 -jobs 2
wait_on_run synth_1
close_design
open_run synth_1 -name synth_1
startgroup
set_property package_pin "" [get_ports [list {keys[1]}]]
place_ports {keys[4]} R11
endgroup
startgroup
set_property package_pin "" [get_ports [list {keys[2]}]]
place_ports {keys[3]} V1
endgroup
startgroup
set_property package_pin "" [get_ports [list {keys[0]}]]
place_ports {keys[2]} R17
endgroup
place_ports {keys[1]} U4
place_ports {keys[0]} R15
place_ports {cs1[3]} G2
place_ports {cs1[2]} C2
place_ports {cs1[1]} C1
place_ports {cs1[0]} H1
place_ports {cs2[3]} G1
place_ports {cs2[2]} F1
place_ports {cs2[1]} E1
place_ports {cs2[0]} G6
place_ports {digit1[7]} B4
place_ports {digit1[6]} A4
place_ports {digit1[5]} A3
place_ports {digit1[4]} B1
place_ports {digit1[3]} A1
place_ports {digit1[2]} B3
place_ports {digit1[1]} B2
place_ports {digit1[0]} D5
place_ports {digit2[7]} D4
set_property package_pin "" [get_ports [list {digit2[6]}]]
place_ports {digit2[6]} E3
place_ports {digit2[5]} D3
place_ports {digit2[4]} F4
place_ports {digit2[3]} F3
place_ports {digit2[2]} E2
place_ports {digit2[1]} D2
place_ports {digit2[0]} H2
save_constraints
close_design
set_property -dict [list CONFIG.Coe_File {f:/LDR/LDR.srcs/sources_1/ip/dat_mem/test_ram.coe}] [get_ips dat_mem]
generate_target all [get_files F:/LDR/LDR.srcs/sources_1/ip/dat_mem/dat_mem.xci]
catch { config_ip_cache -export [get_ips -all dat_mem] }
export_ip_user_files -of_objects [get_files F:/LDR/LDR.srcs/sources_1/ip/dat_mem/dat_mem.xci] -no_script -sync -force -quiet
reset_run dat_mem_synth_1
launch_runs -jobs 2 dat_mem_synth_1
export_simulation -of_objects [get_files F:/LDR/LDR.srcs/sources_1/ip/dat_mem/dat_mem.xci] -directory F:/LDR/LDR.ip_user_files/sim_scripts -ip_user_files_dir F:/LDR/LDR.ip_user_files -ipstatic_source_dir F:/LDR/LDR.ip_user_files/ipstatic -lib_map_path [list {modelsim=F:/LDR/LDR.cache/compile_simlib/modelsim} {questa=F:/LDR/LDR.cache/compile_simlib/questa} {riviera=F:/LDR/LDR.cache/compile_simlib/riviera} {activehdl=F:/LDR/LDR.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
set_property -dict [list CONFIG.Coe_File {f:/LDR/LDR.srcs/sources_1/ip/ins_mem/test_rom.coe}] [get_ips ins_mem]
generate_target all [get_files F:/LDR/LDR.srcs/sources_1/ip/ins_mem/ins_mem.xci]
catch { config_ip_cache -export [get_ips -all ins_mem] }
export_ip_user_files -of_objects [get_files F:/LDR/LDR.srcs/sources_1/ip/ins_mem/ins_mem.xci] -no_script -sync -force -quiet
reset_run ins_mem_synth_1
launch_runs -jobs 2 ins_mem_synth_1
export_simulation -of_objects [get_files F:/LDR/LDR.srcs/sources_1/ip/ins_mem/ins_mem.xci] -directory F:/LDR/LDR.ip_user_files/sim_scripts -ip_user_files_dir F:/LDR/LDR.ip_user_files -ipstatic_source_dir F:/LDR/LDR.ip_user_files/ipstatic -lib_map_path [list {modelsim=F:/LDR/LDR.cache/compile_simlib/modelsim} {questa=F:/LDR/LDR.cache/compile_simlib/questa} {riviera=F:/LDR/LDR.cache/compile_simlib/riviera} {activehdl=F:/LDR/LDR.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 2
wait_on_run impl_1
open_run synth_1 -name synth_1
set_property IOSTANDARD LVCMOS33 [get_ports [list {keys[4]}]]
set_property IOSTANDARD LVCMOS33 [get_ports [list {cs1[3]} {cs1[2]} {cs1[1]} {cs1[0]}]]
set_property IOSTANDARD LVCMOS33 [get_ports [list {digit1[7]} {digit1[6]} {digit1[5]} {digit1[4]} {digit1[3]} {digit1[2]} {digit1[1]} {digit1[0]}]]
set_property IOSTANDARD LVCMOS25 [get_ports [list {cs2[3]} {cs2[2]} {cs2[1]} {cs2[0]}]]
set_property IOSTANDARD LVCMOS33 [get_ports [list {cs2[3]} {cs2[2]} {cs2[1]} {cs2[0]}]]
set_property IOSTANDARD LVCMOS33 [get_ports [list {digit2[7]} {digit2[6]} {digit2[5]} {digit2[4]} {digit2[3]} {digit2[2]} {digit2[1]} {digit2[0]}]]
save_constraints
reset_run impl_1
launch_runs impl_1 -jobs 2
wait_on_run impl_1
launch_runs impl_1 -to_step write_bitstream -jobs 2
wait_on_run impl_1
open_hw
close_hw
open_hw
connect_hw_server
open_hw_target
set_property PROGRAM.FILE {F:/LDR/LDR.runs/impl_1/computer.bit} [get_hw_devices xc7a35t_0]
current_hw_device [get_hw_devices xc7a35t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {F:/LDR/LDR.runs/impl_1/computer.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {F:/LDR/LDR.runs/impl_1/computer.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
close_hw
set_property -dict [list CONFIG.Coe_File {f:/LDR/LDR.srcs/sources_1/ip/ins_mem/test_rom.coe}] [get_ips ins_mem]
generate_target all [get_files F:/LDR/LDR.srcs/sources_1/ip/ins_mem/ins_mem.xci]
catch { config_ip_cache -export [get_ips -all ins_mem] }
export_ip_user_files -of_objects [get_files F:/LDR/LDR.srcs/sources_1/ip/ins_mem/ins_mem.xci] -no_script -sync -force -quiet
reset_run ins_mem_synth_1
launch_runs -jobs 2 ins_mem_synth_1
export_simulation -of_objects [get_files F:/LDR/LDR.srcs/sources_1/ip/ins_mem/ins_mem.xci] -directory F:/LDR/LDR.ip_user_files/sim_scripts -ip_user_files_dir F:/LDR/LDR.ip_user_files -ipstatic_source_dir F:/LDR/LDR.ip_user_files/ipstatic -lib_map_path [list {modelsim=F:/LDR/LDR.cache/compile_simlib/modelsim} {questa=F:/LDR/LDR.cache/compile_simlib/questa} {riviera=F:/LDR/LDR.cache/compile_simlib/riviera} {activehdl=F:/LDR/LDR.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
close_design
reset_run synth_1
launch_runs synth_1 -jobs 2
wait_on_run synth_1
launch_runs impl_1 -jobs 2
wait_on_run impl_1
launch_runs impl_1 -to_step write_bitstream -jobs 2
wait_on_run impl_1
open_hw
connect_hw_server
disconnect_hw_server localhost:3121
connect_hw_server
open_hw_target
set_property PROGRAM.FILE {F:/LDR/LDR.runs/impl_1/computer.bit} [get_hw_devices xc7a35t_0]
current_hw_device [get_hw_devices xc7a35t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {F:/LDR/LDR.runs/impl_1/computer.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
launch_simulation -simset mySim
close_hw
launch_simulation -simset mySim
launch_simulation -simset mySim
close_project
open_project F:/LDR/LDR.xpr
launch_simulation -simset mySim
launch_simulation -simset mySim
open_wave_config F:/LDR/LDR.srcs/mySim/imports/pingpong2/imme_lw_Rtype.wcfg
source computer_t.tcl
current_wave_config {imme_lw_Rtype.wcfg}
add_wave {{/computer_t/little_pc/mips_cpu/dp/Registers/register[1]}}
restart
run 10 us
run 10 us
save_wave_config {F:/LDR/LDR.srcs/mySim/imports/pingpong2/imme_lw_Rtype.wcfg}
close_sim
launch_simulation -simset mySim
open_wave_config F:/LDR/LDR.srcs/mySim/imports/pingpong2/imme_lw_Rtype.wcfg
source computer_t.tcl
run 10 us
current_wave_config {imme_lw_Rtype.wcfg}
add_wave {{/computer_t/little_pc/mips_cpu/dp/Registers/register[13]}}
restart
run 10 us
save_wave_config {F:/LDR/LDR.srcs/mySim/imports/pingpong2/imme_lw_Rtype.wcfg}
close_sim
set_property -dict [list CONFIG.Coe_File {f:/LDR/LDR.srcs/sources_1/ip/ins_mem/test_rom.coe}] [get_ips ins_mem]
generate_target all [get_files F:/LDR/LDR.srcs/sources_1/ip/ins_mem/ins_mem.xci]
catch { config_ip_cache -export [get_ips -all ins_mem] }
export_ip_user_files -of_objects [get_files F:/LDR/LDR.srcs/sources_1/ip/ins_mem/ins_mem.xci] -no_script -sync -force -quiet
reset_run ins_mem_synth_1
launch_runs -jobs 2 ins_mem_synth_1
export_simulation -of_objects [get_files F:/LDR/LDR.srcs/sources_1/ip/ins_mem/ins_mem.xci] -directory F:/LDR/LDR.ip_user_files/sim_scripts -ip_user_files_dir F:/LDR/LDR.ip_user_files -ipstatic_source_dir F:/LDR/LDR.ip_user_files/ipstatic -lib_map_path [list {modelsim=F:/LDR/LDR.cache/compile_simlib/modelsim} {questa=F:/LDR/LDR.cache/compile_simlib/questa} {riviera=F:/LDR/LDR.cache/compile_simlib/riviera} {activehdl=F:/LDR/LDR.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
launch_simulation -simset mySim
open_wave_config F:/LDR/LDR.srcs/mySim/imports/pingpong2/imme_lw_Rtype.wcfg
source computer_t.tcl
run 10 us
reset_run synth_1
launch_runs synth_1 -jobs 2
wait_on_run synth_1
close_sim
launch_runs impl_1 -jobs 2
wait_on_run impl_1
launch_runs impl_1 -to_step write_bitstream -jobs 2
wait_on_run impl_1
open_hw
connect_hw_server
disconnect_hw_server localhost:3121
connect_hw_server
open_hw_target
set_property PROGRAM.FILE {F:/LDR/LDR.runs/impl_1/computer.bit} [get_hw_devices xc7a35t_0]
current_hw_device [get_hw_devices xc7a35t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {F:/LDR/LDR.runs/impl_1/computer.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {F:/LDR/LDR.runs/impl_1/computer.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
close_hw
set_property -dict [list CONFIG.Coe_File {f:/LDR/LDR.srcs/sources_1/ip/ins_mem/test_rom.coe}] [get_ips ins_mem]
generate_target all [get_files F:/LDR/LDR.srcs/sources_1/ip/ins_mem/ins_mem.xci]
catch { config_ip_cache -export [get_ips -all ins_mem] }
export_ip_user_files -of_objects [get_files F:/LDR/LDR.srcs/sources_1/ip/ins_mem/ins_mem.xci] -no_script -sync -force -quiet
reset_run ins_mem_synth_1
launch_runs -jobs 2 ins_mem_synth_1
export_simulation -of_objects [get_files F:/LDR/LDR.srcs/sources_1/ip/ins_mem/ins_mem.xci] -directory F:/LDR/LDR.ip_user_files/sim_scripts -ip_user_files_dir F:/LDR/LDR.ip_user_files -ipstatic_source_dir F:/LDR/LDR.ip_user_files/ipstatic -lib_map_path [list {modelsim=F:/LDR/LDR.cache/compile_simlib/modelsim} {questa=F:/LDR/LDR.cache/compile_simlib/questa} {riviera=F:/LDR/LDR.cache/compile_simlib/riviera} {activehdl=F:/LDR/LDR.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
reset_run synth_1
launch_runs synth_1 -jobs 2
wait_on_run synth_1
launch_runs impl_1 -jobs 2
wait_on_run impl_1
launch_runs impl_1 -to_step write_bitstream -jobs 2
wait_on_run impl_1
open_hw
connect_hw_server
disconnect_hw_server localhost:3121
connect_hw_server
open_hw_target
set_property PROGRAM.FILE {F:/LDR/LDR.runs/impl_1/computer.bit} [get_hw_devices xc7a35t_0]
current_hw_device [get_hw_devices xc7a35t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
set_property PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0]
set_property PROGRAM.FILE {F:/LDR/LDR.runs/impl_1/computer.bit} [get_hw_devices xc7a35t_0]
program_hw_devices [get_hw_devices xc7a35t_0]
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
close_hw
launch_simulation -simset mySim
open_wave_config F:/LDR/LDR.srcs/mySim/imports/pingpong2/imme_lw_Rtype.wcfg
source computer_t.tcl
current_wave_config {imme_lw_Rtype.wcfg}
add_wave {{/computer_t/little_pc/mips_cpu/dp/Registers/register[16]}}
restart
run 10 us
current_wave_config {imme_lw_Rtype.wcfg}
add_wave {{/computer_t/little_pc/mc/keys}}
save_wave_config {F:/LDR/LDR.srcs/mySim/imports/pingpong2/imme_lw_Rtype.wcfg}
restart
run 10 us
run 10 us
run 10 us
run 10 us
run 10 us
run 10 us
run 10 us
close_sim