Sipeed Tang Primer 20K Lite Ext-Board

[multigcs]

In germany, on amazone there is a 'Sipeed Tang Primer 20K Lite Ext-Board' with 10% discount for €36,89:

https://www.amazon.de/gp/product/B0BYD47JRT/ref=ppx_yo_dt_b_asin_title_o00_s00?ie=UTF8&psc=1

thats cheaper then from aliexpress

i ordered one and try to support it

[multigcs]

Tang Primer 20K now supported in new oss-cad-suite :)

[TurBoss]

ordered one

Thank you!

:)

[multigcs]

oh, nooooo :)
i have problems with the programmer on one system, it's a little bit buggy.
and the free toolchain will not work correctly :(

[TurBoss]

don't worry :)

we will figure...

[multigcs]

I sent the main board back because it had a fault and ordered the one with network

now i can send the rio-message via UDP back to the host, but have to figure out how to receive the data on the FPGA,
it's very experimental and i don't think that i can port this to other FPGA's :(

[TurBoss]

Hello, just got nextpnr-gowin git and it worked, not the one from oss-cad-suite

🥳

[multigcs]

The UDP interface is working with linuxcnc now, but not so stable like the udp-bridges.
I have at times a hang of 1ms and do not know yet where it comes from.

[TurBoss]

Hello,

I just noticed that the board name is harcdcoded for tangnano9k here: https://github.com/multigcs/LinuxCNC-RIO/blob/main/generators/firmware/buildsys.py#L40

in my case i changed to

        makefile_data.append(f"	openFPGALoader -b {board.lower()} rio.fs -f")

i'll open a PR but not really sure if there is something else to check

thanks

[multigcs]

a3ff7a5

[TurBoss]

Thank you so much!

[TurBoss]

hello, finally I managed to upgrade the programer firmware

here are the steps i followed

# Gowin programer tang primer 20k lite

## riscv toolchain


https://github.com/riscv-collab/riscv-gnu-toolchain

./configure --prefix=/opt/riscv64 --enable-multilib --with-arch=rv64imafd

make linux -j11


## firmware

https://github.com/sipeed/RV-Debugger-BL702
https://github.com/cjacker/RV-Debugger-BL702/tree/fixbuild

make BOARD=bl702_debugger APP_DIR=../app APP=usb2uartjtag GOWIN_INT_FLASH_QUIRK=1

./bflb_mcu_tool --chipname=bl702 --port=/dev/ttyACM0 --xtal=32M --firmware="<path to firmware.bin>"


output:

tools\bflb_flash_tool> .\bflb_mcu_tool.exe --chipname=bl702 --port=COM9 --xtal=32M --firmware="main.bin"
[22:07:28.296] - ==================================================
[22:07:28.296] - Chip name is bl702
[22:07:28.297] - Serial port is COM9
[22:07:28.299] - Baudrate is 115200
[22:07:28.299] - Firmware is main.bin
[22:07:28.300] - Default flash clock is 72M
[22:07:28.300] - Default pll clock is 144M
[22:07:28.311] - ==================================================
[22:07:28.483] - Update flash cfg finished
[22:07:28.500] - EFUSE_CFG
[22:07:28.500] - BOOTHEADER_CFG
......
[22:07:31.274] - Load 53856/53856 {"progress":100}
[22:07:31.274] - Write check
[22:07:31.274] - Flash load time cost(ms): 267.942626953125
[22:07:31.275] - Finished
[22:07:31.276] - Sha caled by host: 825d198270c2cf509acda8f8e0830751c532da802060c324a4479e1fe599ae1f
[22:07:31.276] - xip mode Verify
[22:07:31.288] - Read Sha256/53856
[22:07:31.288] - Flash xip readsha time cost(ms): 12.508056640625
[22:07:31.288] - Finished
[22:07:31.288] - Sha caled by dev: 825d198270c2cf509acda8f8e0830751c532da802060c324a4479e1fe599ae1f
[22:07:31.288] - Verify success
[22:07:31.289] - Program Finished
[22:07:31.289] - All time cost(ms): 2220.2548828125
[22:07:31.390] - [All Success]

if not posible to build i attacht the binaries

the bflb_mcu_tool can be found in pypi pip install bflb_mcu_tool

usb2uartjtag.zip

:)
edit: added make instruction