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Floating-point extensions for RISC-V can specify rounding mode embedded in the instruction (like Intel's AVX-512). They could be faster than fesetround.
Floating-point extensions for RISC-V can specify rounding mode embedded in the instruction (like Intel's AVX-512). They could be faster than
fesetround
.The C code should be something like:
I'm not going to implement this right now, because I don't have a working GHC for RISC-V.
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