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Make use of static rounding mode on RISC-V #6

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minoki opened this issue Nov 18, 2023 · 0 comments
Open

Make use of static rounding mode on RISC-V #6

minoki opened this issue Nov 18, 2023 · 0 comments

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@minoki
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minoki commented Nov 18, 2023

Floating-point extensions for RISC-V can specify rounding mode embedded in the instruction (like Intel's AVX-512). They could be faster than fesetround.

The C code should be something like:

    // float
    asm("fadd.s %0, %1, %2, rne" : "=f"(result_ne) : "f"(x), "f"(y)); // roundTiesToEven
    asm("fadd.s %0, %1, %2, rmm" : "=f"(result_away) : "f"(x), "f"(y)); // roundTiesToAway
    asm("fadd.s %0, %1, %2, rup" : "=f"(result_up) : "f"(x), "f"(y)); // roundTowardPositive
    asm("fadd.s %0, %1, %2, rdn" : "=f"(result_down) : "f"(x), "f"(y)); // roundTowardNegative
    asm("fadd.s %0, %1, %2, rtz" : "=f"(result_zero) : "f"(x), "f"(y)); // roundTowardZero

    // double
    asm("fadd.d %0, %1, %2, rne" : "=f"(result_ne) : "f"(x), "f"(y)); // roundTiesToEven
    asm("fadd.d %0, %1, %2, rmm" : "=f"(result_away) : "f"(x), "f"(y)); // roundTiesToAway
    asm("fadd.d %0, %1, %2, rup" : "=f"(result_up) : "f"(x), "f"(y)); // roundTowardPositive
    asm("fadd.d %0, %1, %2, rdn" : "=f"(result_down) : "f"(x), "f"(y)); // roundTowardNegative
    asm("fadd.d %0, %1, %2, rtz" : "=f"(result_zero) : "f"(x), "f"(y)); // roundTowardZero

I'm not going to implement this right now, because I don't have a working GHC for RISC-V.

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