-
Notifications
You must be signed in to change notification settings - Fork 0
/
vivado.log
executable file
·576 lines (558 loc) · 47.7 KB
/
vivado.log
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Fri Apr 13 15:54:10 2018
# Process ID: 7632
# Current directory: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent16428 C:\Users\Wendy Li\Desktop\FPGA1\project\ENGN3213_Assignment1\Reaction_Timer_assignment1.xpr
# Log file: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/vivado.log
# Journal file: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1\vivado.jou
#-----------------------------------------------------------
start_gui
open_project {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.xpr}
INFO: [Project 1-313] Project file moved from 'C:/Users/Wendy Li/Desktop/FPGA1/project/Reaction_Timer_assignment1_git' since last save.
Scanning sources...
Finished scanning sources
WARNING: [filemgmt 56-2] IPUserFilesDir: Could not find the directory 'C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.ip_user_files', nor could it be found using path 'C:/Users/Wendy Li/Desktop/FPGA1/project/Reaction_Timer_assignment1_git/Reaction_Timer_assignment1.ip_user_files'.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'.
open_project: Time (s): cpu = 00:00:19 ; elapsed = 00:00:09 . Memory (MB): peak = 778.836 ; gain = 65.375
update_compile_order -fileset sources_1
WARNING: [filemgmt 20-1445] Cannot import file 'C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.srcs/sources_1/imports/sources/autoReset.v' on top of itself. Importing a file from the imported source directory can cause this problem.
import_files -norecurse {{C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.srcs/sources_1/imports/sources/autoReset.v}}
CRITICAL WARNING: [filemgmt 20-1445] Cannot import file 'C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.srcs/sources_1/imports/sources/autoReset.v' on top of itself. Importing a file from the imported source directory can cause this problem.
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 15:57:50 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 15:57:50 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2017.4
**** Build date : Dec 15 2017-21:08:27
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A6E6EFA
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
current_hw_device [get_hw_devices xc7a100t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210292A6E6EFA
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 16:08:02 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 16:08:02 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A6E6EFA
INFO: [Labtools 27-1435] Device xc7a100t (JTAG device index = 0) is not programmed (DONE status = 0).
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 16:16:28 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 16:16:28 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 16:24:13 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 16:24:13 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 16:25:50 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 16:25:50 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 16:36:09 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 16:36:09 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 16:46:30 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 16:46:30 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 16:53:59 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 16:53:59 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 16:58:11 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 16:58:11 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 17:04:10 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 17:04:10 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
open_run impl_1
INFO: [Common 17-41] Interrupt caught. Command should exit soon.
INFO: [Netlist 29-17] Analyzing 103 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
open_run: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1510.992 ; gain = 69.746
INFO: [Common 17-344] 'open_run' was cancelled
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 17:08:12 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 17:08:12 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210292A6E6EFA
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A6E6EFA
INFO: [Labtools 27-1435] Device xc7a100t (JTAG device index = 0) is not programmed (DONE status = 0).
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
close_hw
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 17:15:23 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 17:15:23 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2017.4
**** Build date : Dec 15 2017-21:08:27
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A6E6EFA
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
current_hw_device [get_hw_devices xc7a100t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 17:21:11 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 17:21:11 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210292A6E6EFA
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A6E6EFA
INFO: [Labtools 27-1435] Device xc7a100t (JTAG device index = 0) is not programmed (DONE status = 0).
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 17:32:21 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 17:32:21 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 17:38:06 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 17:38:06 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 17:49:28 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 17:49:28 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
close_hw
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 18:42:18 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 18:42:18 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2017.4
**** Build date : Dec 15 2017-21:08:27
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A6E6EFA
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
current_hw_device [get_hw_devices xc7a100t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
close_hw
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 18:55:38 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 18:55:38 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2017.4
**** Build date : Dec 15 2017-21:08:27
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A6E6EFA
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
current_hw_device [get_hw_devices xc7a100t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210292A6E6EFA
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A6E6EFA
INFO: [Labtools 27-1435] Device xc7a100t (JTAG device index = 0) is not programmed (DONE status = 0).
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
close_hw
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A6E6EFA
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
current_hw_device [get_hw_devices xc7a100t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
close_hw
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 19:07:37 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 19:07:37 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2017.4
**** Build date : Dec 15 2017-21:08:27
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A6E6EFA
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
current_hw_device [get_hw_devices xc7a100t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
close_hw
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Fri Apr 13 19:14:16 2018] Launched synth_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/synth_1/runme.log
[Fri Apr 13 19:14:16 2018] Launched impl_1...
Run output will be captured here: C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/runme.log
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2017.4
**** Build date : Dec 15 2017-21:08:27
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A6E6EFA
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
current_hw_device [get_hw_devices xc7a100t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {C:/Users/Wendy Li/Desktop/FPGA1/project/ENGN3213_Assignment1/Reaction_Timer_assignment1.runs/impl_1/reactionTimer_TOP.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
exit
INFO: [Common 17-206] Exiting Vivado at Fri Apr 13 19:18:10 2018...