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link.cfg
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platform=xilinx_u280_xdma_201920_3
debug=0
kernel_frequency=0:250
[connectivity]
nk=pw_advection:4:pw_advection_1.pw_advection_2.pw_advection_3.pw_advection_4
slr=pw_advection_1:SLR1
slr=pw_advection_2:SLR1
slr=pw_advection_3:SLR2
slr=pw_advection_4:SLR2
sp=pw_advection_1.u:DDR[0]
sp=pw_advection_1.v:DDR[0]
sp=pw_advection_1.w:DDR[0]
sp=pw_advection_1.su:DDR[0]
sp=pw_advection_1.sv:DDR[0]
sp=pw_advection_1.sw:DDR[0]
sp=pw_advection_1.m_axi_constants_port:DDR[0]
sp=pw_advection_2.u:DDR[0]
sp=pw_advection_2.v:DDR[0]
sp=pw_advection_2.w:DDR[0]
sp=pw_advection_2.su:DDR[0]
sp=pw_advection_2.sv:DDR[0]
sp=pw_advection_2.sw:DDR[0]
sp=pw_advection_2.m_axi_constants_port:DDR[0]
sp=pw_advection_3.u:DDR[1]
sp=pw_advection_3.v:DDR[1]
sp=pw_advection_3.w:DDR[1]
sp=pw_advection_3.su:DDR[1]
sp=pw_advection_3.sv:DDR[1]
sp=pw_advection_3.sw:DDR[1]
sp=pw_advection_3.m_axi_constants_port:DDR[1]
sp=pw_advection_4.u:DDR[1]
sp=pw_advection_4.v:DDR[1]
sp=pw_advection_4.w:DDR[1]
sp=pw_advection_4.su:DDR[1]
sp=pw_advection_4.sv:DDR[1]
sp=pw_advection_4.sw:DDR[1]
sp=pw_advection_4.m_axi_constants_port:DDR[1]