diff --git a/valgrind-tracer/generate-regs b/valgrind-tracer/generate-regs new file mode 100644 index 000000000..28c64cc1b --- /dev/null +++ b/valgrind-tracer/generate-regs @@ -0,0 +1,45 @@ +#!/usr/bin/env python3 +import os.path + +from clang.cindex import Index + + +def iter_subtree(node): + yield node + for child_node in node.get_children(): + yield from iter_subtree(child_node) + + +def find_struct_state(node): + for subtree_node in iter_subtree(node): + if subtree_node.spelling == "VexGuestArchState": + return subtree_node.type.get_canonical() + return None + + +def main(): + basedir = os.path.dirname(__file__) + valgrind = os.path.join(basedir, "..", "valgrind") + for arch in [ + "VGA_x86", + "VGA_amd64", + "VGA_ppc64be", + "VGA_ppc64le", + "VGA_arm", + "VGA_arm64", + "VGA_s390x", + ]: + print(f"#if defined({arch})") + index = Index.create() + tu = index.parse( + os.path.join(valgrind, "include", "pub_tool_guest.h"), + [f"-D{arch}", "-I" + os.path.join(valgrind, "VEX", "pub")], + ) + struct_state = find_struct_state(tu.cursor) + for field in struct_state.get_fields(): + print(f" DEFINE_REG({field.spelling}),") + print("#endif") + + +if __name__ == "__main__": + main() diff --git a/valgrind-tracer/mt_regs.h b/valgrind-tracer/mt_regs.h index 29f80b057..c95db8f71 100644 --- a/valgrind-tracer/mt_regs.h +++ b/valgrind-tracer/mt_regs.h @@ -207,6 +207,539 @@ static const struct Reg regs[] = { DEFINE_REG(guest_IP_AT_SYSCALL), DEFINE_REG(pad3), #endif +#if defined(VGA_ppc64be) + DEFINE_REG(host_EvC_FAILADDR), + DEFINE_REG(host_EvC_COUNTER), + DEFINE_REG(pad0), + DEFINE_REG(guest_GPR0), + DEFINE_REG(guest_GPR1), + DEFINE_REG(guest_GPR2), + DEFINE_REG(guest_GPR3), + DEFINE_REG(guest_GPR4), + DEFINE_REG(guest_GPR5), + DEFINE_REG(guest_GPR6), + DEFINE_REG(guest_GPR7), + DEFINE_REG(guest_GPR8), + DEFINE_REG(guest_GPR9), + DEFINE_REG(guest_GPR10), + DEFINE_REG(guest_GPR11), + DEFINE_REG(guest_GPR12), + DEFINE_REG(guest_GPR13), + DEFINE_REG(guest_GPR14), + DEFINE_REG(guest_GPR15), + DEFINE_REG(guest_GPR16), + DEFINE_REG(guest_GPR17), + DEFINE_REG(guest_GPR18), + DEFINE_REG(guest_GPR19), + DEFINE_REG(guest_GPR20), + DEFINE_REG(guest_GPR21), + DEFINE_REG(guest_GPR22), + DEFINE_REG(guest_GPR23), + DEFINE_REG(guest_GPR24), + DEFINE_REG(guest_GPR25), + DEFINE_REG(guest_GPR26), + DEFINE_REG(guest_GPR27), + DEFINE_REG(guest_GPR28), + DEFINE_REG(guest_GPR29), + DEFINE_REG(guest_GPR30), + DEFINE_REG(guest_GPR31), + DEFINE_REG(guest_VSR0), + DEFINE_REG(guest_VSR1), + DEFINE_REG(guest_VSR2), + DEFINE_REG(guest_VSR3), + DEFINE_REG(guest_VSR4), + DEFINE_REG(guest_VSR5), + DEFINE_REG(guest_VSR6), + DEFINE_REG(guest_VSR7), + DEFINE_REG(guest_VSR8), + DEFINE_REG(guest_VSR9), + DEFINE_REG(guest_VSR10), + DEFINE_REG(guest_VSR11), + DEFINE_REG(guest_VSR12), + DEFINE_REG(guest_VSR13), + DEFINE_REG(guest_VSR14), + DEFINE_REG(guest_VSR15), + DEFINE_REG(guest_VSR16), + DEFINE_REG(guest_VSR17), + DEFINE_REG(guest_VSR18), + DEFINE_REG(guest_VSR19), + DEFINE_REG(guest_VSR20), + DEFINE_REG(guest_VSR21), + DEFINE_REG(guest_VSR22), + DEFINE_REG(guest_VSR23), + DEFINE_REG(guest_VSR24), + DEFINE_REG(guest_VSR25), + DEFINE_REG(guest_VSR26), + DEFINE_REG(guest_VSR27), + DEFINE_REG(guest_VSR28), + DEFINE_REG(guest_VSR29), + DEFINE_REG(guest_VSR30), + DEFINE_REG(guest_VSR31), + DEFINE_REG(guest_VSR32), + DEFINE_REG(guest_VSR33), + DEFINE_REG(guest_VSR34), + DEFINE_REG(guest_VSR35), + DEFINE_REG(guest_VSR36), + DEFINE_REG(guest_VSR37), + DEFINE_REG(guest_VSR38), + DEFINE_REG(guest_VSR39), + DEFINE_REG(guest_VSR40), + DEFINE_REG(guest_VSR41), + DEFINE_REG(guest_VSR42), + DEFINE_REG(guest_VSR43), + DEFINE_REG(guest_VSR44), + DEFINE_REG(guest_VSR45), + DEFINE_REG(guest_VSR46), + DEFINE_REG(guest_VSR47), + DEFINE_REG(guest_VSR48), + DEFINE_REG(guest_VSR49), + DEFINE_REG(guest_VSR50), + DEFINE_REG(guest_VSR51), + DEFINE_REG(guest_VSR52), + DEFINE_REG(guest_VSR53), + DEFINE_REG(guest_VSR54), + DEFINE_REG(guest_VSR55), + DEFINE_REG(guest_VSR56), + DEFINE_REG(guest_VSR57), + DEFINE_REG(guest_VSR58), + DEFINE_REG(guest_VSR59), + DEFINE_REG(guest_VSR60), + DEFINE_REG(guest_VSR61), + DEFINE_REG(guest_VSR62), + DEFINE_REG(guest_VSR63), + DEFINE_REG(guest_CIA), + DEFINE_REG(guest_LR), + DEFINE_REG(guest_CTR), + DEFINE_REG(guest_XER_SO), + DEFINE_REG(guest_XER_OV), + DEFINE_REG(guest_XER_OV32), + DEFINE_REG(guest_XER_CA), + DEFINE_REG(guest_XER_CA32), + DEFINE_REG(guest_XER_BC), + DEFINE_REG(guest_CR0_321), + DEFINE_REG(guest_CR0_0), + DEFINE_REG(guest_CR1_321), + DEFINE_REG(guest_CR1_0), + DEFINE_REG(guest_CR2_321), + DEFINE_REG(guest_CR2_0), + DEFINE_REG(guest_CR3_321), + DEFINE_REG(guest_CR3_0), + DEFINE_REG(guest_CR4_321), + DEFINE_REG(guest_CR4_0), + DEFINE_REG(guest_CR5_321), + DEFINE_REG(guest_CR5_0), + DEFINE_REG(guest_CR6_321), + DEFINE_REG(guest_CR6_0), + DEFINE_REG(guest_CR7_321), + DEFINE_REG(guest_CR7_0), + DEFINE_REG(guest_FPROUND), + DEFINE_REG(guest_DFPROUND), + DEFINE_REG(guest_C_FPCC), + DEFINE_REG(pad2), + DEFINE_REG(pad3), + DEFINE_REG(pad4), + DEFINE_REG(guest_VRSAVE), + DEFINE_REG(guest_VSCR), + DEFINE_REG(guest_EMNOTE), + DEFINE_REG(padding), + DEFINE_REG(guest_CMSTART), + DEFINE_REG(guest_CMLEN), + DEFINE_REG(guest_NRADDR), + DEFINE_REG(guest_NRADDR_GPR2), + DEFINE_REG(guest_REDIR_SP), + DEFINE_REG(guest_REDIR_STACK), + DEFINE_REG(guest_IP_AT_SYSCALL), + DEFINE_REG(guest_SPRG3_RO), + DEFINE_REG(guest_TFHAR), + DEFINE_REG(guest_TEXASR), + DEFINE_REG(guest_TFIAR), + DEFINE_REG(guest_PPR), + DEFINE_REG(guest_TEXASRU), + DEFINE_REG(guest_PSPB), + DEFINE_REG(guest_DSCR), + DEFINE_REG(guest_ACC_0_r0), + DEFINE_REG(guest_ACC_0_r1), + DEFINE_REG(guest_ACC_0_r2), + DEFINE_REG(guest_ACC_0_r3), + DEFINE_REG(guest_ACC_1_r0), + DEFINE_REG(guest_ACC_1_r1), + DEFINE_REG(guest_ACC_1_r2), + DEFINE_REG(guest_ACC_1_r3), + DEFINE_REG(guest_ACC_2_r0), + DEFINE_REG(guest_ACC_2_r1), + DEFINE_REG(guest_ACC_2_r2), + DEFINE_REG(guest_ACC_2_r3), + DEFINE_REG(guest_ACC_3_r0), + DEFINE_REG(guest_ACC_3_r1), + DEFINE_REG(guest_ACC_3_r2), + DEFINE_REG(guest_ACC_3_r3), + DEFINE_REG(guest_ACC_4_r0), + DEFINE_REG(guest_ACC_4_r1), + DEFINE_REG(guest_ACC_4_r2), + DEFINE_REG(guest_ACC_4_r3), + DEFINE_REG(guest_ACC_5_r0), + DEFINE_REG(guest_ACC_5_r1), + DEFINE_REG(guest_ACC_5_r2), + DEFINE_REG(guest_ACC_5_r3), + DEFINE_REG(guest_ACC_6_r0), + DEFINE_REG(guest_ACC_6_r1), + DEFINE_REG(guest_ACC_6_r2), + DEFINE_REG(guest_ACC_6_r3), + DEFINE_REG(guest_ACC_7_r0), + DEFINE_REG(guest_ACC_7_r1), + DEFINE_REG(guest_ACC_7_r2), + DEFINE_REG(guest_ACC_7_r3), + DEFINE_REG(guest_syscall_flag), + DEFINE_REG(padding1), + DEFINE_REG(padding2), + DEFINE_REG(padding3), +#endif +#if defined(VGA_ppc64le) + DEFINE_REG(host_EvC_FAILADDR), + DEFINE_REG(host_EvC_COUNTER), + DEFINE_REG(pad0), + DEFINE_REG(guest_GPR0), + DEFINE_REG(guest_GPR1), + DEFINE_REG(guest_GPR2), + DEFINE_REG(guest_GPR3), + DEFINE_REG(guest_GPR4), + DEFINE_REG(guest_GPR5), + DEFINE_REG(guest_GPR6), + DEFINE_REG(guest_GPR7), + DEFINE_REG(guest_GPR8), + DEFINE_REG(guest_GPR9), + DEFINE_REG(guest_GPR10), + DEFINE_REG(guest_GPR11), + DEFINE_REG(guest_GPR12), + DEFINE_REG(guest_GPR13), + DEFINE_REG(guest_GPR14), + DEFINE_REG(guest_GPR15), + DEFINE_REG(guest_GPR16), + DEFINE_REG(guest_GPR17), + DEFINE_REG(guest_GPR18), + DEFINE_REG(guest_GPR19), + DEFINE_REG(guest_GPR20), + DEFINE_REG(guest_GPR21), + DEFINE_REG(guest_GPR22), + DEFINE_REG(guest_GPR23), + DEFINE_REG(guest_GPR24), + DEFINE_REG(guest_GPR25), + DEFINE_REG(guest_GPR26), + DEFINE_REG(guest_GPR27), + DEFINE_REG(guest_GPR28), + DEFINE_REG(guest_GPR29), + DEFINE_REG(guest_GPR30), + DEFINE_REG(guest_GPR31), + DEFINE_REG(guest_VSR0), + DEFINE_REG(guest_VSR1), + DEFINE_REG(guest_VSR2), + DEFINE_REG(guest_VSR3), + DEFINE_REG(guest_VSR4), + DEFINE_REG(guest_VSR5), + DEFINE_REG(guest_VSR6), + DEFINE_REG(guest_VSR7), + DEFINE_REG(guest_VSR8), + DEFINE_REG(guest_VSR9), + DEFINE_REG(guest_VSR10), + DEFINE_REG(guest_VSR11), + DEFINE_REG(guest_VSR12), + DEFINE_REG(guest_VSR13), + DEFINE_REG(guest_VSR14), + DEFINE_REG(guest_VSR15), + DEFINE_REG(guest_VSR16), + DEFINE_REG(guest_VSR17), + DEFINE_REG(guest_VSR18), + DEFINE_REG(guest_VSR19), + DEFINE_REG(guest_VSR20), + DEFINE_REG(guest_VSR21), + DEFINE_REG(guest_VSR22), + DEFINE_REG(guest_VSR23), + DEFINE_REG(guest_VSR24), + DEFINE_REG(guest_VSR25), + DEFINE_REG(guest_VSR26), + DEFINE_REG(guest_VSR27), + DEFINE_REG(guest_VSR28), + DEFINE_REG(guest_VSR29), + DEFINE_REG(guest_VSR30), + DEFINE_REG(guest_VSR31), + DEFINE_REG(guest_VSR32), + DEFINE_REG(guest_VSR33), + DEFINE_REG(guest_VSR34), + DEFINE_REG(guest_VSR35), + DEFINE_REG(guest_VSR36), + DEFINE_REG(guest_VSR37), + DEFINE_REG(guest_VSR38), + DEFINE_REG(guest_VSR39), + DEFINE_REG(guest_VSR40), + DEFINE_REG(guest_VSR41), + DEFINE_REG(guest_VSR42), + DEFINE_REG(guest_VSR43), + DEFINE_REG(guest_VSR44), + DEFINE_REG(guest_VSR45), + DEFINE_REG(guest_VSR46), + DEFINE_REG(guest_VSR47), + DEFINE_REG(guest_VSR48), + DEFINE_REG(guest_VSR49), + DEFINE_REG(guest_VSR50), + DEFINE_REG(guest_VSR51), + DEFINE_REG(guest_VSR52), + DEFINE_REG(guest_VSR53), + DEFINE_REG(guest_VSR54), + DEFINE_REG(guest_VSR55), + DEFINE_REG(guest_VSR56), + DEFINE_REG(guest_VSR57), + DEFINE_REG(guest_VSR58), + DEFINE_REG(guest_VSR59), + DEFINE_REG(guest_VSR60), + DEFINE_REG(guest_VSR61), + DEFINE_REG(guest_VSR62), + DEFINE_REG(guest_VSR63), + DEFINE_REG(guest_CIA), + DEFINE_REG(guest_LR), + DEFINE_REG(guest_CTR), + DEFINE_REG(guest_XER_SO), + DEFINE_REG(guest_XER_OV), + DEFINE_REG(guest_XER_OV32), + DEFINE_REG(guest_XER_CA), + DEFINE_REG(guest_XER_CA32), + DEFINE_REG(guest_XER_BC), + DEFINE_REG(guest_CR0_321), + DEFINE_REG(guest_CR0_0), + DEFINE_REG(guest_CR1_321), + DEFINE_REG(guest_CR1_0), + DEFINE_REG(guest_CR2_321), + DEFINE_REG(guest_CR2_0), + DEFINE_REG(guest_CR3_321), + DEFINE_REG(guest_CR3_0), + DEFINE_REG(guest_CR4_321), + DEFINE_REG(guest_CR4_0), + DEFINE_REG(guest_CR5_321), + DEFINE_REG(guest_CR5_0), + DEFINE_REG(guest_CR6_321), + DEFINE_REG(guest_CR6_0), + DEFINE_REG(guest_CR7_321), + DEFINE_REG(guest_CR7_0), + DEFINE_REG(guest_FPROUND), + DEFINE_REG(guest_DFPROUND), + DEFINE_REG(guest_C_FPCC), + DEFINE_REG(pad2), + DEFINE_REG(pad3), + DEFINE_REG(pad4), + DEFINE_REG(guest_VRSAVE), + DEFINE_REG(guest_VSCR), + DEFINE_REG(guest_EMNOTE), + DEFINE_REG(padding), + DEFINE_REG(guest_CMSTART), + DEFINE_REG(guest_CMLEN), + DEFINE_REG(guest_NRADDR), + DEFINE_REG(guest_NRADDR_GPR2), + DEFINE_REG(guest_REDIR_SP), + DEFINE_REG(guest_REDIR_STACK), + DEFINE_REG(guest_IP_AT_SYSCALL), + DEFINE_REG(guest_SPRG3_RO), + DEFINE_REG(guest_TFHAR), + DEFINE_REG(guest_TEXASR), + DEFINE_REG(guest_TFIAR), + DEFINE_REG(guest_PPR), + DEFINE_REG(guest_TEXASRU), + DEFINE_REG(guest_PSPB), + DEFINE_REG(guest_DSCR), + DEFINE_REG(guest_ACC_0_r0), + DEFINE_REG(guest_ACC_0_r1), + DEFINE_REG(guest_ACC_0_r2), + DEFINE_REG(guest_ACC_0_r3), + DEFINE_REG(guest_ACC_1_r0), + DEFINE_REG(guest_ACC_1_r1), + DEFINE_REG(guest_ACC_1_r2), + DEFINE_REG(guest_ACC_1_r3), + DEFINE_REG(guest_ACC_2_r0), + DEFINE_REG(guest_ACC_2_r1), + DEFINE_REG(guest_ACC_2_r2), + DEFINE_REG(guest_ACC_2_r3), + DEFINE_REG(guest_ACC_3_r0), + DEFINE_REG(guest_ACC_3_r1), + DEFINE_REG(guest_ACC_3_r2), + DEFINE_REG(guest_ACC_3_r3), + DEFINE_REG(guest_ACC_4_r0), + DEFINE_REG(guest_ACC_4_r1), + DEFINE_REG(guest_ACC_4_r2), + DEFINE_REG(guest_ACC_4_r3), + DEFINE_REG(guest_ACC_5_r0), + DEFINE_REG(guest_ACC_5_r1), + DEFINE_REG(guest_ACC_5_r2), + DEFINE_REG(guest_ACC_5_r3), + DEFINE_REG(guest_ACC_6_r0), + DEFINE_REG(guest_ACC_6_r1), + DEFINE_REG(guest_ACC_6_r2), + DEFINE_REG(guest_ACC_6_r3), + DEFINE_REG(guest_ACC_7_r0), + DEFINE_REG(guest_ACC_7_r1), + DEFINE_REG(guest_ACC_7_r2), + DEFINE_REG(guest_ACC_7_r3), + DEFINE_REG(guest_syscall_flag), + DEFINE_REG(padding1), + DEFINE_REG(padding2), + DEFINE_REG(padding3), +#endif +#if defined(VGA_arm) + DEFINE_REG(host_EvC_FAILADDR), + DEFINE_REG(host_EvC_COUNTER), + DEFINE_REG(guest_R0), + DEFINE_REG(guest_R1), + DEFINE_REG(guest_R2), + DEFINE_REG(guest_R3), + DEFINE_REG(guest_R4), + DEFINE_REG(guest_R5), + DEFINE_REG(guest_R6), + DEFINE_REG(guest_R7), + DEFINE_REG(guest_R8), + DEFINE_REG(guest_R9), + DEFINE_REG(guest_R10), + DEFINE_REG(guest_R11), + DEFINE_REG(guest_R12), + DEFINE_REG(guest_R13), + DEFINE_REG(guest_R14), + DEFINE_REG(guest_R15T), + DEFINE_REG(guest_CC_OP), + DEFINE_REG(guest_CC_DEP1), + DEFINE_REG(guest_CC_DEP2), + DEFINE_REG(guest_CC_NDEP), + DEFINE_REG(guest_QFLAG32), + DEFINE_REG(guest_GEFLAG0), + DEFINE_REG(guest_GEFLAG1), + DEFINE_REG(guest_GEFLAG2), + DEFINE_REG(guest_GEFLAG3), + DEFINE_REG(guest_EMNOTE), + DEFINE_REG(guest_CMSTART), + DEFINE_REG(guest_CMLEN), + DEFINE_REG(guest_NRADDR), + DEFINE_REG(guest_IP_AT_SYSCALL), + DEFINE_REG(guest_D0), + DEFINE_REG(guest_D1), + DEFINE_REG(guest_D2), + DEFINE_REG(guest_D3), + DEFINE_REG(guest_D4), + DEFINE_REG(guest_D5), + DEFINE_REG(guest_D6), + DEFINE_REG(guest_D7), + DEFINE_REG(guest_D8), + DEFINE_REG(guest_D9), + DEFINE_REG(guest_D10), + DEFINE_REG(guest_D11), + DEFINE_REG(guest_D12), + DEFINE_REG(guest_D13), + DEFINE_REG(guest_D14), + DEFINE_REG(guest_D15), + DEFINE_REG(guest_D16), + DEFINE_REG(guest_D17), + DEFINE_REG(guest_D18), + DEFINE_REG(guest_D19), + DEFINE_REG(guest_D20), + DEFINE_REG(guest_D21), + DEFINE_REG(guest_D22), + DEFINE_REG(guest_D23), + DEFINE_REG(guest_D24), + DEFINE_REG(guest_D25), + DEFINE_REG(guest_D26), + DEFINE_REG(guest_D27), + DEFINE_REG(guest_D28), + DEFINE_REG(guest_D29), + DEFINE_REG(guest_D30), + DEFINE_REG(guest_D31), + DEFINE_REG(guest_FPSCR), + DEFINE_REG(guest_TPIDRURO), + DEFINE_REG(guest_TPIDRURW), + DEFINE_REG(guest_ITSTATE), +#endif +#if defined(VGA_arm64) + DEFINE_REG(host_EvC_FAILADDR), + DEFINE_REG(host_EvC_COUNTER), + DEFINE_REG(pad0), + DEFINE_REG(guest_X0), + DEFINE_REG(guest_X1), + DEFINE_REG(guest_X2), + DEFINE_REG(guest_X3), + DEFINE_REG(guest_X4), + DEFINE_REG(guest_X5), + DEFINE_REG(guest_X6), + DEFINE_REG(guest_X7), + DEFINE_REG(guest_X8), + DEFINE_REG(guest_X9), + DEFINE_REG(guest_X10), + DEFINE_REG(guest_X11), + DEFINE_REG(guest_X12), + DEFINE_REG(guest_X13), + DEFINE_REG(guest_X14), + DEFINE_REG(guest_X15), + DEFINE_REG(guest_X16), + DEFINE_REG(guest_X17), + DEFINE_REG(guest_X18), + DEFINE_REG(guest_X19), + DEFINE_REG(guest_X20), + DEFINE_REG(guest_X21), + DEFINE_REG(guest_X22), + DEFINE_REG(guest_X23), + DEFINE_REG(guest_X24), + DEFINE_REG(guest_X25), + DEFINE_REG(guest_X26), + DEFINE_REG(guest_X27), + DEFINE_REG(guest_X28), + DEFINE_REG(guest_X29), + DEFINE_REG(guest_X30), + DEFINE_REG(guest_XSP), + DEFINE_REG(guest_PC), + DEFINE_REG(guest_CC_OP), + DEFINE_REG(guest_CC_DEP1), + DEFINE_REG(guest_CC_DEP2), + DEFINE_REG(guest_CC_NDEP), + DEFINE_REG(guest_TPIDR_EL0), + DEFINE_REG(guest_Q0), + DEFINE_REG(guest_Q1), + DEFINE_REG(guest_Q2), + DEFINE_REG(guest_Q3), + DEFINE_REG(guest_Q4), + DEFINE_REG(guest_Q5), + DEFINE_REG(guest_Q6), + DEFINE_REG(guest_Q7), + DEFINE_REG(guest_Q8), + DEFINE_REG(guest_Q9), + DEFINE_REG(guest_Q10), + DEFINE_REG(guest_Q11), + DEFINE_REG(guest_Q12), + DEFINE_REG(guest_Q13), + DEFINE_REG(guest_Q14), + DEFINE_REG(guest_Q15), + DEFINE_REG(guest_Q16), + DEFINE_REG(guest_Q17), + DEFINE_REG(guest_Q18), + DEFINE_REG(guest_Q19), + DEFINE_REG(guest_Q20), + DEFINE_REG(guest_Q21), + DEFINE_REG(guest_Q22), + DEFINE_REG(guest_Q23), + DEFINE_REG(guest_Q24), + DEFINE_REG(guest_Q25), + DEFINE_REG(guest_Q26), + DEFINE_REG(guest_Q27), + DEFINE_REG(guest_Q28), + DEFINE_REG(guest_Q29), + DEFINE_REG(guest_Q30), + DEFINE_REG(guest_Q31), + DEFINE_REG(guest_QCFLAG), + DEFINE_REG(guest_EMNOTE), + DEFINE_REG(guest_CMSTART), + DEFINE_REG(guest_CMLEN), + DEFINE_REG(guest_NRADDR), + DEFINE_REG(guest_IP_AT_SYSCALL), + DEFINE_REG(guest_FPCR), + DEFINE_REG(guest_LLSC_SIZE), + DEFINE_REG(guest_LLSC_ADDR), + DEFINE_REG(guest_LLSC_DATA_LO64), + DEFINE_REG(guest_LLSC_DATA_HI64), + DEFINE_REG(guest_SC_CLASS), + DEFINE_REG(guest_SETC), + DEFINE_REG(pad_end_0), +#endif #if defined(VGA_s390x) DEFINE_REG(guest_a0), DEFINE_REG(guest_a1),