Automatic definition of false path constraints

[whitequark]

In oMigen, there is some code that adds false path constraints on MultiReg and AsyncResetSynchronizer automatically. Unfortunately it looks like it is only designed to work properly with Xilinx; the relevant code for every other platform seems to be blindly copied from the Xilinx file and as far as I can tell it has never worked in any meaningful way.

This needs to be replicated in nMigen, and that requires carefully investigating the data toolchains require to add false path constraints.

[whitequark]

Good documentation on synchronizers: #227 (comment)

[whitequark]

Implemented for Vivado in #227.

[whitequark]

AFAIU, ISE and Diamond do not consider all clocks related by default. So, there is no need to automatically define false path constraints in these toolchains; although one might need to manually add false path constraints for clocks that go through PLLs, etc.