diff --git a/hw/ip/otp_ctrl/data/otp_ctrl_img_rma.hjson b/hw/ip/otp_ctrl/data/otp_ctrl_img_rma.hjson new file mode 100644 index 0000000000000..81c9f30c3d840 --- /dev/null +++ b/hw/ip/otp_ctrl/data/otp_ctrl_img_rma.hjson @@ -0,0 +1,118 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Use the gen-otp-img.py script to convert this configuration into +// a hex file for preloading the OTP in FPGA synthesis or simulation. +// + +{ + // Seed to be used for generation of partition randomized values. + // Can be overridden on the command line with the --seed switch. + seed: 01931961561863975174 + + // The partition and item names must correspond with the OTP memory map. + partitions: [ + { + name: "CREATOR_SW_CFG", + items: [ + { + name: "CREATOR_SW_CFG_CONTENT", + value: "0x0", + } + { + name: "CREATOR_SW_CFG_DIGEST", + value: "0x0", + } + ], + } + { + name: "OWNER_SW_CFG", + items: [ + { + name: "OWNER_SW_CFG_CONTENT", + value: "0x0" + } + { + name: "OWNER_SW_CFG_DIGEST", + value: "0x0", + } + ], + } + { + name: "HW_CFG", + // If set to true, this computes the HW digest value + // and locks the partition. + lock: "True", + items: [ + { + name: "DEVICE_ID", + value: "", + }, + { + name: "EN_ENTROPY_SRC_FW_READ", + value: "0xA5", + }, + ], + } + { + name: "SECRET0", + lock: "True", + items: [ + { + name: "TEST_UNLOCK_TOKEN", + value: "", + } + { + name: "TEST_EXIT_TOKEN", + value: "", + } + ], + } + { + name: "SECRET1", + lock: "True", + items: [ + { + name: "FLASH_ADDR_KEY_SEED", + value: "", + } + { + name: "FLASH_DATA_KEY_SEED", + value: "", + } + { + name: "SRAM_DATA_KEY_SEED", + value: "", + } + ], + } + { + name: "SECRET2", + lock: "False", + items: [ + { + name: "RMA_TOKEN", + value: "", + } + { + name: "CREATOR_ROOT_KEY_SHARE0", + value: "", + } + { + name: "CREATOR_ROOT_KEY_SHARE1", + value: "", + } + ], + } + { + name: "LIFE_CYCLE", + // Can be one of the following strings: + // RAW, TEST_UNLOCKED0-3, TEST_LOCKED0-2, DEV, PROD, PROD_END, RMA, SCRAP + state: "RMA", + // Can range from 0 to 16. + // Note that a value of 0 is only permissible in RAW state. + count: "8" + } + ] +} diff --git a/hw/ip/pinmux/rtl/pinmux_pkg.sv b/hw/ip/pinmux/rtl/pinmux_pkg.sv index eaed12963e738..aefa27937190f 100644 --- a/hw/ip/pinmux/rtl/pinmux_pkg.sv +++ b/hw/ip/pinmux/rtl/pinmux_pkg.sv @@ -16,8 +16,6 @@ package pinmux_pkg; // datastructure below serves this purpose. Note that all the indices below are with respect to // the concatenated {DIO, MIO} packed array. typedef struct packed { - logic const_sampling; // TODO: check whether this can be eliminated. - logic [NumIOs-1:0] tie_offs; // TODO: check whether this can be eliminated. integer tck_idx; integer tms_idx; integer trst_idx; @@ -36,8 +34,6 @@ package pinmux_pkg; } target_cfg_t; parameter target_cfg_t DefaultTargetCfg = '{ - const_sampling: 1'b0, - tie_offs: '0, tck_idx: 0, tms_idx: 0, trst_idx: 0, @@ -51,8 +47,8 @@ package pinmux_pkg; usb_dn_idx: 0, usb_dp_pullup_idx: 0, usb_dn_pullup_idx: 0, - dio_pad_type: {NDioPads{BidirStd}}, - mio_pad_type: {NMioPads{BidirStd}} + dio_pad_type: {NDioPads{BidirStd}}, + mio_pad_type: {NMioPads{BidirStd}} }; // Wakeup Detector Modes diff --git a/hw/ip/pinmux/rtl/pinmux_strap_sampling.sv b/hw/ip/pinmux/rtl/pinmux_strap_sampling.sv index 949ecf54593e3..34499c0ffbce8 100644 --- a/hw/ip/pinmux/rtl/pinmux_strap_sampling.sv +++ b/hw/ip/pinmux/rtl/pinmux_strap_sampling.sv @@ -76,12 +76,10 @@ module pinmux_strap_sampling // Strap Sampling Logic // ////////////////////////// - logic strap_en_q; logic dft_strap_valid_d, dft_strap_valid_q; logic lc_strap_sample_en, rv_strap_sample_en, dft_strap_sample_en; logic [NTapStraps-1:0] tap_strap_d, tap_strap_q; logic [NDFTStraps-1:0] dft_strap_d, dft_strap_q; - lc_ctrl_pkg::lc_tx_e continue_sampling_d, continue_sampling_q; // The LC strap at index 0 has a slightly different // enable condition than the DFT strap at index 1. @@ -104,11 +102,12 @@ module pinmux_strap_sampling lc_strap_sample_en = 1'b0; rv_strap_sample_en = 1'b0; dft_strap_sample_en = 1'b0; - continue_sampling_d = continue_sampling_q; // Initial strap sampling pulse from pwrmgr, // qualified by life cycle signals. - if (strap_en_i || continue_sampling_q == lc_ctrl_pkg::On) begin + // In DFT-enabled life cycle states we continously + // sample all straps. + if (strap_en_i || lc_dft_en[0] == lc_ctrl_pkg::On) begin lc_strap_sample_en = 1'b1; if (lc_hw_debug_en[0] == lc_ctrl_pkg::On) begin rv_strap_sample_en = 1'b1; @@ -117,38 +116,17 @@ module pinmux_strap_sampling dft_strap_sample_en = 1'b1; end end - - // In case DFT is enabled, and in case the TAP straps - // where not set to functional mode upon the first - // sampling event, we continue sampling all straps - // until system reset. This is used during the - // DFT-enabled life cycle states only. - if (lc_dft_en[0] == lc_ctrl_pkg::On) begin - if (strap_en_q && - tap_strap_t'(tap_strap_q) != FuncSel) begin - continue_sampling_d = lc_ctrl_pkg::On; - end - end - // TODO: this can currently be overridden with a parameter for legacy reasons. - // This parameter will be removed in the future. - if (TargetCfg.const_sampling) begin - continue_sampling_d = lc_ctrl_pkg::On; - end end always_ff @(posedge clk_i or negedge rst_ni) begin : p_strap_sample if (!rst_ni) begin tap_strap_q <= '0; dft_strap_q <= '0; - strap_en_q <= 1'b0; dft_strap_valid_q <= 1'b0; - continue_sampling_q <= lc_ctrl_pkg::Off; end else begin tap_strap_q <= tap_strap_d; dft_strap_q <= dft_strap_d; - strap_en_q <= strap_en_i; dft_strap_valid_q <= dft_strap_valid_d; - continue_sampling_q <= continue_sampling_d; end end @@ -250,7 +228,7 @@ module pinmux_strap_sampling k == TargetCfg.trst_idx || k == TargetCfg.tdi_idx || k == TargetCfg.tdo_idx) begin : gen_jtag_signal - assign in_core_o[k] = (jtag_en) ? TargetCfg.tie_offs[k] : in_padring_i[k]; + assign in_core_o[k] = (jtag_en) ? 1'b0 : in_padring_i[k]; end else begin : gen_other_inputs assign in_core_o[k] = in_padring_i[k]; end diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv index 9c69c34dab0fa..6737a59e7b52c 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv @@ -101,16 +101,8 @@ module chip_earlgrey_asic ( parameter int TdiPadIdx = 37; parameter int TdoPadIdx = 36; - // TODO: this is temporary and will be removed in the future. - // This specifies the tie-off values of the muxed MIO/DIOs - // when the JTAG is active. SPI CSB is active low. - localparam logic [pinmux_pkg::NumIOs-1:0] TieOffValues = pinmux_pkg::NumIOs'(1'b1 << ( - pinmux_reg_pkg::NMioPads + DioSpiDeviceCsb)); - // DFT and Debug signal positions in the pinout. localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{ - const_sampling: 1'b1, - tie_offs: TieOffValues, // TODO: can we remove this and just set it to zero? tck_idx: TckPadIdx, tms_idx: TmsPadIdx, trst_idx: TrstNPadIdx, diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv index 9fbb5489afe2e..a266afb6a3313 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv @@ -88,16 +88,8 @@ module chip_earlgrey_nexysvideo #( parameter int TdiPadIdx = 51; parameter int TdoPadIdx = 52; - // TODO: this is temporary and will be removed in the future. - // This specifies the tie-off values of the muxed MIO/DIOs - // when the JTAG is active. SPI CSB is active low. - localparam logic [pinmux_pkg::NumIOs-1:0] TieOffValues = pinmux_pkg::NumIOs'(1'b1 << ( - pinmux_reg_pkg::NMioPads + DioSpiDeviceCsb)); - // DFT and Debug signal positions in the pinout. localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{ - const_sampling: 1'b1, - tie_offs: TieOffValues, // TODO: can we remove this and just set it to zero? tck_idx: TckPadIdx, tms_idx: TmsPadIdx, trst_idx: TrstNPadIdx, diff --git a/hw/top_earlgrey/rtl/chip_earlgrey_verilator.sv b/hw/top_earlgrey/rtl/chip_earlgrey_verilator.sv index d2102c3ab19d3..bf397be6a158c 100644 --- a/hw/top_earlgrey/rtl/chip_earlgrey_verilator.sv +++ b/hw/top_earlgrey/rtl/chip_earlgrey_verilator.sv @@ -125,8 +125,6 @@ module chip_earlgrey_verilator ( // to be split into a Verilator TB and a Verilator chiplevel. // DFT and Debug signal positions in the pinout. localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{ - const_sampling: 1'b1, - tie_offs: '0, tck_idx: pinmux_reg_pkg::NMioPads + top_earlgrey_pkg::DioSpiDeviceSck, tms_idx: pinmux_reg_pkg::NMioPads + diff --git a/hw/top_englishbreakfast/rtl/chip_englishbreakfast_verilator.sv b/hw/top_englishbreakfast/rtl/chip_englishbreakfast_verilator.sv index 2dac22fe94d9e..88bc8d6cf89d1 100644 --- a/hw/top_englishbreakfast/rtl/chip_englishbreakfast_verilator.sv +++ b/hw/top_englishbreakfast/rtl/chip_englishbreakfast_verilator.sv @@ -125,8 +125,6 @@ module chip_englishbreakfast_verilator ( // to be split into a Verilator TB and a Verilator chiplevel. // DFT and Debug signal positions in the pinout. localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{ - const_sampling: 1'b1, - tie_offs: '0, tck_idx: pinmux_reg_pkg::NMioPads + top_englishbreakfast_pkg::DioSpiDeviceSck, tms_idx: pinmux_reg_pkg::NMioPads + diff --git a/sw/device/meson.build b/sw/device/meson.build index b4c6d5506bccc..22116050a5433 100644 --- a/sw/device/meson.build +++ b/sw/device/meson.build @@ -45,11 +45,13 @@ extract_sw_logs_sim_dv_depend_files = [ # Generates the OTP image containing root secrets, sw configuration partitions and # the life cycle state. -# TODO: This just puts the device into DEV life cycle state, with randomized root keys. +# TODO: This just puts the device into RMA life cycle state, with randomized root keys. +# We are using RMA in order to open up all debug and functional infrastructure +# as our testing and emulation environments require that. # Need to make this more flexible in the future. # TODO: additional OTP partitions can be included with the --add-cfg switch # see also util/design/README.md -make_otp_img_inputs = [meson.source_root() / 'hw/ip/otp_ctrl/data/otp_ctrl_img_dev.hjson'] +make_otp_img_inputs = [meson.source_root() / 'hw/ip/otp_ctrl/data/otp_ctrl_img_rma.hjson'] make_otp_img_command = [ prog_python, meson.source_root() / 'util/design/gen-otp-img.py', '--quiet', diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl index dd0c9badfe008..61188c403cc07 100644 --- a/util/topgen/templates/chiplevel.sv.tpl +++ b/util/topgen/templates/chiplevel.sv.tpl @@ -122,16 +122,8 @@ module chip_${top["name"]}_${target["name"]} ( % endfor % endif - // TODO: this is temporary and will be removed in the future. - // This specifies the tie-off values of the muxed MIO/DIOs - // when the JTAG is active. SPI CSB is active low. - localparam logic [pinmux_pkg::NumIOs-1:0] TieOffValues = pinmux_pkg::NumIOs'(1'b1 << ( - pinmux_reg_pkg::NMioPads + DioSpiDeviceCsb)); - // DFT and Debug signal positions in the pinout. localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{ - const_sampling: 1'b1, - tie_offs: TieOffValues, // TODO: can we remove this and just set it to zero? tck_idx: TckPadIdx, tms_idx: TmsPadIdx, trst_idx: TrstNPadIdx,