diff --git a/hw/ip/pwm/data/pwm.hjson b/hw/ip/pwm/data/pwm.hjson index ef3c6057aec77..2bca22c709753 100644 --- a/hw/ip/pwm/data/pwm.hjson +++ b/hw/ip/pwm/data/pwm.hjson @@ -31,7 +31,7 @@ {clock: "clk_core_i", reset: "rst_core_ni"} ] bus_interfaces: [ - { protocol: "tlul", direction: "device" } + { protocol: "tlul", direction: "device", racl_support: true } ], regwidth: "32", param_list: [ @@ -87,6 +87,37 @@ desc: "End-to-end bus integrity scheme." } ] + inter_signal_list: [ + { struct: "racl_policy_vec", + type: "uni", + name: "racl_policies", + act: "rcv", + package: "top_racl_pkg", + desc: ''' + Policy vector distributed to the subscribing RACL IPs. + ''' + } + { struct: "logic", + type: "uni", + name: "racl_error", + act: "req", + width : "1", + desc: ''' + RACL error indication signal. + If 1, the error log contains valid information. + ''' + } + { struct: "racl_error_log", + type: "uni", + name: "racl_error_log", + act: "req", + width: "1" + package: "top_racl_pkg", + desc: ''' + RACL error log information of this module. + ''' + } + ], registers: [ { name: "REGWEN", desc: "Register write enable for all control registers", diff --git a/hw/ip/pwm/doc/interfaces.md b/hw/ip/pwm/doc/interfaces.md index bb3ada272623a..1591ea4255c31 100644 --- a/hw/ip/pwm/doc/interfaces.md +++ b/hw/ip/pwm/doc/interfaces.md @@ -16,9 +16,12 @@ Referring to the [Comportable guideline for peripheral device functionality](htt ## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) -| Port Name | Package::Struct | Type | Act | Width | Description | -|:------------|:------------------|:--------|:------|--------:|:--------------| -| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | +| Port Name | Package::Struct | Type | Act | Width | Description | +|:---------------|:------------------------------|:--------|:------|--------:|:------------------------------------------------------------------------------| +| racl_policies | top_racl_pkg::racl_policy_vec | uni | rcv | 1 | Policy vector distributed to the subscribing RACL IPs. | +| racl_error | logic | uni | req | 1 | RACL error indication signal. If 1, the error log contains valid information. | +| racl_error_log | top_racl_pkg::racl_error_log | uni | req | 1 | RACL error log information of this module. | +| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | ## Security Alerts diff --git a/hw/ip/pwm/rtl/pwm.sv b/hw/ip/pwm/rtl/pwm.sv index 21925e99a77c9..18611056d788d 100644 --- a/hw/ip/pwm/rtl/pwm.sv +++ b/hw/ip/pwm/rtl/pwm.sv @@ -7,9 +7,12 @@ module pwm import pwm_reg_pkg::*; #( - parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, - parameter int PhaseCntDw = 16, - parameter int BeatCntDw = 27 + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + parameter bit EnableRacl = 1'b0, + parameter bit RaclErrorRsp = 1'b1, + parameter int unsigned RaclPolicySelVec[23] = '{23{0}}, + parameter int PhaseCntDw = 16, + parameter int BeatCntDw = 27 ) ( input clk_i, input rst_ni, @@ -23,6 +26,11 @@ module pwm input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + // RACL interface + input top_racl_pkg::racl_policy_vec_t racl_policies_i, + output logic racl_error_o, + output top_racl_pkg::racl_error_log_t racl_error_log_o, + output logic [NOutputs-1:0] cio_pwm_o, output logic [NOutputs-1:0] cio_pwm_en_o ); @@ -30,16 +38,23 @@ module pwm pwm_reg_pkg::pwm_reg2hw_t reg2hw; logic [NumAlerts-1:0] alert_test, alerts; - pwm_reg_top u_reg ( + pwm_reg_top #( + .EnableRacl(EnableRacl), + .RaclErrorRsp(RaclErrorRsp), + .RaclPolicySelVec(RaclPolicySelVec) + ) u_reg ( .clk_i, .rst_ni, .clk_core_i, .rst_core_ni, - .tl_i (tl_i), - .tl_o (tl_o), - .reg2hw (reg2hw), + .tl_i (tl_i), + .tl_o (tl_o), + .reg2hw (reg2hw), + .racl_policies_i (racl_policies_i), + .racl_error_o (racl_error_o), + .racl_error_log_o (racl_error_log_o), // SEC_CM: BUS.INTEGRITY - .intg_err_o (alerts[0]) + .intg_err_o (alerts[0]) ); assign alert_test = { diff --git a/hw/ip/pwm/rtl/pwm_reg_top.sv b/hw/ip/pwm/rtl/pwm_reg_top.sv index 2d1eee529d2ee..cd9e469c19d7a 100644 --- a/hw/ip/pwm/rtl/pwm_reg_top.sv +++ b/hw/ip/pwm/rtl/pwm_reg_top.sv @@ -6,7 +6,12 @@ `include "prim_assert.sv" -module pwm_reg_top ( +module pwm_reg_top + # ( + parameter bit EnableRacl = 1'b0, + parameter bit RaclErrorRsp = 1'b1, + parameter int unsigned RaclPolicySelVec[23] = '{23{0}} + ) ( input clk_i, input rst_ni, input clk_core_i, @@ -16,6 +21,11 @@ module pwm_reg_top ( // To HW output pwm_reg_pkg::pwm_reg2hw_t reg2hw, // Write + // RACL interface + input top_racl_pkg::racl_policy_vec_t racl_policies_i, + output logic racl_error_o, + output top_racl_pkg::racl_error_log_t racl_error_log_o, + // Integrity check errors output logic intg_err_o ); @@ -111,7 +121,8 @@ module pwm_reg_top ( .be_o (reg_be), .busy_i (reg_busy), .rdata_i (reg_rdata), - .error_i (reg_error) + // Translate RACL error to TLUL error if enabled + .error_i (reg_error | (RaclErrorRsp & racl_error_o)) ); // cdc oversampling signals @@ -3087,8 +3098,32 @@ module pwm_reg_top ( logic [22:0] addr_hit; + top_racl_pkg::racl_role_vec_t racl_role_vec; + top_racl_pkg::racl_role_t racl_role; + + logic [22:0] racl_addr_hit_read; + logic [22:0] racl_addr_hit_write; + + if (EnableRacl) begin : gen_racl_role_logic + // Retrieve RACL role from user bits and one-hot encode that for the comparison bitmap + assign racl_role = top_racl_pkg::tlul_extract_racl_role_bits(tl_i.a_user.rsvd); + + prim_onehot_enc #( + .OneHotWidth( $bits(top_racl_pkg::racl_role_vec_t) ) + ) u_racl_role_encode ( + .in_i ( racl_role ), + .en_i ( 1'b1 ), + .out_o( racl_role_vec ) + ); + end else begin : gen_no_racl_role_logic + assign racl_role = '0; + assign racl_role_vec = '0; + end + always_comb begin addr_hit = '0; + racl_addr_hit_read = '0; + racl_addr_hit_write = '0; addr_hit[ 0] = (reg_addr == PWM_ALERT_TEST_OFFSET); addr_hit[ 1] = (reg_addr == PWM_REGWEN_OFFSET); addr_hit[ 2] = (reg_addr == PWM_CFG_OFFSET); @@ -3112,121 +3147,184 @@ module pwm_reg_top ( addr_hit[20] = (reg_addr == PWM_BLINK_PARAM_3_OFFSET); addr_hit[21] = (reg_addr == PWM_BLINK_PARAM_4_OFFSET); addr_hit[22] = (reg_addr == PWM_BLINK_PARAM_5_OFFSET); + + if (EnableRacl) begin : gen_racl_hit + racl_addr_hit_read [ 0] = addr_hit[ 0] & (|(racl_policies_i[RaclPolicySelVec[ 0]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 0] = addr_hit[ 0] & (|(racl_policies_i[RaclPolicySelVec[ 0]].write_perm & racl_role_vec)); + racl_addr_hit_read [ 1] = addr_hit[ 1] & (|(racl_policies_i[RaclPolicySelVec[ 1]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 1] = addr_hit[ 1] & (|(racl_policies_i[RaclPolicySelVec[ 1]].write_perm & racl_role_vec)); + racl_addr_hit_read [ 2] = addr_hit[ 2] & (|(racl_policies_i[RaclPolicySelVec[ 2]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 2] = addr_hit[ 2] & (|(racl_policies_i[RaclPolicySelVec[ 2]].write_perm & racl_role_vec)); + racl_addr_hit_read [ 3] = addr_hit[ 3] & (|(racl_policies_i[RaclPolicySelVec[ 3]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 3] = addr_hit[ 3] & (|(racl_policies_i[RaclPolicySelVec[ 3]].write_perm & racl_role_vec)); + racl_addr_hit_read [ 4] = addr_hit[ 4] & (|(racl_policies_i[RaclPolicySelVec[ 4]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 4] = addr_hit[ 4] & (|(racl_policies_i[RaclPolicySelVec[ 4]].write_perm & racl_role_vec)); + racl_addr_hit_read [ 5] = addr_hit[ 5] & (|(racl_policies_i[RaclPolicySelVec[ 5]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 5] = addr_hit[ 5] & (|(racl_policies_i[RaclPolicySelVec[ 5]].write_perm & racl_role_vec)); + racl_addr_hit_read [ 6] = addr_hit[ 6] & (|(racl_policies_i[RaclPolicySelVec[ 6]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 6] = addr_hit[ 6] & (|(racl_policies_i[RaclPolicySelVec[ 6]].write_perm & racl_role_vec)); + racl_addr_hit_read [ 7] = addr_hit[ 7] & (|(racl_policies_i[RaclPolicySelVec[ 7]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 7] = addr_hit[ 7] & (|(racl_policies_i[RaclPolicySelVec[ 7]].write_perm & racl_role_vec)); + racl_addr_hit_read [ 8] = addr_hit[ 8] & (|(racl_policies_i[RaclPolicySelVec[ 8]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 8] = addr_hit[ 8] & (|(racl_policies_i[RaclPolicySelVec[ 8]].write_perm & racl_role_vec)); + racl_addr_hit_read [ 9] = addr_hit[ 9] & (|(racl_policies_i[RaclPolicySelVec[ 9]].read_perm & racl_role_vec)); + racl_addr_hit_write[ 9] = addr_hit[ 9] & (|(racl_policies_i[RaclPolicySelVec[ 9]].write_perm & racl_role_vec)); + racl_addr_hit_read [10] = addr_hit[10] & (|(racl_policies_i[RaclPolicySelVec[10]].read_perm & racl_role_vec)); + racl_addr_hit_write[10] = addr_hit[10] & (|(racl_policies_i[RaclPolicySelVec[10]].write_perm & racl_role_vec)); + racl_addr_hit_read [11] = addr_hit[11] & (|(racl_policies_i[RaclPolicySelVec[11]].read_perm & racl_role_vec)); + racl_addr_hit_write[11] = addr_hit[11] & (|(racl_policies_i[RaclPolicySelVec[11]].write_perm & racl_role_vec)); + racl_addr_hit_read [12] = addr_hit[12] & (|(racl_policies_i[RaclPolicySelVec[12]].read_perm & racl_role_vec)); + racl_addr_hit_write[12] = addr_hit[12] & (|(racl_policies_i[RaclPolicySelVec[12]].write_perm & racl_role_vec)); + racl_addr_hit_read [13] = addr_hit[13] & (|(racl_policies_i[RaclPolicySelVec[13]].read_perm & racl_role_vec)); + racl_addr_hit_write[13] = addr_hit[13] & (|(racl_policies_i[RaclPolicySelVec[13]].write_perm & racl_role_vec)); + racl_addr_hit_read [14] = addr_hit[14] & (|(racl_policies_i[RaclPolicySelVec[14]].read_perm & racl_role_vec)); + racl_addr_hit_write[14] = addr_hit[14] & (|(racl_policies_i[RaclPolicySelVec[14]].write_perm & racl_role_vec)); + racl_addr_hit_read [15] = addr_hit[15] & (|(racl_policies_i[RaclPolicySelVec[15]].read_perm & racl_role_vec)); + racl_addr_hit_write[15] = addr_hit[15] & (|(racl_policies_i[RaclPolicySelVec[15]].write_perm & racl_role_vec)); + racl_addr_hit_read [16] = addr_hit[16] & (|(racl_policies_i[RaclPolicySelVec[16]].read_perm & racl_role_vec)); + racl_addr_hit_write[16] = addr_hit[16] & (|(racl_policies_i[RaclPolicySelVec[16]].write_perm & racl_role_vec)); + racl_addr_hit_read [17] = addr_hit[17] & (|(racl_policies_i[RaclPolicySelVec[17]].read_perm & racl_role_vec)); + racl_addr_hit_write[17] = addr_hit[17] & (|(racl_policies_i[RaclPolicySelVec[17]].write_perm & racl_role_vec)); + racl_addr_hit_read [18] = addr_hit[18] & (|(racl_policies_i[RaclPolicySelVec[18]].read_perm & racl_role_vec)); + racl_addr_hit_write[18] = addr_hit[18] & (|(racl_policies_i[RaclPolicySelVec[18]].write_perm & racl_role_vec)); + racl_addr_hit_read [19] = addr_hit[19] & (|(racl_policies_i[RaclPolicySelVec[19]].read_perm & racl_role_vec)); + racl_addr_hit_write[19] = addr_hit[19] & (|(racl_policies_i[RaclPolicySelVec[19]].write_perm & racl_role_vec)); + racl_addr_hit_read [20] = addr_hit[20] & (|(racl_policies_i[RaclPolicySelVec[20]].read_perm & racl_role_vec)); + racl_addr_hit_write[20] = addr_hit[20] & (|(racl_policies_i[RaclPolicySelVec[20]].write_perm & racl_role_vec)); + racl_addr_hit_read [21] = addr_hit[21] & (|(racl_policies_i[RaclPolicySelVec[21]].read_perm & racl_role_vec)); + racl_addr_hit_write[21] = addr_hit[21] & (|(racl_policies_i[RaclPolicySelVec[21]].write_perm & racl_role_vec)); + racl_addr_hit_read [22] = addr_hit[22] & (|(racl_policies_i[RaclPolicySelVec[22]].read_perm & racl_role_vec)); + racl_addr_hit_write[22] = addr_hit[22] & (|(racl_policies_i[RaclPolicySelVec[22]].write_perm & racl_role_vec)); + end else begin : gen_no_racl + racl_addr_hit_read = addr_hit; + racl_addr_hit_write = addr_hit; + end end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + // Address hit but failed the RACL check + assign racl_error_o = (|addr_hit) & ~(|(addr_hit & (racl_addr_hit_read | racl_addr_hit_write))); + assign racl_error_log_o.racl_role = racl_role; + + if (EnableRacl) begin : gen_racl_log + assign racl_error_log_o.ctn_uid = top_racl_pkg::tlul_extract_ctn_uid_bits(tl_i.a_user.rsvd); + assign racl_error_log_o.read_not_write = tl_i.a_opcode == tlul_pkg::Get; + end else begin : gen_no_racl_log + assign racl_error_log_o.ctn_uid = '0; + assign racl_error_log_o.read_not_write = 1'b0; + end // Check sub-word write is permitted always_comb begin wr_err = (reg_we & - ((addr_hit[ 0] & (|(PWM_PERMIT[ 0] & ~reg_be))) | - (addr_hit[ 1] & (|(PWM_PERMIT[ 1] & ~reg_be))) | - (addr_hit[ 2] & (|(PWM_PERMIT[ 2] & ~reg_be))) | - (addr_hit[ 3] & (|(PWM_PERMIT[ 3] & ~reg_be))) | - (addr_hit[ 4] & (|(PWM_PERMIT[ 4] & ~reg_be))) | - (addr_hit[ 5] & (|(PWM_PERMIT[ 5] & ~reg_be))) | - (addr_hit[ 6] & (|(PWM_PERMIT[ 6] & ~reg_be))) | - (addr_hit[ 7] & (|(PWM_PERMIT[ 7] & ~reg_be))) | - (addr_hit[ 8] & (|(PWM_PERMIT[ 8] & ~reg_be))) | - (addr_hit[ 9] & (|(PWM_PERMIT[ 9] & ~reg_be))) | - (addr_hit[10] & (|(PWM_PERMIT[10] & ~reg_be))) | - (addr_hit[11] & (|(PWM_PERMIT[11] & ~reg_be))) | - (addr_hit[12] & (|(PWM_PERMIT[12] & ~reg_be))) | - (addr_hit[13] & (|(PWM_PERMIT[13] & ~reg_be))) | - (addr_hit[14] & (|(PWM_PERMIT[14] & ~reg_be))) | - (addr_hit[15] & (|(PWM_PERMIT[15] & ~reg_be))) | - (addr_hit[16] & (|(PWM_PERMIT[16] & ~reg_be))) | - (addr_hit[17] & (|(PWM_PERMIT[17] & ~reg_be))) | - (addr_hit[18] & (|(PWM_PERMIT[18] & ~reg_be))) | - (addr_hit[19] & (|(PWM_PERMIT[19] & ~reg_be))) | - (addr_hit[20] & (|(PWM_PERMIT[20] & ~reg_be))) | - (addr_hit[21] & (|(PWM_PERMIT[21] & ~reg_be))) | - (addr_hit[22] & (|(PWM_PERMIT[22] & ~reg_be))))); + ((racl_addr_hit_write[ 0] & (|(PWM_PERMIT[ 0] & ~reg_be))) | + (racl_addr_hit_write[ 1] & (|(PWM_PERMIT[ 1] & ~reg_be))) | + (racl_addr_hit_write[ 2] & (|(PWM_PERMIT[ 2] & ~reg_be))) | + (racl_addr_hit_write[ 3] & (|(PWM_PERMIT[ 3] & ~reg_be))) | + (racl_addr_hit_write[ 4] & (|(PWM_PERMIT[ 4] & ~reg_be))) | + (racl_addr_hit_write[ 5] & (|(PWM_PERMIT[ 5] & ~reg_be))) | + (racl_addr_hit_write[ 6] & (|(PWM_PERMIT[ 6] & ~reg_be))) | + (racl_addr_hit_write[ 7] & (|(PWM_PERMIT[ 7] & ~reg_be))) | + (racl_addr_hit_write[ 8] & (|(PWM_PERMIT[ 8] & ~reg_be))) | + (racl_addr_hit_write[ 9] & (|(PWM_PERMIT[ 9] & ~reg_be))) | + (racl_addr_hit_write[10] & (|(PWM_PERMIT[10] & ~reg_be))) | + (racl_addr_hit_write[11] & (|(PWM_PERMIT[11] & ~reg_be))) | + (racl_addr_hit_write[12] & (|(PWM_PERMIT[12] & ~reg_be))) | + (racl_addr_hit_write[13] & (|(PWM_PERMIT[13] & ~reg_be))) | + (racl_addr_hit_write[14] & (|(PWM_PERMIT[14] & ~reg_be))) | + (racl_addr_hit_write[15] & (|(PWM_PERMIT[15] & ~reg_be))) | + (racl_addr_hit_write[16] & (|(PWM_PERMIT[16] & ~reg_be))) | + (racl_addr_hit_write[17] & (|(PWM_PERMIT[17] & ~reg_be))) | + (racl_addr_hit_write[18] & (|(PWM_PERMIT[18] & ~reg_be))) | + (racl_addr_hit_write[19] & (|(PWM_PERMIT[19] & ~reg_be))) | + (racl_addr_hit_write[20] & (|(PWM_PERMIT[20] & ~reg_be))) | + (racl_addr_hit_write[21] & (|(PWM_PERMIT[21] & ~reg_be))) | + (racl_addr_hit_write[22] & (|(PWM_PERMIT[22] & ~reg_be))))); end // Generate write-enables - assign alert_test_we = addr_hit[0] & reg_we & !reg_error; + assign alert_test_we = racl_addr_hit_write[0] & reg_we & !reg_error; assign alert_test_wd = reg_wdata[0]; - assign regwen_we = addr_hit[1] & reg_we & !reg_error; + assign regwen_we = racl_addr_hit_write[1] & reg_we & !reg_error; assign regwen_wd = reg_wdata[0]; - assign cfg_we = addr_hit[2] & reg_we & !reg_error; + assign cfg_we = racl_addr_hit_write[2] & reg_we & !reg_error; - assign pwm_en_we = addr_hit[3] & reg_we & !reg_error; + assign pwm_en_we = racl_addr_hit_write[3] & reg_we & !reg_error; - assign invert_we = addr_hit[4] & reg_we & !reg_error; + assign invert_we = racl_addr_hit_write[4] & reg_we & !reg_error; - assign pwm_param_0_we = addr_hit[5] & reg_we & !reg_error; + assign pwm_param_0_we = racl_addr_hit_write[5] & reg_we & !reg_error; - assign pwm_param_1_we = addr_hit[6] & reg_we & !reg_error; + assign pwm_param_1_we = racl_addr_hit_write[6] & reg_we & !reg_error; - assign pwm_param_2_we = addr_hit[7] & reg_we & !reg_error; + assign pwm_param_2_we = racl_addr_hit_write[7] & reg_we & !reg_error; - assign pwm_param_3_we = addr_hit[8] & reg_we & !reg_error; + assign pwm_param_3_we = racl_addr_hit_write[8] & reg_we & !reg_error; - assign pwm_param_4_we = addr_hit[9] & reg_we & !reg_error; + assign pwm_param_4_we = racl_addr_hit_write[9] & reg_we & !reg_error; - assign pwm_param_5_we = addr_hit[10] & reg_we & !reg_error; + assign pwm_param_5_we = racl_addr_hit_write[10] & reg_we & !reg_error; - assign duty_cycle_0_we = addr_hit[11] & reg_we & !reg_error; + assign duty_cycle_0_we = racl_addr_hit_write[11] & reg_we & !reg_error; - assign duty_cycle_1_we = addr_hit[12] & reg_we & !reg_error; + assign duty_cycle_1_we = racl_addr_hit_write[12] & reg_we & !reg_error; - assign duty_cycle_2_we = addr_hit[13] & reg_we & !reg_error; + assign duty_cycle_2_we = racl_addr_hit_write[13] & reg_we & !reg_error; - assign duty_cycle_3_we = addr_hit[14] & reg_we & !reg_error; + assign duty_cycle_3_we = racl_addr_hit_write[14] & reg_we & !reg_error; - assign duty_cycle_4_we = addr_hit[15] & reg_we & !reg_error; + assign duty_cycle_4_we = racl_addr_hit_write[15] & reg_we & !reg_error; - assign duty_cycle_5_we = addr_hit[16] & reg_we & !reg_error; + assign duty_cycle_5_we = racl_addr_hit_write[16] & reg_we & !reg_error; - assign blink_param_0_we = addr_hit[17] & reg_we & !reg_error; + assign blink_param_0_we = racl_addr_hit_write[17] & reg_we & !reg_error; - assign blink_param_1_we = addr_hit[18] & reg_we & !reg_error; + assign blink_param_1_we = racl_addr_hit_write[18] & reg_we & !reg_error; - assign blink_param_2_we = addr_hit[19] & reg_we & !reg_error; + assign blink_param_2_we = racl_addr_hit_write[19] & reg_we & !reg_error; - assign blink_param_3_we = addr_hit[20] & reg_we & !reg_error; + assign blink_param_3_we = racl_addr_hit_write[20] & reg_we & !reg_error; - assign blink_param_4_we = addr_hit[21] & reg_we & !reg_error; + assign blink_param_4_we = racl_addr_hit_write[21] & reg_we & !reg_error; - assign blink_param_5_we = addr_hit[22] & reg_we & !reg_error; + assign blink_param_5_we = racl_addr_hit_write[22] & reg_we & !reg_error; @@ -3262,75 +3360,75 @@ module pwm_reg_top ( always_comb begin reg_rdata_next = '0; unique case (1'b1) - addr_hit[0]: begin + racl_addr_hit_read[0]: begin reg_rdata_next[0] = '0; end - addr_hit[1]: begin + racl_addr_hit_read[1]: begin reg_rdata_next[0] = regwen_qs; end - addr_hit[2]: begin + racl_addr_hit_read[2]: begin reg_rdata_next = DW'(cfg_qs); end - addr_hit[3]: begin + racl_addr_hit_read[3]: begin reg_rdata_next = DW'(pwm_en_qs); end - addr_hit[4]: begin + racl_addr_hit_read[4]: begin reg_rdata_next = DW'(invert_qs); end - addr_hit[5]: begin + racl_addr_hit_read[5]: begin reg_rdata_next = DW'(pwm_param_0_qs); end - addr_hit[6]: begin + racl_addr_hit_read[6]: begin reg_rdata_next = DW'(pwm_param_1_qs); end - addr_hit[7]: begin + racl_addr_hit_read[7]: begin reg_rdata_next = DW'(pwm_param_2_qs); end - addr_hit[8]: begin + racl_addr_hit_read[8]: begin reg_rdata_next = DW'(pwm_param_3_qs); end - addr_hit[9]: begin + racl_addr_hit_read[9]: begin reg_rdata_next = DW'(pwm_param_4_qs); end - addr_hit[10]: begin + racl_addr_hit_read[10]: begin reg_rdata_next = DW'(pwm_param_5_qs); end - addr_hit[11]: begin + racl_addr_hit_read[11]: begin reg_rdata_next = DW'(duty_cycle_0_qs); end - addr_hit[12]: begin + racl_addr_hit_read[12]: begin reg_rdata_next = DW'(duty_cycle_1_qs); end - addr_hit[13]: begin + racl_addr_hit_read[13]: begin reg_rdata_next = DW'(duty_cycle_2_qs); end - addr_hit[14]: begin + racl_addr_hit_read[14]: begin reg_rdata_next = DW'(duty_cycle_3_qs); end - addr_hit[15]: begin + racl_addr_hit_read[15]: begin reg_rdata_next = DW'(duty_cycle_4_qs); end - addr_hit[16]: begin + racl_addr_hit_read[16]: begin reg_rdata_next = DW'(duty_cycle_5_qs); end - addr_hit[17]: begin + racl_addr_hit_read[17]: begin reg_rdata_next = DW'(blink_param_0_qs); end - addr_hit[18]: begin + racl_addr_hit_read[18]: begin reg_rdata_next = DW'(blink_param_1_qs); end - addr_hit[19]: begin + racl_addr_hit_read[19]: begin reg_rdata_next = DW'(blink_param_2_qs); end - addr_hit[20]: begin + racl_addr_hit_read[20]: begin reg_rdata_next = DW'(blink_param_3_qs); end - addr_hit[21]: begin + racl_addr_hit_read[21]: begin reg_rdata_next = DW'(blink_param_4_qs); end - addr_hit[22]: begin + racl_addr_hit_read[22]: begin reg_rdata_next = DW'(blink_param_5_qs); end default: begin @@ -3427,6 +3525,8 @@ module pwm_reg_top ( logic unused_be; assign unused_wdata = ^reg_wdata; assign unused_be = ^reg_be; + logic unused_policy_sel; + assign unused_policy_sel = ^racl_policies_i; // Assertions for Register Interface `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 70590f4395ea7..99896bf76866c 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -4271,6 +4271,42 @@ param_list: [] inter_signal_list: [ + { + name: racl_policies + desc: Policy vector distributed to the subscribing RACL IPs. + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: pwm_aon + index: -1 + } + { + name: racl_error + desc: + ''' + RACL error indication signal. + If 1, the error log contains valid information. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: pwm_aon + index: -1 + } + { + name: racl_error_log + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: pwm_aon + index: -1 + } { name: tl struct: tl @@ -19557,6 +19593,42 @@ top_signame: adc_ctrl_aon_tl index: -1 } + { + name: racl_policies + desc: Policy vector distributed to the subscribing RACL IPs. + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: pwm_aon + index: -1 + } + { + name: racl_error + desc: + ''' + RACL error indication signal. + If 1, the error log contains valid information. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: pwm_aon + index: -1 + } + { + name: racl_error_log + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: pwm_aon + index: -1 + } { name: tl struct: tl diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 68df8c8880f78..66574a844689c 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -1972,6 +1972,9 @@ module top_earlgrey #( .alert_rx_i ( alert_rx[29:29] ), // Inter-module signals + .racl_policies_i(top_racl_pkg::RACL_POLICY_VEC_DEFAULT), + .racl_error_o(), + .racl_error_log_o(), .tl_i(pwm_aon_tl_req), .tl_o(pwm_aon_tl_rsp),