From 4c542afbd735e18e36ebcdc091ee2b9b5e6c226e Mon Sep 17 00:00:00 2001 From: Alexander Williams Date: Sat, 28 Dec 2024 18:05:52 -0800 Subject: [PATCH] [ipgen] Try out a single virtual provider library for all tops Signed-off-by: Alexander Williams --- .../alert_handler/alert_handler.core.tpl | 9 ++++++ .../data/alert_handler.tpldesc.hjson | 6 ++++ .../dv/alert_handler_sim.core.tpl | 9 ++++++ .../fpv/alert_handler_esc_timer_fpv.core.tpl | 13 ++++++++ .../fpv/alert_handler_ping_timer_fpv.core.tpl | 13 ++++++++ hw/ip_templates/clkmgr/clkmgr.core.tpl | 10 +++---- .../clkmgr/data/clkmgr.tpldesc.hjson | 4 +-- hw/ip_templates/clkmgr/dv/clkmgr_sim.core.tpl | 12 ++++---- .../flash_ctrl/data/flash_ctrl.tpldesc.hjson | 4 +-- .../flash_ctrl/dv/flash_ctrl_sim.core.tpl | 16 +++++----- .../flash_ctrl/flash_ctrl.core.tpl | 10 +++---- .../pinmux/data/pinmux.tpldesc.hjson | 6 ++++ .../pinmux/fpv/pinmux_chip_fpv.core.tpl | 13 ++++++++ .../pinmux/fpv/pinmux_fpv.core.tpl | 13 ++++++++ hw/ip_templates/pinmux/pinmux.core.tpl | 13 ++++++++ .../pwrmgr/data/pwrmgr.tpldesc.hjson | 10 ++----- hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core.tpl | 19 ++++-------- hw/ip_templates/pwrmgr/pwrmgr.core.tpl | 10 +++---- .../rstmgr/data/rstmgr.tpldesc.hjson | 10 ++----- .../rstmgr_cnsty_chk_sim.core.tpl | 9 ++++++ hw/ip_templates/rstmgr/dv/rstmgr_sim.core.tpl | 20 ++++--------- hw/ip_templates/rstmgr/rstmgr.core.tpl | 19 ++++-------- .../alert_handler/alert_handler.core | 5 ++++ ...op_darjeeling_alert_handler.ipconfig.hjson | 1 + .../alert_handler/dv/alert_handler_sim.core | 5 ++++ .../fpv/alert_handler_esc_timer_fpv.core | 7 +++++ .../fpv/alert_handler_ping_timer_fpv.core | 7 +++++ .../ip_autogen/clkmgr/clkmgr.core | 6 ++-- .../data/top_darjeeling_clkmgr.ipconfig.hjson | 2 +- .../ip_autogen/clkmgr/dv/clkmgr_sim.core | 6 ++-- .../data/top_darjeeling_pinmux.ipconfig.hjson | 1 + .../pinmux/fpv/pinmux_chip_fpv.core | 7 +++++ .../ip_autogen/pinmux/fpv/pinmux_fpv.core | 7 +++++ .../ip_autogen/pinmux/pinmux.core | 7 +++++ .../data/top_darjeeling_pwrmgr.ipconfig.hjson | 3 +- .../ip_autogen/pwrmgr/dv/pwrmgr_sim.core | 7 ++--- .../ip_autogen/pwrmgr/pwrmgr.core | 6 ++-- .../data/top_darjeeling_rstmgr.ipconfig.hjson | 3 +- .../rstmgr_cnsty_chk_sim.core | 5 ++++ .../ip_autogen/rstmgr/dv/rstmgr_sim.core | 8 ++--- .../ip_autogen/rstmgr/rstmgr.core | 7 ++--- hw/top_earlgrey/dv/top_earlgrey_ast_top.core | 5 +--- .../alert_handler/alert_handler.core | 5 ++++ .../top_earlgrey_alert_handler.ipconfig.hjson | 1 + .../alert_handler/dv/alert_handler_sim.core | 5 ++++ .../fpv/alert_handler_esc_timer_fpv.core | 7 +++++ .../fpv/alert_handler_ping_timer_fpv.core | 7 +++++ hw/top_earlgrey/ip_autogen/clkmgr/clkmgr.core | 6 ++-- .../data/top_earlgrey_clkmgr.ipconfig.hjson | 2 +- .../ip_autogen/clkmgr/dv/clkmgr_sim.core | 6 ++-- .../top_earlgrey_flash_ctrl.ipconfig.hjson | 2 +- .../flash_ctrl/dv/flash_ctrl_sim.core | 8 ++--- .../ip_autogen/flash_ctrl/flash_ctrl.core | 6 ++-- .../data/top_earlgrey_pinmux.ipconfig.hjson | 1 + .../pinmux/fpv/pinmux_chip_fpv.core | 7 +++++ .../ip_autogen/pinmux/fpv/pinmux_fpv.core | 7 +++++ hw/top_earlgrey/ip_autogen/pinmux/pinmux.core | 7 +++++ .../data/top_earlgrey_pwrmgr.ipconfig.hjson | 3 +- .../ip_autogen/pwrmgr/dv/pwrmgr_sim.core | 7 ++--- hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core | 6 ++-- .../data/top_earlgrey_rstmgr.ipconfig.hjson | 3 +- .../rstmgr_cnsty_chk_sim.core | 5 ++++ .../ip_autogen/rstmgr/dv/rstmgr_sim.core | 8 ++--- hw/top_earlgrey/ip_autogen/rstmgr/rstmgr.core | 7 ++--- .../top_earlgrey_virtual_provider.core | 30 +++++++++++++++++++ .../ip_autogen/clkmgr/clkmgr.core | 6 ++-- ...top_englishbreakfast_clkmgr.ipconfig.hjson | 2 +- .../ip_autogen/clkmgr/dv/clkmgr_sim.core | 6 ++-- ...englishbreakfast_flash_ctrl.ipconfig.hjson | 2 +- .../flash_ctrl/dv/flash_ctrl_sim.core | 8 ++--- .../ip_autogen/flash_ctrl/flash_ctrl.core | 6 ++-- ...top_englishbreakfast_pinmux.ipconfig.hjson | 1 + .../pinmux/fpv/pinmux_chip_fpv.core | 7 +++++ .../ip_autogen/pinmux/fpv/pinmux_fpv.core | 7 +++++ .../ip_autogen/pinmux/pinmux.core | 7 +++++ ...top_englishbreakfast_pwrmgr.ipconfig.hjson | 3 +- .../ip_autogen/pwrmgr/dv/pwrmgr_sim.core | 7 ++--- .../ip_autogen/pwrmgr/pwrmgr.core | 6 ++-- ...top_englishbreakfast_rstmgr.ipconfig.hjson | 2 +- .../rstmgr_cnsty_chk_sim.core | 5 ++++ .../ip_autogen/rstmgr/dv/rstmgr_sim.core | 7 ++--- .../ip_autogen/rstmgr/rstmgr.core | 6 ++-- util/topgen.py | 15 +++++----- 83 files changed, 404 insertions(+), 198 deletions(-) create mode 100644 hw/top_earlgrey/top_earlgrey_virtual_provider.core diff --git a/hw/ip_templates/alert_handler/alert_handler.core.tpl b/hw/ip_templates/alert_handler/alert_handler.core.tpl index 9d025e2963ebc..b8bcd2a5b7bfd 100644 --- a/hw/ip_templates/alert_handler/alert_handler.core.tpl +++ b/hw/ip_templates/alert_handler/alert_handler.core.tpl @@ -13,6 +13,11 @@ filesets: - ${instance_vlnv("lowrisc:ip:alert_handler_component:0.1")} - ${instance_vlnv("lowrisc:ip_interfaces:alert_handler_reg:0.1")} file_type: systemVerilogSource +% if len(virtual_provider) > 0: + files_virtual_provider: + depend: + - "fileset_top ? (${virtual_provider})" +% endif parameters: SYNTHESIS: @@ -28,6 +33,10 @@ targets: lint: <<: *default_target +% if len(virtual_provider) > 0: + filesets_append: + - files_virtual_provider +% endif default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/ip_templates/alert_handler/data/alert_handler.tpldesc.hjson b/hw/ip_templates/alert_handler/data/alert_handler.tpldesc.hjson index 9fcb470ef57f7..856c3b2c51ff9 100644 --- a/hw/ip_templates/alert_handler/data/alert_handler.tpldesc.hjson +++ b/hw/ip_templates/alert_handler/data/alert_handler.tpldesc.hjson @@ -51,5 +51,11 @@ type: "object" default: [] } + { + name: "virtual_provider" + desc: "VLNV providing all virtual cores, used with fileset_top flag" + type: "string" + default: "" + } ] } diff --git a/hw/ip_templates/alert_handler/dv/alert_handler_sim.core.tpl b/hw/ip_templates/alert_handler/dv/alert_handler_sim.core.tpl index 52f32902eb4c1..0a04dbb248167 100644 --- a/hw/ip_templates/alert_handler/dv/alert_handler_sim.core.tpl +++ b/hw/ip_templates/alert_handler/dv/alert_handler_sim.core.tpl @@ -18,6 +18,12 @@ filesets: - ${instance_vlnv("lowrisc:dv:alert_handler_sva:0.1")} file_type: systemVerilogSource +% if len(virtual_provider) > 0: + files_virtual_provider: + depend: + - "fileset_top ? (${virtual_provider})" +% endif + generate: ral: generator: ralgen @@ -31,6 +37,9 @@ targets: filesets: - files_rtl - files_dv +% if len(virtual_provider) > 0: + - files_virtual_provider +% endif generate: - ral default_tool: vcs diff --git a/hw/ip_templates/alert_handler/fpv/alert_handler_esc_timer_fpv.core.tpl b/hw/ip_templates/alert_handler/fpv/alert_handler_esc_timer_fpv.core.tpl index 57c16552887bd..d00bbab44de74 100644 --- a/hw/ip_templates/alert_handler/fpv/alert_handler_esc_timer_fpv.core.tpl +++ b/hw/ip_templates/alert_handler/fpv/alert_handler_esc_timer_fpv.core.tpl @@ -14,6 +14,11 @@ filesets: - tb/alert_handler_esc_timer_bind_fpv.sv - tb/alert_handler_esc_timer_tb.sv file_type: systemVerilogSource +% if len(virtual_provider) > 0: + files_virtual_provider: + depend: + - "fileset_top ? (${virtual_provider})" +% endif targets: default: &default_target @@ -26,6 +31,14 @@ targets: formal: <<: *default_target +% if len(virtual_provider) > 0: + filesets_append: + - files_virtual_provider +% endif lint: <<: *default_target +% if len(virtual_provider) > 0: + filesets_append: + - files_virtual_provider +% endif diff --git a/hw/ip_templates/alert_handler/fpv/alert_handler_ping_timer_fpv.core.tpl b/hw/ip_templates/alert_handler/fpv/alert_handler_ping_timer_fpv.core.tpl index f1eab0aeac312..ff0859bb6a6ae 100644 --- a/hw/ip_templates/alert_handler/fpv/alert_handler_ping_timer_fpv.core.tpl +++ b/hw/ip_templates/alert_handler/fpv/alert_handler_ping_timer_fpv.core.tpl @@ -14,6 +14,11 @@ filesets: - tb/alert_handler_ping_timer_bind_fpv.sv - tb/alert_handler_ping_timer_tb.sv file_type: systemVerilogSource +% if len(virtual_provider) > 0: + files_virtual_provider: + depend: + - "${virtual_provider}" +% endif targets: default: &default_target @@ -26,6 +31,14 @@ targets: formal: <<: *default_target +% if len(virtual_provider) > 0: + filesets_append: + - files_virtual_provider +% endif lint: <<: *default_target +% if len(virtual_provider) > 0: + filesets_append: + - files_virtual_provider +% endif diff --git a/hw/ip_templates/clkmgr/clkmgr.core.tpl b/hw/ip_templates/clkmgr/clkmgr.core.tpl index 48441de5ced56..aa73946caf128 100644 --- a/hw/ip_templates/clkmgr/clkmgr.core.tpl +++ b/hw/ip_templates/clkmgr/clkmgr.core.tpl @@ -33,10 +33,10 @@ filesets: - rtl/clkmgr_trans.sv file_type: systemVerilogSource -% if len(pwrmgr_instance_name) > 0: - files_top_lint: +% if len(virtual_provider) > 0: + files_virtual_provider: depend: - - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1", pwrmgr_instance_name)})" + - "fileset_top ? (${virtual_provider})" % endif files_verilator_waiver: @@ -69,9 +69,9 @@ targets: lint: <<: *default_target -% if len(pwrmgr_instance_name) > 0: +% if len(virtual_provider) > 0: filesets_append: - - files_top_lint + - files_virtual_provider % endif default_tool: verilator parameters: diff --git a/hw/ip_templates/clkmgr/data/clkmgr.tpldesc.hjson b/hw/ip_templates/clkmgr/data/clkmgr.tpldesc.hjson index 05b83960923c8..0b3cc67412946 100644 --- a/hw/ip_templates/clkmgr/data/clkmgr.tpldesc.hjson +++ b/hw/ip_templates/clkmgr/data/clkmgr.tpldesc.hjson @@ -93,8 +93,8 @@ default: "1" } { - name: "pwrmgr_instance_name" - desc: "Instance name for the pwrmgr dependencies, if available" + name: "virtual_provider" + desc: "VLNV providing all virtual cores, used with fileset_top flag" type: "string" default: "" } diff --git a/hw/ip_templates/clkmgr/dv/clkmgr_sim.core.tpl b/hw/ip_templates/clkmgr/dv/clkmgr_sim.core.tpl index 2f3c15edee79c..886f214e071bb 100644 --- a/hw/ip_templates/clkmgr/dv/clkmgr_sim.core.tpl +++ b/hw/ip_templates/clkmgr/dv/clkmgr_sim.core.tpl @@ -18,11 +18,11 @@ filesets: - cov/clkmgr_cov_bind.sv file_type: systemVerilogSource -% if len(pwrmgr_instance_name) > 0: - files_top_sim: +% if len(virtual_provider) > 0: + files_virtual_provider: depend: - - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1", pwrmgr_instance_name)})" -%endif + - "fileset_top ? (${virtual_provider})" +% endif targets: sim: &sim_target @@ -30,8 +30,8 @@ targets: filesets: - files_rtl - files_dv -% if len(pwrmgr_instance_name) > 0: - - files_top_sim +% if len(virtual_provider) > 0: + - files_virtual_provider % endif default_tool: vcs diff --git a/hw/ip_templates/flash_ctrl/data/flash_ctrl.tpldesc.hjson b/hw/ip_templates/flash_ctrl/data/flash_ctrl.tpldesc.hjson index baba9a3a9b966..c60928b0e4607 100644 --- a/hw/ip_templates/flash_ctrl/data/flash_ctrl.tpldesc.hjson +++ b/hw/ip_templates/flash_ctrl/data/flash_ctrl.tpldesc.hjson @@ -88,8 +88,8 @@ default: "1048576" } { - name: "pwrmgr_instance_name" - desc: "Instance name for the pwrmgr dependencies, if available" + name: "virtual_provider" + desc: "VLNV providing all virtual cores, used with fileset_top flag" type: "string" default: "" } diff --git a/hw/ip_templates/flash_ctrl/dv/flash_ctrl_sim.core.tpl b/hw/ip_templates/flash_ctrl/dv/flash_ctrl_sim.core.tpl index e78fcb00a2dcf..3c2dabd8f19dc 100644 --- a/hw/ip_templates/flash_ctrl/dv/flash_ctrl_sim.core.tpl +++ b/hw/ip_templates/flash_ctrl/dv/flash_ctrl_sim.core.tpl @@ -22,11 +22,11 @@ filesets: - tb/tb.sv file_type: systemVerilogSource -% if len(pwrmgr_instance_name) > 0: - files_top_sim: +% if len(virtual_provider) > 0: + files_virtual_provider: depend: - - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1", pwrmgr_instance_name)})" -%endif + - "fileset_top ? (${virtual_provider})" +% endif targets: default: &default_target @@ -37,15 +37,15 @@ targets: sim: <<: *default_target -% if len(pwrmgr_instance_name) > 0: +% if len(virtual_provider) > 0: filesets_append: - - files_top_sim + - files_virtual_provider % endif default_tool: vcs lint: <<: *default_target -% if len(pwrmgr_instance_name) > 0: +% if len(virtual_provider) > 0: filesets_append: - - files_top_sim + - files_virtual_provider % endif diff --git a/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl b/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl index 66d5da113c9b9..7c3c6a6aba6b2 100644 --- a/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl +++ b/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl @@ -46,10 +46,10 @@ filesets: - rtl/flash_phy_scramble.sv file_type: systemVerilogSource -% if len(pwrmgr_instance_name) > 0: - files_top_lint: +% if len(virtual_provider) > 0: + files_virtual_provider: depend: - - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1", pwrmgr_instance_name)})" + - "fileset_top ? (${virtual_provider})" % endif files_verilator_waiver: @@ -93,9 +93,9 @@ targets: lint: <<: *default_target -% if len(pwrmgr_instance_name) > 0: +% if len(virtual_provider) > 0: filesets_append: - - files_top_lint + - files_virtual_provider % endif default_tool: verilator parameters: diff --git a/hw/ip_templates/pinmux/data/pinmux.tpldesc.hjson b/hw/ip_templates/pinmux/data/pinmux.tpldesc.hjson index f3b3942aad4f9..66c1d86155c7f 100644 --- a/hw/ip_templates/pinmux/data/pinmux.tpldesc.hjson +++ b/hw/ip_templates/pinmux/data/pinmux.tpldesc.hjson @@ -69,5 +69,11 @@ type: "bool" default: "1" } + { + name: "virtual_provider" + desc: "VLNV providing all virtual cores, used with fileset_top flag" + type: "string" + default: "" + } ] } diff --git a/hw/ip_templates/pinmux/fpv/pinmux_chip_fpv.core.tpl b/hw/ip_templates/pinmux/fpv/pinmux_chip_fpv.core.tpl index 53dffc0ee280f..bcb6d2512ea71 100644 --- a/hw/ip_templates/pinmux/fpv/pinmux_chip_fpv.core.tpl +++ b/hw/ip_templates/pinmux/fpv/pinmux_chip_fpv.core.tpl @@ -20,6 +20,11 @@ filesets: files: - tb/pinmux_chip_tb.sv file_type: systemVerilogSource +% if len(virtual_provider) > 0: + files_virtual_provider: + depend: + - "fileset_top ? (${virtual_provider})" +% endif generate: csr_assert_gen: @@ -38,6 +43,14 @@ targets: formal: <<: *default_target +% if len(virtual_provider) > 0: + filesets_append: + - files_virtual_provider +% endif lint: <<: *default_target +% if len(virtual_provider) > 0: + filesets_append: + - files_virtual_provider +% endif diff --git a/hw/ip_templates/pinmux/fpv/pinmux_fpv.core.tpl b/hw/ip_templates/pinmux/fpv/pinmux_fpv.core.tpl index be660174056fb..fbb92a49fd501 100644 --- a/hw/ip_templates/pinmux/fpv/pinmux_fpv.core.tpl +++ b/hw/ip_templates/pinmux/fpv/pinmux_fpv.core.tpl @@ -16,6 +16,11 @@ filesets: files: - tb/pinmux_tb.sv file_type: systemVerilogSource +% if len(virtual_provider) > 0: + files_virtual_provider: + depend: + - "fileset_top ? (${virtual_provider})" +% endif generate: csr_assert_gen: @@ -34,6 +39,14 @@ targets: formal: <<: *default_target +% if len(virtual_provider) > 0: + filesets_append: + - files_virtual_provider +% endif lint: <<: *default_target +% if len(virtual_provider) > 0: + filesets_append: + - files_virtual_provider +% endif diff --git a/hw/ip_templates/pinmux/pinmux.core.tpl b/hw/ip_templates/pinmux/pinmux.core.tpl index cd0a7cba9f42b..d95b9d54dab9a 100644 --- a/hw/ip_templates/pinmux/pinmux.core.tpl +++ b/hw/ip_templates/pinmux/pinmux.core.tpl @@ -34,6 +34,12 @@ filesets: - rtl/pinmux.sv file_type: systemVerilogSource +% if len(virtual_provider) > 0: + files_virtual_provider: + depend: + - "fileset_top ? (${virtual_provider})" +% endif + files_verilator_waiver: depend: # common waivers @@ -74,6 +80,10 @@ targets: lint: <<: *default_target +% if len(virtual_provider) > 0: + filesets_append: + - files_virtual_provider +% endif default_tool: verilator parameters: - SYNTHESIS=true @@ -95,4 +105,7 @@ targets: formal: filesets: - files_rtl +% if len(virtual_provider) > 0: + - files_virtual_provider +% endif toplevel: pinmux_tb diff --git a/hw/ip_templates/pwrmgr/data/pwrmgr.tpldesc.hjson b/hw/ip_templates/pwrmgr/data/pwrmgr.tpldesc.hjson index f931e04e60a41..d52b46a6a7017 100644 --- a/hw/ip_templates/pwrmgr/data/pwrmgr.tpldesc.hjson +++ b/hw/ip_templates/pwrmgr/data/pwrmgr.tpldesc.hjson @@ -65,14 +65,8 @@ default: "1" } { - name: "alert_handler_instance_name" - desc: "Instance name for the alert_handler dependencies, if available" - type: "string" - default: "" - } - { - name: "clkmgr_instance_name" - desc: "Instance name for the clkmgr dependencies, if available" + name: "virtual_provider" + desc: "VLNV providing all virtual cores, used with fileset_top flag" type: "string" default: "" } diff --git a/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core.tpl b/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core.tpl index fade73ffd5b40..51754d38b805f 100644 --- a/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core.tpl +++ b/hw/ip_templates/pwrmgr/dv/pwrmgr_sim.core.tpl @@ -17,19 +17,10 @@ filesets: - tb.sv - cov/pwrmgr_cov_bind.sv file_type: systemVerilogSource -<% - have_files_top_sim = (len(clkmgr_instance_name) > 0 or - len(alert_handler_instance_name) > 0) -%>\ -% if have_files_top_sim: - files_top_sim: +% if len(virtual_provider) > 0: + files_virtual_provider: depend: -% if len(alert_handler_instance_name) > 0: - - "fileset_top ? (${instance_vlnv("lowrisc:ip:alert_handler_pkg:0.1", alert_handler_instance_name)})" -% endif -% if len(clkmgr_instance_name) > 0: - - "fileset_top ? (${instance_vlnv("lowrisc:ip:clkmgr_pwrmgr_sva_if:0.1", clkmgr_instance_name)})" -% endif + - "fileset_top ? (${virtual_provider})" % endif targets: @@ -38,8 +29,8 @@ targets: filesets: - files_rtl - files_dv -% if have_files_top_sim: - - files_top_sim +% if len(virtual_provider) > 0: + - files_virtual_provider % endif default_tool: vcs diff --git a/hw/ip_templates/pwrmgr/pwrmgr.core.tpl b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl index 51ee2e7edc95a..d079765b5037f 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr.core.tpl +++ b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl @@ -15,10 +15,10 @@ filesets: - ${instance_vlnv("lowrisc:ip:pwrmgr_component:0.1")} file_type: systemVerilogSource -% if len(alert_handler_instance_name) > 0: - files_top_lint: +% if len(virtual_provider) > 0: + files_virtual_provider: depend: - - "fileset_top ? (${instance_vlnv("lowrisc:ip:alert_handler_pkg:0.1", alert_handler_instance_name)})" + - "fileset_top ? (${virtual_provider})" % endif files_verilator_waiver: @@ -62,9 +62,9 @@ targets: lint: <<: *default_target -% if len(alert_handler_instance_name) > 0: +% if len(virtual_provider) > 0: filesets_append: - - files_top_lint + - files_virtual_provider % endif default_tool: verilator parameters: diff --git a/hw/ip_templates/rstmgr/data/rstmgr.tpldesc.hjson b/hw/ip_templates/rstmgr/data/rstmgr.tpldesc.hjson index af581f8dc7f1d..3432eb0f0cf39 100644 --- a/hw/ip_templates/rstmgr/data/rstmgr.tpldesc.hjson +++ b/hw/ip_templates/rstmgr/data/rstmgr.tpldesc.hjson @@ -118,14 +118,8 @@ default: "1" } { - name: "alert_handler_instance_name" - desc: "Instance name for the alert_handler dependencies, if available" - type: "string" - default: "" - } - { - name: "pwrmgr_instance_name" - desc: "Instance name for the pwrmgr dependencies, if available" + name: "virtual_provider" + desc: "VLNV providing all virtual cores, used with fileset_top flag" type: "string" default: "" } diff --git a/hw/ip_templates/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core.tpl b/hw/ip_templates/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core.tpl index b93f30838335a..66d23f2991503 100644 --- a/hw/ip_templates/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core.tpl +++ b/hw/ip_templates/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core.tpl @@ -20,12 +20,21 @@ filesets: - tb.sv file_type: systemVerilogSource +% if len(virtual_provider) > 0: + files_virtual_provider: + depend: + - "fileset_top ? (${virtual_provider})" +% endif + targets: sim: &sim_target toplevel: tb filesets: - files_rtl - files_dv +% if len(virtual_provider) > 0: + - files_virtual_provider +% endif default_tool: vcs lint: diff --git a/hw/ip_templates/rstmgr/dv/rstmgr_sim.core.tpl b/hw/ip_templates/rstmgr/dv/rstmgr_sim.core.tpl index 108e1f673c480..61d1fad33038a 100644 --- a/hw/ip_templates/rstmgr/dv/rstmgr_sim.core.tpl +++ b/hw/ip_templates/rstmgr/dv/rstmgr_sim.core.tpl @@ -17,20 +17,10 @@ filesets: - tb.sv - cov/rstmgr_cov_bind.sv file_type: systemVerilogSource -<% - have_files_top_sim = (len(alert_handler_instance_name) > 0 or - len(pwrmgr_instance_name) > 0) -%>\ -% if have_files_top_sim: - files_top_sim: +% if len(virtual_provider) > 0: + files_virtual_provider: depend: -% if len(alert_handler_instance_name) > 0: - - "fileset_top ? (${instance_vlnv("lowrisc:ip:alert_handler_pkg:0.1", alert_handler_instance_name)})" -% endif -% if len(pwrmgr_instance_name) > 0: - - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1", pwrmgr_instance_name)})" - - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_rstmgr_sva_if:0.1", pwrmgr_instance_name)})" -% endif + - "fileset_top ? (${virtual_provider})" % endif targets: @@ -39,8 +29,8 @@ targets: filesets: - files_rtl - files_dv -% if have_files_top_sim: - - files_top_sim +% if len(virtual_provider) > 0: + - files_virtual_provider % endif default_tool: vcs diff --git a/hw/ip_templates/rstmgr/rstmgr.core.tpl b/hw/ip_templates/rstmgr/rstmgr.core.tpl index 738a7e4f3ff20..563238d8d5629 100644 --- a/hw/ip_templates/rstmgr/rstmgr.core.tpl +++ b/hw/ip_templates/rstmgr/rstmgr.core.tpl @@ -30,19 +30,10 @@ filesets: - rtl/rstmgr.sv file_type: systemVerilogSource -<% - have_files_top_lint = (len(alert_handler_instance_name) > 0 or - len(pwrmgr_instance_name) > 0) -%>\ -% if have_files_top_lint: - files_top_lint: +% if len(virtual_provider) > 0: + files_virtual_provider: depend: -% if len(alert_handler_instance_name) > 0: - - "fileset_top ? (${instance_vlnv("lowrisc:ip:alert_handler_pkg:0.1", alert_handler_instance_name)})" -% endif -% if len(pwrmgr_instance_name) > 0: - - "fileset_top ? (${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1", pwrmgr_instance_name)})" -% endif + - "fileset_top ? (${virtual_provider})" % endif files_verilator_waiver: @@ -76,9 +67,9 @@ targets: lint: <<: *default_target -% if have_files_top_lint: +% if len(virtual_provider) > 0: filesets_append: - - files_top_lint + - files_virtual_provider % endif default_tool: verilator parameters: diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/alert_handler.core b/hw/top_darjeeling/ip_autogen/alert_handler/alert_handler.core index 4cb7db5b0d601..b75a0faa8a4d6 100644 --- a/hw/top_darjeeling/ip_autogen/alert_handler/alert_handler.core +++ b/hw/top_darjeeling/ip_autogen/alert_handler/alert_handler.core @@ -13,6 +13,9 @@ filesets: - lowrisc:opentitan:top_darjeeling_alert_handler_component:0.1 - lowrisc:opentitan:top_darjeeling_alert_handler_reg:0.1 file_type: systemVerilogSource + files_virtual_provider: + depend: + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_virtual_provider)" parameters: SYNTHESIS: @@ -28,6 +31,8 @@ targets: lint: <<: *default_target + filesets_append: + - files_virtual_provider default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/data/top_darjeeling_alert_handler.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/alert_handler/data/top_darjeeling_alert_handler.ipconfig.hjson index de9285f5cb8de..6b43b9001e6dc 100644 --- a/hw/top_darjeeling/ip_autogen/alert_handler/data/top_darjeeling_alert_handler.ipconfig.hjson +++ b/hw/top_darjeeling/ip_autogen/alert_handler/data/top_darjeeling_alert_handler.ipconfig.hjson @@ -218,6 +218,7 @@ 5'd11 5'd11 ] + virtual_provider: lowrisc:opentitan:top_darjeeling_virtual_provider topname: darjeeling } } diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/alert_handler_sim.core b/hw/top_darjeeling/ip_autogen/alert_handler/dv/alert_handler_sim.core index 5149ef2a72be4..a74c89c8285c3 100644 --- a/hw/top_darjeeling/ip_autogen/alert_handler/dv/alert_handler_sim.core +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/alert_handler_sim.core @@ -18,6 +18,10 @@ filesets: - lowrisc:opentitan:top_darjeeling_alert_handler_sva:0.1 file_type: systemVerilogSource + files_virtual_provider: + depend: + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_virtual_provider)" + generate: ral: generator: ralgen @@ -31,6 +35,7 @@ targets: filesets: - files_rtl - files_dv + - files_virtual_provider generate: - ral default_tool: vcs diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core index 721b801f11f0d..b41e74aa3c302 100644 --- a/hw/top_darjeeling/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core +++ b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core @@ -14,6 +14,9 @@ filesets: - tb/alert_handler_esc_timer_bind_fpv.sv - tb/alert_handler_esc_timer_tb.sv file_type: systemVerilogSource + files_virtual_provider: + depend: + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_virtual_provider)" targets: default: &default_target @@ -26,6 +29,10 @@ targets: formal: <<: *default_target + filesets_append: + - files_virtual_provider lint: <<: *default_target + filesets_append: + - files_virtual_provider diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core index 60f051f50e2e1..2583aa02d5b45 100644 --- a/hw/top_darjeeling/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core +++ b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core @@ -14,6 +14,9 @@ filesets: - tb/alert_handler_ping_timer_bind_fpv.sv - tb/alert_handler_ping_timer_tb.sv file_type: systemVerilogSource + files_virtual_provider: + depend: + - "lowrisc:opentitan:top_darjeeling_virtual_provider" targets: default: &default_target @@ -26,6 +29,10 @@ targets: formal: <<: *default_target + filesets_append: + - files_virtual_provider lint: <<: *default_target + filesets_append: + - files_virtual_provider diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr.core b/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr.core index a7f8d1ff70b39..5d35c83c4a53d 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr.core +++ b/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr.core @@ -33,9 +33,9 @@ filesets: - rtl/clkmgr_trans.sv file_type: systemVerilogSource - files_top_lint: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_darjeeling_pwrmgr_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_virtual_provider)" files_verilator_waiver: depend: @@ -68,7 +68,7 @@ targets: lint: <<: *default_target filesets_append: - - files_top_lint + - files_virtual_provider default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/data/top_darjeeling_clkmgr.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/clkmgr/data/top_darjeeling_clkmgr.ipconfig.hjson index fbd89cd3a9290..b4d53011fb0e4 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/data/top_darjeeling_clkmgr.ipconfig.hjson +++ b/hw/top_darjeeling/ip_autogen/clkmgr/data/top_darjeeling_clkmgr.ipconfig.hjson @@ -249,7 +249,7 @@ exported_clks: {} number_of_clock_groups: 7 with_alert_handler: true - pwrmgr_instance_name: top_darjeeling_ + virtual_provider: lowrisc:opentitan:top_darjeeling_virtual_provider topname: darjeeling } } diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim.core b/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim.core index bf1983886e43a..d0fbd5d7e5680 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim.core +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim.core @@ -18,9 +18,9 @@ filesets: - cov/clkmgr_cov_bind.sv file_type: systemVerilogSource - files_top_sim: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_darjeeling_pwrmgr_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_virtual_provider)" targets: sim: &sim_target @@ -28,7 +28,7 @@ targets: filesets: - files_rtl - files_dv - - files_top_sim + - files_virtual_provider default_tool: vcs lint: diff --git a/hw/top_darjeeling/ip_autogen/pinmux/data/top_darjeeling_pinmux.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/pinmux/data/top_darjeeling_pinmux.ipconfig.hjson index 45b4885cd88ba..934e249d20692 100644 --- a/hw/top_darjeeling/ip_autogen/pinmux/data/top_darjeeling_pinmux.ipconfig.hjson +++ b/hw/top_darjeeling/ip_autogen/pinmux/data/top_darjeeling_pinmux.ipconfig.hjson @@ -15,6 +15,7 @@ n_dio_periph_out: 57 enable_usb_wakeup: false enable_strap_sampling: false + virtual_provider: lowrisc:opentitan:top_darjeeling_virtual_provider topname: darjeeling } } diff --git a/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_chip_fpv.core b/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_chip_fpv.core index b925f9c68c586..8de96d60e81ec 100644 --- a/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_chip_fpv.core +++ b/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_chip_fpv.core @@ -20,6 +20,9 @@ filesets: files: - tb/pinmux_chip_tb.sv file_type: systemVerilogSource + files_virtual_provider: + depend: + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_virtual_provider)" generate: csr_assert_gen: @@ -38,6 +41,10 @@ targets: formal: <<: *default_target + filesets_append: + - files_virtual_provider lint: <<: *default_target + filesets_append: + - files_virtual_provider diff --git a/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_fpv.core b/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_fpv.core index b69ef24a4d80b..3f6ea7540970f 100644 --- a/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_fpv.core +++ b/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_fpv.core @@ -16,6 +16,9 @@ filesets: files: - tb/pinmux_tb.sv file_type: systemVerilogSource + files_virtual_provider: + depend: + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_virtual_provider)" generate: csr_assert_gen: @@ -34,6 +37,10 @@ targets: formal: <<: *default_target + filesets_append: + - files_virtual_provider lint: <<: *default_target + filesets_append: + - files_virtual_provider diff --git a/hw/top_darjeeling/ip_autogen/pinmux/pinmux.core b/hw/top_darjeeling/ip_autogen/pinmux/pinmux.core index 53c06b9133499..52642d59dea04 100644 --- a/hw/top_darjeeling/ip_autogen/pinmux/pinmux.core +++ b/hw/top_darjeeling/ip_autogen/pinmux/pinmux.core @@ -31,6 +31,10 @@ filesets: - rtl/pinmux.sv file_type: systemVerilogSource + files_virtual_provider: + depend: + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_virtual_provider)" + files_verilator_waiver: depend: # common waivers @@ -71,6 +75,8 @@ targets: lint: <<: *default_target + filesets_append: + - files_virtual_provider default_tool: verilator parameters: - SYNTHESIS=true @@ -92,4 +98,5 @@ targets: formal: filesets: - files_rtl + - files_virtual_provider toplevel: pinmux_tb diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/data/top_darjeeling_pwrmgr.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/pwrmgr/data/top_darjeeling_pwrmgr.ipconfig.hjson index 9a7c1dc8750ee..87123e156dcfb 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/data/top_darjeeling_pwrmgr.ipconfig.hjson +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/data/top_darjeeling_pwrmgr.ipconfig.hjson @@ -76,8 +76,7 @@ NumRstReqs: 2 wait_for_external_reset: true NumRomInputs: 3 - alert_handler_instance_name: top_darjeeling_ - clkmgr_instance_name: top_darjeeling_ + virtual_provider: lowrisc:opentitan:top_darjeeling_virtual_provider topname: darjeeling } } diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim.core b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim.core index 6d2a139965635..d729467d760ff 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim.core +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim.core @@ -17,10 +17,9 @@ filesets: - tb.sv - cov/pwrmgr_cov_bind.sv file_type: systemVerilogSource - files_top_sim: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_darjeeling_alert_handler_pkg:0.1)" - - "fileset_top ? (lowrisc:opentitan:top_darjeeling_clkmgr_pwrmgr_sva_if:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_virtual_provider)" targets: sim: &sim_target @@ -28,7 +27,7 @@ targets: filesets: - files_rtl - files_dv - - files_top_sim + - files_virtual_provider default_tool: vcs lint: diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core index 9792c62ab170f..d8dee19cd390d 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core @@ -15,9 +15,9 @@ filesets: - lowrisc:opentitan:top_darjeeling_pwrmgr_component:0.1 file_type: systemVerilogSource - files_top_lint: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_darjeeling_alert_handler_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_virtual_provider)" files_verilator_waiver: depend: @@ -61,7 +61,7 @@ targets: lint: <<: *default_target filesets_append: - - files_top_lint + - files_virtual_provider default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/data/top_darjeeling_rstmgr.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/rstmgr/data/top_darjeeling_rstmgr.ipconfig.hjson index 5e6bfe0e4421c..a8c385a923fb1 100644 --- a/hw/top_darjeeling/ip_autogen/rstmgr/data/top_darjeeling_rstmgr.ipconfig.hjson +++ b/hw/top_darjeeling/ip_autogen/rstmgr/data/top_darjeeling_rstmgr.ipconfig.hjson @@ -544,8 +544,7 @@ rst_ni: lc_io_div4 export_rsts: {} with_alert_handler: true - pwrmgr_instance_name: top_darjeeling_ - alert_handler_instance_name: top_darjeeling_ + virtual_provider: lowrisc:opentitan:top_darjeeling_virtual_provider topname: darjeeling } } diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core index bf67489028e83..3bc8b3f533ed7 100644 --- a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core @@ -20,12 +20,17 @@ filesets: - tb.sv file_type: systemVerilogSource + files_virtual_provider: + depend: + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_virtual_provider)" + targets: sim: &sim_target toplevel: tb filesets: - files_rtl - files_dv + - files_virtual_provider default_tool: vcs lint: diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim.core b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim.core index 38bb1f1ee6099..4ef2ad932ff85 100644 --- a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim.core +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim.core @@ -17,11 +17,9 @@ filesets: - tb.sv - cov/rstmgr_cov_bind.sv file_type: systemVerilogSource - files_top_sim: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_darjeeling_alert_handler_pkg:0.1)" - - "fileset_top ? (lowrisc:opentitan:top_darjeeling_pwrmgr_pkg:0.1)" - - "fileset_top ? (lowrisc:opentitan:top_darjeeling_pwrmgr_rstmgr_sva_if:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_virtual_provider)" targets: sim: &sim_target @@ -29,7 +27,7 @@ targets: filesets: - files_rtl - files_dv - - files_top_sim + - files_virtual_provider default_tool: vcs lint: diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr.core b/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr.core index e14fe3d63f097..bef5d46b41134 100644 --- a/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr.core +++ b/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr.core @@ -30,10 +30,9 @@ filesets: - rtl/rstmgr.sv file_type: systemVerilogSource - files_top_lint: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_darjeeling_alert_handler_pkg:0.1)" - - "fileset_top ? (lowrisc:opentitan:top_darjeeling_pwrmgr_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_darjeeling_virtual_provider)" files_verilator_waiver: depend: @@ -67,7 +66,7 @@ targets: lint: <<: *default_target filesets_append: - - files_top_lint + - files_virtual_provider default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_earlgrey/dv/top_earlgrey_ast_top.core b/hw/top_earlgrey/dv/top_earlgrey_ast_top.core index 2591767bfc36f..07c325856ac69 100644 --- a/hw/top_earlgrey/dv/top_earlgrey_ast_top.core +++ b/hw/top_earlgrey/dv/top_earlgrey_ast_top.core @@ -7,10 +7,7 @@ description: "Pseudo top-level for Earl Grey's ast" filesets: files_rtl: depend: - - lowrisc:opentitan:top_earlgrey_alert_handler_pkg - - lowrisc:opentitan:top_earlgrey_clkmgr_pkg - - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg - - lowrisc:opentitan:top_earlgrey_rstmgr_pkg + - lowrisc:opentitan:top_earlgrey_virtual_provider - lowrisc:systems:top_earlgrey_ast parameters: diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/alert_handler.core b/hw/top_earlgrey/ip_autogen/alert_handler/alert_handler.core index 1e80faadc2023..6f0ae09f8404a 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/alert_handler.core +++ b/hw/top_earlgrey/ip_autogen/alert_handler/alert_handler.core @@ -13,6 +13,9 @@ filesets: - lowrisc:opentitan:top_earlgrey_alert_handler_component:0.1 - lowrisc:opentitan:top_earlgrey_alert_handler_reg:0.1 file_type: systemVerilogSource + files_virtual_provider: + depend: + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_virtual_provider)" parameters: SYNTHESIS: @@ -28,6 +31,8 @@ targets: lint: <<: *default_target + filesets_append: + - files_virtual_provider default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson index cc3460faa0f24..1683ed5299814 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson @@ -146,6 +146,7 @@ 5'd17 5'd17 ] + virtual_provider: lowrisc:opentitan:top_earlgrey_virtual_provider topname: earlgrey } } diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/dv/alert_handler_sim.core b/hw/top_earlgrey/ip_autogen/alert_handler/dv/alert_handler_sim.core index 3fcb58c848f13..3454284ab3c62 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/dv/alert_handler_sim.core +++ b/hw/top_earlgrey/ip_autogen/alert_handler/dv/alert_handler_sim.core @@ -18,6 +18,10 @@ filesets: - lowrisc:opentitan:top_earlgrey_alert_handler_sva:0.1 file_type: systemVerilogSource + files_virtual_provider: + depend: + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_virtual_provider)" + generate: ral: generator: ralgen @@ -31,6 +35,7 @@ targets: filesets: - files_rtl - files_dv + - files_virtual_provider generate: - ral default_tool: vcs diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core b/hw/top_earlgrey/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core index abdcd1f4cfd63..635857a84fa46 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core +++ b/hw/top_earlgrey/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core @@ -14,6 +14,9 @@ filesets: - tb/alert_handler_esc_timer_bind_fpv.sv - tb/alert_handler_esc_timer_tb.sv file_type: systemVerilogSource + files_virtual_provider: + depend: + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_virtual_provider)" targets: default: &default_target @@ -26,6 +29,10 @@ targets: formal: <<: *default_target + filesets_append: + - files_virtual_provider lint: <<: *default_target + filesets_append: + - files_virtual_provider diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core b/hw/top_earlgrey/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core index 354bd11a23cc3..c21340afc87c5 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core +++ b/hw/top_earlgrey/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core @@ -14,6 +14,9 @@ filesets: - tb/alert_handler_ping_timer_bind_fpv.sv - tb/alert_handler_ping_timer_tb.sv file_type: systemVerilogSource + files_virtual_provider: + depend: + - "lowrisc:opentitan:top_earlgrey_virtual_provider" targets: default: &default_target @@ -26,6 +29,10 @@ targets: formal: <<: *default_target + filesets_append: + - files_virtual_provider lint: <<: *default_target + filesets_append: + - files_virtual_provider diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/clkmgr.core b/hw/top_earlgrey/ip_autogen/clkmgr/clkmgr.core index 86f43359442ae..40d7428eb8f9a 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/clkmgr.core +++ b/hw/top_earlgrey/ip_autogen/clkmgr/clkmgr.core @@ -33,9 +33,9 @@ filesets: - rtl/clkmgr_trans.sv file_type: systemVerilogSource - files_top_lint: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_virtual_provider)" files_verilator_waiver: depend: @@ -68,7 +68,7 @@ targets: lint: <<: *default_target filesets_append: - - files_top_lint + - files_virtual_provider default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/data/top_earlgrey_clkmgr.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/clkmgr/data/top_earlgrey_clkmgr.ipconfig.hjson index 6cb9e59ffaf7d..3f3298b265213 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/data/top_earlgrey_clkmgr.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/clkmgr/data/top_earlgrey_clkmgr.ipconfig.hjson @@ -259,7 +259,7 @@ exported_clks: {} number_of_clock_groups: 7 with_alert_handler: true - pwrmgr_instance_name: top_earlgrey_ + virtual_provider: lowrisc:opentitan:top_earlgrey_virtual_provider topname: earlgrey } } diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim.core b/hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim.core index fde2c0651f1ae..741caf0abc68d 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim.core +++ b/hw/top_earlgrey/ip_autogen/clkmgr/dv/clkmgr_sim.core @@ -18,9 +18,9 @@ filesets: - cov/clkmgr_cov_bind.sv file_type: systemVerilogSource - files_top_sim: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_virtual_provider)" targets: sim: &sim_target @@ -28,7 +28,7 @@ targets: filesets: - files_rtl - files_dv - - files_top_sim + - files_virtual_provider default_tool: vcs lint: diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/data/top_earlgrey_flash_ctrl.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/flash_ctrl/data/top_earlgrey_flash_ctrl.ipconfig.hjson index 2a109eaf2e67a..453e3911e426a 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/data/top_earlgrey_flash_ctrl.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/data/top_earlgrey_flash_ctrl.ipconfig.hjson @@ -23,7 +23,7 @@ bytes_per_page: 2048 bytes_per_bank: 524288 size: 1048576 - pwrmgr_instance_name: top_earlgrey_ + virtual_provider: lowrisc:opentitan:top_earlgrey_virtual_provider topname: earlgrey } } diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core index 2ef5cf57bd6d3..bcfd94d560ba8 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core @@ -22,9 +22,9 @@ filesets: - tb/tb.sv file_type: systemVerilogSource - files_top_sim: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_virtual_provider)" targets: default: &default_target @@ -36,10 +36,10 @@ targets: sim: <<: *default_target filesets_append: - - files_top_sim + - files_virtual_provider default_tool: vcs lint: <<: *default_target filesets_append: - - files_top_sim + - files_virtual_provider diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core index 6918ebd7426c0..dc2013be83bc4 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core @@ -46,9 +46,9 @@ filesets: - rtl/flash_phy_scramble.sv file_type: systemVerilogSource - files_top_lint: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_virtual_provider)" files_verilator_waiver: depend: @@ -92,7 +92,7 @@ targets: lint: <<: *default_target filesets_append: - - files_top_lint + - files_virtual_provider default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_earlgrey/ip_autogen/pinmux/data/top_earlgrey_pinmux.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/pinmux/data/top_earlgrey_pinmux.ipconfig.hjson index ebb1d3e3ff553..feb6a43177463 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/data/top_earlgrey_pinmux.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/pinmux/data/top_earlgrey_pinmux.ipconfig.hjson @@ -15,6 +15,7 @@ n_dio_periph_out: 14 enable_usb_wakeup: true enable_strap_sampling: true + virtual_provider: lowrisc:opentitan:top_earlgrey_virtual_provider topname: earlgrey } } diff --git a/hw/top_earlgrey/ip_autogen/pinmux/fpv/pinmux_chip_fpv.core b/hw/top_earlgrey/ip_autogen/pinmux/fpv/pinmux_chip_fpv.core index 921efb177462e..1255f9d5b5ff3 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/fpv/pinmux_chip_fpv.core +++ b/hw/top_earlgrey/ip_autogen/pinmux/fpv/pinmux_chip_fpv.core @@ -20,6 +20,9 @@ filesets: files: - tb/pinmux_chip_tb.sv file_type: systemVerilogSource + files_virtual_provider: + depend: + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_virtual_provider)" generate: csr_assert_gen: @@ -38,6 +41,10 @@ targets: formal: <<: *default_target + filesets_append: + - files_virtual_provider lint: <<: *default_target + filesets_append: + - files_virtual_provider diff --git a/hw/top_earlgrey/ip_autogen/pinmux/fpv/pinmux_fpv.core b/hw/top_earlgrey/ip_autogen/pinmux/fpv/pinmux_fpv.core index 91de43b71ffa8..d28b576df3bf4 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/fpv/pinmux_fpv.core +++ b/hw/top_earlgrey/ip_autogen/pinmux/fpv/pinmux_fpv.core @@ -16,6 +16,9 @@ filesets: files: - tb/pinmux_tb.sv file_type: systemVerilogSource + files_virtual_provider: + depend: + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_virtual_provider)" generate: csr_assert_gen: @@ -34,6 +37,10 @@ targets: formal: <<: *default_target + filesets_append: + - files_virtual_provider lint: <<: *default_target + filesets_append: + - files_virtual_provider diff --git a/hw/top_earlgrey/ip_autogen/pinmux/pinmux.core b/hw/top_earlgrey/ip_autogen/pinmux/pinmux.core index a9882615b1e0a..588412538fa96 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/pinmux.core +++ b/hw/top_earlgrey/ip_autogen/pinmux/pinmux.core @@ -32,6 +32,10 @@ filesets: - rtl/pinmux.sv file_type: systemVerilogSource + files_virtual_provider: + depend: + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_virtual_provider)" + files_verilator_waiver: depend: # common waivers @@ -72,6 +76,8 @@ targets: lint: <<: *default_target + filesets_append: + - files_virtual_provider default_tool: verilator parameters: - SYNTHESIS=true @@ -93,4 +99,5 @@ targets: formal: filesets: - files_rtl + - files_virtual_provider toplevel: pinmux_tb diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/data/top_earlgrey_pwrmgr.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/pwrmgr/data/top_earlgrey_pwrmgr.ipconfig.hjson index 085dbf58bb138..06e232dd1b0c5 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/data/top_earlgrey_pwrmgr.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/data/top_earlgrey_pwrmgr.ipconfig.hjson @@ -81,8 +81,7 @@ NumRstReqs: 2 wait_for_external_reset: false NumRomInputs: 1 - alert_handler_instance_name: top_earlgrey_ - clkmgr_instance_name: top_earlgrey_ + virtual_provider: lowrisc:opentitan:top_earlgrey_virtual_provider topname: earlgrey } } diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core index 9694595a9e5f3..c756a4f9f3d15 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim.core @@ -17,10 +17,9 @@ filesets: - tb.sv - cov/pwrmgr_cov_bind.sv file_type: systemVerilogSource - files_top_sim: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_earlgrey_alert_handler_pkg:0.1)" - - "fileset_top ? (lowrisc:opentitan:top_earlgrey_clkmgr_pwrmgr_sva_if:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_virtual_provider)" targets: sim: &sim_target @@ -28,7 +27,7 @@ targets: filesets: - files_rtl - files_dv - - files_top_sim + - files_virtual_provider default_tool: vcs lint: diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core index a2c5aecad7d93..0a12da4275d46 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core @@ -15,9 +15,9 @@ filesets: - lowrisc:opentitan:top_earlgrey_pwrmgr_component:0.1 file_type: systemVerilogSource - files_top_lint: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_earlgrey_alert_handler_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_virtual_provider)" files_verilator_waiver: depend: @@ -61,7 +61,7 @@ targets: lint: <<: *default_target filesets_append: - - files_top_lint + - files_virtual_provider default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/data/top_earlgrey_rstmgr.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/rstmgr/data/top_earlgrey_rstmgr.ipconfig.hjson index 9210ae5f22ed3..f40823a6354f5 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/data/top_earlgrey_rstmgr.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/rstmgr/data/top_earlgrey_rstmgr.ipconfig.hjson @@ -691,8 +691,7 @@ rst_ni: lc_io_div4 export_rsts: {} with_alert_handler: true - pwrmgr_instance_name: top_earlgrey_ - alert_handler_instance_name: top_earlgrey_ + virtual_provider: lowrisc:opentitan:top_earlgrey_virtual_provider topname: earlgrey } } diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core b/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core index 827446a73f4c4..e9bef1e8c60f2 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core +++ b/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core @@ -20,12 +20,17 @@ filesets: - tb.sv file_type: systemVerilogSource + files_virtual_provider: + depend: + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_virtual_provider)" + targets: sim: &sim_target toplevel: tb filesets: - files_rtl - files_dv + - files_virtual_provider default_tool: vcs lint: diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_sim.core b/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_sim.core index e66d672b7182d..d775c0021b75a 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_sim.core +++ b/hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_sim.core @@ -17,11 +17,9 @@ filesets: - tb.sv - cov/rstmgr_cov_bind.sv file_type: systemVerilogSource - files_top_sim: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_earlgrey_alert_handler_pkg:0.1)" - - "fileset_top ? (lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1)" - - "fileset_top ? (lowrisc:opentitan:top_earlgrey_pwrmgr_rstmgr_sva_if:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_virtual_provider)" targets: sim: &sim_target @@ -29,7 +27,7 @@ targets: filesets: - files_rtl - files_dv - - files_top_sim + - files_virtual_provider default_tool: vcs lint: diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/rstmgr.core b/hw/top_earlgrey/ip_autogen/rstmgr/rstmgr.core index 67707db194234..5454652047e59 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/rstmgr.core +++ b/hw/top_earlgrey/ip_autogen/rstmgr/rstmgr.core @@ -30,10 +30,9 @@ filesets: - rtl/rstmgr.sv file_type: systemVerilogSource - files_top_lint: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_earlgrey_alert_handler_pkg:0.1)" - - "fileset_top ? (lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_earlgrey_virtual_provider)" files_verilator_waiver: depend: @@ -67,7 +66,7 @@ targets: lint: <<: *default_target filesets_append: - - files_top_lint + - files_virtual_provider default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_earlgrey/top_earlgrey_virtual_provider.core b/hw/top_earlgrey/top_earlgrey_virtual_provider.core new file mode 100644 index 0000000000000..ebf754b50732b --- /dev/null +++ b/hw/top_earlgrey/top_earlgrey_virtual_provider.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:opentitan:top_earlgrey_virtual_provider:0.1" +description: "Virtual core library provider for Earl Grey" +filesets: + files_rtl_generic: + depend: + - lowrisc:systems:top_earlgrey_racl_pkg + - lowrisc:opentitan:top_earlgrey_alert_handler_reg + - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg + - lowrisc:constants:top_earlgrey_top_pkg + - lowrisc:constants:top_earlgrey_jtag_id_pkg + - lowrisc:constants:top_earlgrey_ibex_pmp_reset_pkg + - lowrisc:opentitan:top_earlgrey_alert_handler + - lowrisc:opentitan:top_earlgrey_clkmgr + - lowrisc:opentitan:top_earlgrey_flash_ctrl + - lowrisc:opentitan:top_earlgrey_rstmgr + - lowrisc:opentitan:top_earlgrey_rv_plic + - lowrisc:opentitan:top_earlgrey_pinmux + - lowrisc:opentitan:top_earlgrey_pwrmgr + - lowrisc:systems:top_earlgrey_sensor_ctrl + - "fileset_partner ? (partner:systems:top_earlgrey_ast_pkg)" + - "!fileset_partner ? (lowrisc:systems:top_earlgrey_ast_pkg)" + +targets: + default: &default_target + filesets: + - files_rtl_generic diff --git a/hw/top_englishbreakfast/ip_autogen/clkmgr/clkmgr.core b/hw/top_englishbreakfast/ip_autogen/clkmgr/clkmgr.core index 0588cafcce347..91cdd5a50f0cc 100644 --- a/hw/top_englishbreakfast/ip_autogen/clkmgr/clkmgr.core +++ b/hw/top_englishbreakfast/ip_autogen/clkmgr/clkmgr.core @@ -33,9 +33,9 @@ filesets: - rtl/clkmgr_trans.sv file_type: systemVerilogSource - files_top_lint: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_pwrmgr_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_virtual_provider)" files_verilator_waiver: depend: @@ -68,7 +68,7 @@ targets: lint: <<: *default_target filesets_append: - - files_top_lint + - files_virtual_provider default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_englishbreakfast/ip_autogen/clkmgr/data/top_englishbreakfast_clkmgr.ipconfig.hjson b/hw/top_englishbreakfast/ip_autogen/clkmgr/data/top_englishbreakfast_clkmgr.ipconfig.hjson index c272dd834b45b..93431632ef17f 100644 --- a/hw/top_englishbreakfast/ip_autogen/clkmgr/data/top_englishbreakfast_clkmgr.ipconfig.hjson +++ b/hw/top_englishbreakfast/ip_autogen/clkmgr/data/top_englishbreakfast_clkmgr.ipconfig.hjson @@ -236,7 +236,7 @@ exported_clks: {} number_of_clock_groups: 8 with_alert_handler: false - pwrmgr_instance_name: top_englishbreakfast_ + virtual_provider: lowrisc:opentitan:top_englishbreakfast_virtual_provider topname: englishbreakfast } } diff --git a/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/clkmgr_sim.core b/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/clkmgr_sim.core index 7cbf3b11b39a0..361a10e3fe714 100644 --- a/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/clkmgr_sim.core +++ b/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/clkmgr_sim.core @@ -18,9 +18,9 @@ filesets: - cov/clkmgr_cov_bind.sv file_type: systemVerilogSource - files_top_sim: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_pwrmgr_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_virtual_provider)" targets: sim: &sim_target @@ -28,7 +28,7 @@ targets: filesets: - files_rtl - files_dv - - files_top_sim + - files_virtual_provider default_tool: vcs lint: diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/data/top_englishbreakfast_flash_ctrl.ipconfig.hjson b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/data/top_englishbreakfast_flash_ctrl.ipconfig.hjson index 9ff864170933b..564785071b874 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/data/top_englishbreakfast_flash_ctrl.ipconfig.hjson +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/data/top_englishbreakfast_flash_ctrl.ipconfig.hjson @@ -23,7 +23,7 @@ bytes_per_page: 2048 bytes_per_bank: 32768 size: 65536 - pwrmgr_instance_name: top_englishbreakfast_ + virtual_provider: lowrisc:opentitan:top_englishbreakfast_virtual_provider topname: englishbreakfast } } diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core index d0c35710b30a8..96af7d38b2714 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/flash_ctrl_sim.core @@ -22,9 +22,9 @@ filesets: - tb/tb.sv file_type: systemVerilogSource - files_top_sim: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_pwrmgr_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_virtual_provider)" targets: default: &default_target @@ -36,10 +36,10 @@ targets: sim: <<: *default_target filesets_append: - - files_top_sim + - files_virtual_provider default_tool: vcs lint: <<: *default_target filesets_append: - - files_top_sim + - files_virtual_provider diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl.core b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl.core index 4dcae766ea9d9..3ba9a5f120754 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl.core +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl.core @@ -46,9 +46,9 @@ filesets: - rtl/flash_phy_scramble.sv file_type: systemVerilogSource - files_top_lint: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_pwrmgr_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_virtual_provider)" files_verilator_waiver: depend: @@ -92,7 +92,7 @@ targets: lint: <<: *default_target filesets_append: - - files_top_lint + - files_virtual_provider default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_englishbreakfast/ip_autogen/pinmux/data/top_englishbreakfast_pinmux.ipconfig.hjson b/hw/top_englishbreakfast/ip_autogen/pinmux/data/top_englishbreakfast_pinmux.ipconfig.hjson index 5b0de5f4731bc..665082684de5c 100644 --- a/hw/top_englishbreakfast/ip_autogen/pinmux/data/top_englishbreakfast_pinmux.ipconfig.hjson +++ b/hw/top_englishbreakfast/ip_autogen/pinmux/data/top_englishbreakfast_pinmux.ipconfig.hjson @@ -15,6 +15,7 @@ n_dio_periph_out: 12 enable_usb_wakeup: true enable_strap_sampling: true + virtual_provider: lowrisc:opentitan:top_englishbreakfast_virtual_provider topname: englishbreakfast } } diff --git a/hw/top_englishbreakfast/ip_autogen/pinmux/fpv/pinmux_chip_fpv.core b/hw/top_englishbreakfast/ip_autogen/pinmux/fpv/pinmux_chip_fpv.core index f28ad749376f4..a869a1d160b94 100644 --- a/hw/top_englishbreakfast/ip_autogen/pinmux/fpv/pinmux_chip_fpv.core +++ b/hw/top_englishbreakfast/ip_autogen/pinmux/fpv/pinmux_chip_fpv.core @@ -20,6 +20,9 @@ filesets: files: - tb/pinmux_chip_tb.sv file_type: systemVerilogSource + files_virtual_provider: + depend: + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_virtual_provider)" generate: csr_assert_gen: @@ -38,6 +41,10 @@ targets: formal: <<: *default_target + filesets_append: + - files_virtual_provider lint: <<: *default_target + filesets_append: + - files_virtual_provider diff --git a/hw/top_englishbreakfast/ip_autogen/pinmux/fpv/pinmux_fpv.core b/hw/top_englishbreakfast/ip_autogen/pinmux/fpv/pinmux_fpv.core index 756b1612f68fe..40825b444e140 100644 --- a/hw/top_englishbreakfast/ip_autogen/pinmux/fpv/pinmux_fpv.core +++ b/hw/top_englishbreakfast/ip_autogen/pinmux/fpv/pinmux_fpv.core @@ -16,6 +16,9 @@ filesets: files: - tb/pinmux_tb.sv file_type: systemVerilogSource + files_virtual_provider: + depend: + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_virtual_provider)" generate: csr_assert_gen: @@ -34,6 +37,10 @@ targets: formal: <<: *default_target + filesets_append: + - files_virtual_provider lint: <<: *default_target + filesets_append: + - files_virtual_provider diff --git a/hw/top_englishbreakfast/ip_autogen/pinmux/pinmux.core b/hw/top_englishbreakfast/ip_autogen/pinmux/pinmux.core index d69c381ed0a68..d5f16c51eac4f 100644 --- a/hw/top_englishbreakfast/ip_autogen/pinmux/pinmux.core +++ b/hw/top_englishbreakfast/ip_autogen/pinmux/pinmux.core @@ -32,6 +32,10 @@ filesets: - rtl/pinmux.sv file_type: systemVerilogSource + files_virtual_provider: + depend: + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_virtual_provider)" + files_verilator_waiver: depend: # common waivers @@ -72,6 +76,8 @@ targets: lint: <<: *default_target + filesets_append: + - files_virtual_provider default_tool: verilator parameters: - SYNTHESIS=true @@ -93,4 +99,5 @@ targets: formal: filesets: - files_rtl + - files_virtual_provider toplevel: pinmux_tb diff --git a/hw/top_englishbreakfast/ip_autogen/pwrmgr/data/top_englishbreakfast_pwrmgr.ipconfig.hjson b/hw/top_englishbreakfast/ip_autogen/pwrmgr/data/top_englishbreakfast_pwrmgr.ipconfig.hjson index 0683872adda48..5a62a17a28d34 100644 --- a/hw/top_englishbreakfast/ip_autogen/pwrmgr/data/top_englishbreakfast_pwrmgr.ipconfig.hjson +++ b/hw/top_englishbreakfast/ip_autogen/pwrmgr/data/top_englishbreakfast_pwrmgr.ipconfig.hjson @@ -60,8 +60,7 @@ NumRstReqs: 1 wait_for_external_reset: false NumRomInputs: 1 - alert_handler_instance_name: top_englishbreakfast_ - clkmgr_instance_name: top_englishbreakfast_ + virtual_provider: lowrisc:opentitan:top_englishbreakfast_virtual_provider topname: englishbreakfast } } diff --git a/hw/top_englishbreakfast/ip_autogen/pwrmgr/dv/pwrmgr_sim.core b/hw/top_englishbreakfast/ip_autogen/pwrmgr/dv/pwrmgr_sim.core index 6e7f7bfdb874b..22905c9cb5c93 100644 --- a/hw/top_englishbreakfast/ip_autogen/pwrmgr/dv/pwrmgr_sim.core +++ b/hw/top_englishbreakfast/ip_autogen/pwrmgr/dv/pwrmgr_sim.core @@ -17,10 +17,9 @@ filesets: - tb.sv - cov/pwrmgr_cov_bind.sv file_type: systemVerilogSource - files_top_sim: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_alert_handler_pkg:0.1)" - - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_clkmgr_pwrmgr_sva_if:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_virtual_provider)" targets: sim: &sim_target @@ -28,7 +27,7 @@ targets: filesets: - files_rtl - files_dv - - files_top_sim + - files_virtual_provider default_tool: vcs lint: diff --git a/hw/top_englishbreakfast/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_englishbreakfast/ip_autogen/pwrmgr/pwrmgr.core index 5bd6c18ebfb9e..d303140b22384 100644 --- a/hw/top_englishbreakfast/ip_autogen/pwrmgr/pwrmgr.core +++ b/hw/top_englishbreakfast/ip_autogen/pwrmgr/pwrmgr.core @@ -15,9 +15,9 @@ filesets: - lowrisc:opentitan:top_englishbreakfast_pwrmgr_component:0.1 file_type: systemVerilogSource - files_top_lint: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_alert_handler_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_virtual_provider)" files_verilator_waiver: depend: @@ -61,7 +61,7 @@ targets: lint: <<: *default_target filesets_append: - - files_top_lint + - files_virtual_provider default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/top_englishbreakfast/ip_autogen/rstmgr/data/top_englishbreakfast_rstmgr.ipconfig.hjson b/hw/top_englishbreakfast/ip_autogen/rstmgr/data/top_englishbreakfast_rstmgr.ipconfig.hjson index f7bfe59d1c1d3..1bc5a2a8a0d1f 100644 --- a/hw/top_englishbreakfast/ip_autogen/rstmgr/data/top_englishbreakfast_rstmgr.ipconfig.hjson +++ b/hw/top_englishbreakfast/ip_autogen/rstmgr/data/top_englishbreakfast_rstmgr.ipconfig.hjson @@ -451,7 +451,7 @@ rst_ni: lc_io_div4 export_rsts: {} with_alert_handler: false - pwrmgr_instance_name: top_englishbreakfast_ + virtual_provider: lowrisc:opentitan:top_englishbreakfast_virtual_provider topname: englishbreakfast } } diff --git a/hw/top_englishbreakfast/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core b/hw/top_englishbreakfast/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core index d6fa3b19a7431..07397a33580af 100644 --- a/hw/top_englishbreakfast/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core +++ b/hw/top_englishbreakfast/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core @@ -20,12 +20,17 @@ filesets: - tb.sv file_type: systemVerilogSource + files_virtual_provider: + depend: + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_virtual_provider)" + targets: sim: &sim_target toplevel: tb filesets: - files_rtl - files_dv + - files_virtual_provider default_tool: vcs lint: diff --git a/hw/top_englishbreakfast/ip_autogen/rstmgr/dv/rstmgr_sim.core b/hw/top_englishbreakfast/ip_autogen/rstmgr/dv/rstmgr_sim.core index 09ce2429465a9..829bdc59920b8 100644 --- a/hw/top_englishbreakfast/ip_autogen/rstmgr/dv/rstmgr_sim.core +++ b/hw/top_englishbreakfast/ip_autogen/rstmgr/dv/rstmgr_sim.core @@ -17,10 +17,9 @@ filesets: - tb.sv - cov/rstmgr_cov_bind.sv file_type: systemVerilogSource - files_top_sim: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_pwrmgr_pkg:0.1)" - - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_pwrmgr_rstmgr_sva_if:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_virtual_provider)" targets: sim: &sim_target @@ -28,7 +27,7 @@ targets: filesets: - files_rtl - files_dv - - files_top_sim + - files_virtual_provider default_tool: vcs lint: diff --git a/hw/top_englishbreakfast/ip_autogen/rstmgr/rstmgr.core b/hw/top_englishbreakfast/ip_autogen/rstmgr/rstmgr.core index 0d501b043adc8..f8f603c25a926 100644 --- a/hw/top_englishbreakfast/ip_autogen/rstmgr/rstmgr.core +++ b/hw/top_englishbreakfast/ip_autogen/rstmgr/rstmgr.core @@ -30,9 +30,9 @@ filesets: - rtl/rstmgr.sv file_type: systemVerilogSource - files_top_lint: + files_virtual_provider: depend: - - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_pwrmgr_pkg:0.1)" + - "fileset_top ? (lowrisc:opentitan:top_englishbreakfast_virtual_provider)" files_verilator_waiver: depend: @@ -66,7 +66,7 @@ targets: lint: <<: *default_target filesets_append: - - files_top_lint + - files_virtual_provider default_tool: verilator parameters: - SYNTHESIS=true diff --git a/util/topgen.py b/util/topgen.py index 8cabee966f474..d0fa568ba2366 100755 --- a/util/topgen.py +++ b/util/topgen.py @@ -227,6 +227,7 @@ def generate_alert_handler(top: Dict[str, object], out_path: Path) -> None: "n_classes": n_classes, "n_lpg": n_lpg, "lpg_map": lpg_map, + "virtual_provider": f"lowrisc:opentitan:top_{topname}_virtual_provider", } ipgen_render("alert_handler", topname, params, out_path) @@ -356,7 +357,8 @@ def generate_pinmux(top: Dict[str, object], out_path: Path) -> None: "n_dio_periph_in": n_dio_periph_in, "n_dio_periph_out": n_dio_periph_out, "enable_usb_wakeup": pinmux['enable_usb_wakeup'], - "enable_strap_sampling": pinmux['enable_strap_sampling'] + "enable_strap_sampling": pinmux['enable_strap_sampling'], + "virtual_provider": f"lowrisc:opentitan:top_{topname}_virtual_provider", } ipgen_render("pinmux", topname, params, out_path) @@ -393,7 +395,7 @@ def generate_clkmgr(topcfg: Dict[str, object], out_path: Path) -> None: "exported_clks": topcfg["exported_clks"], "number_of_clock_groups": len(clocks.groups), "with_alert_handler": with_alert_handler, - "pwrmgr_instance_name": f"top_{topname}_", + "virtual_provider": f"lowrisc:opentitan:top_{topname}_virtual_provider", } ipgen_render("clkmgr", topname, params, out_path) @@ -435,8 +437,7 @@ def generate_pwrmgr(top: Dict[str, object], out_path: Path) -> None: "NumRstReqs": n_rstreqs, "wait_for_external_reset": top['power']['wait_for_external_reset'], "NumRomInputs": n_rom_ctrl, - "alert_handler_instance_name": f"top_{topname}_", - "clkmgr_instance_name": f"top_{topname}_", + "virtual_provider": f"lowrisc:opentitan:top_{topname}_virtual_provider", } ipgen_render("pwrmgr", topname, params, out_path) @@ -490,10 +491,8 @@ def generate_rstmgr(topcfg: Dict[str, object], out_path: Path) -> None: "rst_ni": rst_ni['rst_ni']['name'], "export_rsts": topcfg["exported_rsts"], "with_alert_handler": with_alert_handler, - "pwrmgr_instance_name": f"top_{topname}_", + "virtual_provider": f"lowrisc:opentitan:top_{topname}_virtual_provider", } - if with_alert_handler: - params.update({"alert_handler_instance_name": f"top_{topname}_"}) ipgen_render("rstmgr", topname, params, out_path) @@ -520,7 +519,7 @@ def generate_flash(topcfg: Dict[str, object], out_path: Path) -> None: "metadata_width": 12, "info_types": 3, "infos_per_bank": [10, 1, 2], - "pwrmgr_instance_name": f"top_{topname}_", + "virtual_provider": f"lowrisc:opentitan:top_{topname}_virtual_provider", }) params.pop('base_addrs', None)