README.md

COSE222_Computer_Architecture

• Assignment & Milestone specifications can be found in ./Specifications

Assignments

• Implement & analayze sorting algorithm w/ RV32I assembly

Milestone

• Implement simple single-cyle RV32I CPU which supports pipelining (Verilog)
• Worked mainly in Milestones/RV32I_Class_Project_Milestone_*/RV32I_System/RV32I_CPU/rv32i_cpu.v

Milestone2

• Schematic Drawing

Milestone3

• Add instructions to the provided single-cycle CPU
• xor(i)
• bge(u)
• jalr

Milestone4

• Implement Pipelining w/ Data hazard detection and handling logic

1. Insturction

• sll(i)

2. Flipflop insert
3. Simple Forwarding
4. Forwarding Unit
5. Hardware Interlock

Milestone5

• Add control hazard detection and handling logic
• bne
• btaken으로 통합하기
• mux 2개 새로 만들기
• EX 단계로 branch 옮기기
• nop 추가

Milestone Final

• blt
• bge