Can OpenFPGA be used to generate 2um fabircs? What amounts of RAM would be possible in such a design? #1933
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@HomingHamster Thank you for the interests in OpenFPGA. OpenFPGA supports a flow where you can architect an FPGA fabric and generate its GDS. If you want to create a mask, a GDS or something equivalent is what the lithography tool needs. In addition, to generate the GDS, you may check the EDA tools and PDK that match your process node. OpenFPGA generates the Verilog netlists and you may need third-party tools to close the loop on converting Verilog netlists to GDS. OpenFPGA can support any single-port, two-port, dual port RAM at any sizes. It is designed to integrate your RAM IP into a programmable fabric like FPGA. We do not offer a RAM generator/memory compiler, you may search a third-party tool or check your PDK vendor. 30kB is not an issue. Successful tape-outs have been validated where we have more than 50kB memory. Feel free to contact me. |
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I know you say that you can generate any FPGA with this software, but what would the steps be for making an FPGA mask in the 2um fabric size? I have seen videos and websites of people who are able to make 2um lithography tools in their labs at home, so I was thinking its a sensible idea to cater for home soverign FPGA production as part of your software; where the sand to chip device knowledge is accessible, rather than just the multi-source approach.
A lot more points if you can tell me if such a design could potentially have 30kB of RAM (or even 10kB)? This is because 30kB is enough to run a few different embedded graphical OSes that I've seen with an IPv6 networking stack, and might enable some open source code to run on home soverign hardware.
I have collected some links, repositories, videos and, inspiration on my website, but the title is incorrect because I realised the icesugar is closed source and the documentation is misleading, https://circuspam.coffee/2024/12/29/entirely-self-soverign-48mhz-open-source-linux-computer-with-wifi-networking/ maybe, also, an OpenFPGA design can be used in its place.
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