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[SimplifyCFG] switch: Do Not Transform the Default Case if the Condition is Too Wide #77831

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Jan 12, 2024
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[SimplifyCFG] switch: Do Not Transform the Default Case if the Condition is Too Wide #77831

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bf3bbc4
Fix missing case computation for wide integers.
Jan 11, 2024
c64fade
Revise to not transform when the condition is wide.
Jan 11, 2024
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5 changes: 5 additions & 0 deletions llvm/lib/Transforms/Utils/SimplifyCFG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5623,6 +5623,11 @@ static bool eliminateDeadSwitchCases(SwitchInst *SI, DomTreeUpdater *DTU,
// optimization, such as lookup tables.
if (SI->getNumCases() == AllNumCases - 1) {
assert(NumUnknownBits > 1 && "Should be canonicalized to a branch");
IntegerType *CondTy = cast<IntegerType>(Cond->getType());
if (CondTy->getIntegerBitWidth() > 64 ||
!DL.fitsInLegalInteger(CondTy->getIntegerBitWidth()))
return false;

uint64_t MissingCaseVal = 0;
for (const auto &Case : SI->cases())
MissingCaseVal ^= Case.getCaseValue()->getValue().getLimitedValue();
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33 changes: 33 additions & 0 deletions llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll
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Expand Up @@ -313,6 +313,39 @@ default:

declare void @llvm.assume(i1)

define zeroext i1 @test8(i128 %a) {
; We should not transform conditions wider than 64 bit.
; CHECK-LABEL: define zeroext i1 @test8(
; CHECK-SAME: i128 [[A:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = and i128 [[A]], 3894222643901120721397872246915072
; CHECK-NEXT: switch i128 [[TMP0]], label [[LOR_RHS:%.*]] [
; CHECK-NEXT: i128 1298074214633706907132624082305024, label [[LOR_END:%.*]]
; CHECK-NEXT: i128 2596148429267413814265248164610048, label [[LOR_END]]
; CHECK-NEXT: i128 3894222643901120721397872246915072, label [[LOR_END]]
; CHECK-NEXT: ]
; CHECK: lor.rhs:
; CHECK-NEXT: br label [[LOR_END]]
; CHECK: lor.end:
; CHECK-NEXT: [[TMP1:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[LOR_RHS]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
; CHECK-NEXT: ret i1 [[TMP1]]
;
entry:
%0 = and i128 %a, 3894222643901120721397872246915072
switch i128 %0, label %lor.rhs [
i128 1298074214633706907132624082305024, label %lor.end
i128 2596148429267413814265248164610048, label %lor.end
i128 3894222643901120721397872246915072, label %lor.end
]

lor.rhs: ; preds = %entry
br label %lor.end

lor.end: ; preds = %entry, %entry, %entry, %lor.rhs
%1 = phi i1 [ true, %entry ], [ false, %lor.rhs ], [ true, %entry ], [ true, %entry ]
ret i1 %1
}

!0 = !{!"branch_weights", i32 8, i32 4, i32 2, i32 1}
;.
; CHECK: [[PROF0]] = !{!"branch_weights", i32 0, i32 4, i32 2, i32 1, i32 8}
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