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[AArch64] Fix a presumed typo in isFPImmLegal limit. NFC #106716

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merged 2 commits into from
Aug 30, 2024

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citymarina
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The worst possible case for a double literal goes like:

  mov ...
  movk ..., lsl #16
  movk ..., lsl #32
  movk ..., lsl #48
  fmov ...

The limit of 5 in the code gives the impression that Insn includes all instructions including the fmov, but that's not true. It only counts the integer moves. This led me astray on some other work in this area.

The worst possible case for a double literal goes like:

```
  mov ...
  movk ..., lsl llvm#16
  movk ..., lsl llvm#32
  movk ..., lsl llvm#48
  fmov ...
```

The limit of 5 in the code gives the impression that  `Insn` includes
all instructions including the `fmov`, but that's not true. It only
counts the integer moves. This led me astray on some other work in
this area.
@llvmbot
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llvmbot commented Aug 30, 2024

@llvm/pr-subscribers-backend-aarch64

Author: Marina Taylor (citymarina)

Changes

The worst possible case for a double literal goes like:

  mov ...
  movk ..., lsl #<!-- -->16
  movk ..., lsl #<!-- -->32
  movk ..., lsl #<!-- -->48
  fmov ...

The limit of 5 in the code gives the impression that Insn includes all instructions including the fmov, but that's not true. It only counts the integer moves. This led me astray on some other work in this area.


Full diff: https://github.com/llvm/llvm-project/pull/106716.diff

1 Files Affected:

  • (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+2-1)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 02390e0a85c0a5..98f6f30112a8c7 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -11463,7 +11463,8 @@ bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
     // movw+movk is fused). So we limit up to 2 instrdduction at most.
     SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn;
     AArch64_IMM::expandMOVImm(ImmInt.getZExtValue(), VT.getSizeInBits(), Insn);
-    unsigned Limit = (OptForSize ? 1 : (Subtarget->hasFuseLiterals() ? 5 : 2));
+    assert(Insn.size() <= 4);
+    unsigned Limit = (OptForSize ? 1 : (Subtarget->hasFuseLiterals() ? 4 : 2));
     IsLegal = Insn.size() <= Limit;
   }
 

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@davemgreen davemgreen left a comment

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LGTM, thanks

@@ -11463,7 +11463,9 @@ bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
// movw+movk is fused). So we limit up to 2 instrdduction at most.
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Do you mind changing instrdduction to instructions whilst you are here?

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Oh - you remove it in a follow up. Don't worry about it here then.

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LGTM, thanks

@fhahn fhahn merged commit d0d0e12 into llvm:main Aug 30, 2024
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4 participants