diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 4add33ba0996a..d0cc006ff2598 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -3791,6 +3791,11 @@ ScheduleDAGMILive *llvm::createGenericSchedLive(MachineSchedContext *C) { // data and pass it to later mutations. Have a single mutation that gathers // the interesting nodes in one pass. DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI)); + + const TargetSubtargetInfo &STI = C->MF->getSubtarget(); + // Add MacroFusionDAGMutation if enabled. + if (STI.enableMacroFusion()) + DAG->addMutation(createMacroFusionDAGMutation(STI.getMacroFusions())); return DAG; } @@ -3940,8 +3945,14 @@ void PostGenericScheduler::schedNode(SUnit *SU, bool IsTopNode) { } ScheduleDAGMI *llvm::createGenericSchedPostRA(MachineSchedContext *C) { - return new ScheduleDAGMI(C, std::make_unique(C), - /*RemoveKillFlags=*/true); + ScheduleDAGMI *DAG = + new ScheduleDAGMI(C, std::make_unique(C), + /*RemoveKillFlags=*/true); + const TargetSubtargetInfo &STI = C->MF->getSubtarget(); + // Add MacroFusionDAGMutation if enabled. + if (STI.enableMacroFusion()) + DAG->addMutation(createMacroFusionDAGMutation(STI.getMacroFusions())); + return DAG; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index e620c41f2f791..898ab1e379131 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -343,28 +343,6 @@ class RISCVPassConfig : public TargetPassConfig { return getTM(); } - ScheduleDAGInstrs * - createMachineScheduler(MachineSchedContext *C) const override { - const RISCVSubtarget &ST = C->MF->getSubtarget(); - if (ST.enableMacroFusion()) { - ScheduleDAGMILive *DAG = createGenericSchedLive(C); - DAG->addMutation(createMacroFusionDAGMutation(ST.getMacroFusions())); - return DAG; - } - return nullptr; - } - - ScheduleDAGInstrs * - createPostMachineScheduler(MachineSchedContext *C) const override { - const RISCVSubtarget &ST = C->MF->getSubtarget(); - if (ST.enableMacroFusion()) { - ScheduleDAGMI *DAG = createGenericSchedPostRA(C); - DAG->addMutation(createMacroFusionDAGMutation(ST.getMacroFusions())); - return DAG; - } - return nullptr; - } - void addIRPasses() override; bool addPreISel() override; bool addInstSelector() override;