From 66db262dbf3234d884026f15dca484c5f3d4e153 Mon Sep 17 00:00:00 2001
From: jiahanxie353 <jx353@cornell.edu>
Date: Thu, 11 Jan 2024 01:35:54 -0500
Subject: [PATCH] regbankselect test cases for vectorized G_ADD and G_SUB

---
 .../GlobalISel/regbankselect/rvv/add.mir      | 711 ++++++++++++++++++
 .../GlobalISel/regbankselect/rvv/sub.mir      | 711 ++++++++++++++++++
 .../regbankselect/vec-add-sub-rv32.mir        | 511 -------------
 .../regbankselect/vec-add-sub-rv64.mir        | 511 -------------
 4 files changed, 1422 insertions(+), 1022 deletions(-)
 create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir
 create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir
 delete mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-add-sub-rv32.mir
 delete mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-add-sub-rv64.mir

diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir
new file mode 100644
index 00000000000000..049060b79bf6f4
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir
@@ -0,0 +1,711 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV32I %s
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV64I %s
+---
+name:            vadd_vv_nxv1i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vadd_vv_nxv1i8
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v9
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s8>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[ADD]](<vscale x 1 x s8>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv1i8
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v9
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s8>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[ADD]](<vscale x 1 x s8>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 1 x s8>) = COPY $v8
+    %1:_(<vscale x 1 x s8>) = COPY $v9
+    %2:_(<vscale x 1 x s8>) = G_ADD %0, %1
+    $v8 = COPY %2(<vscale x 1 x s8>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vadd_vv_nxv2i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vadd_vv_nxv2i8
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v9
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 2 x s8>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[ADD]](<vscale x 2 x s8>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv2i8
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v9
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 2 x s8>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[ADD]](<vscale x 2 x s8>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 2 x s8>) = COPY $v8
+    %1:_(<vscale x 2 x s8>) = COPY $v9
+    %2:_(<vscale x 2 x s8>) = G_ADD %0, %1
+    $v8 = COPY %2(<vscale x 2 x s8>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vadd_vv_nxv4i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vadd_vv_nxv4i8
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v9
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s8>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[ADD]](<vscale x 4 x s8>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv4i8
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v9
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s8>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[ADD]](<vscale x 4 x s8>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 4 x s8>) = COPY $v8
+    %1:_(<vscale x 4 x s8>) = COPY $v9
+    %2:_(<vscale x 4 x s8>) = G_ADD %0, %1
+    $v8 = COPY %2(<vscale x 4 x s8>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vadd_vv_nxv8i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vadd_vv_nxv8i8
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v9
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 8 x s8>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[ADD]](<vscale x 8 x s8>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv8i8
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v9
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 8 x s8>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[ADD]](<vscale x 8 x s8>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 8 x s8>) = COPY $v8
+    %1:_(<vscale x 8 x s8>) = COPY $v9
+    %2:_(<vscale x 8 x s8>) = G_ADD %0, %1
+    $v8 = COPY %2(<vscale x 8 x s8>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vadd_vv_nxv16i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m2, $v10m2
+
+    ; RV32I-LABEL: name: vadd_vv_nxv16i8
+    ; RV32I: liveins: $v8m2, $v10m2
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v10m2
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 16 x s8>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m2 = COPY [[ADD]](<vscale x 16 x s8>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m2
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv16i8
+    ; RV64I: liveins: $v8m2, $v10m2
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v10m2
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 16 x s8>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m2 = COPY [[ADD]](<vscale x 16 x s8>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m2
+    %0:_(<vscale x 16 x s8>) = COPY $v8m2
+    %1:_(<vscale x 16 x s8>) = COPY $v10m2
+    %2:_(<vscale x 16 x s8>) = G_ADD %0, %1
+    $v8m2 = COPY %2(<vscale x 16 x s8>)
+    PseudoRET implicit $v8m2
+
+...
+---
+name:            vadd_vv_nxv32i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m4, $v12m4
+
+    ; RV32I-LABEL: name: vadd_vv_nxv32i8
+    ; RV32I: liveins: $v8m4, $v12m4
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v8m4
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v12m4
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 32 x s8>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m4 = COPY [[ADD]](<vscale x 32 x s8>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m4
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv32i8
+    ; RV64I: liveins: $v8m4, $v12m4
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v8m4
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v12m4
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 32 x s8>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m4 = COPY [[ADD]](<vscale x 32 x s8>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m4
+    %0:_(<vscale x 32 x s8>) = COPY $v8m4
+    %1:_(<vscale x 32 x s8>) = COPY $v12m4
+    %2:_(<vscale x 32 x s8>) = G_ADD %0, %1
+    $v8m4 = COPY %2(<vscale x 32 x s8>)
+    PseudoRET implicit $v8m4
+
+...
+---
+name:            vadd_vv_nxv64i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m8, $v16m8
+
+    ; RV32I-LABEL: name: vadd_vv_nxv64i8
+    ; RV32I: liveins: $v8m8, $v16m8
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 64 x s8>) = COPY $v8m8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 64 x s8>) = COPY $v16m8
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 64 x s8>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m8 = COPY [[ADD]](<vscale x 64 x s8>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m8
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv64i8
+    ; RV64I: liveins: $v8m8, $v16m8
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 64 x s8>) = COPY $v8m8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 64 x s8>) = COPY $v16m8
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 64 x s8>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m8 = COPY [[ADD]](<vscale x 64 x s8>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m8
+    %0:_(<vscale x 64 x s8>) = COPY $v8m8
+    %1:_(<vscale x 64 x s8>) = COPY $v16m8
+    %2:_(<vscale x 64 x s8>) = G_ADD %0, %1
+    $v8m8 = COPY %2(<vscale x 64 x s8>)
+    PseudoRET implicit $v8m8
+
+...
+---
+name:            vadd_vv_nxv1i16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vadd_vv_nxv1i16
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v9
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[ADD]](<vscale x 1 x s16>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv1i16
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v9
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[ADD]](<vscale x 1 x s16>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 1 x s16>) = COPY $v8
+    %1:_(<vscale x 1 x s16>) = COPY $v9
+    %2:_(<vscale x 1 x s16>) = G_ADD %0, %1
+    $v8 = COPY %2(<vscale x 1 x s16>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vadd_vv_nxv2i16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vadd_vv_nxv2i16
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v9
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[ADD]](<vscale x 2 x s16>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv2i16
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v9
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[ADD]](<vscale x 2 x s16>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 2 x s16>) = COPY $v8
+    %1:_(<vscale x 2 x s16>) = COPY $v9
+    %2:_(<vscale x 2 x s16>) = G_ADD %0, %1
+    $v8 = COPY %2(<vscale x 2 x s16>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vadd_vv_nxv4i16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vadd_vv_nxv4i16
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v9
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[ADD]](<vscale x 4 x s16>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv4i16
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v9
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[ADD]](<vscale x 4 x s16>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 4 x s16>) = COPY $v8
+    %1:_(<vscale x 4 x s16>) = COPY $v9
+    %2:_(<vscale x 4 x s16>) = G_ADD %0, %1
+    $v8 = COPY %2(<vscale x 4 x s16>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vadd_vv_nxv8i16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m2, $v10m2
+
+    ; RV32I-LABEL: name: vadd_vv_nxv8i16
+    ; RV32I: liveins: $v8m2, $v10m2
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m2
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v10m2
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m2 = COPY [[ADD]](<vscale x 8 x s16>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m2
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv8i16
+    ; RV64I: liveins: $v8m2, $v10m2
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m2
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v10m2
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m2 = COPY [[ADD]](<vscale x 8 x s16>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m2
+    %0:_(<vscale x 8 x s16>) = COPY $v8m2
+    %1:_(<vscale x 8 x s16>) = COPY $v10m2
+    %2:_(<vscale x 8 x s16>) = G_ADD %0, %1
+    $v8m2 = COPY %2(<vscale x 8 x s16>)
+    PseudoRET implicit $v8m2
+
+...
+---
+name:            vadd_vv_nxv16i16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m4, $v12m4
+
+    ; RV32I-LABEL: name: vadd_vv_nxv16i16
+    ; RV32I: liveins: $v8m4, $v12m4
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v8m4
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v12m4
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m4 = COPY [[ADD]](<vscale x 16 x s16>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m4
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv16i16
+    ; RV64I: liveins: $v8m4, $v12m4
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v8m4
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v12m4
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m4 = COPY [[ADD]](<vscale x 16 x s16>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m4
+    %0:_(<vscale x 16 x s16>) = COPY $v8m4
+    %1:_(<vscale x 16 x s16>) = COPY $v12m4
+    %2:_(<vscale x 16 x s16>) = G_ADD %0, %1
+    $v8m4 = COPY %2(<vscale x 16 x s16>)
+    PseudoRET implicit $v8m4
+
+...
+---
+name:            vadd_vv_nxv32i16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m8, $v16m8
+
+    ; RV32I-LABEL: name: vadd_vv_nxv32i16
+    ; RV32I: liveins: $v8m8, $v16m8
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s16>) = COPY $v8m8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 32 x s16>) = COPY $v16m8
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m8 = COPY [[ADD]](<vscale x 32 x s16>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m8
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv32i16
+    ; RV64I: liveins: $v8m8, $v16m8
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s16>) = COPY $v8m8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 32 x s16>) = COPY $v16m8
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m8 = COPY [[ADD]](<vscale x 32 x s16>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m8
+    %0:_(<vscale x 32 x s16>) = COPY $v8m8
+    %1:_(<vscale x 32 x s16>) = COPY $v16m8
+    %2:_(<vscale x 32 x s16>) = G_ADD %0, %1
+    $v8m8 = COPY %2(<vscale x 32 x s16>)
+    PseudoRET implicit $v8m8
+
+...
+---
+name:            vadd_vv_nxv1i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vadd_vv_nxv1i32
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v9
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[ADD]](<vscale x 1 x s32>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv1i32
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v9
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[ADD]](<vscale x 1 x s32>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 1 x s32>) = COPY $v8
+    %1:_(<vscale x 1 x s32>) = COPY $v9
+    %2:_(<vscale x 1 x s32>) = G_ADD %0, %1
+    $v8 = COPY %2(<vscale x 1 x s32>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vadd_vv_nxv2i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vadd_vv_nxv2i32
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v9
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[ADD]](<vscale x 2 x s32>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv2i32
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v9
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[ADD]](<vscale x 2 x s32>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 2 x s32>) = COPY $v8
+    %1:_(<vscale x 2 x s32>) = COPY $v9
+    %2:_(<vscale x 2 x s32>) = G_ADD %0, %1
+    $v8 = COPY %2(<vscale x 2 x s32>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vadd_vv_nxv4i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m2, $v10m2
+
+    ; RV32I-LABEL: name: vadd_vv_nxv4i32
+    ; RV32I: liveins: $v8m2, $v10m2
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v8m2
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v10m2
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m2 = COPY [[ADD]](<vscale x 4 x s32>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m2
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv4i32
+    ; RV64I: liveins: $v8m2, $v10m2
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v8m2
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v10m2
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m2 = COPY [[ADD]](<vscale x 4 x s32>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m2
+    %0:_(<vscale x 4 x s32>) = COPY $v8m2
+    %1:_(<vscale x 4 x s32>) = COPY $v10m2
+    %2:_(<vscale x 4 x s32>) = G_ADD %0, %1
+    $v8m2 = COPY %2(<vscale x 4 x s32>)
+    PseudoRET implicit $v8m2
+
+...
+---
+name:            vadd_vv_nxv8i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m4, $v12m4
+
+    ; RV32I-LABEL: name: vadd_vv_nxv8i32
+    ; RV32I: liveins: $v8m4, $v12m4
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v8m4
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v12m4
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m4 = COPY [[ADD]](<vscale x 8 x s32>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m4
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv8i32
+    ; RV64I: liveins: $v8m4, $v12m4
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v8m4
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v12m4
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m4 = COPY [[ADD]](<vscale x 8 x s32>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m4
+    %0:_(<vscale x 8 x s32>) = COPY $v8m4
+    %1:_(<vscale x 8 x s32>) = COPY $v12m4
+    %2:_(<vscale x 8 x s32>) = G_ADD %0, %1
+    $v8m4 = COPY %2(<vscale x 8 x s32>)
+    PseudoRET implicit $v8m4
+
+...
+---
+name:            vadd_vv_nxv16i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m8, $v16m8
+
+    ; RV32I-LABEL: name: vadd_vv_nxv16i32
+    ; RV32I: liveins: $v8m8, $v16m8
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s32>) = COPY $v8m8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s32>) = COPY $v16m8
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m8 = COPY [[ADD]](<vscale x 16 x s32>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m8
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv16i32
+    ; RV64I: liveins: $v8m8, $v16m8
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s32>) = COPY $v8m8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s32>) = COPY $v16m8
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m8 = COPY [[ADD]](<vscale x 16 x s32>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m8
+    %0:_(<vscale x 16 x s32>) = COPY $v8m8
+    %1:_(<vscale x 16 x s32>) = COPY $v16m8
+    %2:_(<vscale x 16 x s32>) = G_ADD %0, %1
+    $v8m8 = COPY %2(<vscale x 16 x s32>)
+    PseudoRET implicit $v8m8
+
+...
+---
+name:            vadd_vv_nxv1i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vadd_vv_nxv1i64
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s64>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s64>) = COPY $v9
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[ADD]](<vscale x 1 x s64>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv1i64
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s64>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s64>) = COPY $v9
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[ADD]](<vscale x 1 x s64>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 1 x s64>) = COPY $v8
+    %1:_(<vscale x 1 x s64>) = COPY $v9
+    %2:_(<vscale x 1 x s64>) = G_ADD %0, %1
+    $v8 = COPY %2(<vscale x 1 x s64>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vadd_vv_nxv2i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m2, $v10m2
+
+    ; RV32I-LABEL: name: vadd_vv_nxv2i64
+    ; RV32I: liveins: $v8m2, $v10m2
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s64>) = COPY $v8m2
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s64>) = COPY $v10m2
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m2 = COPY [[ADD]](<vscale x 2 x s64>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m2
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv2i64
+    ; RV64I: liveins: $v8m2, $v10m2
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s64>) = COPY $v8m2
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s64>) = COPY $v10m2
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m2 = COPY [[ADD]](<vscale x 2 x s64>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m2
+    %0:_(<vscale x 2 x s64>) = COPY $v8m2
+    %1:_(<vscale x 2 x s64>) = COPY $v10m2
+    %2:_(<vscale x 2 x s64>) = G_ADD %0, %1
+    $v8m2 = COPY %2(<vscale x 2 x s64>)
+    PseudoRET implicit $v8m2
+
+...
+---
+name:            vadd_vv_nxv4i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m4, $v12m4
+
+    ; RV32I-LABEL: name: vadd_vv_nxv4i64
+    ; RV32I: liveins: $v8m4, $v12m4
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s64>) = COPY $v8m4
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s64>) = COPY $v12m4
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m4 = COPY [[ADD]](<vscale x 4 x s64>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m4
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv4i64
+    ; RV64I: liveins: $v8m4, $v12m4
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s64>) = COPY $v8m4
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s64>) = COPY $v12m4
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m4 = COPY [[ADD]](<vscale x 4 x s64>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m4
+    %0:_(<vscale x 4 x s64>) = COPY $v8m4
+    %1:_(<vscale x 4 x s64>) = COPY $v12m4
+    %2:_(<vscale x 4 x s64>) = G_ADD %0, %1
+    $v8m4 = COPY %2(<vscale x 4 x s64>)
+    PseudoRET implicit $v8m4
+
+...
+---
+name:            vadd_vv_nxv8i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m8, $v16m8
+
+    ; RV32I-LABEL: name: vadd_vv_nxv8i64
+    ; RV32I: liveins: $v8m8, $v16m8
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s64>) = COPY $v8m8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s64>) = COPY $v16m8
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m8 = COPY [[ADD]](<vscale x 8 x s64>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m8
+    ;
+    ; RV64I-LABEL: name: vadd_vv_nxv8i64
+    ; RV64I: liveins: $v8m8, $v16m8
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s64>) = COPY $v8m8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s64>) = COPY $v16m8
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m8 = COPY [[ADD]](<vscale x 8 x s64>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m8
+    %0:_(<vscale x 8 x s64>) = COPY $v8m8
+    %1:_(<vscale x 8 x s64>) = COPY $v16m8
+    %2:_(<vscale x 8 x s64>) = G_ADD %0, %1
+    $v8m8 = COPY %2(<vscale x 8 x s64>)
+    PseudoRET implicit $v8m8
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir
new file mode 100644
index 00000000000000..d8580c09761ff6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir
@@ -0,0 +1,711 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV32I %s
+# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV64I %s
+---
+name:            vsub_vv_nxv1i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vsub_vv_nxv1i8
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v9
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 1 x s8>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[SUB]](<vscale x 1 x s8>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv1i8
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v9
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 1 x s8>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[SUB]](<vscale x 1 x s8>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 1 x s8>) = COPY $v8
+    %1:_(<vscale x 1 x s8>) = COPY $v9
+    %2:_(<vscale x 1 x s8>) = G_SUB %0, %1
+    $v8 = COPY %2(<vscale x 1 x s8>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vsub_vv_nxv2i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vsub_vv_nxv2i8
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v9
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 2 x s8>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[SUB]](<vscale x 2 x s8>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv2i8
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v9
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 2 x s8>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[SUB]](<vscale x 2 x s8>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 2 x s8>) = COPY $v8
+    %1:_(<vscale x 2 x s8>) = COPY $v9
+    %2:_(<vscale x 2 x s8>) = G_SUB %0, %1
+    $v8 = COPY %2(<vscale x 2 x s8>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vsub_vv_nxv4i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vsub_vv_nxv4i8
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v9
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 4 x s8>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[SUB]](<vscale x 4 x s8>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv4i8
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v9
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 4 x s8>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[SUB]](<vscale x 4 x s8>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 4 x s8>) = COPY $v8
+    %1:_(<vscale x 4 x s8>) = COPY $v9
+    %2:_(<vscale x 4 x s8>) = G_SUB %0, %1
+    $v8 = COPY %2(<vscale x 4 x s8>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vsub_vv_nxv8i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vsub_vv_nxv8i8
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v9
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 8 x s8>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[SUB]](<vscale x 8 x s8>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv8i8
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v9
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 8 x s8>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[SUB]](<vscale x 8 x s8>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 8 x s8>) = COPY $v8
+    %1:_(<vscale x 8 x s8>) = COPY $v9
+    %2:_(<vscale x 8 x s8>) = G_SUB %0, %1
+    $v8 = COPY %2(<vscale x 8 x s8>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vsub_vv_nxv16i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m2, $v10m2
+
+    ; RV32I-LABEL: name: vsub_vv_nxv16i8
+    ; RV32I: liveins: $v8m2, $v10m2
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v10m2
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 16 x s8>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m2 = COPY [[SUB]](<vscale x 16 x s8>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m2
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv16i8
+    ; RV64I: liveins: $v8m2, $v10m2
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v10m2
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 16 x s8>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m2 = COPY [[SUB]](<vscale x 16 x s8>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m2
+    %0:_(<vscale x 16 x s8>) = COPY $v8m2
+    %1:_(<vscale x 16 x s8>) = COPY $v10m2
+    %2:_(<vscale x 16 x s8>) = G_SUB %0, %1
+    $v8m2 = COPY %2(<vscale x 16 x s8>)
+    PseudoRET implicit $v8m2
+
+...
+---
+name:            vsub_vv_nxv32i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m4, $v12m4
+
+    ; RV32I-LABEL: name: vsub_vv_nxv32i8
+    ; RV32I: liveins: $v8m4, $v12m4
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v8m4
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v12m4
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 32 x s8>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m4 = COPY [[SUB]](<vscale x 32 x s8>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m4
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv32i8
+    ; RV64I: liveins: $v8m4, $v12m4
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v8m4
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v12m4
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 32 x s8>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m4 = COPY [[SUB]](<vscale x 32 x s8>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m4
+    %0:_(<vscale x 32 x s8>) = COPY $v8m4
+    %1:_(<vscale x 32 x s8>) = COPY $v12m4
+    %2:_(<vscale x 32 x s8>) = G_SUB %0, %1
+    $v8m4 = COPY %2(<vscale x 32 x s8>)
+    PseudoRET implicit $v8m4
+
+...
+---
+name:            vsub_vv_nxv64i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m8, $v16m8
+
+    ; RV32I-LABEL: name: vsub_vv_nxv64i8
+    ; RV32I: liveins: $v8m8, $v16m8
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 64 x s8>) = COPY $v8m8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 64 x s8>) = COPY $v16m8
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 64 x s8>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m8 = COPY [[SUB]](<vscale x 64 x s8>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m8
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv64i8
+    ; RV64I: liveins: $v8m8, $v16m8
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 64 x s8>) = COPY $v8m8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 64 x s8>) = COPY $v16m8
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 64 x s8>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m8 = COPY [[SUB]](<vscale x 64 x s8>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m8
+    %0:_(<vscale x 64 x s8>) = COPY $v8m8
+    %1:_(<vscale x 64 x s8>) = COPY $v16m8
+    %2:_(<vscale x 64 x s8>) = G_SUB %0, %1
+    $v8m8 = COPY %2(<vscale x 64 x s8>)
+    PseudoRET implicit $v8m8
+
+...
+---
+name:            vsub_vv_nxv1i16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vsub_vv_nxv1i16
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v9
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[SUB]](<vscale x 1 x s16>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv1i16
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v9
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[SUB]](<vscale x 1 x s16>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 1 x s16>) = COPY $v8
+    %1:_(<vscale x 1 x s16>) = COPY $v9
+    %2:_(<vscale x 1 x s16>) = G_SUB %0, %1
+    $v8 = COPY %2(<vscale x 1 x s16>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vsub_vv_nxv2i16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vsub_vv_nxv2i16
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v9
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[SUB]](<vscale x 2 x s16>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv2i16
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v9
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[SUB]](<vscale x 2 x s16>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 2 x s16>) = COPY $v8
+    %1:_(<vscale x 2 x s16>) = COPY $v9
+    %2:_(<vscale x 2 x s16>) = G_SUB %0, %1
+    $v8 = COPY %2(<vscale x 2 x s16>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vsub_vv_nxv4i16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vsub_vv_nxv4i16
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v9
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[SUB]](<vscale x 4 x s16>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv4i16
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v9
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[SUB]](<vscale x 4 x s16>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 4 x s16>) = COPY $v8
+    %1:_(<vscale x 4 x s16>) = COPY $v9
+    %2:_(<vscale x 4 x s16>) = G_SUB %0, %1
+    $v8 = COPY %2(<vscale x 4 x s16>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vsub_vv_nxv8i16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m2, $v10m2
+
+    ; RV32I-LABEL: name: vsub_vv_nxv8i16
+    ; RV32I: liveins: $v8m2, $v10m2
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m2
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v10m2
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m2 = COPY [[SUB]](<vscale x 8 x s16>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m2
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv8i16
+    ; RV64I: liveins: $v8m2, $v10m2
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m2
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v10m2
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m2 = COPY [[SUB]](<vscale x 8 x s16>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m2
+    %0:_(<vscale x 8 x s16>) = COPY $v8m2
+    %1:_(<vscale x 8 x s16>) = COPY $v10m2
+    %2:_(<vscale x 8 x s16>) = G_SUB %0, %1
+    $v8m2 = COPY %2(<vscale x 8 x s16>)
+    PseudoRET implicit $v8m2
+
+...
+---
+name:            vsub_vv_nxv16i16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m4, $v12m4
+
+    ; RV32I-LABEL: name: vsub_vv_nxv16i16
+    ; RV32I: liveins: $v8m4, $v12m4
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v8m4
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v12m4
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m4 = COPY [[SUB]](<vscale x 16 x s16>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m4
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv16i16
+    ; RV64I: liveins: $v8m4, $v12m4
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v8m4
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v12m4
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m4 = COPY [[SUB]](<vscale x 16 x s16>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m4
+    %0:_(<vscale x 16 x s16>) = COPY $v8m4
+    %1:_(<vscale x 16 x s16>) = COPY $v12m4
+    %2:_(<vscale x 16 x s16>) = G_SUB %0, %1
+    $v8m4 = COPY %2(<vscale x 16 x s16>)
+    PseudoRET implicit $v8m4
+
+...
+---
+name:            vsub_vv_nxv32i16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m8, $v16m8
+
+    ; RV32I-LABEL: name: vsub_vv_nxv32i16
+    ; RV32I: liveins: $v8m8, $v16m8
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s16>) = COPY $v8m8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 32 x s16>) = COPY $v16m8
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m8 = COPY [[SUB]](<vscale x 32 x s16>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m8
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv32i16
+    ; RV64I: liveins: $v8m8, $v16m8
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s16>) = COPY $v8m8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 32 x s16>) = COPY $v16m8
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m8 = COPY [[SUB]](<vscale x 32 x s16>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m8
+    %0:_(<vscale x 32 x s16>) = COPY $v8m8
+    %1:_(<vscale x 32 x s16>) = COPY $v16m8
+    %2:_(<vscale x 32 x s16>) = G_SUB %0, %1
+    $v8m8 = COPY %2(<vscale x 32 x s16>)
+    PseudoRET implicit $v8m8
+
+...
+---
+name:            vsub_vv_nxv1i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vsub_vv_nxv1i32
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v9
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[SUB]](<vscale x 1 x s32>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv1i32
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v9
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[SUB]](<vscale x 1 x s32>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 1 x s32>) = COPY $v8
+    %1:_(<vscale x 1 x s32>) = COPY $v9
+    %2:_(<vscale x 1 x s32>) = G_SUB %0, %1
+    $v8 = COPY %2(<vscale x 1 x s32>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vsub_vv_nxv2i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vsub_vv_nxv2i32
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v9
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[SUB]](<vscale x 2 x s32>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv2i32
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v9
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[SUB]](<vscale x 2 x s32>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 2 x s32>) = COPY $v8
+    %1:_(<vscale x 2 x s32>) = COPY $v9
+    %2:_(<vscale x 2 x s32>) = G_SUB %0, %1
+    $v8 = COPY %2(<vscale x 2 x s32>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vsub_vv_nxv4i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m2, $v10m2
+
+    ; RV32I-LABEL: name: vsub_vv_nxv4i32
+    ; RV32I: liveins: $v8m2, $v10m2
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v8m2
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v10m2
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m2 = COPY [[SUB]](<vscale x 4 x s32>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m2
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv4i32
+    ; RV64I: liveins: $v8m2, $v10m2
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v8m2
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v10m2
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m2 = COPY [[SUB]](<vscale x 4 x s32>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m2
+    %0:_(<vscale x 4 x s32>) = COPY $v8m2
+    %1:_(<vscale x 4 x s32>) = COPY $v10m2
+    %2:_(<vscale x 4 x s32>) = G_SUB %0, %1
+    $v8m2 = COPY %2(<vscale x 4 x s32>)
+    PseudoRET implicit $v8m2
+
+...
+---
+name:            vsub_vv_nxv8i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m4, $v12m4
+
+    ; RV32I-LABEL: name: vsub_vv_nxv8i32
+    ; RV32I: liveins: $v8m4, $v12m4
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v8m4
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v12m4
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m4 = COPY [[SUB]](<vscale x 8 x s32>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m4
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv8i32
+    ; RV64I: liveins: $v8m4, $v12m4
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v8m4
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v12m4
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m4 = COPY [[SUB]](<vscale x 8 x s32>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m4
+    %0:_(<vscale x 8 x s32>) = COPY $v8m4
+    %1:_(<vscale x 8 x s32>) = COPY $v12m4
+    %2:_(<vscale x 8 x s32>) = G_SUB %0, %1
+    $v8m4 = COPY %2(<vscale x 8 x s32>)
+    PseudoRET implicit $v8m4
+
+...
+---
+name:            vsub_vv_nxv16i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m8, $v16m8
+
+    ; RV32I-LABEL: name: vsub_vv_nxv16i32
+    ; RV32I: liveins: $v8m8, $v16m8
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s32>) = COPY $v8m8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s32>) = COPY $v16m8
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m8 = COPY [[SUB]](<vscale x 16 x s32>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m8
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv16i32
+    ; RV64I: liveins: $v8m8, $v16m8
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s32>) = COPY $v8m8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s32>) = COPY $v16m8
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m8 = COPY [[SUB]](<vscale x 16 x s32>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m8
+    %0:_(<vscale x 16 x s32>) = COPY $v8m8
+    %1:_(<vscale x 16 x s32>) = COPY $v16m8
+    %2:_(<vscale x 16 x s32>) = G_SUB %0, %1
+    $v8m8 = COPY %2(<vscale x 16 x s32>)
+    PseudoRET implicit $v8m8
+
+...
+---
+name:            vsub_vv_nxv1i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8, $v9
+
+    ; RV32I-LABEL: name: vsub_vv_nxv1i64
+    ; RV32I: liveins: $v8, $v9
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s64>) = COPY $v8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s64>) = COPY $v9
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8 = COPY [[SUB]](<vscale x 1 x s64>)
+    ; RV32I-NEXT: PseudoRET implicit $v8
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv1i64
+    ; RV64I: liveins: $v8, $v9
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s64>) = COPY $v8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s64>) = COPY $v9
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8 = COPY [[SUB]](<vscale x 1 x s64>)
+    ; RV64I-NEXT: PseudoRET implicit $v8
+    %0:_(<vscale x 1 x s64>) = COPY $v8
+    %1:_(<vscale x 1 x s64>) = COPY $v9
+    %2:_(<vscale x 1 x s64>) = G_SUB %0, %1
+    $v8 = COPY %2(<vscale x 1 x s64>)
+    PseudoRET implicit $v8
+
+...
+---
+name:            vsub_vv_nxv2i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m2, $v10m2
+
+    ; RV32I-LABEL: name: vsub_vv_nxv2i64
+    ; RV32I: liveins: $v8m2, $v10m2
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s64>) = COPY $v8m2
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s64>) = COPY $v10m2
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m2 = COPY [[SUB]](<vscale x 2 x s64>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m2
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv2i64
+    ; RV64I: liveins: $v8m2, $v10m2
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s64>) = COPY $v8m2
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s64>) = COPY $v10m2
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m2 = COPY [[SUB]](<vscale x 2 x s64>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m2
+    %0:_(<vscale x 2 x s64>) = COPY $v8m2
+    %1:_(<vscale x 2 x s64>) = COPY $v10m2
+    %2:_(<vscale x 2 x s64>) = G_SUB %0, %1
+    $v8m2 = COPY %2(<vscale x 2 x s64>)
+    PseudoRET implicit $v8m2
+
+...
+---
+name:            vsub_vv_nxv4i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m4, $v12m4
+
+    ; RV32I-LABEL: name: vsub_vv_nxv4i64
+    ; RV32I: liveins: $v8m4, $v12m4
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s64>) = COPY $v8m4
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s64>) = COPY $v12m4
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m4 = COPY [[SUB]](<vscale x 4 x s64>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m4
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv4i64
+    ; RV64I: liveins: $v8m4, $v12m4
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s64>) = COPY $v8m4
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s64>) = COPY $v12m4
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m4 = COPY [[SUB]](<vscale x 4 x s64>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m4
+    %0:_(<vscale x 4 x s64>) = COPY $v8m4
+    %1:_(<vscale x 4 x s64>) = COPY $v12m4
+    %2:_(<vscale x 4 x s64>) = G_SUB %0, %1
+    $v8m4 = COPY %2(<vscale x 4 x s64>)
+    PseudoRET implicit $v8m4
+
+...
+---
+name:            vsub_vv_nxv8i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $v8m8, $v16m8
+
+    ; RV32I-LABEL: name: vsub_vv_nxv8i64
+    ; RV32I: liveins: $v8m8, $v16m8
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s64>) = COPY $v8m8
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s64>) = COPY $v16m8
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $v8m8 = COPY [[SUB]](<vscale x 8 x s64>)
+    ; RV32I-NEXT: PseudoRET implicit $v8m8
+    ;
+    ; RV64I-LABEL: name: vsub_vv_nxv8i64
+    ; RV64I: liveins: $v8m8, $v16m8
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s64>) = COPY $v8m8
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s64>) = COPY $v16m8
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $v8m8 = COPY [[SUB]](<vscale x 8 x s64>)
+    ; RV64I-NEXT: PseudoRET implicit $v8m8
+    %0:_(<vscale x 8 x s64>) = COPY $v8m8
+    %1:_(<vscale x 8 x s64>) = COPY $v16m8
+    %2:_(<vscale x 8 x s64>) = G_SUB %0, %1
+    $v8m8 = COPY %2(<vscale x 8 x s64>)
+    PseudoRET implicit $v8m8
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-add-sub-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-add-sub-rv32.mir
deleted file mode 100644
index d45009a417297d..00000000000000
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-add-sub-rv32.mir
+++ /dev/null
@@ -1,511 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
-# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
-# RUN:   -o - | FileCheck -check-prefix=RV32I %s
-
----
-name:            add_nxv1s8
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: add_nxv1s8
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v11
-    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s8>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[ADD]](<vscale x 1 x s8>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 1 x s8>) = COPY $v10
-    %1:_(<vscale x 1 x s8>) = COPY $v11
-    %2:_(<vscale x 1 x s8>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 1 x s8>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv2s8
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: sub_nxv2s8
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v11
-    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 2 x s8>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[SUB]](<vscale x 2 x s8>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 2 x s8>) = COPY $v10
-    %1:_(<vscale x 2 x s8>) = COPY $v11
-    %2:_(<vscale x 2 x s8>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 2 x s8>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv4s8
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: add_nxv4s8
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v11
-    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s8>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[ADD]](<vscale x 4 x s8>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 4 x s8>) = COPY $v10
-    %1:_(<vscale x 4 x s8>) = COPY $v11
-    %2:_(<vscale x 4 x s8>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 4 x s8>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv8s8
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: sub_nxv8s8
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v11
-    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 8 x s8>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[SUB]](<vscale x 8 x s8>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 8 x s8>) = COPY $v10
-    %1:_(<vscale x 8 x s8>) = COPY $v11
-    %2:_(<vscale x 8 x s8>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 8 x s8>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv16s8
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: add_nxv16s8
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v11
-    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 16 x s8>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[ADD]](<vscale x 16 x s8>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 16 x s8>) = COPY $v10
-    %1:_(<vscale x 16 x s8>) = COPY $v11
-    %2:_(<vscale x 16 x s8>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 16 x s8>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv32s8
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: sub_nxv32s8
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v11
-    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 32 x s8>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[SUB]](<vscale x 32 x s8>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 32 x s8>) = COPY $v10
-    %1:_(<vscale x 32 x s8>) = COPY $v11
-    %2:_(<vscale x 32 x s8>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 32 x s8>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv64s8
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: add_nxv64s8
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 64 x s8>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 64 x s8>) = COPY $v11
-    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 64 x s8>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[ADD]](<vscale x 64 x s8>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 64 x s8>) = COPY $v10
-    %1:_(<vscale x 64 x s8>) = COPY $v11
-    %2:_(<vscale x 64 x s8>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 64 x s8>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv1s16
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: add_nxv1s16
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v11
-    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[ADD]](<vscale x 1 x s16>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 1 x s16>) = COPY $v10
-    %1:_(<vscale x 1 x s16>) = COPY $v11
-    %2:_(<vscale x 1 x s16>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 1 x s16>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv2s16
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: sub_nxv2s16
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v11
-    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[SUB]](<vscale x 2 x s16>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 2 x s16>) = COPY $v10
-    %1:_(<vscale x 2 x s16>) = COPY $v11
-    %2:_(<vscale x 2 x s16>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 2 x s16>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv4s16
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: add_nxv4s16
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v11
-    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[ADD]](<vscale x 4 x s16>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 4 x s16>) = COPY $v10
-    %1:_(<vscale x 4 x s16>) = COPY $v11
-    %2:_(<vscale x 4 x s16>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 4 x s16>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv8s16
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: sub_nxv8s16
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v11
-    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[SUB]](<vscale x 8 x s16>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 8 x s16>) = COPY $v10
-    %1:_(<vscale x 8 x s16>) = COPY $v11
-    %2:_(<vscale x 8 x s16>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 8 x s16>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv16s16
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: add_nxv16s16
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v11
-    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[ADD]](<vscale x 16 x s16>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 16 x s16>) = COPY $v10
-    %1:_(<vscale x 16 x s16>) = COPY $v11
-    %2:_(<vscale x 16 x s16>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 16 x s16>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv32s16
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: sub_nxv32s16
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s16>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 32 x s16>) = COPY $v11
-    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[SUB]](<vscale x 32 x s16>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 32 x s16>) = COPY $v10
-    %1:_(<vscale x 32 x s16>) = COPY $v11
-    %2:_(<vscale x 32 x s16>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 32 x s16>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv1s32
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: add_nxv1s32
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v11
-    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[ADD]](<vscale x 1 x s32>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 1 x s32>) = COPY $v10
-    %1:_(<vscale x 1 x s32>) = COPY $v11
-    %2:_(<vscale x 1 x s32>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 1 x s32>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv2s32
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: sub_nxv2s32
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v11
-    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[SUB]](<vscale x 2 x s32>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 2 x s32>) = COPY $v10
-    %1:_(<vscale x 2 x s32>) = COPY $v11
-    %2:_(<vscale x 2 x s32>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 2 x s32>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv4s32
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: add_nxv4s32
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v11
-    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[ADD]](<vscale x 4 x s32>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 4 x s32>) = COPY $v10
-    %1:_(<vscale x 4 x s32>) = COPY $v11
-    %2:_(<vscale x 4 x s32>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 4 x s32>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv8s32
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: sub_nxv8s32
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v11
-    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[SUB]](<vscale x 8 x s32>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 8 x s32>) = COPY $v10
-    %1:_(<vscale x 8 x s32>) = COPY $v11
-    %2:_(<vscale x 8 x s32>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 8 x s32>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv16s32
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: add_nxv16s32
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s32>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s32>) = COPY $v11
-    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[ADD]](<vscale x 16 x s32>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 16 x s32>) = COPY $v10
-    %1:_(<vscale x 16 x s32>) = COPY $v11
-    %2:_(<vscale x 16 x s32>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 16 x s32>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv1s64
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: add_nxv1s64
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s64>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s64>) = COPY $v11
-    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[ADD]](<vscale x 1 x s64>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 1 x s64>) = COPY $v10
-    %1:_(<vscale x 1 x s64>) = COPY $v11
-    %2:_(<vscale x 1 x s64>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 1 x s64>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv2s64
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: sub_nxv2s64
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s64>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s64>) = COPY $v11
-    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[SUB]](<vscale x 2 x s64>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 2 x s64>) = COPY $v10
-    %1:_(<vscale x 2 x s64>) = COPY $v11
-    %2:_(<vscale x 2 x s64>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 2 x s64>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv4s64
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: add_nxv4s64
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s64>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s64>) = COPY $v11
-    ; RV32I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[ADD]](<vscale x 4 x s64>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 4 x s64>) = COPY $v10
-    %1:_(<vscale x 4 x s64>) = COPY $v11
-    %2:_(<vscale x 4 x s64>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 4 x s64>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv8s64
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV32I-LABEL: name: sub_nxv8s64
-    ; RV32I: liveins: $v10, $v11
-    ; RV32I-NEXT: {{  $}}
-    ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s64>) = COPY $v10
-    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s64>) = COPY $v11
-    ; RV32I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV32I-NEXT: $v10 = COPY [[SUB]](<vscale x 8 x s64>)
-    ; RV32I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 8 x s64>) = COPY $v10
-    %1:_(<vscale x 8 x s64>) = COPY $v11
-    %2:_(<vscale x 8 x s64>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 8 x s64>)
-    PseudoRET implicit $v10
-
-...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-add-sub-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-add-sub-rv64.mir
deleted file mode 100644
index 4233e0557ab433..00000000000000
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-add-sub-rv64.mir
+++ /dev/null
@@ -1,511 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
-# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
-# RUN:   -o - | FileCheck -check-prefix=RV64I %s
-
----
-name:            add_nxv1s8
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: add_nxv1s8
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v11
-    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s8>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[ADD]](<vscale x 1 x s8>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 1 x s8>) = COPY $v10
-    %1:_(<vscale x 1 x s8>) = COPY $v11
-    %2:_(<vscale x 1 x s8>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 1 x s8>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv2s8
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: sub_nxv2s8
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v11
-    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 2 x s8>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[SUB]](<vscale x 2 x s8>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 2 x s8>) = COPY $v10
-    %1:_(<vscale x 2 x s8>) = COPY $v11
-    %2:_(<vscale x 2 x s8>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 2 x s8>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv4s8
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: add_nxv4s8
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v11
-    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s8>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[ADD]](<vscale x 4 x s8>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 4 x s8>) = COPY $v10
-    %1:_(<vscale x 4 x s8>) = COPY $v11
-    %2:_(<vscale x 4 x s8>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 4 x s8>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv8s8
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: sub_nxv8s8
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v11
-    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 8 x s8>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[SUB]](<vscale x 8 x s8>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 8 x s8>) = COPY $v10
-    %1:_(<vscale x 8 x s8>) = COPY $v11
-    %2:_(<vscale x 8 x s8>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 8 x s8>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv16s8
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: add_nxv16s8
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v11
-    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 16 x s8>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[ADD]](<vscale x 16 x s8>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 16 x s8>) = COPY $v10
-    %1:_(<vscale x 16 x s8>) = COPY $v11
-    %2:_(<vscale x 16 x s8>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 16 x s8>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv32s8
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: sub_nxv32s8
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v11
-    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 32 x s8>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[SUB]](<vscale x 32 x s8>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 32 x s8>) = COPY $v10
-    %1:_(<vscale x 32 x s8>) = COPY $v11
-    %2:_(<vscale x 32 x s8>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 32 x s8>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv64s8
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: add_nxv64s8
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 64 x s8>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 64 x s8>) = COPY $v11
-    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 64 x s8>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[ADD]](<vscale x 64 x s8>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 64 x s8>) = COPY $v10
-    %1:_(<vscale x 64 x s8>) = COPY $v11
-    %2:_(<vscale x 64 x s8>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 64 x s8>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv1s16
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: add_nxv1s16
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v11
-    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[ADD]](<vscale x 1 x s16>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 1 x s16>) = COPY $v10
-    %1:_(<vscale x 1 x s16>) = COPY $v11
-    %2:_(<vscale x 1 x s16>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 1 x s16>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv2s16
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: sub_nxv2s16
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v11
-    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[SUB]](<vscale x 2 x s16>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 2 x s16>) = COPY $v10
-    %1:_(<vscale x 2 x s16>) = COPY $v11
-    %2:_(<vscale x 2 x s16>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 2 x s16>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv4s16
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: add_nxv4s16
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v11
-    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[ADD]](<vscale x 4 x s16>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 4 x s16>) = COPY $v10
-    %1:_(<vscale x 4 x s16>) = COPY $v11
-    %2:_(<vscale x 4 x s16>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 4 x s16>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv8s16
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: sub_nxv8s16
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v11
-    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[SUB]](<vscale x 8 x s16>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 8 x s16>) = COPY $v10
-    %1:_(<vscale x 8 x s16>) = COPY $v11
-    %2:_(<vscale x 8 x s16>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 8 x s16>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv16s16
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: add_nxv16s16
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v11
-    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[ADD]](<vscale x 16 x s16>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 16 x s16>) = COPY $v10
-    %1:_(<vscale x 16 x s16>) = COPY $v11
-    %2:_(<vscale x 16 x s16>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 16 x s16>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv32s16
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: sub_nxv32s16
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s16>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 32 x s16>) = COPY $v11
-    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[SUB]](<vscale x 32 x s16>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 32 x s16>) = COPY $v10
-    %1:_(<vscale x 32 x s16>) = COPY $v11
-    %2:_(<vscale x 32 x s16>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 32 x s16>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv1s32
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: add_nxv1s32
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v11
-    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[ADD]](<vscale x 1 x s32>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 1 x s32>) = COPY $v10
-    %1:_(<vscale x 1 x s32>) = COPY $v11
-    %2:_(<vscale x 1 x s32>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 1 x s32>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv2s32
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: sub_nxv2s32
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v11
-    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[SUB]](<vscale x 2 x s32>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 2 x s32>) = COPY $v10
-    %1:_(<vscale x 2 x s32>) = COPY $v11
-    %2:_(<vscale x 2 x s32>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 2 x s32>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv4s32
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: add_nxv4s32
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v11
-    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[ADD]](<vscale x 4 x s32>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 4 x s32>) = COPY $v10
-    %1:_(<vscale x 4 x s32>) = COPY $v11
-    %2:_(<vscale x 4 x s32>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 4 x s32>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv8s32
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: sub_nxv8s32
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v11
-    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[SUB]](<vscale x 8 x s32>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 8 x s32>) = COPY $v10
-    %1:_(<vscale x 8 x s32>) = COPY $v11
-    %2:_(<vscale x 8 x s32>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 8 x s32>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv16s32
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: add_nxv16s32
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s32>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s32>) = COPY $v11
-    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[ADD]](<vscale x 16 x s32>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 16 x s32>) = COPY $v10
-    %1:_(<vscale x 16 x s32>) = COPY $v11
-    %2:_(<vscale x 16 x s32>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 16 x s32>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv1s64
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: add_nxv1s64
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s64>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s64>) = COPY $v11
-    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[ADD]](<vscale x 1 x s64>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 1 x s64>) = COPY $v10
-    %1:_(<vscale x 1 x s64>) = COPY $v11
-    %2:_(<vscale x 1 x s64>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 1 x s64>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv2s64
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: sub_nxv2s64
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s64>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s64>) = COPY $v11
-    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[SUB]](<vscale x 2 x s64>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 2 x s64>) = COPY $v10
-    %1:_(<vscale x 2 x s64>) = COPY $v11
-    %2:_(<vscale x 2 x s64>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 2 x s64>)
-    PseudoRET implicit $v10
-
-...
----
-name:            add_nxv4s64
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: add_nxv4s64
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s64>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s64>) = COPY $v11
-    ; RV64I-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ADD [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[ADD]](<vscale x 4 x s64>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 4 x s64>) = COPY $v10
-    %1:_(<vscale x 4 x s64>) = COPY $v11
-    %2:_(<vscale x 4 x s64>) = G_ADD %0, %1
-    $v10 = COPY %2(<vscale x 4 x s64>)
-    PseudoRET implicit $v10
-
-...
----
-name:            sub_nxv8s64
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $v10, $v11
-
-    ; RV64I-LABEL: name: sub_nxv8s64
-    ; RV64I: liveins: $v10, $v11
-    ; RV64I-NEXT: {{  $}}
-    ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s64>) = COPY $v10
-    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s64>) = COPY $v11
-    ; RV64I-NEXT: [[SUB:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_SUB [[COPY]], [[COPY1]]
-    ; RV64I-NEXT: $v10 = COPY [[SUB]](<vscale x 8 x s64>)
-    ; RV64I-NEXT: PseudoRET implicit $v10
-    %0:_(<vscale x 8 x s64>) = COPY $v10
-    %1:_(<vscale x 8 x s64>) = COPY $v11
-    %2:_(<vscale x 8 x s64>) = G_SUB %0, %1
-    $v10 = COPY %2(<vscale x 8 x s64>)
-    PseudoRET implicit $v10
-
-...