diff --git a/src/nvme/types.h b/src/nvme/types.h index 04429436..fd6c465b 100644 --- a/src/nvme/types.h +++ b/src/nvme/types.h @@ -1196,7 +1196,13 @@ struct nvme_id_psd { * @rrls: Read Recovery Levels. If a bit is set, then the corresponding * Read Recovery Level is supported. If a bit is cleared, then the * corresponding Read Recovery Level is not supported. - * @rsvd102: Reserved + * @bpcap: Boot Partition Capabilities, see &enum nvme_id_ctrl_bpcap. + * @rsvd103: Reserved + * @nssl: NVM Subsystem Shutdown Latency (NSSL). This field indicates the + * typical latency in microseconds for an NVM Subsystem Shutdown to + * complete. + * @rsvd108: Reserved + * @plsi: Power Loss Signaling Information (PLSI), see &enum nvme_id_ctrl_plsi * @cntrltype: Controller Type, see &enum nvme_id_ctrl_cntrltype * @fguid: FRU GUID, a 128-bit value that is globally unique for a given * Field Replaceable Unit @@ -1206,7 +1212,9 @@ struct nvme_id_psd { * field is 2 * @crdt3: Controller Retry Delay time in 100 millisecond units if CQE CRD * field is 3 - * @rsvd134: Reserved + * @crcap: Controller Reachability Capabilities (CRCAP), see + * &enum nvme_id_ctrl_crcap + * @rsvd135: Reserved * @nvmsr: NVM Subsystem Report, see &enum nvme_id_ctrl_nvmsr * @vwci: VPD Write Cycle Information, see &enum nvme_id_ctrl_vwci * @mec: Management Endpoint Capabilities, see &enum nvme_id_ctrl_mec @@ -1308,11 +1316,23 @@ struct nvme_id_psd { * for the Persistent Event Log. * @domainid: Domain Identifier indicates the identifier of the domain * that contains this controller. - * @rsvd358: Reserved + * @kpioc: Key Per I/O Capabilities (KPIOC), see &enum nvme_id_ctrl_kpioc + * @rsvd359: Reserved + * @mptfawr: Maximum Processing Time for Firmware Activation Without Reset + * (MPTFAWR). This field shall indicate the estimated maximum time + * in 100 ms units required by the controller to process a Firmware + * Commit command that specifies a value of 011b in the Commit + * Action field + * @rsvd362: Reserved * @megcap: Max Endurance Group Capacity indicates the maximum capacity * of a single Endurance Group. * @tmpthha: Temperature Threshold Hysteresis Attributes * @rsvd385: Reserved + * @cqt: Command Quiesce Time (CQT). his field indicates the expected + * worst-case time in 1 millisecond units for the controller to + * quiesce all outstanding commands after a Keep Alive Timeout or + * other communication loss. + * @rsvd388: Reserved * @sqes: Submission Queue Entry Size, see &enum nvme_id_ctrl_sqes. * @cqes: Completion Queue Entry Size, see &enum nvme_id_ctrl_cqes. * @maxcmd: Maximum Outstanding Commands indicates the maximum number of @@ -1359,7 +1379,17 @@ struct nvme_id_psd { * @oaqd: Optimal Aggregated Queue Depth indicates the recommended maximum * total number of outstanding I/O commands across all I/O queues * on the controller for optimal operation. - * @rsvd568: Reserved + * @rhiri: Recommended Host-Initiated Refresh Interval (RHIRI). If the + * Host-Initiated Refresh capability is supported, then this field + * indicates the recommended time interval in days from last power + * down to the time at which the host should initiate the + * Host-Initiated Refresh operation. If this field is cleared to + * 0h, then this field is not reported. + * @hirt: Host-Initiated Refresh Time (HIRT). If the Host-Initiated + * Refresh capability is supported, then this field indicates the + * nominal amount of time in minutes that the controller takes to + * complete the Host-Initiated Refresh operation. If this field is + * cleared to 0h, then this field is not reported. * @cmmrtd: Controller Maximum Memory Range Tracking Descriptors indicates * the maximum number of Memory Range Tracking Descriptors the * controller supports. @@ -1431,13 +1461,18 @@ struct nvme_id_ctrl { __le32 oaes; __le32 ctratt; __le16 rrls; - __u8 rsvd102[9]; + __u8 bpcap; + __u8 rsvd103; + __le32 nssl; + __u8 rsvd108[2]; + __u8 plsi; __u8 cntrltype; __u8 fguid[16]; __le16 crdt1; __le16 crdt2; __le16 crdt3; - __u8 rsvd134[119]; + __u8 crcap; + __u8 rsvd135[118]; __u8 nvmsr; __u8 vwci; __u8 mec; @@ -1476,10 +1511,15 @@ struct nvme_id_ctrl { __le32 nanagrpid; __le32 pels; __le16 domainid; - __u8 rsvd358[10]; + __u8 kpioc; + __u8 rsvd359; + __le16 mptfawr; + __u8 rsvd362[6]; __u8 megcap[16]; __u8 tmpthha; - __u8 rsvd385[127]; + __u8 rsvd385; + __le16 cqt; + __u8 rsvd388[124]; __u8 sqes; __u8 cqes; __le16 maxcmd; @@ -1499,7 +1539,8 @@ struct nvme_id_ctrl { __u8 maxdna[16]; __le32 maxcna; __le32 oaqd; - __u8 rsvd568[2]; + __u8 rhiri; + __u8 hirt; __u16 cmmrtd; __u16 nmmrtd; __u8 minmrtg; @@ -1737,6 +1778,73 @@ enum nvme_id_ctrl_ctratt { NVME_CTRL_CTRATT_FDPS = 1 << 19, }; +/** + * enum nvme_id_ctrl_bpcap - Boot Partition Capabilities + * @NVME_CTRL_BACAP_RPMBBPWPS_SHIFT: Shift amount to get the RPMB Boot Partition Write + * Protection Support from the &struct + * nvme_id_ctrl.bpcap field. + * @NVME_CTRL_BACAP_SFBPWPS_SHIFT: Shift amount to get the Set Features Boot Partition + * Write Protection Support from the &struct + * nvme_id_ctrl.bpcap field. + * @NVME_CTRL_BACAP_RPMBBPWPS_MASK: Mask to get the RPMB Boot Partition Write + * Protection Support from the &struct + * nvme_id_ctrl.bpcap field. + * @NVME_CTRL_BACAP_SFBPWPS_MASK: Mask to get the Set Features Boot Partition Write + * Protection Support from the &struct + * nvme_id_ctrl.bpcap field. + * @NVME_CTRL_BACAP_RPMBBPWPS_NOT_SPECIFIED: Support for RPMB Boot Partition Write Protection + * is not specified. + * @NVME_CTRL_BACAP_RPMBBPWPS_NOT_SUPPORTED: RPMB Boot Partition Write Protection is not + * supported by this controller. + * @NVME_CTRL_BACAP_RPMBBPWPS_SUPPORTED: RPMB Boot Partition Write Protection is supported + * by this controller. + */ +enum nvme_id_ctrl_bpcap { + NVME_CTRL_BACAP_RPMBBPWPS_SHIFT = 0, + NVME_CTRL_BACAP_SFBPWPS_SHIFT = 2, + NVME_CTRL_BACAP_RPMBBPWPS_MASK = 0x3, + NVME_CTRL_BACAP_SFBPWPS_MASK = 0x1, + NVME_CTRL_BACAP_RPMBBPWPS_NOT_SPECIFIED = 0, + NVME_CTRL_BACAP_RPMBBPWPS_NOT_SUPPORTED = 1, + NVME_CTRL_BACAP_RPMBBPWPS_SUPPORTED = 2, +}; + +/** + * enum nvme_id_ctrl_plsi - Power Loss Signaling Information + * @NVME_CTRL_PLSI_PLSEPF_SHIFT: Shift amount to get the PLS Emergency Power Fail from the + * &struct nvme_id_ctrl.plsi field. + * @NVME_CTRL_PLSI_PLSFQ_SHIFT: Shift amount to get the PLS Forced Quiescence from the + * &struct nvme_id_ctrl.plsi field. + * @NVME_CTRL_PLSI_PLSEPF_MASK: Mask to get the PLS Emergency Power Fail from the + * &struct nvme_id_ctrl.plsi field. + * @NVME_CTRL_PLSI_PLSFQ_MASK: Mask to get the PLS Forced Quiescence from the + * &struct nvme_id_ctrl.plsi field. + */ +enum nvme_id_ctrl_plsi { + NVME_CTRL_PLSI_PLSEPF_SHIFT = 0, + NVME_CTRL_PLSI_PLSFQ_SHIFT = 1, + NVME_CTRL_PLSI_PLSEPF_MASK = 0x1, + NVME_CTRL_PLSI_PLSFQ_MASK = 0x1, +}; + +/** + * enum nvme_id_ctrl_crcap - Power Loss Signaling Information + * @NVME_CTRL_CRCAP_RRSUP_SHIFT: Shift amount to get the Reachability Reporting Supported + * from the &struct nvme_id_ctrl.crcap field. + * @NVME_CTRL_CRCAP_RGIDC_SHIFT: Shift amount to get the Reachability Group ID Changeable + * from the &struct nvme_id_ctrl.crcap field. + * @NVME_CTRL_CRCAP_RRSUP_MASK: Mask to get the Reachability Reporting Supported from the + * &struct nvme_id_ctrl.crcap field. + * @NVME_CTRL_CRCAP_RGIDC_MASK: Mask to get the Reachability Group ID Changeable from the + * &struct nvme_id_ctrl.crcap field. + */ +enum nvme_id_ctrl_crcap { + NVME_CTRL_CRCAP_RRSUP_SHIFT = 0, + NVME_CTRL_CRCAP_RGIDC_SHIFT = 1, + NVME_CTRL_CRCAP_RRSUP_MASK = 0x1, + NVME_CTRL_CRCAP_RGIDC_MASK = 0x1, +}; + /** * enum nvme_id_ctrl_cntrltype - Controller types * @NVME_CTRL_CNTRLTYPE_IO: NVM I/O controller @@ -1767,7 +1875,7 @@ enum nvme_id_ctrl_dctype { * @NVME_CTRL_NVMSR_NVMESD: If set, then the NVM Subsystem is part of an NVMe * Storage Device; if cleared, then the NVM Subsystem * is not part of an NVMe Storage Device. - * @NVME_CTRL_NVMSR_NVMEE: If set’, then the NVM Subsystem is part of an NVMe + * @NVME_CTRL_NVMSR_NVMEE: If set, then the NVM Subsystem is part of an NVMe * Enclosure; if cleared, then the NVM Subsystem is * not part of an NVMe Enclosure. */ @@ -2027,6 +2135,25 @@ enum nvme_id_ctrl_anacap { NVME_CTRL_ANACAP_GRPID_MGMT = 1 << 7, }; + +/** + * enum nvme_id_ctrl_kpioc - Key Per I/O Capabilities + * @NVME_CTRL_KPIOC_KPIOS_SHIFT: Shift amount to get the Key Per I/O Supported from the + * &struct nvme_id_ctrl.kpioc field. + * @NVME_CTRL_KPIOC_KPIOSC_SHIFT: Shift amount to get the Key Per I/O Scope from the + * &struct nvme_id_ctrl.kpioc field. + * @NVME_CTRL_KPIOC_KPIOS_MASK: Mask to get the Key Per I/O Supported from the + * &struct nvme_id_ctrl.kpioc field. + * @NVME_CTRL_KPIOC_KPIOSC_MASK: Mask to get the Key Per I/O Scope from the + * &struct nvme_id_ctrl.kpioc field. + */ +enum nvme_id_ctrl_kpioc { + NVME_CTRL_KPIOC_KPIOS_SHIFT = 0, + NVME_CTRL_KPIOC_KPIOSC_SHIFT = 1, + NVME_CTRL_KPIOC_KPIOS_MASK = 0x1, + NVME_CTRL_KPIOC_KPIOSC_MASK = 0x1, +}; + /** * enum nvme_id_ctrl_sqes - Defines the required and maximum Submission Queue * entry size when using the NVM Command Set. @@ -3705,7 +3832,7 @@ enum nvme_cmd_get_log_telemetry_host_lsp { /** * enum nvme_telemetry_da - Telemetry Log Data Area - * @NVME_TELEMETRY_DA_CTRL_DETERMINE: + * @NVME_TELEMETRY_DA_CTRL_DETERMINE: The controller determines the data areas to be created * @NVME_TELEMETRY_DA_1: Data Area 1 * @NVME_TELEMETRY_DA_2: Data Area 2 * @NVME_TELEMETRY_DA_3: Data Area 3