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New arch support #461

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merged 138 commits into from
Feb 24, 2021
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cdcf78f
This branch contains support for new architectures.
pgoodman Sep 15, 2020
9876701
Initial start to support for AArch 32
sschriner Sep 15, 2020
78961ef
Progress
sschriner Sep 17, 2020
f292370
Forgot the new files
sschriner Sep 17, 2020
b83e040
Added all data Integer processing instructions without S + ADDS and s…
sschriner Sep 23, 2020
aa954cd
Updated
sschriner Sep 23, 2020
e3923a2
Finished Integer Data Processing with three registers, added integer …
sschriner Sep 28, 2020
67ba566
UMULL, UMULLS, UMLAL, UMLALS
sschriner Sep 29, 2020
73f0d2a
Corrected condition for addend or 0 immediate for UMULL/UMLAL + SMULL…
sschriner Sep 29, 2020
8618494
Correct ops in Binary.cpp
sschriner Sep 29, 2020
4e88cbd
UMAAL
sschriner Sep 29, 2020
4c9abfa
SMULL, SMULLS, SMLAL, SMLALS + corrected acc was missing shift left i…
sschriner Sep 29, 2020
f71420d
Updated decoding instructions based on top level encodings
sschriner Oct 5, 2020
f5cb08b
Update returns around kDataProcessingRI and kDataProcessingI with com…
sschriner Oct 6, 2020
cdc0587
Added appropriate inst.category flags to Multiply and accumulate
sschriner Oct 6, 2020
8642940
Load/Store Word, Unsigned Byte (immediate, literal) && start of Logic…
sschriner Oct 6, 2020
e9e7b41
Was missing UMAAL DEF_ISEL in Binary.cpp
sschriner Oct 7, 2020
9d48aae
AddAddrRegOp
sschriner Oct 8, 2020
5b82b03
Logical Arithmetic (three register, immediate shift) without accounti…
sschriner Oct 8, 2020
65af9f8
Made DecodeA32ExpandImm much much smaller
sschriner Oct 8, 2020
25f4e50
Replaced some imm ops with AddImmOp calls
sschriner Oct 9, 2020
14a7f06
Created AddShiftOp
sschriner Oct 9, 2020
26e6dbc
Added interpreter for evaluating new PC value at decoding time to han…
sschriner Oct 13, 2020
2674607
Created EvalPCDest added PC evaluation to Logical Arithmetic Instruct…
sschriner Oct 13, 2020
f7b2cd9
AddShiftOp -> AddShiftOp, AddShiftThenExtractOp, AddExtractThenShiftOp
sschriner Oct 13, 2020
f46cc4f
Cleaned up some formatting, Renamed DecodeA32ExpandImm to ExpandTo32A…
sschriner Oct 13, 2020
b3a98d3
Added comment to EvalPCDest for clarity
sschriner Oct 13, 2020
e17750b
Cleaned up some things, updated the decoding semantics and semantics …
sschriner Oct 14, 2020
9d77145
Shortened kLogArithEvaluators and fixed a bug
sschriner Oct 14, 2020
6c819b2
Updates from testing instructions
sschriner Oct 14, 2020
a77db18
Fixed DEF_ISEL for pre/post index instructions in MEM.cpp
sschriner Oct 15, 2020
6aca670
Integer Test and Compare (two register, immediate shift)
sschriner Oct 15, 2020
dda7737
Logical Arithmetic (two register and immediate)
sschriner Oct 15, 2020
803dbfe
Integer Test and Compare (one register and immediate)
sschriner Oct 15, 2020
e179f71
Added to the top level encoding infrastructure to handle the Data-pro…
sschriner Oct 15, 2020
c1d51d4
Add structs for the 3 subsets of Data-processing register (register s…
sschriner Oct 16, 2020
5160320
Code status before refactoring operand types
sschriner Oct 16, 2020
9d745ba
This branch contains support for new architectures.
pgoodman Sep 15, 2020
0b9eea9
Initial start to support for AArch 32
sschriner Sep 15, 2020
e4c7760
Progress
sschriner Sep 17, 2020
025255c
Forgot the new files
sschriner Sep 17, 2020
4090697
Added all data Integer processing instructions without S + ADDS and s…
sschriner Sep 23, 2020
0d0a7f4
Updated
sschriner Sep 23, 2020
488c1f1
Finished Integer Data Processing with three registers, added integer …
sschriner Sep 28, 2020
1020e26
UMULL, UMULLS, UMLAL, UMLALS
sschriner Sep 29, 2020
b38ecbc
Corrected condition for addend or 0 immediate for UMULL/UMLAL + SMULL…
sschriner Sep 29, 2020
c77ff3a
Correct ops in Binary.cpp
sschriner Sep 29, 2020
4580916
UMAAL
sschriner Sep 29, 2020
0e2bc86
SMULL, SMULLS, SMLAL, SMLALS + corrected acc was missing shift left i…
sschriner Sep 29, 2020
038724c
Updated decoding instructions based on top level encodings
sschriner Oct 5, 2020
8e28749
Update returns around kDataProcessingRI and kDataProcessingI with com…
sschriner Oct 6, 2020
10e7daa
Added appropriate inst.category flags to Multiply and accumulate
sschriner Oct 6, 2020
5820e8a
Load/Store Word, Unsigned Byte (immediate, literal) && start of Logic…
sschriner Oct 6, 2020
14d90c3
Was missing UMAAL DEF_ISEL in Binary.cpp
sschriner Oct 7, 2020
8aa2dde
AddAddrRegOp
sschriner Oct 8, 2020
6716d39
Logical Arithmetic (three register, immediate shift) without accounti…
sschriner Oct 8, 2020
99afe5f
Made DecodeA32ExpandImm much much smaller
sschriner Oct 8, 2020
3dc6356
Replaced some imm ops with AddImmOp calls
sschriner Oct 9, 2020
701d75e
Created AddShiftOp
sschriner Oct 9, 2020
84ad098
Added interpreter for evaluating new PC value at decoding time to han…
sschriner Oct 13, 2020
994952c
Created EvalPCDest added PC evaluation to Logical Arithmetic Instruct…
sschriner Oct 13, 2020
8302a1d
AddShiftOp -> AddShiftOp, AddShiftThenExtractOp, AddExtractThenShiftOp
sschriner Oct 13, 2020
b2e05af
Cleaned up some formatting, Renamed DecodeA32ExpandImm to ExpandTo32A…
sschriner Oct 13, 2020
a3b0d5c
Added comment to EvalPCDest for clarity
sschriner Oct 13, 2020
de1950d
Cleaned up some things, updated the decoding semantics and semantics …
sschriner Oct 14, 2020
2cdf979
Shortened kLogArithEvaluators and fixed a bug
sschriner Oct 14, 2020
896f77c
Updates from testing instructions
sschriner Oct 14, 2020
aee262e
Fixed DEF_ISEL for pre/post index instructions in MEM.cpp
sschriner Oct 15, 2020
fe85523
Integer Test and Compare (two register, immediate shift)
sschriner Oct 15, 2020
d831bdc
Logical Arithmetic (two register and immediate)
sschriner Oct 15, 2020
ae7ae3d
Integer Test and Compare (one register and immediate)
sschriner Oct 15, 2020
813b0fb
Added to the top level encoding infrastructure to handle the Data-pro…
sschriner Oct 15, 2020
436fa94
Add structs for the 3 subsets of Data-processing register (register s…
sschriner Oct 16, 2020
c3fa9d6
Code status before refactoring operand types
sschriner Oct 16, 2020
bfb0718
Merge branch 'new_arch_support' of github.com:lifting-bits/remill int…
sschriner Nov 4, 2020
2cf4366
Finished updates off master
sschriner Nov 4, 2020
e477f95
Start of operand refactor
sschriner Nov 4, 2020
7d5b84c
Finished Expression Operand Support
sschriner Nov 5, 2020
1147d8f
Fix the .gitignore to add AArch32 to lib/Arch && removed all extra rr…
sschriner Nov 9, 2020
91023a9
Updated .gitignore again, Added AddShiftRegRegOperand, Updated AddShi…
sschriner Nov 10, 2020
3608a8f
Updated ROR in AddShiftRegRegOperand
sschriner Nov 10, 2020
3333f88
Created ExtractAndZExtExpr
sschriner Nov 10, 2020
8dd8e70
Fixed comment formatting in if else statements
sschriner Nov 10, 2020
d0e1c5b
Created RORExpr
sschriner Nov 10, 2020
7210155
Small fixes
sschriner Nov 12, 2020
405b626
Small fix in Logical Arithmetic (two register and immediate)
sschriner Nov 12, 2020
5234e3e
Corrected AddShiftRegRegOperand and cleaned it up. Split the carry op…
sschriner Nov 13, 2020
534b023
conditional support + Start of Branch instructions
sschriner Nov 17, 2020
fc7920e
Created AddExprOp, cleaned up some expressions in reg shifted reg, an…
sschriner Nov 18, 2020
2c5bee6
Updates from testing register shifted by register value inst
sschriner Nov 18, 2020
98104dc
Fix to ROR in AddShiftRegCarryOperand
sschriner Nov 18, 2020
2ff5cdd
Corrected negation in DecodeCondition
sschriner Nov 19, 2020
9c0ea88
DecodeCondition edit
sschriner Nov 19, 2020
9969a22
Merge branch 'master' into new_arch_support
sschriner Nov 19, 2020
2a6398c
DecodeCondition and AddShiftRegCarryOperand edits
sschriner Nov 19, 2020
31da43f
Merge branch 'new_arch_support' of github.com:lifting-bits/remill int…
sschriner Nov 19, 2020
84f9efa
Updated arch_for_decode to arch
sschriner Nov 19, 2020
ddf993c
Halfword Multiply and Accumulate
sschriner Nov 20, 2020
df2e779
Edits from testing Halfword Multiply and Accumulate
sschriner Nov 20, 2020
9e275b2
Changed order of operands in Halfword Multiply and Accumulate to bett…
sschriner Nov 23, 2020
d0897bb
Branch (Imm) & BX/BXL
sschriner Dec 16, 2020
724eae5
Merge branch 'master' into new_arch_support
sschriner Dec 16, 2020
7655224
Update aarch32 cmake
sschriner Dec 16, 2020
09b74e1
cmake update
sschriner Dec 16, 2020
29eb9a6
CLZ
sschriner Dec 16, 2020
94b1e08
Forgot BITBYTE.cpp
sschriner Dec 16, 2020
350af45
MOVT
sschriner Dec 18, 2020
f4fcaaf
Integer Saturating Arithmetic
sschriner Dec 21, 2020
f8f9a60
updated semantics in SMLAWh & SMLAh to use Select for setting PSTATE.Q
sschriner Dec 21, 2020
d9bc627
Started Load/Store Word, Unsigned Byte (register) & fixed MOV halfword
sschriner Dec 29, 2020
caaa47f
Load/Store Word, Unsigned Byte (register)
sschriner Dec 30, 2020
03d3306
Finished testing load/Store Word, Unsigned Byte (register)
sschriner Dec 30, 2020
9de9323
Load/Store Dual, Half, Signed Byte (register)
sschriner Jan 6, 2021
0b9e841
Rest of Extra load store: Load/Store Dual, Half, Signed Byte (immedia…
sschriner Jan 6, 2021
4138ac4
Finished testing all the Load/store additions
sschriner Jan 11, 2021
b9699c7
Signed multiply, Divide
sschriner Jan 14, 2021
eccc55b
Cleaned up SExt some
sschriner Jan 14, 2021
43784a6
Saturate Insts and Start of Load Store Multiple - STMDB and LDM (alia…
sschriner Jan 20, 2021
8de19a3
Condensed args in STMDB and LDM semantics
sschriner Jan 21, 2021
c5ca741
Rest of Multiple Load/Store that do not execute in a different mode
sschriner Jan 21, 2021
d69619b
Bitfield Extract
sschriner Feb 4, 2021
8c62bf0
Extend and Add
sschriner Feb 4, 2021
f81b251
fix
sschriner Feb 4, 2021
f3b0f63
NOP
sschriner Feb 4, 2021
127c411
Small fix
sschriner Feb 4, 2021
4246c79
Simplified the bit reps in TryMoveSpecialRegisterAndHintsI
sschriner Feb 5, 2021
2bb350c
Moved Bitfield extract semantics out of BINARY and into BITBYTE
sschriner Feb 5, 2021
dfb919e
Merge branch 'master' of github.com:lifting-bits/remill into new_arch…
sschriner Feb 5, 2021
17faa18
Finished correcting S/ZExt and Trunc use
sschriner Feb 5, 2021
af548fe
Ran scripts/format-files to format
sschriner Feb 8, 2021
74649f3
Smoke Test
sschriner Feb 10, 2021
2696e70
Add false delay slot to kCategoryConditionalDirectFunctionCall
sschriner Feb 12, 2021
a58190f
Merge branch 'master' of github.com:lifting-bits/remill into new_arch…
sschriner Feb 19, 2021
c107fc9
Merge branch 'master' of github.com:lifting-bits/remill into new_arch…
sschriner Feb 22, 2021
76f8be1
CI: Use single packaging job, add changelog support (#491)
alessandrogario Feb 22, 2021
71cdec9
CI: Add tag handler (#492)
alessandrogario Feb 23, 2021
fbc5af9
Merge branch 'new_arch_support' of github.com:lifting-bits/remill int…
pgoodman Feb 24, 2021
fdb289b
Delay slot fixes to TraceLifter
pgoodman Feb 24, 2021
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3 changes: 3 additions & 0 deletions CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -183,6 +183,7 @@ else()
endif()

set(REMILL_BUILD_SEMANTICS_DIR_X86 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/X86/Runtime")
set(REMILL_BUILD_SEMANTICS_DIR_AARCH32 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/AArch32/Runtime")
set(REMILL_BUILD_SEMANTICS_DIR_AARCH64 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/AArch64/Runtime")
set(REMILL_BUILD_SEMANTICS_DIR_SPARC32 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/SPARC32/Runtime")
set(REMILL_BUILD_SEMANTICS_DIR_SPARC64 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/SPARC64/Runtime")
Expand Down Expand Up @@ -265,6 +266,7 @@ endif()
target_compile_definitions(remill_settings INTERFACE
"REMILL_INSTALL_SEMANTICS_DIR=\"${REMILL_INSTALL_SEMANTICS_DIR}/\""
"REMILL_BUILD_SEMANTICS_DIR_X86=\"${REMILL_BUILD_SEMANTICS_DIR_X86}\""
"REMILL_BUILD_SEMANTICS_DIR_AARCH32=\"${REMILL_BUILD_SEMANTICS_DIR_AARCH32}\""
"REMILL_BUILD_SEMANTICS_DIR_AARCH64=\"${REMILL_BUILD_SEMANTICS_DIR_AARCH64}\""
"REMILL_BUILD_SEMANTICS_DIR_SPARC32=\"${REMILL_BUILD_SEMANTICS_DIR_SPARC32}\""
"REMILL_BUILD_SEMANTICS_DIR_SPARC64=\"${REMILL_BUILD_SEMANTICS_DIR_SPARC64}\""
Expand Down Expand Up @@ -347,6 +349,7 @@ endif()
set(REMILL_BC_LIBRARY_LOCATION "${REMILL_INSTALL_LIB_DIR}/${static_lib_prefix}remill_bc.${static_lib_extension}")
set(REMILL_ARCH_LIBRARY_LOCATION "${REMILL_INSTALL_LIB_DIR}/${static_lib_prefix}remill_arch.${static_lib_extension}")
set(REMILL_ARCH_X86_LIBRARY_LOCATION "${REMILL_INSTALL_LIB_DIR}/${static_lib_prefix}remill_arch_x86.${static_lib_extension}")
set(REMILL_ARCH_AARCH32_LIBRARY_LOCATION "${REMILL_INSTALL_LIB_DIR}/${static_lib_prefix}remill_arch_aarch32.${static_lib_extension}")
set(REMILL_ARCH_AARCH64_LIBRARY_LOCATION "${REMILL_INSTALL_LIB_DIR}/${static_lib_prefix}remill_arch_aarch64.${static_lib_extension}")
set(REMILL_ARCH_SPARC32_LIBRARY_LOCATION "${REMILL_INSTALL_LIB_DIR}/${static_lib_prefix}remill_arch_sparc32.${static_lib_extension}")
set(REMILL_ARCH_SPARC64_LIBRARY_LOCATION "${REMILL_INSTALL_LIB_DIR}/${static_lib_prefix}remill_arch_sparc64.${static_lib_extension}")
Expand Down
2 changes: 2 additions & 0 deletions CMakeLists_vcpkg.txt
Original file line number Diff line number Diff line change
Expand Up @@ -145,6 +145,7 @@ math(EXPR REMILL_LLVM_VERSION_NUMBER "${LLVM_MAJOR_VERSION} * 100 + ${LLVM_MINOR
set(REMILL_INSTALL_SEMANTICS_DIR "${CMAKE_INSTALL_PREFIX}/${REMILL_INSTALL_SHARE_DIR}/remill/${REMILL_LLVM_VERSION}/semantics" CACHE PATH "Directory into which semantics are installed")

set(REMILL_BUILD_SEMANTICS_DIR_X86 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/X86/Runtime")
set(REMILL_BUILD_SEMANTICS_DIR_AARCH32 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/AArch32/Runtime")
set(REMILL_BUILD_SEMANTICS_DIR_AARCH64 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/AArch64/Runtime")
set(REMILL_BUILD_SEMANTICS_DIR_SPARC32 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/SPARC32/Runtime")
set(REMILL_BUILD_SEMANTICS_DIR_SPARC64 "${CMAKE_CURRENT_BINARY_DIR}/lib/Arch/SPARC64/Runtime")
Expand Down Expand Up @@ -230,6 +231,7 @@ endif()
target_compile_definitions(remill_settings INTERFACE
"REMILL_INSTALL_SEMANTICS_DIR=\"${REMILL_INSTALL_SEMANTICS_DIR}\""
"REMILL_BUILD_SEMANTICS_DIR_X86=\"${REMILL_BUILD_SEMANTICS_DIR_X86}\""
"REMILL_BUILD_SEMANTICS_DIR_AARCH32=\"${REMILL_BUILD_SEMANTICS_DIR_AARCH32}\""
"REMILL_BUILD_SEMANTICS_DIR_AARCH64=\"${REMILL_BUILD_SEMANTICS_DIR_AARCH64}\""
"REMILL_BUILD_SEMANTICS_DIR_SPARC32=\"${REMILL_BUILD_SEMANTICS_DIR_SPARC32}\""
"REMILL_BUILD_SEMANTICS_DIR_SPARC64=\"${REMILL_BUILD_SEMANTICS_DIR_SPARC64}\""
Expand Down
4 changes: 4 additions & 0 deletions cmake/remillConfig.cmake.in
Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,9 @@ if(NOT TARGET remill)
add_library(remill_arch_x86 STATIC IMPORTED)
set_property(TARGET remill_arch_x86 PROPERTY IMPORTED_LOCATION "@REMILL_ARCH_X86_LIBRARY_LOCATION@")

add_library(remill_arch_aarch32 STATIC IMPORTED)
set_property(TARGET remill_arch_aarch32 PROPERTY IMPORTED_LOCATION "@REMILL_ARCH_AARCH32_LIBRARY_LOCATION@")

add_library(remill_arch_aarch64 STATIC IMPORTED)
set_property(TARGET remill_arch_aarch64 PROPERTY IMPORTED_LOCATION "@REMILL_ARCH_AARCH64_LIBRARY_LOCATION@")

Expand All @@ -84,6 +87,7 @@ if(NOT TARGET remill)
remill_os
remill_arch
remill_arch_x86
remill_arch_aarch32
remill_arch_aarch64
remill_arch_sparc32
remill_arch_sparc64
Expand Down
32 changes: 32 additions & 0 deletions include/remill/Arch/AArch32/Runtime/Operators.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,32 @@
/*
* Copyright (c) 2017 Trail of Bits, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

#pragma once

namespace {

// Read a register directly. Sometimes this is needed for suppressed operands.
ALWAYS_INLINE static addr_t _Read(Memory *, Reg reg) {
return reg.aword;
}

// Write directly to a register. This is sometimes needed for suppressed
// register operands.
ALWAYS_INLINE static void _Write(Memory *, Reg &reg, addr_t val) {
reg.aword = val;
}

} // namespace
115 changes: 115 additions & 0 deletions include/remill/Arch/AArch32/Runtime/State.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,115 @@
/*
* Copyright (c) 2017 Trail of Bits, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

#pragma once

#pragma clang diagnostic push
#pragma clang diagnostic fatal "-Wpadded"

#include "remill/Arch/Runtime/State.h"
#include "remill/Arch/Runtime/Types.h"

struct Reg final {
alignas(4) uint32_t dword;
} __attribute__((packed));

static_assert(sizeof(uint32_t) == sizeof(Reg), "Invalid packing of `Reg`.");
static_assert(0 == __builtin_offsetof(Reg, dword),
"Invalid packing of `Reg::dword`.");

struct alignas(8) GPR final {

// Prevents LLVM from casting a `GPR` into an `i64` to access `X0`.
volatile uint32_t _0;
Reg r0;
volatile uint32_t _1;
Reg r1;
volatile uint32_t _2;
Reg r2;
volatile uint32_t _3;
Reg r3;
volatile uint32_t _4;
Reg r4;
volatile uint32_t _5;
Reg r5;
volatile uint32_t _6;
Reg r6;
volatile uint32_t _7;
Reg r7;
volatile uint32_t _8;
Reg r8;
volatile uint32_t _9;
Reg r9;
volatile uint32_t _10;
Reg r10;
volatile uint32_t _11;
Reg r11;
volatile uint32_t _12;
Reg r12;
// R13 is SP (stack pointer)
volatile uint32_t _13;
Reg r13;
// R14 is LR (link register)
volatile uint32_t _14;
Reg r14;
// R15 is PC (program counter)
volatile uint32_t _15;
Reg r15;


} __attribute__((packed));

// System registers affecting control and status of the machine.
struct alignas(8) SR final {

uint8_t _2;
uint8_t n; // Negative condition flag.
uint8_t _3;
uint8_t z; // Zero condition flag
uint8_t _4;
uint8_t c; // Carry condition flag
uint8_t _5;
uint8_t v; // Overflow condition flag

uint8_t _6;
uint8_t ixc; // Inexact (cumulative).
uint8_t _7;
uint8_t ofc; // Overflow (cumulative).
uint8_t _8;
uint8_t ufc; // Underflow (cumulative).
uint8_t _9;
uint8_t idc; // Input denormal (cumulative).
uint8_t _10;
uint8_t ioc; // Invalid operation (cumulative).
uint8_t _11;
uint8_t q; // Sticky overflow bit.

uint8_t _padding[4];
} __attribute__((packed));

struct alignas(16) State final : public ArchState {


GPR gpr; // 528 bytes.
SR sr;
uint64_t _0;


} __attribute__((packed));

using AArch32State = State;

#pragma clang diagnostic pop
72 changes: 72 additions & 0 deletions include/remill/Arch/AArch32/Runtime/Types.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,72 @@
/*
* Copyright (c) 2017 Trail of Bits, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

#pragma once

// We need this for boolean conditions, used in branch instructions.
typedef RnW<uint8_t> R8W;

typedef RnW<uint8_t> R8W;
typedef RnW<uint16_t> R16W;

// Note: AArch64 zero-extends like x86, but the smallest register size that
// can be accessed is 32 bits.
typedef RnW<uint32_t> R32W;

typedef Rn<uint8_t> R8;
//typedef Rn<uint16_t> R16;
typedef Rn<uint32_t> R32;

typedef Vn<vec8_t> V8;
typedef Vn<vec16_t> V16;
typedef Vn<vec32_t> V32;
typedef Vn<vec64_t> V64;
typedef Vn<vec128_t> V128;
typedef VnW<vec128_t> V128W;

typedef MnW<uint8_t> M8W;
typedef MnW<uint16_t> M16W;
typedef MnW<uint32_t> M32W;
typedef MnW<uint64_t> M64W;

typedef MVnW<vec8_t> MV8W;
typedef MVnW<vec16_t> MV16W;
typedef MVnW<vec32_t> MV32W;
typedef MVnW<vec64_t> MV64W;
typedef MVnW<vec128_t> MV128W;

typedef Mn<uint8_t> M8;
typedef Mn<uint16_t> M16;

typedef Mn<uint32_t> M32;
typedef Mn<uint64_t> M64;

typedef MVn<vec8_t> MV8;
typedef MVn<vec16_t> MV16;
typedef MVn<vec32_t> MV32;
typedef MVn<vec64_t> MV64;
typedef MVn<vec128_t> MV128;
typedef MVn<vec256_t> MV256;

typedef In<uint8_t> I8;
typedef In<uint16_t> I16;
typedef In<uint32_t> I32;

typedef In<float32_t> F32;
typedef In<float64_t> F64;

typedef In<addr_t> PC;
typedef In<addr_t> ADDR;
5 changes: 5 additions & 0 deletions include/remill/Arch/Arch.h
Original file line number Diff line number Diff line change
Expand Up @@ -246,6 +246,7 @@ class Arch {

bool IsX86(void) const;
bool IsAMD64(void) const;
bool IsAArch32(void) const;
bool IsAArch64(void) const;
bool IsSPARC32(void) const;
bool IsSPARC64(void) const;
Expand Down Expand Up @@ -287,6 +288,10 @@ class Arch {
static ArchPtr GetX86(llvm::LLVMContext *context, OSName os,
ArchName arch_name);

// Defined in `lib/Arch/AArch32/Arch.cpp`.
static ArchPtr GetAArch32(llvm::LLVMContext *context, OSName os,
ArchName arch_name);

// Defined in `lib/Arch/AArch64/Arch.cpp`.
static ArchPtr GetAArch64(llvm::LLVMContext *context, OSName os,
ArchName arch_name);
Expand Down
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