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New arch support #461

Merged
merged 138 commits into from
Feb 24, 2021
Merged

New arch support #461

merged 138 commits into from
Feb 24, 2021

Commits on Sep 15, 2020

  1. This branch contains support for new architectures.

    @pgoodman
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  2. Initial start to support for AArch 32

    @sschriner
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Commits on Sep 17, 2020

  1. Progress

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  2. Forgot the new files

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Commits on Sep 23, 2020

  1. Added all data Integer processing instructions without S + ADDS and s… 

    …tarted ANDS
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  2. Updated

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Commits on Sep 28, 2020

  1. Finished Integer Data Processing with three registers, added integer … 

    …data processing with 2 regs + immediate, started MUL instructions
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Commits on Sep 29, 2020

  1. UMULL, UMULLS, UMLAL, UMLALS

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  2. Corrected condition for addend or 0 immediate for UMULL/UMLAL + SMULL… 

    …/SMLAL instructions
    @sschriner
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  3. Correct ops in Binary.cpp

    @sschriner
    sschriner committed Sep 29, 2020
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  4. UMAAL

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  5. SMULL, SMULLS, SMLAL, SMLALS + corrected acc was missing shift left i… 

    …n concatination
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Commits on Oct 5, 2020

  1. Updated decoding instructions based on top level encodings

    @sschriner
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Commits on Oct 6, 2020

  1. Update returns around kDataProcessingRI and kDataProcessingI with com… 

    …ments to explain the correlation to the instruction rep
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  2. Added appropriate inst.category flags to Multiply and accumulate

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  3. Load/Store Word, Unsigned Byte (immediate, literal) && start of Logic… 

    …al Arithmetic (three register, immediate shift)
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Commits on Oct 7, 2020

  1. Was missing UMAAL DEF_ISEL in Binary.cpp

    @sschriner
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Commits on Oct 8, 2020

  1. AddAddrRegOp

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  2. Logical Arithmetic (three register, immediate shift) without accounti… 

    …ng for the possible PC jump
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  3. Made DecodeA32ExpandImm much much smaller

    @sschriner
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Commits on Oct 9, 2020

  1. Replaced some imm ops with AddImmOp calls

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  2. Created AddShiftOp

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Commits on Oct 13, 2020

  1. Added interpreter for evaluating new PC value at decoding time to han… 

    …dle direct jumps and conditional jumps
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  2. Created EvalPCDest added PC evaluation to Logical Arithmetic Instruct… 

    …ions
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  3. AddShiftOp -> AddShiftOp, AddShiftThenExtractOp, AddExtractThenShiftOp

    @sschriner
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  4. Cleaned up some formatting, Renamed DecodeA32ExpandImm to ExpandTo32A… 

    …ddImmAddCarry and added a clarifying comment
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  5. Added comment to EvalPCDest for clarity

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Commits on Oct 14, 2020

  1. Cleaned up some things, updated the decoding semantics and semantics … 

    …for the logical instructions
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  2. Shortened kLogArithEvaluators and fixed a bug

    @sschriner
    sschriner committed Oct 14, 2020
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  3. Updates from testing instructions

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    sschriner committed Oct 14, 2020
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Commits on Oct 15, 2020

  1. Fixed DEF_ISEL for pre/post index instructions in MEM.cpp

    @sschriner
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  2. Integer Test and Compare (two register, immediate shift)

    @sschriner
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  3. Logical Arithmetic (two register and immediate)

    @sschriner
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  4. Integer Test and Compare (one register and immediate)

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  5. Added to the top level encoding infrastructure to handle the Data-pro… 

    …cessing register (register shift) set of instructions and 3 corresponding subsets
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Commits on Oct 16, 2020

  1. Add structs for the 3 subsets of Data-processing register (register s… 

    …hift)
    @sschriner
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  2. Code status before refactoring operand types

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Commits on Nov 4, 2020

  1. This branch contains support for new architectures.

    @pgoodman @sschriner
    pgoodman authored and sschriner committed Nov 4, 2020
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  2. Initial start to support for AArch 32

    @sschriner
    sschriner committed Nov 4, 2020
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  3. Progress

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  4. Forgot the new files

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  5. Added all data Integer processing instructions without S + ADDS and s… 

    …tarted ANDS
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  6. Updated

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  7. Finished Integer Data Processing with three registers, added integer … 

    …data processing with 2 regs + immediate, started MUL instructions
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  8. UMULL, UMULLS, UMLAL, UMLALS

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  9. Corrected condition for addend or 0 immediate for UMULL/UMLAL + SMULL… 

    …/SMLAL instructions
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    sschriner committed Nov 4, 2020
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  10. Correct ops in Binary.cpp

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  11. UMAAL

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  12. SMULL, SMULLS, SMLAL, SMLALS + corrected acc was missing shift left i… 

    …n concatination
    @sschriner
    sschriner committed Nov 4, 2020
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  13. Updated decoding instructions based on top level encodings

    @sschriner
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  14. Update returns around kDataProcessingRI and kDataProcessingI with com… 

    …ments to explain the correlation to the instruction rep
    @sschriner
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  15. Added appropriate inst.category flags to Multiply and accumulate

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  16. Load/Store Word, Unsigned Byte (immediate, literal) && start of Logic… 

    …al Arithmetic (three register, immediate shift)
    @sschriner
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  17. Was missing UMAAL DEF_ISEL in Binary.cpp

    @sschriner
    sschriner committed Nov 4, 2020
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  18. AddAddrRegOp

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  19. Logical Arithmetic (three register, immediate shift) without accounti… 

    …ng for the possible PC jump
    @sschriner
    sschriner committed Nov 4, 2020
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  20. Made DecodeA32ExpandImm much much smaller

    @sschriner
    sschriner committed Nov 4, 2020
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  21. Replaced some imm ops with AddImmOp calls

    @sschriner
    sschriner committed Nov 4, 2020
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  22. Created AddShiftOp

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  23. Added interpreter for evaluating new PC value at decoding time to han… 

    …dle direct jumps and conditional jumps
    @sschriner
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  24. Created EvalPCDest added PC evaluation to Logical Arithmetic Instruct… 

    …ions
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  25. AddShiftOp -> AddShiftOp, AddShiftThenExtractOp, AddExtractThenShiftOp

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  26. Cleaned up some formatting, Renamed DecodeA32ExpandImm to ExpandTo32A… 

    …ddImmAddCarry and added a clarifying comment
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  27. Added comment to EvalPCDest for clarity

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  28. Cleaned up some things, updated the decoding semantics and semantics … 

    …for the logical instructions
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  29. Shortened kLogArithEvaluators and fixed a bug

    @sschriner
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  30. Updates from testing instructions

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  31. Fixed DEF_ISEL for pre/post index instructions in MEM.cpp

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  32. Integer Test and Compare (two register, immediate shift)

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  33. Logical Arithmetic (two register and immediate)

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  34. Integer Test and Compare (one register and immediate)

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  35. Added to the top level encoding infrastructure to handle the Data-pro… 

    …cessing register (register shift) set of instructions and 3 corresponding subsets
    @sschriner
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  36. Add structs for the 3 subsets of Data-processing register (register s… 

    …hift)
    @sschriner
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  37. Code status before refactoring operand types

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  38. Merge branch 'new_arch_support' of github.com:lifting-bits/remill int… 

    …o new_arch_support
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  39. Finished updates off master

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  40. Start of operand refactor

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Commits on Nov 5, 2020

  1. Finished Expression Operand Support

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Commits on Nov 9, 2020

  1. Fix the .gitignore to add AArch32 to lib/Arch && removed all extra rr… 

    …x ops from semantics
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Commits on Nov 10, 2020

  1. Updated .gitignore again, Added AddShiftRegRegOperand, Updated AddShi… 

    …ftRegImmOperand, Finished Register shift instructions for Integer Test and Compare, Logical Arithmetic, Integer Data Processing
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  2. Updated ROR in AddShiftRegRegOperand

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  3. Created ExtractAndZExtExpr

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  4. Fixed comment formatting in if else statements

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  5. Created RORExpr

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Commits on Nov 12, 2020

  1. Small fixes

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  2. Small fix in Logical Arithmetic (two register and immediate)

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Commits on Nov 13, 2020

  1. Corrected AddShiftRegRegOperand and cleaned it up. Split the carry op… 

    … into a separate function.
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Commits on Nov 17, 2020

  1. conditional support + Start of Branch instructions

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Commits on Nov 18, 2020

  1. Created AddExprOp, cleaned up some expressions in reg shifted reg, an… 

    …d updated some occurances of ShiftThenExtractOp with ExtractAndZExtExpr
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  2. Updates from testing register shifted by register value inst

    @sschriner
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  3. Fix to ROR in AddShiftRegCarryOperand

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Commits on Nov 19, 2020

  1. Corrected negation in DecodeCondition

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  2. DecodeCondition edit

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  3. Merge branch 'master' into new_arch_support

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  4. DecodeCondition and AddShiftRegCarryOperand edits

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  5. Merge branch 'new_arch_support' of github.com:lifting-bits/remill int… 

    …o new_arch_support
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  6. Updated arch_for_decode to arch

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Commits on Nov 20, 2020

  1. Halfword Multiply and Accumulate

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  2. Edits from testing Halfword Multiply and Accumulate

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Commits on Nov 23, 2020

  1. Changed order of operands in Halfword Multiply and Accumulate to bett… 

    …er reflect inst format + updated inst errors
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Commits on Dec 16, 2020

  1. Branch (Imm) & BX/BXL

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  2. Merge branch 'master' into new_arch_support

    @sschriner
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  3. Update aarch32 cmake

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  4. cmake update

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  5. CLZ

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  6. Forgot BITBYTE.cpp

    @sschriner
    sschriner committed Dec 16, 2020
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Commits on Dec 18, 2020

  1. MOVT

    @sschriner
    sschriner committed Dec 18, 2020
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Commits on Dec 21, 2020

  1. Integer Saturating Arithmetic

    @sschriner
    sschriner committed Dec 21, 2020
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  2. updated semantics in SMLAWh & SMLAh to use Select for setting PSTATE.Q

    @sschriner
    sschriner committed Dec 21, 2020
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Commits on Dec 29, 2020

  1. Started Load/Store Word, Unsigned Byte (register) & fixed MOV halfword

    @sschriner
    sschriner committed Dec 29, 2020
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Commits on Dec 30, 2020

  1. Load/Store Word, Unsigned Byte (register)

    @sschriner
    sschriner committed Dec 30, 2020
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  2. Finished testing load/Store Word, Unsigned Byte (register)

    @sschriner
    sschriner committed Dec 30, 2020
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Commits on Jan 6, 2021

  1. Load/Store Dual, Half, Signed Byte (register)

    @sschriner
    sschriner committed Jan 6, 2021
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  2. Rest of Extra load store: Load/Store Dual, Half, Signed Byte (immedia… 

    …te, literal)
    @sschriner
    sschriner committed Jan 6, 2021
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Commits on Jan 11, 2021

  1. Finished testing all the Load/store additions

    @sschriner
    sschriner committed Jan 11, 2021
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Commits on Jan 14, 2021

  1. Signed multiply, Divide

    @sschriner
    sschriner committed Jan 14, 2021
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  2. Cleaned up SExt some

    @sschriner
    sschriner committed Jan 14, 2021
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Commits on Jan 20, 2021

  1. Saturate Insts and Start of Load Store Multiple - STMDB and LDM (alia… 

    …ses which support PUSH and POP of multiple regs)
    @sschriner
    sschriner committed Jan 20, 2021
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Commits on Jan 21, 2021

  1. Condensed args in STMDB and LDM semantics

    @sschriner
    sschriner committed Jan 21, 2021
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  2. Rest of Multiple Load/Store that do not execute in a different mode

    @sschriner
    sschriner committed Jan 21, 2021
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Commits on Feb 4, 2021

  1. Bitfield Extract

    @sschriner
    sschriner committed Feb 4, 2021
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  2. Extend and Add

    @sschriner
    sschriner committed Feb 4, 2021
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  3. fix

    @sschriner
    sschriner committed Feb 4, 2021
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  4. NOP

    @sschriner
    sschriner committed Feb 4, 2021
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  5. Small fix

    @sschriner
    sschriner committed Feb 4, 2021
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Commits on Feb 5, 2021

  1. Simplified the bit reps in TryMoveSpecialRegisterAndHintsI

    @sschriner
    sschriner committed Feb 5, 2021
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  2. Moved Bitfield extract semantics out of BINARY and into BITBYTE

    @sschriner
    sschriner committed Feb 5, 2021
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  3. Merge branch 'master' of github.com:lifting-bits/remill into new_arch… 

    …_support
    @sschriner
    sschriner committed Feb 5, 2021
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  4. Finished correcting S/ZExt and Trunc use

    @sschriner
    sschriner committed Feb 5, 2021
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Commits on Feb 8, 2021

  1. Ran scripts/format-files to format

    @sschriner
    sschriner committed Feb 8, 2021
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Commits on Feb 10, 2021

  1. Smoke Test

    @sschriner
    sschriner committed Feb 10, 2021
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Commits on Feb 12, 2021

  1. Add false delay slot to kCategoryConditionalDirectFunctionCall

    @sschriner
    sschriner committed Feb 12, 2021
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Commits on Feb 19, 2021

  1. Merge branch 'master' of github.com:lifting-bits/remill into new_arch… 

    …_support
    @sschriner
    sschriner committed Feb 19, 2021
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Commits on Feb 22, 2021

  1. Merge branch 'master' of github.com:lifting-bits/remill into new_arch… 

    …_support
    @sschriner
    sschriner committed Feb 22, 2021
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  2. CI: Use single packaging job, add changelog support (#491)

    @alessandrogario
    alessandrogario authored Feb 22, 2021
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Commits on Feb 23, 2021

  1. CI: Add tag handler (#492)

    @alessandrogario
    alessandrogario authored Feb 23, 2021
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Commits on Feb 24, 2021

  1. Merge branch 'new_arch_support' of github.com:lifting-bits/remill int… 

    …o new_arch_support
    @pgoodman
    pgoodman committed Feb 24, 2021
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  2. Delay slot fixes to TraceLifter

    @pgoodman
    pgoodman committed Feb 24, 2021
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