From 75e55f7d5938ce404496a14cdcf83bf4741834f6 Mon Sep 17 00:00:00 2001 From: Keyi Zhang Date: Wed, 15 May 2019 21:37:58 -0700 Subject: [PATCH 1/3] add number of cycles to ncsim --- fault/system_verilog_target.py | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py index 61176113..bcf36ed0 100644 --- a/fault/system_verilog_target.py +++ b/fault/system_verilog_target.py @@ -32,19 +32,12 @@ endmodule """ -ncsim_cmd_string = """\ -database -open -vcd vcddb -into verilog.vcd -default -timescale ps -probe -create -all -vcd -depth all -run 10000ns -quit -""" - class SystemVerilogTarget(VerilogTarget): def __init__(self, circuit, circuit_name=None, directory="build/", skip_compile=False, magma_output="coreir-verilog", magma_opts={}, include_verilog_libraries=[], simulator=None, - timescale="1ns/1ns", clock_step_delay=5): + timescale="1ns/1ns", clock_step_delay=5, num_cycle=10000): """ circuit: a magma circuit @@ -78,6 +71,7 @@ def __init__(self, circuit, circuit_name=None, directory="build/", self.simulator = simulator self.timescale = timescale self.clock_step_delay = clock_step_delay + self.num_cycle = num_cycle self.declarations = [] def make_name(self, port): @@ -272,6 +266,11 @@ def run(self, actions): self.include_verilog_libraries) cmd_file = Path(f"{self.circuit_name}_cmd.tcl") if self.simulator == "ncsim": + ncsim_cmd_string = f"""\ +database -open -vcd vcddb -into verilog.vcd -default -timescale ps +probe -create -all -vcd -depth all +run {self.num_cycle}ns +quit""" with open(self.directory / cmd_file, "w") as f: f.write(ncsim_cmd_string) cmd = f"""\ From be24833328bbbe3e0c5346671cf063b1d2b7477f Mon Sep 17 00:00:00 2001 From: Keyi Zhang Date: Fri, 17 May 2019 16:37:46 -0700 Subject: [PATCH 2/3] add more ncsim options --- fault/system_verilog_target.py | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py index bcf36ed0..8296b4bd 100644 --- a/fault/system_verilog_target.py +++ b/fault/system_verilog_target.py @@ -37,7 +37,8 @@ class SystemVerilogTarget(VerilogTarget): def __init__(self, circuit, circuit_name=None, directory="build/", skip_compile=False, magma_output="coreir-verilog", magma_opts={}, include_verilog_libraries=[], simulator=None, - timescale="1ns/1ns", clock_step_delay=5, num_cycle=10000): + timescale="1ns/1ns", clock_step_delay=5, num_cycle=10000, + dump_vcd=True, no_warning=False): """ circuit: a magma circuit @@ -72,6 +73,8 @@ def __init__(self, circuit, circuit_name=None, directory="build/", self.timescale = timescale self.clock_step_delay = clock_step_delay self.num_cycle = num_cycle + self.dump_vcd = dump_vcd + self.no_warning = no_warning self.declarations = [] def make_name(self, port): @@ -266,15 +269,24 @@ def run(self, actions): self.include_verilog_libraries) cmd_file = Path(f"{self.circuit_name}_cmd.tcl") if self.simulator == "ncsim": - ncsim_cmd_string = f"""\ + if self.dump_vcd: + vcd_command = """ database -open -vcd vcddb -into verilog.vcd -default -timescale ps -probe -create -all -vcd -depth all +probe -create -all -vcd -depth all""" + else: + vcd_command = "" + ncsim_cmd_string = f"""\ +{vcd_command} run {self.num_cycle}ns quit""" + if self.no_warning: + warning = "-neverwarn" + else: + warning = "" with open(self.directory / cmd_file, "w") as f: f.write(ncsim_cmd_string) cmd = f"""\ -irun -top {self.circuit_name}_tb -timescale {self.timescale} -access +rwc -notimingchecks -input {cmd_file} {test_bench_file} {self.verilog_file} {verilog_libraries} +irun -top {self.circuit_name}_tb -timescale {self.timescale} -access +rwc -notimingchecks {warning} -input {cmd_file} {test_bench_file} {self.verilog_file} {verilog_libraries} """ # nopep8 elif self.simulator == "vcs": cmd = f"""\ From 15a748441bba4d24acfa4652284127a7bf801fd5 Mon Sep 17 00:00:00 2001 From: Keyi Zhang Date: Sat, 18 May 2019 23:00:46 -0700 Subject: [PATCH 3/3] fix typo --- fault/system_verilog_target.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py index 8296b4bd..0ae7bac9 100644 --- a/fault/system_verilog_target.py +++ b/fault/system_verilog_target.py @@ -37,7 +37,7 @@ class SystemVerilogTarget(VerilogTarget): def __init__(self, circuit, circuit_name=None, directory="build/", skip_compile=False, magma_output="coreir-verilog", magma_opts={}, include_verilog_libraries=[], simulator=None, - timescale="1ns/1ns", clock_step_delay=5, num_cycle=10000, + timescale="1ns/1ns", clock_step_delay=5, num_cycles=10000, dump_vcd=True, no_warning=False): """ circuit: a magma circuit @@ -72,7 +72,7 @@ def __init__(self, circuit, circuit_name=None, directory="build/", self.simulator = simulator self.timescale = timescale self.clock_step_delay = clock_step_delay - self.num_cycle = num_cycle + self.num_cycles = num_cycles self.dump_vcd = dump_vcd self.no_warning = no_warning self.declarations = [] @@ -277,7 +277,7 @@ def run(self, actions): vcd_command = "" ncsim_cmd_string = f"""\ {vcd_command} -run {self.num_cycle}ns +run {self.num_cycles}ns quit""" if self.no_warning: warning = "-neverwarn"