From 841d423ecfb07ee4d46587d854b60da4d47f9a98 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 22 Aug 2023 14:06:10 -0700 Subject: [PATCH 01/45] Fix style --- tests/test_tester/test_core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/test_tester/test_core.py b/tests/test_tester/test_core.py index 4315b022..857aaf98 100644 --- a/tests/test_tester/test_core.py +++ b/tests/test_tester/test_core.py @@ -23,7 +23,7 @@ def pytest_generate_tests(metafunc): def check(got, expected): - assert type(got) == type(expected) + assert isinstance(got, type(expected)) if isinstance(got, actions.PortAction): assert got.port is expected.port assert got.value == expected.value From b58f970ed0f16e66c59a4e78ebe4cc106a0ac987 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 12 Oct 2023 22:49:49 +0200 Subject: [PATCH 02/45] [assert] add support for when+assert_immediate (#324) * [assert] add support for when+assert_immediate * Add skip compile * Share tempdir * Fix directory logic --- fault/assert_immediate.py | 10 ++++++++++ tests/test_assert_immediate.py | 36 ++++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/fault/assert_immediate.py b/fault/assert_immediate.py index 1167d463..ce86ba1b 100644 --- a/fault/assert_immediate.py +++ b/fault/assert_immediate.py @@ -1,4 +1,5 @@ import magma as m +from magma.when import get_curr_block as get_curr_when_block, no_when from fault.property import Posedge from fault.assert_utils import add_compile_guards @@ -66,6 +67,15 @@ def _add_docstr(fn): @_add_docstr def assert_immediate(cond, success_msg=None, failure_msg=None, severity="error", name=None, compile_guard=None, inline_wire_prefix=None): + if get_curr_when_block(): + # guard condition by current active when using a boolean with default 0 + # and assigned inside when + with no_when(): + when_cond = m.Bit() + when_cond @= 0 + when_cond @= 1 + cond = ~when_cond | cond + _make_assert("always @(*)", cond, success_msg, failure_msg, severity, name, compile_guard, inline_wire_prefix=inline_wire_prefix) diff --git a/tests/test_assert_immediate.py b/tests/test_assert_immediate.py index 98d1a0c8..2d7666f9 100644 --- a/tests/test_assert_immediate.py +++ b/tests/test_assert_immediate.py @@ -178,3 +178,39 @@ class Foo(m.Circuit): tester.compile_and_run("system-verilog", simulator="ncsim", magma_opts={"inline": True, "sv": True}, directory=dir_) + + +def test_assert_when(): + if verilator_version() < 4.0: + pytest.skip("Untested with earlier verilator versions") + + class Foo(m.Circuit): + io = m.IO( + I0=m.In(m.Bit), + I1=m.In(m.Bit), + S=m.In(m.Bit) + ) + with m.when(io.S): + f.assert_immediate(~(io.I0 & io.I1)) + + tester = f.Tester(Foo) + tester.circuit.I0 = 1 + tester.circuit.I1 = 1 + tester.circuit.S = 1 + tester.eval() + with tempfile.TemporaryDirectory() as dir_: + with pytest.raises(AssertionError): + tester.compile_and_run("verilator", + magma_output="mlir-verilog", + flags=['--assert'], directory=dir_, + disp_type="realtime") + + tester.clear() + tester.circuit.I0 = 1 + tester.circuit.I1 = 1 + tester.eval() + tester.compile_and_run("verilator", + magma_output="mlir-verilog", + flags=['--assert'], directory=dir_, + skip_compile=True, + disp_type="realtime") From 314821aca787f563a8d16f808a1946e5c9c86ff0 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 19 Oct 2023 12:44:23 -0700 Subject: [PATCH 03/45] Update macos.yml (#331) --- .github/workflows/macos.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/macos.yml b/.github/workflows/macos.yml index cbffba66..f6edf53e 100644 --- a/.github/workflows/macos.yml +++ b/.github/workflows/macos.yml @@ -20,7 +20,7 @@ jobs: uses: conda-incubator/setup-miniconda@v2 with: auto-update-conda: true - python-version: 3.7 + python-version: 3.8 - name: Install verilator shell: bash run: | From 6f12d5f5b0713b7c9ecacc817e643ca70ee422fb Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 19 Oct 2023 13:26:13 -0700 Subject: [PATCH 04/45] Release v3.2.0 --- setup.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/setup.py b/setup.py index b52d32c3..c3af5cb0 100644 --- a/setup.py +++ b/setup.py @@ -13,7 +13,7 @@ setup( name='fault', - version='3.1.3', + version='3.2.0', description=DESCRIPTION, scripts=[], packages=[ From 2905be84a0a7e7927af2e16269a032fef7393392 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 19 Oct 2023 17:04:33 -0700 Subject: [PATCH 05/45] Deprecate coreir (#332) * Remove coreir dependency * Fix pysv support * Add no coreir test * Add no coreir test --------- Co-authored-by: Lenny Truong --- conftest.py | 7 ++----- setup.py | 2 -- tests/test_no_coreir.py | 18 ++++++++++++++++++ 3 files changed, 20 insertions(+), 7 deletions(-) create mode 100644 tests/test_no_coreir.py diff --git a/conftest.py b/conftest.py index 0e09e9d4..5ef9af65 100644 --- a/conftest.py +++ b/conftest.py @@ -1,14 +1,11 @@ import pytest -from magma import clear_cachedFunctions -import magma import logging +from magma.util import reset_global_context collect_ignore = ["src"] # pip folder that contains dependencies like magma @pytest.fixture(autouse=True) def magma_test(): - clear_cachedFunctions() - magma.frontend.coreir_.ResetCoreIR() - magma.generator.reset_generator_cache() + reset_global_context() logging.getLogger().setLevel(logging.DEBUG) diff --git a/setup.py b/setup.py index c3af5cb0..b9dd9d3c 100644 --- a/setup.py +++ b/setup.py @@ -22,8 +22,6 @@ ], install_requires=[ "astor", - "coreir", - "cosa", "z3-solver", "hwtypes", "magma-lang>=2.2.3", diff --git a/tests/test_no_coreir.py b/tests/test_no_coreir.py new file mode 100644 index 00000000..cb92b621 --- /dev/null +++ b/tests/test_no_coreir.py @@ -0,0 +1,18 @@ +import hwtypes as ht +import fault as f +import magma as m + +import pytest + + +def test_fault_no_coreir(): + class Foo(m.Circuit): + io = m.IO(I=m.In(m.Bits[16]), O=m.Out(m.Bits[16])) + io.O @= io.I & 0xFF + + tester = f.Tester(Foo) + tester.circuit.I = I = ht.BitVector.random(16) + tester.eval() + tester.circuit.O.expect(I & 0xFF) + + tester.compile_and_run("verilator", magma_output="mlir-verilog") From 455e8606e8b9f8ca3cba94cb2efc9812067ec683 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Wed, 15 Nov 2023 14:15:13 -0800 Subject: [PATCH 06/45] Avoid traversing arrays/tuple in clock logic (#323) Should only descend into tuple/array if there's a nested clock type, otherwise skip (avoids lazy children elaboration when possible). --- fault/tester/base.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fault/tester/base.py b/fault/tester/base.py index 5662e6fe..1b62a9c0 100644 --- a/fault/tester/base.py +++ b/fault/tester/base.py @@ -1,5 +1,6 @@ import logging import magma as m +from magma.clock import is_clock_or_nested_clock from abc import abstractmethod from ..wrapper import CircuitWrapper, PortWrapper from ..select_path import SelectPath @@ -57,7 +58,7 @@ def _find_default_clock(self, ports): next_clock = None if isinstance(port, m.Clock): next_clock = port - elif isinstance(port, (m.Array, m.Tuple)): + elif is_clock_or_nested_clock(type(port)): nested_clock = self._find_default_clock(port.ts) if nested_clock is not None: next_clock = nested_clock From 6bde0b069d487822be69c176b8f78730a05f7501 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 16 Nov 2023 11:51:44 -0800 Subject: [PATCH 07/45] Fix regression --- fault/tester/base.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fault/tester/base.py b/fault/tester/base.py index 1b62a9c0..ad750507 100644 --- a/fault/tester/base.py +++ b/fault/tester/base.py @@ -58,7 +58,7 @@ def _find_default_clock(self, ports): next_clock = None if isinstance(port, m.Clock): next_clock = port - elif is_clock_or_nested_clock(type(port)): + elif is_clock_or_nested_clock(type(port), (m.Clock,)): nested_clock = self._find_default_clock(port.ts) if nested_clock is not None: next_clock = nested_clock From 5ddc4e4dff865e3678c1952b79523053b9075f72 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 16 Nov 2023 11:52:28 -0800 Subject: [PATCH 08/45] Disable fpga build --- .buildkite/pipeline.yml | 76 ++++++++++++++++++++--------------------- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml index 909fe3cc..2f500935 100644 --- a/.buildkite/pipeline.yml +++ b/.buildkite/pipeline.yml @@ -36,41 +36,41 @@ steps: timeout_in_minutes: 60 agents: fault2: "true" - - command: | - # set up environment - source /etc/environment - echo $$PATH - - # create conda env - wget https://repo.anaconda.com/miniconda/Miniconda3-latest-Linux-x86_64.sh - chmod +x Miniconda3-latest-Linux-x86_64.sh - ./Miniconda3-latest-Linux-x86_64.sh -b -u -p $$PWD/miniconda - export PATH=$$PWD/miniconda/bin:$$PATH - conda install python==3.8 -y -q - - # install python dependencies for testing - pip install wheel - pip install "pytest<6" - pip install pytest-cov pytest-pycodestyle - pip install vcdvcd decorator kratos - pip install --upgrade "mantle>=2.0.0" - pip install DeCiDa scipy numpy - - # use the latest cmake - pip install cmake - - # install fault - pip install -e . - - # run tests - pytest --pycodestyle --cov-report=xml --cov=fault tests/ -v -r s - - # upload coverage results - bash <(curl -s https://codecov.io/bash) - - # deactivate virtual environment - deactivate - label: "fpga_verif" - timeout_in_minutes: 60 - agents: - fpga_verif: "true" +# - command: | +# # set up environment +# source /etc/environment +# echo $$PATH +# +# # create conda env +# wget https://repo.anaconda.com/miniconda/Miniconda3-latest-Linux-x86_64.sh +# chmod +x Miniconda3-latest-Linux-x86_64.sh +# ./Miniconda3-latest-Linux-x86_64.sh -b -u -p $$PWD/miniconda +# export PATH=$$PWD/miniconda/bin:$$PATH +# conda install python==3.8 -y -q +# +# # install python dependencies for testing +# pip install wheel +# pip install "pytest<6" +# pip install pytest-cov pytest-pycodestyle +# pip install vcdvcd decorator kratos +# pip install --upgrade "mantle>=2.0.0" +# pip install DeCiDa scipy numpy +# +# # use the latest cmake +# pip install cmake +# +# # install fault +# pip install -e . +# +# # run tests +# pytest --pycodestyle --cov-report=xml --cov=fault tests/ -v -r s +# +# # upload coverage results +# bash <(curl -s https://codecov.io/bash) +# +# # deactivate virtual environment +# deactivate +# label: "fpga_verif" +# timeout_in_minutes: 60 +# agents: +# fpga_verif: "true" From c3bc05808988249754846a66f00d1525ef72d7bc Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 16 Nov 2023 11:56:10 -0800 Subject: [PATCH 09/45] Test build --- .buildkite/pipeline.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml index 2f500935..7b5c7e2e 100644 --- a/.buildkite/pipeline.yml +++ b/.buildkite/pipeline.yml @@ -36,6 +36,7 @@ steps: timeout_in_minutes: 60 agents: fault2: "true" + # - command: | # # set up environment # source /etc/environment From dfe708fd5bae4c397c7e255d55b402fd13c00345 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 16 Nov 2023 11:56:57 -0800 Subject: [PATCH 10/45] Test --- .buildkite/pipeline.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml index 7b5c7e2e..2ca34770 100644 --- a/.buildkite/pipeline.yml +++ b/.buildkite/pipeline.yml @@ -75,3 +75,4 @@ steps: # timeout_in_minutes: 60 # agents: # fpga_verif: "true" + From 948ce440d396c6c7467a37237f6037d4f49f01a2 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 16 Nov 2023 12:16:38 -0800 Subject: [PATCH 11/45] Skip --- tests/test_kratos_debug.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/test_kratos_debug.py b/tests/test_kratos_debug.py index 9ae64c29..847ca295 100644 --- a/tests/test_kratos_debug.py +++ b/tests/test_kratos_debug.py @@ -10,6 +10,8 @@ import hwtypes +pytest.skip("kratos_runtime archived", allow_module_level=True) + has_runtime = fault.util.has_kratos_runtime() From e997c4fdc61269553edac8e58e2ea1b40525d919 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 16 Nov 2023 12:40:54 -0800 Subject: [PATCH 12/45] Use mlir-verilog --- tests/test_property.py | 70 +++++++++++++++++++++--------------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/tests/test_property.py b/tests/test_property.py index 68d48678..3e2b329a 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -40,7 +40,7 @@ class Main(m.Circuit): tester.advance_cycle() tester.circuit.O.expect(0) tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") @requires_ncsim @@ -67,7 +67,7 @@ class Main(m.Circuit): tester.advance_cycle() with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out @@ -106,7 +106,7 @@ class Main(m.Circuit): tester.circuit.read = 1 tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") tester = f.SynchronousTester(Main, Main.CLK) tester.circuit.write = 1 @@ -116,7 +116,7 @@ class Main(m.Circuit): tester.advance_cycle() with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out @@ -130,7 +130,7 @@ class Main(m.Circuit): tester.advance_cycle() with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out @@ -165,7 +165,7 @@ class Main(m.Circuit): # Should fail if we don't see seq2 with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out, out tester.circuit.write = 0 @@ -176,7 +176,7 @@ class Main(m.Circuit): tester.advance_cycle() tester.circuit.write = 0 tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") @requires_ncsim @@ -209,7 +209,7 @@ class Main(m.Circuit): # Should fail if we don't see seq2 with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out # do repeated sequence i times @@ -230,10 +230,10 @@ class Main(m.Circuit): with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", flags=["-sv"], - magma_opts={"inline": True}) + magma_output="mlir-verilog") else: tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") @requires_ncsim @@ -268,12 +268,12 @@ class Main(m.Circuit): tester.advance_cycle() tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") tester.circuit.read = 0 tester.advance_cycle() with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out @@ -300,14 +300,14 @@ class Main(m.Circuit): # Read does not eventually go high with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out tester.circuit.read = 1 tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") @requires_ncsim @@ -339,7 +339,7 @@ class Main(m.Circuit): tester.circuit.b = 0 tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") tester = f.SynchronousTester(Main, Main.CLK) tester.circuit.a = 0 @@ -354,7 +354,7 @@ class Main(m.Circuit): with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out @@ -386,7 +386,7 @@ class Main(m.Circuit): tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") tester = f.SynchronousTester(Main, Main.CLK) tester.circuit.a = 0 @@ -404,7 +404,7 @@ class Main(m.Circuit): with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out @@ -437,7 +437,7 @@ class Main(m.Circuit): tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") tester = f.SynchronousTester(Main, Main.CLK) tester.circuit.a = 0 @@ -455,7 +455,7 @@ class Main(m.Circuit): with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out @@ -477,7 +477,7 @@ class Main(m.Circuit): tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") tester = f.SynchronousTester(Main, Main.CLK) tester.circuit.a = 2 @@ -485,7 +485,7 @@ class Main(m.Circuit): with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out @@ -508,7 +508,7 @@ class Main(m.Circuit): tester.circuit.b = 1 tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") tester = f.SynchronousTester(Main, Main.CLK) tester.circuit.RESETN = 1 tester.circuit.a = 1 @@ -518,7 +518,7 @@ class Main(m.Circuit): tester.circuit.RESETN = 0 tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") tester = f.SynchronousTester(Main, Main.CLK) tester.circuit.RESETN = 1 @@ -529,7 +529,7 @@ class Main(m.Circuit): tester.advance_cycle() with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") @requires_ncsim @@ -557,7 +557,7 @@ class Main(m.Circuit): tester.advance_cycle() # Should not fail with no ASSERT_ON tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") # Check that wire prefix is generated properly with open("build/Main.v", "r") as file_: assert "wire _FAULT_ASSERT_WIRE_0" in file_.read() @@ -568,7 +568,7 @@ class Main(m.Circuit): tester.compile_and_run("system-verilog", simulator="ncsim", flags=["-sv"] + [f"+define+{guard}" for guard in compile_guard], - magma_opts={"inline": True}) + magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.foo has failed" in out assert "Assertion Main_tb.dut.bar has failed" in out @@ -610,7 +610,7 @@ class Main(m.Circuit): tester.circuit.O.expect(0) tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True, + flags=["-sv"], magma_opts={"output": "mlir-verilog", "drive_undriven": True, "terminate_unused": True}) @@ -627,7 +627,7 @@ class Main(m.Circuit): tester.circuit.I = 1 tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}, + flags=["-sv"], magma_output="mlir-verilog", disp_type="realtime", coverage=True) out, _ = capsys.readouterr() @@ -641,7 +641,7 @@ class Main(m.Circuit): tester.advance_cycle() tester.circuit.I = 0 tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}, + flags=["-sv"], magma_output="mlir-verilog", disp_type="realtime", coverage=True) out, _ = capsys.readouterr() @@ -668,7 +668,7 @@ class Main(m.Circuit): # formal tools) with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True}) + flags=["-sv"], magma_output="mlir-verilog") @requires_ncsim @@ -694,7 +694,7 @@ class Main(m.Circuit): tester.step(2) tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"inline": True, + flags=["-sv"], magma_opts={"output": "mlir-verilog", "drive_undriven": True, "terminate_unused": True}) @@ -706,7 +706,7 @@ class Main(m.Circuit): with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", flags=["-sv"], - magma_opts={"inline": True, + magma_opts={"output": "mlir-verilog", "drive_undriven": True, "terminate_unused": True}) @@ -763,7 +763,7 @@ class Foo(m.Circuit): try: tester.compile_and_run("system-verilog", simulator="ncsim", flags=["-sv"], - magma_opts={"inline": True, + magma_opts={"output": "mlir-verilog", "drive_undriven": True, "terminate_unused": True}) assert should_pass @@ -827,7 +827,7 @@ class Foo(m.Circuit): try: tester.compile_and_run("system-verilog", simulator="ncsim", flags=["-sv"], - magma_opts={"inline": True, + magma_opts={"output": "mlir-verilog", "drive_undriven": True, "terminate_unused": True}) except AssertionError: From b7b56655af6597f9b893a50bbd4113460dc25b24 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 16 Nov 2023 12:42:36 -0800 Subject: [PATCH 13/45] Remove wire logic --- tests/test_property.py | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/tests/test_property.py b/tests/test_property.py index 3e2b329a..9a5eaeb6 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -11,8 +11,8 @@ def requires_ncsim(test_fn): def wrapper(test_fn, *args, **kwargs): - if not shutil.which("ncsim"): - return pytest.skip("need ncsim for SVA test") + # if not shutil.which("ncsim"): + # return pytest.skip("need ncsim for SVA test") return test_fn(*args, **kwargs) return decorator.decorator(wrapper, test_fn) @@ -558,9 +558,6 @@ class Main(m.Circuit): # Should not fail with no ASSERT_ON tester.compile_and_run("system-verilog", simulator="ncsim", flags=["-sv"], magma_output="mlir-verilog") - # Check that wire prefix is generated properly - with open("build/Main.v", "r") as file_: - assert "wire _FAULT_ASSERT_WIRE_0" in file_.read() # Should fail with pytest.raises(AssertionError): if isinstance(compile_guard, str): From 21887be46e8f04f5b0e4bd8322b4ca5253fe5af7 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Thu, 16 Nov 2023 13:05:00 -0800 Subject: [PATCH 14/45] Fix redundant arg --- tests/test_property.py | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/tests/test_property.py b/tests/test_property.py index 9a5eaeb6..95611da6 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -607,9 +607,9 @@ class Main(m.Circuit): tester.circuit.O.expect(0) tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"output": "mlir-verilog", - "drive_undriven": True, - "terminate_unused": True}) + magma_output="mlir-verilog", flags=["-sv"], + magma_opts={"drive_undriven": True, + "terminate_unused": True}) @requires_ncsim @@ -691,9 +691,9 @@ class Main(m.Circuit): tester.step(2) tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_opts={"output": "mlir-verilog", - "drive_undriven": True, - "terminate_unused": True}) + magma_output="mlir-verilog", flags=["-sv"], + magma_opts={"drive_undriven": True, + "terminate_unused": True}) tester.circuit.I = 0xFF tester.step(2) @@ -702,9 +702,8 @@ class Main(m.Circuit): with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], - magma_opts={"output": "mlir-verilog", - "drive_undriven": True, + flags=["-sv"], magma_output="mlir-verilog", + magma_opts={"drive_undriven": True, "terminate_unused": True}) @@ -759,9 +758,8 @@ class Foo(m.Circuit): tester.step(2) try: tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], - magma_opts={"output": "mlir-verilog", - "drive_undriven": True, + flags=["-sv"], magma_output="mlir-verilog", + magma_opts={"drive_undriven": True, "terminate_unused": True}) assert should_pass except AssertionError: @@ -823,9 +821,8 @@ class Foo(m.Circuit): tester.step(2) try: tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], - magma_opts={"output": "mlir-verilog", - "drive_undriven": True, + flags=["-sv"], magma_output="mlir-verilog", + magma_opts={"drive_undriven": True, "terminate_unused": True}) except AssertionError: assert not should_pass From 15d8682297fbc17dbabbeff3d3ec1310c2c09042 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 17 Nov 2023 12:54:15 -0800 Subject: [PATCH 15/45] Fix bugs --- tests/test_property.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/tests/test_property.py b/tests/test_property.py index 95611da6..8a4b1e0b 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -609,7 +609,8 @@ class Main(m.Circuit): tester.compile_and_run("system-verilog", simulator="ncsim", magma_output="mlir-verilog", flags=["-sv"], magma_opts={"drive_undriven": True, - "terminate_unused": True}) + "terminate_unused": True, + "flatten_all_tuples": True}) @requires_ncsim @@ -776,9 +777,9 @@ class Foo(m.Circuit): io.ready @= 1 if use_sva: f.assert_( - f.sva(f.not_(~(io.valid & io.ready.value() & io.eop)), + # Note: need sequences to wrap parens + f.sva(f.not_(f.sequence(~(io.valid & io.ready.value() & io.eop))), "throughout", - # Note: need sequence here to wrap parens f.sequence(f.sva((io.valid & io.ready.value() & io.sop), "[-> 2]"))), name="eop_must_happen_btn_two_sop_A", From 84397c6a7ae00f9ee4fa3c36076e6715153e7a49 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 17 Nov 2023 12:57:57 -0800 Subject: [PATCH 16/45] Try sv true --- tests/test_property.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/test_property.py b/tests/test_property.py index 8a4b1e0b..6519233e 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -40,7 +40,8 @@ class Main(m.Circuit): tester.advance_cycle() tester.circuit.O.expect(0) tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") @requires_ncsim From 9b8fe63f93a0d8f542315bf59286ff62b811f6e2 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 17 Nov 2023 12:58:13 -0800 Subject: [PATCH 17/45] Revert ncsim change --- tests/test_property.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/test_property.py b/tests/test_property.py index 6519233e..f00932aa 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -11,8 +11,8 @@ def requires_ncsim(test_fn): def wrapper(test_fn, *args, **kwargs): - # if not shutil.which("ncsim"): - # return pytest.skip("need ncsim for SVA test") + if not shutil.which("ncsim"): + return pytest.skip("need ncsim for SVA test") return test_fn(*args, **kwargs) return decorator.decorator(wrapper, test_fn) From 66831dffdaf8a3feaa83e9de9131a17ec9852273 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 17 Nov 2023 13:37:21 -0800 Subject: [PATCH 18/45] Set sv flag for tests --- tests/test_property.py | 83 +++++++++++++++++++++++++++++------------- 1 file changed, 57 insertions(+), 26 deletions(-) diff --git a/tests/test_property.py b/tests/test_property.py index f00932aa..bdbcda15 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -68,7 +68,8 @@ class Main(m.Circuit): tester.advance_cycle() with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out @@ -107,7 +108,8 @@ class Main(m.Circuit): tester.circuit.read = 1 tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") tester = f.SynchronousTester(Main, Main.CLK) tester.circuit.write = 1 @@ -117,7 +119,8 @@ class Main(m.Circuit): tester.advance_cycle() with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out @@ -131,7 +134,8 @@ class Main(m.Circuit): tester.advance_cycle() with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out @@ -166,7 +170,8 @@ class Main(m.Circuit): # Should fail if we don't see seq2 with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out, out tester.circuit.write = 0 @@ -177,7 +182,8 @@ class Main(m.Circuit): tester.advance_cycle() tester.circuit.write = 0 tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") @requires_ncsim @@ -210,7 +216,8 @@ class Main(m.Circuit): # Should fail if we don't see seq2 with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out # do repeated sequence i times @@ -230,11 +237,12 @@ class Main(m.Circuit): # Should fail on first try (0 times) with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], + magma_opts={"sv": True}, flags=["-sv"], magma_output="mlir-verilog") else: tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") @requires_ncsim @@ -269,12 +277,14 @@ class Main(m.Circuit): tester.advance_cycle() tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") tester.circuit.read = 0 tester.advance_cycle() with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out @@ -301,14 +311,16 @@ class Main(m.Circuit): # Read does not eventually go high with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out tester.circuit.read = 1 tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") @requires_ncsim @@ -340,7 +352,8 @@ class Main(m.Circuit): tester.circuit.b = 0 tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") tester = f.SynchronousTester(Main, Main.CLK) tester.circuit.a = 0 @@ -355,7 +368,8 @@ class Main(m.Circuit): with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out @@ -387,7 +401,8 @@ class Main(m.Circuit): tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") tester = f.SynchronousTester(Main, Main.CLK) tester.circuit.a = 0 @@ -405,7 +420,8 @@ class Main(m.Circuit): with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out @@ -438,7 +454,8 @@ class Main(m.Circuit): tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") tester = f.SynchronousTester(Main, Main.CLK) tester.circuit.a = 0 @@ -456,7 +473,8 @@ class Main(m.Circuit): with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out @@ -478,7 +496,8 @@ class Main(m.Circuit): tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") tester = f.SynchronousTester(Main, Main.CLK) tester.circuit.a = 2 @@ -486,7 +505,8 @@ class Main(m.Circuit): with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out @@ -509,7 +529,8 @@ class Main(m.Circuit): tester.circuit.b = 1 tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") tester = f.SynchronousTester(Main, Main.CLK) tester.circuit.RESETN = 1 tester.circuit.a = 1 @@ -519,7 +540,8 @@ class Main(m.Circuit): tester.circuit.RESETN = 0 tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") tester = f.SynchronousTester(Main, Main.CLK) tester.circuit.RESETN = 1 @@ -530,7 +552,8 @@ class Main(m.Circuit): tester.advance_cycle() with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") @requires_ncsim @@ -558,7 +581,8 @@ class Main(m.Circuit): tester.advance_cycle() # Should not fail with no ASSERT_ON tester.compile_and_run("system-verilog", simulator="ncsim", - flags=["-sv"], magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") # Should fail with pytest.raises(AssertionError): if isinstance(compile_guard, str): @@ -566,6 +590,7 @@ class Main(m.Circuit): tester.compile_and_run("system-verilog", simulator="ncsim", flags=["-sv"] + [f"+define+{guard}" for guard in compile_guard], + magma_opts={"sv": True}, magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.foo has failed" in out @@ -610,6 +635,7 @@ class Main(m.Circuit): tester.compile_and_run("system-verilog", simulator="ncsim", magma_output="mlir-verilog", flags=["-sv"], magma_opts={"drive_undriven": True, + "sv": True, "terminate_unused": True, "flatten_all_tuples": True}) @@ -641,7 +667,8 @@ class Main(m.Circuit): tester.circuit.I = 0 tester.compile_and_run("system-verilog", simulator="ncsim", flags=["-sv"], magma_output="mlir-verilog", - disp_type="realtime", coverage=True) + magma_opts={"sv": True}, disp_type="realtime", + coverage=True) out, _ = capsys.readouterr() # covered @@ -695,6 +722,7 @@ class Main(m.Circuit): tester.compile_and_run("system-verilog", simulator="ncsim", magma_output="mlir-verilog", flags=["-sv"], magma_opts={"drive_undriven": True, + "sv": True, "terminate_unused": True}) tester.circuit.I = 0xFF @@ -706,6 +734,7 @@ class Main(m.Circuit): tester.compile_and_run("system-verilog", simulator="ncsim", flags=["-sv"], magma_output="mlir-verilog", magma_opts={"drive_undriven": True, + "sv": True, "terminate_unused": True}) @@ -762,6 +791,7 @@ class Foo(m.Circuit): tester.compile_and_run("system-verilog", simulator="ncsim", flags=["-sv"], magma_output="mlir-verilog", magma_opts={"drive_undriven": True, + "sv": True, "terminate_unused": True}) assert should_pass except AssertionError: @@ -825,6 +855,7 @@ class Foo(m.Circuit): tester.compile_and_run("system-verilog", simulator="ncsim", flags=["-sv"], magma_output="mlir-verilog", magma_opts={"drive_undriven": True, + "sv": True, "terminate_unused": True}) except AssertionError: assert not should_pass From c4731251c699930608821ba1959802b79a7ffd84 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 17 Nov 2023 13:54:32 -0800 Subject: [PATCH 19/45] Fix style --- tests/test_property.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/tests/test_property.py b/tests/test_property.py index bdbcda15..1231593a 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -134,8 +134,8 @@ class Main(m.Circuit): tester.advance_cycle() with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - magma_opts={"sv": True}, flags=["-sv"], - magma_output="mlir-verilog") + magma_opts={"sv": True}, flags=["-sv"], + magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out @@ -809,7 +809,8 @@ class Foo(m.Circuit): if use_sva: f.assert_( # Note: need sequences to wrap parens - f.sva(f.not_(f.sequence(~(io.valid & io.ready.value() & io.eop))), + f.sva(f.not_(f.sequence(~(io.valid & io.ready.value() & + io.eop))), "throughout", f.sequence(f.sva((io.valid & io.ready.value() & io.sop), "[-> 2]"))), From a047b70731469130f7aa438ebeae66e550306da9 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 17 Nov 2023 14:49:19 -0800 Subject: [PATCH 20/45] Disable initial blocks --- tests/test_property.py | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/tests/test_property.py b/tests/test_property.py index 1231593a..d3029a11 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -40,7 +40,9 @@ class Main(m.Circuit): tester.advance_cycle() tester.circuit.O.expect(0) tester.compile_and_run("system-verilog", simulator="ncsim", - magma_opts={"sv": True}, flags=["-sv"], + magma_opts={"sv": True, + "disable_initial_blocks": True}, + flags=["-sv"], magma_output="mlir-verilog") @@ -68,7 +70,9 @@ class Main(m.Circuit): tester.advance_cycle() with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", - magma_opts={"sv": True}, flags=["-sv"], + magma_opts={"sv": True, + "disable_initial_blocks": True}, + flags=["-sv"], magma_output="mlir-verilog") out, _ = capsys.readouterr() assert "Assertion Main_tb.dut.__assert_1 has failed" in out @@ -635,6 +639,7 @@ class Main(m.Circuit): tester.compile_and_run("system-verilog", simulator="ncsim", magma_output="mlir-verilog", flags=["-sv"], magma_opts={"drive_undriven": True, + "disable_initial_blocks": True, "sv": True, "terminate_unused": True, "flatten_all_tuples": True}) @@ -653,6 +658,8 @@ class Main(m.Circuit): tester.advance_cycle() tester.compile_and_run("system-verilog", simulator="ncsim", flags=["-sv"], magma_output="mlir-verilog", + magma_opts={"sv": True, + "disable_initial_blocks": True}, disp_type="realtime", coverage=True) out, _ = capsys.readouterr() @@ -667,8 +674,9 @@ class Main(m.Circuit): tester.circuit.I = 0 tester.compile_and_run("system-verilog", simulator="ncsim", flags=["-sv"], magma_output="mlir-verilog", - magma_opts={"sv": True}, disp_type="realtime", - coverage=True) + magma_opts={"sv": True, + "disable_initial_blocks": True}, + disp_type="realtime", coverage=True) out, _ = capsys.readouterr() # covered @@ -791,6 +799,7 @@ class Foo(m.Circuit): tester.compile_and_run("system-verilog", simulator="ncsim", flags=["-sv"], magma_output="mlir-verilog", magma_opts={"drive_undriven": True, + "disable_initial_blocks": True, "sv": True, "terminate_unused": True}) assert should_pass @@ -857,6 +866,7 @@ class Foo(m.Circuit): flags=["-sv"], magma_output="mlir-verilog", magma_opts={"drive_undriven": True, "sv": True, + "disable_initial_blocks": True, "terminate_unused": True}) except AssertionError: assert not should_pass From 4ba4343fe0efe5f647e893e305535b7c90985d06 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 17 Nov 2023 14:49:48 -0800 Subject: [PATCH 21/45] Add parens --- tests/test_property.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/test_property.py b/tests/test_property.py index d3029a11..7de3b8ce 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -836,7 +836,7 @@ class Foo(m.Circuit): ) else: f.assert_( - f.not_(~(io.valid & io.ready.value() & io.eop)) + f.not_(f.sequence(~(io.valid & io.ready.value() & io.eop))) | f.throughout | ((io.valid & io.ready.value() & io.sop) | f.goto[2]), name="eop_must_happen_btn_two_sop_A", From 076603f47fdbafa954ad1f542cab90433d2cce65 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 17 Nov 2023 15:50:28 -0800 Subject: [PATCH 22/45] Fix paren logic --- tests/test_property.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/test_property.py b/tests/test_property.py index 7de3b8ce..824c4279 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -817,10 +817,9 @@ class Foo(m.Circuit): io.ready @= 1 if use_sva: f.assert_( - # Note: need sequences to wrap parens - f.sva(f.not_(f.sequence(~(io.valid & io.ready.value() & - io.eop))), + f.sva(f.sequence(f.not_(~(io.valid & io.ready.value() & io.eop))), "throughout", + # Note: need sequences to wrap parens f.sequence(f.sva((io.valid & io.ready.value() & io.sop), "[-> 2]"))), name="eop_must_happen_btn_two_sop_A", @@ -836,8 +835,9 @@ class Foo(m.Circuit): ) else: f.assert_( - f.not_(f.sequence(~(io.valid & io.ready.value() & io.eop))) - | f.throughout | + f.sequence( + f.not_(~(io.valid & io.ready.value() & io.eop)) + ) | f.throughout | ((io.valid & io.ready.value() & io.sop) | f.goto[2]), name="eop_must_happen_btn_two_sop_A", on=f.posedge(io.CLK), From d730f714d101d1edb3011404fbd83a211dd3d1da Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 17 Nov 2023 15:54:32 -0800 Subject: [PATCH 23/45] Set magma opts for assume test --- tests/test_property.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/test_property.py b/tests/test_property.py index 824c4279..9015a88f 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -11,8 +11,8 @@ def requires_ncsim(test_fn): def wrapper(test_fn, *args, **kwargs): - if not shutil.which("ncsim"): - return pytest.skip("need ncsim for SVA test") + # if not shutil.which("ncsim"): + # return pytest.skip("need ncsim for SVA test") return test_fn(*args, **kwargs) return decorator.decorator(wrapper, test_fn) @@ -702,6 +702,8 @@ class Main(m.Circuit): # formal tools) with pytest.raises(AssertionError): tester.compile_and_run("system-verilog", simulator="ncsim", + magma_opts={"sv": True, + "disable_initial_blocks": True}, flags=["-sv"], magma_output="mlir-verilog") From 1cc700fcbbaa65718769c24e0c0652af3339a335 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 17 Nov 2023 16:10:57 -0800 Subject: [PATCH 24/45] Fix style --- tests/test_property.py | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/tests/test_property.py b/tests/test_property.py index 9015a88f..c24b3465 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -299,8 +299,10 @@ def test_eventually(sva, capsys): class Main(m.Circuit): io = m.IO(write=m.In(m.Bit), read=m.In(m.Bit)) + m.ClockIO() if sva: - f.assert_(f.sva(io.write == 1, f"|-> s_eventually", io.read == 1), - on=f.posedge(io.CLK)) + f.assert_( + f.sva(io.write == 1, "|-> s_eventually", io.read == 1), + on=f.posedge(io.CLK) + ) else: f.assert_((io.write == 1) | f.implies | f.eventually | (io.read == 1), on=f.posedge(io.CLK)) @@ -819,11 +821,14 @@ class Foo(m.Circuit): io.ready @= 1 if use_sva: f.assert_( - f.sva(f.sequence(f.not_(~(io.valid & io.ready.value() & io.eop))), - "throughout", - # Note: need sequences to wrap parens - f.sequence(f.sva((io.valid & io.ready.value() & io.sop), - "[-> 2]"))), + f.sva( + f.sequence( + f.not_(~(io.valid & io.ready.value() & io.eop)) + ), + "throughout", + # Note: need sequences to wrap parens + f.sequence(f.sva((io.valid & io.ready.value() & io.sop), + "[-> 2]"))), name="eop_must_happen_btn_two_sop_A", on=f.posedge(io.CLK), disable_iff=f.not_(io.RESETN) From b3eca7ea4012aeb8f28b7cd7efaf28d3b4b0186d Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 17 Nov 2023 19:36:25 -0800 Subject: [PATCH 25/45] Fix sequence logic --- tests/test_property.py | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/tests/test_property.py b/tests/test_property.py index c24b3465..664bc4cf 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -822,9 +822,9 @@ class Foo(m.Circuit): if use_sva: f.assert_( f.sva( - f.sequence( + f.sequence(f.sva( f.not_(~(io.valid & io.ready.value() & io.eop)) - ), + )), "throughout", # Note: need sequences to wrap parens f.sequence(f.sva((io.valid & io.ready.value() & io.sop), @@ -842,9 +842,8 @@ class Foo(m.Circuit): ) else: f.assert_( - f.sequence( - f.not_(~(io.valid & io.ready.value() & io.eop)) - ) | f.throughout | + f.not_(~(io.valid & io.ready.value() & io.eop)) + | f.throughout | ((io.valid & io.ready.value() & io.sop) | f.goto[2]), name="eop_must_happen_btn_two_sop_A", on=f.posedge(io.CLK), From b02a39e0fa1e630a4d715c34e50380cf9718bd1b Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 17 Nov 2023 20:05:47 -0800 Subject: [PATCH 26/45] Change parens --- tests/test_property.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tests/test_property.py b/tests/test_property.py index 664bc4cf..c3f2aa01 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -822,9 +822,11 @@ class Foo(m.Circuit): if use_sva: f.assert_( f.sva( - f.sequence(f.sva( - f.not_(~(io.valid & io.ready.value() & io.eop)) - )), + f.not_( + f.sva( + f.sequence(~(io.valid & io.ready.value() & io.eop)) + ) + ), "throughout", # Note: need sequences to wrap parens f.sequence(f.sva((io.valid & io.ready.value() & io.sop), From 233022bb490c65c0ad8faf38c09482dada9ea03d Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 17 Nov 2023 20:24:58 -0800 Subject: [PATCH 27/45] Fix ncsim logic --- tests/test_property.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/test_property.py b/tests/test_property.py index c3f2aa01..9d2e6db0 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -11,8 +11,8 @@ def requires_ncsim(test_fn): def wrapper(test_fn, *args, **kwargs): - # if not shutil.which("ncsim"): - # return pytest.skip("need ncsim for SVA test") + if not shutil.which("ncsim"): + return pytest.skip("need ncsim for SVA test") return test_fn(*args, **kwargs) return decorator.decorator(wrapper, test_fn) From c4b9d465847074f8d8ad72a469d45765532a1d41 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 17 Nov 2023 20:28:26 -0800 Subject: [PATCH 28/45] Try adding parens --- fault/property.py | 2 +- tests/test_property.py | 11 +++-------- 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/fault/property.py b/fault/property.py index a1efe87e..b1cc18ff 100644 --- a/fault/property.py +++ b/fault/property.py @@ -155,7 +155,7 @@ def _codegen_slice(self, value): def _compile(self, value): if isinstance(value, PropertyUnaryOp): - return f"{value.op_str} {self._compile(value.arg)}" + return f"{value.op_str} ({self._compile(value.arg)})" # TODO: Refactor getitem properties to share code if isinstance(value, Delay): result = "" diff --git a/tests/test_property.py b/tests/test_property.py index 9d2e6db0..95b3e2ae 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -1,18 +1,15 @@ -import shutil import random -import os import pytest import decorator import fault as f import magma as m -from hwtypes import BitVector def requires_ncsim(test_fn): def wrapper(test_fn, *args, **kwargs): - if not shutil.which("ncsim"): - return pytest.skip("need ncsim for SVA test") + # if not shutil.which("ncsim"): + # return pytest.skip("need ncsim for SVA test") return test_fn(*args, **kwargs) return decorator.decorator(wrapper, test_fn) @@ -823,9 +820,7 @@ class Foo(m.Circuit): f.assert_( f.sva( f.not_( - f.sva( - f.sequence(~(io.valid & io.ready.value() & io.eop)) - ) + ~(io.valid & io.ready.value() & io.eop) ), "throughout", # Note: need sequences to wrap parens From f1f3e89846242976b74f5cbd10217de20dc9fd2a Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 17 Nov 2023 20:28:42 -0800 Subject: [PATCH 29/45] Revert ncsim change --- tests/test_property.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/test_property.py b/tests/test_property.py index 95b3e2ae..c2299001 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -8,8 +8,8 @@ def requires_ncsim(test_fn): def wrapper(test_fn, *args, **kwargs): - # if not shutil.which("ncsim"): - # return pytest.skip("need ncsim for SVA test") + if not shutil.which("ncsim"): + return pytest.skip("need ncsim for SVA test") return test_fn(*args, **kwargs) return decorator.decorator(wrapper, test_fn) From d06d2bc78ae2f721d547c1126559c03783d92284 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 20 Nov 2023 11:42:41 -0800 Subject: [PATCH 30/45] Fix import --- tests/test_property.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/test_property.py b/tests/test_property.py index c2299001..e160fe37 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -1,3 +1,4 @@ +import shutil import random import pytest From d5d2f261c9e12ab7ad1d0d279d0e23f164fddf6b Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 20 Nov 2023 12:00:40 -0800 Subject: [PATCH 31/45] Parent sva args --- fault/property.py | 2 +- tests/test_property.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/fault/property.py b/fault/property.py index b1cc18ff..01c95723 100644 --- a/fault/property.py +++ b/fault/property.py @@ -200,7 +200,7 @@ def _compile(self, value): property_str = "" for arg in value.args: if isinstance(arg, str): - property_str += f" {arg} " + property_str += f" ({arg}) " elif isinstance(arg, (SVAProperty, Sequence, FunctionCall, PropertyUnaryOp, Expression)): property_str += f" {self._compile(arg)} " diff --git a/tests/test_property.py b/tests/test_property.py index e160fe37..63312ac0 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -9,8 +9,8 @@ def requires_ncsim(test_fn): def wrapper(test_fn, *args, **kwargs): - if not shutil.which("ncsim"): - return pytest.skip("need ncsim for SVA test") + # if not shutil.which("ncsim"): + # return pytest.skip("need ncsim for SVA test") return test_fn(*args, **kwargs) return decorator.decorator(wrapper, test_fn) From 59551fe61cee2ce65a90e677558c1c906f2e39b8 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 20 Nov 2023 12:01:59 -0800 Subject: [PATCH 32/45] Fix paren logic --- fault/property.py | 2 +- tests/test_property.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/fault/property.py b/fault/property.py index 01c95723..b1cc18ff 100644 --- a/fault/property.py +++ b/fault/property.py @@ -200,7 +200,7 @@ def _compile(self, value): property_str = "" for arg in value.args: if isinstance(arg, str): - property_str += f" ({arg}) " + property_str += f" {arg} " elif isinstance(arg, (SVAProperty, Sequence, FunctionCall, PropertyUnaryOp, Expression)): property_str += f" {self._compile(arg)} " diff --git a/tests/test_property.py b/tests/test_property.py index 63312ac0..7173d1ad 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -333,7 +333,7 @@ def test_throughout(sva, capsys): class Main(m.Circuit): io = m.IO(a=m.In(m.Bit), b=m.In(m.Bit), c=m.In(m.Bit)) + m.ClockIO() if sva: - seq = f.sva(io.b, "throughout", "!", io.c, "[-> 1]") + seq = f.sva(io.b, "throughout", "! (", io.c, "[-> 1])") f.assert_(f.sva(f.rose(io.a), "|->", seq), on=f.posedge(io.CLK)) else: From a4f944b40d8fe28b5de44c15b9017b2ae3654a2c Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 20 Nov 2023 12:17:22 -0800 Subject: [PATCH 33/45] Try other precedence --- tests/test_property.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/test_property.py b/tests/test_property.py index 7173d1ad..3e65fcb5 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -9,8 +9,8 @@ def requires_ncsim(test_fn): def wrapper(test_fn, *args, **kwargs): - # if not shutil.which("ncsim"): - # return pytest.skip("need ncsim for SVA test") + if not shutil.which("ncsim"): + return pytest.skip("need ncsim for SVA test") return test_fn(*args, **kwargs) return decorator.decorator(wrapper, test_fn) @@ -333,11 +333,11 @@ def test_throughout(sva, capsys): class Main(m.Circuit): io = m.IO(a=m.In(m.Bit), b=m.In(m.Bit), c=m.In(m.Bit)) + m.ClockIO() if sva: - seq = f.sva(io.b, "throughout", "! (", io.c, "[-> 1])") + seq = f.sva(io.b, "throughout", "!", io.c, "[-> 1]") f.assert_(f.sva(f.rose(io.a), "|->", seq), on=f.posedge(io.CLK)) else: - seq = io.b | f.throughout | f.not_(io.c | f.goto[1]) + seq = io.b | f.throughout | f.not_(io.c) | f.goto[1] f.assert_(f.rose(io.a) | f.implies | seq, on=f.posedge(io.CLK)) From 964e07fdca2b16fff50aacae1828cd1dfebc096d Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 20 Nov 2023 12:34:39 -0800 Subject: [PATCH 34/45] Fix unary logic --- fault/property.py | 4 ++-- tests/test_property.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/fault/property.py b/fault/property.py index b1cc18ff..d2f4264c 100644 --- a/fault/property.py +++ b/fault/property.py @@ -155,7 +155,7 @@ def _codegen_slice(self, value): def _compile(self, value): if isinstance(value, PropertyUnaryOp): - return f"{value.op_str} ({self._compile(value.arg)})" + return f"({value.op_str} ({self._compile(value.arg)}))" # TODO: Refactor getitem properties to share code if isinstance(value, Delay): result = "" @@ -318,7 +318,7 @@ def __call__(self, *args): stable = Function("$stable") -class PropertyUnaryOp(Expression): +class PropertyUnaryOp: pass diff --git a/tests/test_property.py b/tests/test_property.py index 3e65fcb5..e2c30c95 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -337,7 +337,7 @@ class Main(m.Circuit): f.assert_(f.sva(f.rose(io.a), "|->", seq), on=f.posedge(io.CLK)) else: - seq = io.b | f.throughout | f.not_(io.c) | f.goto[1] + seq = io.b | f.throughout | (f.not_(io.c) | f.goto[1]) f.assert_(f.rose(io.a) | f.implies | seq, on=f.posedge(io.CLK)) From 6e3fbeb62ec6ca70718f0d527b0c12161caf7ac9 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 20 Nov 2023 12:48:31 -0800 Subject: [PATCH 35/45] Fix __or__ logic --- fault/property.py | 7 ++++++- tests/test_property.py | 4 ++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/fault/property.py b/fault/property.py index d2f4264c..94a5a162 100644 --- a/fault/property.py +++ b/fault/property.py @@ -318,7 +318,7 @@ def __call__(self, *args): stable = Function("$stable") -class PropertyUnaryOp: +class PropertyUnaryOp(Expression): pass @@ -328,6 +328,11 @@ class Not(PropertyUnaryOp): def __init__(self, arg): self.arg = arg + def __or__(self, other): + if isinstance(other, Property): + return other.__ror__(self) + return super().__or__(self) + def not_(arg): return Not(arg) diff --git a/tests/test_property.py b/tests/test_property.py index e2c30c95..ad8b6f86 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -9,8 +9,8 @@ def requires_ncsim(test_fn): def wrapper(test_fn, *args, **kwargs): - if not shutil.which("ncsim"): - return pytest.skip("need ncsim for SVA test") + # if not shutil.which("ncsim"): + # return pytest.skip("need ncsim for SVA test") return test_fn(*args, **kwargs) return decorator.decorator(wrapper, test_fn) From 1d7f4d4559eada9b966f899ab2f92efaefc3e88a Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 20 Nov 2023 12:49:14 -0800 Subject: [PATCH 36/45] remove comment --- tests/test_property.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/test_property.py b/tests/test_property.py index ad8b6f86..e2c30c95 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -9,8 +9,8 @@ def requires_ncsim(test_fn): def wrapper(test_fn, *args, **kwargs): - # if not shutil.which("ncsim"): - # return pytest.skip("need ncsim for SVA test") + if not shutil.which("ncsim"): + return pytest.skip("need ncsim for SVA test") return test_fn(*args, **kwargs) return decorator.decorator(wrapper, test_fn) From 785500cb3945567e47252a58c2c26652a57097a4 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 20 Nov 2023 12:59:41 -0800 Subject: [PATCH 37/45] Fix default case bug --- fault/property.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fault/property.py b/fault/property.py index 94a5a162..fe1dd96c 100644 --- a/fault/property.py +++ b/fault/property.py @@ -331,7 +331,7 @@ def __init__(self, arg): def __or__(self, other): if isinstance(other, Property): return other.__ror__(self) - return super().__or__(self) + return super().__or__(other) def not_(arg): From 122086313eb942977437816367b9e17b66a47c27 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 20 Nov 2023 18:10:01 -0800 Subject: [PATCH 38/45] Add tempfile logic --- tests/test_magma_opts.py | 6 +++++- tests/test_no_coreir.py | 8 +++++--- tests/test_protocol.py | 5 ++++- tests/test_pysv.py | 2 +- tests/test_ready_valid.py | 22 ++++++++++++++-------- tests/test_tester/test_call.py | 1 - tests/test_tester/test_sequence_tester.py | 5 ++++- tests/test_tester/test_synchronous.py | 5 ++++- 8 files changed, 37 insertions(+), 17 deletions(-) diff --git a/tests/test_magma_opts.py b/tests/test_magma_opts.py index 1d37d92f..c94601f5 100644 --- a/tests/test_magma_opts.py +++ b/tests/test_magma_opts.py @@ -1,3 +1,4 @@ +import tempfile import magma as m import fault as f @@ -12,4 +13,7 @@ class Foo(m.Circuit): tester.eval() tester.circuit.O.expect(4) - tester.compile_and_run("verilator", magma_opts={"verilog_prefix": "bar_"}) + with tempfile.TemporaryDirectory(dir=".") as tempdir: + tester.compile_and_run("verilator", + magma_opts={"verilog_prefix": "bar_"}, + directory=tempdir) diff --git a/tests/test_no_coreir.py b/tests/test_no_coreir.py index cb92b621..dc230865 100644 --- a/tests/test_no_coreir.py +++ b/tests/test_no_coreir.py @@ -1,9 +1,9 @@ +import tempfile + import hwtypes as ht import fault as f import magma as m -import pytest - def test_fault_no_coreir(): class Foo(m.Circuit): @@ -15,4 +15,6 @@ class Foo(m.Circuit): tester.eval() tester.circuit.O.expect(I & 0xFF) - tester.compile_and_run("verilator", magma_output="mlir-verilog") + with tempfile.TemporaryDirectory(dir=".") as tempdir: + tester.compile_and_run("verilator", magma_output="mlir-verilog", + directory=tempdir) diff --git a/tests/test_protocol.py b/tests/test_protocol.py index 84594de5..2247258f 100644 --- a/tests/test_protocol.py +++ b/tests/test_protocol.py @@ -1,3 +1,4 @@ +import tempfile import magma as m import fault @@ -48,4 +49,6 @@ def test_proto(): tester.circuit.val = 1 tester.eval() tester.circuit.O.expect(2) - tester.compile_and_run("verilator", flags=['-Wno-unused']) + with tempfile.TemporaryDirectory(dir=".") as tempdir: + tester.compile_and_run("verilator", flags=['-Wno-unused'], + directory=tempdir) diff --git a/tests/test_pysv.py b/tests/test_pysv.py index 534f16de..7c6bce2d 100644 --- a/tests/test_pysv.py +++ b/tests/test_pysv.py @@ -24,7 +24,7 @@ def run_tester(tester, target, simulator): # "disp_type": "realtime", "simulator": simulator, "magma_opts": {"sv": True}, - "tmp_dir": False + "tmp_dir": True } if target == "verilator": diff --git a/tests/test_ready_valid.py b/tests/test_ready_valid.py index 898f75ee..4beec0b9 100644 --- a/tests/test_ready_valid.py +++ b/tests/test_ready_valid.py @@ -1,3 +1,4 @@ +import tempfile from hwtypes import BitVector import magma as m import fault as f @@ -22,7 +23,8 @@ def test_basic_ready_valid_sequence(): pytest.skip("Untested with earlier verilator versions") I = [BitVector.random(8) for _ in range(8)] + [0] O = [0] + [i + 1 for i in I[:-1]] - f.run_ready_valid_test(Main, {"I": I, "O": O}, "verilator") + f.run_ready_valid_test(Main, {"I": I, "O": O}, "verilator", + compile_and_run_kwargs={"tmp_dir": True}) def test_basic_ready_valid_sequence_fail(): @@ -30,8 +32,8 @@ def test_basic_ready_valid_sequence_fail(): pytest.skip("Untested with earlier verilator versions") I = [BitVector.random(8) for _ in range(8)] + [0] O = [0] + [i - 1 for i in I[:-1]] - with pytest.raises(AssertionError): - f.run_ready_valid_test(Main, {"I": I, "O": O}, "verilator") + f.run_ready_valid_test(Main, {"I": I, "O": O}, "verilator", + compile_and_run_kwargs={"tmp_dir": True}) class Main2(m.Circuit): @@ -56,8 +58,9 @@ def test_lifted_ready_valid_sequence_simple(): tester = f.ReadyValidTester(Main2, {"I": I, "O": O}) tester.circuit.inc = 2 tester.finish_sequences() - tester.compile_and_run("verilator", disp_type="realtime", - flags=['-Wno-UNUSED']) + with tempfile.TemporaryDirectory(dir=".") as _dir: + tester.compile_and_run("verilator", disp_type="realtime", + flags=['-Wno-UNUSED'], directory=_dir) def test_lifted_ready_valid_sequence_simple_fail(): @@ -74,7 +77,9 @@ def test_lifted_ready_valid_sequence_simple_fail(): tester.circuit.inc = 3 tester.finish_sequences() with pytest.raises(AssertionError): - tester.compile_and_run("verilator", disp_type="realtime") + with tempfile.TemporaryDirectory(dir=".") as _dir: + tester.compile_and_run("verilator", disp_type="realtime", + directory=_dir) def test_lifted_ready_valid_sequence_changing_inc(): @@ -91,5 +96,6 @@ def test_lifted_ready_valid_sequence_changing_inc(): # Advance one cycle to finish last handshake tester.advance_cycle() tester.expect_sequences_finished() - tester.compile_and_run("verilator", disp_type="realtime", - flags=['-Wno-UNUSED']) + with tempfile.TemporaryDirectory(dir=".") as _dir: + tester.compile_and_run("verilator", disp_type="realtime", + flags=['-Wno-UNUSED'], directory=_dir) diff --git a/tests/test_tester/test_call.py b/tests/test_tester/test_call.py index af855c37..956ed5e0 100644 --- a/tests/test_tester/test_call.py +++ b/tests/test_tester/test_call.py @@ -59,7 +59,6 @@ def test_call_interface_clock(target, simulator, caplog): tester.step(2) tester(3, 2).expect(ops[i](BitVector[16](3), BitVector[16](2))) with tempfile.TemporaryDirectory(dir=".") as _dir: - _dir = "build" if target == "verilator": tester.compile_and_run(target, directory=_dir, flags=["-Wno-unused"]) diff --git a/tests/test_tester/test_sequence_tester.py b/tests/test_tester/test_sequence_tester.py index 6caad30e..9c6ca03f 100644 --- a/tests/test_tester/test_sequence_tester.py +++ b/tests/test_tester/test_sequence_tester.py @@ -1,3 +1,4 @@ +import tempfile import pytest import magma as m @@ -76,4 +77,6 @@ def test_simple_alu_sequence(circuit, driver, monitor, clock): tester = SequenceTester(circuit, driver, monitor, sequence, clock=clock) - tester.compile_and_run("verilator", flags=['-Wno-UNUSED']) + with tempfile.TemporaryDirectory(dir=".") as tempdir: + tester.compile_and_run("verilator", flags=['-Wno-UNUSED'], + directory=tempdir) diff --git a/tests/test_tester/test_synchronous.py b/tests/test_tester/test_synchronous.py index 5eb613eb..52cb1d3d 100644 --- a/tests/test_tester/test_synchronous.py +++ b/tests/test_tester/test_synchronous.py @@ -1,4 +1,6 @@ +import tempfile import pytest + from fault import SynchronousTester import magma as m from hwtypes import BitVector @@ -30,7 +32,8 @@ def test_synchronous_basic(target, simulator): tester.advance_cycle() if target == "verilator": - tester.compile_and_run("verilator") + with tempfile.TemporaryDirectory(dir=".") as tempdir: + tester.compile_and_run("verilator", directory=tempdir) else: tester.compile_and_run(target, simulator=simulator, magma_opts={"sv": True}) From e20f44649788827dac7f5bf1439da260ee134477 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 20 Nov 2023 18:24:33 -0800 Subject: [PATCH 39/45] Add flag --- tests/test_ready_valid.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/test_ready_valid.py b/tests/test_ready_valid.py index 4beec0b9..9be3ec35 100644 --- a/tests/test_ready_valid.py +++ b/tests/test_ready_valid.py @@ -24,7 +24,8 @@ def test_basic_ready_valid_sequence(): I = [BitVector.random(8) for _ in range(8)] + [0] O = [0] + [i + 1 for i in I[:-1]] f.run_ready_valid_test(Main, {"I": I, "O": O}, "verilator", - compile_and_run_kwargs={"tmp_dir": True}) + compile_and_run_kwargs={"tmp_dir": True, + "flags": ['-Wno-UNUSED']}) def test_basic_ready_valid_sequence_fail(): @@ -33,7 +34,8 @@ def test_basic_ready_valid_sequence_fail(): I = [BitVector.random(8) for _ in range(8)] + [0] O = [0] + [i - 1 for i in I[:-1]] f.run_ready_valid_test(Main, {"I": I, "O": O}, "verilator", - compile_and_run_kwargs={"tmp_dir": True}) + compile_and_run_kwargs={"tmp_dir": True, + "flags": ['-Wno-UNUSED']}) class Main2(m.Circuit): From 3d6bf7fbc0cdfa68d17f4a8f92514232d2a41d4b Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 20 Nov 2023 19:01:18 -0800 Subject: [PATCH 40/45] Add tempdir --- tests/test_magma_protocol.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/test_magma_protocol.py b/tests/test_magma_protocol.py index 9dde24d5..3cad90c5 100644 --- a/tests/test_magma_protocol.py +++ b/tests/test_magma_protocol.py @@ -1,3 +1,4 @@ +import tempfile from typing import Optional import magma as m import fault @@ -45,4 +46,6 @@ class Bar(m.Circuit): tester.circuit.O.expect(BitVector[8](0xDE << 2) | (BitVector[8](0xDE) << 1)[0] | BitVector[8](0xDE)[0]) - tester.compile_and_run("verilator") + + with tempfile.TemporaryDirectory(dir=".") as _dir: + tester.compile_and_run("verilator", directory=_dir) From dcbbf1fec1e60742a14ddf7612003c9cca945aed Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 20 Nov 2023 19:04:20 -0800 Subject: [PATCH 41/45] Fix test --- tests/test_ready_valid.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/tests/test_ready_valid.py b/tests/test_ready_valid.py index 9be3ec35..afabb4cd 100644 --- a/tests/test_ready_valid.py +++ b/tests/test_ready_valid.py @@ -33,9 +33,13 @@ def test_basic_ready_valid_sequence_fail(): pytest.skip("Untested with earlier verilator versions") I = [BitVector.random(8) for _ in range(8)] + [0] O = [0] + [i - 1 for i in I[:-1]] - f.run_ready_valid_test(Main, {"I": I, "O": O}, "verilator", - compile_and_run_kwargs={"tmp_dir": True, - "flags": ['-Wno-UNUSED']}) + with pytest.raises(AssertionError): + f.run_ready_valid_test( + Main, {"I": I, "O": O}, + "verilator", + compile_and_run_kwargs={"tmp_dir": True, + "flags": ['-Wno-UNUSED']} + ) class Main2(m.Circuit): From c9776ab4ec22b9fc3976659026aa95a7758cbaba Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 21 Nov 2023 10:03:24 -0800 Subject: [PATCH 42/45] Update assert to use inline_verilog2 (#333) * Update assert to use inline_verilog2 * Fix style * Update expectation * Fix ready_valid tests * Fix style * Add verilator version logic --------- Co-authored-by: Lenny Truong --- fault/assert_immediate.py | 22 ++++------- fault/property.py | 24 ++++-------- tests/test_assert_immediate.py | 71 ++++++++++++++++++++-------------- tests/test_ready_valid.py | 43 ++++++++++++-------- 4 files changed, 84 insertions(+), 76 deletions(-) diff --git a/fault/assert_immediate.py b/fault/assert_immediate.py index ce86ba1b..607fba07 100644 --- a/fault/assert_immediate.py +++ b/fault/assert_immediate.py @@ -5,10 +5,7 @@ def _make_assert(type_, cond, success_msg=None, failure_msg=None, - severity="error", name=None, compile_guard=None, delay=False, - inline_wire_prefix=None): - if inline_wire_prefix is None: - inline_wire_prefix = "_FAULT_ASSERT_WIRE_" + severity="error", name=None, compile_guard=None, delay=False): success_msg_str = "" if success_msg is not None: success_msg_str = f" $display(\"{success_msg}\");" @@ -38,9 +35,7 @@ def _make_assert(type_, cond, success_msg=None, failure_msg=None, end """ assert_str = add_compile_guards(compile_guard, assert_str) - m.inline_verilog( - assert_str, inline_wire_prefix=inline_wire_prefix, - **format_args, type_=type_) + m.inline_verilog2(assert_str, **format_args, type_=type_) def _add_docstr(fn): @@ -66,7 +61,7 @@ def _add_docstr(fn): @_add_docstr def assert_immediate(cond, success_msg=None, failure_msg=None, severity="error", - name=None, compile_guard=None, inline_wire_prefix=None): + name=None, compile_guard=None): if get_curr_when_block(): # guard condition by current active when using a boolean with default 0 # and assigned inside when @@ -77,19 +72,18 @@ def assert_immediate(cond, success_msg=None, failure_msg=None, severity="error", cond = ~when_cond | cond _make_assert("always @(*)", cond, success_msg, failure_msg, severity, name, - compile_guard, inline_wire_prefix=inline_wire_prefix) + compile_guard) @_add_docstr def assert_final(cond, success_msg=None, failure_msg=None, severity="error", - name=None, compile_guard=None, inline_wire_prefix=None): + name=None, compile_guard=None): _make_assert("final", cond, success_msg, failure_msg, severity, name, - compile_guard, inline_wire_prefix=inline_wire_prefix) + compile_guard) @_add_docstr def assert_initial(cond, success_msg=None, failure_msg=None, severity="error", - name=None, compile_guard=None, inline_wire_prefix=None): + name=None, compile_guard=None): _make_assert("initial", cond, success_msg, failure_msg, severity, name, - compile_guard, delay=True, - inline_wire_prefix=inline_wire_prefix) + compile_guard, delay=True) diff --git a/fault/property.py b/fault/property.py index fe1dd96c..f0ea481f 100644 --- a/fault/property.py +++ b/fault/property.py @@ -245,8 +245,7 @@ def compile(self, prop): return compiled -def _make_statement(statement, prop, on, disable_iff, compile_guard, name, - inline_wire_prefix): +def _make_statement(statement, prop, on, disable_iff, compile_guard, name): format_args = {} _compiler = _Compiler(format_args) prop = _compiler.compile(prop) @@ -260,26 +259,19 @@ def _make_statement(statement, prop, on, disable_iff, compile_guard, name, raise TypeError("Expected string for name") prop_str = f"{name}: {prop_str}" prop_str = add_compile_guards(compile_guard, prop_str) - m.inline_verilog(prop_str, inline_wire_prefix=inline_wire_prefix, - **format_args) + m.inline_verilog2(prop_str, **format_args) -def assert_(prop, on, disable_iff=None, compile_guard=None, name=None, - inline_wire_prefix="_FAULT_ASSERT_WIRE_"): - _make_statement("assert", prop, on, disable_iff, compile_guard, name, - inline_wire_prefix) +def assert_(prop, on, disable_iff=None, compile_guard=None, name=None): + _make_statement("assert", prop, on, disable_iff, compile_guard, name) -def cover(prop, on, disable_iff=None, compile_guard=None, name=None, - inline_wire_prefix="_FAULT_COVER_WIRE_"): - _make_statement("cover", prop, on, disable_iff, compile_guard, name, - inline_wire_prefix) +def cover(prop, on, disable_iff=None, compile_guard=None, name=None): + _make_statement("cover", prop, on, disable_iff, compile_guard, name) -def assume(prop, on, disable_iff=None, compile_guard=None, name=None, - inline_wire_prefix="_FAULT_ASSUME_WIRE_"): - _make_statement("assume", prop, on, disable_iff, compile_guard, name, - inline_wire_prefix) +def assume(prop, on, disable_iff=None, compile_guard=None, name=None): + _make_statement("assume", prop, on, disable_iff, compile_guard, name) class Sequence: diff --git a/tests/test_assert_immediate.py b/tests/test_assert_immediate.py index 2d7666f9..d8569684 100644 --- a/tests/test_assert_immediate.py +++ b/tests/test_assert_immediate.py @@ -16,60 +16,67 @@ def test_immediate_assert(capsys, failure_msg, success_msg, severity, name): if verilator_version() < 4.0: pytest.skip("Untested with earlier verilator versions") - if verilator_version() > 5.0: - pytest.skip("Untested with later verilator versions") if failure_msg is not None and severity == "fatal": - # Use integer exit code - failure_msg = 1 + # Verilator won't report failure msg for fatal + failure_msg = None class Foo(m.Circuit): io = m.IO( I0=m.In(m.Bit), - I1=m.In(m.Bit) - ) + m.ClockIO() - io.CLK.unused() + I1=m.In(m.Bit), + O=m.Out(m.Bit) + ) + io.O @= io.I0 ^ io.I1 f.assert_immediate(~(io.I0 & io.I1), success_msg=success_msg, failure_msg=failure_msg, severity=severity, name=name) - tester = f.Tester(Foo, Foo.CLK) + tester = f.Tester(Foo) tester.circuit.I0 = 1 tester.circuit.I1 = 1 - tester.step(2) + tester.eval() try: with tempfile.TemporaryDirectory() as dir_: - tester.compile_and_run("verilator", magma_opts={"inline": True}, + tester.compile_and_run("verilator", magma_output="mlir-verilog", flags=['--assert'], directory=dir_, disp_type="realtime") except AssertionError: assert failure_msg is None or severity in ["error", "fatal"] else: - # warning doesn't trigger exit code/failure (but only if there's a - # failure_msg, otherwise severity is ignored) - assert severity == "warning" + assert ( + (severity == "warning") or + # If success msg but no failure msg, doesn't return error code. + (failure_msg is None and success_msg is not None) + ) out, _ = capsys.readouterr() if failure_msg is not None: - if severity == "warning": - msg = "%Warning:" + msg = { + "warning": "%Warning:", + "fatal": "%Fatal:", + "error": "%Error:", + }[severity] + msg += " Foo.v:9: " + if verilator_version() >= 5.016: + if severity == "error": + msg += "Assertion failed in " else: - msg = "%Error:" - msg += " Foo.v:31: Assertion failed in TOP.Foo" + msg += "Assertion failed in " + msg += "TOP.Foo" if name is not None: msg += f".{name}" - if severity == "error": + if failure_msg is not None: msg += f": {failure_msg}" assert msg in out, out tester.clear() tester.circuit.I0 = 0 tester.circuit.I1 = 1 - tester.step(2) + tester.eval() with tempfile.TemporaryDirectory() as dir_: tester.compile_and_run("verilator", - magma_opts={"inline": True, - "verilator_compat": True}, + magma_output="mlir-verilog", flags=['--assert'], directory=dir_, disp_type="realtime") out, _ = capsys.readouterr() @@ -97,11 +104,11 @@ class Foo(m.Circuit): tester.eval() with pytest.raises(AssertionError): with tempfile.TemporaryDirectory() as dir_: - tester.compile_and_run("verilator", magma_opts={"inline": True}, + tester.compile_and_run("verilator", magma_output="mlir-verilog", flags=['--assert', '-Wno-UNUSED'], directory=dir_, disp_type="realtime") out, _ = capsys.readouterr() - msg = ("%Error: Foo.v:15: Assertion failed in TOP.Foo: io.I0 -> 1 != 0 <-" + msg = ("%Error: Foo.v:8: Assertion failed in TOP.Foo: io.I0 -> 1 != 0 <-" " io.I1") assert msg in out, out @@ -124,15 +131,18 @@ class Foo(m.Circuit): tester.step(2) # Should pass without macro defined with tempfile.TemporaryDirectory() as dir_: - tester.compile_and_run("verilator", magma_opts={"inline": True}, + tester.compile_and_run("verilator", magma_output="mlir-verilog", flags=['--assert', '-Wno-UNUSED'], directory=dir_, disp_type="realtime") # Should fail without macro defined with pytest.raises(AssertionError): with tempfile.TemporaryDirectory() as dir_: - tester.compile_and_run("verilator", magma_opts={"inline": True}, - flags=['--assert', '-DASSERT_ON=1', - '-Wno-UNUSED'], directory=dir_) + tester.compile_and_run( + "verilator", + magma_output="mlir-verilog", + flags=['--assert', '-DASSERT_ON=1', '-Wno-UNUSED'], + directory=dir_ + ) def test_assert_final(): @@ -152,12 +162,12 @@ class Foo(m.Circuit): with pytest.raises(AssertionError): with tempfile.TemporaryDirectory() as dir_: dir_ = "build" - tester.compile_and_run("verilator", magma_opts={"inline": True}, + tester.compile_and_run("verilator", magma_output="mlir-verilog", flags=['--assert'], directory=dir_) tester.step(2) # Should pass since count is 3 with tempfile.TemporaryDirectory() as dir_: - tester.compile_and_run("verilator", magma_opts={"inline": True}, + tester.compile_and_run("verilator", magma_output="mlir-verilog", flags=['--assert'], directory=dir_) @@ -176,7 +186,8 @@ class Foo(m.Circuit): with pytest.raises(AssertionError) if not should_pass else nullcontext(): with tempfile.TemporaryDirectory() as dir_: tester.compile_and_run("system-verilog", simulator="ncsim", - magma_opts={"inline": True, "sv": True}, + magma_output="mlir-verilog", + magma_opts={"sv": True}, directory=dir_) diff --git a/tests/test_ready_valid.py b/tests/test_ready_valid.py index afabb4cd..6a6a196f 100644 --- a/tests/test_ready_valid.py +++ b/tests/test_ready_valid.py @@ -1,4 +1,3 @@ -import tempfile from hwtypes import BitVector import magma as m import fault as f @@ -23,9 +22,14 @@ def test_basic_ready_valid_sequence(): pytest.skip("Untested with earlier verilator versions") I = [BitVector.random(8) for _ in range(8)] + [0] O = [0] + [i + 1 for i in I[:-1]] - f.run_ready_valid_test(Main, {"I": I, "O": O}, "verilator", - compile_and_run_kwargs={"tmp_dir": True, - "flags": ['-Wno-UNUSED']}) + f.run_ready_valid_test( + Main, + {"I": I, "O": O}, + "verilator", + compile_and_run_kwargs={'magma_output': 'mlir-verilog', + 'tmp_dir': True, + 'magma_opts': {'flatten_all_tuples': True}} + ) def test_basic_ready_valid_sequence_fail(): @@ -35,10 +39,12 @@ def test_basic_ready_valid_sequence_fail(): O = [0] + [i - 1 for i in I[:-1]] with pytest.raises(AssertionError): f.run_ready_valid_test( - Main, {"I": I, "O": O}, + Main, + {"I": I, "O": O}, "verilator", - compile_and_run_kwargs={"tmp_dir": True, - "flags": ['-Wno-UNUSED']} + compile_and_run_kwargs={'magma_output': 'mlir-verilog', + 'tmp_dir': True, + 'magma_opts': {'flatten_all_tuples': True}} ) @@ -64,9 +70,11 @@ def test_lifted_ready_valid_sequence_simple(): tester = f.ReadyValidTester(Main2, {"I": I, "O": O}) tester.circuit.inc = 2 tester.finish_sequences() - with tempfile.TemporaryDirectory(dir=".") as _dir: - tester.compile_and_run("verilator", disp_type="realtime", - flags=['-Wno-UNUSED'], directory=_dir) + tester.compile_and_run("verilator", disp_type="realtime", + flags=['-Wno-UNUSED'], + magma_output="mlir-verilog", + magma_opts={"flatten_all_tuples": True}, + tmp_dir=True) def test_lifted_ready_valid_sequence_simple_fail(): @@ -83,9 +91,10 @@ def test_lifted_ready_valid_sequence_simple_fail(): tester.circuit.inc = 3 tester.finish_sequences() with pytest.raises(AssertionError): - with tempfile.TemporaryDirectory(dir=".") as _dir: - tester.compile_and_run("verilator", disp_type="realtime", - directory=_dir) + tester.compile_and_run("verilator", disp_type="realtime", + magma_output="mlir-verilog", + magma_opts={"flatten_all_tuples": True}, + tmp_dir=True) def test_lifted_ready_valid_sequence_changing_inc(): @@ -102,6 +111,8 @@ def test_lifted_ready_valid_sequence_changing_inc(): # Advance one cycle to finish last handshake tester.advance_cycle() tester.expect_sequences_finished() - with tempfile.TemporaryDirectory(dir=".") as _dir: - tester.compile_and_run("verilator", disp_type="realtime", - flags=['-Wno-UNUSED'], directory=_dir) + tester.compile_and_run("verilator", disp_type="realtime", + flags=['-Wno-UNUSED'], + magma_output="mlir-verilog", + magma_opts={"flatten_all_tuples": True}, + tmp_dir=True) From d21c160511d191d7a2e6db564518413175d31997 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 28 Nov 2023 10:35:44 -0800 Subject: [PATCH 43/45] When cover (#334) * Update assert to use inline_verilog2 * Fix style * Update expectation * Fix ready_valid tests * Add when support for props * Update opts * Fix style * Fix import * Add verilator version logic * Fix arg * Fix comment * Use implies logic * Improve when cond logic * Fix comment * Formatting * Disable initial blocks * Fix expectation * Try skip compile pattern * Fix expectations * Try setting magma opts * Add advance_cycle * Try not instead of ~ * Try parens * Try different expression * Skip parens on inside * remove paren logic * Remove string wrapper * Fix decorator * Set J 0 * Add decorator * Simplify property * Add boolean test * Fix numeric literal * Fix clock logic * Revert to use implies * Fix sequence * Remove paren --------- Co-authored-by: Lenny Truong --- fault/assert_immediate.py | 16 ++--- fault/assert_utils.py | 17 +++++ fault/property.py | 7 +- tests/test_property.py | 148 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 175 insertions(+), 13 deletions(-) diff --git a/fault/assert_immediate.py b/fault/assert_immediate.py index 607fba07..699ffd85 100644 --- a/fault/assert_immediate.py +++ b/fault/assert_immediate.py @@ -1,11 +1,12 @@ import magma as m -from magma.when import get_curr_block as get_curr_when_block, no_when -from fault.property import Posedge -from fault.assert_utils import add_compile_guards +from fault.assert_utils import add_compile_guards, get_when_cond def _make_assert(type_, cond, success_msg=None, failure_msg=None, severity="error", name=None, compile_guard=None, delay=False): + if (when_cond := get_when_cond()) is not None: + cond = ~when_cond | cond + success_msg_str = "" if success_msg is not None: success_msg_str = f" $display(\"{success_msg}\");" @@ -62,15 +63,6 @@ def _add_docstr(fn): @_add_docstr def assert_immediate(cond, success_msg=None, failure_msg=None, severity="error", name=None, compile_guard=None): - if get_curr_when_block(): - # guard condition by current active when using a boolean with default 0 - # and assigned inside when - with no_when(): - when_cond = m.Bit() - when_cond @= 0 - when_cond @= 1 - cond = ~when_cond | cond - _make_assert("always @(*)", cond, success_msg, failure_msg, severity, name, compile_guard) diff --git a/fault/assert_utils.py b/fault/assert_utils.py index aad2ea53..4a2d4376 100644 --- a/fault/assert_utils.py +++ b/fault/assert_utils.py @@ -1,3 +1,7 @@ +from magma.bit import Bit +from magma.when import get_curr_block as get_curr_when_block, no_when + + def add_compile_guards(compile_guard, verilog_str): if compile_guard is None: return verilog_str @@ -14,3 +18,16 @@ def add_compile_guards(compile_guard, verilog_str): `endif """ return verilog_str + + +def get_when_cond(): + """If active when cond, return a boolean that is true when the when + condition is true. + """ + if not get_curr_when_block(): + return None + with no_when(): + when_cond = Bit() + when_cond @= 0 + when_cond @= 1 + return when_cond diff --git a/fault/property.py b/fault/property.py index f0ea481f..be3ed613 100644 --- a/fault/property.py +++ b/fault/property.py @@ -3,7 +3,7 @@ from fault.sva import SVAProperty from fault.expression import Expression, UnaryOp, BinaryOp from fault.infix import Infix -from fault.assert_utils import add_compile_guards +from fault.assert_utils import add_compile_guards, get_when_cond class Property: @@ -221,6 +221,8 @@ def _compile(self, value): # Double escape on curly braces since this will run through format # inside inline_verilog logic return f"{{{{{contents}}}}}" + if isinstance(value, bool): + return f"1'b{int(value)}" if isinstance(value, int): return str(value) if isinstance(value, BinaryOp): @@ -246,6 +248,9 @@ def compile(self, prop): def _make_statement(statement, prop, on, disable_iff, compile_guard, name): + if (when_cond := get_when_cond()) is not None: + prop = when_cond | implies | prop + format_args = {} _compiler = _Compiler(format_args) prop = _compiler.compile(prop) diff --git a/tests/test_property.py b/tests/test_property.py index e2c30c95..fd680823 100644 --- a/tests/test_property.py +++ b/tests/test_property.py @@ -876,3 +876,151 @@ class Foo(m.Circuit): assert not should_pass else: assert should_pass + + +@requires_ncsim +def test_cover_when(capsys): + class Main(m.Circuit): + io = m.IO(I=m.In(m.Bit), S=m.In(m.Bit), O=m.Out(m.Bit)) + m.ClockIO() + io.O @= m.Register(T=m.Bit)()(io.I) + with m.when(io.S): + f.cover(io.I | f.delay[1] | ~io.I, on=f.posedge(io.CLK)) + with m.otherwise(): + f.cover(io.I | f.delay[1] | io.I, on=f.posedge(io.CLK)) + tester = f.SynchronousTester(Main, Main.CLK) + tester.circuit.S = 0 + tester.circuit.I = 1 + tester.advance_cycle() + tester.circuit.I = 1 + tester.advance_cycle() + tester.compile_and_run("system-verilog", + simulator="ncsim", + magma_output="mlir-verilog", + flags=["-sv"], + magma_opts={"sv": True, + "disable_initial_blocks": True}, + disp_type="realtime", + coverage=True) + + out, _ = capsys.readouterr() + assert """\ + Disabled Finish Failed Assertion Name + 0 0 0 Main_tb.dut.__cover1 + 0 1 0 Main_tb.dut.__cover2 + Total Assertions = 2, Failing Assertions = 0, Unchecked Assertions = 1\ +""" in out, out + tester.clear() + tester.circuit.CLK = 0 + tester.circuit.S = 0 + tester.circuit.I = 1 + tester.advance_cycle() + tester.circuit.I = 0 + tester.advance_cycle() + tester.compile_and_run("system-verilog", simulator="ncsim", + magma_output="mlir-verilog", flags=["-sv"], + skip_compile=True, disp_type="realtime", + magma_opts={"sv": True, + "disable_initial_blocks": True}, + coverage=True) + + out, _ = capsys.readouterr() + assert """\ + Disabled Finish Failed Assertion Name + 0 0 0 Main_tb.dut.__cover1 + 0 0 0 Main_tb.dut.__cover2 + Total Assertions = 2, Failing Assertions = 0, Unchecked Assertions = 2\ +""" in out, out + tester.clear() + tester.circuit.CLK = 0 + tester.circuit.S = 1 + tester.circuit.I = 0 + tester.advance_cycle() + tester.circuit.I = 0 + tester.advance_cycle() + tester.compile_and_run("system-verilog", simulator="ncsim", + flags=["-sv"], skip_compile=True, + magma_opts={"sv": True, + "disable_initial_blocks": True}, + disp_type="realtime", coverage=True) + + out, _ = capsys.readouterr() + assert """\ + Disabled Finish Failed Assertion Name + 0 0 0 Main_tb.dut.__cover1 + 0 0 0 Main_tb.dut.__cover2 + Total Assertions = 2, Failing Assertions = 0, Unchecked Assertions = 2\ +""" in out, out + tester.clear() + tester.circuit.CLK = 0 + tester.circuit.S = 1 + tester.circuit.I = 1 + tester.advance_cycle() + tester.circuit.I = 0 + tester.advance_cycle() + tester.compile_and_run("system-verilog", + simulator="ncsim", + magma_output="mlir-verilog", + flags=["-sv"], + skip_compile=True, + disp_type="realtime", + magma_opts={"sv": True, + "disable_initial_blocks": True}, + coverage=True) + + out, _ = capsys.readouterr() + # covered + assert """\ + Disabled Finish Failed Assertion Name + 0 1 0 Main_tb.dut.__cover1 + 0 0 0 Main_tb.dut.__cover2 + Total Assertions = 2, Failing Assertions = 0, Unchecked Assertions = 1\ +""" in out, out + + +@requires_ncsim +def test_cover_when_true(capsys): + class Main(m.Circuit): + io = m.IO( + I=m.In(m.Bit), J=m.In(m.Bit), S=m.In(m.Bit), O=m.Out(m.Bit) + ) + m.ClockIO() + io.O @= m.Register(T=m.Bit)()(io.I) + with m.when(io.S): + f.cover(True, on=f.posedge(io.CLK)) + with m.otherwise(): + f.cover(True, on=f.posedge(io.CLK)) + tester = f.SynchronousTester(Main, Main.CLK) + tester.circuit.S = 0 + tester.advance_cycle() + tester.compile_and_run("system-verilog", + simulator="ncsim", + magma_output="mlir-verilog", + flags=["-sv"], + magma_opts={"sv": True, + "disable_initial_blocks": True}, + disp_type="realtime", + coverage=True) + + out, _ = capsys.readouterr() + assert """\ + Disabled Finish Failed Assertion Name + 0 0 0 Main_tb.dut.__cover1 + 0 1 0 Main_tb.dut.__cover2 + Total Assertions = 2, Failing Assertions = 0, Unchecked Assertions = 1\ +""" in out, out + tester.clear() + tester.circuit.CLK = 0 + tester.circuit.S = 1 + tester.advance_cycle() + tester.compile_and_run("system-verilog", simulator="ncsim", + flags=["-sv"], skip_compile=True, + magma_opts={"sv": True, + "disable_initial_blocks": True}, + disp_type="realtime", coverage=True) + + out, _ = capsys.readouterr() + assert """\ + Disabled Finish Failed Assertion Name + 0 1 0 Main_tb.dut.__cover1 + 0 0 0 Main_tb.dut.__cover2 + Total Assertions = 2, Failing Assertions = 0, Unchecked Assertions = 1\ +""" in out, out From bd6c4fb4bf912bb7f54e14212346289fb72e0fbb Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 28 Nov 2023 10:36:11 -0800 Subject: [PATCH 44/45] Release v3.3.0 --- setup.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/setup.py b/setup.py index b9dd9d3c..4f7d5afc 100644 --- a/setup.py +++ b/setup.py @@ -13,7 +13,7 @@ setup( name='fault', - version='3.2.0', + version='3.3.0', description=DESCRIPTION, scripts=[], packages=[ From 088fd026a3f209065705b3ade2afa40be09fdc34 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Tue, 28 Nov 2023 10:37:08 -0800 Subject: [PATCH 45/45] Release v3.4.0 --- setup.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/setup.py b/setup.py index 4f7d5afc..e665a8b3 100644 --- a/setup.py +++ b/setup.py @@ -13,7 +13,7 @@ setup( name='fault', - version='3.3.0', + version='3.4.0', description=DESCRIPTION, scripts=[], packages=[