diff --git a/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S b/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S
index c95ba25275f..6e9155a7276 100644
--- a/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S
+++ b/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S
@@ -24,21 +24,21 @@
  *
  */
 
-	.extern ulRegTest1LoopCounter
-	.extern ulRegTest2LoopCounter
+    .extern ulRegTest1LoopCounter
+    .extern ulRegTest2LoopCounter
 
-	.global vRegTest1Implementation
-	.global vRegTest2Implementation
+    .global vRegTest1Implementation
+    .global vRegTest2Implementation
 
 /*-----------------------------------------------------------*/
 
 /* Constants to define the additional registers found on the Pulpino RI5KY. */
-#define lpstart0 	0x7b0
-#define lpend0 		0x7b1
-#define lpcount0 	0x7b2
-#define lpstart1 	0x7b4
-#define lpend1 		0x7b5
-#define lpcount1 	0x7b6
+#define lpstart0     0x7b0
+#define lpend0       0x7b1
+#define lpcount0     0x7b2
+#define lpstart1     0x7b4
+#define lpend1       0x7b5
+#define lpcount1     0x7b6
 
 /*-----------------------------------------------------------*/
 
@@ -50,147 +50,145 @@
 .align( 4 )
 vRegTest1Implementation:
 
-	/* Fill the additional registers with known values. */
-	li t0, 0xaa
-	csrw lpstart0, t0
-	li t0, 0xab
-	csrw lpstart1, t0
-	li t0, 0xac
-	csrw lpend0, t0
-	li t0, 0xad
-	csrw lpend1, t0
-	li t0, 0xae
-	csrw lpcount0, t0
-	li t0, 0xaf
-	csrw lpcount1, t0
-
-	/* Fill the core registers with known values. */
-	li x5, 0x5
-	li x6, 0x6
-	li x7, 0x7
-	li x8, 0x8
-	li x9, 0x9
-	li x10, 0xa
-	li x11, 0xb
-	li x12, 0xc
-	li x13, 0xd
-	li x14, 0xe
-	li x15, 0xf
-	li x16, 0x10
-	li x17, 0x11
-	li x18, 0x12
-	li x19, 0x13
-	li x20, 0x14
-	li x21, 0x15
-	li x22, 0x16
-	li x23, 0x17
-	li x24, 0x18
-	li x25, 0x19
-	li x26, 0x1a
-	li x27, 0x1b
-	li x28, 0x1c
-	li x29, 0x1d
-	li x30, 0x1e
+    /* Fill the additional registers with known values. */
+    li t0, 0xaa
+    csrw lpstart0, t0
+    li t0, 0xab
+    csrw lpstart1, t0
+    li t0, 0xac
+    csrw lpend0, t0
+    li t0, 0xad
+    csrw lpend1, t0
+    li t0, 0xae
+    csrw lpcount0, t0
+    li t0, 0xaf
+    csrw lpcount1, t0
+
+    /* Fill the core registers with known values. */
+    li x5, 0x5
+    li x6, 0x6
+    li x7, 0x7
+    li x8, 0x8
+    li x9, 0x9
+    li x10, 0xa
+    li x11, 0xb
+    li x12, 0xc
+    li x13, 0xd
+    li x14, 0xe
+    li x15, 0xf
+    li x16, 0x10
+    li x17, 0x11
+    li x18, 0x12
+    li x19, 0x13
+    li x20, 0x14
+    li x21, 0x15
+    li x22, 0x16
+    li x23, 0x17
+    li x24, 0x18
+    li x25, 0x19
+    li x26, 0x1a
+    li x27, 0x1b
+    li x28, 0x1c
+    li x29, 0x1d
+    li x30, 0x1e
 
 reg1_loop:
 
-	/* Check each register still contains the expected known value.
-	vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation
-	uses x5 as the temporary. */
-	li x31, 0x5
-	bne x31, x5, reg1_error_loop
-	li x31, 0x6
-	bne x31, x6, reg1_error_loop
-	li x31, 0x7
-	bne x31, x7, reg1_error_loop
-	li x31, 0x8
-	bne x31, x8, reg1_error_loop
-	li x31, 0x9
-	bne x31, x9, reg1_error_loop
-	li x31, 0xa
-	bne x31, x10, reg1_error_loop
-	li x31, 0xb
-	bne x31, x11, reg1_error_loop
-	li x31, 0xc
-	bne x31, x12, reg1_error_loop
-	li x31, 0xd
-	bne x31, x13, reg1_error_loop
-	li x31, 0xe
-	bne x31, x14, reg1_error_loop
-	li x31, 0xf
-	bne x31, x15, reg1_error_loop
-	li x31, 0x10
-	bne x31, x16, reg1_error_loop
-	li x31, 0x11
-	bne x31, x17, reg1_error_loop
-	li x31, 0x12
-	bne x31, x18, reg1_error_loop
-	li x31, 0x13
-	bne x31, x19, reg1_error_loop
-	li x31, 0x14
-	bne x31, x20, reg1_error_loop
-	li x31, 0x15
-	bne x31, x21, reg1_error_loop
-	li x31, 0x16
-	bne x31, x22, reg1_error_loop
-	li x31, 0x17
-	bne x31, x23, reg1_error_loop
-	li x31, 0x18
-	bne x31, x24, reg1_error_loop
-	li x31, 0x19
-	bne x31, x25, reg1_error_loop
-	li x31, 0x1a
-	bne x31, x26, reg1_error_loop
-	li x31, 0x1b
-	bne x31, x27, reg1_error_loop
-	li x31, 0x1c
-	bne x31, x28, reg1_error_loop
-	li x31, 0x1d
-	bne x31, x29, reg1_error_loop
-	li x31, 0x1e
-	bne x31, x30, reg1_error_loop
-
-	/* Check additional chip specific registers still contain the expected
-	values. */
-	csrr x30, lpstart0
-	li x31, 0xaa
-	bne x30, x31, reg1_error_loop
-	csrr x30, lpstart1
-	li x31, 0xab
-	bne x30, x31, reg1_error_loop
-	csrr x30, lpend0
-	li x31, 0xac
-	bne x30, x31, reg1_error_loop
-	csrr x30, lpend1
-	li x31, 0xad
-	bne x30, x31, reg1_error_loop
-	csrr x30, lpcount0
-	li x31, 0xae
-	bne x30, x31, reg1_error_loop
-	csrr x30, lpcount1
-	li x31, 0xaf
-	bne x30, x31, reg1_error_loop
-
-	/* Everything passed, increment the loop counter. */
-	lw x31, ulRegTest1LoopCounterConst
-	lw x30, 0(x31)
-	addi x30, x30, 1
-	sw x30, 0(x31)
-
-	/* Restore clobbered register reading for next loop. */
-	li x30, 0x1e
-
-	/* Yield to increase code coverage. */
-	ecall
-
-	/* Start again. */
-	jal reg1_loop
+    /* Check each register still contains the expected known value.
+    vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation
+    uses x5 as the temporary. */
+    li x31, 0x5
+    bne x31, x5, reg1_error_loop
+    li x31, 0x6
+    bne x31, x6, reg1_error_loop
+    li x31, 0x7
+    bne x31, x7, reg1_error_loop
+    li x31, 0x8
+    bne x31, x8, reg1_error_loop
+    li x31, 0x9
+    bne x31, x9, reg1_error_loop
+    li x31, 0xa
+    bne x31, x10, reg1_error_loop
+    li x31, 0xb
+    bne x31, x11, reg1_error_loop
+    li x31, 0xc
+    bne x31, x12, reg1_error_loop
+    li x31, 0xd
+    bne x31, x13, reg1_error_loop
+    li x31, 0xe
+    bne x31, x14, reg1_error_loop
+    li x31, 0xf
+    bne x31, x15, reg1_error_loop
+    li x31, 0x10
+    bne x31, x16, reg1_error_loop
+    li x31, 0x11
+    bne x31, x17, reg1_error_loop
+    li x31, 0x12
+    bne x31, x18, reg1_error_loop
+    li x31, 0x13
+    bne x31, x19, reg1_error_loop
+    li x31, 0x14
+    bne x31, x20, reg1_error_loop
+    li x31, 0x15
+    bne x31, x21, reg1_error_loop
+    li x31, 0x16
+    bne x31, x22, reg1_error_loop
+    li x31, 0x17
+    bne x31, x23, reg1_error_loop
+    li x31, 0x18
+    bne x31, x24, reg1_error_loop
+    li x31, 0x19
+    bne x31, x25, reg1_error_loop
+    li x31, 0x1a
+    bne x31, x26, reg1_error_loop
+    li x31, 0x1b
+    bne x31, x27, reg1_error_loop
+    li x31, 0x1c
+    bne x31, x28, reg1_error_loop
+    li x31, 0x1d
+    bne x31, x29, reg1_error_loop
+    li x31, 0x1e
+    bne x31, x30, reg1_error_loop
+
+    /* Check additional chip specific registers still contain the expected
+    values. */
+    csrr x30, lpstart0
+    li x31, 0xaa
+    bne x30, x31, reg1_error_loop
+    csrr x30, lpstart1
+    li x31, 0xab
+    bne x30, x31, reg1_error_loop
+    csrr x30, lpend0
+    li x31, 0xac
+    bne x30, x31, reg1_error_loop
+    csrr x30, lpend1
+    li x31, 0xad
+    bne x30, x31, reg1_error_loop
+    csrr x30, lpcount0
+    li x31, 0xae
+    bne x30, x31, reg1_error_loop
+    csrr x30, lpcount1
+    li x31, 0xaf
+    bne x30, x31, reg1_error_loop
+
+    /* Everything passed, increment the loop counter. */
+    lw x31, ulRegTest1LoopCounterConst
+    lw x30, 0(x31)
+    addi x30, x30, 1
+    sw x30, 0(x31)
+
+    /* Restore clobbered register reading for next loop. */
+    li x30, 0x1e
+
+    /* Yield to increase code coverage. */
+    ecall
+
+    /* Start again. */
+    jal reg1_loop
 
 reg1_error_loop:
-	/* Jump here if a register contains an uxpected value.  This stops the loop
-	counter being incremented so the check task knows an error was found. */
-	ebreak
-	jal reg1_error_loop
+    /* Busy loop which holds the task. */
+    jal reg1_error_loop
 
 .align( 4 )
 ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
@@ -200,146 +198,142 @@ ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
 .align( 4 )
 vRegTest2Implementation:
 
-	/* Fill the additional registers with known values. */
-	li t0, 0x1aa
-	csrw lpstart0, t0
-	li t0, 0x1ab
-	csrw lpstart1, t0
-	li t0, 0x1ac
-	csrw lpend0, t0
-	li t0, 0x1ad
-	csrw lpend1, t0
-	li t0, 0x1ae
-	csrw lpcount0, t0
-	li t0, 0x1af
-	csrw lpcount1, t0
-
-	/* Fill the core registers with known values. */
-	li x6, 0x61
-	li x7, 0x71
-	li x8, 0x81
-	li x9, 0x91
-	li x10, 0xa1
-	li x11, 0xb1
-	li x12, 0xc1
-	li x13, 0xd1
-	li x14, 0xe1
-	li x15, 0xf1
-	li x16, 0x20
-	li x17, 0x21
-	li x18, 0x22
-	li x19, 0x23
-	li x20, 0x24
-	li x21, 0x25
-	li x22, 0x26
-	li x23, 0x27
-	li x24, 0x28
-	li x25, 0x29
-	li x26, 0x2a
-	li x27, 0x2b
-	li x28, 0x2c
-	li x29, 0x2d
-	li x30, 0x2e
-	li x31, 0x2f
+    /* Fill the additional registers with known values. */
+    li t0, 0x1aa
+    csrw lpstart0, t0
+    li t0, 0x1ab
+    csrw lpstart1, t0
+    li t0, 0x1ac
+    csrw lpend0, t0
+    li t0, 0x1ad
+    csrw lpend1, t0
+    li t0, 0x1ae
+    csrw lpcount0, t0
+    li t0, 0x1af
+    csrw lpcount1, t0
+
+    /* Fill the core registers with known values. */
+    li x6, 0x61
+    li x7, 0x71
+    li x8, 0x81
+    li x9, 0x91
+    li x10, 0xa1
+    li x11, 0xb1
+    li x12, 0xc1
+    li x13, 0xd1
+    li x14, 0xe1
+    li x15, 0xf1
+    li x16, 0x20
+    li x17, 0x21
+    li x18, 0x22
+    li x19, 0x23
+    li x20, 0x24
+    li x21, 0x25
+    li x22, 0x26
+    li x23, 0x27
+    li x24, 0x28
+    li x25, 0x29
+    li x26, 0x2a
+    li x27, 0x2b
+    li x28, 0x2c
+    li x29, 0x2d
+    li x30, 0x2e
+    li x31, 0x2f
 
 Reg2_loop:
 
-	/* Check each register still contains the expected known value.
-	vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
-	uses x31 as the temporary. */
-	li x5, 0x61
-	bne x5, x6, reg2_error_loop
-	li x5, 0x71
-	bne x5, x7, reg2_error_loop
-	li x5, 0x81
-	bne x5, x8, reg2_error_loop
-	li x5, 0x91
-	bne x5, x9, reg2_error_loop
-	li x5, 0xa1
-	bne x5, x10, reg2_error_loop
-	li x5, 0xb1
-	bne x5, x11, reg2_error_loop
-	li x5, 0xc1
-	bne x5, x12, reg2_error_loop
-	li x5, 0xd1
-	bne x5, x13, reg2_error_loop
-	li x5, 0xe1
-	bne x5, x14, reg2_error_loop
-	li x5, 0xf1
-	bne x5, x15, reg2_error_loop
-	li x5, 0x20
-	bne x5, x16, reg2_error_loop
-	li x5, 0x21
-	bne x5, x17, reg2_error_loop
-	li x5, 0x22
-	bne x5, x18, reg2_error_loop
-	li x5, 0x23
-	bne x5, x19, reg2_error_loop
-	li x5, 0x24
-	bne x5, x20, reg2_error_loop
-	li x5, 0x25
-	bne x5, x21, reg2_error_loop
-	li x5, 0x26
-	bne x5, x22, reg2_error_loop
-	li x5, 0x27
-	bne x5, x23, reg2_error_loop
-	li x5, 0x28
-	bne x5, x24, reg2_error_loop
-	li x5, 0x29
-	bne x5, x25, reg2_error_loop
-	li x5, 0x2a
-	bne x5, x26, reg2_error_loop
-	li x5, 0x2b
-	bne x5, x27, reg2_error_loop
-	li x5, 0x2c
-	bne x5, x28, reg2_error_loop
-	li x5, 0x2d
-	bne x5, x29, reg2_error_loop
-	li x5, 0x2e
-	bne x5, x30, reg2_error_loop
-	li x5, 0x2f
-	bne x5, x31, reg2_error_loop
-
-	/* Check additional chip specific registers still contain the expected
-	values. */
-	csrr x5, lpstart0
-	li x6, 0x1aa
-	bne x5, x6, reg2_error_loop
-	csrr x5, lpstart1
-	li x6, 0x1ab
-	bne x5, x6, reg2_error_loop
-	csrr x5, lpend0
-	li x6, 0x1ac
-	bne x5, x6, reg2_error_loop
-	csrr x5, lpend1
-	li x6, 0x1ad
-	bne x5, x6, reg2_error_loop
-	csrr x5, lpcount0
-	li x6, 0x1ae
-	bne x5, x6, reg2_error_loop
-	csrr x5, lpcount1
-	li x6, 0x1af
-	bne x5, x6, reg2_error_loop
-
-	/* Everything passed, increment the loop counter. */
-	lw x5, ulRegTest2LoopCounterConst
-	lw x6, 0(x5)
-	addi x6, x6, 1
-	sw x6, 0(x5)
-
-	/* Restore clobbered register reading for next loop. */
-	li x6, 0x61
-
-	/* Start again. */
-	jal Reg2_loop
+    /* Check each register still contains the expected known value.
+    vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
+    uses x31 as the temporary. */
+    li x5, 0x61
+    bne x5, x6, reg2_error_loop
+    li x5, 0x71
+    bne x5, x7, reg2_error_loop
+    li x5, 0x81
+    bne x5, x8, reg2_error_loop
+    li x5, 0x91
+    bne x5, x9, reg2_error_loop
+    li x5, 0xa1
+    bne x5, x10, reg2_error_loop
+    li x5, 0xb1
+    bne x5, x11, reg2_error_loop
+    li x5, 0xc1
+    bne x5, x12, reg2_error_loop
+    li x5, 0xd1
+    bne x5, x13, reg2_error_loop
+    li x5, 0xe1
+    bne x5, x14, reg2_error_loop
+    li x5, 0xf1
+    bne x5, x15, reg2_error_loop
+    li x5, 0x20
+    bne x5, x16, reg2_error_loop
+    li x5, 0x21
+    bne x5, x17, reg2_error_loop
+    li x5, 0x22
+    bne x5, x18, reg2_error_loop
+    li x5, 0x23
+    bne x5, x19, reg2_error_loop
+    li x5, 0x24
+    bne x5, x20, reg2_error_loop
+    li x5, 0x25
+    bne x5, x21, reg2_error_loop
+    li x5, 0x26
+    bne x5, x22, reg2_error_loop
+    li x5, 0x27
+    bne x5, x23, reg2_error_loop
+    li x5, 0x28
+    bne x5, x24, reg2_error_loop
+    li x5, 0x29
+    bne x5, x25, reg2_error_loop
+    li x5, 0x2a
+    bne x5, x26, reg2_error_loop
+    li x5, 0x2b
+    bne x5, x27, reg2_error_loop
+    li x5, 0x2c
+    bne x5, x28, reg2_error_loop
+    li x5, 0x2d
+    bne x5, x29, reg2_error_loop
+    li x5, 0x2e
+    bne x5, x30, reg2_error_loop
+    li x5, 0x2f
+    bne x5, x31, reg2_error_loop
+
+    /* Check additional chip specific registers still contain the expected
+    values. */
+    csrr x5, lpstart0
+    li x6, 0x1aa
+    bne x5, x6, reg2_error_loop
+    csrr x5, lpstart1
+    li x6, 0x1ab
+    bne x5, x6, reg2_error_loop
+    csrr x5, lpend0
+    li x6, 0x1ac
+    bne x5, x6, reg2_error_loop
+    csrr x5, lpend1
+    li x6, 0x1ad
+    bne x5, x6, reg2_error_loop
+    csrr x5, lpcount0
+    li x6, 0x1ae
+    bne x5, x6, reg2_error_loop
+    csrr x5, lpcount1
+    li x6, 0x1af
+    bne x5, x6, reg2_error_loop
+
+    /* Everything passed, increment the loop counter. */
+    lw x5, ulRegTest2LoopCounterConst
+    lw x6, 0(x5)
+    addi x6, x6, 1
+    sw x6, 0(x5)
+
+    /* Restore clobbered register reading for next loop. */
+    li x6, 0x61
+
+    /* Start again. */
+    jal Reg2_loop
 
 reg2_error_loop:
-	/* Jump here if a register contains an uxpected value.  This stops the loop
-	counter being incremented so the check task knows an error was found. */
-	ebreak
-	jal reg2_error_loop
+    /* Busy loop which holds the task. */
+    jal reg2_error_loop
 
 .align( 4 )
 ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter
-
-
diff --git a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/RegTest.S b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/RegTest.S
index 4bf738e7cff..fff1e4f6f2a 100644
--- a/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/RegTest.S
+++ b/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC/build/gcc/RegTest.S
@@ -24,11 +24,11 @@
  *
  */
 
-	.extern ulRegTest1LoopCounter
-	.extern ulRegTest2LoopCounter
+    .extern ulRegTest1LoopCounter
+    .extern ulRegTest2LoopCounter
 
-	.global vRegTest1Implementation
-	.global vRegTest2Implementation
+    .global vRegTest1Implementation
+    .global vRegTest2Implementation
 
 /*-----------------------------------------------------------*/
 
@@ -40,112 +40,114 @@
 .align( 4 )
 vRegTest1Implementation:
 
-	/* Fill the core registers with known values. */
-	li x5, 0x5
-	li x6, 0x6
-	li x7, 0x7
-	li x8, 0x8
-	li x9, 0x9
-	li x10, 0xa
-	li x11, 0xb
-	li x12, 0xc
-	li x13, 0xd
-	li x14, 0xe
-	li x15, 0xf
-	li x16, 0x10
-	li x17, 0x11
-	li x18, 0x12
-	li x19, 0x13
-	li x20, 0x14
-	li x21, 0x15
-	li x22, 0x16
-	li x23, 0x17
-	li x24, 0x18
-	li x25, 0x19
-	li x26, 0x1a
-	li x27, 0x1b
-	li x28, 0x1c
-	li x29, 0x1d
-	li x30, 0x1e
+    /* Fill the core registers with known values. */
+    li x5, 0x5
+    li x6, 0x6
+    li x7, 0x7
+    li x8, 0x8
+    li x9, 0x9
+    li x10, 0xa
+    li x11, 0xb
+    li x12, 0xc
+    li x13, 0xd
+    li x14, 0xe
+#ifndef __riscv_32e
+    li x16, 0x10
+    li x17, 0x11
+    li x18, 0x12
+    li x19, 0x13
+    li x20, 0x14
+    li x21, 0x15
+    li x22, 0x16
+    li x23, 0x17
+    li x24, 0x18
+    li x25, 0x19
+    li x26, 0x1a
+    li x27, 0x1b
+    li x28, 0x1c
+    li x29, 0x1d
+    li x30, 0x1e
+    li x31, 0x1f
+#endif
 
 reg1_loop:
 
-	/* Check each register still contains the expected known value.
-	vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation
-	uses x5 as the temporary. */
-	li x31, 0x5
-	bne x31, x5, reg1_error_loop
-	li x31, 0x6
-	bne x31, x6, reg1_error_loop
-	li x31, 0x7
-	bne x31, x7, reg1_error_loop
-	li x31, 0x8
-	bne x31, x8, reg1_error_loop
-	li x31, 0x9
-	bne x31, x9, reg1_error_loop
-	li x31, 0xa
-	bne x31, x10, reg1_error_loop
-	li x31, 0xb
-	bne x31, x11, reg1_error_loop
-	li x31, 0xc
-	bne x31, x12, reg1_error_loop
-	li x31, 0xd
-	bne x31, x13, reg1_error_loop
-	li x31, 0xe
-	bne x31, x14, reg1_error_loop
-	li x31, 0xf
-	bne x31, x15, reg1_error_loop
-	li x31, 0x10
-	bne x31, x16, reg1_error_loop
-	li x31, 0x11
-	bne x31, x17, reg1_error_loop
-	li x31, 0x12
-	bne x31, x18, reg1_error_loop
-	li x31, 0x13
-	bne x31, x19, reg1_error_loop
-	li x31, 0x14
-	bne x31, x20, reg1_error_loop
-	li x31, 0x15
-	bne x31, x21, reg1_error_loop
-	li x31, 0x16
-	bne x31, x22, reg1_error_loop
-	li x31, 0x17
-	bne x31, x23, reg1_error_loop
-	li x31, 0x18
-	bne x31, x24, reg1_error_loop
-	li x31, 0x19
-	bne x31, x25, reg1_error_loop
-	li x31, 0x1a
-	bne x31, x26, reg1_error_loop
-	li x31, 0x1b
-	bne x31, x27, reg1_error_loop
-	li x31, 0x1c
-	bne x31, x28, reg1_error_loop
-	li x31, 0x1d
-	bne x31, x29, reg1_error_loop
-	li x31, 0x1e
-	bne x31, x30, reg1_error_loop
+    /* Check each register still contains the expected known value.
+    vRegTest1Implementation uses x15 as the temporary, vRegTest2Implementation
+    uses x5 as the temporary. */
+    li x15, 0x5
+    bne x15, x5, reg1_error_loop
+    li x15, 0x6
+    bne x15, x6, reg1_error_loop
+    li x15, 0x7
+    bne x15, x7, reg1_error_loop
+    li x15, 0x8
+    bne x15, x8, reg1_error_loop
+    li x15, 0x9
+    bne x15, x9, reg1_error_loop
+    li x15, 0xa
+    bne x15, x10, reg1_error_loop
+    li x15, 0xb
+    bne x15, x11, reg1_error_loop
+    li x15, 0xc
+    bne x15, x12, reg1_error_loop
+    li x15, 0xd
+    bne x15, x13, reg1_error_loop
+    li x15, 0xe
+    bne x15, x14, reg1_error_loop
+#ifndef __riscv_32e
+    li x15, 0x10
+    bne x15, x16, reg1_error_loop
+    li x15, 0x11
+    bne x15, x17, reg1_error_loop
+    li x15, 0x12
+    bne x15, x18, reg1_error_loop
+    li x15, 0x13
+    bne x15, x19, reg1_error_loop
+    li x15, 0x14
+    bne x15, x20, reg1_error_loop
+    li x15, 0x15
+    bne x15, x21, reg1_error_loop
+    li x15, 0x16
+    bne x15, x22, reg1_error_loop
+    li x15, 0x17
+    bne x15, x23, reg1_error_loop
+    li x15, 0x18
+    bne x15, x24, reg1_error_loop
+    li x15, 0x19
+    bne x15, x25, reg1_error_loop
+    li x15, 0x1a
+    bne x15, x26, reg1_error_loop
+    li x15, 0x1b
+    bne x15, x27, reg1_error_loop
+    li x15, 0x1c
+    bne x15, x28, reg1_error_loop
+    li x15, 0x1d
+    bne x15, x29, reg1_error_loop
+    li x15, 0x1e
+    bne x15, x30, reg1_error_loop
+    li x15, 0x1f
+    bne x15, x31, reg1_error_loop
+#endif
 
-	/* Everything passed, increment the loop counter. */
-	lw x31, ulRegTest1LoopCounterConst
-	lw x30, 0(x31)
-	addi x30, x30, 1
-	sw x30, 0(x31)
+    /* Everything passed, increment the loop counter. */
+    lw x15, ulRegTest1LoopCounterConst
+    lw x14, 0(x15)
+    addi x14, x14, 1
+    sw x14, 0(x15)
 
-	/* Restore clobbered register reading for next loop. */
-	li x30, 0x1e
+    /* Restore clobbered register reading for next loop. */
+    li x14, 0xe
 
-	/* Yield to increase code coverage. */
-	ecall
+    /* Yield to increase code coverage. */
+    ecall
 
-	/* Start again. */
-	jal reg1_loop
+    /* Start again. */
+    jal reg1_loop
 
 reg1_error_loop:
-	/* Jump here if a register contains an uxpected value.  This stops the loop
-	counter being incremented so the check task knows an error was found. */
-	ebreak
-	jal reg1_error_loop
+    /* Busy loop which holds the task. */
+    jal reg1_error_loop
 
 .align( 4 )
 ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
@@ -155,111 +157,111 @@ ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
 .align( 4 )
 vRegTest2Implementation:
 
-	/* Fill the core registers with known values. */
-	li x6, 0x61
-	li x7, 0x71
-	li x8, 0x81
-	li x9, 0x91
-	li x10, 0xa1
-	li x11, 0xb1
-	li x12, 0xc1
-	li x13, 0xd1
-	li x14, 0xe1
-	li x15, 0xf1
-	li x16, 0x20
-	li x17, 0x21
-	li x18, 0x22
-	li x19, 0x23
-	li x20, 0x24
-	li x21, 0x25
-	li x22, 0x26
-	li x23, 0x27
-	li x24, 0x28
-	li x25, 0x29
-	li x26, 0x2a
-	li x27, 0x2b
-	li x28, 0x2c
-	li x29, 0x2d
-	li x30, 0x2e
-	li x31, 0x2f
+    /* Fill the core registers with known values. */
+    li x6, 0x61
+    li x7, 0x71
+    li x8, 0x81
+    li x9, 0x91
+    li x10, 0xa1
+    li x11, 0xb1
+    li x12, 0xc1
+    li x13, 0xd1
+    li x14, 0xe1
+    li x15, 0xf1
+#ifndef __riscv_32e
+    li x16, 0x20
+    li x17, 0x21
+    li x18, 0x22
+    li x19, 0x23
+    li x20, 0x24
+    li x21, 0x25
+    li x22, 0x26
+    li x23, 0x27
+    li x24, 0x28
+    li x25, 0x29
+    li x26, 0x2a
+    li x27, 0x2b
+    li x28, 0x2c
+    li x29, 0x2d
+    li x30, 0x2e
+    li x31, 0x2f
+#endif
 
 Reg2_loop:
 
-	/* Check each register still contains the expected known value.
-	vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
-	uses x31 as the temporary. */
-	li x5, 0x61
-	bne x5, x6, reg2_error_loop
-	li x5, 0x71
-	bne x5, x7, reg2_error_loop
-	li x5, 0x81
-	bne x5, x8, reg2_error_loop
-	li x5, 0x91
-	bne x5, x9, reg2_error_loop
-	li x5, 0xa1
-	bne x5, x10, reg2_error_loop
-	li x5, 0xb1
-	bne x5, x11, reg2_error_loop
-	li x5, 0xc1
-	bne x5, x12, reg2_error_loop
-	li x5, 0xd1
-	bne x5, x13, reg2_error_loop
-	li x5, 0xe1
-	bne x5, x14, reg2_error_loop
-	li x5, 0xf1
-	bne x5, x15, reg2_error_loop
-	li x5, 0x20
-	bne x5, x16, reg2_error_loop
-	li x5, 0x21
-	bne x5, x17, reg2_error_loop
-	li x5, 0x22
-	bne x5, x18, reg2_error_loop
-	li x5, 0x23
-	bne x5, x19, reg2_error_loop
-	li x5, 0x24
-	bne x5, x20, reg2_error_loop
-	li x5, 0x25
-	bne x5, x21, reg2_error_loop
-	li x5, 0x26
-	bne x5, x22, reg2_error_loop
-	li x5, 0x27
-	bne x5, x23, reg2_error_loop
-	li x5, 0x28
-	bne x5, x24, reg2_error_loop
-	li x5, 0x29
-	bne x5, x25, reg2_error_loop
-	li x5, 0x2a
-	bne x5, x26, reg2_error_loop
-	li x5, 0x2b
-	bne x5, x27, reg2_error_loop
-	li x5, 0x2c
-	bne x5, x28, reg2_error_loop
-	li x5, 0x2d
-	bne x5, x29, reg2_error_loop
-	li x5, 0x2e
-	bne x5, x30, reg2_error_loop
-	li x5, 0x2f
-	bne x5, x31, reg2_error_loop
+    /* Check each register still contains the expected known value.
+    vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
+    uses x31 as the temporary. */
+    li x5, 0x61
+    bne x5, x6, reg2_error_loop
+    li x5, 0x71
+    bne x5, x7, reg2_error_loop
+    li x5, 0x81
+    bne x5, x8, reg2_error_loop
+    li x5, 0x91
+    bne x5, x9, reg2_error_loop
+    li x5, 0xa1
+    bne x5, x10, reg2_error_loop
+    li x5, 0xb1
+    bne x5, x11, reg2_error_loop
+    li x5, 0xc1
+    bne x5, x12, reg2_error_loop
+    li x5, 0xd1
+    bne x5, x13, reg2_error_loop
+    li x5, 0xe1
+    bne x5, x14, reg2_error_loop
+    li x5, 0xf1
+    bne x5, x15, reg2_error_loop
+#ifndef __riscv_32e
+    li x5, 0x20
+    bne x5, x16, reg2_error_loop
+    li x5, 0x21
+    bne x5, x17, reg2_error_loop
+    li x5, 0x22
+    bne x5, x18, reg2_error_loop
+    li x5, 0x23
+    bne x5, x19, reg2_error_loop
+    li x5, 0x24
+    bne x5, x20, reg2_error_loop
+    li x5, 0x25
+    bne x5, x21, reg2_error_loop
+    li x5, 0x26
+    bne x5, x22, reg2_error_loop
+    li x5, 0x27
+    bne x5, x23, reg2_error_loop
+    li x5, 0x28
+    bne x5, x24, reg2_error_loop
+    li x5, 0x29
+    bne x5, x25, reg2_error_loop
+    li x5, 0x2a
+    bne x5, x26, reg2_error_loop
+    li x5, 0x2b
+    bne x5, x27, reg2_error_loop
+    li x5, 0x2c
+    bne x5, x28, reg2_error_loop
+    li x5, 0x2d
+    bne x5, x29, reg2_error_loop
+    li x5, 0x2e
+    bne x5, x30, reg2_error_loop
+    li x5, 0x2f
+    bne x5, x31, reg2_error_loop
+#endif
 
-	/* Everything passed, increment the loop counter. */
-	lw x5, ulRegTest2LoopCounterConst
-	lw x6, 0(x5)
-	addi x6, x6, 1
-	sw x6, 0(x5)
+    /* Everything passed, increment the loop counter. */
+    lw x5, ulRegTest2LoopCounterConst
+    lw x6, 0(x5)
+    addi x6, x6, 1
+    sw x6, 0(x5)
 
-	/* Restore clobbered register reading for next loop. */
-	li x6, 0x61
+    /* Restore clobbered register reading for next loop. */
+    li x6, 0x61
 
-	/* Start again. */
-	jal Reg2_loop
+    /* Start again. */
+    jal Reg2_loop
 
 reg2_error_loop:
-	/* Jump here if a register contains an uxpected value.  This stops the loop
-	counter being incremented so the check task knows an error was found. */
-	ebreak
-	jal reg2_error_loop
+    /* Busy loop which holds the task. */
+    jal reg2_error_loop
 
 .align( 4 )
 ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter
-
-
diff --git a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/full_demo/RegTest.S b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/full_demo/RegTest.S
index 4bf738e7cff..d97cce51db0 100644
--- a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/full_demo/RegTest.S
+++ b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/full_demo/RegTest.S
@@ -24,11 +24,11 @@
  *
  */
 
-	.extern ulRegTest1LoopCounter
-	.extern ulRegTest2LoopCounter
+    .extern ulRegTest1LoopCounter
+    .extern ulRegTest2LoopCounter
 
-	.global vRegTest1Implementation
-	.global vRegTest2Implementation
+    .global vRegTest1Implementation
+    .global vRegTest2Implementation
 
 /*-----------------------------------------------------------*/
 
@@ -40,112 +40,115 @@
 .align( 4 )
 vRegTest1Implementation:
 
-	/* Fill the core registers with known values. */
-	li x5, 0x5
-	li x6, 0x6
-	li x7, 0x7
-	li x8, 0x8
-	li x9, 0x9
-	li x10, 0xa
-	li x11, 0xb
-	li x12, 0xc
-	li x13, 0xd
-	li x14, 0xe
-	li x15, 0xf
-	li x16, 0x10
-	li x17, 0x11
-	li x18, 0x12
-	li x19, 0x13
-	li x20, 0x14
-	li x21, 0x15
-	li x22, 0x16
-	li x23, 0x17
-	li x24, 0x18
-	li x25, 0x19
-	li x26, 0x1a
-	li x27, 0x1b
-	li x28, 0x1c
-	li x29, 0x1d
-	li x30, 0x1e
+    /* Fill the core registers with known values. */
+    li x5, 0x5
+    li x6, 0x6
+    li x7, 0x7
+    li x8, 0x8
+    li x9, 0x9
+    li x10, 0xa
+    li x11, 0xb
+    li x12, 0xc
+    li x13, 0xd
+    li x14, 0xe
+    li x15, 0xf
+#ifndef __riscv_32e
+    li x16, 0x10
+    li x17, 0x11
+    li x18, 0x12
+    li x19, 0x13
+    li x20, 0x14
+    li x21, 0x15
+    li x22, 0x16
+    li x23, 0x17
+    li x24, 0x18
+    li x25, 0x19
+    li x26, 0x1a
+    li x27, 0x1b
+    li x28, 0x1c
+    li x29, 0x1d
+    li x30, 0x1e
+    li x31, 0x1f
+#endif
 
 reg1_loop:
 
-	/* Check each register still contains the expected known value.
-	vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation
-	uses x5 as the temporary. */
-	li x31, 0x5
-	bne x31, x5, reg1_error_loop
-	li x31, 0x6
-	bne x31, x6, reg1_error_loop
-	li x31, 0x7
-	bne x31, x7, reg1_error_loop
-	li x31, 0x8
-	bne x31, x8, reg1_error_loop
-	li x31, 0x9
-	bne x31, x9, reg1_error_loop
-	li x31, 0xa
-	bne x31, x10, reg1_error_loop
-	li x31, 0xb
-	bne x31, x11, reg1_error_loop
-	li x31, 0xc
-	bne x31, x12, reg1_error_loop
-	li x31, 0xd
-	bne x31, x13, reg1_error_loop
-	li x31, 0xe
-	bne x31, x14, reg1_error_loop
-	li x31, 0xf
-	bne x31, x15, reg1_error_loop
-	li x31, 0x10
-	bne x31, x16, reg1_error_loop
-	li x31, 0x11
-	bne x31, x17, reg1_error_loop
-	li x31, 0x12
-	bne x31, x18, reg1_error_loop
-	li x31, 0x13
-	bne x31, x19, reg1_error_loop
-	li x31, 0x14
-	bne x31, x20, reg1_error_loop
-	li x31, 0x15
-	bne x31, x21, reg1_error_loop
-	li x31, 0x16
-	bne x31, x22, reg1_error_loop
-	li x31, 0x17
-	bne x31, x23, reg1_error_loop
-	li x31, 0x18
-	bne x31, x24, reg1_error_loop
-	li x31, 0x19
-	bne x31, x25, reg1_error_loop
-	li x31, 0x1a
-	bne x31, x26, reg1_error_loop
-	li x31, 0x1b
-	bne x31, x27, reg1_error_loop
-	li x31, 0x1c
-	bne x31, x28, reg1_error_loop
-	li x31, 0x1d
-	bne x31, x29, reg1_error_loop
-	li x31, 0x1e
-	bne x31, x30, reg1_error_loop
+    /* Check each register still contains the expected known value.
+    vRegTest1Implementation uses x15 as the temporary, vRegTest2Implementation
+    uses x5 as the temporary. */
+    li x15, 0x5
+    bne x15, x5, reg1_error_loop
+    li x15, 0x6
+    bne x15, x6, reg1_error_loop
+    li x15, 0x7
+    bne x15, x7, reg1_error_loop
+    li x15, 0x8
+    bne x15, x8, reg1_error_loop
+    li x15, 0x9
+    bne x15, x9, reg1_error_loop
+    li x15, 0xa
+    bne x15, x10, reg1_error_loop
+    li x15, 0xb
+    bne x15, x11, reg1_error_loop
+    li x15, 0xc
+    bne x15, x12, reg1_error_loop
+    li x15, 0xd
+    bne x15, x13, reg1_error_loop
+    li x15, 0xe
+    bne x15, x14, reg1_error_loop
+#ifndef __riscv_32e
+    li x15, 0x10
+    bne x15, x16, reg1_error_loop
+    li x15, 0x11
+    bne x15, x17, reg1_error_loop
+    li x15, 0x12
+    bne x15, x18, reg1_error_loop
+    li x15, 0x13
+    bne x15, x19, reg1_error_loop
+    li x15, 0x14
+    bne x15, x20, reg1_error_loop
+    li x15, 0x15
+    bne x15, x21, reg1_error_loop
+    li x15, 0x16
+    bne x15, x22, reg1_error_loop
+    li x15, 0x17
+    bne x15, x23, reg1_error_loop
+    li x15, 0x18
+    bne x15, x24, reg1_error_loop
+    li x15, 0x19
+    bne x15, x25, reg1_error_loop
+    li x15, 0x1a
+    bne x15, x26, reg1_error_loop
+    li x15, 0x1b
+    bne x15, x27, reg1_error_loop
+    li x15, 0x1c
+    bne x15, x28, reg1_error_loop
+    li x15, 0x1d
+    bne x15, x29, reg1_error_loop
+    li x15, 0x1e
+    bne x15, x30, reg1_error_loop
+    li x15, 0x1f
+    bne x15, x31, reg1_error_loop
+#endif
 
-	/* Everything passed, increment the loop counter. */
-	lw x31, ulRegTest1LoopCounterConst
-	lw x30, 0(x31)
-	addi x30, x30, 1
-	sw x30, 0(x31)
+    /* Everything passed, increment the loop counter. */
+    lw x15, ulRegTest1LoopCounterConst
+    lw x14, 0(x15)
+    addi x14, x14, 1
+    sw x14, 0(x15)
 
-	/* Restore clobbered register reading for next loop. */
-	li x30, 0x1e
+    /* Restore clobbered register reading for next loop. */
+    li x14, 0xe
 
-	/* Yield to increase code coverage. */
-	ecall
+    /* Yield to increase code coverage. */
+    ecall
 
-	/* Start again. */
-	jal reg1_loop
+    /* Start again. */
+    jal reg1_loop
 
 reg1_error_loop:
-	/* Jump here if a register contains an uxpected value.  This stops the loop
-	counter being incremented so the check task knows an error was found. */
-	ebreak
-	jal reg1_error_loop
+    /* Busy loop which holds the task. */
+    jal reg1_error_loop
 
 .align( 4 )
 ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
@@ -155,109 +158,111 @@ ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
 .align( 4 )
 vRegTest2Implementation:
 
-	/* Fill the core registers with known values. */
-	li x6, 0x61
-	li x7, 0x71
-	li x8, 0x81
-	li x9, 0x91
-	li x10, 0xa1
-	li x11, 0xb1
-	li x12, 0xc1
-	li x13, 0xd1
-	li x14, 0xe1
-	li x15, 0xf1
-	li x16, 0x20
-	li x17, 0x21
-	li x18, 0x22
-	li x19, 0x23
-	li x20, 0x24
-	li x21, 0x25
-	li x22, 0x26
-	li x23, 0x27
-	li x24, 0x28
-	li x25, 0x29
-	li x26, 0x2a
-	li x27, 0x2b
-	li x28, 0x2c
-	li x29, 0x2d
-	li x30, 0x2e
-	li x31, 0x2f
+    /* Fill the core registers with known values. */
+    li x6, 0x61
+    li x7, 0x71
+    li x8, 0x81
+    li x9, 0x91
+    li x10, 0xa1
+    li x11, 0xb1
+    li x12, 0xc1
+    li x13, 0xd1
+    li x14, 0xe1
+    li x15, 0xf1
+#ifdef __riscv_32e
+    li x16, 0x20
+    li x17, 0x21
+    li x18, 0x22
+    li x19, 0x23
+    li x20, 0x24
+    li x21, 0x25
+    li x22, 0x26
+    li x23, 0x27
+    li x24, 0x28
+    li x25, 0x29
+    li x26, 0x2a
+    li x27, 0x2b
+    li x28, 0x2c
+    li x29, 0x2d
+    li x30, 0x2e
+    li x31, 0x2f
+#endif
 
 Reg2_loop:
 
-	/* Check each register still contains the expected known value.
-	vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
-	uses x31 as the temporary. */
-	li x5, 0x61
-	bne x5, x6, reg2_error_loop
-	li x5, 0x71
-	bne x5, x7, reg2_error_loop
-	li x5, 0x81
-	bne x5, x8, reg2_error_loop
-	li x5, 0x91
-	bne x5, x9, reg2_error_loop
-	li x5, 0xa1
-	bne x5, x10, reg2_error_loop
-	li x5, 0xb1
-	bne x5, x11, reg2_error_loop
-	li x5, 0xc1
-	bne x5, x12, reg2_error_loop
-	li x5, 0xd1
-	bne x5, x13, reg2_error_loop
-	li x5, 0xe1
-	bne x5, x14, reg2_error_loop
-	li x5, 0xf1
-	bne x5, x15, reg2_error_loop
-	li x5, 0x20
-	bne x5, x16, reg2_error_loop
-	li x5, 0x21
-	bne x5, x17, reg2_error_loop
-	li x5, 0x22
-	bne x5, x18, reg2_error_loop
-	li x5, 0x23
-	bne x5, x19, reg2_error_loop
-	li x5, 0x24
-	bne x5, x20, reg2_error_loop
-	li x5, 0x25
-	bne x5, x21, reg2_error_loop
-	li x5, 0x26
-	bne x5, x22, reg2_error_loop
-	li x5, 0x27
-	bne x5, x23, reg2_error_loop
-	li x5, 0x28
-	bne x5, x24, reg2_error_loop
-	li x5, 0x29
-	bne x5, x25, reg2_error_loop
-	li x5, 0x2a
-	bne x5, x26, reg2_error_loop
-	li x5, 0x2b
-	bne x5, x27, reg2_error_loop
-	li x5, 0x2c
-	bne x5, x28, reg2_error_loop
-	li x5, 0x2d
-	bne x5, x29, reg2_error_loop
-	li x5, 0x2e
-	bne x5, x30, reg2_error_loop
-	li x5, 0x2f
-	bne x5, x31, reg2_error_loop
+    /* Check each register still contains the expected known value.
+    vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
+    uses x31 as the temporary. */
+    li x5, 0x61
+    bne x5, x6, reg2_error_loop
+    li x5, 0x71
+    bne x5, x7, reg2_error_loop
+    li x5, 0x81
+    bne x5, x8, reg2_error_loop
+    li x5, 0x91
+    bne x5, x9, reg2_error_loop
+    li x5, 0xa1
+    bne x5, x10, reg2_error_loop
+    li x5, 0xb1
+    bne x5, x11, reg2_error_loop
+    li x5, 0xc1
+    bne x5, x12, reg2_error_loop
+    li x5, 0xd1
+    bne x5, x13, reg2_error_loop
+    li x5, 0xe1
+    bne x5, x14, reg2_error_loop
+    li x5, 0xf1
+    bne x5, x15, reg2_error_loop
+#ifndef __riscv_32e
+    li x5, 0x20
+    bne x5, x16, reg2_error_loop
+    li x5, 0x21
+    bne x5, x17, reg2_error_loop
+    li x5, 0x22
+    bne x5, x18, reg2_error_loop
+    li x5, 0x23
+    bne x5, x19, reg2_error_loop
+    li x5, 0x24
+    bne x5, x20, reg2_error_loop
+    li x5, 0x25
+    bne x5, x21, reg2_error_loop
+    li x5, 0x26
+    bne x5, x22, reg2_error_loop
+    li x5, 0x27
+    bne x5, x23, reg2_error_loop
+    li x5, 0x28
+    bne x5, x24, reg2_error_loop
+    li x5, 0x29
+    bne x5, x25, reg2_error_loop
+    li x5, 0x2a
+    bne x5, x26, reg2_error_loop
+    li x5, 0x2b
+    bne x5, x27, reg2_error_loop
+    li x5, 0x2c
+    bne x5, x28, reg2_error_loop
+    li x5, 0x2d
+    bne x5, x29, reg2_error_loop
+    li x5, 0x2e
+    bne x5, x30, reg2_error_loop
+    li x5, 0x2f
+    bne x5, x31, reg2_error_loop
+#endif
 
-	/* Everything passed, increment the loop counter. */
-	lw x5, ulRegTest2LoopCounterConst
-	lw x6, 0(x5)
-	addi x6, x6, 1
-	sw x6, 0(x5)
+    /* Everything passed, increment the loop counter. */
+    lw x5, ulRegTest2LoopCounterConst
+    lw x6, 0(x5)
+    addi x6, x6, 1
+    sw x6, 0(x5)
 
-	/* Restore clobbered register reading for next loop. */
-	li x6, 0x61
+    /* Restore clobbered register reading for next loop. */
+    li x6, 0x61
 
-	/* Start again. */
-	jal Reg2_loop
+    /* Start again. */
+    jal Reg2_loop
 
 reg2_error_loop:
-	/* Jump here if a register contains an uxpected value.  This stops the loop
-	counter being incremented so the check task knows an error was found. */
-	ebreak
-	jal reg2_error_loop
+    /* Busy loop which holds the task. */
+    jal reg2_error_loop
 
 .align( 4 )
 ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter
diff --git a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/FreeRTOSConfig.h
index 3bb06b44c23..2f08c5dd333 100644
--- a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/FreeRTOSConfig.h
@@ -94,7 +94,7 @@
 
 /* Normal assert() semantics without relying on the provision of an assert.h
  * header file. */
-#define configASSERT( x )                   if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); __asm volatile( "ebreak" ); for( ;; ); }
+#define configASSERT( x )                   if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
 
 /* Map to the platform write function. */
 extern void vSendString( const char * const pcString );
diff --git a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/full_demo/RegTest.s b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/full_demo/RegTest.s
index 80effd4fc63..31536bfda29 100644
--- a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/full_demo/RegTest.s
+++ b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/full_demo/RegTest.s
@@ -54,7 +54,7 @@ vRegTest1Implementation:
     li x12, 0xc
     li x13, 0xd
     li x14, 0xe
-    li x15, 0xf
+#ifndef __riscv_32e
     li x16, 0x10
     li x17, 0x11
     li x18, 0x12
@@ -70,73 +70,77 @@ vRegTest1Implementation:
     li x28, 0x1c
     li x29, 0x1d
     li x30, 0x1e
+    li x31, 0x1f
+#endif
 
 reg1_loop:
 
     /* Check each register still contains the expected known value.
-     * vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation
+     * vRegTest1Implementation uses x15 as the temporary, vRegTest2Implementation
      * uses x5 as the temporary. */
-    li x31, 0x5
-    bne x31, x5, reg1_error_loop
-    li x31, 0x6
-    bne x31, x6, reg1_error_loop
-    li x31, 0x7
-    bne x31, x7, reg1_error_loop
-    li x31, 0x8
-    bne x31, x8, reg1_error_loop
-    li x31, 0x9
-    bne x31, x9, reg1_error_loop
-    li x31, 0xa
-    bne x31, x10, reg1_error_loop
-    li x31, 0xb
-    bne x31, x11, reg1_error_loop
-    li x31, 0xc
-    bne x31, x12, reg1_error_loop
-    li x31, 0xd
-    bne x31, x13, reg1_error_loop
-    li x31, 0xe
-    bne x31, x14, reg1_error_loop
-    li x31, 0xf
-    bne x31, x15, reg1_error_loop
-    li x31, 0x10
-    bne x31, x16, reg1_error_loop
-    li x31, 0x11
-    bne x31, x17, reg1_error_loop
-    li x31, 0x12
-    bne x31, x18, reg1_error_loop
-    li x31, 0x13
-    bne x31, x19, reg1_error_loop
-    li x31, 0x14
-    bne x31, x20, reg1_error_loop
-    li x31, 0x15
-    bne x31, x21, reg1_error_loop
-    li x31, 0x16
-    bne x31, x22, reg1_error_loop
-    li x31, 0x17
-    bne x31, x23, reg1_error_loop
-    li x31, 0x18
-    bne x31, x24, reg1_error_loop
-    li x31, 0x19
-    bne x31, x25, reg1_error_loop
-    li x31, 0x1a
-    bne x31, x26, reg1_error_loop
-    li x31, 0x1b
-    bne x31, x27, reg1_error_loop
-    li x31, 0x1c
-    bne x31, x28, reg1_error_loop
-    li x31, 0x1d
-    bne x31, x29, reg1_error_loop
-    li x31, 0x1e
-    bne x31, x30, reg1_error_loop
+    li x15, 0x5
+    bne x15, x5, reg1_error_loop
+    li x15, 0x6
+    bne x15, x6, reg1_error_loop
+    li x15, 0x7
+    bne x15, x7, reg1_error_loop
+    li x15, 0x8
+    bne x15, x8, reg1_error_loop
+    li x15, 0x9
+    bne x15, x9, reg1_error_loop
+    li x15, 0xa
+    bne x15, x10, reg1_error_loop
+    li x15, 0xb
+    bne x15, x11, reg1_error_loop
+    li x15, 0xc
+    bne x15, x12, reg1_error_loop
+    li x15, 0xd
+    bne x15, x13, reg1_error_loop
+    li x15, 0xe
+    bne x15, x14, reg1_error_loop
+#ifndef __riscv_32e
+    li x15, 0x10
+    bne x15, x16, reg1_error_loop
+    li x15, 0x11
+    bne x15, x17, reg1_error_loop
+    li x15, 0x12
+    bne x15, x18, reg1_error_loop
+    li x15, 0x13
+    bne x15, x19, reg1_error_loop
+    li x15, 0x14
+    bne x15, x20, reg1_error_loop
+    li x15, 0x15
+    bne x15, x21, reg1_error_loop
+    li x15, 0x16
+    bne x15, x22, reg1_error_loop
+    li x15, 0x17
+    bne x15, x23, reg1_error_loop
+    li x15, 0x18
+    bne x15, x24, reg1_error_loop
+    li x15, 0x19
+    bne x15, x25, reg1_error_loop
+    li x15, 0x1a
+    bne x15, x26, reg1_error_loop
+    li x15, 0x1b
+    bne x15, x27, reg1_error_loop
+    li x15, 0x1c
+    bne x15, x28, reg1_error_loop
+    li x15, 0x1d
+    bne x15, x29, reg1_error_loop
+    li x15, 0x1e
+    bne x15, x30, reg1_error_loop
+    li x15, 0x1f
+    bne x15, x31, reg1_error_loop
+#endif
 
     /* Everything passed, increment the loop counter. */
-    lw x31, pulRegTest1LoopCounter
-    lw x30, 0(x31)
-    addi x30, x30, 1
-    sw x30, 0(x31)
+    lw x15, pulRegTest1LoopCounter
+    lw x14, 0(x15)
+    addi x14, x14, 1
+    sw x14, 0(x15)
 
     /* Restore clobbered register reading for next loop. */
-    li x30, 0x1e
+    li x14, 0xe
 
     /* Yield to increase code coverage. */
     ecall
@@ -145,9 +149,7 @@ reg1_loop:
     jal reg1_loop
 
 reg1_error_loop:
-    /* Jump here if a register contains an uxpected value.  This stops the loop
-     * counter being incremented so the check task knows an error was found. */
-    ebreak
+    /* Busy loop which holds the task. */
     jal reg1_error_loop
 
 /*-----------------------------------------------------------*/
@@ -166,6 +168,7 @@ vRegTest2Implementation:
     li x13, 0xd1
     li x14, 0xe1
     li x15, 0xf1
+#ifndef __riscv_32e
     li x16, 0x20
     li x17, 0x21
     li x18, 0x22
@@ -182,12 +185,13 @@ vRegTest2Implementation:
     li x29, 0x2d
     li x30, 0x2e
     li x31, 0x2f
+#endif
 
 Reg2_loop:
 
     /* Check each register still contains the expected known value.
      * vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
-     * uses x31 as the temporary. */
+     * uses x15 as the temporary. */
     li x5, 0x61
     bne x5, x6, reg2_error_loop
     li x5, 0x71
@@ -208,6 +212,7 @@ Reg2_loop:
     bne x5, x14, reg2_error_loop
     li x5, 0xf1
     bne x5, x15, reg2_error_loop
+#ifndef __riscv_32e
     li x5, 0x20
     bne x5, x16, reg2_error_loop
     li x5, 0x21
@@ -240,6 +245,7 @@ Reg2_loop:
     bne x5, x30, reg2_error_loop
     li x5, 0x2f
     bne x5, x31, reg2_error_loop
+#endif
 
     /* Everything passed, increment the loop counter. */
     lw x5, pulRegTest2LoopCounter
@@ -254,9 +260,7 @@ Reg2_loop:
     jal Reg2_loop
 
 reg2_error_loop:
-    /* Jump here if a register contains an uxpected value.  This stops the loop
-     * counter being incremented so the check task knows an error was found. */
-    ebreak
+    /* Busy loop which holds the task. */
     jal reg2_error_loop
 
 /*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/main.c b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/main.c
index bc31adbe892..8a8a52bb393 100644
--- a/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/main.c
+++ b/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/main.c
@@ -242,7 +242,6 @@ void vApplicationMallocFailedHook( void )
      * to query the size of free heap space that remains (although it does not
      * provide information on how the remaining heap might be fragmented). */
     taskDISABLE_INTERRUPTS();
-    __asm volatile( "ebreak" );
     for( ;; );
 }
 /*-----------------------------------------------------------*/
@@ -270,7 +269,6 @@ void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
      * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2.  This hook
      * function is called if a stack overflow is detected. */
     taskDISABLE_INTERRUPTS();
-    __asm volatile( "ebreak" );
     for( ;; );
 }
 /*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/full_demo/RegTest.S b/FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/full_demo/RegTest.S
index 187ab215136..3ac8e67551c 100644
--- a/FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/full_demo/RegTest.S
+++ b/FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/full_demo/RegTest.S
@@ -142,9 +142,7 @@ reg1_loop:
     jal reg1_loop
 
 reg1_error_loop:
-    /* Jump here if a register contains an uxpected value.  This stops the loop
-     * counter being incremented so the check task knows an error was found. */
-    ebreak
+    /* Busy loop which holds the task. */
     jal reg1_error_loop
 
 .align( 4 )
@@ -254,9 +252,7 @@ Reg2_loop:
     jal Reg2_loop
 
 reg2_error_loop:
-    /* Jump here if a register contains an uxpected value.  This stops the loop
-     * counter being incremented so the check task knows an error was found. */
-    ebreak
+    /* Busy loop which holds the task. */
     jal reg2_error_loop
 
 .align( 4 )
diff --git a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/FreeRTOSConfig.h b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/FreeRTOSConfig.h
index 8ba7bde1142..ce6027aabf1 100644
--- a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/FreeRTOSConfig.h
@@ -98,7 +98,7 @@ to exclude the API function. */
 
 /* Normal assert() semantics without relying on the provision of an assert.h
 header file. */
-#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); __asm volatile( "ebreak" ); for( ;; ); }
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
 
 /* Defined in main.c and used in main_blinky.c and main_full.c. */
 void vSendString( const char * const pcString );
diff --git a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/RegTest.S b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/RegTest.S
index 3382c21840c..5ed5468e222 100644
--- a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/RegTest.S
+++ b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/full_demo/RegTest.S
@@ -24,11 +24,11 @@
  *
  */
 
-	.extern ulRegTest1LoopCounter
-	.extern ulRegTest2LoopCounter
+    .extern ulRegTest1LoopCounter
+    .extern ulRegTest2LoopCounter
 
-	.global vRegTest1Implementation
-	.global vRegTest2Implementation
+    .global vRegTest1Implementation
+    .global vRegTest2Implementation
 
 /*-----------------------------------------------------------*/
 
@@ -40,112 +40,110 @@
 .align( 4 )
 vRegTest1Implementation:
 
-	/* Fill the core registers with known values. */
-	li x5, 0x5
-	li x6, 0x6
-	li x7, 0x7
-	li x8, 0x8
-	li x9, 0x9
-	li x10, 0xa
-	li x11, 0xb
-	li x12, 0xc
-	li x13, 0xd
-	li x14, 0xe
-	li x15, 0xf
-	li x16, 0x10
-	li x17, 0x11
-	li x18, 0x12
-	li x19, 0x13
-	li x20, 0x14
-	li x21, 0x15
-	li x22, 0x16
-	li x23, 0x17
-	li x24, 0x18
-	li x25, 0x19
-	li x26, 0x1a
-	li x27, 0x1b
-	li x28, 0x1c
-	li x29, 0x1d
-	li x30, 0x1e
+    /* Fill the core registers with known values. */
+    li x5, 0x5
+    li x6, 0x6
+    li x7, 0x7
+    li x8, 0x8
+    li x9, 0x9
+    li x10, 0xa
+    li x11, 0xb
+    li x12, 0xc
+    li x13, 0xd
+    li x14, 0xe
+    li x15, 0xf
+    li x16, 0x10
+    li x17, 0x11
+    li x18, 0x12
+    li x19, 0x13
+    li x20, 0x14
+    li x21, 0x15
+    li x22, 0x16
+    li x23, 0x17
+    li x24, 0x18
+    li x25, 0x19
+    li x26, 0x1a
+    li x27, 0x1b
+    li x28, 0x1c
+    li x29, 0x1d
+    li x30, 0x1e
 
 reg1_loop:
 
-	/* Check each register still contains the expected known value.
-	vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation
-	uses x5 as the temporary. */
-	li x31, 0x5
-	bne x31, x5, reg1_error_loop
-	li x31, 0x6
-	bne x31, x6, reg1_error_loop
-	li x31, 0x7
-	bne x31, x7, reg1_error_loop
-	li x31, 0x8
-	bne x31, x8, reg1_error_loop
-	li x31, 0x9
-	bne x31, x9, reg1_error_loop
-	li x31, 0xa
-	bne x31, x10, reg1_error_loop
-	li x31, 0xb
-	bne x31, x11, reg1_error_loop
-	li x31, 0xc
-	bne x31, x12, reg1_error_loop
-	li x31, 0xd
-	bne x31, x13, reg1_error_loop
-	li x31, 0xe
-	bne x31, x14, reg1_error_loop
-	li x31, 0xf
-	bne x31, x15, reg1_error_loop
-	li x31, 0x10
-	bne x31, x16, reg1_error_loop
-	li x31, 0x11
-	bne x31, x17, reg1_error_loop
-	li x31, 0x12
-	bne x31, x18, reg1_error_loop
-	li x31, 0x13
-	bne x31, x19, reg1_error_loop
-	li x31, 0x14
-	bne x31, x20, reg1_error_loop
-	li x31, 0x15
-	bne x31, x21, reg1_error_loop
-	li x31, 0x16
-	bne x31, x22, reg1_error_loop
-	li x31, 0x17
-	bne x31, x23, reg1_error_loop
-	li x31, 0x18
-	bne x31, x24, reg1_error_loop
-	li x31, 0x19
-	bne x31, x25, reg1_error_loop
-	li x31, 0x1a
-	bne x31, x26, reg1_error_loop
-	li x31, 0x1b
-	bne x31, x27, reg1_error_loop
-	li x31, 0x1c
-	bne x31, x28, reg1_error_loop
-	li x31, 0x1d
-	bne x31, x29, reg1_error_loop
-	li x31, 0x1e
-	bne x31, x30, reg1_error_loop
+    /* Check each register still contains the expected known value.
+    vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation
+    uses x5 as the temporary. */
+    li x31, 0x5
+    bne x31, x5, reg1_error_loop
+    li x31, 0x6
+    bne x31, x6, reg1_error_loop
+    li x31, 0x7
+    bne x31, x7, reg1_error_loop
+    li x31, 0x8
+    bne x31, x8, reg1_error_loop
+    li x31, 0x9
+    bne x31, x9, reg1_error_loop
+    li x31, 0xa
+    bne x31, x10, reg1_error_loop
+    li x31, 0xb
+    bne x31, x11, reg1_error_loop
+    li x31, 0xc
+    bne x31, x12, reg1_error_loop
+    li x31, 0xd
+    bne x31, x13, reg1_error_loop
+    li x31, 0xe
+    bne x31, x14, reg1_error_loop
+    li x31, 0xf
+    bne x31, x15, reg1_error_loop
+    li x31, 0x10
+    bne x31, x16, reg1_error_loop
+    li x31, 0x11
+    bne x31, x17, reg1_error_loop
+    li x31, 0x12
+    bne x31, x18, reg1_error_loop
+    li x31, 0x13
+    bne x31, x19, reg1_error_loop
+    li x31, 0x14
+    bne x31, x20, reg1_error_loop
+    li x31, 0x15
+    bne x31, x21, reg1_error_loop
+    li x31, 0x16
+    bne x31, x22, reg1_error_loop
+    li x31, 0x17
+    bne x31, x23, reg1_error_loop
+    li x31, 0x18
+    bne x31, x24, reg1_error_loop
+    li x31, 0x19
+    bne x31, x25, reg1_error_loop
+    li x31, 0x1a
+    bne x31, x26, reg1_error_loop
+    li x31, 0x1b
+    bne x31, x27, reg1_error_loop
+    li x31, 0x1c
+    bne x31, x28, reg1_error_loop
+    li x31, 0x1d
+    bne x31, x29, reg1_error_loop
+    li x31, 0x1e
+    bne x31, x30, reg1_error_loop
 
-	/* Everything passed, increment the loop counter. */
-	lw x31, ulRegTest1LoopCounterConst
-	lw x30, 0(x31)
-	addi x30, x30, 1
-	sw x30, 0(x31)
+    /* Everything passed, increment the loop counter. */
+    lw x31, ulRegTest1LoopCounterConst
+    lw x30, 0(x31)
+    addi x30, x30, 1
+    sw x30, 0(x31)
 
-	/* Restore clobbered register reading for next loop. */
-	li x30, 0x1e
+    /* Restore clobbered register reading for next loop. */
+    li x30, 0x1e
 
-	/* Yield to increase code coverage. */
-	ecall
+    /* Yield to increase code coverage. */
+    ecall
 
-	/* Start again. */
-	jal reg1_loop
+    /* Start again. */
+    jal reg1_loop
 
 reg1_error_loop:
-	/* Jump here if a register contains an uxpected value.  This stops the loop
-	counter being incremented so the check task knows an error was found. */
-	ebreak
-	jal reg1_error_loop
+    /* Busy loop which holds the task. */
+    jal reg1_error_loop
 
 .align( 4 )
 ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
@@ -155,109 +153,107 @@ ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter
 .align( 4 )
 vRegTest2Implementation:
 
-	/* Fill the core registers with known values. */
-	li x6, 0x61
-	li x7, 0x71
-	li x8, 0x81
-	li x9, 0x91
-	li x10, 0xa1
-	li x11, 0xb1
-	li x12, 0xc1
-	li x13, 0xd1
-	li x14, 0xe1
-	li x15, 0xf1
-	li x16, 0x20
-	li x17, 0x21
-	li x18, 0x22
-	li x19, 0x23
-	li x20, 0x24
-	li x21, 0x25
-	li x22, 0x26
-	li x23, 0x27
-	li x24, 0x28
-	li x25, 0x29
-	li x26, 0x2a
-	li x27, 0x2b
-	li x28, 0x2c
-	li x29, 0x2d
-	li x30, 0x2e
-	li x31, 0x2f
+    /* Fill the core registers with known values. */
+    li x6, 0x61
+    li x7, 0x71
+    li x8, 0x81
+    li x9, 0x91
+    li x10, 0xa1
+    li x11, 0xb1
+    li x12, 0xc1
+    li x13, 0xd1
+    li x14, 0xe1
+    li x15, 0xf1
+    li x16, 0x20
+    li x17, 0x21
+    li x18, 0x22
+    li x19, 0x23
+    li x20, 0x24
+    li x21, 0x25
+    li x22, 0x26
+    li x23, 0x27
+    li x24, 0x28
+    li x25, 0x29
+    li x26, 0x2a
+    li x27, 0x2b
+    li x28, 0x2c
+    li x29, 0x2d
+    li x30, 0x2e
+    li x31, 0x2f
 
 Reg2_loop:
 
-	/* Check each register still contains the expected known value.
-	vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
-	uses x31 as the temporary. */
-	li x5, 0x61
-	bne x5, x6, reg2_error_loop
-	li x5, 0x71
-	bne x5, x7, reg2_error_loop
-	li x5, 0x81
-	bne x5, x8, reg2_error_loop
-	li x5, 0x91
-	bne x5, x9, reg2_error_loop
-	li x5, 0xa1
-	bne x5, x10, reg2_error_loop
-	li x5, 0xb1
-	bne x5, x11, reg2_error_loop
-	li x5, 0xc1
-	bne x5, x12, reg2_error_loop
-	li x5, 0xd1
-	bne x5, x13, reg2_error_loop
-	li x5, 0xe1
-	bne x5, x14, reg2_error_loop
-	li x5, 0xf1
-	bne x5, x15, reg2_error_loop
-	li x5, 0x20
-	bne x5, x16, reg2_error_loop
-	li x5, 0x21
-	bne x5, x17, reg2_error_loop
-	li x5, 0x22
-	bne x5, x18, reg2_error_loop
-	li x5, 0x23
-	bne x5, x19, reg2_error_loop
-	li x5, 0x24
-	bne x5, x20, reg2_error_loop
-	li x5, 0x25
-	bne x5, x21, reg2_error_loop
-	li x5, 0x26
-	bne x5, x22, reg2_error_loop
-	li x5, 0x27
-	bne x5, x23, reg2_error_loop
-	li x5, 0x28
-	bne x5, x24, reg2_error_loop
-	li x5, 0x29
-	bne x5, x25, reg2_error_loop
-	li x5, 0x2a
-	bne x5, x26, reg2_error_loop
-	li x5, 0x2b
-	bne x5, x27, reg2_error_loop
-	li x5, 0x2c
-	bne x5, x28, reg2_error_loop
-	li x5, 0x2d
-	bne x5, x29, reg2_error_loop
-	li x5, 0x2e
-	bne x5, x30, reg2_error_loop
-	li x5, 0x2f
-	bne x5, x31, reg2_error_loop
+    /* Check each register still contains the expected known value.
+    vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
+    uses x31 as the temporary. */
+    li x5, 0x61
+    bne x5, x6, reg2_error_loop
+    li x5, 0x71
+    bne x5, x7, reg2_error_loop
+    li x5, 0x81
+    bne x5, x8, reg2_error_loop
+    li x5, 0x91
+    bne x5, x9, reg2_error_loop
+    li x5, 0xa1
+    bne x5, x10, reg2_error_loop
+    li x5, 0xb1
+    bne x5, x11, reg2_error_loop
+    li x5, 0xc1
+    bne x5, x12, reg2_error_loop
+    li x5, 0xd1
+    bne x5, x13, reg2_error_loop
+    li x5, 0xe1
+    bne x5, x14, reg2_error_loop
+    li x5, 0xf1
+    bne x5, x15, reg2_error_loop
+    li x5, 0x20
+    bne x5, x16, reg2_error_loop
+    li x5, 0x21
+    bne x5, x17, reg2_error_loop
+    li x5, 0x22
+    bne x5, x18, reg2_error_loop
+    li x5, 0x23
+    bne x5, x19, reg2_error_loop
+    li x5, 0x24
+    bne x5, x20, reg2_error_loop
+    li x5, 0x25
+    bne x5, x21, reg2_error_loop
+    li x5, 0x26
+    bne x5, x22, reg2_error_loop
+    li x5, 0x27
+    bne x5, x23, reg2_error_loop
+    li x5, 0x28
+    bne x5, x24, reg2_error_loop
+    li x5, 0x29
+    bne x5, x25, reg2_error_loop
+    li x5, 0x2a
+    bne x5, x26, reg2_error_loop
+    li x5, 0x2b
+    bne x5, x27, reg2_error_loop
+    li x5, 0x2c
+    bne x5, x28, reg2_error_loop
+    li x5, 0x2d
+    bne x5, x29, reg2_error_loop
+    li x5, 0x2e
+    bne x5, x30, reg2_error_loop
+    li x5, 0x2f
+    bne x5, x31, reg2_error_loop
 
-	/* Everything passed, increment the loop counter. */
-	lw x5, ulRegTest2LoopCounterConst
-	lw x6, 0(x5)
-	addi x6, x6, 1
-	sw x6, 0(x5)
+    /* Everything passed, increment the loop counter. */
+    lw x5, ulRegTest2LoopCounterConst
+    lw x6, 0(x5)
+    addi x6, x6, 1
+    sw x6, 0(x5)
 
-	/* Restore clobbered register reading for next loop. */
-	li x6, 0x61
+    /* Restore clobbered register reading for next loop. */
+    li x6, 0x61
 
-	/* Start again. */
-	jal Reg2_loop
+    /* Start again. */
+    jal Reg2_loop
 
 reg2_error_loop:
-	/* Jump here if a register contains an uxpected value.  This stops the loop
-	counter being incremented so the check task knows an error was found. */
-	ebreak
-	jal reg2_error_loop
+    /* Busy loop which holds the task. */
+    jal reg2_error_loop
 
 .align( 4 )
 ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter
diff --git a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/main.c b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/main.c
index 475e5e95af7..c2f8f693c81 100644
--- a/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/main.c
+++ b/FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/main.c
@@ -137,7 +137,6 @@ void vApplicationMallocFailedHook( void )
 	to query the size of free heap space that remains (although it does not
 	provide information on how the remaining heap might be fragmented). */
 	taskDISABLE_INTERRUPTS();
-	__asm volatile( "ebreak" );
 	for( ;; );
 }
 /*-----------------------------------------------------------*/
@@ -165,7 +164,6 @@ void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
 	configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2.  This hook
 	function is called if a stack overflow is detected. */
 	taskDISABLE_INTERRUPTS();
-	__asm volatile( "ebreak" );
 	for( ;; );
 }
 /*-----------------------------------------------------------*/