| +Device + | ++xc7z010 + | +
| +SpeedGrade + | ++-1 + | +
| +Part + | ++xc7z010clg400-1 + | +
| +Description + | ++Zynq PS Configuration Report with register details + | +
| +Vendor + | ++Xilinx + | +
| +MIO Pin + | ++Peripheral + | ++Signal + | ++IO Type + | ++Speed + | ++Pullup + | ++Direction + | +
| +MIO 0 + | ++GPIO + | ++gpio[0] + | ++LVCMOS 3.3V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 1 + | ++Quad SPI Flash + | ++qspi0_ss_b + | ++LVCMOS 3.3V + | ++slow + | ++disabled + | ++out + | +
| +MIO 2 + | ++Quad SPI Flash + | ++qspi0_io[0] + | ++LVCMOS 3.3V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 3 + | ++Quad SPI Flash + | ++qspi0_io[1] + | ++LVCMOS 3.3V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 4 + | ++Quad SPI Flash + | ++qspi0_io[2] + | ++LVCMOS 3.3V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 5 + | ++Quad SPI Flash + | ++qspi0_io[3] + | ++LVCMOS 3.3V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 6 + | ++Quad SPI Flash + | ++qspi0_sclk + | ++LVCMOS 3.3V + | ++slow + | ++disabled + | ++out + | +
| +MIO 7 + | ++USB Reset + | ++reset + | ++LVCMOS 3.3V + | ++slow + | ++disabled + | ++out + | +
| +MIO 8 + | ++Quad SPI Flash + | ++qspi_fbclk + | ++LVCMOS 3.3V + | ++slow + | ++disabled + | ++out + | +
| +MIO 9 + | ++GPIO + | ++gpio[9] + | ++LVCMOS 3.3V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 10 + | ++GPIO + | ++gpio[10] + | ++LVCMOS 3.3V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 11 + | ++GPIO + | ++gpio[11] + | ++LVCMOS 3.3V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 12 + | ++GPIO + | ++gpio[12] + | ++LVCMOS 3.3V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 13 + | ++GPIO + | ++gpio[13] + | ++LVCMOS 3.3V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 14 + | ++GPIO + | ++gpio[14] + | ++LVCMOS 3.3V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 15 + | ++GPIO + | ++gpio[15] + | ++LVCMOS 3.3V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 16 + | ++Enet 0 + | ++tx_clk + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++out + | +
| +MIO 17 + | ++Enet 0 + | ++txd[0] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++out + | +
| +MIO 18 + | ++Enet 0 + | ++txd[1] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++out + | +
| +MIO 19 + | ++Enet 0 + | ++txd[2] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++out + | +
| +MIO 20 + | ++Enet 0 + | ++txd[3] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++out + | +
| +MIO 21 + | ++Enet 0 + | ++tx_ctl + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++out + | +
| +MIO 22 + | ++Enet 0 + | ++rx_clk + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++in + | +
| +MIO 23 + | ++Enet 0 + | ++rxd[0] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++in + | +
| +MIO 24 + | ++Enet 0 + | ++rxd[1] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++in + | +
| +MIO 25 + | ++Enet 0 + | ++rxd[2] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++in + | +
| +MIO 26 + | ++Enet 0 + | ++rxd[3] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++in + | +
| +MIO 27 + | ++Enet 0 + | ++rx_ctl + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++in + | +
| +MIO 28 + | ++USB 0 + | ++data[4] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 29 + | ++USB 0 + | ++dir + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++in + | +
| +MIO 30 + | ++USB 0 + | ++stp + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++out + | +
| +MIO 31 + | ++USB 0 + | ++nxt + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++in + | +
| +MIO 32 + | ++USB 0 + | ++data[0] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 33 + | ++USB 0 + | ++data[1] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 34 + | ++USB 0 + | ++data[2] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 35 + | ++USB 0 + | ++data[3] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 36 + | ++USB 0 + | ++clk + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++in + | +
| +MIO 37 + | ++USB 0 + | ++data[5] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 38 + | ++USB 0 + | ++data[6] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 39 + | ++USB 0 + | ++data[7] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 40 + | ++SD 0 + | ++clk + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 41 + | ++SD 0 + | ++cmd + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 42 + | ++SD 0 + | ++data[0] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 43 + | ++SD 0 + | ++data[1] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 44 + | ++SD 0 + | ++data[2] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 45 + | ++SD 0 + | ++data[3] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 46 + | ++SD 0 + | ++cd + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++in + | +
| +MIO 47 + | ++GPIO + | ++gpio[47] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 48 + | ++UART 1 + | ++tx + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++out + | +
| +MIO 49 + | ++UART 1 + | ++rx + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++in + | +
| +MIO 50 + | ++SD 0 + | ++wp + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++in + | +
| +MIO 51 + | ++GPIO + | ++gpio[51] + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++inout + | +
| +MIO 52 + | ++Enet 0 + | ++mdc + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++out + | +
| +MIO 53 + | ++Enet 0 + | ++mdio + | ++LVCMOS 1.8V + | ++slow + | ++disabled + | ++inout + | +
| +Parameter name + | ++Value + | ++Description + | +
| +Enable DDR + | ++1 + | ++Enable DDR Controller of Zynq PS + | +
| +Enable DDR + | ++1 + | ++Enable DDR Controller of Zynq PS + | +
| +Memory Part + | ++MT41K256M16 RE-125 + | ++ + | +
| +DRAM bus width + | ++32 Bit + | ++Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths + | +
| +ECC + | ++Disabled + | ++ECC is supported only for data width of 16-bit + | +
| +BURST Length (lppdr only) + | ++8 + | ++Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller + | +
| +Internal Vref + | ++1 + | ++ + | +
| +Operating Frequency (MHz) + | ++533.333333 + | ++Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade + | +
| +HIGH temperature + | ++Normal (0-85) + | ++Select the operating temparature + | +
| +DRAM IC bus width + | ++16 Bits + | ++Provide the width of the DRAM chip + | +
| +DRAM Device Capacity + | ++4096 MBits + | ++ + | +
| +Speed Bin + | ++DDR3_1066F + | ++Provide the Speed Bin + | +
| +BANK Address Count + | ++3 + | ++Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied + | +
| +ROW Address Count + | ++15 + | ++Provide the Row address for ACTIVE commands + | +
| +COLUMN Address Count + | ++10 + | ++Provide the Row address for READ/WRITE commands + | +
| +CAS Latency + | ++7 + | ++Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module + | +
| +CAS Write Latency + | ++6 + | ++Select the CAS Write Latency + | +
| +RAS to CAS Delay + | ++7 + | ++Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) + | +
| +RECHARGE Time + | ++7 + | ++Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row + | +
| +tRC (ns ) + | ++48.75 + | ++Provide the Row cycle time tRC (ns) + | +
| +tRASmin ( ns ) + | ++35.0 + | ++tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command + | +
| +tFAW + | ++40.0 + | ++It restricts the number of activates that can be done within a certain window of time + | +
| +ADDITIVE Latency + | ++0 + | ++Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths + | +
| +Write levelling + | ++1 + | ++ + | +
| +Read gate + | ++1 + | ++ + | +
| +Read gate + | ++1 + | ++ + | +
| +DQS to Clock delay [0] (ns) + | ++-0.073 + | ++The daly difference of each DQS path delay subtracted from the clock path delay + | +
| +DQS to Clock delay [1] (ns) + | ++-0.072 + | ++The daly difference of each DQS path delay subtracted from the clock path delay + | +
| +DQS to Clock delay [2] (ns) + | ++0.024 + | ++The daly difference of each DQS path delay subtracted from the clock path delay + | +
| +DQS to Clock delay [3] (ns) + | ++0.023 + | ++The daly difference of each DQS path delay subtracted from the clock path delay + | +
| +Board delay [0] (ns) + | ++0.294 + | ++The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) + | +
| +Board delay [1] (ns) + | ++0.298 + | ++The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) + | +
| +Board delay [2] (ns) + | ++0.338 + | ++The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) + | +
| +Board delay [3] (ns) + | ++0.334 + | ++The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) + | +
| +Peripheral + | ++PLL source + | ++Frequency (MHz) + | +
| +CPU 6x Freq (MHz) + | ++ARM PLL + | ++666.666687 + | +
| +QSPI Flash Freq (MHz) + | ++IO PLL + | ++200.000000 + | +
| +ENET0 Freq (MHz) + | ++IO PLL + | ++125.000000 + | +
| +SDIO Freq (MHz) + | ++IO PLL + | ++50.000000 + | +
| +UART Freq (MHz) + | ++IO PLL + | ++50.000000 + | +
| +TTC0 CLK0 Freq (MHz) + | ++CPU_1X + | ++111.111115 + | +
| +TTC0 CLK1 Freq (MHz) + | ++CPU_1X + | ++111.111115 + | +
| +TTC0 CLK2 Freq (MHz) + | ++CPU_1X + | ++111.111115 + | +
| +FPGA0 Freq (MHz) + | ++IO PLL + | ++100.000000 + | +
| +FPGA1 Freq (MHz) + | ++IO PLL + | ++100.000000 + | +
| +FPGA2 Freq (MHz) + | ++IO PLL + | ++33.333336 + | +
| +FPGA3 Freq (MHz) + | ++IO PLL + | ++50.000000 + | +
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| + +SLCR_UNLOCK + + | ++0XF8000008 + | ++32 + | ++WO + | ++0x000000 + | ++SLCR Write Protection Unlock + | +
| + +ARM_PLL_CFG + + | ++0XF8000110 + | ++32 + | ++RW + | ++0x000000 + | ++ARM PLL Configuration + | +
| + +ARM_PLL_CTRL + + | ++0XF8000100 + | ++32 + | ++RW + | ++0x000000 + | ++ARM PLL Control + | +
| + +ARM_PLL_CTRL + + | ++0XF8000100 + | ++32 + | ++RW + | ++0x000000 + | ++ARM PLL Control + | +
| + +ARM_PLL_CTRL + + | ++0XF8000100 + | ++32 + | ++RW + | ++0x000000 + | ++ARM PLL Control + | +
| + +ARM_PLL_CTRL + + | ++0XF8000100 + | ++32 + | ++RW + | ++0x000000 + | ++ARM PLL Control + | +
| + +ARM_PLL_CTRL + + | ++0XF8000100 + | ++32 + | ++RW + | ++0x000000 + | ++ARM PLL Control + | +
| + +ARM_CLK_CTRL + + | ++0XF8000120 + | ++32 + | ++RW + | ++0x000000 + | ++CPU Clock Control + | +
| + +DDR_PLL_CFG + + | ++0XF8000114 + | ++32 + | ++RW + | ++0x000000 + | ++DDR PLL Configuration + | +
| + +DDR_PLL_CTRL + + | ++0XF8000104 + | ++32 + | ++RW + | ++0x000000 + | ++DDR PLL Control + | +
| + +DDR_PLL_CTRL + + | ++0XF8000104 + | ++32 + | ++RW + | ++0x000000 + | ++DDR PLL Control + | +
| + +DDR_PLL_CTRL + + | ++0XF8000104 + | ++32 + | ++RW + | ++0x000000 + | ++DDR PLL Control + | +
| + +DDR_PLL_CTRL + + | ++0XF8000104 + | ++32 + | ++RW + | ++0x000000 + | ++DDR PLL Control + | +
| + +DDR_PLL_CTRL + + | ++0XF8000104 + | ++32 + | ++RW + | ++0x000000 + | ++DDR PLL Control + | +
| + +DDR_CLK_CTRL + + | ++0XF8000124 + | ++32 + | ++RW + | ++0x000000 + | ++DDR Clock Control + | +
| + +IO_PLL_CFG + + | ++0XF8000118 + | ++32 + | ++RW + | ++0x000000 + | ++IO PLL Configuration + | +
| + +IO_PLL_CTRL + + | ++0XF8000108 + | ++32 + | ++RW + | ++0x000000 + | ++IO PLL Control + | +
| + +IO_PLL_CTRL + + | ++0XF8000108 + | ++32 + | ++RW + | ++0x000000 + | ++IO PLL Control + | +
| + +IO_PLL_CTRL + + | ++0XF8000108 + | ++32 + | ++RW + | ++0x000000 + | ++IO PLL Control + | +
| + +IO_PLL_CTRL + + | ++0XF8000108 + | ++32 + | ++RW + | ++0x000000 + | ++IO PLL Control + | +
| + +IO_PLL_CTRL + + | ++0XF8000108 + | ++32 + | ++RW + | ++0x000000 + | ++IO PLL Control + | +
| + +SLCR_LOCK + + | ++0XF8000004 + | ++32 + | ++WO + | ++0x000000 + | ++SLCR Write Protection Lock + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +SLCR_UNLOCK + | ++0XF8000008 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +UNLOCK_KEY + | ++15:0 + | ++ffff + | ++df0d + | ++df0d + | ++Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. + | +
| +SLCR_UNLOCK@0XF8000008 + | ++31:0 + | ++ffff + | ++ + | ++df0d + | ++SLCR Write Protection Unlock + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +ARM_PLL_CFG + | ++0XF8000110 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PLL_RES + | ++7:4 + | ++f0 + | ++2 + | ++20 + | ++Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control + | +
| +PLL_CP + | ++11:8 + | ++f00 + | ++2 + | ++200 + | ++Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control + | +
| +LOCK_CNT + | ++21:12 + | ++3ff000 + | ++fa + | ++fa000 + | ++Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. + | +
| +ARM_PLL_CFG@0XF8000110 + | ++31:0 + | ++3ffff0 + | ++ + | ++fa220 + | ++ARM PLL Configuration + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +ARM_PLL_CTRL + | ++0XF8000100 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PLL_FDIV + | ++18:12 + | ++7f000 + | ++28 + | ++28000 + | ++Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. + | +
| +ARM_PLL_CTRL@0XF8000100 + | ++31:0 + | ++7f000 + | ++ + | ++28000 + | ++ARM PLL Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +ARM_PLL_CTRL + | ++0XF8000100 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PLL_BYPASS_FORCE + | ++4:4 + | ++10 + | ++1 + | ++10 + | ++ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. + | +
| +ARM_PLL_CTRL@0XF8000100 + | ++31:0 + | ++10 + | ++ + | ++10 + | ++ARM PLL Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +ARM_PLL_CTRL + | ++0XF8000100 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PLL_RESET + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) + | +
| +ARM_PLL_CTRL@0XF8000100 + | ++31:0 + | ++1 + | ++ + | ++1 + | ++ARM PLL Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +ARM_PLL_CTRL + | ++0XF8000100 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PLL_RESET + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) + | +
| +ARM_PLL_CTRL@0XF8000100 + | ++31:0 + | ++1 + | ++ + | ++0 + | ++ARM PLL Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +PLL_STATUS + | ++0XF800010C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +ARM_PLL_LOCK + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++ARM PLL lock status: 0: not locked, 1: locked + | +
| +PLL_STATUS@0XF800010C + | ++31:0 + | ++1 + | ++ + | ++1 + | ++tobe + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +ARM_PLL_CTRL + | ++0XF8000100 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PLL_BYPASS_FORCE + | ++4:4 + | ++10 + | ++0 + | ++0 + | ++ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. + | +
| +ARM_PLL_CTRL@0XF8000100 + | ++31:0 + | ++10 + | ++ + | ++0 + | ++ARM PLL Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +ARM_CLK_CTRL + | ++0XF8000120 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +SRCSEL + | ++5:4 + | ++30 + | ++0 + | ++0 + | ++Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. + | +
| +DIVISOR + | ++13:8 + | ++3f00 + | ++2 + | ++200 + | ++Frequency divisor for the CPU clock source. + | +
| +CPU_6OR4XCLKACT + | ++24:24 + | ++1000000 + | ++1 + | ++1000000 + | ++CPU_6x4x Clock control: 0: disable, 1: enable + | +
| +CPU_3OR2XCLKACT + | ++25:25 + | ++2000000 + | ++1 + | ++2000000 + | ++CPU_3x2x Clock control: 0: disable, 1: enable + | +
| +CPU_2XCLKACT + | ++26:26 + | ++4000000 + | ++1 + | ++4000000 + | ++CPU_2x Clock control: 0: disable, 1: enable + | +
| +CPU_1XCLKACT + | ++27:27 + | ++8000000 + | ++1 + | ++8000000 + | ++CPU_1x Clock control: 0: disable, 1: enable + | +
| +CPU_PERI_CLKACT + | ++28:28 + | ++10000000 + | ++1 + | ++10000000 + | ++Clock active: 0: Clock is disabled 1: Clock is enabled + | +
| +ARM_CLK_CTRL@0XF8000120 + | ++31:0 + | ++1f003f30 + | ++ + | ++1f000200 + | ++CPU Clock Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDR_PLL_CFG + | ++0XF8000114 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PLL_RES + | ++7:4 + | ++f0 + | ++2 + | ++20 + | ++Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. + | +
| +PLL_CP + | ++11:8 + | ++f00 + | ++2 + | ++200 + | ++Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. + | +
| +LOCK_CNT + | ++21:12 + | ++3ff000 + | ++12c + | ++12c000 + | ++Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. + | +
| +DDR_PLL_CFG@0XF8000114 + | ++31:0 + | ++3ffff0 + | ++ + | ++12c220 + | ++DDR PLL Configuration + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDR_PLL_CTRL + | ++0XF8000104 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PLL_FDIV + | ++18:12 + | ++7f000 + | ++20 + | ++20000 + | ++Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. + | +
| +DDR_PLL_CTRL@0XF8000104 + | ++31:0 + | ++7f000 + | ++ + | ++20000 + | ++DDR PLL Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDR_PLL_CTRL + | ++0XF8000104 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PLL_BYPASS_FORCE + | ++4:4 + | ++10 + | ++1 + | ++10 + | ++DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. + | +
| +DDR_PLL_CTRL@0XF8000104 + | ++31:0 + | ++10 + | ++ + | ++10 + | ++DDR PLL Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDR_PLL_CTRL + | ++0XF8000104 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PLL_RESET + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) + | +
| +DDR_PLL_CTRL@0XF8000104 + | ++31:0 + | ++1 + | ++ + | ++1 + | ++DDR PLL Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDR_PLL_CTRL + | ++0XF8000104 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PLL_RESET + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) + | +
| +DDR_PLL_CTRL@0XF8000104 + | ++31:0 + | ++1 + | ++ + | ++0 + | ++DDR PLL Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +PLL_STATUS + | ++0XF800010C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +DDR_PLL_LOCK + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++DDR PLL lock status: 0: not locked, 1: locked + | +
| +PLL_STATUS@0XF800010C + | ++31:0 + | ++2 + | ++ + | ++2 + | ++tobe + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDR_PLL_CTRL + | ++0XF8000104 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PLL_BYPASS_FORCE + | ++4:4 + | ++10 + | ++0 + | ++0 + | ++DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. + | +
| +DDR_PLL_CTRL@0XF8000104 + | ++31:0 + | ++10 + | ++ + | ++0 + | ++DDR PLL Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDR_CLK_CTRL + | ++0XF8000124 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +DDR_3XCLKACT + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++DDR_3x Clock control: 0: disable, 1: enable + | +
| +DDR_2XCLKACT + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++DDR_2x Clock control: 0: disable, 1: enable + | +
| +DDR_3XCLK_DIVISOR + | ++25:20 + | ++3f00000 + | ++2 + | ++200000 + | ++Frequency divisor for the ddr_3x clock + | +
| +DDR_2XCLK_DIVISOR + | ++31:26 + | ++fc000000 + | ++3 + | ++c000000 + | ++Frequency divisor for the ddr_2x clock + | +
| +DDR_CLK_CTRL@0XF8000124 + | ++31:0 + | ++fff00003 + | ++ + | ++c200003 + | ++DDR Clock Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +IO_PLL_CFG + | ++0XF8000118 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PLL_RES + | ++7:4 + | ++f0 + | ++c + | ++c0 + | ++Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. + | +
| +PLL_CP + | ++11:8 + | ++f00 + | ++2 + | ++200 + | ++Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. + | +
| +LOCK_CNT + | ++21:12 + | ++3ff000 + | ++145 + | ++145000 + | ++Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. + | +
| +IO_PLL_CFG@0XF8000118 + | ++31:0 + | ++3ffff0 + | ++ + | ++1452c0 + | ++IO PLL Configuration + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +IO_PLL_CTRL + | ++0XF8000108 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PLL_FDIV + | ++18:12 + | ++7f000 + | ++1e + | ++1e000 + | ++Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. + | +
| +IO_PLL_CTRL@0XF8000108 + | ++31:0 + | ++7f000 + | ++ + | ++1e000 + | ++IO PLL Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +IO_PLL_CTRL + | ++0XF8000108 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PLL_BYPASS_FORCE + | ++4:4 + | ++10 + | ++1 + | ++10 + | ++IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. + | +
| +IO_PLL_CTRL@0XF8000108 + | ++31:0 + | ++10 + | ++ + | ++10 + | ++IO PLL Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +IO_PLL_CTRL + | ++0XF8000108 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PLL_RESET + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) + | +
| +IO_PLL_CTRL@0XF8000108 + | ++31:0 + | ++1 + | ++ + | ++1 + | ++IO PLL Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +IO_PLL_CTRL + | ++0XF8000108 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PLL_RESET + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) + | +
| +IO_PLL_CTRL@0XF8000108 + | ++31:0 + | ++1 + | ++ + | ++0 + | ++IO PLL Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +PLL_STATUS + | ++0XF800010C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +IO_PLL_LOCK + | ++2:2 + | ++4 + | ++1 + | ++4 + | ++IO PLL lock status: 0: not locked, 1: locked + | +
| +PLL_STATUS@0XF800010C + | ++31:0 + | ++4 + | ++ + | ++4 + | ++tobe + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +IO_PLL_CTRL + | ++0XF8000108 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PLL_BYPASS_FORCE + | ++4:4 + | ++10 + | ++0 + | ++0 + | ++IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. + | +
| +IO_PLL_CTRL@0XF8000108 + | ++31:0 + | ++10 + | ++ + | ++0 + | ++IO PLL Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +SLCR_LOCK + | ++0XF8000004 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +LOCK_KEY + | ++15:0 + | ++ffff + | ++767b + | ++767b + | ++Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. + | +
| +SLCR_LOCK@0XF8000004 + | ++31:0 + | ++ffff + | ++ + | ++767b + | ++SLCR Write Protection Lock + | +
+
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| + +SLCR_UNLOCK + + | ++0XF8000008 + | ++32 + | ++WO + | ++0x000000 + | ++SLCR Write Protection Unlock + | +
| + +DCI_CLK_CTRL + + | ++0XF8000128 + | ++32 + | ++RW + | ++0x000000 + | ++DCI clock control + | +
| + +GEM0_RCLK_CTRL + + | ++0XF8000138 + | ++32 + | ++RW + | ++0x000000 + | ++GigE 0 Rx Clock and Rx Signals Select + | +
| + +GEM0_CLK_CTRL + + | ++0XF8000140 + | ++32 + | ++RW + | ++0x000000 + | ++GigE 0 Ref Clock Control + | +
| + +LQSPI_CLK_CTRL + + | ++0XF800014C + | ++32 + | ++RW + | ++0x000000 + | ++Quad SPI Ref Clock Control + | +
| + +SDIO_CLK_CTRL + + | ++0XF8000150 + | ++32 + | ++RW + | ++0x000000 + | ++SDIO Ref Clock Control + | +
| + +UART_CLK_CTRL + + | ++0XF8000154 + | ++32 + | ++RW + | ++0x000000 + | ++UART Ref Clock Control + | +
| + +PCAP_CLK_CTRL + + | ++0XF8000168 + | ++32 + | ++RW + | ++0x000000 + | ++PCAP Clock Control + | +
| + +FPGA0_CLK_CTRL + + | ++0XF8000170 + | ++32 + | ++RW + | ++0x000000 + | ++PL Clock 0 Output control + | +
| + +FPGA1_CLK_CTRL + + | ++0XF8000180 + | ++32 + | ++RW + | ++0x000000 + | ++PL Clock 1 Output control + | +
| + +FPGA2_CLK_CTRL + + | ++0XF8000190 + | ++32 + | ++RW + | ++0x000000 + | ++PL Clock 2 output control + | +
| + +FPGA3_CLK_CTRL + + | ++0XF80001A0 + | ++32 + | ++RW + | ++0x000000 + | ++PL Clock 3 output control + | +
| + +CLK_621_TRUE + + | ++0XF80001C4 + | ++32 + | ++RW + | ++0x000000 + | ++CPU Clock Ratio Mode select + | +
| + +APER_CLK_CTRL + + | ++0XF800012C + | ++32 + | ++RW + | ++0x000000 + | ++AMBA Peripheral Clock Control + | +
| + +SLCR_LOCK + + | ++0XF8000004 + | ++32 + | ++WO + | ++0x000000 + | ++SLCR Write Protection Lock + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +SLCR_UNLOCK + | ++0XF8000008 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +UNLOCK_KEY + | ++15:0 + | ++ffff + | ++df0d + | ++df0d + | ++Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. + | +
| +SLCR_UNLOCK@0XF8000008 + | ++31:0 + | ++ffff + | ++ + | ++df0d + | ++SLCR Write Protection Unlock + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DCI_CLK_CTRL + | ++0XF8000128 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +CLKACT + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++DCI clock control - 0: disable, 1: enable + | +
| +DIVISOR0 + | ++13:8 + | ++3f00 + | ++23 + | ++2300 + | ++Provides the divisor used to divide the source clock to generate the required generated clock frequency. + | +
| +DIVISOR1 + | ++25:20 + | ++3f00000 + | ++3 + | ++300000 + | ++Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider + | +
| +DCI_CLK_CTRL@0XF8000128 + | ++31:0 + | ++3f03f01 + | ++ + | ++302301 + | ++DCI clock control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +GEM0_RCLK_CTRL + | ++0XF8000138 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +CLKACT + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Ethernet Controler 0 Rx Clock control 0: disable, 1: enable + | +
| +SRCSEL + | ++4:4 + | ++10 + | ++0 + | ++0 + | ++Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO + | +
| +GEM0_RCLK_CTRL@0XF8000138 + | ++31:0 + | ++11 + | ++ + | ++1 + | ++GigE 0 Rx Clock and Rx Signals Select + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +GEM0_CLK_CTRL + | ++0XF8000140 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +CLKACT + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Ethernet Controller 0 Reference Clock control 0: disable, 1: enable + | +
| +SRCSEL + | ++6:4 + | ++70 + | ++0 + | ++0 + | ++Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock + | +
| +DIVISOR + | ++13:8 + | ++3f00 + | ++8 + | ++800 + | ++First divisor for Ethernet controller 0 source clock. + | +
| +DIVISOR1 + | ++25:20 + | ++3f00000 + | ++1 + | ++100000 + | ++Second divisor for Ethernet controller 0 source clock. + | +
| +GEM0_CLK_CTRL@0XF8000140 + | ++31:0 + | ++3f03f71 + | ++ + | ++100801 + | ++GigE 0 Ref Clock Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +LQSPI_CLK_CTRL + | ++0XF800014C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +CLKACT + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Quad SPI Controller Reference Clock control 0: disable, 1: enable + | +
| +SRCSEL + | ++5:4 + | ++30 + | ++0 + | ++0 + | ++Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL + | +
| +DIVISOR + | ++13:8 + | ++3f00 + | ++5 + | ++500 + | ++Divisor for Quad SPI Controller source clock. + | +
| +LQSPI_CLK_CTRL@0XF800014C + | ++31:0 + | ++3f31 + | ++ + | ++501 + | ++Quad SPI Ref Clock Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +SDIO_CLK_CTRL + | ++0XF8000150 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +CLKACT0 + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++SDIO Controller 0 Clock control. 0: disable, 1: enable + | +
| +CLKACT1 + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++SDIO Controller 1 Clock control. 0: disable, 1: enable + | +
| +SRCSEL + | ++5:4 + | ++30 + | ++0 + | ++0 + | ++Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. + | +
| +DIVISOR + | ++13:8 + | ++3f00 + | ++14 + | ++1400 + | ++Provides the divisor used to divide the source clock to generate the required generated clock frequency. + | +
| +SDIO_CLK_CTRL@0XF8000150 + | ++31:0 + | ++3f33 + | ++ + | ++1401 + | ++SDIO Ref Clock Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +UART_CLK_CTRL + | ++0XF8000154 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +CLKACT0 + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++UART 0 Reference clock control. 0: disable, 1: enable + | +
| +CLKACT1 + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled + | +
| +SRCSEL + | ++5:4 + | ++30 + | ++0 + | ++0 + | ++Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL + | +
| +DIVISOR + | ++13:8 + | ++3f00 + | ++14 + | ++1400 + | ++Divisor for UART Controller source clock. + | +
| +UART_CLK_CTRL@0XF8000154 + | ++31:0 + | ++3f33 + | ++ + | ++1402 + | ++UART Ref Clock Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +PCAP_CLK_CTRL + | ++0XF8000168 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +CLKACT + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Clock active: 0: Clock is disabled 1: Clock is enabled + | +
| +SRCSEL + | ++5:4 + | ++30 + | ++0 + | ++0 + | ++Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. + | +
| +DIVISOR + | ++13:8 + | ++3f00 + | ++5 + | ++500 + | ++Provides the divisor used to divide the source clock to generate the required generated clock frequency. + | +
| +PCAP_CLK_CTRL@0XF8000168 + | ++31:0 + | ++3f31 + | ++ + | ++501 + | ++PCAP Clock Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +FPGA0_CLK_CTRL + | ++0XF8000170 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +SRCSEL + | ++5:4 + | ++30 + | ++0 + | ++0 + | ++Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. + | +
| +DIVISOR0 + | ++13:8 + | ++3f00 + | ++a + | ++a00 + | ++Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. + | +
| +DIVISOR1 + | ++25:20 + | ++3f00000 + | ++1 + | ++100000 + | ++Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide + | +
| +FPGA0_CLK_CTRL@0XF8000170 + | ++31:0 + | ++3f03f30 + | ++ + | ++100a00 + | ++PL Clock 0 Output control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +FPGA1_CLK_CTRL + | ++0XF8000180 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +SRCSEL + | ++5:4 + | ++30 + | ++0 + | ++0 + | ++Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. + | +
| +DIVISOR0 + | ++13:8 + | ++3f00 + | ++a + | ++a00 + | ++Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. + | +
| +DIVISOR1 + | ++25:20 + | ++3f00000 + | ++1 + | ++100000 + | ++Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide + | +
| +FPGA1_CLK_CTRL@0XF8000180 + | ++31:0 + | ++3f03f30 + | ++ + | ++100a00 + | ++PL Clock 1 Output control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +FPGA2_CLK_CTRL + | ++0XF8000190 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +SRCSEL + | ++5:4 + | ++30 + | ++0 + | ++0 + | ++Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. + | +
| +DIVISOR0 + | ++13:8 + | ++3f00 + | ++1e + | ++1e00 + | ++Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. + | +
| +DIVISOR1 + | ++25:20 + | ++3f00000 + | ++1 + | ++100000 + | ++Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide + | +
| +FPGA2_CLK_CTRL@0XF8000190 + | ++31:0 + | ++3f03f30 + | ++ + | ++101e00 + | ++PL Clock 2 output control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +FPGA3_CLK_CTRL + | ++0XF80001A0 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +SRCSEL + | ++5:4 + | ++30 + | ++0 + | ++0 + | ++Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. + | +
| +DIVISOR0 + | ++13:8 + | ++3f00 + | ++14 + | ++1400 + | ++Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. + | +
| +DIVISOR1 + | ++25:20 + | ++3f00000 + | ++1 + | ++100000 + | ++Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide + | +
| +FPGA3_CLK_CTRL@0XF80001A0 + | ++31:0 + | ++3f03f30 + | ++ + | ++101400 + | ++PL Clock 3 output control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +CLK_621_TRUE + | ++0XF80001C4 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +CLK_621_TRUE + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 + | +
| +CLK_621_TRUE@0XF80001C4 + | ++31:0 + | ++1 + | ++ + | ++1 + | ++CPU Clock Ratio Mode select + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +APER_CLK_CTRL + | ++0XF800012C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +DMA_CPU_2XCLKACT + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++DMA controller AMBA Clock control 0: disable, 1: enable + | +
| +USB0_CPU_1XCLKACT + | ++2:2 + | ++4 + | ++1 + | ++4 + | ++USB controller 0 AMBA Clock control 0: disable, 1: enable + | +
| +USB1_CPU_1XCLKACT + | ++3:3 + | ++8 + | ++1 + | ++8 + | ++USB controller 1 AMBA Clock control 0: disable, 1: enable + | +
| +GEM0_CPU_1XCLKACT + | ++6:6 + | ++40 + | ++1 + | ++40 + | ++Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable + | +
| +GEM1_CPU_1XCLKACT + | ++7:7 + | ++80 + | ++0 + | ++0 + | ++Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable + | +
| +SDI0_CPU_1XCLKACT + | ++10:10 + | ++400 + | ++1 + | ++400 + | ++SDIO controller 0 AMBA Clock 0: disable, 1: enable + | +
| +SDI1_CPU_1XCLKACT + | ++11:11 + | ++800 + | ++0 + | ++0 + | ++SDIO controller 1 AMBA Clock control 0: disable, 1: enable + | +
| +SPI0_CPU_1XCLKACT + | ++14:14 + | ++4000 + | ++0 + | ++0 + | ++SPI 0 AMBA Clock control 0: disable, 1: enable + | +
| +SPI1_CPU_1XCLKACT + | ++15:15 + | ++8000 + | ++0 + | ++0 + | ++SPI 1 AMBA Clock control 0: disable, 1: enable + | +
| +CAN0_CPU_1XCLKACT + | ++16:16 + | ++10000 + | ++0 + | ++0 + | ++CAN 0 AMBA Clock control 0: disable, 1: enable + | +
| +CAN1_CPU_1XCLKACT + | ++17:17 + | ++20000 + | ++0 + | ++0 + | ++CAN 1 AMBA Clock control 0: disable, 1: enable + | +
| +I2C0_CPU_1XCLKACT + | ++18:18 + | ++40000 + | ++1 + | ++40000 + | ++I2C 0 AMBA Clock control 0: disable, 1: enable + | +
| +I2C1_CPU_1XCLKACT + | ++19:19 + | ++80000 + | ++1 + | ++80000 + | ++I2C 1 AMBA Clock control 0: disable, 1: enable + | +
| +UART0_CPU_1XCLKACT + | ++20:20 + | ++100000 + | ++0 + | ++0 + | ++UART 0 AMBA Clock control 0: disable, 1: enable + | +
| +UART1_CPU_1XCLKACT + | ++21:21 + | ++200000 + | ++1 + | ++200000 + | ++UART 1 AMBA Clock control 0: disable, 1: enable + | +
| +GPIO_CPU_1XCLKACT + | ++22:22 + | ++400000 + | ++1 + | ++400000 + | ++GPIO AMBA Clock control 0: disable, 1: enable + | +
| +LQSPI_CPU_1XCLKACT + | ++23:23 + | ++800000 + | ++1 + | ++800000 + | ++Quad SPI AMBA Clock control 0: disable, 1: enable + | +
| +SMC_CPU_1XCLKACT + | ++24:24 + | ++1000000 + | ++1 + | ++1000000 + | ++SMC AMBA Clock control 0: disable, 1: enable + | +
| +APER_CLK_CTRL@0XF800012C + | ++31:0 + | ++1ffcccd + | ++ + | ++1ec044d + | ++AMBA Peripheral Clock Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +SLCR_LOCK + | ++0XF8000004 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +LOCK_KEY + | ++15:0 + | ++ffff + | ++767b + | ++767b + | ++Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. + | +
| +SLCR_LOCK@0XF8000004 + | ++31:0 + | ++ffff + | ++ + | ++767b + | ++SLCR Write Protection Lock + | +
+
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| + +ddrc_ctrl + + | ++0XF8006000 + | ++32 + | ++RW + | ++0x000000 + | ++DDRC Control + | +
| + +Two_rank_cfg + + | ++0XF8006004 + | ++32 + | ++RW + | ++0x000000 + | ++Two Rank Configuration + | +
| + +HPR_reg + + | ++0XF8006008 + | ++32 + | ++RW + | ++0x000000 + | ++HPR Queue control + | +
| + +LPR_reg + + | ++0XF800600C + | ++32 + | ++RW + | ++0x000000 + | ++LPR Queue control + | +
| + +WR_reg + + | ++0XF8006010 + | ++32 + | ++RW + | ++0x000000 + | ++WR Queue control + | +
| + +DRAM_param_reg0 + + | ++0XF8006014 + | ++32 + | ++RW + | ++0x000000 + | ++DRAM Parameters 0 + | +
| + +DRAM_param_reg1 + + | ++0XF8006018 + | ++32 + | ++RW + | ++0x000000 + | ++DRAM Parameters 1 + | +
| + +DRAM_param_reg2 + + | ++0XF800601C + | ++32 + | ++RW + | ++0x000000 + | ++DRAM Parameters 2 + | +
| + +DRAM_param_reg3 + + | ++0XF8006020 + | ++32 + | ++RW + | ++0x000000 + | ++DRAM Parameters 3 + | +
| + +DRAM_param_reg4 + + | ++0XF8006024 + | ++32 + | ++RW + | ++0x000000 + | ++DRAM Parameters 4 + | +
| + +DRAM_init_param + + | ++0XF8006028 + | ++32 + | ++RW + | ++0x000000 + | ++DRAM Initialization Parameters + | +
| + +DRAM_EMR_reg + + | ++0XF800602C + | ++32 + | ++RW + | ++0x000000 + | ++DRAM EMR2, EMR3 access + | +
| + +DRAM_EMR_MR_reg + + | ++0XF8006030 + | ++32 + | ++RW + | ++0x000000 + | ++DRAM EMR, MR access + | +
| + +DRAM_burst8_rdwr + + | ++0XF8006034 + | ++32 + | ++RW + | ++0x000000 + | ++DRAM Burst 8 read/write + | +
| + +DRAM_disable_DQ + + | ++0XF8006038 + | ++32 + | ++RW + | ++0x000000 + | ++DRAM Disable DQ + | +
| + +DRAM_addr_map_bank + + | ++0XF800603C + | ++32 + | ++RW + | ++0x000000 + | ++Row/Column address bits + | +
| + +DRAM_addr_map_col + + | ++0XF8006040 + | ++32 + | ++RW + | ++0x000000 + | ++Column address bits + | +
| + +DRAM_addr_map_row + + | ++0XF8006044 + | ++32 + | ++RW + | ++0x000000 + | ++Select DRAM row address bits + | +
| + +DRAM_ODT_reg + + | ++0XF8006048 + | ++32 + | ++RW + | ++0x000000 + | ++DRAM ODT control + | +
| + +phy_cmd_timeout_rddata_cpt + + | ++0XF8006050 + | ++32 + | ++RW + | ++0x000000 + | ++PHY command time out and read data capture FIFO + | +
| + +DLL_calib + + | ++0XF8006058 + | ++32 + | ++RW + | ++0x000000 + | ++DLL calibration + | +
| + +ODT_delay_hold + + | ++0XF800605C + | ++32 + | ++RW + | ++0x000000 + | ++ODT delay and ODT hold + | +
| + +ctrl_reg1 + + | ++0XF8006060 + | ++32 + | ++RW + | ++0x000000 + | ++Controller 1 + | +
| + +ctrl_reg2 + + | ++0XF8006064 + | ++32 + | ++RW + | ++0x000000 + | ++Controller 2 + | +
| + +ctrl_reg3 + + | ++0XF8006068 + | ++32 + | ++RW + | ++0x000000 + | ++Controller 3 + | +
| + +ctrl_reg4 + + | ++0XF800606C + | ++32 + | ++RW + | ++0x000000 + | ++Controller 4 + | +
| + +ctrl_reg5 + + | ++0XF8006078 + | ++32 + | ++RW + | ++0x000000 + | ++Controller register 5 + | +
| + +ctrl_reg6 + + | ++0XF800607C + | ++32 + | ++RW + | ++0x000000 + | ++Controller register 6 + | +
| + +CHE_T_ZQ + + | ++0XF80060A4 + | ++32 + | ++RW + | ++0x000000 + | ++ZQ parameters + | +
| + +CHE_T_ZQ_Short_Interval_Reg + + | ++0XF80060A8 + | ++32 + | ++RW + | ++0x000000 + | ++Misc parameters + | +
| + +deep_pwrdwn_reg + + | ++0XF80060AC + | ++32 + | ++RW + | ++0x000000 + | ++Deep powerdown (LPDDR2) + | +
| + +reg_2c + + | ++0XF80060B0 + | ++32 + | ++RW + | ++0x000000 + | ++Training control + | +
| + +reg_2d + + | ++0XF80060B4 + | ++32 + | ++RW + | ++0x000000 + | ++Misc Debug + | +
| + +dfi_timing + + | ++0XF80060B8 + | ++32 + | ++RW + | ++0x000000 + | ++DFI timing + | +
| + +CHE_ECC_CONTROL_REG_OFFSET + + | ++0XF80060C4 + | ++32 + | ++RW + | ++0x000000 + | ++ECC error clear + | +
| + +CHE_ECC_CONTROL_REG_OFFSET + + | ++0XF80060C4 + | ++32 + | ++RW + | ++0x000000 + | ++ECC error clear + | +
| + +CHE_CORR_ECC_LOG_REG_OFFSET + + | ++0XF80060C8 + | ++32 + | ++RW + | ++0x000000 + | ++ECC error correction + | +
| + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + | ++0XF80060DC + | ++32 + | ++RW + | ++0x000000 + | ++ECC unrecoverable error status + | +
| + +CHE_ECC_STATS_REG_OFFSET + + | ++0XF80060F0 + | ++32 + | ++RW + | ++0x000000 + | ++ECC error count + | +
| + +ECC_scrub + + | ++0XF80060F4 + | ++32 + | ++RW + | ++0x000000 + | ++ECC mode/scrub + | +
| + +phy_rcvr_enable + + | ++0XF8006114 + | ++32 + | ++RW + | ++0x000000 + | ++Phy receiver enable register + | +
| + +PHY_Config + + | ++0XF8006118 + | ++32 + | ++RW + | ++0x000000 + | ++PHY configuration register for data slice 0. + | +
| + +PHY_Config + + | ++0XF800611C + | ++32 + | ++RW + | ++0x000000 + | ++PHY configuration register for data slice 0. + | +
| + +PHY_Config + + | ++0XF8006120 + | ++32 + | ++RW + | ++0x000000 + | ++PHY configuration register for data slice 0. + | +
| + +PHY_Config + + | ++0XF8006124 + | ++32 + | ++RW + | ++0x000000 + | ++PHY configuration register for data slice 0. + | +
| + +phy_init_ratio + + | ++0XF800612C + | ++32 + | ++RW + | ++0x000000 + | ++PHY init ratio register for data slice 0. + | +
| + +phy_init_ratio + + | ++0XF8006130 + | ++32 + | ++RW + | ++0x000000 + | ++PHY init ratio register for data slice 0. + | +
| + +phy_init_ratio + + | ++0XF8006134 + | ++32 + | ++RW + | ++0x000000 + | ++PHY init ratio register for data slice 0. + | +
| + +phy_init_ratio + + | ++0XF8006138 + | ++32 + | ++RW + | ++0x000000 + | ++PHY init ratio register for data slice 0. + | +
| + +phy_rd_dqs_cfg + + | ++0XF8006140 + | ++32 + | ++RW + | ++0x000000 + | ++PHY read DQS configuration register for data slice 0. + | +
| + +phy_rd_dqs_cfg + + | ++0XF8006144 + | ++32 + | ++RW + | ++0x000000 + | ++PHY read DQS configuration register for data slice 0. + | +
| + +phy_rd_dqs_cfg + + | ++0XF8006148 + | ++32 + | ++RW + | ++0x000000 + | ++PHY read DQS configuration register for data slice 0. + | +
| + +phy_rd_dqs_cfg + + | ++0XF800614C + | ++32 + | ++RW + | ++0x000000 + | ++PHY read DQS configuration register for data slice 0. + | +
| + +phy_wr_dqs_cfg + + | ++0XF8006154 + | ++32 + | ++RW + | ++0x000000 + | ++PHY write DQS configuration register for data slice 0. + | +
| + +phy_wr_dqs_cfg + + | ++0XF8006158 + | ++32 + | ++RW + | ++0x000000 + | ++PHY write DQS configuration register for data slice 0. + | +
| + +phy_wr_dqs_cfg + + | ++0XF800615C + | ++32 + | ++RW + | ++0x000000 + | ++PHY write DQS configuration register for data slice 0. + | +
| + +phy_wr_dqs_cfg + + | ++0XF8006160 + | ++32 + | ++RW + | ++0x000000 + | ++PHY write DQS configuration register for data slice 0. + | +
| + +phy_we_cfg + + | ++0XF8006168 + | ++32 + | ++RW + | ++0x000000 + | ++PHY FIFO write enable configuration for data slice 0. + | +
| + +phy_we_cfg + + | ++0XF800616C + | ++32 + | ++RW + | ++0x000000 + | ++PHY FIFO write enable configuration for data slice 0. + | +
| + +phy_we_cfg + + | ++0XF8006170 + | ++32 + | ++RW + | ++0x000000 + | ++PHY FIFO write enable configuration for data slice 0. + | +
| + +phy_we_cfg + + | ++0XF8006174 + | ++32 + | ++RW + | ++0x000000 + | ++PHY FIFO write enable configuration for data slice 0. + | +
| + +wr_data_slv + + | ++0XF800617C + | ++32 + | ++RW + | ++0x000000 + | ++PHY write data slave ratio config for data slice 0. + | +
| + +wr_data_slv + + | ++0XF8006180 + | ++32 + | ++RW + | ++0x000000 + | ++PHY write data slave ratio config for data slice 0. + | +
| + +wr_data_slv + + | ++0XF8006184 + | ++32 + | ++RW + | ++0x000000 + | ++PHY write data slave ratio config for data slice 0. + | +
| + +wr_data_slv + + | ++0XF8006188 + | ++32 + | ++RW + | ++0x000000 + | ++PHY write data slave ratio config for data slice 0. + | +
| + +reg_64 + + | ++0XF8006190 + | ++32 + | ++RW + | ++0x000000 + | ++Training control 2 + | +
| + +reg_65 + + | ++0XF8006194 + | ++32 + | ++RW + | ++0x000000 + | ++Training control 3 + | +
| + +page_mask + + | ++0XF8006204 + | ++32 + | ++RW + | ++0x000000 + | ++Page mask + | +
| + +axi_priority_wr_port + + | ++0XF8006208 + | ++32 + | ++RW + | ++0x000000 + | ++AXI Priority control for write port 0. + | +
| + +axi_priority_wr_port + + | ++0XF800620C + | ++32 + | ++RW + | ++0x000000 + | ++AXI Priority control for write port 0. + | +
| + +axi_priority_wr_port + + | ++0XF8006210 + | ++32 + | ++RW + | ++0x000000 + | ++AXI Priority control for write port 0. + | +
| + +axi_priority_wr_port + + | ++0XF8006214 + | ++32 + | ++RW + | ++0x000000 + | ++AXI Priority control for write port 0. + | +
| + +axi_priority_rd_port + + | ++0XF8006218 + | ++32 + | ++RW + | ++0x000000 + | ++AXI Priority control for read port 0. + | +
| + +axi_priority_rd_port + + | ++0XF800621C + | ++32 + | ++RW + | ++0x000000 + | ++AXI Priority control for read port 0. + | +
| + +axi_priority_rd_port + + | ++0XF8006220 + | ++32 + | ++RW + | ++0x000000 + | ++AXI Priority control for read port 0. + | +
| + +axi_priority_rd_port + + | ++0XF8006224 + | ++32 + | ++RW + | ++0x000000 + | ++AXI Priority control for read port 0. + | +
| + +lpddr_ctrl0 + + | ++0XF80062A8 + | ++32 + | ++RW + | ++0x000000 + | ++LPDDR2 Control 0 + | +
| + +lpddr_ctrl1 + + | ++0XF80062AC + | ++32 + | ++RW + | ++0x000000 + | ++LPDDR2 Control 1 + | +
| + +lpddr_ctrl2 + + | ++0XF80062B0 + | ++32 + | ++RW + | ++0x000000 + | ++LPDDR2 Control 2 + | +
| + +lpddr_ctrl3 + + | ++0XF80062B4 + | ++32 + | ++RW + | ++0x000000 + | ++LPDDR2 Control 3 + | +
| + +ddrc_ctrl + + | ++0XF8006000 + | ++32 + | ++RW + | ++0x000000 + | ++DDRC Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +ddrc_ctrl + | ++0XF8006000 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_soft_rstb + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. + | +
| +reg_ddrc_powerdown_en + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable + | +
| +reg_ddrc_data_bus_width + | ++3:2 + | ++c + | ++0 + | ++0 + | ++DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved + | +
| +reg_ddrc_burst8_refresh + | ++6:4 + | ++70 + | ++0 + | ++0 + | ++Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh + | +
| +reg_ddrc_rdwr_idle_gap + | ++13:7 + | ++3f80 + | ++1 + | ++80 + | ++When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. + | +
| +reg_ddrc_dis_rd_bypass + | ++14:14 + | ++4000 + | ++0 + | ++0 + | ++Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. + | +
| +reg_ddrc_dis_act_bypass + | ++15:15 + | ++8000 + | ++0 + | ++0 + | ++Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. + | +
| +reg_ddrc_dis_auto_refresh + | ++16:16 + | ++10000 + | ++0 + | ++0 + | ++Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. + | +
| +ddrc_ctrl@0XF8006000 + | ++31:0 + | ++1ffff + | ++ + | ++80 + | ++DDRC Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +Two_rank_cfg + | ++0XF8006004 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_t_rfc_nom_x32 + | ++11:0 + | ++fff + | ++81 + | ++81 + | ++tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. + | +
| +reserved_reg_ddrc_active_ranks + | ++13:12 + | ++3000 + | ++1 + | ++1000 + | ++Reserved. Do not modify. + | +
| +reg_ddrc_addrmap_cs_bit0 + | ++18:14 + | ++7c000 + | ++0 + | ++0 + | ++Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. + | +
| +Two_rank_cfg@0XF8006004 + | ++31:0 + | ++7ffff + | ++ + | ++1081 + | ++Two Rank Configuration + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +HPR_reg + | ++0XF8006008 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_hpr_min_non_critical_x32 + | ++10:0 + | ++7ff + | ++f + | ++f + | ++Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). + | +
| +reg_ddrc_hpr_max_starve_x32 + | ++21:11 + | ++3ff800 + | ++f + | ++7800 + | ++Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks + | +
| +reg_ddrc_hpr_xact_run_length + | ++25:22 + | ++3c00000 + | ++f + | ++3c00000 + | ++Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. + | +
| +HPR_reg@0XF8006008 + | ++31:0 + | ++3ffffff + | ++ + | ++3c0780f + | ++HPR Queue control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +LPR_reg + | ++0XF800600C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_lpr_min_non_critical_x32 + | ++10:0 + | ++7ff + | ++1 + | ++1 + | ++Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks + | +
| +reg_ddrc_lpr_max_starve_x32 + | ++21:11 + | ++3ff800 + | ++2 + | ++1000 + | ++Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks + | +
| +reg_ddrc_lpr_xact_run_length + | ++25:22 + | ++3c00000 + | ++8 + | ++2000000 + | ++Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available + | +
| +LPR_reg@0XF800600C + | ++31:0 + | ++3ffffff + | ++ + | ++2001001 + | ++LPR Queue control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +WR_reg + | ++0XF8006010 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_w_min_non_critical_x32 + | ++10:0 + | ++7ff + | ++1 + | ++1 + | ++Number of clock cycles that the WR queue is guaranteed to be non-critical. + | +
| +reg_ddrc_w_xact_run_length + | ++14:11 + | ++7800 + | ++8 + | ++4000 + | ++Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available + | +
| +reg_ddrc_w_max_starve_x32 + | ++25:15 + | ++3ff8000 + | ++2 + | ++10000 + | ++Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. + | +
| +WR_reg@0XF8006010 + | ++31:0 + | ++3ffffff + | ++ + | ++14001 + | ++WR Queue control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DRAM_param_reg0 + | ++0XF8006014 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_t_rc + | ++5:0 + | ++3f + | ++1a + | ++1a + | ++tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. + | +
| +reg_ddrc_t_rfc_min + | ++13:6 + | ++3fc0 + | ++a0 + | ++2800 + | ++tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. + | +
| +reg_ddrc_post_selfref_gap_x32 + | ++20:14 + | ++1fc000 + | ++10 + | ++40000 + | ++Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related + | +
| +DRAM_param_reg0@0XF8006014 + | ++31:0 + | ++1fffff + | ++ + | ++4281a + | ++DRAM Parameters 0 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DRAM_param_reg1 + | ++0XF8006018 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_wr2pre + | ++4:0 + | ++1f + | ++12 + | ++12 + | ++Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. + | +
| +reg_ddrc_powerdown_to_x32 + | ++9:5 + | ++3e0 + | ++6 + | ++c0 + | ++After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. + | +
| +reg_ddrc_t_faw + | ++15:10 + | ++fc00 + | ++16 + | ++5800 + | ++tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. + | +
| +reg_ddrc_t_ras_max + | ++21:16 + | ++3f0000 + | ++24 + | ++240000 + | ++tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. + | +
| +reg_ddrc_t_ras_min + | ++26:22 + | ++7c00000 + | ++13 + | ++4c00000 + | ++tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. + | +
| +reg_ddrc_t_cke + | ++31:28 + | ++f0000000 + | ++4 + | ++40000000 + | ++Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. + | +
| +DRAM_param_reg1@0XF8006018 + | ++31:0 + | ++f7ffffff + | ++ + | ++44e458d2 + | ++DRAM Parameters 1 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DRAM_param_reg2 + | ++0XF800601C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_write_latency + | ++4:0 + | ++1f + | ++5 + | ++5 + | ++Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 + | +
| +reg_ddrc_rd2wr + | ++9:5 + | ++3e0 + | ++7 + | ++e0 + | ++Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. + | +
| +reg_ddrc_wr2rd + | ++14:10 + | ++7c00 + | ++e + | ++3800 + | ++Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. + | +
| +reg_ddrc_t_xp + | ++19:15 + | ++f8000 + | ++4 + | ++20000 + | ++tXP: Minimum time after power down exit to any operation. DRAM related. + | +
| +reg_ddrc_pad_pd + | ++22:20 + | ++700000 + | ++0 + | ++0 + | ++If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. + | +
| +reg_ddrc_rd2pre + | ++27:23 + | ++f800000 + | ++4 + | ++2000000 + | ++Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. + | +
| +reg_ddrc_t_rcd + | ++31:28 + | ++f0000000 + | ++7 + | ++70000000 + | ++tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. + | +
| +DRAM_param_reg2@0XF800601C + | ++31:0 + | ++ffffffff + | ++ + | ++720238e5 + | ++DRAM Parameters 2 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DRAM_param_reg3 + | ++0XF8006020 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_t_ccd + | ++4:2 + | ++1c + | ++4 + | ++10 + | ++tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. + | +
| +reg_ddrc_t_rrd + | ++7:5 + | ++e0 + | ++6 + | ++c0 + | ++tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED + | +
| +reg_ddrc_refresh_margin + | ++11:8 + | ++f00 + | ++2 + | ++200 + | ++Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. + | +
| +reg_ddrc_t_rp + | ++15:12 + | ++f000 + | ++7 + | ++7000 + | ++tRP - Minimum time from precharge to activate of same bank. DRAM RELATED + | +
| +reg_ddrc_refresh_to_x32 + | ++20:16 + | ++1f0000 + | ++8 + | ++80000 + | ++If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. + | +
| +reg_ddrc_mobile + | ++22:22 + | ++400000 + | ++0 + | ++0 + | ++0: DDR2 or DDR3 device. 1: LPDDR2 device. + | +
| +reg_ddrc_en_dfi_dram_clk_disable + | ++23:23 + | ++800000 + | ++0 + | ++0 + | ++Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down + | +
| +reg_ddrc_read_latency + | ++28:24 + | ++1f000000 + | ++7 + | ++7000000 + | ++Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. + | +
| +reg_phy_mode_ddr1_ddr2 + | ++29:29 + | ++20000000 + | ++1 + | ++20000000 + | ++unused + | +
| +reg_ddrc_dis_pad_pd + | ++30:30 + | ++40000000 + | ++0 + | ++0 + | ++1: disable the pad power down feature 0: Enable the pad power down feature. + | +
| +DRAM_param_reg3@0XF8006020 + | ++31:0 + | ++7fdffffc + | ++ + | ++270872d0 + | ++DRAM Parameters 3 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DRAM_param_reg4 + | ++0XF8006024 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_en_2t_timing_mode + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++1: DDRC will use 2T timing 0: DDRC will use 1T timing + | +
| +reg_ddrc_prefer_write + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++1: Bank selector prefers writes over reads + | +
| +reg_ddrc_mr_wr + | ++6:6 + | ++40 + | ++0 + | ++0 + | ++A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. + | +
| +reg_ddrc_mr_addr + | ++8:7 + | ++180 + | ++0 + | ++0 + | ++DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 + | +
| +reg_ddrc_mr_data + | ++24:9 + | ++1fffe00 + | ++0 + | ++0 + | ++DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. + | +
| +ddrc_reg_mr_wr_busy + | ++25:25 + | ++2000000 + | ++0 + | ++0 + | ++Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. + | +
| +reg_ddrc_mr_type + | ++26:26 + | ++4000000 + | ++0 + | ++0 + | ++Indicates whether the Mode register operation is read or write 0: write 1: read + | +
| +reg_ddrc_mr_rdata_valid + | ++27:27 + | ++8000000 + | ++0 + | ++0 + | ++This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. + | +
| +DRAM_param_reg4@0XF8006024 + | ++31:0 + | ++fffffc3 + | ++ + | ++0 + | ++DRAM Parameters 4 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DRAM_init_param + | ++0XF8006028 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_final_wait_x32 + | ++6:0 + | ++7f + | ++7 + | ++7 + | ++Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. + | +
| +reg_ddrc_pre_ocd_x32 + | ++10:7 + | ++780 + | ++0 + | ++0 + | ++Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. + | +
| +reg_ddrc_t_mrd + | ++13:11 + | ++3800 + | ++4 + | ++2000 + | ++tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. + | +
| +DRAM_init_param@0XF8006028 + | ++31:0 + | ++3fff + | ++ + | ++2007 + | ++DRAM Initialization Parameters + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DRAM_EMR_reg + | ++0XF800602C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_emr2 + | ++15:0 + | ++ffff + | ++8 + | ++8 + | ++DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register + | +
| +reg_ddrc_emr3 + | ++31:16 + | ++ffff0000 + | ++0 + | ++0 + | ++DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused + | +
| +DRAM_EMR_reg@0XF800602C + | ++31:0 + | ++ffffffff + | ++ + | ++8 + | ++DRAM EMR2, EMR3 access + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DRAM_EMR_MR_reg + | ++0XF8006030 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_mr + | ++15:0 + | ++ffff + | ++930 + | ++930 + | ++DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register + | +
| +reg_ddrc_emr + | ++31:16 + | ++ffff0000 + | ++4 + | ++40000 + | ++DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register + | +
| +DRAM_EMR_MR_reg@0XF8006030 + | ++31:0 + | ++ffffffff + | ++ + | ++40930 + | ++DRAM EMR, MR access + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DRAM_burst8_rdwr + | ++0XF8006034 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_burst_rdwr + | ++3:0 + | ++f + | ++4 + | ++4 + | ++Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved + | +
| +reg_ddrc_pre_cke_x1024 + | ++13:4 + | ++3ff0 + | ++105 + | ++1050 + | ++Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) + | +
| +reg_ddrc_post_cke_x1024 + | ++25:16 + | ++3ff0000 + | ++1 + | ++10000 + | ++Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. + | +
| +reg_ddrc_burstchop + | ++28:28 + | ++10000000 + | ++0 + | ++0 + | ++Feature not supported. When 1, Controller is out in burstchop mode. + | +
| +DRAM_burst8_rdwr@0XF8006034 + | ++31:0 + | ++13ff3fff + | ++ + | ++11054 + | ++DRAM Burst 8 read/write + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DRAM_disable_DQ + | ++0XF8006038 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_force_low_pri_n + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. + | +
| +reg_ddrc_dis_dq + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. + | +
| +DRAM_disable_DQ@0XF8006038 + | ++31:0 + | ++3 + | ++ + | ++0 + | ++DRAM Disable DQ + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DRAM_addr_map_bank + | ++0XF800603C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_addrmap_bank_b0 + | ++3:0 + | ++f + | ++7 + | ++7 + | ++Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. + | +
| +reg_ddrc_addrmap_bank_b1 + | ++7:4 + | ++f0 + | ++7 + | ++70 + | ++Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. + | +
| +reg_ddrc_addrmap_bank_b2 + | ++11:8 + | ++f00 + | ++7 + | ++700 + | ++Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. + | +
| +reg_ddrc_addrmap_col_b5 + | ++15:12 + | ++f000 + | ++0 + | ++0 + | ++Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. + | +
| +reg_ddrc_addrmap_col_b6 + | ++19:16 + | ++f0000 + | ++0 + | ++0 + | ++Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. + | +
| +DRAM_addr_map_bank@0XF800603C + | ++31:0 + | ++fffff + | ++ + | ++777 + | ++Row/Column address bits + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DRAM_addr_map_col + | ++0XF8006040 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_addrmap_col_b2 + | ++3:0 + | ++f + | ++0 + | ++0 + | ++Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. + | +
| +reg_ddrc_addrmap_col_b3 + | ++7:4 + | ++f0 + | ++0 + | ++0 + | ++Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. + | +
| +reg_ddrc_addrmap_col_b4 + | ++11:8 + | ++f00 + | ++0 + | ++0 + | ++Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. + | +
| +reg_ddrc_addrmap_col_b7 + | ++15:12 + | ++f000 + | ++0 + | ++0 + | ++Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. + | +
| +reg_ddrc_addrmap_col_b8 + | ++19:16 + | ++f0000 + | ++0 + | ++0 + | ++Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. + | +
| +reg_ddrc_addrmap_col_b9 + | ++23:20 + | ++f00000 + | ++f + | ++f00000 + | ++Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. + | +
| +reg_ddrc_addrmap_col_b10 + | ++27:24 + | ++f000000 + | ++f + | ++f000000 + | ++Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. + | +
| +reg_ddrc_addrmap_col_b11 + | ++31:28 + | ++f0000000 + | ++f + | ++f0000000 + | ++Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. + | +
| +DRAM_addr_map_col@0XF8006040 + | ++31:0 + | ++ffffffff + | ++ + | ++fff00000 + | ++Column address bits + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DRAM_addr_map_row + | ++0XF8006044 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_addrmap_row_b0 + | ++3:0 + | ++f + | ++6 + | ++6 + | ++Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field + | +
| +reg_ddrc_addrmap_row_b1 + | ++7:4 + | ++f0 + | ++6 + | ++60 + | ++Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. + | +
| +reg_ddrc_addrmap_row_b2_11 + | ++11:8 + | ++f00 + | ++6 + | ++600 + | ++Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. + | +
| +reg_ddrc_addrmap_row_b12 + | ++15:12 + | ++f000 + | ++6 + | ++6000 + | ++Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. + | +
| +reg_ddrc_addrmap_row_b13 + | ++19:16 + | ++f0000 + | ++6 + | ++60000 + | ++Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. + | +
| +reg_ddrc_addrmap_row_b14 + | ++23:20 + | ++f00000 + | ++6 + | ++600000 + | ++Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. + | +
| +reg_ddrc_addrmap_row_b15 + | ++27:24 + | ++f000000 + | ++f + | ++f000000 + | ++Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. + | +
| +DRAM_addr_map_row@0XF8006044 + | ++31:0 + | ++fffffff + | ++ + | ++f666666 + | ++Select DRAM row address bits + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DRAM_ODT_reg + | ++0XF8006048 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_rd_local_odt + | ++13:12 + | ++3000 + | ++0 + | ++0 + | ++Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. + | +
| +reg_phy_wr_local_odt + | ++15:14 + | ++c000 + | ++3 + | ++c000 + | ++Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. + | +
| +reg_phy_idle_local_odt + | ++17:16 + | ++30000 + | ++3 + | ++30000 + | ++Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. + | +
| +DRAM_ODT_reg@0XF8006048 + | ++31:0 + | ++3f000 + | ++ + | ++3c000 + | ++DRAM ODT control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +phy_cmd_timeout_rddata_cpt + | ++0XF8006050 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_rd_cmd_to_data + | ++3:0 + | ++f + | ++0 + | ++0 + | ++Not used in DFI PHY. + | +
| +reg_phy_wr_cmd_to_data + | ++7:4 + | ++f0 + | ++0 + | ++0 + | ++Not used in DFI PHY. + | +
| +reg_phy_rdc_we_to_re_delay + | ++11:8 + | ++f00 + | ++8 + | ++800 + | ++This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. + | +
| +reg_phy_rdc_fifo_rst_disable + | ++15:15 + | ++8000 + | ++0 + | ++0 + | ++When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. + | +
| +reg_phy_use_fixed_re + | ++16:16 + | ++10000 + | ++1 + | ++10000 + | ++When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. + | +
| +reg_phy_rdc_fifo_rst_err_cnt_clr + | ++17:17 + | ++20000 + | ++0 + | ++0 + | ++Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. + | +
| +reg_phy_dis_phy_ctrl_rstn + | ++18:18 + | ++40000 + | ++0 + | ++0 + | ++Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. + | +
| +reg_phy_clk_stall_level + | ++19:19 + | ++80000 + | ++0 + | ++0 + | ++1: stall clock, for DLL aging control + | +
| +reg_phy_gatelvl_num_of_dq0 + | ++27:24 + | ++f000000 + | ++7 + | ++7000000 + | ++This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. + | +
| +reg_phy_wrlvl_num_of_dq0 + | ++31:28 + | ++f0000000 + | ++7 + | ++70000000 + | ++This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. + | +
| +phy_cmd_timeout_rddata_cpt@0XF8006050 + | ++31:0 + | ++ff0f8fff + | ++ + | ++77010800 + | ++PHY command time out and read data capture FIFO + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DLL_calib + | ++0XF8006058 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_dis_dll_calib + | ++16:16 + | ++10000 + | ++0 + | ++0 + | ++When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically + | +
| +DLL_calib@0XF8006058 + | ++31:0 + | ++10000 + | ++ + | ++0 + | ++DLL calibration + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +ODT_delay_hold + | ++0XF800605C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_rd_odt_delay + | ++3:0 + | ++f + | ++3 + | ++3 + | ++UNUSED + | +
| +reg_ddrc_wr_odt_delay + | ++7:4 + | ++f0 + | ++0 + | ++0 + | ++The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. + | +
| +reg_ddrc_rd_odt_hold + | ++11:8 + | ++f00 + | ++0 + | ++0 + | ++Unused + | +
| +reg_ddrc_wr_odt_hold + | ++15:12 + | ++f000 + | ++5 + | ++5000 + | ++Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 + | +
| +ODT_delay_hold@0XF800605C + | ++31:0 + | ++ffff + | ++ + | ++5003 + | ++ODT delay and ODT hold + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +ctrl_reg1 + | ++0XF8006060 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_pageclose + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. + | +
| +reg_ddrc_lpr_num_entries + | ++6:1 + | ++7e + | ++1f + | ++3e + | ++Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. + | +
| +reg_ddrc_auto_pre_en + | ++7:7 + | ++80 + | ++0 + | ++0 + | ++When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) + | +
| +reg_ddrc_refresh_update_level + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. + | +
| +reg_ddrc_dis_wc + | ++9:9 + | ++200 + | ++0 + | ++0 + | ++Disable Write Combine: 0: enable 1: disable + | +
| +reg_ddrc_dis_collision_page_opt + | ++10:10 + | ++400 + | ++0 + | ++0 + | ++When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). + | +
| +reg_ddrc_selfref_en + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. + | +
| +ctrl_reg1@0XF8006060 + | ++31:0 + | ++17ff + | ++ + | ++3e + | ++Controller 1 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +ctrl_reg2 + | ++0XF8006064 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_go2critical_hysteresis + | ++12:5 + | ++1fe0 + | ++0 + | ++0 + | ++Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. + | +
| +reg_arb_go2critical_en + | ++17:17 + | ++20000 + | ++1 + | ++20000 + | ++0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. + | +
| +ctrl_reg2@0XF8006064 + | ++31:0 + | ++21fe0 + | ++ + | ++20000 + | ++Controller 2 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +ctrl_reg3 + | ++0XF8006068 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_wrlvl_ww + | ++7:0 + | ++ff + | ++41 + | ++41 + | ++DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) + | +
| +reg_ddrc_rdlvl_rr + | ++15:8 + | ++ff00 + | ++41 + | ++4100 + | ++DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. + | +
| +reg_ddrc_dfi_t_wlmrd + | ++25:16 + | ++3ff0000 + | ++28 + | ++280000 + | ++DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. + | +
| +ctrl_reg3@0XF8006068 + | ++31:0 + | ++3ffffff + | ++ + | ++284141 + | ++Controller 3 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +ctrl_reg4 + | ++0XF800606C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +dfi_t_ctrlupd_interval_min_x1024 + | ++7:0 + | ++ff + | ++10 + | ++10 + | ++This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks + | +
| +dfi_t_ctrlupd_interval_max_x1024 + | ++15:8 + | ++ff00 + | ++16 + | ++1600 + | ++This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks + | +
| +ctrl_reg4@0XF800606C + | ++31:0 + | ++ffff + | ++ + | ++1610 + | ++Controller 4 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +ctrl_reg5 + | ++0XF8006078 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_dfi_t_ctrl_delay + | ++3:0 + | ++f + | ++1 + | ++1 + | ++Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. + | +
| +reg_ddrc_dfi_t_dram_clk_disable + | ++7:4 + | ++f0 + | ++1 + | ++10 + | ++Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. + | +
| +reg_ddrc_dfi_t_dram_clk_enable + | ++11:8 + | ++f00 + | ++1 + | ++100 + | ++Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. + | +
| +reg_ddrc_t_cksre + | ++15:12 + | ++f000 + | ++6 + | ++6000 + | ++This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE + | +
| +reg_ddrc_t_cksrx + | ++19:16 + | ++f0000 + | ++6 + | ++60000 + | ++This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX + | +
| +reg_ddrc_t_ckesr + | ++25:20 + | ++3f00000 + | ++4 + | ++400000 + | ++Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 + | +
| +ctrl_reg5@0XF8006078 + | ++31:0 + | ++3ffffff + | ++ + | ++466111 + | ++Controller register 5 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +ctrl_reg6 + | ++0XF800607C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_t_ckpde + | ++3:0 + | ++f + | ++2 + | ++2 + | ++This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. + | +
| +reg_ddrc_t_ckpdx + | ++7:4 + | ++f0 + | ++2 + | ++20 + | ++This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. + | +
| +reg_ddrc_t_ckdpde + | ++11:8 + | ++f00 + | ++2 + | ++200 + | ++This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. + | +
| +reg_ddrc_t_ckdpdx + | ++15:12 + | ++f000 + | ++2 + | ++2000 + | ++This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. + | +
| +reg_ddrc_t_ckcsx + | ++19:16 + | ++f0000 + | ++3 + | ++30000 + | ++This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. + | +
| +ctrl_reg6@0XF800607C + | ++31:0 + | ++fffff + | ++ + | ++32222 + | ++Controller register 6 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +CHE_T_ZQ + | ++0XF80060A4 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_dis_auto_zq + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. + | +
| +reg_ddrc_ddr3 + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. + | +
| +reg_ddrc_t_mod + | ++11:2 + | ++ffc + | ++200 + | ++800 + | ++Mode register set command update delay (minimum d'128) + | +
| +reg_ddrc_t_zq_long_nop + | ++21:12 + | ++3ff000 + | ++200 + | ++200000 + | ++DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. + | +
| +reg_ddrc_t_zq_short_nop + | ++31:22 + | ++ffc00000 + | ++40 + | ++10000000 + | ++DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. + | +
| +CHE_T_ZQ@0XF80060A4 + | ++31:0 + | ++ffffffff + | ++ + | ++10200802 + | ++ZQ parameters + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +CHE_T_ZQ_Short_Interval_Reg + | ++0XF80060A8 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +t_zq_short_interval_x1024 + | ++19:0 + | ++fffff + | ++cb73 + | ++cb73 + | ++DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. + | +
| +dram_rstn_x1024 + | ++27:20 + | ++ff00000 + | ++69 + | ++6900000 + | ++Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. + | +
| +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + | ++31:0 + | ++fffffff + | ++ + | ++690cb73 + | ++Misc parameters + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +deep_pwrdwn_reg + | ++0XF80060AC + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +deeppowerdown_en + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. + | +
| +deeppowerdown_to_x1024 + | ++8:1 + | ++1fe + | ++ff + | ++1fe + | ++DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. + | +
| +deep_pwrdwn_reg@0XF80060AC + | ++31:0 + | ++1ff + | ++ + | ++1fe + | ++Deep powerdown (LPDDR2) + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +reg_2c + | ++0XF80060B0 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +dfi_wrlvl_max_x1024 + | ++11:0 + | ++fff + | ++fff + | ++fff + | ++Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks + | +
| +dfi_rdlvl_max_x1024 + | ++23:12 + | ++fff000 + | ++fff + | ++fff000 + | ++Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks + | +
| +ddrc_reg_twrlvl_max_error + | ++24:24 + | ++1000000 + | ++0 + | ++0 + | ++When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. + | +
| +ddrc_reg_trdlvl_max_error + | ++25:25 + | ++2000000 + | ++0 + | ++0 + | ++DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. + | +
| +reg_ddrc_dfi_wr_level_en + | ++26:26 + | ++4000000 + | ++1 + | ++4000000 + | ++0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs + | +
| +reg_ddrc_dfi_rd_dqs_gate_level + | ++27:27 + | ++8000000 + | ++1 + | ++8000000 + | ++0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs + | +
| +reg_ddrc_dfi_rd_data_eye_train + | ++28:28 + | ++10000000 + | ++1 + | ++10000000 + | ++DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. + | +
| +reg_2c@0XF80060B0 + | ++31:0 + | ++1fffffff + | ++ + | ++1cffffff + | ++Training control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +reg_2d + | ++0XF80060B4 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_skip_ocd + | ++9:9 + | ++200 + | ++1 + | ++200 + | ++This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. + | +
| +reg_2d@0XF80060B4 + | ++31:0 + | ++200 + | ++ + | ++200 + | ++Misc Debug + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +dfi_timing + | ++0XF80060B8 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_dfi_t_rddata_en + | ++4:0 + | ++1f + | ++6 + | ++6 + | ++Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. + | +
| +reg_ddrc_dfi_t_ctrlup_min + | ++14:5 + | ++7fe0 + | ++3 + | ++60 + | ++Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. + | +
| +reg_ddrc_dfi_t_ctrlup_max + | ++24:15 + | ++1ff8000 + | ++40 + | ++200000 + | ++Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. + | +
| +dfi_timing@0XF80060B8 + | ++31:0 + | ++1ffffff + | ++ + | ++200066 + | ++DFI timing + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +CHE_ECC_CONTROL_REG_OFFSET + | ++0XF80060C4 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +Clear_Uncorrectable_DRAM_ECC_error + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. + | +
| +Clear_Correctable_DRAM_ECC_error + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. + | +
| +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + | ++31:0 + | ++3 + | ++ + | ++3 + | ++ECC error clear + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +CHE_ECC_CONTROL_REG_OFFSET + | ++0XF80060C4 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +Clear_Uncorrectable_DRAM_ECC_error + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. + | +
| +Clear_Correctable_DRAM_ECC_error + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. + | +
| +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + | ++31:0 + | ++3 + | ++ + | ++0 + | ++ECC error clear + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +CHE_CORR_ECC_LOG_REG_OFFSET + | ++0XF80060C8 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +CORR_ECC_LOG_VALID + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) + | +
| +ECC_CORRECTED_BIT_NUM + | ++7:1 + | ++fe + | ++0 + | ++0 + | ++Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. + | +
| +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + | ++31:0 + | ++ff + | ++ + | ++0 + | ++ECC error correction + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +CHE_UNCORR_ECC_LOG_REG_OFFSET + | ++0XF80060DC + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +UNCORR_ECC_LOG_VALID + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). + | +
| +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + | ++31:0 + | ++1 + | ++ + | ++0 + | ++ECC unrecoverable error status + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +CHE_ECC_STATS_REG_OFFSET + | ++0XF80060F0 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +STAT_NUM_CORR_ERR + | ++15:8 + | ++ff00 + | ++0 + | ++0 + | ++Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). + | +
| +STAT_NUM_UNCORR_ERR + | ++7:0 + | ++ff + | ++0 + | ++0 + | ++Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). + | +
| +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + | ++31:0 + | ++ffff + | ++ + | ++0 + | ++ECC error count + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +ECC_scrub + | ++0XF80060F4 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_ecc_mode + | ++2:0 + | ++7 + | ++0 + | ++0 + | ++DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved + | +
| +reg_ddrc_dis_scrub + | ++3:3 + | ++8 + | ++1 + | ++8 + | ++0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs + | +
| +ECC_scrub@0XF80060F4 + | ++31:0 + | ++f + | ++ + | ++8 + | ++ECC mode/scrub + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +phy_rcvr_enable + | ++0XF8006114 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_dif_on + | ++3:0 + | ++f + | ++0 + | ++0 + | ++Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. + | +
| +reg_phy_dif_off + | ++7:4 + | ++f0 + | ++0 + | ++0 + | ++Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. + | +
| +phy_rcvr_enable@0XF8006114 + | ++31:0 + | ++ff + | ++ + | ++0 + | ++Phy receiver enable register + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +PHY_Config + | ++0XF8006118 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_data_slice_in_use + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. + | +
| +reg_phy_rdlvl_inc_mode + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++reserved + | +
| +reg_phy_gatelvl_inc_mode + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++reserved + | +
| +reg_phy_wrlvl_inc_mode + | ++3:3 + | ++8 + | ++0 + | ++0 + | ++reserved + | +
| +reg_phy_bist_shift_dq + | ++14:6 + | ++7fc0 + | ++0 + | ++0 + | ++Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. + | +
| +reg_phy_bist_err_clr + | ++23:15 + | ++ff8000 + | ++0 + | ++0 + | ++Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared + | +
| +reg_phy_dq_offset + | ++30:24 + | ++7f000000 + | ++40 + | ++40000000 + | ++Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. + | +
| +PHY_Config@0XF8006118 + | ++31:0 + | ++7fffffcf + | ++ + | ++40000001 + | ++PHY configuration register for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +PHY_Config + | ++0XF800611C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_data_slice_in_use + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. + | +
| +reg_phy_rdlvl_inc_mode + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++reserved + | +
| +reg_phy_gatelvl_inc_mode + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++reserved + | +
| +reg_phy_wrlvl_inc_mode + | ++3:3 + | ++8 + | ++0 + | ++0 + | ++reserved + | +
| +reg_phy_bist_shift_dq + | ++14:6 + | ++7fc0 + | ++0 + | ++0 + | ++Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. + | +
| +reg_phy_bist_err_clr + | ++23:15 + | ++ff8000 + | ++0 + | ++0 + | ++Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared + | +
| +reg_phy_dq_offset + | ++30:24 + | ++7f000000 + | ++40 + | ++40000000 + | ++Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. + | +
| +PHY_Config@0XF800611C + | ++31:0 + | ++7fffffcf + | ++ + | ++40000001 + | ++PHY configuration register for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +PHY_Config + | ++0XF8006120 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_data_slice_in_use + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. + | +
| +reg_phy_rdlvl_inc_mode + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++reserved + | +
| +reg_phy_gatelvl_inc_mode + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++reserved + | +
| +reg_phy_wrlvl_inc_mode + | ++3:3 + | ++8 + | ++0 + | ++0 + | ++reserved + | +
| +reg_phy_bist_shift_dq + | ++14:6 + | ++7fc0 + | ++0 + | ++0 + | ++Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. + | +
| +reg_phy_bist_err_clr + | ++23:15 + | ++ff8000 + | ++0 + | ++0 + | ++Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared + | +
| +reg_phy_dq_offset + | ++30:24 + | ++7f000000 + | ++40 + | ++40000000 + | ++Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. + | +
| +PHY_Config@0XF8006120 + | ++31:0 + | ++7fffffcf + | ++ + | ++40000001 + | ++PHY configuration register for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +PHY_Config + | ++0XF8006124 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_data_slice_in_use + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. + | +
| +reg_phy_rdlvl_inc_mode + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++reserved + | +
| +reg_phy_gatelvl_inc_mode + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++reserved + | +
| +reg_phy_wrlvl_inc_mode + | ++3:3 + | ++8 + | ++0 + | ++0 + | ++reserved + | +
| +reg_phy_bist_shift_dq + | ++14:6 + | ++7fc0 + | ++0 + | ++0 + | ++Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. + | +
| +reg_phy_bist_err_clr + | ++23:15 + | ++ff8000 + | ++0 + | ++0 + | ++Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared + | +
| +reg_phy_dq_offset + | ++30:24 + | ++7f000000 + | ++40 + | ++40000000 + | ++Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. + | +
| +PHY_Config@0XF8006124 + | ++31:0 + | ++7fffffcf + | ++ + | ++40000001 + | ++PHY configuration register for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +phy_init_ratio + | ++0XF800612C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_wrlvl_init_ratio + | ++9:0 + | ++3ff + | ++0 + | ++0 + | ++The user programmable init ratio used by Write Leveling FSM + | +
| +reg_phy_gatelvl_init_ratio + | ++19:10 + | ++ffc00 + | ++b0 + | ++2c000 + | ++The user programmable init ratio used Gate Leveling FSM + | +
| +phy_init_ratio@0XF800612C + | ++31:0 + | ++fffff + | ++ + | ++2c000 + | ++PHY init ratio register for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +phy_init_ratio + | ++0XF8006130 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_wrlvl_init_ratio + | ++9:0 + | ++3ff + | ++0 + | ++0 + | ++The user programmable init ratio used by Write Leveling FSM + | +
| +reg_phy_gatelvl_init_ratio + | ++19:10 + | ++ffc00 + | ++b1 + | ++2c400 + | ++The user programmable init ratio used Gate Leveling FSM + | +
| +phy_init_ratio@0XF8006130 + | ++31:0 + | ++fffff + | ++ + | ++2c400 + | ++PHY init ratio register for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +phy_init_ratio + | ++0XF8006134 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_wrlvl_init_ratio + | ++9:0 + | ++3ff + | ++3 + | ++3 + | ++The user programmable init ratio used by Write Leveling FSM + | +
| +reg_phy_gatelvl_init_ratio + | ++19:10 + | ++ffc00 + | ++bc + | ++2f000 + | ++The user programmable init ratio used Gate Leveling FSM + | +
| +phy_init_ratio@0XF8006134 + | ++31:0 + | ++fffff + | ++ + | ++2f003 + | ++PHY init ratio register for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +phy_init_ratio + | ++0XF8006138 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_wrlvl_init_ratio + | ++9:0 + | ++3ff + | ++3 + | ++3 + | ++The user programmable init ratio used by Write Leveling FSM + | +
| +reg_phy_gatelvl_init_ratio + | ++19:10 + | ++ffc00 + | ++bb + | ++2ec00 + | ++The user programmable init ratio used Gate Leveling FSM + | +
| +phy_init_ratio@0XF8006138 + | ++31:0 + | ++fffff + | ++ + | ++2ec03 + | ++PHY init ratio register for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +phy_rd_dqs_cfg + | ++0XF8006140 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_rd_dqs_slave_ratio + | ++9:0 + | ++3ff + | ++35 + | ++35 + | ++Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications + | +
| +reg_phy_rd_dqs_slave_force + | ++10:10 + | ++400 + | ++0 + | ++0 + | ++0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. + | +
| +reg_phy_rd_dqs_slave_delay + | ++19:11 + | ++ff800 + | ++0 + | ++0 + | ++If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. + | +
| +phy_rd_dqs_cfg@0XF8006140 + | ++31:0 + | ++fffff + | ++ + | ++35 + | ++PHY read DQS configuration register for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +phy_rd_dqs_cfg + | ++0XF8006144 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_rd_dqs_slave_ratio + | ++9:0 + | ++3ff + | ++35 + | ++35 + | ++Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications + | +
| +reg_phy_rd_dqs_slave_force + | ++10:10 + | ++400 + | ++0 + | ++0 + | ++0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. + | +
| +reg_phy_rd_dqs_slave_delay + | ++19:11 + | ++ff800 + | ++0 + | ++0 + | ++If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. + | +
| +phy_rd_dqs_cfg@0XF8006144 + | ++31:0 + | ++fffff + | ++ + | ++35 + | ++PHY read DQS configuration register for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +phy_rd_dqs_cfg + | ++0XF8006148 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_rd_dqs_slave_ratio + | ++9:0 + | ++3ff + | ++35 + | ++35 + | ++Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications + | +
| +reg_phy_rd_dqs_slave_force + | ++10:10 + | ++400 + | ++0 + | ++0 + | ++0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. + | +
| +reg_phy_rd_dqs_slave_delay + | ++19:11 + | ++ff800 + | ++0 + | ++0 + | ++If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. + | +
| +phy_rd_dqs_cfg@0XF8006148 + | ++31:0 + | ++fffff + | ++ + | ++35 + | ++PHY read DQS configuration register for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +phy_rd_dqs_cfg + | ++0XF800614C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_rd_dqs_slave_ratio + | ++9:0 + | ++3ff + | ++35 + | ++35 + | ++Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications + | +
| +reg_phy_rd_dqs_slave_force + | ++10:10 + | ++400 + | ++0 + | ++0 + | ++0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. + | +
| +reg_phy_rd_dqs_slave_delay + | ++19:11 + | ++ff800 + | ++0 + | ++0 + | ++If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. + | +
| +phy_rd_dqs_cfg@0XF800614C + | ++31:0 + | ++fffff + | ++ + | ++35 + | ++PHY read DQS configuration register for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +phy_wr_dqs_cfg + | ++0XF8006154 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_wr_dqs_slave_ratio + | ++9:0 + | ++3ff + | ++77 + | ++77 + | ++Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) + | +
| +reg_phy_wr_dqs_slave_force + | ++10:10 + | ++400 + | ++0 + | ++0 + | ++0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. + | +
| +reg_phy_wr_dqs_slave_delay + | ++19:11 + | ++ff800 + | ++0 + | ++0 + | ++If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. + | +
| +phy_wr_dqs_cfg@0XF8006154 + | ++31:0 + | ++fffff + | ++ + | ++77 + | ++PHY write DQS configuration register for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +phy_wr_dqs_cfg + | ++0XF8006158 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_wr_dqs_slave_ratio + | ++9:0 + | ++3ff + | ++77 + | ++77 + | ++Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) + | +
| +reg_phy_wr_dqs_slave_force + | ++10:10 + | ++400 + | ++0 + | ++0 + | ++0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. + | +
| +reg_phy_wr_dqs_slave_delay + | ++19:11 + | ++ff800 + | ++0 + | ++0 + | ++If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. + | +
| +phy_wr_dqs_cfg@0XF8006158 + | ++31:0 + | ++fffff + | ++ + | ++77 + | ++PHY write DQS configuration register for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +phy_wr_dqs_cfg + | ++0XF800615C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_wr_dqs_slave_ratio + | ++9:0 + | ++3ff + | ++83 + | ++83 + | ++Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) + | +
| +reg_phy_wr_dqs_slave_force + | ++10:10 + | ++400 + | ++0 + | ++0 + | ++0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. + | +
| +reg_phy_wr_dqs_slave_delay + | ++19:11 + | ++ff800 + | ++0 + | ++0 + | ++If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. + | +
| +phy_wr_dqs_cfg@0XF800615C + | ++31:0 + | ++fffff + | ++ + | ++83 + | ++PHY write DQS configuration register for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +phy_wr_dqs_cfg + | ++0XF8006160 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_wr_dqs_slave_ratio + | ++9:0 + | ++3ff + | ++83 + | ++83 + | ++Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) + | +
| +reg_phy_wr_dqs_slave_force + | ++10:10 + | ++400 + | ++0 + | ++0 + | ++0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. + | +
| +reg_phy_wr_dqs_slave_delay + | ++19:11 + | ++ff800 + | ++0 + | ++0 + | ++If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. + | +
| +phy_wr_dqs_cfg@0XF8006160 + | ++31:0 + | ++fffff + | ++ + | ++83 + | ++PHY write DQS configuration register for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +phy_we_cfg + | ++0XF8006168 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_fifo_we_slave_ratio + | ++10:0 + | ++7ff + | ++105 + | ++105 + | ++Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. + | +
| +reg_phy_fifo_we_in_force + | ++11:11 + | ++800 + | ++0 + | ++0 + | ++0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units + | +
| +reg_phy_fifo_we_in_delay + | ++20:12 + | ++1ff000 + | ++0 + | ++0 + | ++Delay value to be used when reg_phy_fifo_we_in_force is set to 1. + | +
| +phy_we_cfg@0XF8006168 + | ++31:0 + | ++1fffff + | ++ + | ++105 + | ++PHY FIFO write enable configuration for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +phy_we_cfg + | ++0XF800616C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_fifo_we_slave_ratio + | ++10:0 + | ++7ff + | ++106 + | ++106 + | ++Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. + | +
| +reg_phy_fifo_we_in_force + | ++11:11 + | ++800 + | ++0 + | ++0 + | ++0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units + | +
| +reg_phy_fifo_we_in_delay + | ++20:12 + | ++1ff000 + | ++0 + | ++0 + | ++Delay value to be used when reg_phy_fifo_we_in_force is set to 1. + | +
| +phy_we_cfg@0XF800616C + | ++31:0 + | ++1fffff + | ++ + | ++106 + | ++PHY FIFO write enable configuration for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +phy_we_cfg + | ++0XF8006170 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_fifo_we_slave_ratio + | ++10:0 + | ++7ff + | ++111 + | ++111 + | ++Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. + | +
| +reg_phy_fifo_we_in_force + | ++11:11 + | ++800 + | ++0 + | ++0 + | ++0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units + | +
| +reg_phy_fifo_we_in_delay + | ++20:12 + | ++1ff000 + | ++0 + | ++0 + | ++Delay value to be used when reg_phy_fifo_we_in_force is set to 1. + | +
| +phy_we_cfg@0XF8006170 + | ++31:0 + | ++1fffff + | ++ + | ++111 + | ++PHY FIFO write enable configuration for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +phy_we_cfg + | ++0XF8006174 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_fifo_we_slave_ratio + | ++10:0 + | ++7ff + | ++110 + | ++110 + | ++Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. + | +
| +reg_phy_fifo_we_in_force + | ++11:11 + | ++800 + | ++0 + | ++0 + | ++0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units + | +
| +reg_phy_fifo_we_in_delay + | ++20:12 + | ++1ff000 + | ++0 + | ++0 + | ++Delay value to be used when reg_phy_fifo_we_in_force is set to 1. + | +
| +phy_we_cfg@0XF8006174 + | ++31:0 + | ++1fffff + | ++ + | ++110 + | ++PHY FIFO write enable configuration for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +wr_data_slv + | ++0XF800617C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_wr_data_slave_ratio + | ++9:0 + | ++3ff + | ++b7 + | ++b7 + | ++Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. + | +
| +reg_phy_wr_data_slave_force + | ++10:10 + | ++400 + | ++0 + | ++0 + | ++0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. + | +
| +reg_phy_wr_data_slave_delay + | ++19:11 + | ++ff800 + | ++0 + | ++0 + | ++If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. + | +
| +wr_data_slv@0XF800617C + | ++31:0 + | ++fffff + | ++ + | ++b7 + | ++PHY write data slave ratio config for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +wr_data_slv + | ++0XF8006180 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_wr_data_slave_ratio + | ++9:0 + | ++3ff + | ++b7 + | ++b7 + | ++Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. + | +
| +reg_phy_wr_data_slave_force + | ++10:10 + | ++400 + | ++0 + | ++0 + | ++0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. + | +
| +reg_phy_wr_data_slave_delay + | ++19:11 + | ++ff800 + | ++0 + | ++0 + | ++If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. + | +
| +wr_data_slv@0XF8006180 + | ++31:0 + | ++fffff + | ++ + | ++b7 + | ++PHY write data slave ratio config for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +wr_data_slv + | ++0XF8006184 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_wr_data_slave_ratio + | ++9:0 + | ++3ff + | ++c3 + | ++c3 + | ++Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. + | +
| +reg_phy_wr_data_slave_force + | ++10:10 + | ++400 + | ++0 + | ++0 + | ++0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. + | +
| +reg_phy_wr_data_slave_delay + | ++19:11 + | ++ff800 + | ++0 + | ++0 + | ++If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. + | +
| +wr_data_slv@0XF8006184 + | ++31:0 + | ++fffff + | ++ + | ++c3 + | ++PHY write data slave ratio config for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +wr_data_slv + | ++0XF8006188 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_wr_data_slave_ratio + | ++9:0 + | ++3ff + | ++c3 + | ++c3 + | ++Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. + | +
| +reg_phy_wr_data_slave_force + | ++10:10 + | ++400 + | ++0 + | ++0 + | ++0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. + | +
| +reg_phy_wr_data_slave_delay + | ++19:11 + | ++ff800 + | ++0 + | ++0 + | ++If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. + | +
| +wr_data_slv@0XF8006188 + | ++31:0 + | ++fffff + | ++ + | ++c3 + | ++PHY write data slave ratio config for data slice 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +reg_64 + | ++0XF8006190 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_bl2 + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Reserved for future Use. + | +
| +reg_phy_at_spd_atpg + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. + | +
| +reg_phy_bist_enable + | ++3:3 + | ++8 + | ++0 + | ++0 + | ++Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. + | +
| +reg_phy_bist_force_err + | ++4:4 + | ++10 + | ++0 + | ++0 + | ++This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. + | +
| +reg_phy_bist_mode + | ++6:5 + | ++60 + | ++0 + | ++0 + | ++The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved + | +
| +reg_phy_invert_clkout + | ++7:7 + | ++80 + | ++1 + | ++80 + | ++Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. + | +
| +reg_phy_sel_logic + | ++9:9 + | ++200 + | ++0 + | ++0 + | ++Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms + | +
| +reg_phy_ctrl_slave_ratio + | ++19:10 + | ++ffc00 + | ++100 + | ++40000 + | ++Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. + | +
| +reg_phy_ctrl_slave_force + | ++20:20 + | ++100000 + | ++0 + | ++0 + | ++0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. + | +
| +reg_phy_ctrl_slave_delay + | ++27:21 + | ++fe00000 + | ++0 + | ++0 + | ++If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. + | +
| +reg_phy_lpddr + | ++29:29 + | ++20000000 + | ++0 + | ++0 + | ++0: DDR2 or DDR3. 1: LPDDR2. + | +
| +reg_phy_cmd_latency + | ++30:30 + | ++40000000 + | ++0 + | ++0 + | ++If set to 1, command comes to phy_ctrl through a flop. + | +
| +reg_64@0XF8006190 + | ++31:0 + | ++6ffffefe + | ++ + | ++40080 + | ++Training control 2 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +reg_65 + | ++0XF8006194 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_phy_wr_rl_delay + | ++4:0 + | ++1f + | ++2 + | ++2 + | ++This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. + | +
| +reg_phy_rd_rl_delay + | ++9:5 + | ++3e0 + | ++4 + | ++80 + | ++This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. + | +
| +reg_phy_dll_lock_diff + | ++13:10 + | ++3c00 + | ++f + | ++3c00 + | ++The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted + | +
| +reg_phy_use_wr_level + | ++14:14 + | ++4000 + | ++1 + | ++4000 + | ++Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. + | +
| +reg_phy_use_rd_dqs_gate_level + | ++15:15 + | ++8000 + | ++1 + | ++8000 + | ++Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. + | +
| +reg_phy_use_rd_data_eye_level + | ++16:16 + | ++10000 + | ++1 + | ++10000 + | ++Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure + | +
| +reg_phy_dis_calib_rst + | ++17:17 + | ++20000 + | ++0 + | ++0 + | ++Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs + | +
| +reg_phy_ctrl_slave_delay + | ++19:18 + | ++c0000 + | ++0 + | ++0 + | ++If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value + | +
| +reg_65@0XF8006194 + | ++31:0 + | ++fffff + | ++ + | ++1fc82 + | ++Training control 3 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +page_mask + | ++0XF8006204 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_arb_page_addr_mask + | ++31:0 + | ++ffffffff + | ++0 + | ++0 + | ++Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. + | +
| +page_mask@0XF8006204 + | ++31:0 + | ++ffffffff + | ++ + | ++0 + | ++Page mask + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +axi_priority_wr_port + | ++0XF8006208 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_arb_pri_wr_portn + | ++9:0 + | ++3ff + | ++3ff + | ++3ff + | ++Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. + | +
| +reg_arb_disable_aging_wr_portn + | ++16:16 + | ++10000 + | ++0 + | ++0 + | ++Disable aging for this Write Port. + | +
| +reg_arb_disable_urgent_wr_portn + | ++17:17 + | ++20000 + | ++0 + | ++0 + | ++Disable urgent for this Write Port. + | +
| +reg_arb_dis_page_match_wr_portn + | ++18:18 + | ++40000 + | ++0 + | ++0 + | ++Disable the page match feature. + | +
| +axi_priority_wr_port@0XF8006208 + | ++31:0 + | ++703ff + | ++ + | ++3ff + | ++AXI Priority control for write port 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +axi_priority_wr_port + | ++0XF800620C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_arb_pri_wr_portn + | ++9:0 + | ++3ff + | ++3ff + | ++3ff + | ++Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. + | +
| +reg_arb_disable_aging_wr_portn + | ++16:16 + | ++10000 + | ++0 + | ++0 + | ++Disable aging for this Write Port. + | +
| +reg_arb_disable_urgent_wr_portn + | ++17:17 + | ++20000 + | ++0 + | ++0 + | ++Disable urgent for this Write Port. + | +
| +reg_arb_dis_page_match_wr_portn + | ++18:18 + | ++40000 + | ++0 + | ++0 + | ++Disable the page match feature. + | +
| +axi_priority_wr_port@0XF800620C + | ++31:0 + | ++703ff + | ++ + | ++3ff + | ++AXI Priority control for write port 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +axi_priority_wr_port + | ++0XF8006210 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_arb_pri_wr_portn + | ++9:0 + | ++3ff + | ++3ff + | ++3ff + | ++Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. + | +
| +reg_arb_disable_aging_wr_portn + | ++16:16 + | ++10000 + | ++0 + | ++0 + | ++Disable aging for this Write Port. + | +
| +reg_arb_disable_urgent_wr_portn + | ++17:17 + | ++20000 + | ++0 + | ++0 + | ++Disable urgent for this Write Port. + | +
| +reg_arb_dis_page_match_wr_portn + | ++18:18 + | ++40000 + | ++0 + | ++0 + | ++Disable the page match feature. + | +
| +axi_priority_wr_port@0XF8006210 + | ++31:0 + | ++703ff + | ++ + | ++3ff + | ++AXI Priority control for write port 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +axi_priority_wr_port + | ++0XF8006214 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_arb_pri_wr_portn + | ++9:0 + | ++3ff + | ++3ff + | ++3ff + | ++Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. + | +
| +reg_arb_disable_aging_wr_portn + | ++16:16 + | ++10000 + | ++0 + | ++0 + | ++Disable aging for this Write Port. + | +
| +reg_arb_disable_urgent_wr_portn + | ++17:17 + | ++20000 + | ++0 + | ++0 + | ++Disable urgent for this Write Port. + | +
| +reg_arb_dis_page_match_wr_portn + | ++18:18 + | ++40000 + | ++0 + | ++0 + | ++Disable the page match feature. + | +
| +axi_priority_wr_port@0XF8006214 + | ++31:0 + | ++703ff + | ++ + | ++3ff + | ++AXI Priority control for write port 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +axi_priority_rd_port + | ++0XF8006218 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_arb_pri_rd_portn + | ++9:0 + | ++3ff + | ++3ff + | ++3ff + | ++Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. + | +
| +reg_arb_disable_aging_rd_portn + | ++16:16 + | ++10000 + | ++0 + | ++0 + | ++Disable aging for this Read Port. + | +
| +reg_arb_disable_urgent_rd_portn + | ++17:17 + | ++20000 + | ++0 + | ++0 + | ++Disable urgent for this Read Port. + | +
| +reg_arb_dis_page_match_rd_portn + | ++18:18 + | ++40000 + | ++0 + | ++0 + | ++Disable the page match feature. + | +
| +reg_arb_set_hpr_rd_portn + | ++19:19 + | ++80000 + | ++0 + | ++0 + | ++Enable reads to be generated as HPR for this Read Port. + | +
| +axi_priority_rd_port@0XF8006218 + | ++31:0 + | ++f03ff + | ++ + | ++3ff + | ++AXI Priority control for read port 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +axi_priority_rd_port + | ++0XF800621C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_arb_pri_rd_portn + | ++9:0 + | ++3ff + | ++3ff + | ++3ff + | ++Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. + | +
| +reg_arb_disable_aging_rd_portn + | ++16:16 + | ++10000 + | ++0 + | ++0 + | ++Disable aging for this Read Port. + | +
| +reg_arb_disable_urgent_rd_portn + | ++17:17 + | ++20000 + | ++0 + | ++0 + | ++Disable urgent for this Read Port. + | +
| +reg_arb_dis_page_match_rd_portn + | ++18:18 + | ++40000 + | ++0 + | ++0 + | ++Disable the page match feature. + | +
| +reg_arb_set_hpr_rd_portn + | ++19:19 + | ++80000 + | ++0 + | ++0 + | ++Enable reads to be generated as HPR for this Read Port. + | +
| +axi_priority_rd_port@0XF800621C + | ++31:0 + | ++f03ff + | ++ + | ++3ff + | ++AXI Priority control for read port 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +axi_priority_rd_port + | ++0XF8006220 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_arb_pri_rd_portn + | ++9:0 + | ++3ff + | ++3ff + | ++3ff + | ++Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. + | +
| +reg_arb_disable_aging_rd_portn + | ++16:16 + | ++10000 + | ++0 + | ++0 + | ++Disable aging for this Read Port. + | +
| +reg_arb_disable_urgent_rd_portn + | ++17:17 + | ++20000 + | ++0 + | ++0 + | ++Disable urgent for this Read Port. + | +
| +reg_arb_dis_page_match_rd_portn + | ++18:18 + | ++40000 + | ++0 + | ++0 + | ++Disable the page match feature. + | +
| +reg_arb_set_hpr_rd_portn + | ++19:19 + | ++80000 + | ++0 + | ++0 + | ++Enable reads to be generated as HPR for this Read Port. + | +
| +axi_priority_rd_port@0XF8006220 + | ++31:0 + | ++f03ff + | ++ + | ++3ff + | ++AXI Priority control for read port 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +axi_priority_rd_port + | ++0XF8006224 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_arb_pri_rd_portn + | ++9:0 + | ++3ff + | ++3ff + | ++3ff + | ++Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. + | +
| +reg_arb_disable_aging_rd_portn + | ++16:16 + | ++10000 + | ++0 + | ++0 + | ++Disable aging for this Read Port. + | +
| +reg_arb_disable_urgent_rd_portn + | ++17:17 + | ++20000 + | ++0 + | ++0 + | ++Disable urgent for this Read Port. + | +
| +reg_arb_dis_page_match_rd_portn + | ++18:18 + | ++40000 + | ++0 + | ++0 + | ++Disable the page match feature. + | +
| +reg_arb_set_hpr_rd_portn + | ++19:19 + | ++80000 + | ++0 + | ++0 + | ++Enable reads to be generated as HPR for this Read Port. + | +
| +axi_priority_rd_port@0XF8006224 + | ++31:0 + | ++f03ff + | ++ + | ++3ff + | ++AXI Priority control for read port 0. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +lpddr_ctrl0 + | ++0XF80062A8 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_lpddr2 + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. + | +
| +reg_ddrc_derate_enable + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed + | +
| +reg_ddrc_mr4_margin + | ++11:4 + | ++ff0 + | ++0 + | ++0 + | ++UNUSED + | +
| +lpddr_ctrl0@0XF80062A8 + | ++31:0 + | ++ff5 + | ++ + | ++0 + | ++LPDDR2 Control 0 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +lpddr_ctrl1 + | ++0XF80062AC + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_mr4_read_interval + | ++31:0 + | ++ffffffff + | ++0 + | ++0 + | ++Interval between two MR4 reads, USED to derate the timing parameters. + | +
| +lpddr_ctrl1@0XF80062AC + | ++31:0 + | ++ffffffff + | ++ + | ++0 + | ++LPDDR2 Control 1 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +lpddr_ctrl2 + | ++0XF80062B0 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_min_stable_clock_x1 + | ++3:0 + | ++f + | ++5 + | ++5 + | ++Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. + | +
| +reg_ddrc_idle_after_reset_x32 + | ++11:4 + | ++ff0 + | ++12 + | ++120 + | ++Idle time after the reset command, tINIT4. Units: 32 clock cycles. + | +
| +reg_ddrc_t_mrw + | ++21:12 + | ++3ff000 + | ++5 + | ++5000 + | ++Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. + | +
| +lpddr_ctrl2@0XF80062B0 + | ++31:0 + | ++3fffff + | ++ + | ++5125 + | ++LPDDR2 Control 2 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +lpddr_ctrl3 + | ++0XF80062B4 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_max_auto_init_x1024 + | ++7:0 + | ++ff + | ++a8 + | ++a8 + | ++Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. + | +
| +reg_ddrc_dev_zqinit_x32 + | ++17:8 + | ++3ff00 + | ++12 + | ++1200 + | ++ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. + | +
| +lpddr_ctrl3@0XF80062B4 + | ++31:0 + | ++3ffff + | ++ + | ++12a8 + | ++LPDDR2 Control 3 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_DCI_STATUS + | ++0XF8000B74 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +DONE + | ++13:13 + | ++2000 + | ++1 + | ++2000 + | ++DCI done signal + | +
| +DDRIOB_DCI_STATUS@0XF8000B74 + | ++31:0 + | ++2000 + | ++ + | ++2000 + | ++tobe + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +ddrc_ctrl + | ++0XF8006000 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reg_ddrc_soft_rstb + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. + | +
| +reg_ddrc_powerdown_en + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable + | +
| +reg_ddrc_data_bus_width + | ++3:2 + | ++c + | ++0 + | ++0 + | ++DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved + | +
| +reg_ddrc_burst8_refresh + | ++6:4 + | ++70 + | ++0 + | ++0 + | ++Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh + | +
| +reg_ddrc_rdwr_idle_gap + | ++13:7 + | ++3f80 + | ++1 + | ++80 + | ++When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. + | +
| +reg_ddrc_dis_rd_bypass + | ++14:14 + | ++4000 + | ++0 + | ++0 + | ++Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. + | +
| +reg_ddrc_dis_act_bypass + | ++15:15 + | ++8000 + | ++0 + | ++0 + | ++Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. + | +
| +reg_ddrc_dis_auto_refresh + | ++16:16 + | ++10000 + | ++0 + | ++0 + | ++Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. + | +
| +ddrc_ctrl@0XF8006000 + | ++31:0 + | ++1ffff + | ++ + | ++81 + | ++DDRC Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +mode_sts_reg + | ++0XF8006054 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +ddrc_reg_operating_mode + | ++2:0 + | ++7 + | ++1 + | ++1 + | ++Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) + | +
| +mode_sts_reg@0XF8006054 + | ++31:0 + | ++7 + | ++ + | ++1 + | ++tobe + | +
+
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| + +SLCR_UNLOCK + + | ++0XF8000008 + | ++32 + | ++WO + | ++0x000000 + | ++SLCR Write Protection Unlock + | +
| + +DDRIOB_ADDR0 + + | ++0XF8000B40 + | ++32 + | ++RW + | ++0x000000 + | ++DDR IOB Config for A[14:0], CKE and DRST_B + | +
| + +DDRIOB_ADDR1 + + | ++0XF8000B44 + | ++32 + | ++RW + | ++0x000000 + | ++DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B + | +
| + +DDRIOB_DATA0 + + | ++0XF8000B48 + | ++32 + | ++RW + | ++0x000000 + | ++DDR IOB Config for Data 15:0 + | +
| + +DDRIOB_DATA1 + + | ++0XF8000B4C + | ++32 + | ++RW + | ++0x000000 + | ++DDR IOB Config for Data 31:16 + | +
| + +DDRIOB_DIFF0 + + | ++0XF8000B50 + | ++32 + | ++RW + | ++0x000000 + | ++DDR IOB Config for DQS 1:0 + | +
| + +DDRIOB_DIFF1 + + | ++0XF8000B54 + | ++32 + | ++RW + | ++0x000000 + | ++DDR IOB Config for DQS 3:2 + | +
| + +DDRIOB_CLOCK + + | ++0XF8000B58 + | ++32 + | ++RW + | ++0x000000 + | ++DDR IOB Config for Clock Output + | +
| + +DDRIOB_DRIVE_SLEW_ADDR + + | ++0XF8000B5C + | ++32 + | ++RW + | ++0x000000 + | ++Drive and Slew controls for Address and Command pins of the DDR Interface + | +
| + +DDRIOB_DRIVE_SLEW_DATA + + | ++0XF8000B60 + | ++32 + | ++RW + | ++0x000000 + | ++Drive and Slew controls for DQ pins of the DDR Interface + | +
| + +DDRIOB_DRIVE_SLEW_DIFF + + | ++0XF8000B64 + | ++32 + | ++RW + | ++0x000000 + | ++Drive and Slew controls for DQS pins of the DDR Interface + | +
| + +DDRIOB_DRIVE_SLEW_CLOCK + + | ++0XF8000B68 + | ++32 + | ++RW + | ++0x000000 + | ++Drive and Slew controls for Clock pins of the DDR Interface + | +
| + +DDRIOB_DDR_CTRL + + | ++0XF8000B6C + | ++32 + | ++RW + | ++0x000000 + | ++DDR IOB Buffer Control + | +
| + +DDRIOB_DCI_CTRL + + | ++0XF8000B70 + | ++32 + | ++RW + | ++0x000000 + | ++DDR IOB DCI Config + | +
| + +DDRIOB_DCI_CTRL + + | ++0XF8000B70 + | ++32 + | ++RW + | ++0x000000 + | ++DDR IOB DCI Config + | +
| + +DDRIOB_DCI_CTRL + + | ++0XF8000B70 + | ++32 + | ++RW + | ++0x000000 + | ++DDR IOB DCI Config + | +
| + +MIO_PIN_00 + + | ++0XF8000700 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 0 Control + | +
| + +MIO_PIN_01 + + | ++0XF8000704 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 1 Control + | +
| + +MIO_PIN_02 + + | ++0XF8000708 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 2 Control + | +
| + +MIO_PIN_03 + + | ++0XF800070C + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 3 Control + | +
| + +MIO_PIN_04 + + | ++0XF8000710 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 4 Control + | +
| + +MIO_PIN_05 + + | ++0XF8000714 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 5 Control + | +
| + +MIO_PIN_06 + + | ++0XF8000718 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 6 Control + | +
| + +MIO_PIN_07 + + | ++0XF800071C + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 7 Control + | +
| + +MIO_PIN_08 + + | ++0XF8000720 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 8 Control + | +
| + +MIO_PIN_09 + + | ++0XF8000724 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 9 Control + | +
| + +MIO_PIN_10 + + | ++0XF8000728 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 10 Control + | +
| + +MIO_PIN_11 + + | ++0XF800072C + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 11 Control + | +
| + +MIO_PIN_12 + + | ++0XF8000730 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 12 Control + | +
| + +MIO_PIN_13 + + | ++0XF8000734 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 13 Control + | +
| + +MIO_PIN_14 + + | ++0XF8000738 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 14 Control + | +
| + +MIO_PIN_15 + + | ++0XF800073C + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 15 Control + | +
| + +MIO_PIN_16 + + | ++0XF8000740 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 16 Control + | +
| + +MIO_PIN_17 + + | ++0XF8000744 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 17 Control + | +
| + +MIO_PIN_18 + + | ++0XF8000748 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 18 Control + | +
| + +MIO_PIN_19 + + | ++0XF800074C + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 19 Control + | +
| + +MIO_PIN_20 + + | ++0XF8000750 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 20 Control + | +
| + +MIO_PIN_21 + + | ++0XF8000754 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 21 Control + | +
| + +MIO_PIN_22 + + | ++0XF8000758 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 22 Control + | +
| + +MIO_PIN_23 + + | ++0XF800075C + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 23 Control + | +
| + +MIO_PIN_24 + + | ++0XF8000760 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 24 Control + | +
| + +MIO_PIN_25 + + | ++0XF8000764 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 25 Control + | +
| + +MIO_PIN_26 + + | ++0XF8000768 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 26 Control + | +
| + +MIO_PIN_27 + + | ++0XF800076C + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 27 Control + | +
| + +MIO_PIN_28 + + | ++0XF8000770 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 28 Control + | +
| + +MIO_PIN_29 + + | ++0XF8000774 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 29 Control + | +
| + +MIO_PIN_30 + + | ++0XF8000778 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 30 Control + | +
| + +MIO_PIN_31 + + | ++0XF800077C + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 31 Control + | +
| + +MIO_PIN_32 + + | ++0XF8000780 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 32 Control + | +
| + +MIO_PIN_33 + + | ++0XF8000784 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 33 Control + | +
| + +MIO_PIN_34 + + | ++0XF8000788 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 34 Control + | +
| + +MIO_PIN_35 + + | ++0XF800078C + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 35 Control + | +
| + +MIO_PIN_36 + + | ++0XF8000790 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 36 Control + | +
| + +MIO_PIN_37 + + | ++0XF8000794 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 37 Control + | +
| + +MIO_PIN_38 + + | ++0XF8000798 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 38 Control + | +
| + +MIO_PIN_39 + + | ++0XF800079C + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 39 Control + | +
| + +MIO_PIN_40 + + | ++0XF80007A0 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 40 Control + | +
| + +MIO_PIN_41 + + | ++0XF80007A4 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 41 Control + | +
| + +MIO_PIN_42 + + | ++0XF80007A8 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 42 Control + | +
| + +MIO_PIN_43 + + | ++0XF80007AC + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 43 Control + | +
| + +MIO_PIN_44 + + | ++0XF80007B0 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 44 Control + | +
| + +MIO_PIN_45 + + | ++0XF80007B4 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 45 Control + | +
| + +MIO_PIN_46 + + | ++0XF80007B8 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 46 Control + | +
| + +MIO_PIN_47 + + | ++0XF80007BC + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 47 Control + | +
| + +MIO_PIN_48 + + | ++0XF80007C0 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 48 Control + | +
| + +MIO_PIN_49 + + | ++0XF80007C4 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 49 Control + | +
| + +MIO_PIN_50 + + | ++0XF80007C8 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 50 Control + | +
| + +MIO_PIN_51 + + | ++0XF80007CC + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 51 Control + | +
| + +MIO_PIN_52 + + | ++0XF80007D0 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 52 Control + | +
| + +MIO_PIN_53 + + | ++0XF80007D4 + | ++32 + | ++RW + | ++0x000000 + | ++MIO Pin 53 Control + | +
| + +SD0_WP_CD_SEL + + | ++0XF8000830 + | ++32 + | ++RW + | ++0x000000 + | ++SDIO 0 WP CD select + | +
| + +SLCR_LOCK + + | ++0XF8000004 + | ++32 + | ++WO + | ++0x000000 + | ++SLCR Write Protection Lock + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +SLCR_UNLOCK + | ++0XF8000008 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +UNLOCK_KEY + | ++15:0 + | ++ffff + | ++df0d + | ++df0d + | ++Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. + | +
| +SLCR_UNLOCK@0XF8000008 + | ++31:0 + | ++ffff + | ++ + | ++df0d + | ++SLCR Write Protection Unlock + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_ADDR0 + | ++0XF8000B40 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reserved_INP_POWER + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +INP_TYPE + | ++2:1 + | ++6 + | ++0 + | ++0 + | ++Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. + | +
| +DCI_UPDATE_B + | ++3:3 + | ++8 + | ++0 + | ++0 + | ++DCI Update Enable: 0: disable 1: enable + | +
| +TERM_EN + | ++4:4 + | ++10 + | ++0 + | ++0 + | ++Tri State Termination Enable: 0: disable 1: enable + | +
| +DCI_TYPE + | ++6:5 + | ++60 + | ++0 + | ++0 + | ++DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) + | +
| +IBUF_DISABLE_MODE + | ++7:7 + | ++80 + | ++0 + | ++0 + | ++Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. + | +
| +TERM_DISABLE_MODE + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. + | +
| +OUTPUT_EN + | ++10:9 + | ++600 + | ++3 + | ++600 + | ++Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf + | +
| +PULLUP_EN + | ++11:11 + | ++800 + | ++0 + | ++0 + | ++enables pullup on output 0: no pullup 1: pullup enabled + | +
| +DDRIOB_ADDR0@0XF8000B40 + | ++31:0 + | ++fff + | ++ + | ++600 + | ++DDR IOB Config for A[14:0], CKE and DRST_B + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_ADDR1 + | ++0XF8000B44 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reserved_INP_POWER + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +INP_TYPE + | ++2:1 + | ++6 + | ++0 + | ++0 + | ++Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. + | +
| +DCI_UPDATE_B + | ++3:3 + | ++8 + | ++0 + | ++0 + | ++DCI Update Enable: 0: disable 1: enable + | +
| +TERM_EN + | ++4:4 + | ++10 + | ++0 + | ++0 + | ++Tri State Termination Enable: 0: disable 1: enable + | +
| +DCI_TYPE + | ++6:5 + | ++60 + | ++0 + | ++0 + | ++DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) + | +
| +IBUF_DISABLE_MODE + | ++7:7 + | ++80 + | ++0 + | ++0 + | ++Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. + | +
| +TERM_DISABLE_MODE + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. + | +
| +OUTPUT_EN + | ++10:9 + | ++600 + | ++3 + | ++600 + | ++Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf + | +
| +PULLUP_EN + | ++11:11 + | ++800 + | ++0 + | ++0 + | ++enables pullup on output 0: no pullup 1: pullup enabled + | +
| +DDRIOB_ADDR1@0XF8000B44 + | ++31:0 + | ++fff + | ++ + | ++600 + | ++DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_DATA0 + | ++0XF8000B48 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reserved_INP_POWER + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +INP_TYPE + | ++2:1 + | ++6 + | ++1 + | ++2 + | ++Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. + | +
| +DCI_UPDATE_B + | ++3:3 + | ++8 + | ++0 + | ++0 + | ++DCI Update Enable: 0: disable 1: enable + | +
| +TERM_EN + | ++4:4 + | ++10 + | ++1 + | ++10 + | ++Tri State Termination Enable: 0: disable 1: enable + | +
| +DCI_TYPE + | ++6:5 + | ++60 + | ++3 + | ++60 + | ++DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) + | +
| +IBUF_DISABLE_MODE + | ++7:7 + | ++80 + | ++0 + | ++0 + | ++Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. + | +
| +TERM_DISABLE_MODE + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. + | +
| +OUTPUT_EN + | ++10:9 + | ++600 + | ++3 + | ++600 + | ++Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf + | +
| +PULLUP_EN + | ++11:11 + | ++800 + | ++0 + | ++0 + | ++enables pullup on output 0: no pullup 1: pullup enabled + | +
| +DDRIOB_DATA0@0XF8000B48 + | ++31:0 + | ++fff + | ++ + | ++672 + | ++DDR IOB Config for Data 15:0 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_DATA1 + | ++0XF8000B4C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reserved_INP_POWER + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +INP_TYPE + | ++2:1 + | ++6 + | ++1 + | ++2 + | ++Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. + | +
| +DCI_UPDATE_B + | ++3:3 + | ++8 + | ++0 + | ++0 + | ++DCI Update Enable: 0: disable 1: enable + | +
| +TERM_EN + | ++4:4 + | ++10 + | ++1 + | ++10 + | ++Tri State Termination Enable: 0: disable 1: enable + | +
| +DCI_TYPE + | ++6:5 + | ++60 + | ++3 + | ++60 + | ++DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) + | +
| +IBUF_DISABLE_MODE + | ++7:7 + | ++80 + | ++0 + | ++0 + | ++Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. + | +
| +TERM_DISABLE_MODE + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. + | +
| +OUTPUT_EN + | ++10:9 + | ++600 + | ++3 + | ++600 + | ++Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf + | +
| +PULLUP_EN + | ++11:11 + | ++800 + | ++0 + | ++0 + | ++enables pullup on output 0: no pullup 1: pullup enabled + | +
| +DDRIOB_DATA1@0XF8000B4C + | ++31:0 + | ++fff + | ++ + | ++672 + | ++DDR IOB Config for Data 31:16 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_DIFF0 + | ++0XF8000B50 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reserved_INP_POWER + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +INP_TYPE + | ++2:1 + | ++6 + | ++2 + | ++4 + | ++Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. + | +
| +DCI_UPDATE_B + | ++3:3 + | ++8 + | ++0 + | ++0 + | ++DCI Update Enable: 0: disable 1: enable + | +
| +TERM_EN + | ++4:4 + | ++10 + | ++1 + | ++10 + | ++Tri State Termination Enable: 0: disable 1: enable + | +
| +DCI_TYPE + | ++6:5 + | ++60 + | ++3 + | ++60 + | ++DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) + | +
| +IBUF_DISABLE_MODE + | ++7:7 + | ++80 + | ++0 + | ++0 + | ++Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. + | +
| +TERM_DISABLE_MODE + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. + | +
| +OUTPUT_EN + | ++10:9 + | ++600 + | ++3 + | ++600 + | ++Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf + | +
| +PULLUP_EN + | ++11:11 + | ++800 + | ++0 + | ++0 + | ++enables pullup on output 0: no pullup 1: pullup enabled + | +
| +DDRIOB_DIFF0@0XF8000B50 + | ++31:0 + | ++fff + | ++ + | ++674 + | ++DDR IOB Config for DQS 1:0 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_DIFF1 + | ++0XF8000B54 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reserved_INP_POWER + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +INP_TYPE + | ++2:1 + | ++6 + | ++2 + | ++4 + | ++Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. + | +
| +DCI_UPDATE_B + | ++3:3 + | ++8 + | ++0 + | ++0 + | ++DCI Update Enable: 0: disable 1: enable + | +
| +TERM_EN + | ++4:4 + | ++10 + | ++1 + | ++10 + | ++Tri State Termination Enable: 0: disable 1: enable + | +
| +DCI_TYPE + | ++6:5 + | ++60 + | ++3 + | ++60 + | ++DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) + | +
| +IBUF_DISABLE_MODE + | ++7:7 + | ++80 + | ++0 + | ++0 + | ++Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. + | +
| +TERM_DISABLE_MODE + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. + | +
| +OUTPUT_EN + | ++10:9 + | ++600 + | ++3 + | ++600 + | ++Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf + | +
| +PULLUP_EN + | ++11:11 + | ++800 + | ++0 + | ++0 + | ++enables pullup on output 0: no pullup 1: pullup enabled + | +
| +DDRIOB_DIFF1@0XF8000B54 + | ++31:0 + | ++fff + | ++ + | ++674 + | ++DDR IOB Config for DQS 3:2 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_CLOCK + | ++0XF8000B58 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reserved_INP_POWER + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +INP_TYPE + | ++2:1 + | ++6 + | ++0 + | ++0 + | ++Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. + | +
| +DCI_UPDATE_B + | ++3:3 + | ++8 + | ++0 + | ++0 + | ++DCI Update Enable: 0: disable 1: enable + | +
| +TERM_EN + | ++4:4 + | ++10 + | ++0 + | ++0 + | ++Tri State Termination Enable: 0: disable 1: enable + | +
| +DCI_TYPE + | ++6:5 + | ++60 + | ++0 + | ++0 + | ++DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) + | +
| +IBUF_DISABLE_MODE + | ++7:7 + | ++80 + | ++0 + | ++0 + | ++Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. + | +
| +TERM_DISABLE_MODE + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. + | +
| +OUTPUT_EN + | ++10:9 + | ++600 + | ++3 + | ++600 + | ++Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf + | +
| +PULLUP_EN + | ++11:11 + | ++800 + | ++0 + | ++0 + | ++enables pullup on output 0: no pullup 1: pullup enabled + | +
| +DDRIOB_CLOCK@0XF8000B58 + | ++31:0 + | ++fff + | ++ + | ++600 + | ++DDR IOB Config for Clock Output + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_DRIVE_SLEW_ADDR + | ++0XF8000B5C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reserved_DRIVE_P + | ++6:0 + | ++7f + | ++1c + | ++1c + | ++Reserved. Do not modify. + | +
| +reserved_DRIVE_N + | ++13:7 + | ++3f80 + | ++c + | ++600 + | ++Reserved. Do not modify. + | +
| +reserved_SLEW_P + | ++18:14 + | ++7c000 + | ++3 + | ++c000 + | ++Reserved. Do not modify. + | +
| +reserved_SLEW_N + | ++23:19 + | ++f80000 + | ++3 + | ++180000 + | ++Reserved. Do not modify. + | +
| +reserved_GTL + | ++26:24 + | ++7000000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_RTERM + | ++31:27 + | ++f8000000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + | ++31:0 + | ++ffffffff + | ++ + | ++18c61c + | ++Drive and Slew controls for Address and Command pins of the DDR Interface + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_DRIVE_SLEW_DATA + | ++0XF8000B60 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reserved_DRIVE_P + | ++6:0 + | ++7f + | ++1c + | ++1c + | ++Reserved. Do not modify. + | +
| +reserved_DRIVE_N + | ++13:7 + | ++3f80 + | ++c + | ++600 + | ++Reserved. Do not modify. + | +
| +reserved_SLEW_P + | ++18:14 + | ++7c000 + | ++6 + | ++18000 + | ++Reserved. Do not modify. + | +
| +reserved_SLEW_N + | ++23:19 + | ++f80000 + | ++1f + | ++f80000 + | ++Reserved. Do not modify. + | +
| +reserved_GTL + | ++26:24 + | ++7000000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_RTERM + | ++31:27 + | ++f8000000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + | ++31:0 + | ++ffffffff + | ++ + | ++f9861c + | ++Drive and Slew controls for DQ pins of the DDR Interface + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_DRIVE_SLEW_DIFF + | ++0XF8000B64 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reserved_DRIVE_P + | ++6:0 + | ++7f + | ++1c + | ++1c + | ++Reserved. Do not modify. + | +
| +reserved_DRIVE_N + | ++13:7 + | ++3f80 + | ++c + | ++600 + | ++Reserved. Do not modify. + | +
| +reserved_SLEW_P + | ++18:14 + | ++7c000 + | ++6 + | ++18000 + | ++Reserved. Do not modify. + | +
| +reserved_SLEW_N + | ++23:19 + | ++f80000 + | ++1f + | ++f80000 + | ++Reserved. Do not modify. + | +
| +reserved_GTL + | ++26:24 + | ++7000000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_RTERM + | ++31:27 + | ++f8000000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + | ++31:0 + | ++ffffffff + | ++ + | ++f9861c + | ++Drive and Slew controls for DQS pins of the DDR Interface + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_DRIVE_SLEW_CLOCK + | ++0XF8000B68 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reserved_DRIVE_P + | ++6:0 + | ++7f + | ++1c + | ++1c + | ++Reserved. Do not modify. + | +
| +reserved_DRIVE_N + | ++13:7 + | ++3f80 + | ++c + | ++600 + | ++Reserved. Do not modify. + | +
| +reserved_SLEW_P + | ++18:14 + | ++7c000 + | ++6 + | ++18000 + | ++Reserved. Do not modify. + | +
| +reserved_SLEW_N + | ++23:19 + | ++f80000 + | ++1f + | ++f80000 + | ++Reserved. Do not modify. + | +
| +reserved_GTL + | ++26:24 + | ++7000000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_RTERM + | ++31:27 + | ++f8000000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + | ++31:0 + | ++ffffffff + | ++ + | ++f9861c + | ++Drive and Slew controls for Clock pins of the DDR Interface + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_DDR_CTRL + | ++0XF8000B6C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +VREF_INT_EN + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Enables VREF internal generator + | +
| +VREF_SEL + | ++4:1 + | ++1e + | ++4 + | ++8 + | ++Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO + | +
| +VREF_EXT_EN + | ++6:5 + | ++60 + | ++0 + | ++0 + | ++Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits + | +
| +reserved_VREF_PULLUP_EN + | ++8:7 + | ++180 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +REFIO_EN + | ++9:9 + | ++200 + | ++1 + | ++200 + | ++Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio + | +
| +reserved_REFIO_TEST + | ++11:10 + | ++c00 + | ++3 + | ++c00 + | ++Reserved. Do not modify. + | +
| +reserved_REFIO_PULLUP_EN + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_DRST_B_PULLUP_EN + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_CKE_PULLUP_EN + | ++14:14 + | ++4000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +DDRIOB_DDR_CTRL@0XF8000B6C + | ++31:0 + | ++7fff + | ++ + | ++e09 + | ++DDR IOB Buffer Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_DCI_CTRL + | ++0XF8000B70 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +RESET + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++At least toggle once to initialize flops in DCI system + | +
| +DDRIOB_DCI_CTRL@0XF8000B70 + | ++31:0 + | ++1 + | ++ + | ++1 + | ++DDR IOB DCI Config + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_DCI_CTRL + | ++0XF8000B70 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +RESET + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++At least toggle once to initialize flops in DCI system + | +
| +reserved_VRN_OUT + | ++5:5 + | ++20 + | ++1 + | ++20 + | ++Reserved. Do not modify. + | +
| +DDRIOB_DCI_CTRL@0XF8000B70 + | ++31:0 + | ++21 + | ++ + | ++20 + | ++DDR IOB DCI Config + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_DCI_CTRL + | ++0XF8000B70 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +RESET + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++At least toggle once to initialize flops in DCI system + | +
| +ENABLE + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 + | +
| +reserved_VRP_TRI + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_VRN_TRI + | ++3:3 + | ++8 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_VRP_OUT + | ++4:4 + | ++10 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_VRN_OUT + | ++5:5 + | ++20 + | ++1 + | ++20 + | ++Reserved. Do not modify. + | +
| +NREF_OPT1 + | ++7:6 + | ++c0 + | ++0 + | ++0 + | ++DCI Calibration. Use the values in the Calibration Table. + | +
| +NREF_OPT2 + | ++10:8 + | ++700 + | ++0 + | ++0 + | ++DCI Calibration. Use the values in the Calibration Table. + | +
| +NREF_OPT4 + | ++13:11 + | ++3800 + | ++1 + | ++800 + | ++DCI Calibration. Use the values in the Calibration Table. + | +
| +PREF_OPT1 + | ++15:14 + | ++c000 + | ++0 + | ++0 + | ++DCI Calibration. Use the values in the Calibration Table. + | +
| +PREF_OPT2 + | ++19:17 + | ++e0000 + | ++0 + | ++0 + | ++DCI Calibration. Use the values in the Calibration Table. + | +
| +UPDATE_CONTROL + | ++20:20 + | ++100000 + | ++0 + | ++0 + | ++DCI Update Mode. Use the values in the Calibration Table. + | +
| +reserved_INIT_COMPLETE + | ++21:21 + | ++200000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_TST_CLK + | ++22:22 + | ++400000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_TST_HLN + | ++23:23 + | ++800000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_TST_HLP + | ++24:24 + | ++1000000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_TST_RST + | ++25:25 + | ++2000000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_INT_DCI_EN + | ++26:26 + | ++4000000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +DDRIOB_DCI_CTRL@0XF8000B70 + | ++31:0 + | ++7feffff + | ++ + | ++823 + | ++DDR IOB DCI Config + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_00 + | ++0XF8000700 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Tri-state enable, active high. 0: disable 1: enable + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: reserved + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++3 + | ++600 + | ++Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Enables Pullup on IO Buffer pin 0: disable 1: enable + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable + | +
| +MIO_PIN_00@0XF8000700 + | ++31:0 + | ++3fff + | ++ + | ++600 + | ++MIO Pin 0 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_01 + | ++0XF8000704 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: reserved + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++3 + | ++600 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_01@0XF8000704 + | ++31:0 + | ++3fff + | ++ + | ++602 + | ++MIO Pin 1 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_02 + | ++0XF8000708 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++3 + | ++600 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_02@0XF8000708 + | ++31:0 + | ++3fff + | ++ + | ++602 + | ++MIO Pin 2 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_03 + | ++0XF800070C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++3 + | ++600 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_03@0XF800070C + | ++31:0 + | ++3fff + | ++ + | ++602 + | ++MIO Pin 3 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_04 + | ++0XF8000710 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++3 + | ++600 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_04@0XF8000710 + | ++31:0 + | ++3fff + | ++ + | ++602 + | ++MIO Pin 4 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_05 + | ++0XF8000714 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++3 + | ++600 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_05@0XF8000714 + | ++31:0 + | ++3fff + | ++ + | ++602 + | ++MIO Pin 5 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_06 + | ++0XF8000718 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++3 + | ++600 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_06@0XF8000718 + | ++31:0 + | ++3fff + | ++ + | ++602 + | ++MIO Pin 6 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_07 + | ++0XF800071C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: reserved + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++3 + | ++600 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_07@0XF800071C + | ++31:0 + | ++3fff + | ++ + | ++600 + | ++MIO Pin 7 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_08 + | ++0XF8000720 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++3 + | ++600 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_08@0XF8000720 + | ++31:0 + | ++3fff + | ++ + | ++602 + | ++MIO Pin 8 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_09 + | ++0XF8000724 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++3 + | ++600 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_09@0XF8000724 + | ++31:0 + | ++3fff + | ++ + | ++600 + | ++MIO Pin 9 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_10 + | ++0XF8000728 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++3 + | ++600 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_10@0XF8000728 + | ++31:0 + | ++3fff + | ++ + | ++600 + | ++MIO Pin 10 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_11 + | ++0XF800072C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++3 + | ++600 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_11@0XF800072C + | ++31:0 + | ++3fff + | ++ + | ++600 + | ++MIO Pin 11 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_12 + | ++0XF8000730 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++3 + | ++600 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_12@0XF8000730 + | ++31:0 + | ++3fff + | ++ + | ++600 + | ++MIO Pin 12 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_13 + | ++0XF8000734 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++3 + | ++600 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_13@0XF8000734 + | ++31:0 + | ++3fff + | ++ + | ++600 + | ++MIO Pin 13 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_14 + | ++0XF8000738 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1= Not Used + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++3 + | ++600 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_14@0XF8000738 + | ++31:0 + | ++3fff + | ++ + | ++600 + | ++MIO Pin 14 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_15 + | ++0XF800073C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1= Not Used + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++3 + | ++600 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_15@0XF800073C + | ++31:0 + | ++3fff + | ++ + | ++600 + | ++MIO Pin 15 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_16 + | ++0XF8000740 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_16@0XF8000740 + | ++31:0 + | ++3fff + | ++ + | ++202 + | ++MIO Pin 16 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_17 + | ++0XF8000744 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_17@0XF8000744 + | ++31:0 + | ++3fff + | ++ + | ++202 + | ++MIO Pin 17 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_18 + | ++0XF8000748 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_18@0XF8000748 + | ++31:0 + | ++3fff + | ++ + | ++202 + | ++MIO Pin 18 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_19 + | ++0XF800074C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_19@0XF800074C + | ++31:0 + | ++3fff + | ++ + | ++202 + | ++MIO Pin 19 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_20 + | ++0XF8000750 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: reserved + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_20@0XF8000750 + | ++31:0 + | ++3fff + | ++ + | ++202 + | ++MIO Pin 20 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_21 + | ++0XF8000754 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: reserved + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_21@0XF8000754 + | ++31:0 + | ++3fff + | ++ + | ++202 + | ++MIO Pin 21 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_22 + | ++0XF8000758 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_22@0XF8000758 + | ++31:0 + | ++3fff + | ++ + | ++203 + | ++MIO Pin 22 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_23 + | ++0XF800075C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_23@0XF800075C + | ++31:0 + | ++3fff + | ++ + | ++203 + | ++MIO Pin 23 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_24 + | ++0XF8000760 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_24@0XF8000760 + | ++31:0 + | ++3fff + | ++ + | ++203 + | ++MIO Pin 24 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_25 + | ++0XF8000764 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_25@0XF8000764 + | ++31:0 + | ++3fff + | ++ + | ++203 + | ++MIO Pin 25 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_26 + | ++0XF8000768 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_26@0XF8000768 + | ++31:0 + | ++3fff + | ++ + | ++203 + | ++MIO Pin 26 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_27 + | ++0XF800076C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_27@0XF800076C + | ++31:0 + | ++3fff + | ++ + | ++203 + | ++MIO Pin 27 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_28 + | ++0XF8000770 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++1 + | ++4 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_28@0XF8000770 + | ++31:0 + | ++3fff + | ++ + | ++204 + | ++MIO Pin 28 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_29 + | ++0XF8000774 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++1 + | ++4 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_29@0XF8000774 + | ++31:0 + | ++3fff + | ++ + | ++205 + | ++MIO Pin 29 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_30 + | ++0XF8000778 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++1 + | ++4 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_30@0XF8000778 + | ++31:0 + | ++3fff + | ++ + | ++204 + | ++MIO Pin 30 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_31 + | ++0XF800077C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++1 + | ++4 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_31@0XF800077C + | ++31:0 + | ++3fff + | ++ + | ++205 + | ++MIO Pin 31 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_32 + | ++0XF8000780 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++1 + | ++4 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_32@0XF8000780 + | ++31:0 + | ++3fff + | ++ + | ++204 + | ++MIO Pin 32 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_33 + | ++0XF8000784 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++1 + | ++4 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_33@0XF8000784 + | ++31:0 + | ++3fff + | ++ + | ++204 + | ++MIO Pin 33 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_34 + | ++0XF8000788 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++1 + | ++4 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_34@0XF8000788 + | ++31:0 + | ++3fff + | ++ + | ++204 + | ++MIO Pin 34 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_35 + | ++0XF800078C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++1 + | ++4 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_35@0XF800078C + | ++31:0 + | ++3fff + | ++ + | ++204 + | ++MIO Pin 35 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_36 + | ++0XF8000790 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++1 + | ++4 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_36@0XF8000790 + | ++31:0 + | ++3fff + | ++ + | ++205 + | ++MIO Pin 36 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_37 + | ++0XF8000794 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++1 + | ++4 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_37@0XF8000794 + | ++31:0 + | ++3fff + | ++ + | ++204 + | ++MIO Pin 37 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_38 + | ++0XF8000798 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++1 + | ++4 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_38@0XF8000798 + | ++31:0 + | ++3fff + | ++ + | ++204 + | ++MIO Pin 38 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_39 + | ++0XF800079C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++1 + | ++4 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_39@0XF800079C + | ++31:0 + | ++3fff + | ++ + | ++204 + | ++MIO Pin 39 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_40 + | ++0XF80007A0 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: reserved + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++4 + | ++80 + | ++Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_40@0XF80007A0 + | ++31:0 + | ++3fff + | ++ + | ++280 + | ++MIO Pin 40 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_41 + | ++0XF80007A4 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: reserved + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++4 + | ++80 + | ++Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_41@0XF80007A4 + | ++31:0 + | ++3fff + | ++ + | ++280 + | ++MIO Pin 41 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_42 + | ++0XF80007A8 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1= Not Used + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++4 + | ++80 + | ++Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_42@0XF80007A8 + | ++31:0 + | ++3fff + | ++ + | ++280 + | ++MIO Pin 42 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_43 + | ++0XF80007AC + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: reserved + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++4 + | ++80 + | ++Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_43@0XF80007AC + | ++31:0 + | ++3fff + | ++ + | ++280 + | ++MIO Pin 43 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_44 + | ++0XF80007B0 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: reserved + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++4 + | ++80 + | ++Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_44@0XF80007B0 + | ++31:0 + | ++3fff + | ++ + | ++280 + | ++MIO Pin 44 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_45 + | ++0XF80007B4 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: reserved + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++4 + | ++80 + | ++Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_45@0XF80007B4 + | ++31:0 + | ++3fff + | ++ + | ++280 + | ++MIO Pin 45 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_46 + | ++0XF80007B8 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_46@0XF80007B8 + | ++31:0 + | ++3f01 + | ++ + | ++201 + | ++MIO Pin 46 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_47 + | ++0XF80007BC + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: reserved + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3, Input/Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 47 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_47@0XF80007BC + | ++31:0 + | ++3fff + | ++ + | ++200 + | ++MIO Pin 47 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_48 + | ++0XF80007C0 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: reserved + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++7 + | ++e0 + | ++Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_48@0XF80007C0 + | ++31:0 + | ++3fff + | ++ + | ++2e0 + | ++MIO Pin 48 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_49 + | ++0XF80007C4 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: reserved + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++7 + | ++e0 + | ++Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_49@0XF80007C4 + | ++31:0 + | ++3fff + | ++ + | ++2e1 + | ++MIO Pin 49 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_50 + | ++0XF80007C8 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_50@0XF80007C8 + | ++31:0 + | ++3f01 + | ++ + | ++201 + | ++MIO Pin 50 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_51 + | ++0XF80007CC + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: reserved + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++0 + | ++0 + | ++Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_51@0XF80007CC + | ++31:0 + | ++3fff + | ++ + | ++200 + | ++MIO Pin 51 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_52 + | ++0XF80007D0 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: reserved + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: reserved + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++4 + | ++80 + | ++Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_52@0XF80007D0 + | ++31:0 + | ++3fff + | ++ + | ++280 + | ++MIO Pin 52 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MIO_PIN_53 + | ++0XF80007D4 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +TRI_ENABLE + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[TRI_ENABLE] + | +
| +L0_SEL + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++Level 0 Mux Select 0: Level 1 Mux 1: reserved + | +
| +L1_SEL + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++Level 1 Mux Select 0: Level 2 Mux 1: reserved + | +
| +L2_SEL + | ++4:3 + | ++18 + | ++0 + | ++0 + | ++Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output + | +
| +L3_SEL + | ++7:5 + | ++e0 + | ++4 + | ++80 + | ++Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input + | +
| +Speed + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[Speed] + | +
| +IO_Type + | ++11:9 + | ++e00 + | ++1 + | ++200 + | ++Operates the same as MIO_PIN_00[IO_Type] + | +
| +PULLUP + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[PULLUP] + | +
| +DisableRcvr + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Operates the same as MIO_PIN_00[DisableRcvr] + | +
| +MIO_PIN_53@0XF80007D4 + | ++31:0 + | ++3fff + | ++ + | ++280 + | ++MIO Pin 53 Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +SD0_WP_CD_SEL + | ++0XF8000830 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +SDIO0_WP_SEL + | ++5:0 + | ++3f + | ++32 + | ++32 + | ++SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input + | +
| +SDIO0_CD_SEL + | ++21:16 + | ++3f0000 + | ++2e + | ++2e0000 + | ++SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input + | +
| +SD0_WP_CD_SEL@0XF8000830 + | ++31:0 + | ++3f003f + | ++ + | ++2e0032 + | ++SDIO 0 WP CD select + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +SLCR_LOCK + | ++0XF8000004 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +LOCK_KEY + | ++15:0 + | ++ffff + | ++767b + | ++767b + | ++Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. + | +
| +SLCR_LOCK@0XF8000004 + | ++31:0 + | ++ffff + | ++ + | ++767b + | ++SLCR Write Protection Lock + | +
+
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| + +SLCR_UNLOCK + + | ++0XF8000008 + | ++32 + | ++WO + | ++0x000000 + | ++SLCR Write Protection Unlock + | +
| + +DDRIOB_DATA0 + + | ++0XF8000B48 + | ++32 + | ++RW + | ++0x000000 + | ++DDR IOB Config for Data 15:0 + | +
| + +DDRIOB_DATA1 + + | ++0XF8000B4C + | ++32 + | ++RW + | ++0x000000 + | ++DDR IOB Config for Data 31:16 + | +
| + +DDRIOB_DIFF0 + + | ++0XF8000B50 + | ++32 + | ++RW + | ++0x000000 + | ++DDR IOB Config for DQS 1:0 + | +
| + +DDRIOB_DIFF1 + + | ++0XF8000B54 + | ++32 + | ++RW + | ++0x000000 + | ++DDR IOB Config for DQS 3:2 + | +
| + +SLCR_LOCK + + | ++0XF8000004 + | ++32 + | ++WO + | ++0x000000 + | ++SLCR Write Protection Lock + | +
| + +Baud_rate_divider_reg0 + + | ++0XE0001034 + | ++32 + | ++RW + | ++0x000000 + | ++Baud Rate Divider Register + | +
| + +Baud_rate_gen_reg0 + + | ++0XE0001018 + | ++32 + | ++RW + | ++0x000000 + | ++Baud Rate Generator Register. + | +
| + +Control_reg0 + + | ++0XE0001000 + | ++32 + | ++RW + | ++0x000000 + | ++UART Control Register + | +
| + +mode_reg0 + + | ++0XE0001004 + | ++32 + | ++RW + | ++0x000000 + | ++UART Mode Register + | +
| + +Config_reg + + | ++0XE000D000 + | ++32 + | ++RW + | ++0x000000 + | ++SPI configuration register + | +
| + +CTRL + + | ++0XF8007000 + | ++32 + | ++RW + | ++0x000000 + | ++Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. + | +
| + +DIRM_0 + + | ++0XE000A204 + | ++32 + | ++RW + | ++0x000000 + | ++Direction mode (GPIO Bank0, MIO) + | +
| + +MASK_DATA_0_LSW + + | ++0XE000A000 + | ++32 + | ++RW + | ++0x000000 + | ++Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) + | +
| + +OEN_0 + + | ++0XE000A208 + | ++32 + | ++RW + | ++0x000000 + | ++Output enable (GPIO Bank0, MIO) + | +
| + +MASK_DATA_0_LSW + + | ++0XE000A000 + | ++32 + | ++RW + | ++0x000000 + | ++Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) + | +
| + +MASK_DATA_0_LSW + + | ++0XE000A000 + | ++32 + | ++RW + | ++0x000000 + | ++Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +SLCR_UNLOCK + | ++0XF8000008 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +UNLOCK_KEY + | ++15:0 + | ++ffff + | ++df0d + | ++df0d + | ++Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. + | +
| +SLCR_UNLOCK@0XF8000008 + | ++31:0 + | ++ffff + | ++ + | ++df0d + | ++SLCR Write Protection Unlock + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_DATA0 + | ++0XF8000B48 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +IBUF_DISABLE_MODE + | ++7:7 + | ++80 + | ++1 + | ++80 + | ++Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. + | +
| +TERM_DISABLE_MODE + | ++8:8 + | ++100 + | ++1 + | ++100 + | ++Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. + | +
| +DDRIOB_DATA0@0XF8000B48 + | ++31:0 + | ++180 + | ++ + | ++180 + | ++DDR IOB Config for Data 15:0 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_DATA1 + | ++0XF8000B4C + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +IBUF_DISABLE_MODE + | ++7:7 + | ++80 + | ++1 + | ++80 + | ++Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. + | +
| +TERM_DISABLE_MODE + | ++8:8 + | ++100 + | ++1 + | ++100 + | ++Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. + | +
| +DDRIOB_DATA1@0XF8000B4C + | ++31:0 + | ++180 + | ++ + | ++180 + | ++DDR IOB Config for Data 31:16 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_DIFF0 + | ++0XF8000B50 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +IBUF_DISABLE_MODE + | ++7:7 + | ++80 + | ++1 + | ++80 + | ++Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. + | +
| +TERM_DISABLE_MODE + | ++8:8 + | ++100 + | ++1 + | ++100 + | ++Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. + | +
| +DDRIOB_DIFF0@0XF8000B50 + | ++31:0 + | ++180 + | ++ + | ++180 + | ++DDR IOB Config for DQS 1:0 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DDRIOB_DIFF1 + | ++0XF8000B54 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +IBUF_DISABLE_MODE + | ++7:7 + | ++80 + | ++1 + | ++80 + | ++Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. + | +
| +TERM_DISABLE_MODE + | ++8:8 + | ++100 + | ++1 + | ++100 + | ++Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. + | +
| +DDRIOB_DIFF1@0XF8000B54 + | ++31:0 + | ++180 + | ++ + | ++180 + | ++DDR IOB Config for DQS 3:2 + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +SLCR_LOCK + | ++0XF8000004 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +LOCK_KEY + | ++15:0 + | ++ffff + | ++767b + | ++767b + | ++Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. + | +
| +SLCR_LOCK@0XF8000004 + | ++31:0 + | ++ffff + | ++ + | ++767b + | ++SLCR Write Protection Lock + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +Baud_rate_divider_reg0 + | ++0XE0001034 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +BDIV + | ++7:0 + | ++ff + | ++6 + | ++6 + | ++Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate + | +
| +Baud_rate_divider_reg0@0XE0001034 + | ++31:0 + | ++ff + | ++ + | ++6 + | ++Baud Rate Divider Register + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +Baud_rate_gen_reg0 + | ++0XE0001018 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +CD + | ++15:0 + | ++ffff + | ++3e + | ++3e + | ++Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + | +
| +Baud_rate_gen_reg0@0XE0001018 + | ++31:0 + | ++ffff + | ++ + | ++3e + | ++Baud Rate Generator Register. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +Control_reg0 + | ++0XE0001000 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +STPBRK + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. + | +
| +STTBRK + | ++7:7 + | ++80 + | ++0 + | ++0 + | ++Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. + | +
| +RSTTO + | ++6:6 + | ++40 + | ++0 + | ++0 + | ++Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. + | +
| +TXDIS + | ++5:5 + | ++20 + | ++0 + | ++0 + | ++Transmit disable: 0: enable transmitter 1: disable transmitter + | +
| +TXEN + | ++4:4 + | ++10 + | ++1 + | ++10 + | ++Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. + | +
| +RXDIS + | ++3:3 + | ++8 + | ++0 + | ++0 + | ++Receive disable: 0: enable 1: disable, regardless of the value of RXEN + | +
| +RXEN + | ++2:2 + | ++4 + | ++1 + | ++4 + | ++Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. + | +
| +TXRES + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. + | +
| +RXRES + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. + | +
| +Control_reg0@0XE0001000 + | ++31:0 + | ++1ff + | ++ + | ++17 + | ++UART Control Register + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +mode_reg0 + | ++0XE0001004 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +CHMODE + | ++9:8 + | ++300 + | ++0 + | ++0 + | ++Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback + | +
| +NBSTOP + | ++7:6 + | ++c0 + | ++0 + | ++0 + | ++Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved + | +
| +PAR + | ++5:3 + | ++38 + | ++4 + | ++20 + | ++Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity + | +
| +CHRL + | ++2:1 + | ++6 + | ++0 + | ++0 + | ++Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits + | +
| +CLKS + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 + | +
| +mode_reg0@0XE0001004 + | ++31:0 + | ++3ff + | ++ + | ++20 + | ++UART Mode Register + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +Config_reg + | ++0XE000D000 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +Holdb_dr + | ++19:19 + | ++80000 + | ++1 + | ++80000 + | ++If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI + | +
| +Config_reg@0XE000D000 + | ++31:0 + | ++80000 + | ++ + | ++80000 + | ++SPI configuration register + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +CTRL + | ++0XF8007000 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +PCFG_POR_CNT_4K + | ++29:29 + | ++20000000 + | ++0 + | ++0 + | ++This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer + | +
| +CTRL@0XF8007000 + | ++31:0 + | ++20000000 + | ++ + | ++0 + | ++Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +DIRM_0 + | ++0XE000A204 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +DIRECTION_0 + | ++31:0 + | ++ffffffff + | ++80 + | ++80 + | ++Direction mode 0: input 1: output Each bit configures the corresponding pin within the 32-bit bank NOTE: bits[8:7] of bank0 cannot be used as inputs. The DIRM bits can be set to 0, but reading DATA_RO does not reflect the input value. See the GPIO chapter for more information. + | +
| +DIRM_0@0XE000A204 + | ++31:0 + | ++ffffffff + | ++ + | ++80 + | ++Direction mode (GPIO Bank0, MIO) + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MASK_DATA_0_LSW + | ++0XE000A000 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +MASK_0_LSW + | ++31:16 + | ++ffff0000 + | ++ff7f + | ++ff7f0000 + | ++On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. + | +
| +DATA_0_LSW + | ++15:0 + | ++ffff + | ++80 + | ++80 + | ++On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. + | +
| +MASK_DATA_0_LSW@0XE000A000 + | ++31:0 + | ++ffffffff + | ++ + | ++ff7f0080 + | ++Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +OEN_0 + | ++0XE000A208 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +OP_ENABLE_0 + | ++31:0 + | ++ffffffff + | ++80 + | ++80 + | ++Output enables 0: disabled 1: enabled Each bit configures the corresponding pin within the 32-bit bank + | +
| +OEN_0@0XE000A208 + | ++31:0 + | ++ffffffff + | ++ + | ++80 + | ++Output enable (GPIO Bank0, MIO) + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MASK_DATA_0_LSW + | ++0XE000A000 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +MASK_0_LSW + | ++31:16 + | ++ffff0000 + | ++ff7f + | ++ff7f0000 + | ++On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. + | +
| +DATA_0_LSW + | ++15:0 + | ++ffff + | ++0 + | ++0 + | ++On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. + | +
| +MASK_DATA_0_LSW@0XE000A000 + | ++31:0 + | ++ffffffff + | ++ + | ++ff7f0000 + | ++Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +MASK_DATA_0_LSW + | ++0XE000A000 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +MASK_0_LSW + | ++31:16 + | ++ffff0000 + | ++ff7f + | ++ff7f0000 + | ++On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. + | +
| +DATA_0_LSW + | ++15:0 + | ++ffff + | ++80 + | ++80 + | ++On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. + | +
| +MASK_DATA_0_LSW@0XE000A000 + | ++31:0 + | ++ffffffff + | ++ + | ++ff7f0080 + | ++Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) + | +
+
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| + +SLCR_UNLOCK + + | ++0XF8000008 + | ++32 + | ++WO + | ++0x000000 + | ++SLCR Write Protection Unlock + | +
| + +LVL_SHFTR_EN + + | ++0XF8000900 + | ++32 + | ++RW + | ++0x000000 + | ++Level Shifters Enable + | +
| + +FPGA_RST_CTRL + + | ++0XF8000240 + | ++32 + | ++RW + | ++0x000000 + | ++FPGA Software Reset Control + | +
| + +SLCR_LOCK + + | ++0XF8000004 + | ++32 + | ++WO + | ++0x000000 + | ++SLCR Write Protection Lock + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +SLCR_UNLOCK + | ++0XF8000008 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +UNLOCK_KEY + | ++15:0 + | ++ffff + | ++df0d + | ++df0d + | ++Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. + | +
| +SLCR_UNLOCK@0XF8000008 + | ++31:0 + | ++ffff + | ++ + | ++df0d + | ++SLCR Write Protection Unlock + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +LVL_SHFTR_EN + | ++0XF8000900 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +USER_LVL_INP_EN_0 + | ++3:3 + | ++8 + | ++1 + | ++8 + | ++Level shifter enable to drive signals from PL to PS + | +
| +USER_LVL_OUT_EN_0 + | ++2:2 + | ++4 + | ++1 + | ++4 + | ++Level shifter enable to drive signals from PS to PL + | +
| +USER_LVL_INP_EN_1 + | ++1:1 + | ++2 + | ++1 + | ++2 + | ++Level shifter enable to drive signals from PL to PS + | +
| +USER_LVL_OUT_EN_1 + | ++0:0 + | ++1 + | ++1 + | ++1 + | ++Level shifter enable to drive signals from PS to PL + | +
| +LVL_SHFTR_EN@0XF8000900 + | ++31:0 + | ++f + | ++ + | ++f + | ++Level Shifters Enable + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +FPGA_RST_CTRL + | ++0XF8000240 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +reserved_3 + | ++31:25 + | ++fe000000 + | ++0 + | ++0 + | ++Reserved. Writes are ignored, read data is zero. + | +
| +reserved_FPGA_ACP_RST + | ++24:24 + | ++1000000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_FPGA_AXDS3_RST + | ++23:23 + | ++800000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_FPGA_AXDS2_RST + | ++22:22 + | ++400000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_FPGA_AXDS1_RST + | ++21:21 + | ++200000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_FPGA_AXDS0_RST + | ++20:20 + | ++100000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_2 + | ++19:18 + | ++c0000 + | ++0 + | ++0 + | ++Reserved. Writes are ignored, read data is zero. + | +
| +reserved_FSSW1_FPGA_RST + | ++17:17 + | ++20000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_FSSW0_FPGA_RST + | ++16:16 + | ++10000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_1 + | ++15:14 + | ++c000 + | ++0 + | ++0 + | ++Reserved. Writes are ignored, read data is zero. + | +
| +reserved_FPGA_FMSW1_RST + | ++13:13 + | ++2000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_FPGA_FMSW0_RST + | ++12:12 + | ++1000 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_FPGA_DMA3_RST + | ++11:11 + | ++800 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_FPGA_DMA2_RST + | ++10:10 + | ++400 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_FPGA_DMA1_RST + | ++9:9 + | ++200 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved_FPGA_DMA0_RST + | ++8:8 + | ++100 + | ++0 + | ++0 + | ++Reserved. Do not modify. + | +
| +reserved + | ++7:4 + | ++f0 + | ++0 + | ++0 + | ++Reserved. Writes are ignored, read data is zero. + | +
| +FPGA3_OUT_RST + | ++3:3 + | ++8 + | ++0 + | ++0 + | ++PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) + | +
| +FPGA2_OUT_RST + | ++2:2 + | ++4 + | ++0 + | ++0 + | ++PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) + | +
| +FPGA1_OUT_RST + | ++1:1 + | ++2 + | ++0 + | ++0 + | ++PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) + | +
| +FPGA0_OUT_RST + | ++0:0 + | ++1 + | ++0 + | ++0 + | ++PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) + | +
| +FPGA_RST_CTRL@0XF8000240 + | ++31:0 + | ++ffffffff + | ++ + | ++0 + | ++FPGA Software Reset Control + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +SLCR_LOCK + | ++0XF8000004 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +LOCK_KEY + | ++15:0 + | ++ffff + | ++767b + | ++767b + | ++Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. + | +
| +SLCR_LOCK@0XF8000004 + | ++31:0 + | ++ffff + | ++ + | ++767b + | ++SLCR Write Protection Lock + | +
+
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| + +LAR + + | ++0XF8898FB0 + | ++32 + | ++WO + | ++0x000000 + | ++Lock Access Register + | +
| + +LAR + + | ++0XF8899FB0 + | ++32 + | ++WO + | ++0x000000 + | ++Lock Access Register + | +
| + +LAR + + | ++0XF8809FB0 + | ++32 + | ++WO + | ++0x000000 + | ++Lock Access Register + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +LAR + | ++0XF8898FB0 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +KEY + | ++31:0 + | ++ffffffff + | ++c5acce55 + | ++c5acce55 + | ++Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. + | +
| +LAR@0XF8898FB0 + | ++31:0 + | ++ffffffff + | ++ + | ++c5acce55 + | ++Lock Access Register + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +LAR + | ++0XF8899FB0 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +KEY + | ++31:0 + | ++ffffffff + | ++c5acce55 + | ++c5acce55 + | ++Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. + | +
| +LAR@0XF8899FB0 + | ++31:0 + | ++ffffffff + | ++ + | ++c5acce55 + | ++Lock Access Register + | +
+
| +Register Name + | ++Address + | ++Width + | ++Type + | ++Reset Value + | ++Description + | +
| +LAR + | ++0XF8809FB0 + | ++32 + | ++rw + | ++0x00000000 + | ++-- + | +
+
| +Field Name + | ++Bits + | ++Mask + | ++Value + | ++Shifted Value + | ++Description + | +
| +KEY + | ++31:0 + | ++ffffffff + | ++c5acce55 + | ++c5acce55 + | ++Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. + | +
| +LAR@0XF8809FB0 + | ++31:0 + | ++ffffffff + | ++ + | ++c5acce55 + | ++Lock Access Register + | +
+
+ + + +