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m.twr
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m.twr
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--------------------------------------------------------------------------------
Release 14.7 Trace (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 4
-n 3 -fastpaths -xml m.twx m.ncd -o m.twr m.pcf -ucf initialize.ucf
Design file: m.ncd
Physical constraint file: m.pcf
Device,package,speed: xc3s400,tq144,-4 (PRODUCTION 1.39 2013-10-13)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter
value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
'Phase Error' calculations, these terms will be zero in the Clock
Uncertainty calculation. Please make appropriate modification to
SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
Error.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
DATA_CLK | 8.544(R)| -0.545(R)|clk_BUFGP | 0.000|
DATA_IN<0> | 5.659(R)| 1.167(R)|clk_BUFGP | 0.000|
DATA_IN<1> | 5.807(R)| 0.925(R)|clk_BUFGP | 0.000|
DATA_IN<2> | 5.927(R)| 1.168(R)|clk_BUFGP | 0.000|
DATA_IN<3> | 6.693(R)| 0.604(R)|clk_BUFGP | 0.000|
DATA_IN<4> | 5.982(R)| 0.781(R)|clk_BUFGP | 0.000|
DATA_IN<5> | 5.710(R)| 1.234(R)|clk_BUFGP | 0.000|
DATA_IN<6> | 5.405(R)| 0.861(R)|clk_BUFGP | 0.000|
HALL11 | 2.799(R)| 0.307(R)|clk_BUFGP | 0.000|
HALL12 | 3.020(R)| 0.147(R)|clk_BUFGP | 0.000|
HALL13 | 3.099(R)| 0.055(R)|clk_BUFGP | 0.000|
HALL14 | 1.956(R)| 0.909(R)|clk_BUFGP | 0.000|
HALL21 | 2.370(R)| -0.407(R)|clk_BUFGP | 0.000|
HALL22 | 2.619(R)| 0.015(R)|clk_BUFGP | 0.000|
HALL23 | 3.031(R)| 0.151(R)|clk_BUFGP | 0.000|
HALL24 | 0.741(R)| 0.882(R)|clk_BUFGP | 0.000|
HALL31 | 1.611(R)| 0.186(R)|clk_BUFGP | 0.000|
HALL32 | 1.703(R)| 0.106(R)|clk_BUFGP | 0.000|
HALL33 | 0.961(R)| 0.706(R)|clk_BUFGP | 0.000|
HALL34 | 0.647(R)| 0.957(R)|clk_BUFGP | 0.000|
TXE | 4.386(R)| -0.484(R)|clk_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Clock clk to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
DATA_OUT<0> | 9.624(R)|clk_BUFGP | 0.000|
DATA_OUT<1> | 9.554(R)|clk_BUFGP | 0.000|
DATA_OUT<2> | 10.611(R)|clk_BUFGP | 0.000|
DATA_OUT<3> | 10.793(R)|clk_BUFGP | 0.000|
DATA_OUT<4> | 10.680(R)|clk_BUFGP | 0.000|
DATA_OUT<5> | 9.930(R)|clk_BUFGP | 0.000|
DATA_OUT<6> | 9.591(R)|clk_BUFGP | 0.000|
DATA_USB<4> | 9.929(R)|clk_BUFGP | 0.000|
DATA_USB<5> | 8.409(R)|clk_BUFGP | 0.000|
DATA_USB<6> | 9.218(R)|clk_BUFGP | 0.000|
DATA_USB<7> | 8.449(R)|clk_BUFGP | 0.000|
HALL_OUT | 8.454(R)|clk_BUFGP | 0.000|
LED<1> | 15.455(R)|clk_BUFGP | 0.000|
LED<2> | 15.102(R)|clk_BUFGP | 0.000|
LED<3> | 14.082(R)|clk_BUFGP | 0.000|
M1n1 | 12.890(R)|clk_BUFGP | 0.000|
M1n2 | 11.408(R)|clk_BUFGP | 0.000|
M1n3 | 12.362(R)|clk_BUFGP | 0.000|
M1n4 | 10.952(R)|clk_BUFGP | 0.000|
M1p1 | 11.639(R)|clk_BUFGP | 0.000|
M1p2 | 10.994(R)|clk_BUFGP | 0.000|
M1p3 | 12.258(R)|clk_BUFGP | 0.000|
M1p4 | 10.150(R)|clk_BUFGP | 0.000|
M2n1 | 12.056(R)|clk_BUFGP | 0.000|
M2n2 | 11.565(R)|clk_BUFGP | 0.000|
M2n3 | 12.270(R)|clk_BUFGP | 0.000|
M2n4 | 11.554(R)|clk_BUFGP | 0.000|
M2p1 | 11.311(R)|clk_BUFGP | 0.000|
M2p2 | 11.164(R)|clk_BUFGP | 0.000|
M2p3 | 12.412(R)|clk_BUFGP | 0.000|
M2p4 | 10.327(R)|clk_BUFGP | 0.000|
M3n1 | 12.379(R)|clk_BUFGP | 0.000|
M3n2 | 11.941(R)|clk_BUFGP | 0.000|
M3n3 | 12.145(R)|clk_BUFGP | 0.000|
M3n4 | 11.724(R)|clk_BUFGP | 0.000|
M3p1 | 11.528(R)|clk_BUFGP | 0.000|
M3p2 | 11.740(R)|clk_BUFGP | 0.000|
M3p3 | 11.720(R)|clk_BUFGP | 0.000|
M3p4 | 10.379(R)|clk_BUFGP | 0.000|
USB_WR | 9.763(R)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 30.819| | | |
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
TEST_KEY<0> |LED<1> | 12.315|
TEST_KEY<0> |LED<2> | 12.306|
TEST_KEY<0> |LED<3> | 11.652|
TEST_KEY<1> |LED<1> | 12.106|
TEST_KEY<1> |LED<2> | 12.552|
TEST_KEY<1> |LED<3> | 11.822|
---------------+---------------+---------+
Analysis completed Fri Jul 17 16:49:01 2015
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 205 MB