diff --git a/3x_ov7670_st7735_16bit.gif b/3x_ov7670_st7735_16bit.gif
new file mode 100755
index 0000000..31d9505
Binary files /dev/null and b/3x_ov7670_st7735_16bit.gif differ
diff --git a/4cam_qqvga_16bitvga.gif b/4cam_qqvga_16bitvga.gif
new file mode 100755
index 0000000..fb384e7
Binary files /dev/null and b/4cam_qqvga_16bitvga.gif differ
diff --git a/README.md b/README.md
new file mode 100755
index 0000000..eac5d04
--- /dev/null
+++ b/README.md
@@ -0,0 +1,13 @@
+#
+[lcd_rotate.gif](lcd_rotate.gif)
+[pwm_led.gif](pwm_led.gif)
+[digital_clock.gif](digital_clock.gif)
+[gof_glidergun_st7735r.gif](gof_glidergun_st7735r.gif)
+[gof_glidergun_ssd1306_32x32.gif](gof_glidergun_ssd1306_32x32.gif)
+[adc.gif](adc.gif)
+[ladder_r2r.gif](ladder_r2r.gif)
+[simple_logicanalyser.gif](simple_logicanalyser.gif)
+[simple_monitoring_4x_camera.gif](simple_monitoring_4x_camera.gif)
+[3x_ov7670_st7735_16bit.gif](3x_ov7670_st7735_16bit.gif)
+[4cam_qqvga_16bitvga.gif](4cam_qqvga_16bitvga.gif)
+#
diff --git a/adc.gif b/adc.gif
new file mode 100755
index 0000000..c87b03d
Binary files /dev/null and b/adc.gif differ
diff --git a/adc_counter/adc_counter.ucf b/adc_counter/adc_counter.ucf
new file mode 100755
index 0000000..bc1ca3f
--- /dev/null
+++ b/adc_counter/adc_counter.ucf
@@ -0,0 +1,36 @@
+
+NET "i_clock" LOC = "B8";
+NET "i_reset" LOC = "B18";
+#NET "BUTTON<1>" LOC = "D18";
+
+NET "io_ladder<11>" LOC = "L15";
+NET "io_ladder<10>" LOC = "K12";
+NET "io_ladder<9>" LOC = "L17";
+NET "io_ladder<8>" LOC = "M15";
+NET "io_ladder<7>" LOC = "K13";
+NET "io_ladder<6>" LOC = "L16";
+NET "io_ladder<5>" LOC = "M14";
+NET "io_ladder<4>" LOC = "M16";
+
+NET "io_ladder<3>" LOC = "M13";
+NET "io_ladder<2>" LOC = "R18";
+NET "io_ladder<1>" LOC = "R15";
+NET "io_ladder<0>" LOC = "T17";
+NET "i_from_comparator" LOC = "P17";
+NET "o_eoc" LOC = "R16";
+#NET "JB<6>" LOC = "T18";
+#NET "JB<7>" LOC = "U18";
+
+NET "o_segment<0>" LOC = "L18";
+NET "o_segment<1>" LOC = "F18";
+NET "o_segment<2>" LOC = "D17";
+NET "o_segment<3>" LOC = "D16";
+NET "o_segment<4>" LOC = "G14";
+NET "o_segment<5>" LOC = "J17";
+NET "o_segment<6>" LOC = "H14";
+#NET "o_dp" LOC = "C17";
+
+NET "o_anode<0>" LOC = "F17";
+NET "o_anode<1>" LOC = "H17";
+NET "o_anode<2>" LOC = "C18";
+NET "o_anode<3>" LOC = "F15";
diff --git a/adc_counter/adc_counter.vhd b/adc_counter/adc_counter.vhd
new file mode 100755
index 0000000..ddb3b01
--- /dev/null
+++ b/adc_counter/adc_counter.vhd
@@ -0,0 +1,142 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:47:54 05/07/2021
+-- Design Name:
+-- Module Name: sar_adc - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_globals.ALL;
+use WORK.p_lcd_display.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity adc_counter is
+Generic (
+G_BOARD_CLOCK : integer := G_BOARD_CLOCK;
+data_size : integer := 12
+);
+Port (
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_from_comparator : in std_logic;
+io_ladder : out std_logic_vector(data_size-1 downto 0);
+o_anode : out std_logic_vector(G_LCDAnode-1 downto 0);
+o_segment : out std_logic_vector(G_LCDSegment-1 downto 0);
+o_eoc : out std_logic
+);
+end adc_counter;
+
+architecture Behavioral of adc_counter is
+
+component lcd_display is
+Generic (
+LCDClockDivider : integer := G_LCDClockDivider -- XXX in ms
+);
+Port (
+i_clock : in std_logic;
+i_LCDChar : LCDHex;
+o_anode : out std_logic_vector(G_LCDAnode-1 downto 0);
+o_segment : out std_logic_vector(G_LCDSegment-1 downto 0)
+);
+end component lcd_display;
+
+signal divclock : std_logic;
+signal LCDChar : LCDHex;
+
+begin
+
+p_clockdivider : process (i_clock,i_reset) is
+ constant count_max : integer := G_BOARD_CLOCK/1000;
+ variable count : integer range 0 to count_max-1 := 0;
+begin
+ if (i_reset = '1') then
+ count := 0;
+ divclock <= '0';
+ elsif (rising_edge(i_clock)) then
+ if (count = count_max-1) then
+ count := 0;
+ divclock <= '1';
+ else
+ count := count + 1;
+ divclock <= '0';
+ end if;
+ end if;
+end process p_clockdivider;
+
+p_comparator : process (divclock,i_reset) is
+ variable a : std_logic;
+ constant ccount : integer := 2**data_size;
+ variable count : integer range 0 to ccount-1 := 0;
+ variable veoc : std_logic;
+ variable vladder : std_logic_vector(data_size-1 downto 0);
+begin
+ if (i_reset = '1') then
+ count := 0;
+ a := '0';
+ veoc := '0';
+ vladder := (others => '0');
+ elsif (rising_edge(divclock)) then
+-- a := not i_from_comparator; -- XXX maybe with S&H
+ a := i_from_comparator;
+ case (a) is
+ when '0' =>
+ if (count = ccount-1) then
+ count := ccount-1;
+ veoc := '1';
+ else
+ count := count + 1;
+ veoc := '0';
+ end if;
+ vladder := std_logic_vector(to_unsigned(count,data_size));
+ when '1' =>
+ if (count = 0) then
+ count := 0;
+ veoc := '1';
+ else
+ count := count - 1;
+ veoc := '0';
+ end if;
+ vladder := std_logic_vector(to_unsigned(count,data_size));
+ when others =>
+ count := 0;
+ veoc := '0';
+ end case;
+ o_eoc <= veoc;
+ io_ladder <= vladder;
+ LCDChar <= (vladder(3 downto 0),vladder(7 downto 4),vladder(11 downto 8),x"0");
+ end if;
+end process p_comparator;
+
+lcddisplay_entity : lcd_display
+generic map (
+LCDClockDivider => 4 -- XXX in ms
+)
+port map (
+i_clock => i_clock,
+i_LCDChar => LCDChar,
+o_anode => o_anode,
+o_segment => o_segment
+);
+
+end Behavioral;
diff --git a/adc_counter/adc_counter.xise b/adc_counter/adc_counter.xise
new file mode 100755
index 0000000..78b3828
--- /dev/null
+++ b/adc_counter/adc_counter.xise
@@ -0,0 +1,369 @@
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diff --git a/adc_counter/clock_divider.vhd b/adc_counter/clock_divider.vhd
new file mode 100755
index 0000000..04f2606
--- /dev/null
+++ b/adc_counter/clock_divider.vhd
@@ -0,0 +1,65 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:42:10 09/18/2020
+-- Design Name:
+-- Module Name: clock_divider - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_globals.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_divider is
+Generic (
+ g_board_clock : integer := G_BOARD_CLOCK;
+ g_divider : integer := 1
+);
+Port (
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+);
+end clock_divider;
+
+architecture Behavioral of clock_divider is
+ constant clock_divider : integer := g_board_clock / g_divider;
+begin
+
+p0 : process (i_clock) is
+ variable clock_out : std_logic;
+ variable counter : integer range 0 to clock_divider - 1 := 0;
+begin
+ if (rising_edge(i_clock)) then
+ if (counter = clock_divider-1) then
+ clock_out := '1';
+ counter := 0;
+ else
+ clock_out := '0';
+ counter := counter + 1;
+ end if;
+ end if;
+ o_clock <= clock_out;
+end process p0;
+
+end Behavioral;
+
diff --git a/adc_counter/lcd_display.vhd b/adc_counter/lcd_display.vhd
new file mode 100755
index 0000000..43f3b61
--- /dev/null
+++ b/adc_counter/lcd_display.vhd
@@ -0,0 +1,130 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:24:00 11/28/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/memorymodule/lcd_display.vhd
+-- Project Name: memorymodule
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_globals.ALL;
+use WORK.p_lcd_display.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity lcd_display is
+Generic (
+ LCDClockDivider : integer := G_LCDClockDivider -- XXX in ms
+);
+Port (
+ i_clock : in std_logic;
+ i_LCDChar : LCDHex;
+ o_anode : out std_logic_vector(G_LCDAnode-1 downto 0);
+ o_segment : out std_logic_vector(G_LCDSegment-1 downto 0)
+);
+end lcd_display;
+
+architecture Behavioral of lcd_display is
+
+ component clock_divider is
+ Generic(
+ g_board_clock : integer;
+ g_divider : integer
+ );
+ Port(
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+ );
+ end component clock_divider;
+ for all : clock_divider use entity work.clock_divider(Behavioral);
+
+ signal clock_divider_1 : std_logic;
+
+begin
+
+ c_clock_divider_1 : clock_divider
+ Generic Map (
+ g_board_clock => G_BOARD_CLOCK,
+ g_divider => 1000/LCDClockDivider
+ )
+ Port Map (
+ i_clock => i_clock,
+ o_clock => clock_divider_1
+ );
+
+ p0 : process (clock_divider_1) is
+ variable count : integer range 0 to G_LCDAnode := 0;
+ begin
+ if (rising_edge(clock_divider_1)) then
+ case count is
+ when 0 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "0111";
+ when 1 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1011";
+ when 2 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1101";
+ when 3 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1110";
+ when others =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1111";
+ end case;
+ if (count = G_LCDAnode-1) then
+ count := 0;
+ else
+ count := count + 1;
+ end if;
+ end if;
+ end process p0;
+
+ p1 : process (clock_divider_1) is
+ variable count : integer range 0 to G_LCDAnode := 0;
+ begin
+ if (rising_edge(clock_divider_1)) then
+ case to_integer(unsigned(i_LCDChar(count))) is
+ when 0 => o_segment <= "1000000"; -- 0
+ when 1 => o_segment <= "1111001"; -- 1
+ when 2 => o_segment <= "0100100"; -- 2
+ when 3 => o_segment <= "0110000"; -- 3
+ when 4 => o_segment <= "0011001"; -- 4
+ when 5 => o_segment <= "0010010"; -- 5
+ when 6 => o_segment <= "0000010"; -- 6
+ when 7 => o_segment <= "1111000"; -- 7
+ when 8 => o_segment <= "0000000"; -- 8
+ when 9 => o_segment <= "0010000"; -- 9
+ when 10 => o_segment <= "0001000"; -- a
+ when 11 => o_segment <= "0000011"; -- b
+ when 12 => o_segment <= "1000110"; -- c
+ when 13 => o_segment <= "0100001"; -- d
+ when 14 => o_segment <= "0000110"; -- e
+ when 15 => o_segment <= "0001110"; -- f
+ when others => null;
+ end case;
+ if (count = G_LCDAnode-1) then
+ count := 0;
+ else
+ count := count + 1;
+ end if;
+ end if;
+ end process p1;
+
+end Behavioral;
+
diff --git a/adc_counter/p_globals.vhd b/adc_counter/p_globals.vhd
new file mode 100755
index 0000000..fc4728e
--- /dev/null
+++ b/adc_counter/p_globals.vhd
@@ -0,0 +1,22 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package p_globals is
+
+ constant G_BOARD_CLOCK : integer := 50_000_000;
+ constant G_LCDSegment : integer := 7;
+ constant G_LCDAnode : integer := 4;
+ constant G_LCDClockDivider : integer := 200;
+ constant G_MemoryAddress : integer := 24;
+ constant G_MemoryData : integer := 16;
+ constant G_Switch : integer := 8;
+ constant G_Button : integer := 4;
+ constant G_Led : integer := 8;
+ constant G_HalfHex : integer := 4;
+ constant G_FullHex : integer := G_HalfHex*2;
+
+end p_globals;
+
+package body p_globals is
+end p_globals;
+
diff --git a/adc_counter/p_lcd_display.vhd b/adc_counter/p_lcd_display.vhd
new file mode 100755
index 0000000..7bcf763
--- /dev/null
+++ b/adc_counter/p_lcd_display.vhd
@@ -0,0 +1,13 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use WORK.p_globals.ALL;
+
+package p_lcd_display is
+
+ type LCDHex is array(G_LCDAnode-1 downto 0) of std_logic_vector(G_HalfHex-1 downto 0);
+
+end p_lcd_display;
+
+package body p_lcd_display is
+end p_lcd_display;
+
diff --git a/adc_counter/sine_unsigned0to255.ucf b/adc_counter/sine_unsigned0to255.ucf
new file mode 100755
index 0000000..31dbcf1
--- /dev/null
+++ b/adc_counter/sine_unsigned0to255.ucf
@@ -0,0 +1,31 @@
+
+NET "i_clock" LOC = "B8";
+NET "i_reset" LOC = "B18";
+#NET "BUTTON<1>" LOC = "D18";
+
+#NET "io_ladder<11>" LOC = "L15";
+#NET "io_ladder<10>" LOC = "K12";
+#NET "io_ladder<9>" LOC = "L17";
+#NET "io_ladder<8>" LOC = "M15";
+NET "io_ladder<0>" LOC = "L15";
+NET "io_ladder<1>" LOC = "K12";
+NET "io_ladder<2>" LOC = "L17";
+NET "io_ladder<3>" LOC = "M15";
+
+NET "io_ladder<4>" LOC = "M13";
+NET "io_ladder<5>" LOC = "R18";
+NET "io_ladder<6>" LOC = "R15";
+NET "io_ladder<7>" LOC = "T17";
+#NET "JB<4>" LOC = "P17";
+#NET "JB<5>" LOC = "R16";
+#NET "JB<6>" LOC = "T18";
+#NET "JB<7>" LOC = "U18";
+
+#NET "o_data<0>" LOC = "J14";
+#NET "o_data<1>" LOC = "J15";
+#NET "o_data<2>" LOC = "K15";
+#NET "o_data<3>" LOC = "K14";
+#NET "o_data<4>" LOC = "E16";
+#NET "o_data<5>" LOC = "P16";
+#NET "o_data<6>" LOC = "E4";
+#NET "o_data<7>" LOC = "P4";
diff --git a/adc_counter/sine_unsigned0to255.vhd b/adc_counter/sine_unsigned0to255.vhd
new file mode 100755
index 0000000..f6068fc
--- /dev/null
+++ b/adc_counter/sine_unsigned0to255.vhd
@@ -0,0 +1,82 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:43:44 08/13/2021
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity sine_unsigned0to255 is
+Generic (
+N : integer := 8;
+M : integer := 5_000_000
+);
+Port (
+i_clock : in STD_LOGIC;
+i_reset : in STD_LOGIC;
+io_ladder : out STD_LOGIC_VECTOR(N-1 downto 0)
+);
+end sine_unsigned0to255;
+
+architecture Behavioral of sine_unsigned0to255 is
+ constant PROBES : integer := 256;
+ type trom is array (0 to PROBES-1) of integer range 0 to 255;
+ constant rom : trom := (128,145,162,178,193,207,220,231,240,247,252,255,255,253,249,243,234,223,211,197,182,166,149,132,115,98,81,66,51,38,27,17,9,4,0,0,1,5,10,19,29,40,54,69,84,101,118,135,152,169,185,200,213,225,236,244,250,254,255,255,252,246,239,229,218,205,191,175,159,142,124,107,90,74,59,45,33,22,13,6,2,0,0,2,7,14,23,34,46,60,76,92,109,126,143,160,176,192,206,219,230,240,247,252,255,255,254,250,243,235,224,212,199,184,168,151,134,117,99,83,67,53,39,28,18,10,4,1,0,1,4,10,18,28,39,53,67,83,99,117,134,151,168,184,199,212,224,235,243,250,254,255,255,252,247,240,230,219,206,192,176,160,143,126,109,92,76,60,46,34,23,14,7,2,0,0,2,6,13,22,33,45,59,74,90,107,124,142,159,175,191,205,218,229,239,246,252,255,255,254,250,244,236,225,213,200,185,169,152,135,118,101,84,69,54,40,29,19,10,5,1,0,0,4,9,17,27,38,51,66,81,98,115,132,149,166,182,197,211,223,234,243,249,253,255,255,252,247,240,231,220,207,193,178,162,145);
+ signal clock_divider : std_logic;
+begin
+ p0 : process (i_clock,i_reset) is
+ constant ccount : integer := M;
+ variable count : integer range 0 to ccount-1;
+ begin
+ if (i_reset = '1') then
+ count := 0;
+ clock_divider <= '0';
+ elsif (rising_edge(i_clock)) then
+ if (count = ccount-1) then
+ clock_divider <= '1';
+ count := 0;
+ else
+ clock_divider <= '0';
+ count := count + 1;
+ end if;
+ end if;
+ end process p0;
+ p1 : process (clock_divider,i_reset) is
+ variable count : integer range 0 to PROBES-1;
+ begin
+ if (i_reset = '1') then
+ count := 0;
+ io_ladder <= (others => '0');
+ elsif (rising_edge(clock_divider)) then
+ io_ladder <= std_logic_vector(to_signed(rom(count),N));
+ if (count = PROBES-1) then
+ count := 0;
+ else
+ count := count + 1;
+ end if;
+ end if;
+ end process p1;
+end Behavioral;
diff --git a/adc_sar/FDCPE_Q_QB.vhd b/adc_sar/FDCPE_Q_QB.vhd
new file mode 100755
index 0000000..618d1cd
--- /dev/null
+++ b/adc_sar/FDCPE_Q_QB.vhd
@@ -0,0 +1,56 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:23:05 04/18/2021
+-- Design Name:
+-- Module Name: FDCPE_Q_QB - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity FDCPE_Q_QB is
+Generic (
+ INIT : BIT := '0'
+);
+Port (
+ Q : out STD_LOGIC;
+ QB : out STD_LOGIC;
+ C : in STD_LOGIC;
+ CE : in STD_LOGIC;
+ CLR : in STD_LOGIC;
+ D : in STD_LOGIC;
+ PRE : in STD_LOGIC
+);
+end FDCPE_Q_QB;
+
+architecture Behavioral of FDCPE_Q_QB is
+ signal s_q : std_logic;
+begin
+ FDCPE_inst : FDCPE
+ generic map (INIT => INIT)
+ port map (Q=>s_q,C=>C,CE=>CE,CLR=>CLR,D=>D,PRE=>PRE);
+ Q <= s_q;
+ QB <= not s_q after 100 ps; -- XXX wait from FDCPE lib
+end Behavioral;
+
diff --git a/adc_sar/adc_sar.ucf b/adc_sar/adc_sar.ucf
new file mode 100755
index 0000000..928dfda
--- /dev/null
+++ b/adc_sar/adc_sar.ucf
@@ -0,0 +1,35 @@
+NET "i_clock" LOC = "B8";
+NET "i_reset" LOC = "B18";
+NET "i_soc" LOC = "D18";
+
+NET "io_ladder<0>" LOC = "L15";
+NET "io_ladder<1>" LOC = "K12";
+NET "io_ladder<2>" LOC = "L17";
+NET "io_ladder<3>" LOC = "M15";
+NET "io_ladder<4>" LOC = "K13";
+NET "io_ladder<5>" LOC = "L16";
+NET "io_ladder<6>" LOC = "M14";
+NET "io_ladder<7>" LOC = "M16";
+
+NET "io_ladder<8>" LOC = "M13";
+NET "io_ladder<9>" LOC = "R18";
+NET "io_ladder<10>" LOC = "R15";
+NET "io_ladder<11>" LOC = "T17";
+NET "i_from_comparator" LOC = "P17";
+NET "o_eoc" LOC = "R16";
+NET "o_soc" LOC = "T18";
+#NET "JB<7>" LOC = "U18";
+
+NET "o_segment<0>" LOC = "L18";
+NET "o_segment<1>" LOC = "F18";
+NET "o_segment<2>" LOC = "D17";
+NET "o_segment<3>" LOC = "D16";
+NET "o_segment<4>" LOC = "G14";
+NET "o_segment<5>" LOC = "J17";
+NET "o_segment<6>" LOC = "H14";
+#NET "o_dp" LOC = "C17";
+
+NET "o_anode<0>" LOC = "F17";
+NET "o_anode<1>" LOC = "H17";
+NET "o_anode<2>" LOC = "C18";
+NET "o_anode<3>" LOC = "F15";
diff --git a/adc_sar/adc_sar.vhd b/adc_sar/adc_sar.vhd
new file mode 100755
index 0000000..9a0f669
--- /dev/null
+++ b/adc_sar/adc_sar.vhd
@@ -0,0 +1,211 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:47:54 05/07/2021
+-- Design Name:
+-- Module Name: sar_adc - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_globals.ALL;
+use WORK.p_lcd_display.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity adc_sar is
+Generic (
+G_BOARD_CLOCK : integer := G_BOARD_CLOCK;
+data_size : integer := 12
+);
+Port (
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_from_comparator : in std_logic;
+i_soc: in std_logic;
+o_soc: out std_logic;
+io_ladder : inout std_logic_vector(data_size-1 downto 0);
+o_anode : out std_logic_vector(G_LCDAnode-1 downto 0);
+o_segment : out std_logic_vector(G_LCDSegment-1 downto 0);
+o_eoc : out std_logic
+);
+end adc_sar;
+
+architecture Behavioral of adc_sar is
+
+component succesive_approximation_register is
+Generic (
+n : integer := data_size
+);
+Port (
+i_clock : in STD_LOGIC;
+i_reset : in STD_LOGIC;
+i_select : in STD_LOGIC;
+o_q : out STD_LOGIC_VECTOR (n-1 downto 0);
+o_end : inout STD_LOGIC
+);
+end component succesive_approximation_register;
+
+component nxp_74hc573 is
+generic (
+nbit : integer := data_size
+);
+port (
+i_le : in std_logic;
+i_oeb : in std_logic;
+i_d : in std_logic_vector(nbit-1 downto 0);
+o_q : out std_logic_vector(nbit-1 downto 0)
+);
+end component nxp_74hc573;
+
+component lcd_display is
+Generic (
+LCDClockDivider : integer := 1 -- XXX in ms
+);
+Port (
+i_clock : in std_logic;
+i_LCDChar : LCDHex;
+o_anode : out std_logic_vector(G_LCDAnode-1 downto 0);
+o_segment : out std_logic_vector(G_LCDSegment-1 downto 0)
+);
+end component lcd_display;
+
+signal divclock,soc,oeb,eoc : std_logic;
+signal ladderbuf : std_logic_vector(data_size-1 downto 0);
+signal sample : std_logic;
+
+type states is (idle,start,stop);
+signal state : states;
+
+signal LCDChar : LCDHex;
+
+begin
+
+p_fsm : process (divclock,i_reset) is
+ constant CW : integer := 10;
+ variable w : integer range 0 to CW-1;
+begin
+ if (i_reset = '1') then
+ state <= idle;
+ soc <= '0';
+ oeb <= '1';
+ w := 0;
+ elsif (rising_edge(divclock)) then
+ case (state) is
+ when idle =>
+ if (sample = '1') then
+ state <= start;
+ soc <= '1';
+ oeb <= '1';
+ else
+ state <= idle;
+ soc <= '0';
+ oeb <= '0';
+ end if;
+ when start =>
+ if (eoc = '1') then
+ state <= stop;
+ oeb <= '1';
+ soc <= '0';
+ ladderbuf <= io_ladder;
+ LCDChar <= (ladderbuf(3 downto 0),ladderbuf(7 downto 4),ladderbuf(11 downto 8),x"0");
+ else
+ state <= start;
+ soc <= '1';
+ end if;
+ when stop =>
+ if (w = CW-1) then
+ state <= idle;
+ w := 0;
+ oeb <= '1';
+ else
+ state <= stop;
+ w := w + 1;
+ oeb <= '0';
+ end if;
+ when others => null;
+ end case;
+ end if;
+end process p_fsm;
+
+p_clockdivider : process (i_clock,i_reset) is
+ constant count_max : integer := G_BOARD_CLOCK/1000;
+ variable count : integer range 0 to count_max-1 := 0;
+begin
+ if (i_reset = '1') then
+ count := 0;
+ divclock <= '0';
+ elsif (rising_edge(i_clock)) then
+ if (count = count_max-1) then
+ count := 0;
+ divclock <= '1';
+ else
+ count := count + 1;
+ divclock <= '0';
+ end if;
+ end if;
+end process p_clockdivider;
+
+p_sampleclock : process (i_clock,i_reset) is
+ constant count_max : integer := G_BOARD_CLOCK/1000;
+ variable count : integer range 0 to count_max-1 := 0;
+begin
+ if (i_reset = '1') then
+ count := 0;
+ sample <= '0';
+ elsif (rising_edge(i_clock)) then
+ if (count = count_max-1) then
+ count := 0;
+ sample <= '1';
+ else
+ count := count + 1;
+ sample <= '0';
+ end if;
+ end if;
+end process p_sampleclock;
+
+o_eoc <= eoc;
+o_soc <= i_soc;
+
+sar_entity : succesive_approximation_register
+Generic map (
+n => data_size
+)
+Port map (
+i_clock => divclock,
+i_reset => soc,
+i_select => not i_from_comparator,
+o_q => io_ladder,
+o_end => eoc
+);
+
+lcddisplay_entity : lcd_display
+generic map (
+LCDClockDivider => 4 -- XXX in ms
+)
+port map (
+i_clock => i_clock,
+i_LCDChar => LCDChar,
+o_anode => o_anode,
+o_segment => o_segment
+);
+
+end Behavioral;
diff --git a/adc_sar/adc_sar.xise b/adc_sar/adc_sar.xise
new file mode 100755
index 0000000..4e21f4e
--- /dev/null
+++ b/adc_sar/adc_sar.xise
@@ -0,0 +1,400 @@
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diff --git a/adc_sar/clock_divider.vhd b/adc_sar/clock_divider.vhd
new file mode 100755
index 0000000..04f2606
--- /dev/null
+++ b/adc_sar/clock_divider.vhd
@@ -0,0 +1,65 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:42:10 09/18/2020
+-- Design Name:
+-- Module Name: clock_divider - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_globals.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_divider is
+Generic (
+ g_board_clock : integer := G_BOARD_CLOCK;
+ g_divider : integer := 1
+);
+Port (
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+);
+end clock_divider;
+
+architecture Behavioral of clock_divider is
+ constant clock_divider : integer := g_board_clock / g_divider;
+begin
+
+p0 : process (i_clock) is
+ variable clock_out : std_logic;
+ variable counter : integer range 0 to clock_divider - 1 := 0;
+begin
+ if (rising_edge(i_clock)) then
+ if (counter = clock_divider-1) then
+ clock_out := '1';
+ counter := 0;
+ else
+ clock_out := '0';
+ counter := counter + 1;
+ end if;
+ end if;
+ o_clock <= clock_out;
+end process p0;
+
+end Behavioral;
+
diff --git a/adc_sar/dac_delta_sigma.vhd b/adc_sar/dac_delta_sigma.vhd
new file mode 100755
index 0000000..6a8db65
--- /dev/null
+++ b/adc_sar/dac_delta_sigma.vhd
@@ -0,0 +1,52 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:50:09 03/03/2021
+-- Design Name:
+-- Module Name: dac_delta_sigma - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity dac_delta_sigma is
+Port (
+clk : in STD_LOGIC;
+data : in STD_LOGIC_VECTOR (7 downto 0);
+PulseStream : out STD_LOGIC
+);
+end dac_delta_sigma;
+
+architecture Behavioral of dac_delta_sigma is
+ signal sum : STD_LOGIC_VECTOR(8 downto 0) := (others=>'0');
+begin
+ PulseStream <= sum(8);
+ p0 : process (clk,sum) is
+ begin
+ if (rising_edge(clk)) then
+ sum <= ("0" & sum(7 downto 0)) + ("0" & data);
+ end if;
+ end process p0;
+end Behavioral;
diff --git a/adc_sar/lcd_display.vhd b/adc_sar/lcd_display.vhd
new file mode 100755
index 0000000..43f3b61
--- /dev/null
+++ b/adc_sar/lcd_display.vhd
@@ -0,0 +1,130 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:24:00 11/28/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/memorymodule/lcd_display.vhd
+-- Project Name: memorymodule
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_globals.ALL;
+use WORK.p_lcd_display.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity lcd_display is
+Generic (
+ LCDClockDivider : integer := G_LCDClockDivider -- XXX in ms
+);
+Port (
+ i_clock : in std_logic;
+ i_LCDChar : LCDHex;
+ o_anode : out std_logic_vector(G_LCDAnode-1 downto 0);
+ o_segment : out std_logic_vector(G_LCDSegment-1 downto 0)
+);
+end lcd_display;
+
+architecture Behavioral of lcd_display is
+
+ component clock_divider is
+ Generic(
+ g_board_clock : integer;
+ g_divider : integer
+ );
+ Port(
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+ );
+ end component clock_divider;
+ for all : clock_divider use entity work.clock_divider(Behavioral);
+
+ signal clock_divider_1 : std_logic;
+
+begin
+
+ c_clock_divider_1 : clock_divider
+ Generic Map (
+ g_board_clock => G_BOARD_CLOCK,
+ g_divider => 1000/LCDClockDivider
+ )
+ Port Map (
+ i_clock => i_clock,
+ o_clock => clock_divider_1
+ );
+
+ p0 : process (clock_divider_1) is
+ variable count : integer range 0 to G_LCDAnode := 0;
+ begin
+ if (rising_edge(clock_divider_1)) then
+ case count is
+ when 0 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "0111";
+ when 1 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1011";
+ when 2 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1101";
+ when 3 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1110";
+ when others =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1111";
+ end case;
+ if (count = G_LCDAnode-1) then
+ count := 0;
+ else
+ count := count + 1;
+ end if;
+ end if;
+ end process p0;
+
+ p1 : process (clock_divider_1) is
+ variable count : integer range 0 to G_LCDAnode := 0;
+ begin
+ if (rising_edge(clock_divider_1)) then
+ case to_integer(unsigned(i_LCDChar(count))) is
+ when 0 => o_segment <= "1000000"; -- 0
+ when 1 => o_segment <= "1111001"; -- 1
+ when 2 => o_segment <= "0100100"; -- 2
+ when 3 => o_segment <= "0110000"; -- 3
+ when 4 => o_segment <= "0011001"; -- 4
+ when 5 => o_segment <= "0010010"; -- 5
+ when 6 => o_segment <= "0000010"; -- 6
+ when 7 => o_segment <= "1111000"; -- 7
+ when 8 => o_segment <= "0000000"; -- 8
+ when 9 => o_segment <= "0010000"; -- 9
+ when 10 => o_segment <= "0001000"; -- a
+ when 11 => o_segment <= "0000011"; -- b
+ when 12 => o_segment <= "1000110"; -- c
+ when 13 => o_segment <= "0100001"; -- d
+ when 14 => o_segment <= "0000110"; -- e
+ when 15 => o_segment <= "0001110"; -- f
+ when others => null;
+ end case;
+ if (count = G_LCDAnode-1) then
+ count := 0;
+ else
+ count := count + 1;
+ end if;
+ end if;
+ end process p1;
+
+end Behavioral;
+
diff --git a/adc_sar/nxp_74hc573.vhd b/adc_sar/nxp_74hc573.vhd
new file mode 100755
index 0000000..53466d8
--- /dev/null
+++ b/adc_sar/nxp_74hc573.vhd
@@ -0,0 +1,70 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 10:01:44 04/12/2021
+-- Design Name:
+-- Module Name: nxp_74hc573 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity nxp_74hc573 is
+generic (
+nbit : integer := 8
+);
+port (
+i_le : in std_logic;
+i_oeb : in std_logic;
+i_d : in std_logic_vector(nbit-1 downto 0);
+o_q : out std_logic_vector(nbit-1 downto 0)
+);
+end nxp_74hc573;
+
+architecture Behavioral of nxp_74hc573 is
+
+signal d : std_logic_vector(nbit-1 downto 0);
+signal q : std_logic_vector(nbit-1 downto 0);
+
+begin
+
+IBUF_generate : for i in 0 to nbit-1 generate
+begin
+IBUF_inst : IBUF
+port map (O => d(i),I => i_d(i));
+end generate IBUF_generate;
+
+LDCE_generate : for i in 0 to nbit-1 generate
+begin
+LDCE_inst : LDCE
+port map (Q => q(i),CLR => '0',D => d(i),G => not i_le,GE => not i_le);
+end generate LDCE_generate;
+
+OBUFT_generate : for i in 0 to nbit-1 generate
+begin
+OBUFT_inst : OBUFT
+port map (O => o_q(i),I => q(i),T => i_oeb);
+end generate OBUFT_generate;
+
+end Behavioral;
+
diff --git a/adc_sar/p_globals.vhd b/adc_sar/p_globals.vhd
new file mode 100755
index 0000000..fc4728e
--- /dev/null
+++ b/adc_sar/p_globals.vhd
@@ -0,0 +1,22 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package p_globals is
+
+ constant G_BOARD_CLOCK : integer := 50_000_000;
+ constant G_LCDSegment : integer := 7;
+ constant G_LCDAnode : integer := 4;
+ constant G_LCDClockDivider : integer := 200;
+ constant G_MemoryAddress : integer := 24;
+ constant G_MemoryData : integer := 16;
+ constant G_Switch : integer := 8;
+ constant G_Button : integer := 4;
+ constant G_Led : integer := 8;
+ constant G_HalfHex : integer := 4;
+ constant G_FullHex : integer := G_HalfHex*2;
+
+end p_globals;
+
+package body p_globals is
+end p_globals;
+
diff --git a/adc_sar/p_lcd_display.vhd b/adc_sar/p_lcd_display.vhd
new file mode 100755
index 0000000..7bcf763
--- /dev/null
+++ b/adc_sar/p_lcd_display.vhd
@@ -0,0 +1,13 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use WORK.p_globals.ALL;
+
+package p_lcd_display is
+
+ type LCDHex is array(G_LCDAnode-1 downto 0) of std_logic_vector(G_HalfHex-1 downto 0);
+
+end p_lcd_display;
+
+package body p_lcd_display is
+end p_lcd_display;
+
diff --git a/adc_sar/sine_unsigned0to255.vhd b/adc_sar/sine_unsigned0to255.vhd
new file mode 100755
index 0000000..2f4a45b
--- /dev/null
+++ b/adc_sar/sine_unsigned0to255.vhd
@@ -0,0 +1,84 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:43:44 08/13/2021
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity sine_unsigned0to255 is
+Generic (
+N : integer := 8;
+M : integer := 5_000_000
+);
+Port (
+i_clock : in STD_LOGIC;
+i_reset : in STD_LOGIC;
+o_ladder : out STD_LOGIC_VECTOR(N-1 downto 0)
+);
+end sine_unsigned0to255;
+
+architecture Behavioral of sine_unsigned0to255 is
+ constant PROBES : integer := 256;
+ type trom is array (0 to PROBES-1) of integer range 0 to 255;
+ constant rom : trom := (
+128,145,162,178,193,207,220,231,240,247,252,255,255,253,249,243,234,223,211,197,182,166,149,132,115,98,81,66,51,38,27,17,9,4,0,0,1,5,10,19,29,40,54,69,84,101,118,135,152,169,185,200,213,225,236,244,250,254,255,255,252,246,239,229,218,205,191,175,159,142,124,107,90,74,59,45,33,22,13,6,2,0,0,2,7,14,23,34,46,60,76,92,109,126,143,160,176,192,206,219,230,240,247,252,255,255,254,250,243,235,224,212,199,184,168,151,134,117,99,83,67,53,39,28,18,10,4,1,0,1,4,10,18,28,39,53,67,83,99,117,134,151,168,184,199,212,224,235,243,250,254,255,255,252,247,240,230,219,206,192,176,160,143,126,109,92,76,60,46,34,23,14,7,2,0,0,2,6,13,22,33,45,59,74,90,107,124,142,159,175,191,205,218,229,239,246,252,255,255,254,250,244,236,225,213,200,185,169,152,135,118,101,84,69,54,40,29,19,10,5,1,0,0,4,9,17,27,38,51,66,81,98,115,132,149,166,182,197,211,223,234,243,249,253,255,255,252,247,240,231,220,207,193,178,162,145
+);
+ signal clock_divider : std_logic;
+begin
+ p0 : process (i_clock,i_reset) is
+ constant ccount : integer := M;
+ variable count : integer range 0 to ccount-1;
+ begin
+ if (i_reset = '1') then
+ count := 0;
+ clock_divider <= '0';
+ elsif (rising_edge(i_clock)) then
+ if (count = ccount-1) then
+ clock_divider <= '1';
+ count := 0;
+ else
+ clock_divider <= '0';
+ count := count + 1;
+ end if;
+ end if;
+ end process p0;
+ p1 : process (clock_divider,i_reset) is
+ variable count : integer range 0 to PROBES-1;
+ begin
+ if (i_reset = '1') then
+ count := 0;
+ o_ladder <= (others => '0');
+ elsif (rising_edge(clock_divider)) then
+ o_ladder <= std_logic_vector(to_unsigned(rom(count),8));
+ if (count = PROBES-1) then
+ count := 0;
+ else
+ count := count + 1;
+ end if;
+ end if;
+ end process p1;
+end Behavioral;
diff --git a/adc_sar/succesive_approximation_register.vhd b/adc_sar/succesive_approximation_register.vhd
new file mode 100755
index 0000000..8933505
--- /dev/null
+++ b/adc_sar/succesive_approximation_register.vhd
@@ -0,0 +1,116 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:19:16 04/18/2021
+-- Design Name:
+-- Module Name: succesive_approximation_register - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity succesive_approximation_register is
+Generic (
+n : integer := 4
+);
+Port (
+i_clock : in STD_LOGIC;
+i_reset : in STD_LOGIC;
+i_select : in STD_LOGIC;
+o_q : out STD_LOGIC_VECTOR (n-1 downto 0);
+o_end : inout STD_LOGIC
+);
+end succesive_approximation_register;
+
+architecture Behavioral of succesive_approximation_register is
+
+COMPONENT FDCPE_Q_QB IS
+Generic (
+ INIT : BIT := '0'
+);
+Port (
+ Q : out STD_LOGIC;
+ QB : out STD_LOGIC;
+ C : in STD_LOGIC;
+ CE : in STD_LOGIC;
+ CLR : in STD_LOGIC;
+ D : in STD_LOGIC;
+ PRE : in STD_LOGIC
+);
+END COMPONENT FDCPE_Q_QB;
+
+signal first_q,first_qb : std_logic;
+signal q1 : std_logic_vector(n-1 downto 0);
+signal qb1 : std_logic_vector(n-2 downto 0);
+signal q2 : std_logic_vector(n-1 downto 0);
+
+begin
+-- XXX based on https://api.intechopen.com/media/chapter/39238/media/image5.JPG
+
+o_end <= q1(n-1) after 1 ns;
+
+first : FDCPE_Q_QB
+generic map (INIT => '0')
+port map (Q=>first_q,QB=>first_qb,C=>i_clock,CE=>'1',CLR=>'0',D=>o_end,PRE=>not i_reset);
+
+FDCPE_g1 : for i in 0 to n-1 generate
+ n1_first : if (i=0) generate
+ FDCPE_inst : FDCPE_Q_QB
+ generic map (INIT => '0')
+ port map (Q=>q1(i),QB=>qb1(i),C=>i_clock,CE=>'1',CLR=>not i_reset,D=>first_q,PRE=>'0');
+ end generate n1_first;
+ n1_chain : if (0 '0')
+ port map (Q=>q1(i),QB=>qb1(i),C=>i_clock,CE=>'1',CLR=>not i_reset,D=>q1(i-1),PRE=>'0');
+ end generate n1_chain;
+ n1_last : if (i=n-1) generate
+ FDCPE_inst : FDCPE
+ generic map (INIT => '0')
+ port map (Q=>q1(n-1),C=>i_clock,CE=>'1',CLR=>not i_reset,D=>q1(i-1),PRE=>'0');
+ end generate n1_last;
+end generate FDCPE_g1;
+
+FDCPE_g2 : for i in 0 to n-1 generate
+ n2_first : if (i=0) generate
+ FDCPE_inst : FDCPE
+ generic map (INIT => '0')
+ port map (Q=>q2(i),C=>first_qb,CE=>'1',CLR=>not i_reset,D=>i_select,PRE=>'0');
+ end generate n2_first;
+ n2_chain : if (0 '0')
+ port map (Q=>q2(i),C=>qb1(i-1),CE=>'1',CLR=>not i_reset,D=>i_select,PRE=>'0');
+ end generate n2_chain;
+end generate FDCPE_g2;
+
+OR_gates : for i in 0 to n-1 generate
+ or_first : if (i=0) generate
+ o_q(n-1) <= q2(i) or first_q after 1 ns;
+ end generate or_first;
+ or_rest : if (0 i_clock,
+i_reset => i_reset,
+i_from_comparator => i_from_comparator,
+i_soc => i_soc,
+o_soc => o_soc,
+io_ladder => io_ladder,
+o_anode => o_anode,
+o_segment => o_segment,
+o_eoc => o_eoc
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+i_reset <= '1';
+wait for 100 ns;
+i_reset <= '0';
+wait for i_clock_period*10;
+
+-- insert stimulus here
+
+wait;
+end process;
+
+END;
diff --git a/adc_sar/tb_sar_adc.vhd b/adc_sar/tb_sar_adc.vhd
new file mode 100755
index 0000000..b8713ef
--- /dev/null
+++ b/adc_sar/tb_sar_adc.vhd
@@ -0,0 +1,252 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:17:33 08/16/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/dac_ladder_r2r/tb_sar_adc.vhd
+-- Project Name: dac_ladder_r2r
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: sar_adc
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_sar_adc IS
+END tb_sar_adc;
+
+ARCHITECTURE behavior OF tb_sar_adc IS
+
+--constant C_CLOCK : integer := 200; -- XXX tb
+constant C_CLOCK : integer := 5_000_000; -- XXX orig
+constant C_DATA_SIZE : integer := 8;
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT sar_adc
+GENERIC (
+G_BOARD_CLOCK : integer;
+data_size : integer
+);
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+i_from_comparator : IN std_logic;
+i_soc : IN std_logic;
+o_soc : OUT std_logic;
+io_ladder : INOUT std_logic_vector(C_DATA_SIZE-1 downto 0);
+o_data : OUT std_logic_vector(C_DATA_SIZE-1 downto 0);
+o_eoc : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+signal i_from_comparator : std_logic := '0';
+signal i_soc : std_logic := '0';
+
+signal io_ladder : std_logic_vector(C_DATA_SIZE-1 downto 0);
+
+--Outputs
+signal o_soc : std_logic;
+signal o_data : std_logic_vector(C_DATA_SIZE-1 downto 0);
+signal o_eoc : std_logic;
+
+-- Clock period definitions
+--constant i_clock_period : time := (1_000_000_000/C_CLOCK) * 1 ns;
+constant i_clock_period : time := 20 ns;
+
+BEGIN
+-- Instantiate the Unit Under Test (UUT)
+uut: sar_adc
+GENERIC MAP (
+G_BOARD_CLOCK => C_CLOCK,
+data_size => C_DATA_SIZE
+)
+PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+i_from_comparator => i_from_comparator,
+i_soc => i_soc,
+o_soc => o_soc,
+io_ladder => io_ladder,
+o_data => o_data,
+o_eoc => o_eoc
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- insert stimulus here
+i_reset <= '1';
+wait for C_CLOCK * i_clock_period;
+i_reset <= '0';
+
+wait for 3 * C_CLOCK * i_clock_period;
+
+i_soc <= '0';
+i_from_comparator <= '0';
+
+wait for C_CLOCK * i_clock_period;
+i_soc <= '1';
+wait for C_CLOCK * i_clock_period;
+i_soc <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+
+i_soc <= '0';
+i_from_comparator <= '0';
+
+wait for 3 * C_CLOCK * i_clock_period;
+
+i_soc <= '1';
+wait for C_CLOCK * i_clock_period;
+i_soc <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+
+i_soc <= '0';
+i_from_comparator <= '0';
+
+wait for 3 * C_CLOCK * i_clock_period;
+
+i_soc <= '1';
+wait for C_CLOCK * i_clock_period;
+i_soc <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+
+i_soc <= '0';
+i_from_comparator <= '0';
+
+wait for 3 * C_CLOCK * i_clock_period;
+
+i_soc <= '1';
+wait for C_CLOCK * i_clock_period;
+i_soc <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+
+i_soc <= '0';
+i_from_comparator <= '0';
+
+wait for 3 * C_CLOCK * i_clock_period;
+
+i_soc <= '1';
+wait for C_CLOCK * i_clock_period;
+i_soc <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '0';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+wait for C_CLOCK * i_clock_period;
+i_from_comparator <= '1';
+
+wait for C_CLOCK * i_clock_period;
+
+i_soc <= '0';
+i_from_comparator <= '0';
+
+wait;
+end process;
+
+END;
diff --git a/adc_sar/tb_succesive_approximation_register.vhd b/adc_sar/tb_succesive_approximation_register.vhd
new file mode 100755
index 0000000..68193a7
--- /dev/null
+++ b/adc_sar/tb_succesive_approximation_register.vhd
@@ -0,0 +1,128 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:41:51 04/18/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_succesive_approximation_register.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: succesive_approximation_register
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_succesive_approximation_register IS
+END tb_succesive_approximation_register;
+
+ARCHITECTURE behavior OF tb_succesive_approximation_register IS
+
+constant N : integer := 8;
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT succesive_approximation_register
+GENERIC(
+n : INTEGER := N
+);
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+i_select : IN std_logic;
+o_q : OUT std_logic_vector(N-1 downto 0);
+o_end : INOUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+signal i_select : std_logic := '0';
+
+--BiDirs
+signal o_end : std_logic;
+
+--Outputs
+signal o_q : std_logic_vector(N-1 downto 0);
+
+-- Clock period definitions
+constant i_clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: succesive_approximation_register
+GENERIC MAP (
+n => N
+)
+PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+i_select => i_select,
+o_q => o_q,
+o_end => o_end
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+--o_end <= '1';
+i_reset <= '0';
+wait for 3*i_clock_period;
+i_reset <= '1';
+wait for 1*i_clock_period;
+i_select <= '1';
+wait for 1*i_clock_period;
+i_select <= '0';
+wait for 5*i_clock_period;
+i_select <= '1';
+wait for 1*i_clock_period;
+i_select <= '0';
+wait for 14*i_clock_period;
+i_reset <= '0';
+wait for 5*i_clock_period;
+i_reset <= '1';
+wait for 24*i_clock_period;
+i_reset <= '0';
+-- insert stimulus here
+--l0 : for i in 0 to 2**N-1 loop
+--wait for i_clock_period*17; -- XXX must be less than (2**N)
+--i_select <= '1';
+----o_end <= '0';
+--wait for 3*i_clock_period;
+--i_select <= '0';
+----o_end <= '0';
+--end loop l0;
+wait;
+end process;
+
+END;
diff --git a/adc_sar/tb_top.vhd b/adc_sar/tb_top.vhd
new file mode 100755
index 0000000..c3215dd
--- /dev/null
+++ b/adc_sar/tb_top.vhd
@@ -0,0 +1,93 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:27:43 08/13/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/dac_ladder_r2r/tb_top.vhd
+-- Project Name: dac_ladder_r2r
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_top IS
+END tb_top;
+
+ARCHITECTURE behavior OF tb_top IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT top
+GENERIC (
+N : integer := 8;
+M : integer := 1_000_00
+);
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+o_ladder : OUT std_logic_vector(7 downto 0)
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+
+--Outputs
+signal o_ladder : std_logic_vector(7 downto 0);
+
+-- Clock period definitions
+constant i_clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: top PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+o_ladder => o_ladder
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+i_reset <= '1';
+wait for 100 ns;
+i_reset <= '0';
+wait for i_clock_period*10;
+-- insert stimulus here
+wait;
+end process;
+
+END;
diff --git a/camera1/VGA.vhd b/camera1/VGA.vhd
new file mode 100755
index 0000000..3cc9a5d
--- /dev/null
+++ b/camera1/VGA.vhd
@@ -0,0 +1,24 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity RGB is
+ Port ( Din : in STD_LOGIC_VECTOR (7 downto 0); -- niveau de gris du pixels sur 8 bits
+ Nblank : in STD_LOGIC; -- signal indique les zone d'affichage, hors la zone d'affichage
+ -- les trois couleurs prendre 0
+ R : out STD_LOGIC_VECTOR (3 downto 1);
+ G : out STD_LOGIC_VECTOR (3 downto 1);
+ B : out STD_LOGIC_VECTOR (3 downto 2)
+ );
+end RGB;
+
+architecture Behavioral of RGB is
+
+begin
+ R <= Din(7 downto 5) when Nblank='1' else "000";
+ G <= Din(4 downto 2) when Nblank='1' else "000";
+ B <= Din(1 downto 0) when Nblank='1' else "00";
+
+end Behavioral;
diff --git a/camera1/VGA1.vhd b/camera1/VGA1.vhd
new file mode 100755
index 0000000..f925c89
--- /dev/null
+++ b/camera1/VGA1.vhd
@@ -0,0 +1,120 @@
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+
+entity VGA is
+ Port ( CLK25 : in STD_LOGIC; -- Horloge d'entrée de 25 MHz
+ --clkout : out STD_LOGIC; -- Horloge de sortie vers le ADV7123 et l'écran TFT
+ rez_160x120 : IN std_logic;
+ rez_320x240 : IN std_logic;
+ Hsync,Vsync : out STD_LOGIC; -- les deux signaux de synchronisation pour l'écran VGA
+ --Nblank : out STD_LOGIC; -- signal de commande du convertisseur N/A ADV7123
+ activeArea : out STD_LOGIC;
+ --Nsync : out STD_LOGIC
+ video : out std_logic
+ ); -- signaux de synchronisation et commande de l'écran TFT
+end VGA;
+
+architecture Behavioral of VGA is
+signal Hcnt:STD_LOGIC_VECTOR(9 downto 0):="0000000000"; -- pour le comptage des colonnes
+signal Vcnt:STD_LOGIC_VECTOR(9 downto 0):="1000001000"; -- pour le comptage des lignes
+--signal video:STD_LOGIC;
+constant HM: integer :=799; --la taille maximale considéré 800 (horizontal)
+constant HD: integer :=640; --la taille de l'écran (horizontal)
+constant HF: integer :=16; --front porch
+constant HB: integer :=48; --back porch
+constant HR: integer :=96; --sync time
+constant VM: integer :=524; --la taille maximale considéré 525 (vertical)
+constant VD: integer :=480; --la taille de l'écran (vertical)
+constant VF: integer :=10; --front porch
+constant VB: integer :=33; --back porch
+constant VR: integer :=2; --retrace
+
+begin
+
+-- initialisation d'un compteur de 0 Ã 799 (800 pixel par ligne):
+-- à chaque front d'horloge en incrémente le compteur de colonnes
+-- c-a-d du 0 Ã 799.
+ process(CLK25)
+ begin
+ if (rising_edge(CLK25)) then
+ if (Hcnt = HM) then
+ Hcnt <= "0000000000";
+ if (Vcnt= VM) then
+ Vcnt <= "0000000000";
+ activeArea <= '1';
+ else
+ if rez_160x120 = '1' then
+ if vCnt < 120-1 then
+ activeArea <= '1';
+ end if;
+ elsif rez_320x240 = '1' then
+ if vCnt < 240-1 then
+ activeArea <= '1';
+ end if;
+ else
+ if vCnt < 480-1 then
+ activeArea <= '1';
+ end if;
+ end if;
+ Vcnt <= Vcnt+1;
+ end if;
+ else
+ if rez_160x120 = '1' then
+ if hcnt = 160-1 then
+ activeArea <= '0';
+ end if;
+ elsif rez_320x240 = '1' then
+ if hcnt = 320-1 then
+ activeArea <= '0';
+ end if;
+ else
+ if hcnt = 640-1 then
+ activeArea <= '0';
+ end if;
+ end if;
+ Hcnt <= Hcnt + 1;
+ end if;
+ end if;
+ end process;
+----------------------------------------------------------------
+
+-- génération du signal de synchronisation horizontale Hsync:
+ process(CLK25)
+ begin
+ if (rising_edge(CLK25)) then
+ if (Hcnt >= (HD+HF) and Hcnt <= (HD+HF+HR-1)) then --- Hcnt >= 656 and Hcnt <= 751
+ Hsync <= '0';
+ else
+ Hsync <= '1';
+ end if;
+ end if;
+ end process;
+----------------------------------------------------------------
+
+-- génération du signal de synchronisation verticale Vsync:
+ process(CLK25)
+ begin
+ if (rising_edge(CLK25)) then
+ if (Vcnt >= (VD+VF) and Vcnt <= (VD+VF+VR-1)) then ---Vcnt >= 490 and vcnt<= 491
+ Vsync <= '0';
+ else
+ Vsync <= '1';
+ end if;
+ end if;
+ end process;
+----------------------------------------------------------------
+
+-- Nblank et Nsync pour commander le covertisseur ADV7123:
+--Nsync <= '1';
+video <= '1' when (Hcnt < HD) and (Vcnt < VD) -- c'est pour utiliser la résolution complète 640 x 480
+ else '0';
+--Nblank <= video;
+--clkout <= CLK25;
+
+
+end Behavioral;
diff --git a/camera1/address_generator.vhd b/camera1/address_generator.vhd
new file mode 100755
index 0000000..c1d5dd6
--- /dev/null
+++ b/camera1/address_generator.vhd
@@ -0,0 +1,53 @@
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+--use IEEE.STD_LOGIC_ARITH.ALL;
+--use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity Address_Generator is
+ Port ( CLK25,enable : in STD_LOGIC; -- horloge de 25 MHz et signal d'activation respectivement
+ rez_160x120 : IN std_logic;
+ rez_320x240 : IN std_logic;
+ vsync : in STD_LOGIC;
+ address : out STD_LOGIC_VECTOR (14 downto 0)); -- adresse généré
+end Address_Generator;
+
+architecture Behavioral of Address_Generator is
+ signal val: STD_LOGIC_VECTOR(address'range):= (others => '0'); -- signal intermidiaire
+ constant RES1 : integer := 160*120;
+ constant RES2 : integer := 320*240;
+ constant RES3 : integer := 640*480;
+begin
+ address <= val; -- adresse généré
+
+ process(CLK25,val,enable)
+ begin
+ if rising_edge(CLK25) then
+-- if (enable='1') then -- si enable = 0 on arrete la génération d'adresses
+ if rez_160x120 = '1' then
+ if (enable='1') then
+ if (to_integer(unsigned(val)) < RES1) then -- si l'espace mémoire est balayé complétement
+ val <= std_logic_vector(to_unsigned(to_integer(unsigned(val))+1,address'left+1));
+ end if;
+ end if;
+ elsif rez_320x240 = '1' then
+ if (enable='1') then
+ if (to_integer(unsigned(val)) < RES2) then -- si l'espace mémoire est balayé complétement
+ val <= std_logic_vector(to_unsigned(to_integer(unsigned(val))+1,address'left+1));
+ end if;
+ end if;
+ else
+ if (enable='1') then
+ if (to_integer(unsigned(val)) < RES3) then -- si l'espace mémoire est balayé complétement
+ val <= std_logic_vector(to_unsigned(to_integer(unsigned(val))+1,address'left+1));
+ end if;
+ end if;
+ end if;
+-- end if;
+ if vsync = '0' then
+ val <= (others => '0');
+ end if;
+ end if;
+ end process;
+end Behavioral;
diff --git a/camera1/bram_vga.vhd b/camera1/bram_vga.vhd
new file mode 100755
index 0000000..2e5c0f4
--- /dev/null
+++ b/camera1/bram_vga.vhd
@@ -0,0 +1,71 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:03:44 07/10/2022
+-- Design Name:
+-- Module Name: bram_vga - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+--
+-- Dual-Port RAM with Synchronous Read (Read Through)
+-- using More than One Clock
+-- UG627 PDF p. 153
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity bram_vga is
+generic (
+constant WIDTH : integer := 0;
+constant DEPTH: integer := 0
+);
+port (
+clka : in std_logic;
+clkb : in std_logic;
+wea : in std_logic;
+addra : in std_logic_vector(DEPTH-1 downto 0);
+addrb : in std_logic_vector(DEPTH-1 downto 0);
+dina : in std_logic_vector(WIDTH-1 downto 0);
+douta : out std_logic_vector(WIDTH-1 downto 0)
+);
+end entity bram_vga;
+
+architecture simulation of bram_vga is
+ type ram_type is array (0 to 2**DEPTH-1) of std_logic_vector(WIDTH-1 downto 0);
+ signal RAM : ram_type;
+ signal read_addra : std_logic_vector(DEPTH-1 downto 0);
+ signal read_addrb : std_logic_vector(DEPTH-1 downto 0);
+begin
+ pa : process (clka)
+ begin
+ if (rising_edge(clka)) then
+ if (wea = '1') then
+ RAM(conv_integer(addra)) <= dina;
+ end if;
+ read_addra <= addra;
+ end if;
+ end process pa;
+
+ pb : process (clkb)
+ begin
+ if (rising_edge(clkb)) then
+ read_addrb <= addrb;
+ end if;
+ end process pb;
+ douta <= RAM(conv_integer(read_addrb));
+
+end architecture simulation;
diff --git a/camera1/camera.vhd b/camera1/camera.vhd
new file mode 100755
index 0000000..eb9da16
--- /dev/null
+++ b/camera1/camera.vhd
@@ -0,0 +1,271 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:56:40 07/10/2022
+-- Design Name:
+-- Module Name: camera - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+-- XXX ov7670 camera emulator vga 640x480 30fps
+-- XXX based on datasheet VGA Frame Timing Figure 6 p. 7
+entity camera is
+generic (
+constant CLOCK_PERIOD : integer := 42; -- 21/42/100 ns - 10/24/48 MHZ - Min/Typ/Max Unit
+constant RAW_RGB : integer := 0; -- 0 - RAW / 1 - RGB
+constant ZERO : integer := 0
+);
+port (
+io_scl : inout std_logic;
+io_sda : inout std_logic;
+o_vs : out std_logic;
+o_hs : out std_logic;
+o_pclk : out std_logic;
+i_xclk : in std_logic;
+o_d : out std_logic_vector(7 downto 0);
+i_rst : in std_logic;
+i_pwdn : in std_logic
+);
+end camera;
+
+architecture Behavioral of camera is
+ constant CLOCK_PERIOD1 : integer := 21;
+ constant CLOCK_PERIOD2 : integer := 42;
+ constant CLOCK_PERIOD3 : integer := 100;
+ -- 1 or 2 pclk for tp
+ constant tp : integer := 2**RAW_RGB;
+ -- tline = 784tp = 640tp + 144tp
+ constant HREF1 : integer := 640;
+ constant CHREF1 : integer := HREF1 * tp; -- HREF 1 pulse time
+ constant HREF0 : integer := 144;
+ constant CHREF0 : integer := HREF0 * tp; -- HREF 0 pulse time
+ constant tline : integer := CHREF1 + CHREF0;
+ -- VSYNC pulse have 510tline
+ constant CVSYNC1 : integer := 3;
+ constant VSYNC1 : integer := CVSYNC1 * tline;
+ constant CVSYNC2 : integer := 17;
+ constant VSYNC2 : integer := CVSYNC2 * tline;
+ constant CVSYNC3 : integer := 480;
+ constant VSYNC3 : integer := CVSYNC3 * tline;
+ constant CVSYNC4 : integer := 10;
+ constant VSYNC4 : integer := CVSYNC4 * tline;
+ constant CVSYNCALL : integer := CVSYNC1 + CVSYNC2 + CVSYNC3 + CVSYNC4; -- 510tline
+ signal href_time : std_logic;
+ signal pixel_time : std_logic;
+begin
+
+ -- check the clock period
+ p0 : process (i_rst) is
+ begin
+ if (i_rst = '0') then
+ assert (CLOCK_PERIOD = CLOCK_PERIOD1 or CLOCK_PERIOD = CLOCK_PERIOD2 or CLOCK_PERIOD = CLOCK_PERIOD3)
+ report "-- CLOCK_PERIOD must have " & integer'image(CLOCK_PERIOD1) & "," & integer'image(CLOCK_PERIOD2) & "," & integer'image(CLOCK_PERIOD3) & " --"
+ severity failure;
+ end if;
+ end process p0;
+
+ -- generate sync pulse
+ -- p.14 15 COM10 0x00 RW [2] - VSYNC changes on falling edge PCLK
+ p1 : process (i_xclk,i_rst) is
+ variable count : integer range 0 to CVSYNCALL*tline - 1;
+ variable vvsync : std_logic;
+ type states is (svs1,svs2,svs3,svs4);
+ variable state : states;
+ begin
+ if (i_rst = '0') then
+ count := 0;
+ vvsync := '0';
+ state := svs1;
+ href_time <= '0';
+ elsif (falling_edge(i_xclk)) then
+ case (state) is
+ when svs1 =>
+ vvsync := '1';
+ href_time <= '0';
+ if (count = VSYNC1) then
+ state := svs2;
+ count := 0;
+ else
+ state := svs1;
+ count := count + 1;
+ end if;
+ when svs2 =>
+ vvsync := '0';
+ href_time <= '0';
+ if (count = VSYNC2) then
+ state := svs3;
+ count := 0;
+ else
+ state := svs2;
+ count := count + 1;
+ end if;
+ when svs3 =>
+ vvsync := '0';
+ href_time <= '1';
+ if (count = VSYNC3) then
+ state := svs4;
+ count := 0;
+ else
+ state := svs3;
+ count := count + 1;
+ end if;
+ when svs4 =>
+ vvsync := '0';
+ href_time <= '0';
+ if (count = VSYNC4) then
+ state := svs1;
+ count := 0;
+ else
+ state := svs4;
+ count := count + 1;
+ end if;
+ end case;
+ o_vs <= vvsync;
+ end if;
+ end process p1;
+
+ -- generate href pulse
+ -- on falling edge
+ p2 : process (i_rst,i_xclk,href_time) is
+ variable count : integer range 0 to VSYNC3 - 1;
+ variable counth1 : integer range 0 to CHREF1 - 1;
+ variable counth0 : integer range 0 to CHREF0 - 1;
+ type states is (swait4vsync,shref1,shref0);
+ variable state : states;
+ variable vhref : std_logic;
+ begin
+ if (i_rst = '0') then
+ count := 0;
+ counth1 := 0;
+ counth0 := 0;
+ state := swait4vsync;
+ vhref := '0';
+ elsif (falling_edge(i_xclk)) then
+ case (state) is
+ when swait4vsync =>
+ pixel_time <= '0';
+ if (href_time = '1') then
+ if (count = VSYNC3) then
+ state := swait4vsync;
+ count := 0;
+ else
+ state := shref1;
+ pixel_time <= '1';
+ count := count + 1;
+ end if;
+ else
+ state := swait4vsync;
+ end if;
+ when shref1 =>
+ pixel_time <= '1';
+ vhref := '1';
+ if (counth1 = CHREF1 - 1) then
+ pixel_time <= '0';
+ state := shref0;
+ counth1 := 0;
+ else
+ state := shref1;
+ counth1 := counth1 + 1;
+ end if;
+ when shref0 =>
+ pixel_time <= '0';
+ vhref := '0';
+ if (counth0 = CHREF0 - 1) then
+ state := swait4vsync;
+ counth0 := 0;
+ else
+ state := shref0;
+ counth0 := counth0 + 1;
+ end if;
+ end case;
+ o_hs <= vhref;
+ end if;
+ end process p2;
+
+ p3 : process (i_rst,i_xclk,pixel_time) is
+ constant CDATALENGTH : integer := 5;
+ constant CNUMPIXELS : integer := HREF1 - CDATALENGTH*2;
+ variable count : integer range 0 to CDATALENGTH - 1;
+ type tdata is array(0 to CDATALENGTH - 1) of std_logic_vector(7 downto 0);
+ constant startdata : tdata := (x"FF",x"EE",x"DD",x"CC",x"BB");
+ constant enddata : tdata := (x"BB",x"CC",x"DD",x"EE",x"FF");
+ constant odddata : std_logic_vector(7 downto 0) := x"AA";
+ constant evendata : std_logic_vector(7 downto 0) := x"55";
+ type states is (s1,s2,s3);
+ variable state : states;
+ variable vd : std_logic_vector(7 downto 0);
+ begin
+ if (i_rst = '0') then
+ vd := (others => '0');
+ state := s1;
+ count := 0;
+ elsif (falling_edge(i_xclk)) then
+ if (pixel_time = '1') then
+ case (state) is
+ when s1 =>
+ vd := startdata(count);
+ if (count = CDATALENGTH - 1) then
+ count := 0;
+ state := s2;
+ else
+ count := count + 1;
+ state := s1;
+ end if;
+ when s2 =>
+ if (count = CNUMPIXELS - 1) then
+ state := s3;
+ count := 0;
+ else
+ state := s2;
+ if (count mod 2 = 0) then
+ vd := odddata;
+ count := count + 1;
+ elsif (count mod 2 = 1) then
+ vd := evendata;
+ count := count + 1;
+ else
+ vd := (others => 'U');
+ end if;
+ end if;
+ when s3 =>
+ vd := enddata(count);
+ if (count = CDATALENGTH - 1) then
+ count := 0;
+ state := s1;
+ else
+ count := count + 1;
+ state := s3;
+ end if;
+ end case;
+ else
+ vd := (others => '0');
+ end if;
+ o_d <= vd;
+ end if;
+ end process p3;
+
+o_pclk <= i_xclk;
+
+end Behavioral;
diff --git a/camera1/camera1.xise b/camera1/camera1.xise
new file mode 100755
index 0000000..2572654
--- /dev/null
+++ b/camera1/camera1.xise
@@ -0,0 +1,407 @@
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diff --git a/camera1/i3c2.vhd b/camera1/i3c2.vhd
new file mode 100755
index 0000000..4629e7e
--- /dev/null
+++ b/camera1/i3c2.vhd
@@ -0,0 +1,316 @@
+----------------------------------------------------------------------------------
+-- Engineer: Mike Field
+--
+-- Create Date: 21:30:20 05/25/2013
+-- Design Name: i3c2 - Intelligent I2C Controller
+-- Module Name: i3c2 - Behavioral
+-- Description: The main CPU/logic
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity i3c2 is
+ Generic( clk_divide : STD_LOGIC_VECTOR (7 downto 0));
+
+ Port ( clk : in STD_LOGIC;
+ inst_address : out STD_LOGIC_VECTOR (9 downto 0);
+ inst_data : in STD_LOGIC_VECTOR (8 downto 0);
+ i2c_scl : out STD_LOGIC;
+ i2c_sda : inout STD_LOGIC;
+ inputs : in STD_LOGIC_VECTOR (15 downto 0);
+ outputs : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
+ reg_addr : out STD_LOGIC_VECTOR (4 downto 0);
+ reg_data : out STD_LOGIC_VECTOR (7 downto 0);
+ reg_write : out STD_LOGIC;
+ error : out STD_LOGIC);
+end i3c2;
+
+architecture Behavioral of i3c2 is
+
+ constant STATE_RUN : std_logic_vector(3 downto 0) := "0000";
+ constant STATE_DELAY : std_logic_vector(3 downto 0) := "0001";
+ constant STATE_I2C_START : std_logic_vector(3 downto 0) := "0010";
+ constant STATE_I2C_BITS : std_logic_vector(3 downto 0) := "0011";
+ constant STATE_I2C_STOP : std_logic_vector(3 downto 0) := "0100";
+ signal state : std_logic_vector(3 downto 0) := STATE_RUN;
+
+ constant OPCODE_JUMP : std_logic_vector( 3 downto 0) := "0000";
+ constant OPCODE_SKIPSET : std_logic_vector( 3 downto 0) := "0001";
+ constant OPCODE_SKIPCLEAR : std_logic_vector( 3 downto 0) := "0010";
+ constant OPCODE_SET : std_logic_vector( 3 downto 0) := "0011";
+ constant OPCODE_CLEAR : std_logic_vector( 3 downto 0) := "0100";
+ constant OPCODE_I2C_READ : std_logic_vector( 3 downto 0) := "0101";
+ constant OPCODE_DELAY : std_logic_vector( 3 downto 0) := "0110";
+ constant OPCODE_SKIPACK : std_logic_vector( 3 downto 0) := "0111";
+ constant OPCODE_SKIPNACK : std_logic_vector( 3 downto 0) := "1000";
+ constant OPCODE_NOP : std_logic_vector( 3 downto 0) := "1001";
+ constant OPCODE_I2C_STOP : std_logic_vector( 3 downto 0) := "1010";
+ constant OPCODE_I2C_WRITE : std_logic_vector( 3 downto 0) := "1011";
+ constant OPCODE_WRITELOW : std_logic_vector( 3 downto 0) := "1100";
+ constant OPCODE_WRITEHI : std_logic_vector( 3 downto 0) := "1101";
+ constant OPCODE_UNKNOWN : std_logic_vector( 3 downto 0) := "1110";
+ signal opcode : std_logic_vector( 3 downto 0);
+
+
+ signal ack_flag : std_logic := '0';
+ signal skip : std_logic := '1'; -- IGNORE THE FIRST INSTRUCTION
+
+ -- I2C status
+ signal i2c_doing_read : std_logic := '0';
+ signal i2c_started : std_logic := '0';
+ signal i2c_bits_left : unsigned(3 downto 0);
+
+ -- counters
+ signal pcnext : unsigned(9 downto 0) := (others => '0');
+ signal delay : unsigned(15 downto 0);
+ signal bitcount : unsigned( 7 downto 0);
+
+ -- Input/output data
+ signal i2c_data : std_logic_vector( 8 downto 0);
+
+begin
+
+-- |Opcode | Instruction | Action
+-- +---------+-------------+----------------------------------------
+-- |00nnnnnnn| JUMP m | Set PC to m (n = m/8)
+-- |01000nnnn| SKIPCLEAR n | Skip if input n clear
+-- |01001nnnn| SKIPSET n | skip if input n set
+-- |01010nnnn| CLEAR n | Clear output n
+-- |01011nnnn| SET n | Set output n
+-- |0110nnnnn| READ n | Read to register n
+-- |01110nnnn| DELAY m | Delay m clock cycles (n = log2(m))
+-- |011110000| SKIPNACK | Skip if NACK is set
+-- |011110001| SKIPACK | Skip if ACK is set
+-- |011110010| WRITELOW | Write inputs 7 downto 0 to the I2C bus
+-- |011110011| WRITEHI | Write inputs 15 downto 8 to the I2C bus
+-- |011110100| USER0 | User defined
+-- |.........| |
+-- |011111110| USER9 | User defined
+-- |011111111| STOP | Send Stop on i2C bus
+-- |1nnnnnnnn| WRITE n | Output n on I2C bus
+
+ opcode <= OPCODE_JUMP when inst_data(8 downto 7) = "00" else
+ OPCODE_SKIPCLEAR when inst_data(8 downto 4) = "01000" else
+ OPCODE_SKIPSET when inst_data(8 downto 4) = "01001" else
+ OPCODE_CLEAR when inst_data(8 downto 4) = "01010" else
+ OPCODE_SET when inst_data(8 downto 4) = "01011" else
+ OPCODE_I2C_READ when inst_data(8 downto 5) = "0110" else
+ OPCODE_DELAY when inst_data(8 downto 4) = "01110" else
+ OPCODE_SKIPACK when inst_data(8 downto 0) = "011110000" else
+ OPCODE_SKIPNACK when inst_data(8 downto 0) = "011110001" else
+ OPCODE_WRITELOW when inst_data(8 downto 0) = "011110010" else
+ OPCODE_WRITEHI when inst_data(8 downto 0) = "011110011" else
+ -- user codes can go here
+ OPCODE_NOP when inst_data(8 downto 0) = "011111110" else
+ OPCODE_I2C_STOP when inst_data(8 downto 0) = "011111111" else
+ OPCODE_I2C_WRITE when inst_data(8 downto 8) = "1" else OPCODE_UNKNOWN;
+
+ inst_address <= std_logic_vector(pcnext);
+
+cpu: process(clk)
+ begin
+ if rising_edge(clk) then
+ case state is
+ when STATE_I2C_START =>
+ i2c_started <= '1';
+ i2c_scl <= 'Z';
+
+ if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
+ i2c_sda <= '0';
+ end if;
+
+ if bitcount = 0 then
+ state <= STATE_I2C_BITS;
+ i2c_scl <= '0';
+ bitcount <= unsigned(clk_divide);
+ else
+ bitcount <= bitcount-1;
+ end if;
+
+
+ when STATE_I2C_BITS => -- scl has always just lowered '0' on entry
+ -- set the data half way through clock low half of the cycle
+ if bitcount = unsigned(clk_divide) - unsigned("00" & clk_divide(clk_divide'high downto 2)) then
+ if i2c_data(8) = '0' then
+ i2c_sda <= '0';
+ else
+ i2c_sda <= 'Z';
+ end if;
+ end if;
+
+ -- raise the clock half way thorugh
+ if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
+ i2c_scl <= 'Z';
+ end if;
+
+ -- Input bits three quarters through the cycle
+ if bitcount = unsigned("00" & clk_divide(clk_divide'high downto 2)) then
+ i2c_data <= i2c_data(7 downto 0) & i2c_sda;
+ end if;
+
+ -- lower the clock at the end of the cycle
+ if bitcount = 0 then
+ i2c_scl <= '0';
+ if i2c_bits_left = "000" then
+ i2c_scl <= '0';
+ if i2c_doing_read = '1' then
+ reg_data <= i2c_data(8 downto 1);
+ reg_write <= '1';
+ end if;
+ ack_flag <= NOT i2c_data(0);
+ state <= STATE_RUN;
+ pcnext <= pcnext+1;
+ else
+ i2c_bits_left <= i2c_bits_left -1;
+ end if;
+ bitcount <= unsigned(clk_divide);
+ else
+ bitcount <= bitcount-1;
+ end if;
+
+
+ when STATE_I2C_STOP =>
+ -- clock stays high, and data goes high half way through a bit
+ i2c_started <= '0';
+ if bitcount = unsigned(clk_divide) - unsigned("00" & clk_divide(clk_divide'high downto 2)) then
+ i2c_sda <= '0';
+ end if;
+
+ if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
+ i2c_scl <= 'Z';
+ end if;
+
+ if bitcount = unsigned("00" & clk_divide(clk_divide'high downto 2)) then
+ i2c_sda <= 'Z';
+ end if;
+ if bitcount = 0 then
+ state <= STATE_RUN;
+ pcnext <= pcnext+1;
+ else
+ bitcount <= bitcount-1;
+ end if;
+
+ when STATE_DELAY =>
+ if bitcount /= 0 then
+ bitcount <= bitcount -1;
+ else
+ if delay = 0 then
+ pcnext <= pcnext+1;
+ state <= STATE_RUN;
+ else
+ delay <= delay-1;
+ bitcount <= unsigned(clk_divide) - 1;
+ end if;
+ end if;
+
+ when STATE_RUN =>
+ reg_data <= "XXXXXXXX";
+
+ if skip = '1'then
+ -- Do nothing for a cycle other than unset 'skip';
+ skip <= '0';
+ pcnext <= pcnext+1;
+ else
+ case opcode is
+ when OPCODE_JUMP =>
+ -- Ignore the next instruciton while fetching the jump destination
+ skip <= '1';
+ pcnext <= unsigned(inst_data(6 downto 0)) & "000";
+
+ when OPCODE_I2C_WRITE =>
+ i2c_data <= inst_data(7 downto 0) & "1";
+ bitcount <= unsigned(clk_divide);
+ i2c_doing_read <= '0';
+ i2c_bits_left <= "1000";
+ if i2c_started = '0' then
+ state <= STATE_I2C_START;
+ else
+ state <= STATE_I2C_BITS;
+ end if;
+
+ when OPCODE_I2C_READ =>
+ reg_addr <= inst_data(4 downto 0);
+ i2c_data <= x"FF" & "1"; -- keep the SDA pulled up while clocking in data & ACK
+ bitcount <= unsigned(clk_divide);
+ i2c_bits_left <= "1000";
+ i2c_doing_read <= '1';
+ if i2c_started = '0' then
+ state <= STATE_I2C_START;
+ else
+ state <= STATE_I2C_BITS;
+ end if;
+
+ when OPCODE_SKIPCLEAR =>
+ skip <= inputs(to_integer(unsigned(inst_data(3 downto 0)))) xnor inst_data(4);
+ pcnext <= pcnext+1;
+
+ when OPCODE_SKIPSET =>
+ skip <= inputs(to_integer(unsigned(inst_data(3 downto 0)))) xnor inst_data(4);
+ pcnext <= pcnext+1;
+
+ when OPCODE_CLEAR =>
+ outputs(to_integer(unsigned(inst_data(3 downto 0)))) <= inst_data(4);
+ pcnext <= pcnext+1;
+
+ when OPCODE_SET =>
+ outputs(to_integer(unsigned(inst_data(3 downto 0)))) <= inst_data(4);
+ pcnext <= pcnext+1;
+
+ when OPCODE_SKIPACK =>
+ skip <= ack_flag;
+ pcnext <= pcnext+1;
+
+ when OPCODE_SKIPNACK =>
+ skip <= not ack_flag;
+ pcnext <= pcnext+1;
+
+ when OPCODE_DELAY =>
+ state <= STATE_DELAY;
+ bitcount <= unsigned(clk_divide);
+ case inst_data(3 downto 0) is
+ when "0000" => delay <= x"0001";
+ when "0001" => delay <= x"0002";
+ when "0010" => delay <= x"0004";
+ when "0011" => delay <= x"0008";
+ when "0100" => delay <= x"0010";
+ when "0101" => delay <= x"0020";
+ when "0110" => delay <= x"0040";
+ when "0111" => delay <= x"0080";
+ when "1000" => delay <= x"0100";
+ when "1001" => delay <= x"0200";
+ when "1010" => delay <= x"0400";
+ when "1011" => delay <= x"0800";
+ when "1100" => delay <= x"1000";
+ when "1101" => delay <= x"2000";
+ when "1110" => delay <= x"4000";
+ when others => delay <= x"8000";
+ end case;
+
+ when OPCODE_I2C_STOP =>
+ bitcount <= unsigned(clk_divide);
+ state <= STATE_I2C_STOP;
+
+ when OPCODE_NOP =>
+ pcnext <= pcnext+1;
+ outputs(0) <= '1';
+ when others =>
+ error <= '1';
+
+ end case;
+ end if;
+
+ when others =>
+ state <= STATE_RUN;
+ pcnext <= (others => '0');
+ skip <= '1';
+
+ end case;
+ end if;
+ end process;
+end Behavioral;
diff --git a/camera1/ov7670_capture.vhd b/camera1/ov7670_capture.vhd
new file mode 100755
index 0000000..56f04b6
--- /dev/null
+++ b/camera1/ov7670_capture.vhd
@@ -0,0 +1,113 @@
+----------------------------------------------------------------------------------
+-- Engineer: Mike Field
+--
+-- Description: Captures the pixels coming from the OV7670 camera and
+-- Stores them in block RAM
+--
+-- The length of href last controls how often pixels are captive - (2 downto 0) stores
+-- one pixel every 4 cycles.
+--
+-- "line" is used to control how often data is captured. In this case every forth
+-- line
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity ov7670_capture is
+ Port ( pclk : in STD_LOGIC;
+ rez_160x120 : IN std_logic;
+ rez_320x240 : IN std_logic;
+ vsync : in STD_LOGIC;
+ href : in STD_LOGIC;
+ d : in STD_LOGIC_VECTOR (7 downto 0);
+ addr : out STD_LOGIC_VECTOR (14 downto 0);
+ dout : out STD_LOGIC_VECTOR (7 downto 0);
+ we : out STD_LOGIC);
+end ov7670_capture;
+
+architecture Behavioral of ov7670_capture is
+ signal d_latch : std_logic_vector(2*d'left+1 downto 0) := (others => '0');
+ signal address : STD_LOGIC_VECTOR(addr'left downto 0) := (others => '0');
+ signal line : std_logic_vector(1 downto 0) := (others => '0');
+ signal href_last : std_logic_vector(6 downto 0) := (others => '0');
+ signal we_reg : std_logic := '0';
+ signal href_hold : std_logic := '0';
+ signal latched_vsync : STD_LOGIC := '0';
+ signal latched_href : STD_LOGIC := '0';
+ signal latched_d : STD_LOGIC_VECTOR (d'left downto 0) := (others => '0');
+begin
+ addr <= address;
+ we <= we_reg;
+ dout <= d_latch(15 downto 13) & d_latch(12 downto 10) & d_latch(9 downto 8);
+-- dout <= d_latch(7 downto 5) & d_latch(4 downto 2) & d_latch(1 downto 0);
+-- dout <= d_latch(10 downto 8) & d_latch(6 downto 4) & d_latch(1 downto 0);
+-- dout <= d_latch;
+
+capture_process: process(pclk)
+ begin
+ if falling_edge(pclk) then
+ if we_reg = '1' then
+ address <= std_logic_vector(unsigned(address)+1);
+ end if;
+
+ -- This is a bit tricky href starts a pixel transfer that takes 3 cycles
+ -- Input | state after clock tick
+ -- href | wr_hold d_latch dout we address address_next
+ -- cycle -1 x | xx xxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxx xxxx
+ -- cycle 0 1 | x1 xxxxxxxxRRRRRGGG xxxxxxxxxxxx x xxxx addr
+ -- cycle 1 0 | 10 RRRRRGGGGGGBBBBB xxxxxxxxxxxx x addr addr
+ -- cycle 2 x | 0x GGGBBBBBxxxxxxxx RRRRGGGGBBBB 1 addr addr+1
+
+ -- detect the rising edge on href - the start of the scan line
+ if href_hold = '0' and latched_href = '1' then
+ case line is
+ when "00" => line <= "01";
+ when "01" => line <= "10";
+ when "10" => line <= "11";
+ when others => line <= "00";
+ end case;
+ end if;
+ href_hold <= latched_href;
+
+ -- capturing the data from the camera, 12-bit RGB
+ if latched_href = '1' then
+ d_latch <= d_latch( 7 downto 0) & latched_d;
+ end if;
+ we_reg <= '0';
+
+ -- Is a new screen about to start (i.e. we have to restart capturing
+ if latched_vsync = '1' then
+ address <= (others => '0');
+ href_last <= (others => '0');
+ line <= (others => '0');
+ else
+ -- If not, set the write enable whenever we need to capture a pixel
+ if (rez_160x120 = '1' and href_last(6) = '1') or
+ (rez_320x240 = '1' and href_last(2) = '1') or
+ (rez_160x120 = '0' and rez_320x240 = '0' and href_last(0) = '1') then
+
+ if rez_160x120 = '1' then
+ if line = "10" then
+ we_reg <= '1';
+ end if;
+ elsif rez_320x240 = '1' then
+ if line(1) = '1' then
+ we_reg <= '1';
+ end if;
+ else
+ we_reg <= '1';
+ end if;
+ href_last <= (others => '0');
+ else
+ href_last <= href_last(href_last'high-1 downto 0) & latched_href;
+ end if;
+ end if;
+ end if;
+ if falling_edge(pclk) then
+ latched_d <= d;
+ latched_href <= href;
+ latched_vsync <= vsync;
+ end if;
+ end process;
+end Behavioral;
diff --git a/camera1/ov7670_controller.vhd b/camera1/ov7670_controller.vhd
new file mode 100755
index 0000000..c00a246
--- /dev/null
+++ b/camera1/ov7670_controller.vhd
@@ -0,0 +1,326 @@
+----------------------------------------------------------------------------------
+-- Engineer: Mike Field
+--
+-- Description: Controller for the OV760 camera - transferes registers to the
+-- camera over an I2C like bus
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity ov7670_controller is
+ Port ( clk : in STD_LOGIC;
+ resend :in STD_LOGIC;
+ config_finished : out std_logic;
+ sioc : out STD_LOGIC;
+ siod : inout STD_LOGIC;
+ reset : out STD_LOGIC;
+ pwdn : out STD_LOGIC;
+ xclk : out STD_LOGIC
+);
+end ov7670_controller;
+
+architecture Behavioral of ov7670_controller is
+ COMPONENT i3c2 GENERIC (
+ clk_divide : std_logic_vector(7 downto 0)
+ );
+ PORT(
+ clk : IN std_logic;
+ inst_data : IN std_logic_vector(8 downto 0);
+ inputs : IN std_logic_vector(15 downto 0);
+ i2c_sda : INOUT std_logic;
+ inst_address : OUT std_logic_vector(9 downto 0);
+ i2c_scl : OUT std_logic;
+ outputs : OUT std_logic_vector(15 downto 0);
+ reg_addr : OUT std_logic_vector(4 downto 0);
+ reg_data : OUT std_logic_vector(7 downto 0);
+ reg_write : OUT std_logic;
+ error : OUT std_logic
+ );
+ END COMPONENT;
+
+ signal inputs : std_logic_vector(15 downto 0);
+ signal outputs : std_logic_vector(15 downto 0);
+ signal data : std_logic_vector( 8 downto 0);
+ signal address : std_logic_vector( 9 downto 0);
+ signal sys_clk : std_logic := '0';
+begin
+ inputs(0) <= resend;
+ config_finished <= outputs(0);
+
+ Inst_i3c2: i3c2 GENERIC MAP(
+ clk_divide => std_logic_vector(to_unsigned(125,8))
+ ) PORT MAP(
+ clk => clk,
+ inst_address => address ,
+ inst_data => data,
+ i2c_scl => sioc,
+ i2c_sda => siod,
+ inputs => inputs,
+ outputs => outputs,
+ reg_addr => open,
+ reg_data => open,
+ reg_write => open,
+ error => open
+ );
+
+ reset <= '1'; -- Normal mode
+ pwdn <= '0'; -- Power device up
+ xclk <= sys_clk;
+
+ process(clk)
+ begin
+ if rising_edge(clk) then
+ sys_clk <= not sys_clk;
+
+ case address is
+ when "0000000000" => data <= "011100100"; -- delay
+ when "0000000001" => data <= "101000010"; -- 0x42
+ when "0000000010" => data <= "100010010"; -- 0x12 COM7
+ when "0000000011" => data <= "110000000"; -- reset all regs
+ when "0000000100" => data <= "011111111"; -- send
+ when "0000000101" => data <= "011101001"; -- delay long
+ when "0000000110" => data <= "101000010"; -- 0x42
+ when "0000000111" => data <= "100010010"; -- 0x12 COM7
+ when "0000001000" => data <= "100000100"; -- set RGB XXXXXXXXXXXXXXXXXXXXXXXXXXXXx
+ when "0000001001" => data <= "011111111"; -- send
+ when "0000001010" => data <= "101000010"; -- 0x42
+ when "0000001011" => data <= "100010001"; -- 0x11 CLKRC
+ when "0000001100" => data <= "100000000"; -- 0x00 or 0x80 default
+ when "0000001101" => data <= "011111111"; -- send
+ when "0000001110" => data <= "101000010"; -- 0x42
+ when "0000001111" => data <= "100001100"; -- 0x0C COM3
+ when "0000010000" => data <= "100000000"; -- 0x00 default
+ when "0000010001" => data <= "011111111"; -- send
+ when "0000010010" => data <= "101000010"; -- 0x42
+ when "0000010011" => data <= "100111110"; -- 0x3E COM14
+ when "0000010100" => data <= "100000000"; -- 0x00 default
+ when "0000010101" => data <= "011111111"; -- send
+ when "0000010110" => data <= "101000010"; -- 0x42
+ when "0000010111" => data <= "110001100"; -- 0x8C RGB444
+ when "0000011000" => data <= "100000011"; -- enable RGBx
+ when "0000011001" => data <= "011111111"; -- send
+ when "0000011010" => data <= "101000010"; -- 0x42
+ when "0000011011" => data <= "100000100"; -- 0x08 RAVE
+ when "0000011100" => data <= "100000000"; -- 0x00 default
+ when "0000011101" => data <= "011111111"; -- send
+ when "0000011110" => data <= "101000010"; -- 0x42
+ when "0000011111" => data <= "101000000"; -- 0x40 COM15
+ when "0000100000" => data <= "111110000"; --
+ when "0000100001" => data <= "011111111"; -- send
+ when "0000100010" => data <= "101000010"; -- 0x42
+ when "0000100011" => data <= "100111010"; -- 0x3A TSLB
+ when "0000100100" => data <= "100000100"; -- 0x0D default, use reserved bit
+ when "0000100101" => data <= "011111111"; -- send
+ when "0000100110" => data <= "101000010"; -- 0x42
+ when "0000100111" => data <= "100010100"; -- 0x14 COM9
+ when "0000101000" => data <= "100111000"; -- 0x4A default
+ when "0000101001" => data <= "011111111"; -- send
+ when "0000101010" => data <= "101000010"; -- 0x42
+ when "0000101011" => data <= "101001111"; -- 0x4F MTX1
+ when "0000101100" => data <= "101000000"; -- 0x40 default
+ when "0000101101" => data <= "011111111"; -- send
+ when "0000101110" => data <= "101000010"; -- 0x42
+ when "0000101111" => data <= "101010000"; -- 0x50 MTX2
+ when "0000110000" => data <= "100110100"; -- 0x34 default
+ when "0000110001" => data <= "011111111"; -- send
+ when "0000110010" => data <= "101000010"; -- 0x42
+ when "0000110011" => data <= "101010001"; -- 0x51 MTX3
+ when "0000110100" => data <= "100001100"; -- 0x0C default
+ when "0000110101" => data <= "011111111"; -- send
+ when "0000110110" => data <= "101000010"; -- 0x42
+ when "0000110111" => data <= "101010010"; -- 0x52 MTX4
+ when "0000111000" => data <= "100010111"; -- 0x17 default
+ when "0000111001" => data <= "011111111"; -- send
+ when "0000111010" => data <= "101000010"; -- 0x42
+ when "0000111011" => data <= "101010011"; -- 0x53 MTX5
+ when "0000111100" => data <= "100101001"; -- 0x29 default
+ when "0000111101" => data <= "011111111"; -- send
+ when "0000111110" => data <= "101000010"; -- 0x42
+ when "0000111111" => data <= "101010100"; -- 0x54 MTX6
+ when "0001000000" => data <= "101000000"; -- 0x40 default
+ when "0001000001" => data <= "011111111"; -- send
+ when "0001000010" => data <= "101000010"; -- 0x42
+ when "0001000011" => data <= "101011000"; -- 0x58 MTXS
+ when "0001000100" => data <= "100011110"; -- 0x1E default
+ when "0001000101" => data <= "011111111"; -- send
+ when "0001000110" => data <= "101000010"; -- 0x42
+ when "0001000111" => data <= "100111101"; -- 0x3D COM13
+ when "0001001000" => data <= "111000000"; -- 0x88 default,gamma enable,UVSL-UV auto adjust
+ when "0001001001" => data <= "011111111"; -- send
+ when "0001001010" => data <= "101000010"; -- 0x42
+ when "0001001011" => data <= "100010001"; -- 0x11 CLKRC
+ when "0001001100" => data <= "100000000"; -- 0x00 or 0x80 default,not use reserved bits
+ when "0001001101" => data <= "011111111"; -- send
+ when "0001001110" => data <= "101000010"; -- 0x42
+ when "0001001111" => data <= "100010111"; -- 0x17 HSTART
+ when "0001010000" => data <= "100010001"; -- 0x11 default
+ when "0001010001" => data <= "011111111"; -- send
+ when "0001010010" => data <= "101000010"; -- 0x42
+ when "0001010011" => data <= "100011000"; -- 0x18 HSTOP
+ when "0001010100" => data <= "101100001"; -- 0x61 default
+ when "0001010101" => data <= "011111111"; -- send
+ when "0001010110" => data <= "101000010"; -- 0x42
+ when "0001010111" => data <= "100110010"; -- 0x32 HREF
+ when "0001011000" => data <= "110100100"; -- 0x80 default,HREF start/end low 3 LSB
+ when "0001011001" => data <= "011111111"; -- send
+ when "0001011010" => data <= "101000010"; -- 0x42
+ when "0001011011" => data <= "100011001"; -- 0x19 VSTRT
+ when "0001011100" => data <= "100000011"; -- 0x03 default
+ when "0001011101" => data <= "011111111"; -- send
+ when "0001011110" => data <= "101000010"; -- 0x42
+ when "0001011111" => data <= "100011010"; -- 0x1A VSTOP
+ when "0001100000" => data <= "101111011"; -- 0x7B default
+ when "0001100001" => data <= "011111111"; -- send
+ when "0001100010" => data <= "101000010"; -- 0x42
+ when "0001100011" => data <= "100000011"; -- 0x03 VREF
+ when "0001100100" => data <= "100001010"; -- 0x00 default,VREF start/end low 2 bit
+ when "0001100101" => data <= "011111111"; -- send
+ when "0001100110" => data <= "101000010"; -- 0x42
+ when "0001100111" => data <= "100001110"; -- 0x07 AECHH
+ when "0001101000" => data <= "101100001"; -- 0x00 default,?
+ when "0001101001" => data <= "011111111"; -- send
+ when "0001101010" => data <= "101000010"; -- 0x42
+ when "0001101011" => data <= "100001111"; -- 0x0F COM6
+ when "0001101100" => data <= "101001011"; -- 0x43 default,use 0x4B
+ when "0001101101" => data <= "011111111"; -- send
+ when "0001101110" => data <= "101000010"; -- 0x42
+ when "0001101111" => data <= "100010110"; -- 0x16 RSVD
+ when "0001110000" => data <= "100000010"; -- 0xXX default
+ when "0001110001" => data <= "011111111"; -- send
+ when "0001110010" => data <= "101000010"; -- 0x42
+ when "0001110011" => data <= "100011110"; -- 0x1E MVFP
+ when "0001110100" => data <= "100000101"; -- 0x01 default,mirror/vflip image,black sun enable
+ when "0001110101" => data <= "011111111"; -- send
+ when "0001110110" => data <= "101000010"; -- 0x42
+ when "0001110111" => data <= "100100001"; -- 0x21 ADCCTR1
+ when "0001111000" => data <= "100000010"; -- 0x02 default
+ when "0001111001" => data <= "011111111"; -- send
+ when "0001111010" => data <= "101000010"; -- 0x42
+ when "0001111011" => data <= "100100010"; -- 0x22 ADCCTR2
+ when "0001111100" => data <= "110010001"; -- 0x01 default,?
+ when "0001111101" => data <= "011111111"; -- send
+ when "0001111110" => data <= "101000010"; -- 0x42
+ when "0001111111" => data <= "100101001"; -- 0x29 RSVD
+ when "0010000000" => data <= "100000111"; -- 0xXX default,?
+ when "0010000001" => data <= "011111111"; -- send
+ when "0010000010" => data <= "101000010"; -- 0x42
+ when "0010000011" => data <= "100110011"; -- 0x33 CHLF
+ when "0010000100" => data <= "100001011"; -- 0x08 default,?
+ when "0010000101" => data <= "011111111"; -- send
+ when "0010000110" => data <= "101000010"; -- 0x42
+ when "0010000111" => data <= "100110101"; -- 0x35 RSVD
+ when "0010001000" => data <= "100001011"; -- 0xXX default,?
+ when "0010001001" => data <= "011111111"; -- send
+ when "0010001010" => data <= "101000010"; -- 0x42
+ when "0010001011" => data <= "100110111"; -- 0x37 ADC
+ when "0010001100" => data <= "100011101"; -- 0x3F default,?
+ when "0010001101" => data <= "011111111"; -- send
+ when "0010001110" => data <= "101000010"; -- 0x42
+ when "0010001111" => data <= "100111000"; -- 0x38 ACOM
+ when "0010010000" => data <= "101110001"; -- 0x01 default,?
+ when "0010010001" => data <= "011111111"; -- send
+ when "0010010010" => data <= "101000010"; -- 0x42
+ when "0010010011" => data <= "100111001"; -- 0x39 OFON
+ when "0010010100" => data <= "100101010"; -- 0x00 default,?
+ when "0010010101" => data <= "011111111"; -- send
+ when "0010010110" => data <= "101000010"; -- 0x42
+ when "0010010111" => data <= "100111100"; -- 0x3C COM12
+ when "0010011000" => data <= "101111000"; -- 0x68 default,?
+ when "0010011001" => data <= "011111111"; -- send
+ when "0010011010" => data <= "101000010"; -- 0x42
+ when "0010011011" => data <= "101001101"; -- 0x4D RSVD
+ when "0010011100" => data <= "101000000"; -- 0xXX default,?
+ when "0010011101" => data <= "011111111"; -- send
+ when "0010011110" => data <= "101000010"; -- 0x42
+ when "0010011111" => data <= "101001110"; -- 0x4E RSVD
+ when "0010100000" => data <= "100100000"; -- 0xXX default,?
+ when "0010100001" => data <= "011111111"; -- send
+ when "0010100010" => data <= "101000010"; -- 0x42
+ when "0010100011" => data <= "101101001"; -- 0x69 GFIX
+ when "0010100100" => data <= "100000000"; -- 0x00 default
+ when "0010100101" => data <= "011111111"; -- send
+ when "0010100110" => data <= "101000010"; -- 0x42
+ when "0010100111" => data <= "101101011"; -- 0x6B DBLV PLL CONTROL
+ when "0010101000" => data <= "101001010"; -- 0x0A default,input clock 4x
+ when "0010101001" => data <= "011111111"; -- send
+ when "0010101010" => data <= "101000010"; -- 0x42
+ when "0010101011" => data <= "101110100"; -- 0x74 REG74
+ when "0010101100" => data <= "100010000"; -- 0x00 default,digital gain control REG74/bypass
+ when "0010101101" => data <= "011111111"; -- send
+ when "0010101110" => data <= "101000010"; -- 0x42
+ when "0010101111" => data <= "110001101"; -- 0x8D RSVD
+ when "0010110000" => data <= "101001111"; -- 0xXX default,?
+ when "0010110001" => data <= "011111111"; -- send
+ when "0010110010" => data <= "101000010"; -- 0x42
+ when "0010110011" => data <= "110001110"; -- 0x8E RSVD
+ when "0010110100" => data <= "100000000"; -- 0xXX default,?
+ when "0010110101" => data <= "011111111"; -- send
+ when "0010110110" => data <= "101000010"; -- 0x42
+ when "0010110111" => data <= "110001111"; -- 0x8F RSVD
+ when "0010111000" => data <= "100000000"; -- 0xXX default,?
+ when "0010111001" => data <= "011111111"; -- send
+ when "0010111010" => data <= "101000010"; -- 0x42
+ when "0010111011" => data <= "110010000"; -- 0x90 RSVD
+ when "0010111100" => data <= "100000000"; -- 0xXX default,?
+ when "0010111101" => data <= "011111111"; -- send
+ when "0010111110" => data <= "101000010"; -- 0x42
+ when "0010111111" => data <= "110010001"; -- 0x91 RSVD
+ when "0011000000" => data <= "100000000"; -- 0xXX default,?
+ when "0011000001" => data <= "011111111"; -- send
+ when "0011000010" => data <= "101000010"; -- 0x42
+ when "0011000011" => data <= "110010110"; -- 0x96 RSVD
+ when "0011000100" => data <= "100000000"; -- 0xXX default,?
+ when "0011000101" => data <= "011111111"; -- send
+ when "0011000110" => data <= "101000010"; -- 0x42
+ when "0011000111" => data <= "110011010"; -- 0x9A RSVD
+ when "0011001000" => data <= "100000000"; -- 0xXX default,?
+ when "0011001001" => data <= "011111111"; -- send
+ when "0011001010" => data <= "101000010"; -- 0x42
+ when "0011001011" => data <= "110110000"; -- 0xB0 RSVD
+ when "0011001100" => data <= "110000100"; -- 0xXX default,?
+ when "0011001101" => data <= "011111111"; -- send
+ when "0011001110" => data <= "101000010"; -- 0x42
+ when "0011001111" => data <= "110110001"; -- 0xB1 ABLC1
+ when "0011010000" => data <= "100001100"; -- 0x00 default,enable ABLC func
+ when "0011010001" => data <= "011111111"; -- send
+ when "0011010010" => data <= "101000010"; -- 0x42
+ when "0011010011" => data <= "110110010"; -- 0xB2 RSVD
+ when "0011010100" => data <= "100001110"; -- 0xXX default,?
+ when "0011010101" => data <= "011111111"; -- send
+ when "0011010110" => data <= "101000010"; -- 0x42
+ when "0011010111" => data <= "110110011"; -- 0xB3 THL_ST
+ when "0011011000" => data <= "110000010"; -- 0x80 default,?
+ when "0011011001" => data <= "011111111"; -- send
+ when "0011011010" => data <= "101000010"; -- 0x42
+ when "0011011011" => data <= "110111000"; -- 0xB8 RSVD
+ when "0011011100" => data <= "100001010"; -- 0xXX default,?
+ when "0011011101" => data <= "011111111"; -- send
+
+-- when "0011011110" => data <= "101000010"; -- 0x42
+-- when "0011011111" => data <= "110111000"; -- 0xB8 RSVD
+-- when "0011100000" => data <= "100000000"; -- 0xXX default,?
+-- when "0011100001" => data <= "011111111"; -- send
+--
+-- when "0011100010" => data <= "101000010"; -- 0x42
+-- when "0011100011" => data <= "110111000"; -- 0xB8 RSVD
+-- when "0011100100" => data <= "100000000"; -- 0xXX default,?
+-- when "0011100101" => data <= "011111111"; -- send
+
+-- when "0011100110" => data <= "011111110"; -- user defined
+-- when "0011100111" => data <= "011111110"; -- user defined
+-- when "0011101000" => data <= "010000000"; -- SKIPCLEAR n | Skip if input n clear
+-- when "0011101001" => data <= "000000000"; -- JUMP m | Set PC to m (n = m/8),0
+-- when "0011101010" => data <= "000011100"; -- JUMP m | Set PC to m (n = m/8),28,m=n*8,m=28*8=224
+
+ when "0011011110" => data <= "011111110"; -- user defined
+ when "0011011111" => data <= "011111110"; -- user defined
+ when "0011100000" => data <= "010000000"; -- SKIPCLEAR n | Skip if input n clear
+ when "0011100001" => data <= "000000000"; -- JUMP m | Set PC to m (n = m/8),0
+ when "0011100010" => data <= "000011100"; -- JUMP m | Set PC to m (n = m/8),28,m=n*8,m=28*8=224
+
+ when others => data <= (others =>'0'); -- all list have 226 instructions,XXX TODO
+ end case;
+ end if;
+ end process;
+end Behavioral;
diff --git a/camera1/tb_camera.vhd b/camera1/tb_camera.vhd
new file mode 100755
index 0000000..5f3c580
--- /dev/null
+++ b/camera1/tb_camera.vhd
@@ -0,0 +1,120 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:18:44 07/10/2022
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/camera1/tb_camera.vhd
+-- Project Name: camera1
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: camera
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_camera IS
+END tb_camera;
+
+ARCHITECTURE behavior OF tb_camera IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT camera
+PORT(
+io_scl : INOUT std_logic;
+io_sda : INOUT std_logic;
+o_vs : OUT std_logic;
+o_hs : OUT std_logic;
+o_pclk : OUT std_logic;
+i_xclk : IN std_logic;
+o_d : OUT std_logic_vector(7 downto 0);
+i_rst : IN std_logic;
+i_pwdn : IN std_logic
+);
+END COMPONENT;
+
+
+--Inputs
+signal i_xclk : std_logic := '0';
+signal i_rst : std_logic := '0';
+signal i_pwdn : std_logic := '0';
+
+--BiDirs
+signal io_scl : std_logic;
+signal io_sda : std_logic;
+
+--Outputs
+signal o_vs : std_logic;
+signal o_hs : std_logic;
+signal o_pclk : std_logic;
+signal o_d : std_logic_vector(7 downto 0);
+
+-- Clock period definitions
+--constant o_pclk_period : time := 10 ns;
+constant i_xclk_period : time := 42 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: camera PORT MAP (
+io_scl => io_scl,
+io_sda => io_sda,
+o_vs => o_vs,
+o_hs => o_hs,
+o_pclk => o_pclk,
+i_xclk => i_xclk,
+o_d => o_d,
+i_rst => i_rst,
+i_pwdn => i_pwdn
+);
+
+---- Clock process definitions
+--o_pclk_process : process
+--begin
+--o_pclk <= '0';
+--wait for o_pclk_period/2;
+--o_pclk <= '1';
+--wait for o_pclk_period/2;
+--end process;
+
+i_xclk_process : process
+begin
+i_xclk <= '0';
+wait for i_xclk_period/2;
+i_xclk <= '1';
+wait for i_xclk_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+i_rst <= '0';
+wait for 100 ns;
+i_rst <= '1';
+wait for i_xclk_period*10;
+-- insert stimulus here
+wait;
+end process;
+
+END;
diff --git a/camera1/tb_top.vhd b/camera1/tb_top.vhd
new file mode 100755
index 0000000..b039881
--- /dev/null
+++ b/camera1/tb_top.vhd
@@ -0,0 +1,198 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:16:58 07/09/2022
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/camera1/tb_top.vhd
+-- Project Name: camera1
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_top IS
+END tb_top;
+
+ARCHITECTURE behavior OF tb_top IS
+
+COMPONENT camera
+PORT(
+io_scl : INOUT std_logic;
+io_sda : INOUT std_logic;
+o_vs : OUT std_logic;
+o_hs : OUT std_logic;
+o_pclk : OUT std_logic;
+i_xclk : IN std_logic;
+o_d : OUT std_logic_vector(7 downto 0);
+i_rst : IN std_logic;
+i_pwdn : IN std_logic
+);
+END COMPONENT;
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT top
+PORT(
+i_clock : IN std_logic;
+o_r : OUT std_logic_vector(3 downto 1);
+o_g : OUT std_logic_vector(3 downto 1);
+o_b : OUT std_logic_vector(3 downto 2);
+o_h : OUT std_logic;
+o_v : OUT std_logic;
+i_sw : IN std_logic_vector(7 downto 0);
+cam_xclk : OUT std_logic;
+cam_pclk : IN std_logic;
+cam_sioc : INOUT std_logic;
+cam_siod : INOUT std_logic;
+cam_data : IN std_logic_vector(7 downto 0);
+cam_vsync : IN std_logic;
+cam_href : IN std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_sw : std_logic_vector(7 downto 0) := (others => '0');
+signal cam_pclk : std_logic := '0';
+signal cam_data : std_logic_vector(7 downto 0) := (others => '0');
+signal cam_vsync : std_logic := '0';
+signal cam_href : std_logic := '0';
+
+--BiDirs
+signal cam_sioc : std_logic;
+signal cam_siod : std_logic;
+
+--Outputs
+signal o_r : std_logic_vector(3 downto 1);
+signal o_g : std_logic_vector(3 downto 1);
+signal o_b : std_logic_vector(3 downto 2);
+signal o_h : std_logic;
+signal o_v : std_logic;
+signal cam_xclk : std_logic;
+
+-- Clock period definitions
+constant i_clock_period : time := 20 ns;
+-- constant cam_xclk_period : time := 40 ns;
+constant cam_pclk_period : time := 41 ns;
+
+--Inputs
+signal i_xclk : std_logic := '0';
+signal i_rst : std_logic := '0';
+signal i_pwdn : std_logic := '0';
+
+--BiDirs
+signal io_scl : std_logic;
+signal io_sda : std_logic;
+
+--Outputs
+signal o_vs : std_logic;
+signal o_hs : std_logic;
+signal o_pclk : std_logic;
+signal o_d : std_logic_vector(7 downto 0);
+
+-- Clock period definitions
+--constant o_pclk_period : time := 10 ns;
+constant i_xclk_period : time := 41 ns;
+
+BEGIN
+
+cam : camera PORT MAP (
+io_scl => io_scl,
+io_sda => io_sda,
+o_vs => o_vs,
+o_hs => o_hs,
+o_pclk => o_pclk,
+i_xclk => i_xclk,
+o_d => o_d,
+i_rst => i_rst,
+i_pwdn => i_pwdn
+);
+
+-- Instantiate the Unit Under Test (UUT)
+uut: top PORT MAP (
+i_clock => i_clock,
+o_r => o_r,
+o_g => o_g,
+o_b => o_b,
+o_h => o_h,
+o_v => o_v,
+i_sw => i_sw,
+cam_xclk => cam_xclk,
+cam_pclk => cam_pclk,
+cam_sioc => cam_sioc,
+cam_siod => cam_siod,
+cam_data => o_d,
+cam_vsync => o_vs,
+cam_href => o_hs
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- cam_xclk_process :process
+-- begin
+-- cam_xclk <= '0';
+-- wait for cam_xclk_period/2;
+-- cam_xclk <= '1';
+-- wait for cam_xclk_period/2;
+-- end process;
+
+cam_pclk_process :process
+begin
+cam_pclk <= '0';
+wait for cam_pclk_period/2;
+cam_pclk <= '1';
+wait for cam_pclk_period/2;
+end process;
+
+i_xclk_process : process
+begin
+i_xclk <= '0';
+wait for i_xclk_period/2;
+i_xclk <= '1';
+wait for i_xclk_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+i_sw(0) <= '1';
+i_rst <= '0';
+wait for 100 ns;
+i_sw(0) <= '0';
+i_rst <= '1';
+wait for i_clock_period*10;
+-- insert stimulus here
+wait;
+end process;
+
+END;
diff --git a/camera1/top.ucf b/camera1/top.ucf
new file mode 100755
index 0000000..91e880a
--- /dev/null
+++ b/camera1/top.ucf
@@ -0,0 +1,81 @@
+NET "i_clock" LOC="B8";
+#NET "i_clock" LOC="U9";
+#NET "i_reset" LOC="B18";
+NET "o_r<1>" LOC="R9";
+NET "o_r<2>" LOC="T8";
+NET "o_r<3>" LOC="R8";
+NET "o_g<1>" LOC="N8";
+NET "o_g<2>" LOC="P8";
+NET "o_g<3>" LOC="P6";
+NET "o_b<2>" LOC="U5";
+NET "o_b<3>" LOC="U4";
+NET "o_h" LOC="T4";
+NET "o_v" LOC="U3";
+
+NET "i_sw<0>" LOC = "G18";
+NET "i_sw<1>" LOC = "H18";
+NET "i_sw<2>" LOC = "K18";
+NET "i_sw<3>" LOC = "K17";
+NET "i_sw<4>" LOC = "L14";
+NET "i_sw<5>" LOC = "L13";
+NET "i_sw<6>" LOC = "N17";
+NET "i_sw<7>" LOC = "R17";
+
+NET "btn<0>" LOC = "B18";
+NET "btn<1>" LOC = "D18";
+NET "btn<2>" LOC = "E18";
+NET "btn<3>" LOC = "H13";
+
+NET "cam_pclk" LOC = "H16";
+NET "cam_xclk" LOC = "M15";
+NET "cam_sioc" LOC = "J13";
+NET "cam_siod" LOC = "M18";
+NET "cam_data<0>" LOC = "M13";
+NET "cam_data<1>" LOC = "R18";
+NET "cam_data<2>" LOC = "R15";
+NET "cam_data<3>" LOC = "T17";
+NET "cam_data<4>" LOC = "P17";
+NET "cam_data<5>" LOC = "R16";
+NET "cam_data<6>" LOC = "T18";
+NET "cam_data<7>" LOC = "U18";
+NET "cam_vsync" LOC = "K12";
+NET "cam_href" LOC = "L17";
+NET "cam_rst" LOC = "L15";
+
+NET "cam_pclk" CLOCK_DEDICATED_ROUTE = FALSE;
+
+#NET "JA<0>" LOC = "L15"; # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1
+#NET "JA<1>" LOC = "K12"; # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2
+#NET "JA<2>" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
+#NET "JA<3>" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
+#NET "JA<4>" LOC = "K13"; # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL, Sch name = JA7
+#NET "JA<5>" LOC = "L16"; # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL, Sch name = JA8
+#NET "JA<6>" LOC = "M14"; # Bank = 1, Pin name = IO_L05P_1, Type = I/O, Sch name = JA9
+#NET "JA<7>" LOC = "M16"; # Bank = 1, Pin name = IO_L07N_1, Type = I/O, Sch name = JA10
+#
+#NET "JB<0>" LOC = "M13"; # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF, Sch name = JB1
+#NET "JB<1>" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
+#NET "JB<2>" LOC = "R15"; # Bank = 1, Pin name = IO_L03P_1, Type = I/O, Sch name = JB3
+#NET "JB<3>" LOC = "T17"; # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL, Sch name = JB4
+#NET "JB<4>" LOC = "P17"; # Bank = 1, Pin name = IO_L06P_1, Type = I/O, Sch name = JB7
+#NET "JB<5>" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
+#NET "JB<6>" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
+#NET "JB<7>" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
+#
+#NET "JC<0>" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
+#NET "JC<1>" LOC = "J16"; # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL, Sch name = JC2
+#NET "JC<2>" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
+#NET "JC<3>" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
+#NET "JC<4>" LOC = "H15"; # Bank = 1, Pin name = IO_L17N_1, Type = I/O, Sch name = JC7
+#NET "JC<5>" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
+#NET "JC<6>" LOC = "G16"; # Bank = 1, Pin name = IO_L18N_1, Type = I/O, Sch name = JC9
+#NET "JC<7>" LOC = "J12"; # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL, Sch name = JC10
+#
+#NET "io_sda" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
+#NET "io_scl" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
+#
+#NET "jc<3>" CLOCK_DEDICATED_ROUTE = FALSE;
+#NET "ja<1>" CLOCK_DEDICATED_ROUTE = FALSE;
+#NET "ja<2>" CLOCK_DEDICATED_ROUTE = FALSE;
+#NET "i_clock" CLOCK_DEDICATED_ROUTE = FALSE;
+#PIN "DCM_SP_inst_vga.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
diff --git a/camera1/top.vhd b/camera1/top.vhd
new file mode 100755
index 0000000..ff113d6
--- /dev/null
+++ b/camera1/top.vhd
@@ -0,0 +1,348 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+--use IEEE.NUMERIC_STD.ALL;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity top is
+port (
+i_clock : in std_logic;
+--i_reset : in std_logic;
+o_r : out std_logic_vector(3 downto 1);
+o_g : out std_logic_vector(3 downto 1);
+o_b : out std_logic_vector(3 downto 2);
+o_h : out std_logic;
+o_v : out std_logic;
+btn : in std_logic_vector(3 downto 0);
+i_sw : in std_logic_vector(7 downto 0);
+cam_xclk : out std_logic;
+cam_pclk : in std_logic;
+cam_sioc : inout std_logic;
+cam_siod : inout std_logic;
+cam_data : in std_logic_vector(7 downto 0);
+cam_vsync : in std_logic;
+cam_href : in std_logic;
+cam_rst : out std_logic
+);
+end top;
+
+architecture Behavioral of top is
+
+component Address_Generator is
+Port (
+CLK25,enable : in STD_LOGIC;
+rez_160x120 : IN std_logic;
+rez_320x240 : IN std_logic;
+vsync : in STD_LOGIC;
+address : out STD_LOGIC_VECTOR (14 downto 0)
+);
+end component Address_Generator;
+
+component RGB is
+Port (
+Din : in STD_LOGIC_VECTOR (7 downto 0);
+Nblank : in STD_LOGIC;
+R : out STD_LOGIC_VECTOR (3 downto 1);
+G : out STD_LOGIC_VECTOR (3 downto 1);
+B : out STD_LOGIC_VECTOR (3 downto 2)
+);
+end component RGB;
+
+component VGA is
+Port (
+CLK25 : in STD_LOGIC;
+rez_160x120 : IN std_logic;
+rez_320x240 : IN std_logic;
+Hsync,Vsync : out STD_LOGIC;
+activeArea : out STD_LOGIC;
+video : out std_logic
+);
+end component VGA;
+
+--component debounce is
+--Port (
+--clk : in STD_LOGIC;
+--i : in STD_LOGIC;
+--o : out STD_LOGIC
+--);
+--end component debounce;
+
+component ov7670_capture is
+Port (
+pclk : in STD_LOGIC;
+rez_160x120 : IN std_logic;
+rez_320x240 : IN std_logic;
+vsync : in STD_LOGIC;
+href : in STD_LOGIC;
+d : in STD_LOGIC_VECTOR (7 downto 0);
+addr : out STD_LOGIC_VECTOR (14 downto 0);
+dout : out STD_LOGIC_VECTOR (7 downto 0);
+we : out STD_LOGIC
+);
+end component ov7670_capture;
+
+component ov7670_controller is
+Port (
+clk : in STD_LOGIC;
+resend :in STD_LOGIC;
+config_finished : out std_logic;
+sioc : out STD_LOGIC;
+siod : inout STD_LOGIC;
+reset : out STD_LOGIC;
+pwdn : out STD_LOGIC;
+xclk : out STD_LOGIC
+);
+end component ov7670_controller;
+
+--component i3c2 is
+--Generic(
+--clk_divide : STD_LOGIC_VECTOR (7 downto 0)
+--);
+--Port (
+--clk : in STD_LOGIC;
+--inst_address : out STD_LOGIC_VECTOR (9 downto 0);
+--inst_data : in STD_LOGIC_VECTOR (8 downto 0);
+--i2c_scl : out STD_LOGIC;
+--i2c_sda : inout STD_LOGIC;
+--inputs : in STD_LOGIC_VECTOR (15 downto 0);
+--outputs : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
+--reg_addr : out STD_LOGIC_VECTOR (4 downto 0);
+--reg_data : out STD_LOGIC_VECTOR (7 downto 0);
+--reg_write : out STD_LOGIC;
+--error : out STD_LOGIC
+--);
+--end component i3c2;
+
+signal ag_clk25,ag_enable,ag_rez1,ag_rez2,ag_vsync : std_logic;
+signal ag_address : std_logic_vector(14 downto 0);
+signal rgb_nblank : std_logic;
+signal rgb_din : STD_LOGIC_VECTOR (7 downto 0);
+signal rgb_r : std_logic_vector(3 downto 1);
+signal rgb_g : std_logic_vector(3 downto 1);
+signal rgb_b : std_logic_vector(3 downto 2);
+signal vga_clk25,vga_rez1,vga_rez2,vga_hs,vga_vs,vga_aa,vga_video : std_logic;
+--signal d_clk,d_i,d_o : std_logic;
+signal ov1_pclk,ov1_rez1,ov1_rez2,ov1_vs,ov1_hr,ov1_we : std_logic;
+signal ov1_d : STD_LOGIC_VECTOR (7 downto 0);
+signal ov1_addr : STD_LOGIC_VECTOR (14 downto 0);
+signal ov1_dout : STD_LOGIC_VECTOR (7 downto 0);
+signal ovc2_clk,ovc2_resend,ovc2_cf,ovc2_sioc,ovc2_siod,ovc2_reset,ovc2_pwdn,ovc2_xclk : std_logic;
+--signal ic_clk,ic_scl,ic_sda,ic_regwrite,ic_error : std_logic;
+--signal ic_addr : STD_LOGIC_VECTOR (9 downto 0);
+--signal ic_data : STD_LOGIC_VECTOR (8 downto 0);
+--signal ic_regaddr : STD_LOGIC_VECTOR (4 downto 0);
+--signal ic_regdata : STD_LOGIC_VECTOR (7 downto 0);
+--signal ic_ip : STD_LOGIC_VECTOR (15 downto 0);
+--signal ic_op : STD_LOGIC_VECTOR (15 downto 0);
+
+signal clockbuf,clockbuf1,clockbuf2 : std_logic;
+signal clock25 : std_logic;
+signal reset : std_logic;
+signal clock : std_logic;
+
+component bram_vga is
+generic (
+constant WIDTH : integer := 0;
+constant DEPTH: integer := 0
+);
+port (
+clka : in std_logic;
+clkb : in std_logic;
+wea : in std_logic;
+addra : in std_logic_vector(DEPTH-1 downto 0);
+addrb : in std_logic_vector(DEPTH-1 downto 0);
+dina : in std_logic_vector(WIDTH-1 downto 0);
+douta : out std_logic_vector(WIDTH-1 downto 0)
+);
+end component bram_vga;
+
+signal bram_wea,bram_clka,bram_ena,bram_clkb : std_logic;
+signal bram_addra : std_logic_vector(14 downto 0);
+signal bram_addrb : std_logic_vector(14 downto 0);
+signal bram_dina : std_logic_vector(7 downto 0);
+signal bram_doutb : std_logic_vector(7 downto 0);
+
+begin
+
+clock <= i_clock;
+--reset <= i_reset;
+reset <= btn(0);
+cam_rst <= not btn(1);
+vga_clk25 <= clock25;
+ag_clk25 <= clock25;
+--ovc2_clk <= clockbuf when ovc2_cf = '0' else '0';
+ovc2_clk <= clockbuf;
+vga_rez1 <= i_sw(1);
+vga_rez2 <= i_sw(2);
+ag_rez1 <= i_sw(1);
+ag_rez2 <= i_sw(2);
+ov1_rez1 <= i_sw(1);
+ov1_rez2 <= i_sw(2);
+o_h <= vga_hs;
+o_v <= vga_vs;
+ov1_pclk <= cam_pclk;
+cam_sioc <= ovc2_sioc;
+--cam_sioc <= 'Z';
+cam_siod <= ovc2_siod;
+--cam_siod <= 'Z';
+ov1_d <= cam_data;
+ov1_vs <= cam_vsync;
+ov1_hr <= cam_href;
+ag_enable <= vga_aa;
+rgb_nblank <= vga_aa;
+ag_vsync <= vga_vs;
+cam_xclk <= ovc2_xclk;
+
+o_r <= rgb_r;
+o_g <= rgb_g;
+o_b <= rgb_b;
+
+clk25 : DCM
+generic map (
+CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
+CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32
+CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+CLKIN_PERIOD => 20.0, -- Specify period of input clock
+CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
+CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
+DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
+DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
+DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
+DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+FACTORY_JF => X"C080", -- FACTORY JF Values
+PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
+SIM_MODE => "SAFE", -- Simulation: "SAFE" vs "FAST", see "Synthesis and Simulation Design Guide" for details
+STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+)
+port map (
+CLK0 => clockbuf1, -- 0 degree DCM CLK ouptput
+CLK180 => open, -- 180 degree DCM CLK output
+CLK270 => open, -- 270 degree DCM CLK output
+CLK2X => open, -- 2X DCM CLK output
+CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+CLK90 => open, -- 90 degree DCM CLK output
+CLKDV => clock25, -- Divided DCM CLK out (CLKDV_DIVIDE)
+CLKFX => open, -- DCM CLK synthesis out (M/D)
+CLKFX180 => open, -- 180 degree CLK synthesis out
+LOCKED => open, -- DCM LOCK status output
+PSDONE => open, -- Dynamic phase adjust done output
+STATUS => open, -- 8-bit DCM status bits output
+CLKFB => clockbuf2, -- DCM clock feedback
+CLKIN => clockbuf, -- Clock input (from IBUFG, BUFG or DCM)
+PSCLK => '0', -- Dynamic phase adjust clock input
+PSEN => '0', -- Dynamic phase adjust enable input
+PSINCDEC => open, -- Dynamic phase adjust increment/decrement
+RST => reset -- DCM asynchronous reset input
+);
+ibuf_clk25 : ibufg
+port map (o => clockbuf, i => clock);
+buf_clk25 : bufg
+port map (o => clockbuf2, i => clockbuf1);
+
+a1 : Address_Generator
+Port map (
+CLK25 => ag_clk25,
+enable => ag_enable,
+rez_160x120 => ag_rez1,
+rez_320x240 => ag_rez2,
+vsync => ag_vsync,
+address => ag_address
+);
+
+b1 : RGB
+Port map (
+Din => rgb_din,
+Nblank => rgb_nblank,
+R => rgb_r,
+G => rgb_g,
+B => rgb_b
+);
+
+c1 : VGA
+Port map (
+CLK25 => vga_clk25,
+rez_160x120 => vga_rez1,
+rez_320x240 => vga_rez2,
+Hsync => vga_hs,
+Vsync => vga_vs,
+activeArea => vga_aa,
+video => vga_video
+);
+
+--d1 : debounce
+--Port map (
+--clk => d_clk,
+--i => d_i,
+--o => d_o
+--);
+
+e1 : ov7670_capture
+Port map (
+pclk => ov1_pclk,
+rez_160x120 => ov1_rez1,
+rez_320x240 => ov1_rez2,
+vsync => ov1_vs,
+href => ov1_hr,
+d => ov1_d,
+addr => ov1_addr,
+dout => ov1_dout,
+we => ov1_we
+);
+
+f1 : ov7670_controller
+Port map (
+clk => ovc2_clk,
+resend => ovc2_resend,
+config_finished => ovc2_cf,
+sioc => ovc2_sioc,
+siod => ovc2_siod,
+reset => ovc2_reset,
+pwdn => ovc2_pwdn,
+xclk => ovc2_xclk
+);
+
+--g1 : i3c2
+--Generic map (
+--clk_divide => "10000000"
+--)
+--Port map (
+--clk => ic_clk,
+--inst_address => ic_addr,
+--inst_data => ic_data,
+--i2c_scl => ic_scl,
+--i2c_sda => ic_sda,
+--inputs => ic_ip,
+--outputs => ic_op,
+--reg_addr => ic_regaddr,
+--reg_data => ic_regdata,
+--reg_write => ic_regwrite,
+--error => ic_error
+--);
+
+ram : bram_vga
+generic map (
+WIDTH => 8,
+DEPTH => 15
+)
+port map (
+clka => bram_clka,
+clkb => bram_clkb,
+wea => bram_wea,
+addra => bram_addra,
+addrb => bram_addrb,
+dina => bram_dina,
+douta => bram_doutb
+);
+
+rgb_din <= bram_doutb;
+bram_addrb <= ag_address;
+bram_clkb <= clock25;
+
+bram_addra <= ov1_addr;
+bram_clka <= ov1_pclk;
+bram_dina <= ov1_dout;
+bram_wea <= ov1_we;
+bram_ena <= '1';
+
+end Behavioral;
diff --git a/camera3/bram_vga.vhd b/camera3/bram_vga.vhd
new file mode 100755
index 0000000..9e305fd
--- /dev/null
+++ b/camera3/bram_vga.vhd
@@ -0,0 +1,71 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:03:44 07/10/2022
+-- Design Name:
+-- Module Name: bram_vga - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+--
+-- Dual-Port RAM with Synchronous Read (Read Through)
+-- using More than One Clock
+-- UG627 PDF p. 153
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity bram_vga is
+generic (
+constant WIDTH : integer := 0;
+constant DEPTH : integer := 0
+);
+port (
+clka : in std_logic;
+clkb : in std_logic;
+wea : in std_logic;
+addra : in std_logic_vector(DEPTH-1 downto 0);
+addrb : in std_logic_vector(DEPTH-1 downto 0);
+dina : in std_logic_vector(WIDTH-1 downto 0);
+douta : out std_logic_vector(WIDTH-1 downto 0)
+);
+end entity bram_vga;
+
+architecture simulation of bram_vga is
+ type ram_type is array (0 to 2**DEPTH-1) of std_logic_vector(WIDTH-1 downto 0);
+ signal RAM : ram_type := (others => (others => '0'));
+ signal read_addra : std_logic_vector(DEPTH-1 downto 0);
+ signal read_addrb : std_logic_vector(DEPTH-1 downto 0);
+begin
+ pa : process (clka)
+ begin
+ if (rising_edge(clka)) then
+ if (wea = '1') then
+ RAM(conv_integer(addra)) <= dina;
+ end if;
+ read_addra <= addra;
+ end if;
+ end process pa;
+
+ pb : process (clkb)
+ begin
+ if (rising_edge(clkb)) then
+ read_addrb <= addrb;
+ end if;
+ end process pb;
+ douta <= RAM(conv_integer(addrb));
+
+end architecture simulation;
diff --git a/camera3/camera.vhd b/camera3/camera.vhd
new file mode 100755
index 0000000..3187533
--- /dev/null
+++ b/camera3/camera.vhd
@@ -0,0 +1,271 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:56:40 07/10/2022
+-- Design Name:
+-- Module Name: camera - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+-- XXX ov7670 camera emulator vga 640x480 30fps
+-- XXX based on datasheet VGA Frame Timing Figure 6 p. 7
+entity camera is
+generic (
+constant CLOCK_PERIOD : integer := 42; -- 21/42/100 ns - 10/24/48 MHZ - Min/Typ/Max Unit
+constant RAW_RGB : integer := 0; -- 0 - RAW / 1 - RGB
+constant ZERO : integer := 0
+);
+port (
+io_scl : inout std_logic;
+io_sda : inout std_logic;
+o_vs : out std_logic;
+o_hs : out std_logic;
+o_pclk : out std_logic;
+i_xclk : in std_logic;
+o_d : out std_logic_vector(7 downto 0);
+i_rst : in std_logic;
+i_pwdn : in std_logic
+);
+end camera;
+
+architecture Behavioral of camera is
+ constant CLOCK_PERIOD1 : integer := 21;
+ constant CLOCK_PERIOD2 : integer := 42;
+ constant CLOCK_PERIOD3 : integer := 100;
+ -- 1 or 2 pclk for tp
+ constant tp : integer := 2**RAW_RGB;
+ -- tline = 784tp = 640tp + 144tp
+ constant HREF1 : integer := 640;
+ constant CHREF1 : integer := HREF1 * tp; -- HREF 1 pulse time
+ constant HREF0 : integer := 144;
+ constant CHREF0 : integer := HREF0 * tp; -- HREF 0 pulse time
+ constant tline : integer := CHREF1 + CHREF0;
+ -- VSYNC pulse have 510tline
+ constant CVSYNC1 : integer := 3;
+ constant VSYNC1 : integer := CVSYNC1 * tline;
+ constant CVSYNC2 : integer := 17;
+ constant VSYNC2 : integer := CVSYNC2 * tline;
+ constant CVSYNC3 : integer := 480;
+ constant VSYNC3 : integer := CVSYNC3 * tline;
+ constant CVSYNC4 : integer := 10;
+ constant VSYNC4 : integer := CVSYNC4 * tline;
+ constant CVSYNCALL : integer := CVSYNC1 + CVSYNC2 + CVSYNC3 + CVSYNC4; -- 510tline
+ signal href_time : std_logic;
+ signal pixel_time : std_logic;
+begin
+
+ -- check the clock period
+ p0 : process (i_rst) is
+ begin
+ if (i_rst = '0') then
+ assert (CLOCK_PERIOD = CLOCK_PERIOD1 or CLOCK_PERIOD = CLOCK_PERIOD2 or CLOCK_PERIOD = CLOCK_PERIOD3)
+ report "-- CLOCK_PERIOD must have " & integer'image(CLOCK_PERIOD1) & "," & integer'image(CLOCK_PERIOD2) & "," & integer'image(CLOCK_PERIOD3) & " --"
+ severity failure;
+ end if;
+ end process p0;
+
+ -- generate sync pulse
+ -- p.14 15 COM10 0x00 RW [2] - VSYNC changes on falling edge PCLK
+ p1 : process (i_xclk,i_rst) is
+ variable count : integer range 0 to CVSYNCALL*tline - 1;
+ variable vvsync : std_logic;
+ type states is (svs1,svs2,svs3,svs4);
+ variable state : states;
+ begin
+ if (i_rst = '0') then
+ count := 0;
+ vvsync := '0';
+ state := svs1;
+ href_time <= '0';
+ elsif (falling_edge(i_xclk)) then
+ case (state) is
+ when svs1 =>
+ vvsync := '1';
+ href_time <= '0';
+ if (count = VSYNC1) then
+ state := svs2;
+ count := 0;
+ else
+ state := svs1;
+ count := count + 1;
+ end if;
+ when svs2 =>
+ vvsync := '0';
+ href_time <= '0';
+ if (count = VSYNC2) then
+ state := svs3;
+ count := 0;
+ else
+ state := svs2;
+ count := count + 1;
+ end if;
+ when svs3 =>
+ vvsync := '0';
+ href_time <= '1';
+ if (count = VSYNC3) then
+ state := svs4;
+ count := 0;
+ else
+ state := svs3;
+ count := count + 1;
+ end if;
+ when svs4 =>
+ vvsync := '0';
+ href_time <= '0';
+ if (count = VSYNC4) then
+ state := svs1;
+ count := 0;
+ else
+ state := svs4;
+ count := count + 1;
+ end if;
+ end case;
+ o_vs <= vvsync;
+ end if;
+ end process p1;
+
+ -- generate href pulse
+ -- on falling edge
+ p2 : process (i_rst,i_xclk,href_time) is
+ variable count : integer range 0 to VSYNC3 - 1;
+ variable counth1 : integer range 0 to CHREF1 - 1;
+ variable counth0 : integer range 0 to CHREF0 - 1;
+ type states is (swait4vsync,shref1,shref0);
+ variable state : states;
+ variable vhref : std_logic;
+ begin
+ if (i_rst = '0') then
+ count := 0;
+ counth1 := 0;
+ counth0 := 0;
+ state := swait4vsync;
+ vhref := '0';
+ elsif (falling_edge(i_xclk)) then
+ case (state) is
+ when swait4vsync =>
+ pixel_time <= '0';
+ if (href_time = '1') then
+ if (count = VSYNC3) then
+ state := swait4vsync;
+ count := 0;
+ else
+ state := shref1;
+ pixel_time <= '1';
+ count := count + 1;
+ end if;
+ else
+ state := swait4vsync;
+ end if;
+ when shref1 =>
+ pixel_time <= '1';
+ vhref := '1';
+ if (counth1 = CHREF1 - 1) then
+ pixel_time <= '0';
+ state := shref0;
+ counth1 := 0;
+ else
+ state := shref1;
+ counth1 := counth1 + 1;
+ end if;
+ when shref0 =>
+ pixel_time <= '0';
+ vhref := '0';
+ if (counth0 = CHREF0 - 1) then
+ state := swait4vsync;
+ counth0 := 0;
+ else
+ state := shref0;
+ counth0 := counth0 + 1;
+ end if;
+ end case;
+ o_hs <= vhref;
+ end if;
+ end process p2;
+
+ p3 : process (i_rst,i_xclk,pixel_time) is
+ constant CDATALENGTH : integer := 5;
+ constant CNUMPIXELS : integer := HREF1 - CDATALENGTH*2;
+ variable count : integer range 0 to CDATALENGTH - 1;
+ type tdata is array(0 to CDATALENGTH - 1) of std_logic_vector(7 downto 0);
+ constant startdata : tdata := (x"FF",x"EE",x"DD",x"CC",x"BB");
+ constant enddata : tdata := (x"AA",x"BB",x"CC",x"DD",x"EE");
+ constant odddata : std_logic_vector(7 downto 0) := x"AA";
+ constant evendata : std_logic_vector(7 downto 0) := x"55";
+ type states is (s1,s2,s3);
+ variable state : states;
+ variable vd : std_logic_vector(7 downto 0);
+ begin
+ if (i_rst = '0') then
+ vd := (others => '0');
+ state := s1;
+ count := 0;
+ elsif (falling_edge(i_xclk)) then
+ if (pixel_time = '1') then
+ case (state) is
+ when s1 =>
+ vd := startdata(count);
+ if (count = CDATALENGTH - 1) then
+ count := 0;
+ state := s2;
+ else
+ count := count + 1;
+ state := s1;
+ end if;
+ when s2 =>
+ if (count = CNUMPIXELS - 1) then
+ state := s3;
+ count := 0;
+ else
+ state := s2;
+ if (count mod 2 = 0) then
+ vd := odddata;
+ count := count + 1;
+ elsif (count mod 2 = 1) then
+ vd := evendata;
+ count := count + 1;
+ else
+ vd := (others => 'U');
+ end if;
+ end if;
+ when s3 =>
+ vd := enddata(count);
+ if (count = CDATALENGTH - 1) then
+ count := 0;
+ state := s1;
+ else
+ count := count + 1;
+ state := s3;
+ end if;
+ end case;
+ else
+ vd := (others => '0');
+ end if;
+ o_d <= vd;
+ end if;
+ end process p3;
+
+o_pclk <= i_xclk;
+
+end Behavioral;
diff --git a/camera3/camera3.xise b/camera3/camera3.xise
new file mode 100755
index 0000000..7433298
--- /dev/null
+++ b/camera3/camera3.xise
@@ -0,0 +1,372 @@
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diff --git a/camera3/camera_qqvga.vhd b/camera3/camera_qqvga.vhd
new file mode 100755
index 0000000..3ca298f
--- /dev/null
+++ b/camera3/camera_qqvga.vhd
@@ -0,0 +1,274 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:56:40 07/10/2022
+-- Design Name:
+-- Module Name: camera - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+-- XXX ov7670 camera emulator vga 640x480 30fps
+-- XXX based on datasheet VGA Frame Timing Figure 6 p. 7
+entity camera_qqvga is
+generic (
+constant CLOCK_PERIOD : integer := 42; -- 21/42/100 ns - 10/24/48 MHZ - Min/Typ/Max Unit
+constant RAW_RGB : integer := 0; -- 0 - RAW / 1 - RGB
+constant ZERO : integer := 0
+);
+port (
+camera_io_scl : inout std_logic;
+camera_io_sda : inout std_logic;
+camera_o_vs : out std_logic;
+camera_o_hs : out std_logic;
+camera_o_pclk : out std_logic;
+camera_i_xclk : in std_logic;
+camera_o_d : out std_logic_vector(7 downto 0);
+camera_i_rst : in std_logic;
+camera_i_pwdn : in std_logic
+);
+end camera_qqvga;
+
+architecture Behavioral of camera_qqvga is
+ constant CLOCK_PERIOD1 : integer := 21;
+ constant CLOCK_PERIOD2 : integer := 42;
+ constant CLOCK_PERIOD3 : integer := 100;
+ -- 1 or 2 pclk for tp
+ constant tp : integer := 2**RAW_RGB;
+ -- tline = 784tp = 640tp + 144tp -- for VGA
+ -- tline = (href1+href0)*tp
+ constant HREF1 : real := 320.0;
+ constant CHREF1 : real := HREF1 * real(tp); -- HREF 1 pulse time
+ constant HREF0 : real := 1247.0;
+ constant CHREF0 : real := HREF0 * real(tp); -- HREF 0 pulse time
+ constant tline : real := CHREF1 + CHREF0;
+ -- VSYNC pulse have (510/4)*tline
+ constant CVSYNC1 : real := 0.7505;
+ constant VSYNC1 : real := CVSYNC1 * real(tline);
+ constant CVSYNC2 : real := 5.0560; -- 5.0565
+ constant VSYNC2 : real := CVSYNC2 * real(tline);
+ constant CVSYNC3 : real := 120.0000;
+ constant VSYNC3 : real := CVSYNC3 * real(tline);
+ constant CVSYNC4 : real := 1.7775; --1.8025
+ constant VSYNC4 : real := CVSYNC4 * real(tline);
+ constant CVSYNCALL : real := CVSYNC1 + CVSYNC2 + CVSYNC3 + CVSYNC4; -- 510tline
+ signal href_time : std_logic;
+ signal pixel_time : std_logic;
+
+
+ signal a,b,c,d,e,f : std_logic;
+
+begin
+
+ -- check the clock period
+ p0 : process (camera_i_rst) is
+ begin
+ if (camera_i_rst = '0') then
+ assert (CLOCK_PERIOD = CLOCK_PERIOD1 or CLOCK_PERIOD = CLOCK_PERIOD2 or CLOCK_PERIOD = CLOCK_PERIOD3)
+ report "-- CLOCK_PERIOD must have " & integer'image(CLOCK_PERIOD1) & "," & integer'image(CLOCK_PERIOD2) & "," & integer'image(CLOCK_PERIOD3) & " --"
+ severity warning;
+ end if;
+ end process p0;
+
+ -- generate sync pulse
+ -- p.14 15 COM10 0x00 RW [2] - VSYNC changes on falling edge PCLK
+ p1 : process (camera_i_xclk,camera_i_rst) is
+ variable count : integer range 0 to integer(CVSYNCALL)*integer(tline) - 1;
+ variable vvsync : std_logic;
+ type states is (svs1,svs2,svs3,svs4);
+ variable state : states;
+ begin
+ if (camera_i_rst = '0') then
+ count := 0;
+ vvsync := '1';
+ state := svs1;
+ href_time <= '0';
+ elsif (falling_edge(camera_i_xclk)) then
+ case (state) is
+ when svs1 =>
+ vvsync := '0';
+ href_time <= '0';
+ if (count = integer(VSYNC1) - 1) then
+ state := svs2;
+ count := 0;
+ else
+ state := svs1;
+ count := count + 1;
+ end if;
+ when svs2 =>
+ vvsync := '1';
+ href_time <= '0';
+ if (count = integer(VSYNC2) - 1) then
+ state := svs3;
+ count := 0;
+ else
+ state := svs2;
+ count := count + 1;
+ end if;
+ when svs3 =>
+ vvsync := '1';
+ href_time <= '1';
+ if (count = integer(VSYNC3) - 1) then
+ state := svs4;
+ count := 0;
+ else
+ state := svs3;
+ count := count + 1;
+ end if;
+ when svs4 =>
+ vvsync := '1';
+ href_time <= '0';
+ if (count = integer(VSYNC4) - 1) then
+ state := svs1;
+ count := 0;
+ else
+ state := svs4;
+ count := count + 1;
+ end if;
+ end case;
+ camera_o_vs <= not vvsync;
+ end if;
+ end process p1;
+
+ -- generate href pulse
+ -- on falling edge
+ p2 : process (camera_i_rst,camera_i_xclk,href_time) is
+ variable count : integer range 0 to integer(VSYNC3) - 1;
+ variable counth1 : integer range 0 to integer(CHREF1) - 1;
+ variable counth0 : integer range 0 to integer(CHREF0) - 1;
+ type states is (swait4vsync,shref1,shref0);
+ variable state : states;
+ variable vhref : std_logic;
+ begin
+ if (camera_i_rst = '0') then
+ count := 0;
+ counth1 := 0;
+ counth0 := 0;
+ state := swait4vsync;
+ vhref := '0';
+ elsif (falling_edge(camera_i_xclk)) then
+ case (state) is
+ when swait4vsync =>
+ if (href_time = '1') then
+ state := shref1;
+ pixel_time <= '1';
+ else
+ state := swait4vsync;
+ pixel_time <= '0';
+ end if;
+ when shref1 =>
+ pixel_time <= '1';
+ vhref := '1';
+ if (counth1 = integer(CHREF1) - 1) then
+ pixel_time <= '0';
+ state := shref0;
+ counth1 := 0;
+ else
+ state := shref1;
+ counth1 := counth1 + 1;
+ end if;
+ when shref0 =>
+ pixel_time <= '0';
+ vhref := '0';
+ if (counth0 = integer(CHREF0) - 1) then
+ state := swait4vsync;
+ counth0 := 0;
+ else
+ state := shref0;
+ counth0 := counth0 + 1;
+ end if;
+ end case;
+ camera_o_hs <= vhref;
+ end if;
+ end process p2;
+
+ p3 : process (camera_i_rst,camera_i_xclk,pixel_time) is
+ constant CDATALENGTH : integer := 5;
+ constant CNUMPIXELS : integer := integer(HREF1) - CDATALENGTH*2;
+ variable count : integer range 0 to CDATALENGTH - 1;
+ type tdata is array(0 to CDATALENGTH - 1) of std_logic_vector(7 downto 0);
+-- constant startdata : tdata := (x"FF",x"FF",x"FF",x"FF",x"FF");
+-- constant enddata : tdata := (x"FF",x"FF",x"FF",x"FF",x"FF");
+-- constant odddata : std_logic_vector(7 downto 0) := x"FF";
+-- constant evendata : std_logic_vector(7 downto 0) := x"FF";
+ constant startdata : tdata := (x"FF",x"EE",x"DD",x"CC",x"BB");
+ constant enddata : tdata := (x"BB",x"CC",x"DD",x"EE",x"FF");
+ constant odddata : std_logic_vector(7 downto 0) := x"55";
+ constant evendata : std_logic_vector(7 downto 0) := x"AA";
+ type states is (s1,s2,s3);
+ variable state : states;
+ variable vd : std_logic_vector(7 downto 0);
+ begin
+ if (camera_i_rst = '0') then
+ vd := (others => '0');
+ state := s1;
+ count := 0;
+ elsif (falling_edge(camera_i_xclk)) then
+ if (pixel_time = '1') then
+ case (state) is
+ when s1 =>
+ vd := startdata(count);
+ if (count = CDATALENGTH - 1) then
+ count := 0;
+ state := s2;
+ else
+ count := count + 1;
+ state := s1;
+ end if;
+ when s2 =>
+ if (count = CNUMPIXELS - 1) then
+ state := s3;
+ count := 0;
+ else
+ state := s2;
+ if (count mod 2 = 0) then
+ vd := odddata;
+ count := count + 1;
+ elsif (count mod 2 = 1) then
+ vd := evendata;
+ count := count + 1;
+ else
+ vd := (others => 'U');
+ end if;
+ end if;
+ when s3 =>
+ vd := enddata(count);
+ if (count = CDATALENGTH - 1) then
+ count := 0;
+ state := s1;
+ else
+ count := count + 1;
+ state := s3;
+ end if;
+ end case;
+ else
+ vd := (others => '0');
+ end if;
+ camera_o_d <= vd;
+ end if;
+ end process p3;
+
+camera_o_pclk <= camera_i_xclk;
+
+end Behavioral;
diff --git a/camera3/tb_camera.vhd b/camera3/tb_camera.vhd
new file mode 100755
index 0000000..5f3c580
--- /dev/null
+++ b/camera3/tb_camera.vhd
@@ -0,0 +1,120 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:18:44 07/10/2022
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/camera1/tb_camera.vhd
+-- Project Name: camera1
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: camera
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_camera IS
+END tb_camera;
+
+ARCHITECTURE behavior OF tb_camera IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT camera
+PORT(
+io_scl : INOUT std_logic;
+io_sda : INOUT std_logic;
+o_vs : OUT std_logic;
+o_hs : OUT std_logic;
+o_pclk : OUT std_logic;
+i_xclk : IN std_logic;
+o_d : OUT std_logic_vector(7 downto 0);
+i_rst : IN std_logic;
+i_pwdn : IN std_logic
+);
+END COMPONENT;
+
+
+--Inputs
+signal i_xclk : std_logic := '0';
+signal i_rst : std_logic := '0';
+signal i_pwdn : std_logic := '0';
+
+--BiDirs
+signal io_scl : std_logic;
+signal io_sda : std_logic;
+
+--Outputs
+signal o_vs : std_logic;
+signal o_hs : std_logic;
+signal o_pclk : std_logic;
+signal o_d : std_logic_vector(7 downto 0);
+
+-- Clock period definitions
+--constant o_pclk_period : time := 10 ns;
+constant i_xclk_period : time := 42 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: camera PORT MAP (
+io_scl => io_scl,
+io_sda => io_sda,
+o_vs => o_vs,
+o_hs => o_hs,
+o_pclk => o_pclk,
+i_xclk => i_xclk,
+o_d => o_d,
+i_rst => i_rst,
+i_pwdn => i_pwdn
+);
+
+---- Clock process definitions
+--o_pclk_process : process
+--begin
+--o_pclk <= '0';
+--wait for o_pclk_period/2;
+--o_pclk <= '1';
+--wait for o_pclk_period/2;
+--end process;
+
+i_xclk_process : process
+begin
+i_xclk <= '0';
+wait for i_xclk_period/2;
+i_xclk <= '1';
+wait for i_xclk_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+i_rst <= '0';
+wait for 100 ns;
+i_rst <= '1';
+wait for i_xclk_period*10;
+-- insert stimulus here
+wait;
+end process;
+
+END;
diff --git a/camera3/tb_camera_qqvga.vhd b/camera3/tb_camera_qqvga.vhd
new file mode 100755
index 0000000..24cfc39
--- /dev/null
+++ b/camera3/tb_camera_qqvga.vhd
@@ -0,0 +1,117 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:18:44 07/10/2022
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/camera1/tb_camera.vhd
+-- Project Name: camera1
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: camera
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_camera_qqvga IS
+END tb_camera_qqvga;
+
+ARCHITECTURE behavior OF tb_camera_qqvga IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT camera_qqvga is
+generic (
+constant CLOCK_PERIOD : integer := 42; -- 21/42/100 ns - 10/24/48 MHZ - Min/Typ/Max Unit
+constant RAW_RGB : integer := 0; -- 0 - RAW / 1 - RGB
+constant ZERO : integer := 0
+);
+port (
+camera_io_scl : inout std_logic;
+camera_io_sda : inout std_logic;
+camera_o_vs : out std_logic;
+camera_o_hs : out std_logic;
+camera_o_pclk : out std_logic;
+camera_i_xclk : in std_logic;
+camera_o_d : out std_logic_vector(7 downto 0);
+camera_i_rst : in std_logic;
+camera_i_pwdn : in std_logic
+);
+END COMPONENT camera_qqvga;
+
+--Inputs
+signal camera_i_xclk : std_logic := '0';
+signal camera_i_rst : std_logic := '0';
+signal camera_i_pwdn : std_logic := '0';
+
+--BiDirs
+signal camera_io_scl : std_logic;
+signal camera_io_sda : std_logic;
+
+--Outputs
+signal camera_o_vs : std_logic;
+signal camera_o_hs : std_logic;
+signal camera_o_pclk : std_logic;
+signal camera_o_d : std_logic_vector(7 downto 0);
+
+-- Clock period definitions
+constant camera_i_xclk_period : time := 1000 ns; -- 1mhz
+--constant camera_i_xclk_period : time := 500 ns; -- 2mhz
+--constant camera_i_xclk_period : time := 125 ns; -- 8mhz
+--constant camera_i_xclk_period : time := 83.333 ns; -- 12mhz
+--constant camera_i_xclk_period : time := 62.5 ns; -- 16mhz
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: camera_qqvga PORT MAP (
+camera_io_scl => camera_io_scl,
+camera_io_sda => camera_io_sda,
+camera_o_vs => camera_o_vs,
+camera_o_hs => camera_o_hs,
+camera_o_pclk => camera_o_pclk,
+camera_i_xclk => camera_i_xclk,
+camera_o_d => camera_o_d,
+camera_i_rst => camera_i_rst,
+camera_i_pwdn => camera_i_pwdn
+);
+
+camera_i_xclk_process : process
+begin
+camera_i_xclk <= '0';
+wait for camera_i_xclk_period/2;
+camera_i_xclk <= '1';
+wait for camera_i_xclk_period/2;
+end process;
+
+-- Stimulus process
+stim_proc : process
+begin
+-- hold reset state for 100 ns.
+camera_i_rst <= '0';
+wait for 100 ns;
+camera_i_rst <= '1';
+wait for camera_i_xclk_period*10;
+-- insert stimulus here
+wait;
+end process;
+
+END;
diff --git a/camera3/tb_top.vhd b/camera3/tb_top.vhd
new file mode 100755
index 0000000..9fb1895
--- /dev/null
+++ b/camera3/tb_top.vhd
@@ -0,0 +1,107 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:33:49 06/23/2022
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/camera1/tb_top.vhd
+-- Project Name: camera1
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_top IS
+END tb_top;
+
+ARCHITECTURE behavior OF tb_top IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT top
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+i_sw : IN std_logic_vector(7 downto 0);
+o_r : OUT std_logic_vector(2 downto 0);
+o_g : OUT std_logic_vector(2 downto 0);
+o_b : OUT std_logic_vector(1 downto 0);
+o_h : OUT std_logic;
+o_v : OUT std_logic
+);
+END COMPONENT;
+
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+signal i_sw : std_logic_vector(7 downto 0) := (others => '1');
+
+--Outputs
+signal o_r : std_logic_vector(2 downto 0);
+signal o_g : std_logic_vector(2 downto 0);
+signal o_b : std_logic_vector(1 downto 0);
+signal o_h : std_logic;
+signal o_v : std_logic;
+
+-- Clock period definitions
+constant i_clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: top PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+i_sw => i_sw,
+o_r => o_r,
+o_g => o_g,
+o_b => o_b,
+o_h => o_h,
+o_v => o_v
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+i_reset <= '1';
+wait for 100 ns;
+i_reset <= '0';
+wait for i_clock_period*10;
+-- insert stimulus here
+
+wait;
+end process;
+
+END;
diff --git a/camera3/top.ucf b/camera3/top.ucf
new file mode 100755
index 0000000..d52fb14
--- /dev/null
+++ b/camera3/top.ucf
@@ -0,0 +1,22 @@
+NET "i_clock" LOC="B8";
+NET "i_reset" LOC="B18";
+NET "o_r<1>" LOC="R9";
+NET "o_r<2>" LOC="T8";
+NET "o_r<3>" LOC="R8";
+NET "o_g<1>" LOC="N8";
+NET "o_g<2>" LOC="P8";
+NET "o_g<3>" LOC="P6";
+NET "o_b<2>" LOC="U5";
+NET "o_b<3>" LOC="U4";
+NET "o_h" LOC="T4";
+NET "o_v" LOC="U3";
+NET "i_sw<0>" LOC = "G18";
+NET "i_sw<1>" LOC = "H18";
+NET "i_sw<2>" LOC = "K18";
+NET "i_sw<3>" LOC = "K17";
+NET "i_sw<4>" LOC = "L14";
+NET "i_sw<5>" LOC = "L13";
+NET "i_sw<6>" LOC = "N17";
+NET "i_sw<7>" LOC = "R17";
+
+#NET "i_clock" CLOCK_DEDICATED_ROUTE = FALSE;
diff --git a/camera3/top.vhd b/camera3/top.vhd
new file mode 100755
index 0000000..b37cd18
--- /dev/null
+++ b/camera3/top.vhd
@@ -0,0 +1,413 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:38:38 06/23/2022
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity top is
+port (
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_sw : in std_logic_vector(7 downto 0);
+o_r : out std_logic_vector(3 downto 1);
+o_g : out std_logic_vector(3 downto 1);
+o_b : out std_logic_vector(3 downto 2);
+o_h : out std_logic;
+o_v : out std_logic
+);
+end top;
+
+architecture Behavioral of top is
+
+signal h : std_logic;
+signal v : std_logic;
+signal display_flag : std_logic;
+signal clock : std_logic;
+signal clockbuf1a,clockbuf1b,clockbuf1,clkdv_vga : std_logic;
+signal clockbuf2a,clockbuf2b,clockbuf2,clkdv_cam : std_logic;
+
+component camera is
+generic (
+constant CLOCK_PERIOD : integer := 42; -- 21/42/100 ns - 10/24/48 MHZ - Min/Typ/Max Unit
+constant RAW_RGB : integer := 0; -- 0 - RAW / 1 - RGB
+constant ZERO : integer := 0
+);
+port (
+io_scl : inout std_logic;
+io_sda : inout std_logic;
+o_vs : out std_logic;
+o_hs : out std_logic;
+o_pclk : out std_logic;
+i_xclk : in std_logic;
+o_d : out std_logic_vector(7 downto 0);
+i_rst : in std_logic;
+i_pwdn : in std_logic
+);
+end component camera;
+signal camera_io_scl,camera_io_sda,camera_o_vs,camera_o_hs,camera_o_pclk,camera_i_xclk,camera_i_rst,camera_i_pwdn : std_logic;
+signal camera_o_d : std_logic_vector(7 downto 0);
+
+constant C_BRAM_VGA_WIDTH : integer := 8;
+constant C_BRAM_VGA_DEPTH : integer := 2;
+component bram_vga is
+generic (
+constant WIDTH : integer := C_BRAM_VGA_WIDTH;
+constant DEPTH : integer := C_BRAM_VGA_DEPTH
+);
+port (
+clka : in std_logic;
+clkb : in std_logic;
+wea : in std_logic;
+addra : in std_logic_vector(DEPTH-1 downto 0);
+addrb : in std_logic_vector(DEPTH-1 downto 0);
+dina : in std_logic_vector(WIDTH-1 downto 0);
+douta : out std_logic_vector(WIDTH-1 downto 0)
+);
+end component bram_vga;
+signal bram_vga_clka,bram_vga_clkb,bram_vga_wea : std_logic;
+signal bram_vga_addra,bram_vga_addrb : std_logic_vector(C_BRAM_VGA_DEPTH - 1 downto 0);
+signal bram_vga_dina,bram_vga_douta : std_logic_vector(C_BRAM_VGA_WIDTh - 1 downto 0);
+
+signal activeh : std_logic;
+
+begin
+
+clock <= i_clock;
+
+bram_vga_clka <= clkdv_cam;
+bram_vga_clkb <= clkdv_vga;
+bram_vga_wea <= camera_o_hs;
+bram_vga_dina <= camera_o_d;
+
+camera_i_rst <= not i_reset;
+camera_i_xclk <= clkdv_cam;
+o_h <= h;
+o_v <= v;
+
+--o_r(3) <= bram_vga_douta(7);
+--o_r(2) <= bram_vga_douta(6);
+--o_r(1) <= bram_vga_douta(5);
+--o_g(3) <= bram_vga_douta(4);
+--o_g(2) <= bram_vga_douta(3);
+--o_g(1) <= bram_vga_douta(2);
+--o_b(3) <= bram_vga_douta(1);
+--o_b(2) <= bram_vga_douta(0);
+
+o_r(3) <= bram_vga_douta(7) when display_flag = '1' else '0';
+o_r(2) <= bram_vga_douta(6) when display_flag = '1' else '0';
+o_r(1) <= bram_vga_douta(5) when display_flag = '1' else '0';
+o_g(3) <= bram_vga_douta(4) when display_flag = '1' else '0';
+o_g(2) <= bram_vga_douta(3) when display_flag = '1' else '0';
+o_g(1) <= bram_vga_douta(2) when display_flag = '1' else '0';
+o_b(3) <= bram_vga_douta(1) when display_flag = '1' else '0';
+o_b(2) <= bram_vga_douta(0) when display_flag = '1' else '0';
+
+pmemaddra : process (bram_vga_clka,i_reset) is
+ constant C_COUNT : integer := 2**C_BRAM_VGA_DEPTH;
+ variable count : integer range 0 to C_COUNT - 1;
+begin
+ if (i_reset = '1') then
+ count := 0;
+ elsif(rising_edge(bram_vga_clka)) then
+ if (camera_o_hs = '1') then
+ if (count = C_COUNT - 1) then
+ count := 0;
+ else
+ count := count + 1;
+ end if;
+ end if;
+ bram_vga_addra <= std_logic_vector(to_unsigned(count,C_BRAM_VGA_DEPTH));
+ end if;
+end process pmemaddra;
+
+pmemaddrb : process (bram_vga_clkb,i_reset) is
+ constant C_COUNT : integer := 2**C_BRAM_VGA_DEPTH;
+ variable count : integer range 0 to C_COUNT - 1;
+begin
+ if (i_reset = '1') then
+ count := 0;
+ elsif(rising_edge(bram_vga_clkb)) then
+ if (display_flag = '1') then
+ if (count = C_COUNT - 1) then
+ count := 0;
+ else
+ count := count + 1;
+ end if;
+ end if;
+ bram_vga_addrb <= std_logic_vector(to_unsigned(count,C_BRAM_VGA_DEPTH));
+ end if;
+end process pmemaddrb;
+
+p3 : process (clkdv_vga,i_reset,h) is
+ constant C_PW : integer := 95;
+ constant C_FP : integer := 16;
+ constant C_BP : integer := 48;
+ constant C_DISP : integer := 640;
+ variable pwh : integer range 0 to C_PW - 1 := 0;
+ variable fph : integer range 0 to C_FP - 1 := 0;
+ variable bph : integer range 0 to C_BP - 1 := 0;
+ variable disph : integer range 0 to C_DISP - 1 := 0;
+ type statesh is (idleh,state_pwh,state_fph,state_disph,state_bph);
+ variable stateh : statesh;
+begin
+ if (i_reset = '1') then
+ fph := 0;
+ bph := 0;
+ disph := 0;
+ stateh := idleh;
+ display_flag <= '0';
+ elsif (rising_edge(clkdv_vga)) then
+ case (stateh) is
+ when idleh =>
+ display_flag <= '0';
+ h <= '0';
+ if (activeh = '1') then
+ stateh := state_pwh;
+ else
+ stateh := idleh;
+ end if;
+ when state_pwh =>
+ display_flag <= '0';
+ h <= '0';
+ if (pwh = C_PW - 1) then
+ stateh := state_bph;
+ pwh := 0;
+ else
+ stateh := state_pwh;
+ pwh := pwh + 1;
+ end if;
+ when state_bph =>
+ display_flag <= '0';
+ h <= '1';
+ if (bph = C_BP - 1) then
+ stateh := state_disph;
+ bph := 0;
+ else
+ stateh := state_bph;
+ bph := bph + 1;
+ end if;
+ when state_disph =>
+ display_flag <= '1';
+ h <= '1';
+ if (disph = C_DISP - 1) then
+ stateh := state_fph;
+ disph := 0;
+ else
+ stateh := state_disph;
+ disph := disph + 1;
+ end if;
+ when state_fph =>
+ display_flag <= '0';
+ h <= '1';
+ if (fph = C_FP - 1) then
+ stateh := idleh;
+ fph := 0;
+ else
+ stateh := state_fph;
+ fph := fph + 1;
+ end if;
+ end case;
+ end if;
+end process p3;
+
+p4 : process (clkdv_vga,i_reset,v) is
+ constant C_PW : integer := 1600;
+ constant C_FP : integer := 8000;
+ constant C_BP : integer := 33*800;--23200;
+ constant C_DISP : integer := 384000;
+ variable pwv : integer range 0 to C_PW - 1 := 0;
+ variable fpv : integer range 0 to C_FP - 1 := 0;
+ variable bpv : integer range 0 to C_BP - 1 := 0;
+ variable dispv : integer range 0 to C_DISP - 1 := 0;
+ type statesv is (state_pwv,state_fpv,state_dispv,state_bpv);
+ variable statev : statesv;
+begin
+ if (i_reset = '1') then
+ pwv := 0;
+ fpv := 0;
+ bpv := 0;
+ dispv := 0;
+ statev := state_pwv;
+ activeh <= '0';
+ elsif (rising_edge(clkdv_vga)) then
+ case (statev) is
+ when state_pwv =>
+ activeh <= '0';
+ v <= '0';
+ if (pwv = C_PW - 1) then
+ statev := state_bpv;
+ pwv := 0;
+ else
+ statev := state_pwv;
+ pwv := pwv + 1;
+ end if;
+ when state_bpv =>
+ activeh <= '0';
+ v <= '1';
+ if (bpv = C_BP - 1) then
+ statev := state_dispv;
+ bpv := 0;
+ else
+ statev := state_bpv;
+ bpv := bpv + 1;
+ end if;
+ when state_dispv =>
+ activeh <= '1';
+ v <= '1';
+ if (dispv = C_DISP - 1) then
+ statev := state_fpv;
+ dispv := 0;
+ else
+ statev := state_dispv;
+ dispv := dispv + 1;
+ end if;
+ when state_fpv =>
+ activeh <= '0';
+ v <= '1';
+ if (fpv = C_FP - 1) then
+ statev := state_pwv;
+ fpv := 0;
+ else
+ statev := state_fpv;
+ fpv := fpv + 1;
+ end if;
+ end case;
+ end if;
+end process p4;
+
+dcm_vga : DCM
+generic map (
+CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
+CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32
+CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+CLKIN_PERIOD => 20.0, -- Specify period of input clock
+CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
+CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
+DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
+DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
+DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
+DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+FACTORY_JF => X"C080", -- FACTORY JF Values
+PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
+SIM_MODE => "SAFE", -- Simulation: "SAFE" vs "FAST", see "Synthesis and Simulation Design Guide" for details
+STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+)
+port map (
+CLK0 => clockbuf1a, -- 0 degree DCM CLK ouptput
+CLK180 => open, -- 180 degree DCM CLK output
+CLK270 => open, -- 270 degree DCM CLK output
+CLK2X => open, -- 2X DCM CLK output
+CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+CLK90 => open, -- 90 degree DCM CLK output
+CLKDV => clkdv_vga, -- Divided DCM CLK out (CLKDV_DIVIDE)
+CLKFX => open, -- DCM CLK synthesis out (M/D)
+CLKFX180 => open, -- 180 degree CLK synthesis out
+LOCKED => open, -- DCM LOCK status output
+PSDONE => open, -- Dynamic phase adjust done output
+STATUS => open, -- 8-bit DCM status bits output
+CLKFB => clockbuf1b, -- DCM clock feedback
+CLKIN => clockbuf1, -- Clock input (from IBUFG, BUFG or DCM)
+PSCLK => '0', -- Dynamic phase adjust clock input
+PSEN => '0', -- Dynamic phase adjust enable input
+PSINCDEC => open, -- Dynamic phase adjust increment/decrement
+RST => i_reset -- DCM asynchronous reset input
+);
+ibuf_clk_vga : ibufg
+port map (o => clockbuf1, i => clock);
+buf_clk_vga : bufg
+port map (o => clockbuf1b, i => clockbuf1a);
+
+dcm_cam : DCM
+generic map (
+CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+CLKFX_DIVIDE => 31, -- Can be any interger from 1 to 32
+CLKFX_MULTIPLY => 15, -- Can be any integer from 1 to 32
+CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+CLKIN_PERIOD => 20.0, -- Specify period of input clock
+CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
+CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
+DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
+DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
+DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
+DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+FACTORY_JF => X"C080", -- FACTORY JF Values
+PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
+SIM_MODE => "SAFE", -- Simulation: "SAFE" vs "FAST", see "Synthesis and Simulation Design Guide" for details
+STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+)
+port map (
+CLK0 => clockbuf2a, -- 0 degree DCM CLK ouptput
+CLK180 => open, -- 180 degree DCM CLK output
+CLK270 => open, -- 270 degree DCM CLK output
+CLK2X => open, -- 2X DCM CLK output
+CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+CLK90 => open, -- 90 degree DCM CLK output
+CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
+CLKFX => clkdv_cam, -- DCM CLK synthesis out (M/D)
+CLKFX180 => open, -- 180 degree CLK synthesis out
+LOCKED => open, -- DCM LOCK status output
+PSDONE => open, -- Dynamic phase adjust done output
+STATUS => open, -- 8-bit DCM status bits output
+CLKFB => clockbuf2b, -- DCM clock feedback
+CLKIN => clockbuf2, -- Clock input (from IBUFG, BUFG or DCM)
+PSCLK => '0', -- Dynamic phase adjust clock input
+PSEN => '0', -- Dynamic phase adjust enable input
+PSINCDEC => open, -- Dynamic phase adjust increment/decrement
+RST => i_reset -- DCM asynchronous reset input
+);
+ibuf_clk_cam : bufg
+port map (o => clockbuf2, i => clockbuf1);
+buf_clk_cam : bufg
+port map (o => clockbuf2b, i => clockbuf2a);
+
+mem : bram_vga
+port map (
+clka => bram_vga_clka,
+clkb => bram_vga_clkb,
+wea => bram_vga_wea,
+addra => bram_vga_addra,
+addrb => bram_vga_addrb,
+dina => bram_vga_dina,
+douta => bram_vga_douta
+);
+
+cam : camera
+port map (
+io_scl => camera_io_scl,
+io_sda => camera_io_sda,
+o_vs => camera_o_vs,
+o_hs => camera_o_hs,
+o_pclk => camera_o_pclk,
+i_xclk => camera_i_xclk,
+o_d => camera_o_d,
+i_rst => camera_i_rst,
+i_pwdn => camera_i_pwdn
+);
+
+end Behavioral;
diff --git a/clock/Nexys2_1200General.ucf b/clock/Nexys2_1200General.ucf
new file mode 100755
index 0000000..8f75bf1
--- /dev/null
+++ b/clock/Nexys2_1200General.ucf
@@ -0,0 +1,263 @@
+## This file is a general .ucf for Nexys2 rev A board
+## To use it in a project:
+## - remove or comment the lines corresponding to unused pins
+## - rename the used signals according to the project
+
+## Signals Led<7>Led<4> are assigned to pins which change type from s3e500 to other dies using the same package
+## Both versions are provided in this file.
+## Keep only the appropriate one, and remove or comment the other one.
+
+NET "CLK" LOC = "B8";
+NET "SDA" LOC = "L15";
+#NET "SDA" PULLUP;
+NET "SCL" LOC = "K12";
+#NET "SCL" PULLUP;
+NET "BTN_1" LOC = "B18";
+#NET "BTN_1" PULLUP;
+NET "BTN_2" LOC = "D18";
+#NET "BTN_2" PULLUP;
+NET "BTN_3" LOC = "E18";
+#NET "BTN_3" PULLUP;
+NET "BTN_4" LOC = "H13";
+#NET "BTN_4" PULLUP;
+
+## Clock pin for Nexys 2 Board
+#NET "clk" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
+#NET "clk1" LOC = "U9"; # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK, Sch name = GCLK1
+
+## onBoard USB controller
+## NOTE: DEPP and DSTM net names use some of the same pins, if trying to use both DEPP and DSTM use a signle net name for each shared pin.
+
+## Data bus for both the DEPP and DSTM interfaces uncomment lines 19-26 if using either one
+#NET "DB<0>" LOC = "R14"; # Bank = 2, Pin name = IO_L24N_2/A20, Type = DUAL, Sch name = U-FD0
+#NET "DB<1>" LOC = "R13"; # Bank = 2, Pin name = IO_L22N_2/A22, Type = DUAL, Sch name = U-FD1
+#NET "DB<2>" LOC = "P13"; # Bank = 2, Pin name = IO_L22P_2/A23, Type = DUAL, Sch name = U-FD2
+#NET "DB<3>" LOC = "T12"; # Bank = 2, Pin name = IO_L20P_2, Type = I/O, Sch name = U-FD3
+#NET "DB<4>" LOC = "N11"; # Bank = 2, Pin name = IO_L18N_2, Type = I/O, Sch name = U-FD4
+#NET "DB<5>" LOC = "R11"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = U-FD5
+#NET "DB<6>" LOC = "P10"; # Bank = 2, Pin name = IO_L15N_2/D1/GCLK3, Type = DUAL/GCLK, Sch name = U-FD6
+#NET "DB<7>" LOC = "R10"; # Bank = 2, Pin name = IO_L15P_2/D2/GCLK2, Type = DUAL/GCLK, Sch name = U-FD7
+
+## If using the DEPP interface uncomment lines 29-32
+#NET "EppWRITE" LOC = "V16"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-FLAGC
+#NET "EppASTB" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
+#NET "EppDSTB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
+#NET "EppWAIT" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
+
+## If using the DSTM interface uncomment lines 35-44
+#NET "DstmIFCLK" LOC = "T15"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = U-IFCLK
+#NET "DstmSLCS" LOC = "T16"; # Bank = 2, Pin name = IO_L26P_2/VS0/A17, Type = DUAL, Sch name = U-SLCS
+#NET "DstmFLAGA" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
+#NET "DstmFLAGB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
+#NET "DstmADR<0>" LOC = "T14"; # Bank = 2, Pin name = IO_L24P_2/A21, Type = DUAL, Sch name = U-FIFOAD0
+#NET "DstmADR<1>" LOC = "V13"; # Bank = 2, Pin name = IO_L19N_2/VREF_2, Type = VREF, Sch name = U-FIFOAD1
+#NET "DstmSLRD" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
+#NET "DstmSLWR" LOC = "V9"; # Bank = 2, Pin name = IO_L13N_2/D3/GCLK15, Type = DUAL/GCLK, Sch name = U-SLWR
+#NET "DstmSLOE" LOC = "V15"; # Bank = 2, Pin name = IO_L25P_2/VS2/A19, Type = DUAL, Sch name = U-SLOE
+#NET "DstmPKTEND" LOC = "V12"; # Bank = 2, Pin name = IO_L19P_2, Type = I/O, Sch name = U-PKTEND
+
+#NET "UsbMode" LOC = "U15"; # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type = DUAL, Sch name = U-INT0#
+#NET "UsbRdy" LOC = "U13"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-RDY
+
+## onBoard Cellular RAM and StrataFlash
+#NET "MemOE" LOC = "T2"; # Bank = 3, Pin name = IO_L24P_3, Type = I/O, Sch name = OE
+#NET "MemWR" LOC = "N7"; # Bank = 2, Pin name = IO_L07P_2, Type = I/O, Sch name = WE
+
+#NET "RamAdv" LOC = "J4"; # Bank = 3, Pin name = IO_L11N_3/LHCLK1, Type = LHCLK, Sch name = MT-ADV
+#NET "RamCS" LOC = "R6"; # Bank = 2, Pin name = IO_L05P_2, Type = I/O, Sch name = MT-CE
+#NET "RamClk" LOC = "H5"; # Bank = 3, Pin name = IO_L08N_3, Type = I/O, Sch name = MT-CLK
+#NET "RamCRE" LOC = "P7"; # Bank = 2, Pin name = IO_L07N_2, Type = I/O, Sch name = MT-CRE
+#NET "RamLB" LOC = "K5"; # Bank = 3, Pin name = IO_L14N_3/LHCLK7, Type = LHCLK, Sch name = MT-LB
+#NET "RamUB" LOC = "K4"; # Bank = 3, Pin name = IO_L13N_3/LHCLK5, Type = LHCLK, Sch name = MT-UB
+#NET "RamWait" LOC = "F5"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = MT-WAIT
+
+#NET "FlashRp" LOC = "T5"; # Bank = 2, Pin name = IO_L04N_2, Type = I/O, Sch name = RP#
+#NET "FlashCS" LOC = "R5"; # Bank = 2, Pin name = IO_L04P_2, Type = I/O, Sch name = ST-CE
+#NET "FlashStSts" LOC = "D3"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = ST-STS
+
+#NET "MemAdr<1>" LOC = "J1"; # Bank = 3, Pin name = IO_L12P_3/LHCLK2, Type = LHCLK, Sch name = ADR1
+#NET "MemAdr<2>" LOC = "J2"; # Bank = 3, Pin name = IO_L12N_3/LHCLK3/IRDY2, Type = LHCLK, Sch name = ADR2
+#NET "MemAdr<3>" LOC = "H4"; # Bank = 3, Pin name = IO_L09P_3, Type = I/O, Sch name = ADR3
+#NET "MemAdr<4>" LOC = "H1"; # Bank = 3, Pin name = IO_L10N_3, Type = I/O, Sch name = ADR4
+#NET "MemAdr<5>" LOC = "H2"; # Bank = 3, Pin name = IO_L10P_3, Type = I/O, Sch name = ADR5
+#NET "MemAdr<6>" LOC = "J5"; # Bank = 3, Pin name = IO_L11P_3/LHCLK0, Type = LHCLK, Sch name = ADR6
+#NET "MemAdr<7>" LOC = "H3"; # Bank = 3, Pin name = IO_L09N_3, Type = I/O, Sch name = ADR7
+#NET "MemAdr<8>" LOC = "H6"; # Bank = 3, Pin name = IO_L08P_3, Type = I/O, Sch name = ADR8
+#NET "MemAdr<9>" LOC = "F1"; # Bank = 3, Pin name = IO_L05P_3, Type = I/O, Sch name = ADR9
+#NET "MemAdr<10>" LOC = "G3"; # Bank = 3, Pin name = IO_L06P_3, Type = I/O, Sch name = ADR10
+#NET "MemAdr<11>" LOC = "G6"; # Bank = 3, Pin name = IO_L07P_3, Type = I/O, Sch name = ADR11
+#NET "MemAdr<12>" LOC = "G5"; # Bank = 3, Pin name = IO_L07N_3, Type = I/O, Sch name = ADR12
+#NET "MemAdr<13>" LOC = "G4"; # Bank = 3, Pin name = IO_L06N_3/VREF_3, Type = VREF, Sch name = ADR13
+#NET "MemAdr<14>" LOC = "F2"; # Bank = 3, Pin name = IO_L05N_3, Type = I/O, Sch name = ADR14
+#NET "MemAdr<15>" LOC = "E1"; # Bank = 3, Pin name = IO_L03N_3, Type = I/O, Sch name = ADR15
+#NET "MemAdr<16>" LOC = "M5"; # Bank = 3, Pin name = IO_L19P_3, Type = I/O, Sch name = ADR16
+#NET "MemAdr<17>" LOC = "E2"; # Bank = 3, Pin name = IO_L03P_3, Type = I/O, Sch name = ADR17
+#NET "MemAdr<18>" LOC = "C2"; # Bank = 3, Pin name = IO_L01N_3, Type = I/O, Sch name = ADR18
+#NET "MemAdr<19>" LOC = "C1"; # Bank = 3, Pin name = IO_L01P_3, Type = I/O, Sch name = ADR19
+#NET "MemAdr<20>" LOC = "D2"; # Bank = 3, Pin name = IO_L02N_3/VREF_3, Type = VREF, Sch name = ADR20
+#NET "MemAdr<21>" LOC = "K3"; # Bank = 3, Pin name = IO_L13P_3/LHCLK4/TRDY2, Type = LHCLK, Sch name = ADR21
+#NET "MemAdr<22>" LOC = "D1"; # Bank = 3, Pin name = IO_L02P_3, Type = I/O, Sch name = ADR22
+#NET "MemAdr<23>" LOC = "K6"; # Bank = 3, Pin name = IO_L14P_3/LHCLK6, Type = LHCLK, Sch name = ADR23
+
+#NET "MemDB<0>" LOC = "L1"; # Bank = 3, Pin name = IO_L15P_3, Type = I/O, Sch name = DB0
+#NET "MemDB<1>" LOC = "L4"; # Bank = 3, Pin name = IO_L16N_3, Type = I/O, Sch name = DB1
+#NET "MemDB<2>" LOC = "L6"; # Bank = 3, Pin name = IO_L17P_3, Type = I/O, Sch name = DB2
+#NET "MemDB<3>" LOC = "M4"; # Bank = 3, Pin name = IO_L18P_3, Type = I/O, Sch name = DB3
+#NET "MemDB<4>" LOC = "N5"; # Bank = 3, Pin name = IO_L20N_3, Type = I/O, Sch name = DB4
+#NET "MemDB<5>" LOC = "P1"; # Bank = 3, Pin name = IO_L21N_3, Type = I/O, Sch name = DB5
+#NET "MemDB<6>" LOC = "P2"; # Bank = 3, Pin name = IO_L21P_3, Type = I/O, Sch name = DB6
+#NET "MemDB<7>" LOC = "R2"; # Bank = 3, Pin name = IO_L23N_3, Type = I/O, Sch name = DB7
+#NET "MemDB<8>" LOC = "L3"; # Bank = 3, Pin name = IO_L16P_3, Type = I/O, Sch name = DB8
+#NET "MemDB<9>" LOC = "L5"; # Bank = 3, Pin name = IO_L17N_3/VREF_3, Type = VREF, Sch name = DB9
+#NET "MemDB<10>" LOC = "M3"; # Bank = 3, Pin name = IO_L18N_3, Type = I/O, Sch name = DB10
+#NET "MemDB<11>" LOC = "M6"; # Bank = 3, Pin name = IO_L19N_3, Type = I/O, Sch name = DB11
+#NET "MemDB<12>" LOC = "L2"; # Bank = 3, Pin name = IO_L15N_3, Type = I/O, Sch name = DB12
+#NET "MemDB<13>" LOC = "N4"; # Bank = 3, Pin name = IO_L20P_3, Type = I/O, Sch name = DB13
+#NET "MemDB<14>" LOC = "R3"; # Bank = 3, Pin name = IO_L23P_3, Type = I/O, Sch name = DB14
+#NET "MemDB<15>" LOC = "T1"; # Bank = 3, Pin name = IO_L24N_3, Type = I/O, Sch name = DB15
+
+## 7 segment display
+#NET "seg<0>" LOC = "L18"; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA
+#NET "seg<1>" LOC = "F18"; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB
+#NET "seg<2>" LOC = "D17"; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC
+#NET "seg<3>" LOC = "D16"; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD
+#NET "seg<4>" LOC = "G14"; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE
+#NET "seg<5>" LOC = "J17"; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
+#NET "seg<6>" LOC = "H14"; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG
+#NET "dp" LOC = "C17"; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP
+
+#NET "an<0>" LOC = "F17"; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0
+#NET "an<1>" LOC = "H17"; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1
+#NET "an<2>" LOC = "C18"; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2
+#NET "an<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3
+
+## Leds
+#NET "Led<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
+#NET "Led<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
+#NET "Led<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
+#NET "Led<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
+#NET "Led<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4? s3e500 only
+#NET "Led<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5? s3e500 only
+#NET "Led<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6? s3e500 only
+#NET "Led<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7? s3e500 only
+#NET "Led<4>" LOC = "E16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD4? other than s3e500
+#NET "Led<5>" LOC = "P16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD5? other than s3e500
+#NET "Led<6>" LOC = "E4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD6? other than s3e500
+#NET "Led<7>" LOC = "P4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD7? other than s3e500
+
+## Switches
+#NET "sw<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
+#NET "sw<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
+#NET "sw<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
+#NET "sw<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
+#NET "sw<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
+#NET "sw<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
+#NET "sw<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
+#NET "sw<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7
+
+## Buttons
+#NET "btn<0>" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
+#NET "btn<1>" LOC = "D18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = BTN1
+#NET "btn<2>" LOC = "E18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN2
+#NET "btn<3>" LOC = "H13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN3
+
+## VGA Connector
+#NET "vgaRed<1>" LOC = "R9"; # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0
+#NET "vgaRed<2>" LOC = "T8"; # Bank = 2, Pin name = IO_L10N_2, Type = I/O, Sch name = RED1
+#NET "vgaRed<3>" LOC = "R8"; # Bank = 2, Pin name = IO_L10P_2, Type = I/O, Sch name = RED2
+#NET "vgaGreen<1>" LOC = "N8"; # Bank = 2, Pin name = IO_L09N_2, Type = I/O, Sch name = GRN0
+#NET "vgaGreen<2>" LOC = "P8"; # Bank = 2, Pin name = IO_L09P_2, Type = I/O, Sch name = GRN1
+#NET "vgaGreen<3>" LOC = "P6"; # Bank = 2, Pin name = IO_L05N_2, Type = I/O, Sch name = GRN2
+#NET "vgaBlue<2>" LOC = "U5"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = BLU1
+#NET "vgaBlue<3>" LOC = "U4"; # Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DUAL, Sch name = BLU2
+
+#NET "Hsync" LOC = "T4"; # Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type = DUAL, Sch name = HSYNC
+#NET "Vsync" LOC = "U3"; # Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUAL, Sch name = VSYNC
+
+## PS/2 connector
+#NET "PS2C" LOC = "R12"; # Bank = 2, Pin name = IO_L20N_2, Type = I/O, Sch name = PS2C
+#NET "PS2D" LOC = "P11"; # Bank = 2, Pin name = IO_L18P_2, Type = I/O, Sch name = PS2D
+
+## FX2 connector
+#NET "PIO<0>" LOC = "B4"; # Bank = 0, Pin name = IO_L24N_0, Type = I/O, Sch name = R-IO1
+#NET "PIO<1>" LOC = "A4"; # Bank = 0, Pin name = IO_L24P_0, Type = I/O, Sch name = R-IO2
+#NET "PIO<2>" LOC = "C3"; # Bank = 0, Pin name = IO_L25P_0, Type = I/O, Sch name = R-IO3
+#NET "PIO<3>" LOC = "C4"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO4
+#NET "PIO<4>" LOC = "B6"; # Bank = 0, Pin name = IO_L20P_0, Type = I/O, Sch name = R-IO5
+#NET "PIO<5>" LOC = "D5"; # Bank = 0, Pin name = IO_L23N_0/VREF_0, Type = VREF, Sch name = R-IO6
+#NET "PIO<6>" LOC = "C5"; # Bank = 0, Pin name = IO_L23P_0, Type = I/O, Sch name = R-IO7
+#NET "PIO<7>" LOC = "F7"; # Bank = 0, Pin name = IO_L19P_0, Type = I/O, Sch name = R-IO8
+#NET "PIO<8>" LOC = "E7"; # Bank = 0, Pin name = IO_L19N_0/VREF_0, Type = VREF, Sch name = R-IO9
+#NET "PIO<9>" LOC = "A6"; # Bank = 0, Pin name = IO_L20N_0, Type = I/O, Sch name = R-IO10
+#NET "PIO<10>" LOC = "C7"; # Bank = 0, Pin name = IO_L18P_0, Type = I/O, Sch name = R-IO11
+#NET "PIO<11>" LOC = "F8"; # Bank = 0, Pin name = IO_L17N_0, Type = I/O, Sch name = R-IO12
+#NET "PIO<12>" LOC = "D7"; # Bank = 0, Pin name = IO_L18N_0/VREF_0, Type = VREF, Sch name = R-IO13
+#NET "PIO<13>" LOC = "E8"; # Bank = 0, Pin name = IO_L17P_0, Type = I/O, Sch name = R-IO14
+#NET "PIO<14>" LOC = "E9"; # Bank = 0, Pin name = IO_L15P_0, Type = I/O, Sch name = R-IO15
+#NET "PIO<15>" LOC = "C9"; # Bank = 0, Pin name = IO_L14P_0/GCLK10, Type = GCLK, Sch name = R-IO16
+#NET "PIO<16>" LOC = "A8"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO17
+#NET "PIO<17>" LOC = "G9"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO18
+#NET "PIO<18>" LOC = "F9"; # Bank = 0, Pin name = IO_L15N_0, Type = I/O, Sch name = R-IO19
+#NET "PIO<19>" LOC = "D10"; # Bank = 0, Pin name = IO_L11P_0/GCLK4, Type = GCLK, Sch name = R-IO20
+#NET "PIO<20>" LOC = "A10"; # Bank = 0, Pin name = IO_L12N_0/GCLK7, Type = GCLK, Sch name = R-IO21
+#NET "PIO<21>" LOC = "B10"; # Bank = 0, Pin name = IO_L12P_0/GCLK6, Type = GCLK, Sch name = R-IO22
+#NET "PIO<22>" LOC = "A11"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO23
+#NET "PIO<23>" LOC = "D11"; # Bank = 0, Pin name = IO_L09N_0, Type = I/O, Sch name = R-IO24
+#NET "PIO<24>" LOC = "E10"; # Bank = 0, Pin name = IO_L11N_0/GCLK5, Type = GCLK, Sch name = R-IO25
+#NET "PIO<25>" LOC = "B11"; # Bank = 0, Pin name = IO/VREF_0, Type = VREF, Sch name = R-IO26
+#NET "PIO<26>" LOC = "C11"; # Bank = 0, Pin name = IO_L09P_0, Type = I/O, Sch name = R-IO27
+#NET "PIO<27>" LOC = "E11"; # Bank = 0, Pin name = IO_L08P_0, Type = I/O, Sch name = R-IO28
+#NET "PIO<28>" LOC = "F11"; # Bank = 0, Pin name = IO_L08N_0, Type = I/O, Sch name = R-IO29
+#NET "PIO<29>" LOC = "E12"; # Bank = 0, Pin name = IO_L06N_0, Type = I/O, Sch name = R-IO30
+#NET "PIO<30>" LOC = "F12"; # Bank = 0, Pin name = IO_L06P_0, Type = I/O, Sch name = R-IO31
+#NET "PIO<31>" LOC = "A13"; # Bank = 0, Pin name = IO_L05P_0, Type = I/O, Sch name = R-IO32
+#NET "PIO<32>" LOC = "B13"; # Bank = 0, Pin name = IO_L05N_0/VREF_0, Type = VREF, Sch name = R-IO33
+#NET "PIO<33>" LOC = "E13"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO34
+#NET "PIO<34>" LOC = "A14"; # Bank = 0, Pin name = IO_L04N_0, Type = I/O, Sch name = R-IO35
+#NET "PIO<35>" LOC = "C14"; # Bank = 0, Pin name = IO_L03N_0/VREF_0, Type = VREF, Sch name = R-IO36
+#NET "PIO<36>" LOC = "D14"; # Bank = 0, Pin name = IO_L03P_0, Type = I/O, Sch name = R-IO37
+#NET "PIO<37>" LOC = "B14"; # Bank = 0, Pin name = IO_L04P_0, Type = I/O, Sch name = R-IO38
+#NET "PIO<38>" LOC = "A16"; # Bank = 0, Pin name = IO_L01N_0, Type = I/O, Sch name = R-IO39
+#NET "PIO<39>" LOC = "B16"; # Bank = 0, Pin name = IO_L01P_0, Type = I/O, Sch name = R-IO40
+
+## 12 pin connectors
+
+##JA
+#NET "JA<0>" LOC = "L15"; # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1
+#NET "JA<1>" LOC = "K12"; # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2
+#NET "JA<2>" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
+#NET "JA<3>" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
+#NET "JA<4>" LOC = "K13"; # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL, Sch name = JA7
+#NET "JA<5>" LOC = "L16"; # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL, Sch name = JA8
+#NET "JA<6>" LOC = "M14"; # Bank = 1, Pin name = IO_L05P_1, Type = I/O, Sch name = JA9
+#NET "JA<7>" LOC = "M16"; # Bank = 1, Pin name = IO_L07N_1, Type = I/O, Sch name = JA10
+
+##JB
+#NET "JB<0>" LOC = "M13"; # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF, Sch name = JB1
+#NET "JB<1>" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
+#NET "JB<2>" LOC = "R15"; # Bank = 1, Pin name = IO_L03P_1, Type = I/O, Sch name = JB3
+#NET "JB<3>" LOC = "T17"; # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL, Sch name = JB4
+#NET "JB<4>" LOC = "P17"; # Bank = 1, Pin name = IO_L06P_1, Type = I/O, Sch name = JB7
+#NET "JB<5>" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
+#NET "JB<6>" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
+#NET "JB<7>" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
+
+##JC
+#NET "JC<0>" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
+#NET "JC<1>" LOC = "J16"; # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL, Sch name = JC2
+#NET "JC<2>" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
+#NET "JC<3>" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
+#NET "JC<4>" LOC = "H15"; # Bank = 1, Pin name = IO_L17N_1, Type = I/O, Sch name = JC7
+#NET "JC<5>" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
+#NET "JC<6>" LOC = "G16"; # Bank = 1, Pin name = IO_L18N_1, Type = I/O, Sch name = JC9
+#NET "JC<7>" LOC = "J12"; # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL, Sch name = JC10
+
+##JD - NOTE: For other JD pins see LD(3:0) above under "Leds"
+#NET "JD<0>" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
+#NET "JD<1>" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
+#NET "JD<2>" LOC = "N18"; # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3
+#NET "JD<3>" LOC = "P18"; # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4
+
+## RS232 connector
+#NET "RsRx" LOC = "U6"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = RS-RX
+#NET "RsTx" LOC = "P9"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = RS-TX
diff --git a/clock/clock.xise b/clock/clock.xise
new file mode 100755
index 0000000..472cc30
--- /dev/null
+++ b/clock/clock.xise
@@ -0,0 +1,363 @@
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diff --git a/convert_glcdfont.awk b/clock/convert_glcdfont.awk
old mode 100644
new mode 100755
similarity index 100%
rename from convert_glcdfont.awk
rename to clock/convert_glcdfont.awk
diff --git a/clock/debounce_button.vhd b/clock/debounce_button.vhd
new file mode 100755
index 0000000..a04f42c
--- /dev/null
+++ b/clock/debounce_button.vhd
@@ -0,0 +1,96 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:13:46 09/15/2020
+-- Design Name:
+-- Module Name: debounce_button - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity debounce_button is
+generic (g_board_clock : integer);
+Port
+(
+i_button : in STD_LOGIC;
+i_clk : in STD_LOGIC;
+o_stable : out STD_LOGIC
+);
+end debounce_button;
+
+architecture Behavioral of debounce_button is
+
+signal slow_clk_en : std_logic;
+signal Q0,Q1,Q2,Q2_bar : std_logic := '0';
+
+begin
+
+p0 : process (i_clk) is
+ variable aa : integer := 250_000;
+ variable counter : integer := 0;
+ variable clk : std_logic;
+begin
+ if (rising_edge(i_clk)) then
+ if (counter = aa-1) then
+ counter := 0;
+ clk := '1';
+ else
+ clk := '0';
+ end if;
+ end if;
+ counter := counter + 1;
+ slow_clk_en <= clk;
+end process p0;
+
+p1a : process (i_clk) is
+begin
+ if (rising_edge(i_clk)) then
+ --if (slow_clk_en = '1') then
+ Q0 <= i_button;
+ --end if;
+ end if;
+end process p1a;
+
+p1b : process (i_clk) is
+begin
+ if (rising_edge(i_clk)) then
+ --if (slow_clk_en = '1') then
+ Q1 <= Q0;
+ --end if;
+ end if;
+end process p1b;
+
+p1c : process (i_clk) is
+begin
+ if (rising_edge(i_clk)) then
+ --if (slow_clk_en = '1') then
+ Q2 <= Q1;
+ --end if;
+ end if;
+end process p1c;
+
+Q2_bar <= not Q2;
+o_stable <= Q1 and Q2_bar;
+
+end Behavioral;
diff --git a/glcdfont.vhd b/clock/glcdfont.vhd
old mode 100644
new mode 100755
similarity index 100%
rename from glcdfont.vhd
rename to clock/glcdfont.vhd
diff --git a/i2c.vhd b/clock/i2c.vhd
old mode 100644
new mode 100755
similarity index 100%
rename from i2c.vhd
rename to clock/i2c.vhd
diff --git a/p_pkg1.vhd b/clock/p_pkg1.vhd
old mode 100644
new mode 100755
similarity index 95%
rename from p_pkg1.vhd
rename to clock/p_pkg1.vhd
index d445afe..ee9b28c
--- a/p_pkg1.vhd
+++ b/clock/p_pkg1.vhd
@@ -11,7 +11,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all;
package p_pkg1 is
- type array1 is array(natural range <>) of std_logic_vector(11 downto 0);
+ type array1 is array(natural range <>) of std_logic_vector(7 downto 0);
-- type is
-- record
diff --git a/clock/tb_clock_divider.vhd b/clock/tb_clock_divider.vhd
new file mode 100755
index 0000000..73997c8
--- /dev/null
+++ b/clock/tb_clock_divider.vhd
@@ -0,0 +1,95 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:42:51 09/18/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/i2c_test_2/tb_clock_divider.vhd
+-- Project Name: i2c_test_1
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: clock_divider
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_clock_divider IS
+END tb_clock_divider;
+
+ARCHITECTURE behavior OF tb_clock_divider IS
+
+procedure clk_gen(signal clk : out std_logic; constant wait_start : time; constant HT : time; constant LT : time) is
+begin
+clk <= '0';
+wait for wait_start;
+loop
+clk <= '1';
+wait for HT;
+clk <= '0';
+wait for LT;
+end loop;
+end procedure;
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT clock_divider
+ Generic(g_board_clock : integer);
+ PORT(
+ i_clk : IN std_logic;
+ o_clk_25khz : OUT std_logic;
+ o_clk_50khz : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal i_clk : std_logic := '0';
+
+ --Outputs
+ signal o_clk_25khz : std_logic;
+ signal o_clk_50khz : std_logic;
+
+ -- Clock period definitions
+ constant board_clock : integer := 50_000_000;
+
+BEGIN
+
+ clk_gen(i_clk, 0 ns, 20 ns, 20 ns);
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: clock_divider
+ Generic map (g_board_clock => board_clock)
+ PORT MAP (
+ i_clk => i_clk,
+ o_clk_25khz => o_clk_25khz,
+ o_clk_50khz => o_clk_50khz
+ );
+
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ wait;
+ end process;
+
+END;
diff --git a/clock/tb_debounce_button.vhd b/clock/tb_debounce_button.vhd
new file mode 100755
index 0000000..3384688
--- /dev/null
+++ b/clock/tb_debounce_button.vhd
@@ -0,0 +1,108 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:32:21 09/15/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/i2c_test_2/tb_debounce_button.vhd
+-- Project Name: i2c_test_1
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: debounce_button
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_debounce_button IS
+END tb_debounce_button;
+
+ARCHITECTURE behavior OF tb_debounce_button IS
+
+constant board_clock : integer := 50_000_000;
+
+procedure clk_gen(signal clk : out std_logic; constant wait_start : time; constant HT : time; constant LT : time) is
+begin
+clk <= '0';
+wait for wait_start;
+loop
+clk <= '1';
+wait for HT;
+clk <= '0';
+wait for LT;
+end loop;
+end procedure;
+
+COMPONENT debounce_button
+generic (g_board_clock : integer);
+PORT(
+i_button : IN std_logic;
+i_clk : IN std_logic;
+o_stable : OUT std_logic
+);
+END COMPONENT;
+
+signal i_button : std_logic := '0';
+signal i_clk : std_logic := '0';
+signal o_stable : std_logic := '0';
+
+BEGIN
+
+clk_gen(i_clk, 0 ns, 10 ns, 10 ns);
+
+uut: debounce_button
+generic map (g_board_clock => board_clock)
+PORT MAP (
+i_button => i_button,
+i_clk => i_clk,
+o_stable => o_stable
+);
+
+-- Stimulus process
+stim_proc: process
+begin
+
+wait for 2450 us;
+i_button <= '0';
+wait for 1 us;
+i_button <= '1';
+wait for 300 us;
+i_button <= '0';
+wait for 50 us;
+i_button <= '1';
+wait for 200 us;
+i_button <= '0';
+wait for 70 us;
+i_button <= '1';
+wait for 100 us;
+i_button <= '0';
+wait for 100 us;
+
+--i_button <= '0';
+--wait for 1000 ns;
+--i_button <= '1';
+--wait for 20 ms;
+--i_button <= '0';
+
+wait;
+end process;
+
+END;
diff --git a/tb_glcdfont.vhd b/clock/tb_glcdfont.vhd
old mode 100644
new mode 100755
similarity index 100%
rename from tb_glcdfont.vhd
rename to clock/tb_glcdfont.vhd
diff --git a/clock/tb_test_oled.vhd b/clock/tb_test_oled.vhd
new file mode 100755
index 0000000..d01d75a
--- /dev/null
+++ b/clock/tb_test_oled.vhd
@@ -0,0 +1,99 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:51:58 08/28/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/i2c_test_1/tb_test_oled.vhd
+-- Project Name: i2c_test_1
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: test_oled
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE WORK.p_pkg1.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_test_oled IS
+END tb_test_oled;
+
+ARCHITECTURE behavior OF tb_test_oled IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT test_oled
+ PORT(
+ i_clk : IN std_logic;
+ i_rst : IN std_logic;
+ i_refresh : IN std_logic;
+ i_char : in array1;
+ io_sda : INOUT std_logic;
+ io_scl : INOUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal clk : std_logic := '0';
+ signal rst : std_logic := '0';
+ signal refresh : std_logic := '0';
+ signal text : array1(0 to 6-1) := (x"30",x"31",x"32",x"33",x"34",x"35"); -- 012345
+
+ --BiDirs
+ signal sda : std_logic;
+ signal scl : std_logic;
+
+ -- Clock period definitions
+ constant clk_period : time := 20 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: test_oled PORT MAP (
+ i_clk => clk,
+ i_rst => rst,
+ i_refresh => refresh,
+ i_char => text,
+ io_sda => sda,
+ io_scl => scl
+ );
+
+ -- Clock process definitions
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+-- wait for 60 ms;
+-- refresh <= '1';
+-- wait for 20 ns;
+-- refresh <= '0';
+ wait;
+ end process;
+
+END;
diff --git a/clock/tb_top.vhd b/clock/tb_top.vhd
new file mode 100755
index 0000000..f954556
--- /dev/null
+++ b/clock/tb_top.vhd
@@ -0,0 +1,113 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:06:42 09/11/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/i2c_test_2/tb_top.vhd
+-- Project Name: i2c_test_1
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_top IS
+END tb_top;
+
+ARCHITECTURE behavior OF tb_top IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT top GENERIC(
+ g_board_clock : INTEGER;
+ g_bus_clock : INTEGER);
+ PORT(
+ clk : IN std_logic;
+ btn_1 : IN std_logic;
+ btn_2 : IN std_logic;
+ btn_3 : IN std_logic;
+ btn_4 : IN std_logic;
+ sda : INOUT std_logic;
+ scl : INOUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal clk : std_logic := '0';
+ signal btn_1 : std_logic := '0';
+ signal btn_2 : std_logic := '0';
+ signal btn_3 : std_logic := '0';
+ signal btn_4 : std_logic := '0';
+
+ --BiDirs
+ signal sda : std_logic;
+ signal scl : std_logic;
+
+ -- Clock period definitions
+ constant clk_period : time := 20 ns;
+ constant board_clock : integer := 1_000_000; -- 20ms
+ constant bus_clock : integer := 2_000; -- 20 ms
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: top
+ GENERIC MAP (
+ g_board_clock => board_clock,
+ g_bus_clock => bus_clock)
+ PORT MAP (
+ clk => clk,
+ btn_1 => btn_1,
+ btn_2 => btn_2,
+ btn_3 => btn_3,
+ btn_4 => btn_4,
+ sda => sda,
+ scl => scl
+ );
+
+ -- Clock process definitions
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+
+ wait for clk_period*10;
+
+ -- insert stimulus here
+
+ wait;
+ end process;
+
+END;
diff --git a/test_oled.vhd b/clock/test_oled.vhd
old mode 100644
new mode 100755
similarity index 78%
rename from test_oled.vhd
rename to clock/test_oled.vhd
index b4c28bc..f47999e
--- a/test_oled.vhd
+++ b/clock/test_oled.vhd
@@ -22,10 +22,16 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use WORK.p_pkg1.ALL;
-entity test_oled is
+entity test_oled is
+generic (
+g_board_clock : integer;
+g_bus_clock : integer
+);
port
(
signal i_clk : in std_logic;
+signal i_rst : in std_logic;
+signal i_refresh : in std_logic;
signal i_char : in array1;
signal io_sda,io_scl : inout std_logic
);
@@ -33,8 +39,8 @@ end test_oled;
architecture Behavioral of test_oled is
-constant GCLK : integer := 50_000_000;
-constant BCLK : integer := 100_000;
+constant GCLK : integer := g_board_clock;
+constant BCLK : integer := g_bus_clock;
constant OLED_WIDTH : integer := 128;
constant OLED_HEIGHT : integer := 32;
@@ -42,13 +48,9 @@ constant OLED_PAGES_ALL : integer := OLED_WIDTH * ((OLED_HEIGHT + 7) / 8);
constant OLED_DATA : integer := to_integer(unsigned'(x"40"));
constant OLED_COMMAND : integer := to_integer(unsigned'(x"00")); -- 00,80
-constant OLED_STABLE : integer := 2; -- we send the same data x-time
-
-SIGNAL busy_cnt : INTEGER := 0; -- for i2c, count the clk tick when i2c_busy=1
-
-constant NI_INIT : natural := 26;
+constant NI_INIT : natural := 25;
type A_INIT is array (0 to NI_INIT-1) of std_logic_vector(7 downto 0);
-signal init_display : A_INIT := (x"AE",x"D5",x"F0",x"A8",x"1F",x"D3",x"00",x"40",x"8D",x"14",x"20",x"00",x"A1",x"C8",x"DA",x"02",x"81",x"8F",x"D9",x"F1",x"DB",x"40",x"A4",x"A6",x"2E",x"AF");
+signal init_display : A_INIT := (x"AE",x"D5",x"F0",x"A8",x"1F",x"D3",x"00",x"40",x"8D",x"14",x"20",x"00",x"A1",x"C8",x"DA",x"02",x"81",x"8F",x"D9",x"F1",x"DB",x"40",x"A4",x"A6",x"2E");
constant NI_SET_COORDINATION : natural := 6;
type A_SET_COORDINATION is array (0 to NI_SET_COORDINATION-1) of std_logic_vector(7 downto 0);
@@ -62,6 +64,10 @@ SIGNAL i2c_busy : STD_LOGIC; --i2c busy signal
SIGNAL i2c_reset : STD_LOGIC; --i2c busy signal
SIGNAL busy_prev : STD_LOGIC; --previous value of i2c busy signal
+signal busy_cnt : INTEGER := 0; -- for i2c, count the clk tick when i2c_busy=1
+signal index_character : INTEGER := 0;
+signal current_character : std_logic_vector(7 downto 0);
+
component glcdfont is
port(
i_clk : in std_logic;
@@ -97,10 +103,12 @@ type state is
(
start, -- initialize oled
set_address_1, -- set begin point 0,0
- clear_display_state, -- clear display
+ clear_display_state_1, -- clear display and power on
set_address_2, -- set begin point 0,0
- send_character, -- send the some data
+ send_character, -- send the some data/text array
check_character_index, -- check have char
+ clear_display_state_2, -- clear display - rest after text
+ scroll_left,
stop -- when index=counter, i2c disable
);
signal c_state,n_state : state := start;
@@ -139,19 +147,19 @@ PORT MAP
scl => io_scl
);
-p0 : process (i_clk,i2c_reset) is
- variable index : INTEGER RANGE 0 TO OLED_STABLE := 0;
- variable counter : INTEGER RANGE 0 TO OLED_STABLE := OLED_STABLE;
- variable index_character : INTEGER := 0;
+p0 : process (i_clk,i_rst) is
begin
- if (i2c_reset = '0') then
- i2c_ena <= '0';
- busy_cnt <= 0;
- c_state <= start;
- i2c_reset <= '1';
- elsif (rising_edge(i_clk)) then
- c_state <= n_state;
- if (index < counter) then
+ if (rising_edge(i_clk)) then
+ if (i_rst = '1') then
+ n_state <= start;
+ busy_cnt <= 0;
+ index_character <= 0;
+ elsif (i_refresh = '1') then
+ n_state <= set_address_1;
+ busy_cnt <= 0;
+ index_character <= 0;
+ else
+ c_state <= n_state;
case c_state is
when start =>
busy_prev <= i2c_busy;
@@ -160,6 +168,7 @@ begin
end if;
case busy_cnt is
when 0 =>
+ i2c_reset <= '1';
i2c_ena <= '1'; -- we are busy
i2c_addr <= "0111100"; -- address 3C 3D 78 ; 0111100 0111101 1111000
i2c_rw <= '0';
@@ -191,11 +200,11 @@ begin
i2c_ena <= '0';
if (i2c_busy = '0') then
busy_cnt <= 0;
- n_state <= clear_display_state;
+ n_state <= clear_display_state_1;
end if;
when others => null;
end case;
- when clear_display_state =>
+ when clear_display_state_1 =>
busy_prev <= i2c_busy;
if (busy_prev = '0' and i2c_busy = '1') then
busy_cnt <= busy_cnt + 1;
@@ -205,10 +214,12 @@ begin
i2c_ena <= '1'; -- we are busy
i2c_addr <= "0111100"; -- address 3C 3D 78 ; 0111100 0111101 1111000
i2c_rw <= '0';
- i2c_data_wr <= std_logic_vector(to_unsigned(OLED_DATA,8));
+ i2c_data_wr <= std_logic_vector(to_unsigned(OLED_COMMAND,8));
when 1 to OLED_PAGES_ALL =>
i2c_data_wr <= x"00"; -- command - FF/allpixels,00/blank,F0/zebra
when OLED_PAGES_ALL+1 =>
+ i2c_data_wr <= x"AF"; -- display on
+ when OLED_PAGES_ALL+2 =>
i2c_ena <= '0';
if (i2c_busy = '0') then
busy_cnt <= 0;
@@ -248,20 +259,21 @@ begin
i2c_addr <= "0111100"; -- address 3C 3D 78 ; 0111100 0111101 1111000
i2c_rw <= '0';
i2c_data_wr <= std_logic_vector(to_unsigned(OLED_DATA,8));
+ current_character <= i_char(index_character);
when 1 =>
- glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(i_char(index_character)))+0,glcdfont_index'length));
+ glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(current_character))*5+0,glcdfont_index'length));
i2c_data_wr <= glcdfont_character;
when 2 =>
- glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(i_char(index_character)))+1,glcdfont_index'length));
+ glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(current_character))*5+1,glcdfont_index'length));
i2c_data_wr <= glcdfont_character;
when 3 =>
- glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(i_char(index_character)))+2,glcdfont_index'length));
+ glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(current_character))*5+2,glcdfont_index'length));
i2c_data_wr <= glcdfont_character;
when 4 =>
- glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(i_char(index_character)))+3,glcdfont_index'length));
+ glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(current_character))*5+3,glcdfont_index'length));
i2c_data_wr <= glcdfont_character;
when 5 =>
- glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(i_char(index_character)))+4,glcdfont_index'length));
+ glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(current_character))*5+4,glcdfont_index'length));
i2c_data_wr <= glcdfont_character;
when 6 =>
i2c_data_wr <= x"00"; -- to space between characters / optional
@@ -282,20 +294,18 @@ begin
when 0 =>
i2c_ena <= '1'; -- we are busy
if (i2c_busy = '1') then
- index_character := index_character + 1;
+ index_character <= index_character + 1;
end if;
when 1 =>
i2c_data_wr <= x"00";
if (i2c_busy = '1') then
if (index_character > i_char'length-1) then -- we gain end array
i2c_ena <= '0';
- if (i2c_busy = '0') then
- busy_cnt <= 0;
- n_state <= stop;
- end if;
+ busy_cnt <= 0;
+ n_state <= clear_display_state_2;
end if;
end if;
- when 3 =>
+ when 2 =>
i2c_ena <= '0';
if (i2c_busy = '0') then
busy_cnt <= 0;
@@ -303,13 +313,31 @@ begin
end if;
when others => null;
end case;
+ when clear_display_state_2 =>
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ i2c_addr <= "0111100"; -- address 3C 3D 78 ; 0111100 0111101 1111000
+ i2c_rw <= '0';
+ i2c_data_wr <= std_logic_vector(to_unsigned(OLED_COMMAND,8));
+ when 1 to (OLED_PAGES_ALL-(i_char'length*6)) =>
+ i2c_data_wr <= x"00"; -- command - FF/allpixels,00/blank,F0/zebra
+ when (OLED_PAGES_ALL-(i_char'length*6))+1 =>
+ i2c_ena <= '0';
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ n_state <= stop;
+ end if;
+ when others => null;
+ end case;
when stop =>
- index := index + 1;
- n_state <= start;
+ i2c_ena <= '0';
when others => null;
end case;
- else
- i2c_ena <= '0'; -- if index=counter then disable i2c, high impedance on sda/scl
end if;
end if;
end process p0;
diff --git a/clock/top.vhd b/clock/top.vhd
new file mode 100755
index 0000000..a960813
--- /dev/null
+++ b/clock/top.vhd
@@ -0,0 +1,267 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:11:54 09/04/2020
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_pkg1.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top is
+generic (
+g_board_clock : integer := 50_000_000;
+g_bus_clock : integer := 100_000
+);
+port(
+signal clk : in std_logic;
+signal btn_1 : in std_logic;
+signal btn_2 : in std_logic;
+signal btn_3 : in std_logic;
+signal btn_4 : in std_logic;
+signal sda,scl : inout std_logic
+);
+end top;
+
+architecture Behavioral of top is
+
+component test_oled is
+generic (
+g_board_clock : integer;
+g_bus_clock : integer
+);
+port
+(
+signal i_clk : in std_logic;
+signal i_rst : in std_logic;
+signal i_refresh : in std_logic;
+signal i_char : in array1;
+signal io_sda,io_scl : inout std_logic
+);
+end component test_oled;
+for all : test_oled use entity WORK.test_oled(Behavioral);
+
+component debounce_button is
+generic (g_board_clock : integer);
+Port
+(
+i_button : in STD_LOGIC;
+i_clk : in STD_LOGIC;
+o_stable : out STD_LOGIC
+);
+end component debounce_button;
+for all : debounce_button use entity WORK.debounce_button(Behavioral);
+
+constant TEXT_LENGTH : integer := 8;
+signal text : array1(0 to TEXT_LENGTH-1) := (x"30",x"30",x"3A",x"30",x"30",x"3A",x"30",x"30");
+
+signal second1 : std_logic;
+
+signal second_a,second_b,minute_a,minute_b,hour_a,hour_b : integer := 0;
+
+signal refresh_screen : std_logic := '1';
+signal prev_stop_timer,stop_timer : std_logic := '0';
+
+signal o_stable_btn1,o_stable_btn2,o_stable_btn3,o_stable_btn4 : std_logic;
+
+constant BOARD_FREQUENCY_NORMAL : integer := g_board_clock;
+constant BOARD_FREQUENCY_DIV10 : integer := BOARD_FREQUENCY_NORMAL/2;
+
+signal ONE_SECOND : integer := BOARD_FREQUENCY_NORMAL;
+
+begin
+
+c0 : test_oled
+generic map (
+g_board_clock => g_board_clock,
+g_bus_clock => g_bus_clock
+)
+port map
+(
+ i_clk => clk,
+ i_rst => o_stable_btn1,
+ i_refresh => refresh_screen,
+ i_char => text,
+ io_sda => sda,
+ io_scl => scl
+);
+
+c1 : debounce_button
+generic map (
+ g_board_clock => g_board_clock
+)
+port map
+(
+ i_button => btn_1,
+ i_clk => clk,
+ o_stable => o_stable_btn1
+);
+
+c2 : debounce_button
+generic map (
+ g_board_clock => g_board_clock
+)
+port map
+(
+ i_button => btn_2,
+ i_clk => clk,
+ o_stable => o_stable_btn2
+);
+
+c3 : debounce_button
+generic map (
+ g_board_clock => g_board_clock
+)
+port map
+(
+ i_button => btn_3,
+ i_clk => clk,
+ o_stable => o_stable_btn3
+);
+
+c4 : debounce_button
+generic map (
+ g_board_clock => g_board_clock
+)
+port map
+(
+ i_button => btn_4,
+ i_clk => clk,
+ o_stable => o_stable_btn4
+);
+
+p0 : process (clk) is
+ variable TICK : integer := 0;
+begin
+ if (rising_edge(clk)) then
+ if (o_stable_btn1 = '1') then -- reset timer
+ second_a <= 0;
+ second_b <= 0;
+ minute_a <= 0;
+ minute_b <= 0;
+ hour_a <= 0;
+ hour_b <= 0;
+ elsif (o_stable_btn2 = '1') then -- stop timer
+ stop_timer <= not stop_timer;
+ elsif (o_stable_btn3 = '1') then -- set minute
+ if (stop_timer = '1') then
+ if (minute_b*10+minute_a+1 < 60) then
+ if (minute_a < 9) then
+ minute_a <= minute_a + 1;
+ else
+ minute_b <= minute_b + 1;
+ minute_a <= 0;
+ end if;
+ else
+ minute_a <= 0;
+ minute_b <= 0;
+ end if;
+ end if;
+ elsif (o_stable_btn4 = '1') then -- set hour
+ if (stop_timer = '1') then
+ if (not (hour_b = 2 and hour_a = 3)) then
+ if (hour_a < 9) then
+ hour_a <= hour_a + 1;
+ else
+ hour_b <= hour_b + 1;
+ hour_a <= 0;
+ end if;
+ else
+ hour_a <= 0;
+ hour_b <= 0;
+ end if;
+ end if;
+ end if;
+ if (stop_timer = '1') then
+ ONE_SECOND <= BOARD_FREQUENCY_DIV10;
+ elsif (stop_timer = '0') then
+ ONE_SECOND <= BOARD_FREQUENCY_NORMAL;
+ end if;
+ if (TICK < ONE_SECOND-1) then
+ second1 <= '0';
+ TICK := TICK + 1;
+ refresh_screen <= '0';
+ else
+ second1 <= '1';
+ TICK := 0;
+ refresh_screen <= '1';
+ if (stop_timer = '0') then
+ if (second_a < 9) then
+ second_a <= second_a + 1;
+ else
+ second_b <= second_b + 1;
+ second_a <= 0;
+ if (second_b*10+second_a+1 > 59) then
+ minute_a <= minute_a + 1;
+ if (minute_a < 9) then
+ minute_a <= minute_a + 1;
+ second_a <= 0;
+ second_b <= 0;
+ else
+ minute_b <= minute_b + 1;
+ minute_a <= 0;
+ second_a <= 0;
+ second_b <= 0;
+ if (minute_b*10+minute_a+1 > 59) then
+ hour_a <= hour_a + 1;
+ if (hour_a < 9) then
+ hour_a <= hour_a + 1;
+ second_a <= 0;
+ second_b <= 0;
+ minute_a <= 0;
+ minute_b <= 0;
+ else
+ hour_b <= hour_b + 1;
+ hour_a <= 0;
+ second_a <= 0;
+ second_b <= 0;
+ minute_a <= 0;
+ minute_b <= 0;
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+ if (hour_b = 2 and hour_a = 3 and minute_b = 5 and minute_a = 9 and second_b = 5 and second_a = 9) then
+ second_a <= 0;
+ second_b <= 0;
+ minute_a <= 0;
+ minute_b <= 0;
+ hour_a <= 0;
+ hour_b <= 0;
+ end if;
+ end if;
+ end if;
+ end if;
+end process p0;
+
+text(7) <= std_logic_vector(to_unsigned(to_integer(unsigned'(x"30"))+second_a,8));
+text(6) <= std_logic_vector(to_unsigned(to_integer(unsigned'(x"30"))+second_b,8));
+text(4) <= std_logic_vector(to_unsigned(to_integer(unsigned'(x"30"))+minute_a,8));
+text(3) <= std_logic_vector(to_unsigned(to_integer(unsigned'(x"30"))+minute_b,8));
+text(1) <= std_logic_vector(to_unsigned(to_integer(unsigned'(x"30"))+hour_a,8));
+text(0) <= std_logic_vector(to_unsigned(to_integer(unsigned'(x"30"))+hour_b,8));
+
+end Behavioral;
diff --git a/clock/top.xst b/clock/top.xst
new file mode 100755
index 0000000..6201acd
--- /dev/null
+++ b/clock/top.xst
@@ -0,0 +1,56 @@
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn top.prj
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc3s1200e-4-fg320
+-top top
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/dac_delta_sigma/Nexys2_1200General.ucf b/dac_delta_sigma/Nexys2_1200General.ucf
new file mode 100755
index 0000000..a9a88ae
--- /dev/null
+++ b/dac_delta_sigma/Nexys2_1200General.ucf
@@ -0,0 +1,252 @@
+## This file is a general .ucf for Nexys2 rev A board
+## To use it in a project:
+## - remove or comment the lines corresponding to unused pins
+## - rename the used signals according to the project
+
+## Signals Led<7>Led<4> are assigned to pins which change type from s3e500 to other dies using the same package
+## Both versions are provided in this file.
+## Keep only the appropriate one, and remove or comment the other one.
+
+#NET "SDA" LOC = "L15";
+#NET "SCL" LOC = "K12";
+
+## Clock pin for Nexys 2 Board
+NET "clk" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
+#NET "clk1" LOC = "U9"; # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK, Sch name = GCLK1
+
+## onBoard USB controller
+## NOTE: DEPP and DSTM net names use some of the same pins, if trying to use both DEPP and DSTM use a signle net name for each shared pin.
+
+## Data bus for both the DEPP and DSTM interfaces uncomment lines 19-26 if using either one
+#NET "DB<0>" LOC = "R14"; # Bank = 2, Pin name = IO_L24N_2/A20, Type = DUAL, Sch name = U-FD0
+#NET "DB<1>" LOC = "R13"; # Bank = 2, Pin name = IO_L22N_2/A22, Type = DUAL, Sch name = U-FD1
+#NET "DB<2>" LOC = "P13"; # Bank = 2, Pin name = IO_L22P_2/A23, Type = DUAL, Sch name = U-FD2
+#NET "DB<3>" LOC = "T12"; # Bank = 2, Pin name = IO_L20P_2, Type = I/O, Sch name = U-FD3
+#NET "DB<4>" LOC = "N11"; # Bank = 2, Pin name = IO_L18N_2, Type = I/O, Sch name = U-FD4
+#NET "DB<5>" LOC = "R11"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = U-FD5
+#NET "DB<6>" LOC = "P10"; # Bank = 2, Pin name = IO_L15N_2/D1/GCLK3, Type = DUAL/GCLK, Sch name = U-FD6
+#NET "DB<7>" LOC = "R10"; # Bank = 2, Pin name = IO_L15P_2/D2/GCLK2, Type = DUAL/GCLK, Sch name = U-FD7
+
+## If using the DEPP interface uncomment lines 29-32
+#NET "EppWRITE" LOC = "V16"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-FLAGC
+#NET "EppASTB" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
+#NET "EppDSTB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
+#NET "EppWAIT" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
+
+## If using the DSTM interface uncomment lines 35-44
+#NET "DstmIFCLK" LOC = "T15"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = U-IFCLK
+#NET "DstmSLCS" LOC = "T16"; # Bank = 2, Pin name = IO_L26P_2/VS0/A17, Type = DUAL, Sch name = U-SLCS
+#NET "DstmFLAGA" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
+#NET "DstmFLAGB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
+#NET "DstmADR<0>" LOC = "T14"; # Bank = 2, Pin name = IO_L24P_2/A21, Type = DUAL, Sch name = U-FIFOAD0
+#NET "DstmADR<1>" LOC = "V13"; # Bank = 2, Pin name = IO_L19N_2/VREF_2, Type = VREF, Sch name = U-FIFOAD1
+#NET "DstmSLRD" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
+#NET "DstmSLWR" LOC = "V9"; # Bank = 2, Pin name = IO_L13N_2/D3/GCLK15, Type = DUAL/GCLK, Sch name = U-SLWR
+#NET "DstmSLOE" LOC = "V15"; # Bank = 2, Pin name = IO_L25P_2/VS2/A19, Type = DUAL, Sch name = U-SLOE
+#NET "DstmPKTEND" LOC = "V12"; # Bank = 2, Pin name = IO_L19P_2, Type = I/O, Sch name = U-PKTEND
+
+#NET "UsbMode" LOC = "U15"; # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type = DUAL, Sch name = U-INT0#
+#NET "UsbRdy" LOC = "U13"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-RDY
+
+## onBoard Cellular RAM and StrataFlash
+#NET "io_MemOE" LOC = "T2"; # Bank = 3, Pin name = IO_L24P_3, Type = I/O, Sch name = OE
+#NET "io_MemWR" LOC = "N7"; # Bank = 2, Pin name = IO_L07P_2, Type = I/O, Sch name = WE
+
+#NET "io_RamAdv" LOC = "J4"; # Bank = 3, Pin name = IO_L11N_3/LHCLK1, Type = LHCLK, Sch name = MT-ADV
+#NET "io_RamCS" LOC = "R6"; # Bank = 2, Pin name = IO_L05P_2, Type = I/O, Sch name = MT-CE
+#NET "io_RamClk" LOC = "H5"; # Bank = 3, Pin name = IO_L08N_3, Type = I/O, Sch name = MT-CLK
+#NET "io_RamCRE" LOC = "P7"; # Bank = 2, Pin name = IO_L07N_2, Type = I/O, Sch name = MT-CRE
+#NET "io_RamLB" LOC = "K5"; # Bank = 3, Pin name = IO_L14N_3/LHCLK7, Type = LHCLK, Sch name = MT-LB
+#NET "io_RamUB" LOC = "K4"; # Bank = 3, Pin name = IO_L13N_3/LHCLK5, Type = LHCLK, Sch name = MT-UB
+#NET "RamWait" LOC = "F5"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = MT-WAIT
+
+#NET "FlashRp" LOC = "T5"; # Bank = 2, Pin name = IO_L04N_2, Type = I/O, Sch name = RP#
+#NET "io_FlashCS" LOC = "R5"; # Bank = 2, Pin name = IO_L04P_2, Type = I/O, Sch name = ST-CE
+#NET "FlashStSts" LOC = "D3"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = ST-STS
+
+#NET "io_MemAdr<1>" LOC = "J1"; # Bank = 3, Pin name = IO_L12P_3/LHCLK2, Type = LHCLK, Sch name = ADR1
+#NET "io_MemAdr<2>" LOC = "J2"; # Bank = 3, Pin name = IO_L12N_3/LHCLK3/IRDY2, Type = LHCLK, Sch name = ADR2
+#NET "io_MemAdr<3>" LOC = "H4"; # Bank = 3, Pin name = IO_L09P_3, Type = I/O, Sch name = ADR3
+#NET "io_MemAdr<4>" LOC = "H1"; # Bank = 3, Pin name = IO_L10N_3, Type = I/O, Sch name = ADR4
+#NET "io_MemAdr<5>" LOC = "H2"; # Bank = 3, Pin name = IO_L10P_3, Type = I/O, Sch name = ADR5
+#NET "io_MemAdr<6>" LOC = "J5"; # Bank = 3, Pin name = IO_L11P_3/LHCLK0, Type = LHCLK, Sch name = ADR6
+#NET "io_MemAdr<7>" LOC = "H3"; # Bank = 3, Pin name = IO_L09N_3, Type = I/O, Sch name = ADR7
+#NET "io_MemAdr<8>" LOC = "H6"; # Bank = 3, Pin name = IO_L08P_3, Type = I/O, Sch name = ADR8
+#NET "io_MemAdr<9>" LOC = "F1"; # Bank = 3, Pin name = IO_L05P_3, Type = I/O, Sch name = ADR9
+#NET "io_MemAdr<10>" LOC = "G3"; # Bank = 3, Pin name = IO_L06P_3, Type = I/O, Sch name = ADR10
+#NET "io_MemAdr<11>" LOC = "G6"; # Bank = 3, Pin name = IO_L07P_3, Type = I/O, Sch name = ADR11
+#NET "io_MemAdr<12>" LOC = "G5"; # Bank = 3, Pin name = IO_L07N_3, Type = I/O, Sch name = ADR12
+#NET "io_MemAdr<13>" LOC = "G4"; # Bank = 3, Pin name = IO_L06N_3/VREF_3, Type = VREF, Sch name = ADR13
+#NET "io_MemAdr<14>" LOC = "F2"; # Bank = 3, Pin name = IO_L05N_3, Type = I/O, Sch name = ADR14
+#NET "io_MemAdr<15>" LOC = "E1"; # Bank = 3, Pin name = IO_L03N_3, Type = I/O, Sch name = ADR15
+#NET "io_MemAdr<16>" LOC = "M5"; # Bank = 3, Pin name = IO_L19P_3, Type = I/O, Sch name = ADR16
+#NET "io_MemAdr<17>" LOC = "E2"; # Bank = 3, Pin name = IO_L03P_3, Type = I/O, Sch name = ADR17
+#NET "io_MemAdr<18>" LOC = "C2"; # Bank = 3, Pin name = IO_L01N_3, Type = I/O, Sch name = ADR18
+#NET "io_MemAdr<19>" LOC = "C1"; # Bank = 3, Pin name = IO_L01P_3, Type = I/O, Sch name = ADR19
+#NET "io_MemAdr<20>" LOC = "D2"; # Bank = 3, Pin name = IO_L02N_3/VREF_3, Type = VREF, Sch name = ADR20
+#NET "io_MemAdr<21>" LOC = "K3"; # Bank = 3, Pin name = IO_L13P_3/LHCLK4/TRDY2, Type = LHCLK, Sch name = ADR21
+#NET "io_MemAdr<22>" LOC = "D1"; # Bank = 3, Pin name = IO_L02P_3, Type = I/O, Sch name = ADR22
+#NET "io_MemAdr<23>" LOC = "K6"; # Bank = 3, Pin name = IO_L14P_3/LHCLK6, Type = LHCLK, Sch name = ADR23
+
+#NET "io_MemDB<0>" LOC = "L1"; # Bank = 3, Pin name = IO_L15P_3, Type = I/O, Sch name = DB0
+#NET "io_MemDB<1>" LOC = "L4"; # Bank = 3, Pin name = IO_L16N_3, Type = I/O, Sch name = DB1
+#NET "io_MemDB<2>" LOC = "L6"; # Bank = 3, Pin name = IO_L17P_3, Type = I/O, Sch name = DB2
+#NET "io_MemDB<3>" LOC = "M4"; # Bank = 3, Pin name = IO_L18P_3, Type = I/O, Sch name = DB3
+#NET "io_MemDB<4>" LOC = "N5"; # Bank = 3, Pin name = IO_L20N_3, Type = I/O, Sch name = DB4
+#NET "io_MemDB<5>" LOC = "P1"; # Bank = 3, Pin name = IO_L21N_3, Type = I/O, Sch name = DB5
+#NET "io_MemDB<6>" LOC = "P2"; # Bank = 3, Pin name = IO_L21P_3, Type = I/O, Sch name = DB6
+#NET "io_MemDB<7>" LOC = "R2"; # Bank = 3, Pin name = IO_L23N_3, Type = I/O, Sch name = DB7
+#NET "io_MemDB<8>" LOC = "L3"; # Bank = 3, Pin name = IO_L16P_3, Type = I/O, Sch name = DB8
+#NET "io_MemDB<9>" LOC = "L5"; # Bank = 3, Pin name = IO_L17N_3/VREF_3, Type = VREF, Sch name = DB9
+#NET "io_MemDB<10>" LOC = "M3"; # Bank = 3, Pin name = IO_L18N_3, Type = I/O, Sch name = DB10
+#NET "io_MemDB<11>" LOC = "M6"; # Bank = 3, Pin name = IO_L19N_3, Type = I/O, Sch name = DB11
+#NET "io_MemDB<12>" LOC = "L2"; # Bank = 3, Pin name = IO_L15N_3, Type = I/O, Sch name = DB12
+#NET "io_MemDB<13>" LOC = "N4"; # Bank = 3, Pin name = IO_L20P_3, Type = I/O, Sch name = DB13
+#NET "io_MemDB<14>" LOC = "R3"; # Bank = 3, Pin name = IO_L23P_3, Type = I/O, Sch name = DB14
+#NET "io_MemDB<15>" LOC = "T1"; # Bank = 3, Pin name = IO_L24N_3, Type = I/O, Sch name = DB15
+
+## 7 segment display
+#NET "seg<0>" LOC = "L18"; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA
+#NET "seg<1>" LOC = "F18"; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB
+#NET "seg<2>" LOC = "D17"; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC
+#NET "seg<3>" LOC = "D16"; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD
+#NET "seg<4>" LOC = "G14"; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE
+#NET "seg<5>" LOC = "J17"; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
+#NET "seg<6>" LOC = "H14"; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG
+#NET "dp" LOC = "C17"; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP
+
+#NET "an<0>" LOC = "F17"; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0
+#NET "an<1>" LOC = "H17"; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1
+#NET "an<2>" LOC = "C18"; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2
+#NET "an<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3
+
+## Leds
+NET "Led<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
+NET "Led<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
+NET "Led<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
+NET "Led<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
+#NET "Led<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4? s3e500 only
+#NET "Led<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5? s3e500 only
+#NET "Led<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6? s3e500 only
+#NET "Led<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7? s3e500 only
+NET "Led<4>" LOC = "E16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD4? other than s3e500
+NET "Led<5>" LOC = "P16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD5? other than s3e500
+NET "Led<6>" LOC = "E4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD6? other than s3e500
+NET "Led<7>" LOC = "P4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD7? other than s3e500
+
+## Switches
+#NET "sw<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
+#NET "sw<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
+#NET "sw<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
+#NET "sw<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
+#NET "sw<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
+#NET "sw<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
+#NET "sw<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
+#NET "sw<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7
+
+## Buttons
+#NET "btn<0>" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
+#NET "btn<1>" LOC = "D18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = BTN1
+#NET "btn<2>" LOC = "E18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN2
+#NET "btn<3>" LOC = "H13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN3
+
+## VGA Connector
+#NET "vgaRed<1>" LOC = "R9"; # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0
+#NET "vgaRed<2>" LOC = "T8"; # Bank = 2, Pin name = IO_L10N_2, Type = I/O, Sch name = RED1
+#NET "vgaRed<3>" LOC = "R8"; # Bank = 2, Pin name = IO_L10P_2, Type = I/O, Sch name = RED2
+#NET "vgaGreen<1>" LOC = "N8"; # Bank = 2, Pin name = IO_L09N_2, Type = I/O, Sch name = GRN0
+#NET "vgaGreen<2>" LOC = "P8"; # Bank = 2, Pin name = IO_L09P_2, Type = I/O, Sch name = GRN1
+#NET "vgaGreen<3>" LOC = "P6"; # Bank = 2, Pin name = IO_L05N_2, Type = I/O, Sch name = GRN2
+#NET "vgaBlue<2>" LOC = "U5"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = BLU1
+#NET "vgaBlue<3>" LOC = "U4"; # Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DUAL, Sch name = BLU2
+
+#NET "Hsync" LOC = "T4"; # Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type = DUAL, Sch name = HSYNC
+#NET "Vsync" LOC = "U3"; # Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUAL, Sch name = VSYNC
+
+## PS/2 connector
+#NET "PS2C" LOC = "R12"; # Bank = 2, Pin name = IO_L20N_2, Type = I/O, Sch name = PS2C
+#NET "PS2D" LOC = "P11"; # Bank = 2, Pin name = IO_L18P_2, Type = I/O, Sch name = PS2D
+
+## FX2 connector
+#NET "PIO<0>" LOC = "B4"; # Bank = 0, Pin name = IO_L24N_0, Type = I/O, Sch name = R-IO1
+#NET "PIO<1>" LOC = "A4"; # Bank = 0, Pin name = IO_L24P_0, Type = I/O, Sch name = R-IO2
+#NET "PIO<2>" LOC = "C3"; # Bank = 0, Pin name = IO_L25P_0, Type = I/O, Sch name = R-IO3
+#NET "PIO<3>" LOC = "C4"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO4
+#NET "PIO<4>" LOC = "B6"; # Bank = 0, Pin name = IO_L20P_0, Type = I/O, Sch name = R-IO5
+#NET "PIO<5>" LOC = "D5"; # Bank = 0, Pin name = IO_L23N_0/VREF_0, Type = VREF, Sch name = R-IO6
+#NET "PIO<6>" LOC = "C5"; # Bank = 0, Pin name = IO_L23P_0, Type = I/O, Sch name = R-IO7
+#NET "PIO<7>" LOC = "F7"; # Bank = 0, Pin name = IO_L19P_0, Type = I/O, Sch name = R-IO8
+#NET "PIO<8>" LOC = "E7"; # Bank = 0, Pin name = IO_L19N_0/VREF_0, Type = VREF, Sch name = R-IO9
+#NET "PIO<9>" LOC = "A6"; # Bank = 0, Pin name = IO_L20N_0, Type = I/O, Sch name = R-IO10
+#NET "PIO<10>" LOC = "C7"; # Bank = 0, Pin name = IO_L18P_0, Type = I/O, Sch name = R-IO11
+#NET "PIO<11>" LOC = "F8"; # Bank = 0, Pin name = IO_L17N_0, Type = I/O, Sch name = R-IO12
+#NET "PIO<12>" LOC = "D7"; # Bank = 0, Pin name = IO_L18N_0/VREF_0, Type = VREF, Sch name = R-IO13
+#NET "PIO<13>" LOC = "E8"; # Bank = 0, Pin name = IO_L17P_0, Type = I/O, Sch name = R-IO14
+#NET "PIO<14>" LOC = "E9"; # Bank = 0, Pin name = IO_L15P_0, Type = I/O, Sch name = R-IO15
+#NET "PIO<15>" LOC = "C9"; # Bank = 0, Pin name = IO_L14P_0/GCLK10, Type = GCLK, Sch name = R-IO16
+#NET "PIO<16>" LOC = "A8"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO17
+#NET "PIO<17>" LOC = "G9"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO18
+#NET "PIO<18>" LOC = "F9"; # Bank = 0, Pin name = IO_L15N_0, Type = I/O, Sch name = R-IO19
+#NET "PIO<19>" LOC = "D10"; # Bank = 0, Pin name = IO_L11P_0/GCLK4, Type = GCLK, Sch name = R-IO20
+#NET "PIO<20>" LOC = "A10"; # Bank = 0, Pin name = IO_L12N_0/GCLK7, Type = GCLK, Sch name = R-IO21
+#NET "PIO<21>" LOC = "B10"; # Bank = 0, Pin name = IO_L12P_0/GCLK6, Type = GCLK, Sch name = R-IO22
+#NET "PIO<22>" LOC = "A11"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO23
+#NET "PIO<23>" LOC = "D11"; # Bank = 0, Pin name = IO_L09N_0, Type = I/O, Sch name = R-IO24
+#NET "PIO<24>" LOC = "E10"; # Bank = 0, Pin name = IO_L11N_0/GCLK5, Type = GCLK, Sch name = R-IO25
+#NET "PIO<25>" LOC = "B11"; # Bank = 0, Pin name = IO/VREF_0, Type = VREF, Sch name = R-IO26
+#NET "PIO<26>" LOC = "C11"; # Bank = 0, Pin name = IO_L09P_0, Type = I/O, Sch name = R-IO27
+#NET "PIO<27>" LOC = "E11"; # Bank = 0, Pin name = IO_L08P_0, Type = I/O, Sch name = R-IO28
+#NET "PIO<28>" LOC = "F11"; # Bank = 0, Pin name = IO_L08N_0, Type = I/O, Sch name = R-IO29
+#NET "PIO<29>" LOC = "E12"; # Bank = 0, Pin name = IO_L06N_0, Type = I/O, Sch name = R-IO30
+#NET "PIO<30>" LOC = "F12"; # Bank = 0, Pin name = IO_L06P_0, Type = I/O, Sch name = R-IO31
+#NET "PIO<31>" LOC = "A13"; # Bank = 0, Pin name = IO_L05P_0, Type = I/O, Sch name = R-IO32
+#NET "PIO<32>" LOC = "B13"; # Bank = 0, Pin name = IO_L05N_0/VREF_0, Type = VREF, Sch name = R-IO33
+#NET "PIO<33>" LOC = "E13"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO34
+#NET "PIO<34>" LOC = "A14"; # Bank = 0, Pin name = IO_L04N_0, Type = I/O, Sch name = R-IO35
+#NET "PIO<35>" LOC = "C14"; # Bank = 0, Pin name = IO_L03N_0/VREF_0, Type = VREF, Sch name = R-IO36
+#NET "PIO<36>" LOC = "D14"; # Bank = 0, Pin name = IO_L03P_0, Type = I/O, Sch name = R-IO37
+#NET "PIO<37>" LOC = "B14"; # Bank = 0, Pin name = IO_L04P_0, Type = I/O, Sch name = R-IO38
+#NET "PIO<38>" LOC = "A16"; # Bank = 0, Pin name = IO_L01N_0, Type = I/O, Sch name = R-IO39
+#NET "PIO<39>" LOC = "B16"; # Bank = 0, Pin name = IO_L01P_0, Type = I/O, Sch name = R-IO40
+
+## 12 pin connectors
+
+##JA
+#NET "JA<0>" LOC = "L15"; # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1
+#NET "JA<1>" LOC = "K12"; # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2
+#NET "JA<2>" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
+#NET "JA<3>" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
+#NET "JA<4>" LOC = "K13"; # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL, Sch name = JA7
+#NET "JA<5>" LOC = "L16"; # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL, Sch name = JA8
+#NET "JA<6>" LOC = "M14"; # Bank = 1, Pin name = IO_L05P_1, Type = I/O, Sch name = JA9
+#NET "JA<7>" LOC = "M16"; # Bank = 1, Pin name = IO_L07N_1, Type = I/O, Sch name = JA10
+
+##JB
+#NET "JB<0>" LOC = "M13"; # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF, Sch name = JB1
+#NET "JB<1>" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
+#NET "JB<2>" LOC = "R15"; # Bank = 1, Pin name = IO_L03P_1, Type = I/O, Sch name = JB3
+#NET "JB<3>" LOC = "T17"; # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL, Sch name = JB4
+#NET "JB<4>" LOC = "P17"; # Bank = 1, Pin name = IO_L06P_1, Type = I/O, Sch name = JB7
+#NET "JB<5>" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
+#NET "JB<6>" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
+#NET "JB<7>" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
+
+##JC
+#NET "JC<0>" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
+#NET "JC<1>" LOC = "J16"; # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL, Sch name = JC2
+#NET "JC<2>" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
+#NET "JC<3>" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
+#NET "JC<4>" LOC = "H15"; # Bank = 1, Pin name = IO_L17N_1, Type = I/O, Sch name = JC7
+#NET "JC<5>" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
+#NET "JC<6>" LOC = "G16"; # Bank = 1, Pin name = IO_L18N_1, Type = I/O, Sch name = JC9
+#NET "JC<7>" LOC = "J12"; # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL, Sch name = JC10
+
+##JD - NOTE: For other JD pins see LD(3:0) above under "Leds"
+#NET "JD<0>" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
+#NET "JD<1>" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
+#NET "JD<2>" LOC = "N18"; # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3
+#NET "JD<3>" LOC = "P18"; # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4
+
+## RS232 connector
+#NET "RsRx" LOC = "U6"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = RS-RX
+#NET "RsTx" LOC = "P9"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = RS-TX
diff --git a/dac_delta_sigma/clock_divider.vhd b/dac_delta_sigma/clock_divider.vhd
new file mode 100755
index 0000000..3278099
--- /dev/null
+++ b/dac_delta_sigma/clock_divider.vhd
@@ -0,0 +1,63 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:42:10 09/18/2020
+-- Design Name:
+-- Module Name: clock_divider - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_divider is
+Port(
+i_clk : in STD_LOGIC;
+i_board_clock : in INTEGER;
+i_divider : in INTEGER;
+o_clk : out STD_LOGIC
+);
+end clock_divider;
+
+architecture Behavioral of clock_divider is
+begin
+
+p0 : process (i_clk) is
+ variable clk_out : std_logic;
+ variable a : integer := i_board_clock;
+ variable b : integer := i_divider;
+begin
+ if (rising_edge(i_clk)) then
+ if (a <= 0) then
+ clk_out := '1';
+ a := i_board_clock;
+ b := i_divider;
+ else
+ clk_out := '0';
+ a := a - b;
+ end if;
+ end if;
+ o_clk <= clk_out;
+end process p0;
+
+end Behavioral;
+
diff --git a/dac_delta_sigma/clock_divider1.vhd b/dac_delta_sigma/clock_divider1.vhd
new file mode 100755
index 0000000..f8fdf45
--- /dev/null
+++ b/dac_delta_sigma/clock_divider1.vhd
@@ -0,0 +1,62 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:42:10 09/18/2020
+-- Design Name:
+-- Module Name: clock_divider - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_divider1 is
+Generic (
+ g_board_clock : integer;
+ g_divider : integer
+);
+Port (
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+);
+end clock_divider1;
+
+architecture Behavioral of clock_divider1 is
+begin
+
+p0 : process (i_clock) is
+ variable clock_out : std_logic;
+ variable counter : integer := 0;
+begin
+ if (rising_edge(i_clock)) then
+ if (counter = (g_board_clock / g_divider) - 1) then
+ clock_out := '1';
+ counter := 0;
+ else
+ clock_out := '0';
+ counter := counter + 1;
+ end if;
+ end if;
+ o_clock <= clock_out;
+end process p0;
+
+end Behavioral;
diff --git a/dac_delta_sigma/dac_delta_sigma.vhd b/dac_delta_sigma/dac_delta_sigma.vhd
new file mode 100755
index 0000000..6a8db65
--- /dev/null
+++ b/dac_delta_sigma/dac_delta_sigma.vhd
@@ -0,0 +1,52 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:50:09 03/03/2021
+-- Design Name:
+-- Module Name: dac_delta_sigma - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity dac_delta_sigma is
+Port (
+clk : in STD_LOGIC;
+data : in STD_LOGIC_VECTOR (7 downto 0);
+PulseStream : out STD_LOGIC
+);
+end dac_delta_sigma;
+
+architecture Behavioral of dac_delta_sigma is
+ signal sum : STD_LOGIC_VECTOR(8 downto 0) := (others=>'0');
+begin
+ PulseStream <= sum(8);
+ p0 : process (clk,sum) is
+ begin
+ if (rising_edge(clk)) then
+ sum <= ("0" & sum(7 downto 0)) + ("0" & data);
+ end if;
+ end process p0;
+end Behavioral;
diff --git a/dac_delta_sigma/dac_delta_sigma.xise b/dac_delta_sigma/dac_delta_sigma.xise
new file mode 100755
index 0000000..24ae14c
--- /dev/null
+++ b/dac_delta_sigma/dac_delta_sigma.xise
@@ -0,0 +1,363 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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diff --git a/dac_delta_sigma/modulator_example.vhd b/dac_delta_sigma/modulator_example.vhd
new file mode 100755
index 0000000..d89346b
--- /dev/null
+++ b/dac_delta_sigma/modulator_example.vhd
@@ -0,0 +1,48 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity modulator is
+generic (
+ N_AUDIO : integer := 16;
+ N_DELTA : integer := 24;
+ N_SIGMA : integer := 32;
+ N_DELAY : integer := 25
+port (
+);
+ i_clock : in std_logic;
+ i_reset : in std_logic; -- resetb?
+ i_audio : in signed(N_AUDIO-1 downto 0);
+ i_pwm_fb : in signed(N_DELTA-1 downto 0);
+ o_pwm_out : out std_logic
+);
+end entity modulator;
+
+architecture arch of modulator is
+ signal compare : std_logic;
+ signal delta,feedback : signed(N_DELTA-1 downto 0);
+ signal sigma : signed(N_SIGMA-1 downto 0);
+ signal delay : std_logic_vector(N_DELAY-1 downto 0);
+begin
+ -- discrete-time model of first-order asynch delta-sigma modulator
+ p0 : process (i_clock,i_reset) is
+ begin
+ if (reset = '1') then
+ delta <= 0;
+ sigma <= 0;
+ delay <= (others => '0');
+ elsif (rising_edge(i_clock)) then
+ delta <= audio_in - feedback;
+ sigma <= sigma + delta;
+ delay <= delay(N_DELAY-2 downto 0) & compare;
+ end if;
+ end process p0;
+
+ -- comparator : check sign bit (MSB) of input word
+ compare <= not sigma(N_SIGMA-1);
+ -- PWM out : last bit of delay line
+ pwm_out <= delay(N_DELAY-1);
+ -- generate feedback amplitude from PWM state
+ feedback <= pwm_fb when (pwm_out = '1') else -pwm_fb;
+end architecture arch;
+
diff --git a/dac_delta_sigma/tb_dac_delta_sigma.vhd b/dac_delta_sigma/tb_dac_delta_sigma.vhd
new file mode 100755
index 0000000..c9066e3
--- /dev/null
+++ b/dac_delta_sigma/tb_dac_delta_sigma.vhd
@@ -0,0 +1,94 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:53:38 03/03/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/dac_delta_sigma/tb_dac_delta_sigma.vhd
+-- Project Name: dac_delta_sigma
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: dac_delta_sigma
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_dac_delta_sigma IS
+END tb_dac_delta_sigma;
+
+ARCHITECTURE behavior OF tb_dac_delta_sigma IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT dac_delta_sigma
+ PORT(
+ clk : IN std_logic;
+ data : IN std_logic_vector(0 to 7);
+ PulseStream : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal clk : std_logic := '0';
+ signal data : std_logic_vector(7 downto 0) := (others => '0');
+
+ --Outputs
+ signal PulseStream : std_logic;
+
+ -- Clock period definitions
+ constant clk_period : time := 20 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: dac_delta_sigma PORT MAP (
+ clk => clk,
+ data => data,
+ PulseStream => PulseStream
+ );
+
+ -- Clock process definitions
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+ -- Stimulus process
+ stim_proc: process
+ variable cp : integer := 15;
+ begin
+ for i in 0 to 255 loop
+ data <= std_logic_vector(to_unsigned(i,8));
+ wait for cp*clk_period;
+ end loop;
+ for i in 0 to 255 loop
+ data <= std_logic_vector(to_unsigned(255-i,8));
+ wait for cp*clk_period;
+ end loop;
+ wait;
+ end process;
+
+END;
diff --git a/dac_delta_sigma/tb_dac_delta_sigma.wcfg b/dac_delta_sigma/tb_dac_delta_sigma.wcfg
new file mode 100755
index 0000000..eeb7eaf
--- /dev/null
+++ b/dac_delta_sigma/tb_dac_delta_sigma.wcfg
@@ -0,0 +1,62 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ tb
+ label
+
+ clk
+ clk
+
+
+ data[7:0]
+ data[7:0]
+
+
+ pulsestream
+ pulsestream
+
+
+ clk_period
+ clk_period
+
+
+
+ top
+ label
+
+ clk
+ clk
+
+
+ data[7:0]
+ data[7:0]
+ HEXRADIX
+
+
+ pulsestream
+ pulsestream
+
+
+ sum[8:0]
+ sum[8:0]
+ HEXRADIX
+
+
+
diff --git a/dac_delta_sigma/tb_top.vhd b/dac_delta_sigma/tb_top.vhd
new file mode 100755
index 0000000..e8b4e59
--- /dev/null
+++ b/dac_delta_sigma/tb_top.vhd
@@ -0,0 +1,90 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:28:34 03/03/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/dac_delta_sigma/tb_top.vhd
+-- Project Name: dac_delta_sigma
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_top IS
+END tb_top;
+
+ARCHITECTURE behavior OF tb_top IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT top
+ PORT(
+ clk : IN std_logic;
+ led : OUT std_logic_vector(7 downto 0)
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal clk : std_logic := '0';
+
+ --Outputs
+ signal led : std_logic_vector(7 downto 0);
+
+ -- Clock period definitions
+ constant clk_period : time := 20 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: top PORT MAP (
+ clk => clk,
+ led => led
+ );
+
+ -- Clock process definitions
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+
+ wait for clk_period*10;
+
+ -- insert stimulus here
+
+ wait;
+ end process;
+
+END;
diff --git a/dac_delta_sigma/tb_top.wcfg b/dac_delta_sigma/tb_top.wcfg
new file mode 100755
index 0000000..8d16af9
--- /dev/null
+++ b/dac_delta_sigma/tb_top.wcfg
@@ -0,0 +1,76 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ tb_top
+ label
+
+ clk
+ clk
+
+
+ led[7:0]
+ led[7:0]
+
+
+ clk_period
+ clk_period
+
+
+
+ top
+ label
+
+ clk
+ clk
+
+
+ led[7:0]
+ led[7:0]
+
+
+ data[7:0]
+ data[7:0]
+ UNSIGNEDDECRADIX
+
+
+ o_ps
+ o_ps
+
+
+
+ c0
+ label
+
+ clk
+ clk
+
+
+ data[7:0]
+ data[7:0]
+ HEXRADIX
+
+
+ pulsestream
+ pulsestream
+
+
+ sum[8:0]
+ sum[8:0]
+ HEXRADIX
+
+
+
diff --git a/dac_delta_sigma/top.vhd b/dac_delta_sigma/top.vhd
new file mode 100755
index 0000000..2597a0d
--- /dev/null
+++ b/dac_delta_sigma/top.vhd
@@ -0,0 +1,116 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:13:38 03/03/2021
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top is
+Port (
+clk : in STD_LOGIC;
+led : out STD_LOGIC_VECTOR (7 downto 0)
+);
+end top;
+
+architecture Behavioral of top is
+
+component clock_divider1 is
+Generic (
+ g_board_clock : integer;
+ g_divider : integer
+);
+Port (
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+);
+end component clock_divider1;
+
+component dac_delta_sigma is
+Port (
+clk : in STD_LOGIC;
+data : in STD_LOGIC_VECTOR (7 downto 0);
+PulseStream : out STD_LOGIC
+);
+end component dac_delta_sigma;
+
+signal data : std_logic_vector(7 downto 0);
+signal o_ps : std_logic;
+
+signal o_clk : std_logic;
+
+signal direction : std_logic := '0';
+
+begin
+
+c0 : dac_delta_sigma
+port map (
+clk => o_clk,
+data => data,
+PulseStream => o_ps
+);
+
+c1 : clock_divider1
+Generic map (g_board_clock => 50_000_000, g_divider => 100)
+Port map(i_clock => clk, o_clock => o_clk);
+
+p0 : process (o_clk,direction) is
+ variable index : integer range 0 to 255 := 0;
+ variable v_data : std_logic_vector(7 downto 0);
+begin
+ if (o_clk = '0') then
+ if (direction = '0') then
+ if (index = 255) then
+ direction <= '1';
+ index := 255;
+ else
+ v_data := std_logic_vector(to_unsigned(index,8));
+ index := index + 1;
+ end if;
+ end if;
+ if (direction = '1') then
+ if (index = 0) then
+ direction <= '0';
+ index := 0;
+ else
+ v_data := std_logic_vector(to_unsigned(index,8));
+ index := index - 1;
+ end if;
+ end if;
+ end if;
+ data <= v_data;
+end process p0;
+
+led(0) <= o_ps;
+led(1) <= o_ps;
+led(2) <= o_ps;
+led(3) <= o_ps;
+led(4) <= o_ps;
+led(5) <= o_ps;
+led(6) <= o_ps;
+led(7) <= o_ps;
+
+end Behavioral;
diff --git a/digital_clock.gif b/digital_clock.gif
new file mode 100755
index 0000000..e88f6f8
Binary files /dev/null and b/digital_clock.gif differ
diff --git a/example_csram_oled/clock_divider.vhd b/example_csram_oled/clock_divider.vhd
new file mode 100755
index 0000000..3278099
--- /dev/null
+++ b/example_csram_oled/clock_divider.vhd
@@ -0,0 +1,63 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:42:10 09/18/2020
+-- Design Name:
+-- Module Name: clock_divider - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_divider is
+Port(
+i_clk : in STD_LOGIC;
+i_board_clock : in INTEGER;
+i_divider : in INTEGER;
+o_clk : out STD_LOGIC
+);
+end clock_divider;
+
+architecture Behavioral of clock_divider is
+begin
+
+p0 : process (i_clk) is
+ variable clk_out : std_logic;
+ variable a : integer := i_board_clock;
+ variable b : integer := i_divider;
+begin
+ if (rising_edge(i_clk)) then
+ if (a <= 0) then
+ clk_out := '1';
+ a := i_board_clock;
+ b := i_divider;
+ else
+ clk_out := '0';
+ a := a - b;
+ end if;
+ end if;
+ o_clk <= clk_out;
+end process p0;
+
+end Behavioral;
+
diff --git a/example_csram_oled/i2c.vhd b/example_csram_oled/i2c.vhd
new file mode 100755
index 0000000..9042896
--- /dev/null
+++ b/example_csram_oled/i2c.vhd
@@ -0,0 +1,269 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:46:01 08/21/2020
+-- Design Name:
+-- Module Name: i2c - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+--
+-- FileName: i2c_master.vhd
+-- Dependencies: none
+-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
+--
+-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
+-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
+-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
+-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
+-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
+-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
+-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
+-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
+--
+-- Version History
+-- Version 1.0 11/01/2012 Scott Larson
+-- Initial Public Release
+-- Version 2.0 06/20/2014 Scott Larson
+-- Added ability to interface with different slaves in the same transaction
+-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
+-- Corrected timing of when ack_error signal clears
+-- Version 2.1 10/21/2014 Scott Larson
+-- Replaced gated clock with clock enable
+-- Adjusted timing of SCL during start and stop conditions
+-- Version 2.2 02/05/2015 Scott Larson
+-- Corrected small SDA glitch introduced in version 2.1
+--
+--------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY i2c_master IS
+ GENERIC(
+ input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
+ bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz
+ PORT(
+ clk : IN STD_LOGIC; --system clock
+ reset_n : IN STD_LOGIC; --active low reset
+ ena : IN STD_LOGIC; --latch in command
+ addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
+ rw : IN STD_LOGIC; --'0' is write, '1' is read
+ data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
+ busy : OUT STD_LOGIC; --indicates transaction in progress
+ data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
+ ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
+ sda : INOUT STD_LOGIC; --serial data output of i2c bus
+ scl : INOUT STD_LOGIC); --serial clock output of i2c bus
+END i2c_master;
+
+ARCHITECTURE logic OF i2c_master IS
+ CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
+ TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
+ SIGNAL state : machine; --state machine
+ SIGNAL data_clk : STD_LOGIC; --data clock for sda
+ SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
+ SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
+ SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
+ SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
+ SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
+ SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
+ SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
+ SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
+ SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
+ SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
+BEGIN
+
+ --generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
+ PROCESS(clk, reset_n)
+ VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
+ BEGIN
+ IF(reset_n = '0') THEN --reset asserted
+ stretch <= '0';
+ count := 0;
+ ELSIF(clk'EVENT AND clk = '1') THEN
+ data_clk_prev <= data_clk; --store previous value of data clock
+ IF(count = divider*4-1) THEN --end of timing cycle
+ count := 0; --reset timer
+ ELSIF(stretch = '0') THEN --clock stretching from slave not detected
+ count := count + 1; --continue clock generation timing
+ END IF;
+ CASE count IS
+ WHEN 0 TO divider-1 => --first 1/4 cycle of clocking
+ scl_clk <= '0';
+ data_clk <= '0';
+ WHEN divider TO divider*2-1 => --second 1/4 cycle of clocking
+ scl_clk <= '0';
+ data_clk <= '1';
+ WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking
+ scl_clk <= '1'; --release scl
+ IF(scl = '0') THEN --detect if slave is stretching clock
+ stretch <= '1';
+ ELSE
+ stretch <= '0';
+ END IF;
+ data_clk <= '1';
+ WHEN OTHERS => --last 1/4 cycle of clocking
+ scl_clk <= '1';
+ data_clk <= '0';
+ END CASE;
+ END IF;
+ END PROCESS;
+
+ --state machine and writing to sda during scl low (data_clk rising edge)
+ PROCESS(clk, reset_n)
+ BEGIN
+ IF(reset_n = '0') THEN --reset asserted
+ state <= ready; --return to initial state
+ busy <= '1'; --indicate not available
+ scl_ena <= '0'; --sets scl high impedance
+ sda_int <= '1'; --sets sda high impedance
+ ack_error <= '0'; --clear acknowledge error flag
+ bit_cnt <= 7; --restarts data bit counter
+ data_rd <= "00000000"; --clear data read port
+ ELSIF(clk'EVENT AND clk = '1') THEN
+ IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
+ CASE state IS
+ WHEN ready => --idle state
+ IF(ena = '1') THEN --transaction requested
+ busy <= '1'; --flag busy
+ addr_rw <= addr & rw; --collect requested slave address and command
+ data_tx <= data_wr; --collect requested data to write
+ state <= start; --go to start bit
+ ELSE --remain idle
+ busy <= '0'; --unflag busy
+ state <= ready; --remain idle
+ END IF;
+ WHEN start => --start bit of transaction
+ busy <= '1'; --resume busy if continuous mode
+ sda_int <= addr_rw(bit_cnt); --set first address bit to bus
+ state <= command; --go to command
+ WHEN command => --address and command byte of transaction
+ IF(bit_cnt = 0) THEN --command transmit finished
+ sda_int <= '1'; --release sda for slave acknowledge
+ bit_cnt <= 7; --reset bit counter for "byte" states
+ state <= slv_ack1; --go to slave acknowledge (command)
+ ELSE --next clock cycle of command state
+ bit_cnt <= bit_cnt - 1; --keep track of transaction bits
+ sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
+ state <= command; --continue with command
+ END IF;
+ WHEN slv_ack1 => --slave acknowledge bit (command)
+ IF(addr_rw(0) = '0') THEN --write command
+ sda_int <= data_tx(bit_cnt); --write first bit of data
+ state <= wr; --go to write byte
+ ELSE --read command
+ sda_int <= '1'; --release sda from incoming data
+ state <= rd; --go to read byte
+ END IF;
+ WHEN wr => --write byte of transaction
+ busy <= '1'; --resume busy if continuous mode
+ IF(bit_cnt = 0) THEN --write byte transmit finished
+ sda_int <= '1'; --release sda for slave acknowledge
+ bit_cnt <= 7; --reset bit counter for "byte" states
+ state <= slv_ack2; --go to slave acknowledge (write)
+ ELSE --next clock cycle of write state
+ bit_cnt <= bit_cnt - 1; --keep track of transaction bits
+ sda_int <= data_tx(bit_cnt-1); --write next bit to bus
+ state <= wr; --continue writing
+ END IF;
+ WHEN rd => --read byte of transaction
+ busy <= '1'; --resume busy if continuous mode
+ IF(bit_cnt = 0) THEN --read byte receive finished
+ IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
+ sda_int <= '0'; --acknowledge the byte has been received
+ ELSE --stopping or continuing with a write
+ sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
+ END IF;
+ bit_cnt <= 7; --reset bit counter for "byte" states
+ data_rd <= data_rx; --output received data
+ state <= mstr_ack; --go to master acknowledge
+ ELSE --next clock cycle of read state
+ bit_cnt <= bit_cnt - 1; --keep track of transaction bits
+ state <= rd; --continue reading
+ END IF;
+ WHEN slv_ack2 => --slave acknowledge bit (write)
+ IF(ena = '1') THEN --continue transaction
+ busy <= '0'; --continue is accepted
+ addr_rw <= addr & rw; --collect requested slave address and command
+ data_tx <= data_wr; --collect requested data to write
+ IF(addr_rw = addr & rw) THEN --continue transaction with another write
+ sda_int <= data_wr(bit_cnt); --write first bit of data
+ state <= wr; --go to write byte
+ ELSE --continue transaction with a read or new slave
+ state <= start; --go to repeated start
+ END IF;
+ ELSE --complete transaction
+ state <= stop; --go to stop bit
+ END IF;
+ WHEN mstr_ack => --master acknowledge bit after a read
+ IF(ena = '1') THEN --continue transaction
+ busy <= '0'; --continue is accepted and data received is available on bus
+ addr_rw <= addr & rw; --collect requested slave address and command
+ data_tx <= data_wr; --collect requested data to write
+ IF(addr_rw = addr & rw) THEN --continue transaction with another read
+ sda_int <= '1'; --release sda from incoming data
+ state <= rd; --go to read byte
+ ELSE --continue transaction with a write or new slave
+ state <= start; --repeated start
+ END IF;
+ ELSE --complete transaction
+ state <= stop; --go to stop bit
+ END IF;
+ WHEN stop => --stop bit of transaction
+ busy <= '0'; --unflag busy
+ state <= ready; --go to idle state
+ END CASE;
+ ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
+ CASE state IS
+ WHEN start =>
+ IF(scl_ena = '0') THEN --starting new transaction
+ scl_ena <= '1'; --enable scl output
+ ack_error <= '0'; --reset acknowledge error output
+ END IF;
+ WHEN slv_ack1 => --receiving slave acknowledge (command)
+ IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
+ ack_error <= '1'; --set error output if no-acknowledge
+ END IF;
+ WHEN rd => --receiving slave data
+ data_rx(bit_cnt) <= sda; --receive current slave data bit
+ WHEN slv_ack2 => --receiving slave acknowledge (write)
+ IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
+ ack_error <= '1'; --set error output if no-acknowledge
+ END IF;
+ WHEN stop =>
+ scl_ena <= '0'; --disable scl
+ WHEN OTHERS =>
+ NULL;
+ END CASE;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ --set sda output
+ WITH state SELECT
+ sda_ena_n <= data_clk_prev WHEN start, --generate start condition
+ NOT data_clk_prev WHEN stop, --generate stop condition
+ sda_int WHEN OTHERS; --set to internal sda signal
+
+ --set scl and sda outputs
+ scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
+ sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
+
+END logic;
+
+
diff --git a/example_csram_oled/memorymodule.vhd b/example_csram_oled/memorymodule.vhd
new file mode 100755
index 0000000..4dbac24
--- /dev/null
+++ b/example_csram_oled/memorymodule.vhd
@@ -0,0 +1,184 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:11:00 11/28/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/memorymodule/memorymodule.vhd
+-- Project Name: memorymodule
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_memory_content.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity memorymodule is
+Port (
+i_clock : in std_logic;
+i_enable : in std_logic;
+i_write : in std_logic;
+i_read : in std_logic;
+o_busy : out std_logic;
+i_MemAdr : in MemoryAddress;
+i_MemDB : in MemoryDataByte;
+o_MemDB : out MemoryDataByte;
+io_MemOE : out std_logic;
+io_MemWR : out std_logic;
+io_RamAdv : out std_logic;
+io_RamCS : out std_logic;
+io_RamLB : out std_logic;
+io_RamCRE : out std_logic;
+io_RamUB : out std_logic;
+io_RamClk : out std_logic;
+io_MemAdr : out MemoryAddress;
+io_MemDB : inout MemoryDataByte
+);
+end memorymodule;
+
+architecture Behavioral of memorymodule is
+
+ type state is (
+ idle,
+ start,
+ write_setup,
+ read_setup,
+ write_enable,
+ wait1,
+ write_disable,
+ stop,
+ read1,
+ wait2
+ );
+ signal cstate : state;
+
+ signal MemOE : std_logic;
+ signal MemWR : std_logic;
+ signal RamAdv : std_logic;
+ signal RamCS : std_logic;
+ signal RamLB : std_logic;
+ signal RamCRE : std_logic;
+ signal RamUB : std_logic;
+ signal RamClk : std_logic;
+ signal MemAdr : MemoryAddress;
+ signal MemDB : MemoryDataByte;
+
+begin
+
+ io_MemOE <= MemOE;
+ io_MemWR <= MemWR;
+ io_RamAdv <= RamAdv;
+ io_RamCS <= RamCS;
+ io_RamLB <= RamLB;
+ io_RamCRE <= RamCRE;
+ io_RamUB <= RamUB;
+ io_RamClk <= RamClk;
+ io_MemAdr <= MemAdr;
+
+ RamLB <= '0';
+ RamUB <= '0';
+ RamCRE <= '0';
+ RamAdv <= '0';
+ RamClk <= '0';
+
+ MemAdr <= i_MemAdr when (RamCS = '0' and (MemWR = '0' or MemOE = '0')) else (others => 'Z');
+ o_MemDB <= io_MemDB when (cstate = idle) else (others => 'Z');
+ io_MemDB <= i_MemDB when (RamCS = '0' and MemWR = '0') else (others => 'Z');
+
+ p0 : process (i_clock) is
+ constant cw : integer := 6;
+ variable w : integer range 0 to cw := 0;
+ variable t : std_logic_vector(G_MemoryData-1 downto 0);
+ variable tz : std_logic_vector(G_MemoryData-1 downto 0) := (others => 'Z');
+ begin
+ if (rising_edge(i_clock)) then
+ if (w > 0) then
+ w := w - 1;
+ end if;
+ case cstate is
+ when idle =>
+ if (i_enable = '1') then
+ cstate <= start; -- XXX check CSb
+ else
+ cstate <= idle;
+ end if;
+ when start =>
+ if (i_write = '1') then
+ cstate <= write_setup;
+ elsif (i_read = '1') then
+ cstate <= read_setup;
+ else
+ cstate <= start;
+ end if;
+ RamCS <= '1';
+ MemWR <= '1';
+ MemOE <= '1';
+ when write_setup =>
+ if (w = 0) then
+ cstate <= write_enable;
+ o_busy <= '1';
+ MemOE <= '1';
+ else
+ cstate <= write_setup;
+ end if;
+ when write_enable =>
+ cstate <= wait1;
+ MemWR <= '0';
+ RamCS <= '0';
+ w := cw;
+ when wait1 =>
+ if (w = 0) then
+ cstate <= write_disable;
+ else
+ cstate <= wait1;
+ end if;
+ when write_disable =>
+ cstate <= stop;
+ RamCS <= '1';
+ MemWR <= '1';
+ when read_setup =>
+ if (w = 0) then
+ cstate <= read1;
+ RamCS <= '0';
+ MemOE <= '0';
+ o_busy <= '1';
+ else
+ cstate <= read_setup;
+ end if;
+ when read1 =>
+ cstate <= wait2;
+ w := cw;
+ when wait2 =>
+ if (w = 0) then
+ cstate <= stop;
+ else
+ cstate <= wait2;
+ end if;
+ when stop =>
+ cstate <= idle;
+ o_busy <= '0';
+ RamCS <= '1';
+ MemOE <= '1';
+ when others => null;
+ end case;
+ end if;
+ end process p0;
+
+end Behavioral;
diff --git a/example_csram_oled/oled_display.vhd b/example_csram_oled/oled_display.vhd
new file mode 100755
index 0000000..c42b1de
--- /dev/null
+++ b/example_csram_oled/oled_display.vhd
@@ -0,0 +1,361 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:47:49 08/21/2020
+-- Design Name:
+-- Module Name: test_oled - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity oled_display is
+generic
+(
+GLOBAL_CLK : integer := 50_000_000;
+I2C_CLK : integer := 100_000;
+WIDTH_O : integer := 128;
+HEIGHT_O : integer := 32;
+W_BITS : integer := 7;
+H_BITS : integer := 5;
+BYTE_SIZE : integer := 8);
+port
+(
+signal i_clk : in std_logic;
+signal i_rst : in std_logic;
+signal i_clear : in std_logic;
+signal i_draw : in std_logic;
+signal i_x : in std_logic_vector(W_BITS-1 downto 0);
+signal i_y : in std_logic_vector(H_BITS-1 downto 0);
+signal i_byte : in std_logic_vector(BYTE_SIZE-1 downto 0);
+signal i_all_pixels : in std_logic;
+signal o_busy : out std_logic;
+signal o_display_initialize : inout std_logic;
+signal io_sda,io_scl : inout std_logic);
+end oled_display;
+
+architecture Behavioral of oled_display is
+
+constant WIDTH : integer := 128; -- XXX
+constant HEIGHT : integer := 4; -- XXX
+
+constant OLED_PAGES_ALL : integer := WIDTH * HEIGHT;
+constant OLED_DATA : integer := to_integer(unsigned'(x"40"));
+constant OLED_COMMAND : integer := to_integer(unsigned'(x"00")); -- 00,80
+constant COUNTER_WAIT1 : integer := 1;
+
+constant NI_INIT : natural := 26;
+type A_INIT is array (0 to NI_INIT-1) of std_logic_vector(BYTE_SIZE-1 downto 0);
+signal init_display : A_INIT :=
+(
+ x"AE" -- display off
+,x"D5",x"80" -- setdisplayclockdiv
+,x"A8",x"1F" -- 00-0f/10-1f - Set Lower Column Start Address for Page Addressing Mode
+,x"D3",x"00" -- display offset
+,x"40" -- set start line
+,x"8D",x"14" -- chargepump
+,x"20",x"00" -- Set Memory Addressing Mode
+,x"A1",x"C8" -- A0/A1,C0/C8 - start from specify four display corner - a0|a1 - segremap , c0|c8 - comscandec
+,x"DA",x"02" -- setcompins
+,x"81",x"8F" -- contrast
+,x"D9",x"F1" -- precharge
+,x"DB",x"40" -- setvcomdetect
+,x"A4" -- displayon resume
+,x"A6" -- normal display
+,x"2E" -- scroll off
+,x"AF" -- display on
+);
+
+constant NI_SET_COORDINATION : natural := 6;
+type A_SET_COORDINATION is array (0 to NI_SET_COORDINATION-1) of std_logic_vector(BYTE_SIZE-1 downto 0);
+signal set_coordination_00 : A_SET_COORDINATION :=
+(x"21",x"00",std_logic_vector(to_unsigned(WIDTH-1,BYTE_SIZE))
+,x"22",x"00",std_logic_vector(to_unsigned(HEIGHT-1,BYTE_SIZE)));
+
+COMPONENT i2c IS
+GENERIC(
+ input_clk : INTEGER; --input clock speed from user logic in Hz
+ bus_clk : INTEGER --speed the i2c bus (scl) will run at in Hz
+);
+PORT(
+ clk : IN STD_LOGIC; --system clock
+ reset_n : IN STD_LOGIC; --active low reset
+ ena : IN STD_LOGIC; --latch in command
+ addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
+ rw : IN STD_LOGIC; --'0' is write, '1' is read
+ data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
+ busy : OUT STD_LOGIC; --indicates transaction in progress
+ data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
+ ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
+ sda : INOUT STD_LOGIC; --serial data output of i2c bus
+ scl : INOUT STD_LOGIC); --serial clock output of i2c bus
+END component i2c;
+for all : i2c use entity WORK.i2c_master(logic);
+
+type state is
+(
+ idle,
+ start, -- initialize oled
+ wait0,
+ set_address_1, -- set begin point 0,0
+ wait1, -- wait after initialize
+ send_character, -- send the some data in loop
+ wait2, -- disable i2c and wait between transition coordination
+ wait3,
+ set_coordinations,
+ set_address_2, -- set begin point 0,0
+ clear_display_state, -- clear display
+ stop -- when index=counter, i2c disable
+);
+
+signal c_state : state := start;
+SIGNAL i2c_ena : STD_LOGIC; --i2c enable signal
+SIGNAL i2c_addr : STD_LOGIC_VECTOR(6 DOWNTO 0); --i2c address signal
+SIGNAL i2c_rw : STD_LOGIC; --i2c read/write command signal
+SIGNAL i2c_data_wr : STD_LOGIC_VECTOR(7 DOWNTO 0); --i2c write data
+SIGNAL i2c_busy : STD_LOGIC; --i2c busy signal
+SIGNAL i2c_reset : STD_LOGIC; --i2c busy signal
+SIGNAL busy_prev : STD_LOGIC; --previous value of i2c busy signal
+SIGNAL busy_cnt : INTEGER := 0; -- for i2c, count the clk tick when i2c_busy=1
+
+signal counter : integer range 0 to COUNTER_WAIT1 := COUNTER_WAIT1;
+signal coord_prev_x : std_logic_vector(W_BITS-1 downto 0) := (others => '0');
+signal coord_prev_y : std_logic_vector(H_BITS-1 downto 0) := (others => '0');
+
+begin
+
+c0 : i2c
+GENERIC MAP
+(
+ input_clk => GLOBAL_CLK,
+ bus_clk => I2C_CLK
+)
+PORT MAP
+(
+ clk => i_clk,
+ reset_n => i2c_reset,
+ ena => i2c_ena,
+ addr => i2c_addr,
+ rw => i2c_rw,
+ data_wr => i2c_data_wr,
+ busy => i2c_busy,
+ data_rd => open,
+ ack_error => open,
+ sda => io_sda,
+ scl => io_scl
+);
+
+p0 : process (i_clk,i_rst) is
+begin
+ if (i_rst = '1') then
+ c_state <= idle;
+ elsif (rising_edge(i_clk)) then
+ if (i_all_pixels = '1') then
+ c_state <= stop;
+ end if;
+ if (counter > 0) then
+ counter <= counter - 1;
+ end if;
+ case c_state is
+ when idle =>
+ busy_cnt <= 0;
+ if (i_all_pixels = '1') then
+ c_state <= idle;
+ else
+ if (o_display_initialize = '1') then
+ c_state <= wait0;
+ else
+ c_state <= start;
+ end if;
+ end if;
+ when start =>
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_reset <= '1';
+ i2c_ena <= '1'; -- we are busy
+ i2c_addr <= "0111100"; -- address 3C 3D 78 ; 0111100 0111101 1111000
+ i2c_rw <= '0';
+ i2c_data_wr <= std_logic_vector(to_unsigned(OLED_COMMAND,BYTE_SIZE));
+ when 1 to NI_INIT =>
+ i2c_data_wr <= init_display(busy_cnt-1); -- command
+ when NI_INIT+1 =>
+ i2c_ena <= '0';
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ c_state <= set_address_2;
+ end if;
+ when others => null;
+ end case;
+ when set_address_2 =>
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ i2c_addr <= "0111100"; -- address 3C 3D 78 ; 0111100 0111101 1111000
+ i2c_rw <= '0';
+ i2c_data_wr <= std_logic_vector(to_unsigned(OLED_COMMAND,BYTE_SIZE));
+ when 1 to NI_SET_COORDINATION =>
+ i2c_data_wr <= set_coordination_00(busy_cnt-1); -- command
+ when NI_SET_COORDINATION+1 =>
+ i2c_ena <= '0';
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ c_state <= clear_display_state;
+ end if;
+ when others => null;
+ end case;
+ when clear_display_state =>
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ i2c_addr <= "0111100"; -- address 3C 3D 78 ; 0111100 0111101 1111000
+ i2c_rw <= '0';
+ i2c_data_wr <= std_logic_vector(to_unsigned(OLED_DATA,BYTE_SIZE));
+ when 1 to OLED_PAGES_ALL => -- XXX
+ i2c_data_wr <= x"00"; -- command - FF/allpixels,00/blank,F0/zebra
+ when OLED_PAGES_ALL+1 => -- XXX
+ i2c_ena <= '0';
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ c_state <= wait0;
+ end if;
+ when others => null;
+ end case;
+ when wait0 =>
+ c_state <= set_address_1;
+ when set_address_1 =>
+ --coord_prev_x <= std_logic_vector(to_unsigned(0,W_BITS));
+ --coord_prev_y <= std_logic_vector(to_unsigned(0,H_BITS));
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ i2c_addr <= "0111100"; -- address 3C 3D 78 ; 0111100 0111101 1111000
+ i2c_rw <= '0';
+ i2c_data_wr <= std_logic_vector(to_unsigned(OLED_COMMAND,BYTE_SIZE));
+ when 1 to NI_SET_COORDINATION =>
+ i2c_data_wr <= set_coordination_00(busy_cnt-1); -- command
+ when NI_SET_COORDINATION+1 =>
+ i2c_ena <= '0';
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ c_state <= wait1;
+ o_display_initialize <= '1';
+ end if;
+ when others => null;
+ end case;
+ when wait1 =>
+ if (i_draw = '1') then
+ c_state <= send_character;
+ else
+ c_state <= wait1;
+ end if;
+ when send_character =>
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ i2c_addr <= "0111100"; -- address 3C 3D 78 ; 0111100 0111101 1111000
+ i2c_rw <= '0';
+ i2c_data_wr <= std_logic_vector(to_unsigned(OLED_DATA,BYTE_SIZE));
+ o_busy <= '1';
+ when 1 =>
+ i2c_data_wr <= i_byte;
+ when 2 =>
+ i2c_ena <= '0';
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ c_state <= wait2;
+ coord_prev_x <= i_x;
+ coord_prev_y <= i_y;
+ o_busy <= '0';
+ end if;
+ when others => null;
+ end case;
+ when wait2 =>
+ i2c_ena <= '0';
+ o_busy <= '0';
+ busy_cnt <= 0;
+
+ if (counter = 0) then
+ --if (coord_prev_y /= i_y) then
+ --c_state <= wait3;
+ --else
+ if (coord_prev_x /= i_x) then
+ c_state <= send_character;
+ end if;
+ --end if;
+ end if;
+ when wait3 =>
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ i2c_addr <= "0111100"; -- address 3C 3D 78 ; 0111100 0111101 1111000
+ i2c_rw <= '0';
+ i2c_data_wr <= std_logic_vector(to_unsigned(OLED_COMMAND,BYTE_SIZE));
+ o_busy <= '1';
+ when 1 =>
+ i2c_data_wr <= x"21";
+ when 2 =>
+ i2c_data_wr <= std_logic_vector(to_unsigned(0,BYTE_SIZE-W_BITS))&i_x; -- XXX
+ when 3 =>
+ i2c_data_wr <= std_logic_vector(to_unsigned(WIDTH-1,BYTE_SIZE));
+ when 4 =>
+ i2c_data_wr <= x"22";
+ when 5 =>
+ i2c_data_wr <= std_logic_vector(to_unsigned(0,BYTE_SIZE-H_BITS))&i_y; -- XXX
+ when 6 =>
+ i2c_data_wr <= std_logic_vector(to_unsigned(HEIGHT-1,BYTE_SIZE));
+ when 7 =>
+ i2c_ena <= '0';
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ counter <= COUNTER_WAIT1-1;
+ c_state <= send_character;
+ o_busy <= '0';
+ end if;
+ when others => null;
+ end case;
+ when stop =>
+ i2c_ena <= '0';
+ c_state <= idle;
+ when others => null;
+ end case;
+ end if;
+end process p0;
+
+end Behavioral;
+
diff --git a/example_csram_oled/p_memory_content.vhd b/example_csram_oled/p_memory_content.vhd
new file mode 100755
index 0000000..02c58de
--- /dev/null
+++ b/example_csram_oled/p_memory_content.vhd
@@ -0,0 +1,179 @@
+--
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+--
+-- To use any of the example code shown below, uncomment the lines and modify as necessary
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package p_memory_content is
+
+ constant G_BOARD_CLOCK : integer := 50_000_000;
+ constant G_BUS_CLOCK : integer := 100_000;
+ constant G_ClockDivider : integer := 10000000;
+ constant G_MemoryAddress : integer := 24;
+ constant G_MemoryData : integer := 16;
+ subtype MemoryAddress is std_logic_vector(G_MemoryAddress-1 downto 1);
+ subtype MemoryAddressAll is std_logic_vector(G_MemoryAddress-1 downto 0);
+ subtype MemoryDataByte is std_logic_vector(G_MemoryData-1 downto 0);
+ constant G_HalfHex : integer := 4;
+ constant G_FullHex : integer := G_HalfHex*2;
+ constant ROWS : integer := 128;
+ constant ROWS_BITS : integer := 7;
+ constant COLS_PIXEL : integer := 32;
+ constant COLS_PIXEL_BITS : integer := 5;
+ constant COLS_BLOCK : integer := 4;
+ constant COLS_BLOCK_BITS : integer := 2;
+ constant BYTE_BITS : integer := 8;
+ constant WORD_BITS : integer := COLS_BLOCK*BYTE_BITS;
+ constant G_LCDSegment : integer := 7;
+ constant G_LCDAnode : integer := 4;
+ constant G_LCDClockDivider : integer := 200;
+ constant G_Button : integer := 4;
+ constant G_Led : integer := 8;
+ constant BYTE_SIZE : integer := 8;
+ type LCDHex is array(G_LCDAnode-1 downto 0) of std_logic_vector(G_HalfHex-1 downto 0);
+ subtype WORD is std_logic_vector(0 to WORD_BITS-1);
+ type MEMORY is array(0 to ROWS-1) of WORD;
+
+ constant memory_content : MEMORY :=
+ ( -- f 0f 0
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101"),
+ ("10101010101010101111111111111111"),
+ ("11111111111111110101010101010101")
+
+ );
+
+end p_memory_content;
+
+package body p_memory_content is
+end p_memory_content;
diff --git a/example_csram_oled/tb_memorymodule.vhd b/example_csram_oled/tb_memorymodule.vhd
new file mode 100755
index 0000000..e5fbf05
--- /dev/null
+++ b/example_csram_oled/tb_memorymodule.vhd
@@ -0,0 +1,161 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:35:05 11/30/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/memorymodule/tb_memorymodule.vhd
+-- Project Name: memorymodule
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: memorymodule
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE WORK.p_memory_content.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_memorymodule IS
+END tb_memorymodule;
+
+ARCHITECTURE behavior OF tb_memorymodule IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT memorymodule
+ PORT(
+ i_clock : IN std_logic;
+ i_enable : IN std_logic;
+ i_write : IN std_logic;
+ i_read : IN std_logic;
+ i_MemAdr : IN std_logic_vector(23 downto 0);
+ i_MemDB : IN std_logic_vector(15 downto 0);
+ o_MemDB : OUT std_logic_vector(15 downto 0);
+ io_MemOE : OUT std_logic;
+ io_MemWR : OUT std_logic;
+ io_RamAdv : OUT std_logic;
+ io_RamCS : OUT std_logic;
+ io_RamLB : OUT std_logic;
+ io_RamUB : OUT std_logic;
+ io_MemAdr : INOUT std_logic_vector(23 downto 0);
+ io_MemDB : INOUT std_logic_vector(15 downto 0)
+ );
+ END COMPONENT;
+
+ --Inputs
+ signal i_clock : std_logic := '0';
+ signal i_enable : std_logic := '0';
+ signal i_write : std_logic := '0';
+ signal i_read : std_logic := '0';
+ signal i_MemAdr : std_logic_vector(23 downto 0) := (others => '0');
+ signal i_MemDB : std_logic_vector(15 downto 0) := (others => '0');
+
+ --BiDirs
+ signal io_MemDB : std_logic_vector(15 downto 0);
+
+ --Outputs
+ signal o_MemDB : std_logic_vector(15 downto 0);
+ signal io_MemOE : std_logic;
+ signal io_MemWR : std_logic;
+ signal io_RamAdv : std_logic;
+ signal io_RamCS : std_logic;
+ signal io_RamLB : std_logic;
+ signal io_RamUB : std_logic;
+ signal io_MemAdr : std_logic_vector(23 downto 0);
+
+ -- Clock period definitions
+ constant i_clock_period : time := (1_000_000_000 / G_BOARD_CLOCK) * 1 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: memorymodule PORT MAP (
+ i_clock => i_clock,
+ i_enable => i_enable,
+ i_write => i_write,
+ i_read => i_read,
+ i_MemAdr => i_MemAdr,
+ i_MemDB => i_MemDB,
+ o_MemDB => o_MemDB,
+ io_MemOE => io_MemOE,
+ io_MemWR => io_MemWR,
+ io_RamAdv => io_RamAdv,
+ io_RamCS => io_RamCS,
+ io_RamLB => io_RamLB,
+ io_RamUB => io_RamUB,
+ io_MemAdr => io_MemAdr,
+ io_MemDB => io_MemDB
+ );
+
+ -- Clock process definitions
+ i_clock_process :process
+ begin
+ i_clock <= '0';
+ wait for i_clock_period/2;
+ i_clock <= '1';
+ wait for i_clock_period/2;
+ end process;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+ -- insert stimulus here
+ -- write
+ wait for i_clock_period*10;
+ i_enable <= '1';
+ wait for i_clock_period;
+ i_write <= '1';
+ wait for i_clock_period;
+ i_MemAdr <= x"000001";
+ i_MemDB <= x"1234";
+ wait for i_clock_period;
+ i_write <= '0';
+ wait for i_clock_period;
+ i_enable <= '0';
+ wait for i_clock_period*10;
+ i_enable <= '1';
+ wait for i_clock_period;
+ i_write <= '1';
+ wait for i_clock_period;
+ i_MemAdr <= x"000002";
+ i_MemDB <= x"2222";
+ wait for i_clock_period;
+ i_write <= '0';
+ wait for i_clock_period;
+ i_enable <= '0';
+ -- read
+ wait for i_clock_period*10;
+ i_enable <= '1';
+ wait for i_clock_period;
+ i_read <= '1';
+ wait for i_clock_period;
+ i_MemAdr <= x"000001";
+ --i_MemDB <= x"1234";
+ wait for i_clock_period;
+ i_read <= '0';
+ wait for i_clock_period;
+ i_enable <= '0';
+ wait;
+ end process;
+
+END;
diff --git a/example_csram_oled/tb_top.vhd b/example_csram_oled/tb_top.vhd
new file mode 100755
index 0000000..6f6319a
--- /dev/null
+++ b/example_csram_oled/tb_top.vhd
@@ -0,0 +1,121 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:37:20 12/11/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/test_oled_mem/tb_top.vhd
+-- Project Name: test_oled_mem
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE WORK.p_memory_content.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_top IS
+END tb_top;
+
+ARCHITECTURE behavior OF tb_top IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT top
+ PORT(
+ clk : IN std_logic;
+ sda : INOUT std_logic;
+ scl : INOUT std_logic;
+ io_MemOE : INOUT std_logic;
+ io_MemWR : INOUT std_logic;
+ io_RamAdv : INOUT std_logic;
+ io_RamCS : INOUT std_logic;
+ io_RamCRE : INOUT std_logic;
+ io_RamLB : INOUT std_logic;
+ io_RamUB : INOUT std_logic;
+ io_RamWait : INOUT std_logic;
+ io_RamClk : INOUT std_logic;
+ io_MemAdr : INOUT MemoryAddress;
+ io_MemDB : INOUT MemoryDataByte
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal clk : std_logic := '0';
+
+ --BiDirs
+ signal sda : std_logic;
+ signal scl : std_logic;
+ signal io_MemOE : std_logic;
+ signal io_MemWR : std_logic;
+ signal io_RamAdv : std_logic;
+ signal io_RamCS : std_logic;
+ signal io_RamCRE : std_logic;
+ signal io_RamLB : std_logic;
+ signal io_RamUB : std_logic;
+ signal io_RamWait : std_logic;
+ signal io_RamClk : std_logic;
+ signal io_MemAdr : MemoryAddress;
+ signal io_MemDB : MemoryDataByte;
+
+ -- Clock period definitions
+ constant clk_period : time := 20 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: top PORT MAP (
+ clk => clk,
+ sda => sda,
+ scl => scl,
+ io_MemOE => io_MemOE,
+ io_MemWR => io_MemWR,
+ io_RamAdv => io_RamAdv,
+ io_RamCS => io_RamCS,
+ io_RamCRE => io_RamCRE,
+ io_RamLB => io_RamLB,
+ io_RamUB => io_RamUB,
+ io_RamWait => io_RamWait,
+ io_RamClk => io_RamClk,
+ io_MemAdr => io_MemAdr,
+ io_MemDB => io_MemDB
+ );
+
+ -- Clock process definitions
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ -- insert stimulus here
+ wait;
+ end process;
+
+END;
diff --git a/example_csram_oled/top.vhd b/example_csram_oled/top.vhd
new file mode 100755
index 0000000..5f18099
--- /dev/null
+++ b/example_csram_oled/top.vhd
@@ -0,0 +1,581 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:11:54 09/04/2020
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_memory_content.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top is
+port(
+signal clk : in std_logic;
+signal sda,scl : inout std_logic;
+signal io_MemOE : inout std_logic;
+signal io_MemWR : inout std_logic;
+signal io_RamAdv : inout std_logic;
+signal io_RamCS : inout std_logic;
+signal io_RamCRE : inout std_logic;
+signal io_RamLB : inout std_logic;
+signal io_RamUB : inout std_logic;
+signal io_RamWait : inout std_logic;
+signal io_RamClk : inout std_logic;
+signal io_MemAdr : inout MemoryAddress;
+signal io_MemDB : inout MemoryDataByte;
+signal io_FlashCS : out std_logic
+);
+end top;
+
+architecture Behavioral of top is
+
+component oled_display is
+generic(
+GLOBAL_CLK : integer;
+I2C_CLK : integer;
+WIDTH_O : integer;
+HEIGHT_O : integer;
+W_BITS : integer;
+H_BITS : integer;
+BYTE_SIZE : integer);
+port(
+signal i_clk : in std_logic;
+signal i_rst : in std_logic;
+signal i_clear : in std_logic;
+signal i_draw : in std_logic;
+signal i_x : in std_logic_vector(W_BITS-1 downto 0);
+signal i_y : in std_logic_vector(H_BITS-1 downto 0);
+signal i_byte : in std_logic_vector(BYTE_SIZE-1 downto 0);
+signal i_all_pixels : in std_logic;
+signal o_busy : out std_logic;
+signal o_display_initialize : inout std_logic;
+signal io_sda,io_scl : inout std_logic);
+end component oled_display;
+for all : oled_display use entity WORK.oled_display(Behavioral);
+
+component clock_divider is
+Port(
+i_clk : in STD_LOGIC;
+i_board_clock : in INTEGER;
+i_divider : in INTEGER;
+o_clk : out STD_LOGIC
+);
+end component clock_divider;
+for all : clock_divider use entity WORK.clock_divider(Behavioral);
+
+component memorymodule is
+Port (
+i_clock : in std_logic;
+i_enable : in std_logic;
+i_write : in std_logic;
+i_read : in std_logic;
+o_busy : out std_logic;
+i_MemAdr : in MemoryAddress;
+i_MemDB : in MemoryDataByte;
+o_MemDB : out MemoryDataByte;
+io_MemOE : out std_logic;
+io_MemWR : out std_logic;
+io_RamAdv : out std_logic;
+io_RamCS : out std_logic;
+io_RamLB : out std_logic;
+io_RamUB : out std_logic;
+io_RamCRE : out std_logic;
+io_RamClk : out std_logic;
+io_MemAdr : out MemoryAddress;
+io_MemDB : inout MemoryDataByte
+);
+end component memorymodule;
+for all : memorymodule use entity WORK.memorymodule(Behavioral);
+
+signal CD : integer := G_ClockDivider;
+signal clk_1s : std_logic;
+signal btn_1,btn_2 : std_logic;
+signal draw : std_logic;
+signal i_x : std_logic_vector(ROWS_BITS-1 downto 0);
+signal i_y : std_logic_vector(COLS_BLOCK_BITS-1 downto 0);
+signal all_pixels : std_logic;
+signal o_disbusy : std_logic;
+signal display_initialize : std_logic;
+signal display_byte : std_logic_vector(BYTE_SIZE-1 downto 0);
+signal i_enable : std_logic;
+signal i_write : std_logic;
+signal i_read : std_logic;
+signal o_membusy : std_logic;
+signal i_MemAdr : MemoryAddress;
+signal i_MemDB : MemoryDataByte;
+signal o_MemDB : MemoryDataByte;
+signal diby : std_logic_vector(BYTE_SIZE-1 downto 0);
+
+signal MemOE : std_logic;
+signal MemWR : std_logic;
+signal RamAdv : std_logic;
+signal RamCS : std_logic;
+signal RamLB : std_logic;
+signal RamUB : std_logic;
+signal RamCRE : std_logic;
+signal RamClk : std_logic;
+signal MemAdr : MemoryAddress;
+signal MemDB : MemoryDataByte;
+
+type state is
+(
+wait0,
+wa0_em,wa0_sa,wa0_ew,wa0_dw,wa0_dm,wa0_wait,
+wa1_em,wa1_sa,wa1_ew,wa1_dw,wa1_dm,wa1_wait,
+wa2_em,wa2_sa,wa2_ew,wa2_dw,wa2_dm,wa2_wait,
+wa3_em,wa3_sa,wa3_ew,wa3_dw,wa3_dm,wa3_wait,
+ed,
+da0_em,da0_er,da0_sa,da0_dr,da0_dm,da0_wait,da0_bfh,da0_fh,da0_waitfh,da0_bsh,da0_sh,da0_waitsh,
+da1_em,da1_er,da1_sa,da1_dr,da1_dm,da1_wait,da1_bfh,da1_fh,da1_waitfh,da1_bsh,da1_sh,da1_waitsh,
+da2_em,da2_er,da2_sa,da2_dr,da2_dm,da2_wait,da2_bfh,da2_fh,da2_waitfh,da2_bsh,da2_sh,da2_waitsh,
+da3_em,da3_er,da3_sa,da3_dr,da3_dm,da3_wait,da3_bfh,da3_fh,da3_waitfh,da3_bsh,da3_sh,da3_waitsh,
+dd
+);
+signal cstate : state;
+
+signal a0 : MemoryAddressAll := x"002040";
+signal a1 : MemoryAddressAll := x"003050";
+signal a2 : MemoryAddressAll := x"004060";
+signal a3 : MemoryAddressAll := x"005070";
+signal d0 : MemoryDataByte := x"fff0";
+signal d1 : MemoryDataByte := x"0ff0";
+signal d2 : MemoryDataByte := x"0ff0";
+signal d3 : MemoryDataByte := x"0fff";
+
+begin
+
+io_MemOE <= MemOE;
+io_MemWR <= MemWR;
+io_RamAdv <= RamAdv;
+io_RamCS <= RamCS;
+io_RamLB <= RamLB;
+io_RamUB <= RamUB;
+io_RamCRE <= RamCRE;
+io_RamClk <= RamClk;
+io_MemAdr <= MemAdr;
+io_MemDB <= MemDB;
+
+io_FlashCS <= '1'; -- flash is always off
+
+display_byte <= diby;
+
+clk_div : clock_divider
+port map (
+ i_clk => clk,
+ i_board_clock => G_BOARD_CLOCK,
+ i_divider => CD,
+ o_clk => clk_1s
+);
+
+c0 : oled_display
+generic map (
+ GLOBAL_CLK => G_BOARD_CLOCK,
+ I2C_CLK => G_BUS_CLOCK,
+ WIDTH_O => ROWS,
+ HEIGHT_O => COLS_BLOCK,
+ W_BITS => ROWS_BITS,
+ H_BITS => COLS_BLOCK_BITS,
+ BYTE_SIZE => BYTE_BITS)
+port map (
+ i_clk => clk,
+ i_rst => btn_1,
+ i_clear => btn_2,
+ i_draw => draw,
+ i_x => i_x,
+ i_y => i_y,
+ i_byte => display_byte,
+ i_all_pixels => all_pixels,
+ o_busy => o_disbusy,
+ o_display_initialize => display_initialize,
+ io_sda => sda,
+ io_scl => scl
+);
+
+mm : memorymodule PORT MAP (
+ i_clock => clk_1s,
+ i_enable => i_enable,
+ i_write => i_write,
+ i_read => i_read,
+ o_busy => o_membusy,
+ i_MemAdr => i_MemAdr,
+ i_MemDB => i_MemDB,
+ o_MemDB => o_MemDB,
+ io_MemOE => MemOE,
+ io_MemWR => MemWR,
+ io_RamAdv => RamAdv,
+ io_RamCS => RamCS,
+ io_RamLB => RamLB,
+ io_RamUB => RamUB,
+ io_RamCRE => RamCRE,
+ io_RamClk => RamClk,
+ io_MemAdr => MemAdr,
+ io_MemDB => MemDB
+);
+
+p0 : process (clk_1s) is
+ constant W : integer := 5000;
+ variable w1 : integer := W;
+begin
+ if (rising_edge(clk_1s)) then
+ if (w1 > 0) then
+ w1 := w1 - 1;
+ end if;
+ case cstate is
+ when wait0 =>
+ if (display_initialize='1') then
+ i_x <= std_logic_vector(to_unsigned(0,ROWS_BITS));
+ i_y <= std_logic_vector(to_unsigned(0,COLS_BLOCK_BITS));
+ cstate <= wa0_em;
+ end if;
+
+ when wa0_em =>
+ cstate <= wa0_ew;
+ i_enable <= '1';
+ when wa0_ew =>
+ cstate <= wa0_sa;
+ i_write <= '1';
+ when wa0_sa =>
+ cstate <= wa0_dw;
+ i_MemAdr <= a0(G_MemoryAddress-1 downto 1);
+ i_MemDB <= d0;
+ when wa0_dw =>
+ cstate <= wa0_dm;
+ i_write <= '0';
+ when wa0_dm =>
+ cstate <= wa0_wait;
+ i_enable <= '0';
+ when wa0_wait =>
+ if (o_membusy='1') then
+ cstate <= wa0_wait;
+ else
+ cstate <= wa1_em;
+ end if;
+
+ when wa1_em =>
+ cstate <= wa1_ew;
+ i_enable <= '1';
+ when wa1_ew =>
+ cstate <= wa1_sa;
+ i_write <= '1';
+ when wa1_sa =>
+ cstate <= wa1_dw;
+ i_MemAdr <= a1(G_MemoryAddress-1 downto 1);
+ i_MemDB <= d1;
+ when wa1_dw =>
+ cstate <= wa1_dm;
+ i_write <= '0';
+ when wa1_dm =>
+ cstate <= wa1_wait;
+ i_enable <= '0';
+ when wa1_wait =>
+ if (o_membusy='1') then
+ cstate <= wa1_wait;
+ else
+ cstate <= wa2_em;
+ end if;
+
+ when wa2_em =>
+ cstate <= wa2_ew;
+ i_enable <= '1';
+ when wa2_ew =>
+ cstate <= wa2_sa;
+ i_write <= '1';
+ when wa2_sa =>
+ cstate <= wa2_dw;
+ i_MemAdr <= a2(G_MemoryAddress-1 downto 1);
+ i_MemDB <= d2;
+ when wa2_dw =>
+ cstate <= wa2_dm;
+ i_write <= '0';
+ when wa2_dm =>
+ cstate <= wa2_wait;
+ i_enable <= '0';
+ when wa2_wait =>
+ if (o_membusy='1') then
+ cstate <= wa2_wait;
+ else
+ cstate <= wa3_em;
+ end if;
+
+ when wa3_em =>
+ cstate <= wa3_ew;
+ i_enable <= '1';
+ when wa3_ew =>
+ cstate <= wa3_sa;
+ i_write <= '1';
+ when wa3_sa =>
+ cstate <= wa3_dw;
+ i_MemAdr <= a3(G_MemoryAddress-1 downto 1);
+ i_MemDB <= d3;
+ when wa3_dw =>
+ cstate <= wa3_dm;
+ i_write <= '0';
+ when wa3_dm =>
+ cstate <= wa3_wait;
+ i_enable <= '0';
+ when wa3_wait =>
+ if (o_membusy='1') then
+ cstate <= wa3_wait;
+ else
+ cstate <= ed;
+ w1 := W;
+ end if;
+
+ when ed =>
+ if (w1 = 0) then
+ cstate <= da0_em;
+ all_pixels <= '0';
+ draw <= '1';
+ else
+ cstate <= ed;
+ end if;
+
+ when da0_em =>
+ cstate <= da0_er;
+ i_enable <= '1';
+ when da0_er =>
+ cstate <= da0_sa;
+ i_read <= '1';
+ when da0_sa =>
+ cstate <= da0_dr;
+ i_MemAdr <= a0(G_MemoryAddress-1 downto 1);
+ when da0_dr =>
+ cstate <= da0_dm;
+ i_read <= '0';
+ when da0_dm =>
+ cstate <= da0_wait;
+ i_enable <= '0';
+ when da0_wait =>
+ if (o_membusy='1') then
+ cstate <= da0_wait;
+ else
+ cstate <= da0_bfh;
+ end if;
+ when da0_bfh =>
+ if (o_disbusy='0') then
+ cstate <= da0_bfh;
+ else
+ cstate <= da0_fh;
+ end if;
+ when da0_fh =>
+ cstate <= da0_waitfh;
+ i_x <= std_logic_vector(to_unsigned(0,ROWS_BITS));
+ diby <= o_MemDB(15 downto 8);
+ when da0_waitfh =>
+ if (o_disbusy='1') then
+ cstate <= da0_waitfh;
+ else
+ cstate <= da0_bsh;
+ end if;
+ when da0_bsh =>
+ if (o_disbusy='1') then
+ cstate <= da0_bsh;
+ else
+ cstate <= da0_sh;
+ end if;
+ when da0_sh =>
+ cstate <= da0_waitsh;
+ i_x <= std_logic_vector(to_unsigned(1,ROWS_BITS));
+ diby <= o_MemDB(7 downto 0);
+ when da0_waitsh =>
+ if (o_disbusy='1') then
+ cstate <= da0_waitsh;
+ else
+ cstate <= da1_em;
+ end if;
+
+ when da1_em =>
+ cstate <= da1_er;
+ i_enable <= '1';
+ when da1_er =>
+ cstate <= da1_sa;
+ i_read <= '1';
+ when da1_sa =>
+ cstate <= da1_dr;
+ i_MemAdr <= a1(G_MemoryAddress-1 downto 1);
+ when da1_dr =>
+ cstate <= da1_dm;
+ i_read <= '0';
+ when da1_dm =>
+ cstate <= da1_wait;
+ i_enable <= '0';
+ when da1_wait =>
+ if (o_membusy='1') then
+ cstate <= da1_wait;
+ else
+ cstate <= da1_bfh;
+ end if;
+ when da1_bfh =>
+ if (o_disbusy='1') then
+ cstate <= da1_bfh;
+ else
+ cstate <= da1_fh;
+ end if;
+ when da1_fh =>
+ cstate <= da1_waitfh;
+ i_x <= std_logic_vector(to_unsigned(2,ROWS_BITS));
+ diby <= o_MemDB(15 downto 8);
+ when da1_waitfh =>
+ if (o_disbusy='1') then
+ cstate <= da1_waitfh;
+ else
+ cstate <= da1_bsh;
+ end if;
+ when da1_bsh =>
+ if (o_disbusy='1') then
+ cstate <= da1_bsh;
+ else
+ cstate <= da1_sh;
+ end if;
+ when da1_sh =>
+ cstate <= da1_waitsh;
+ i_x <= std_logic_vector(to_unsigned(3,ROWS_BITS));
+ diby <= o_MemDB(7 downto 0);
+ when da1_waitsh =>
+ if (o_disbusy='1') then
+ cstate <= da1_waitsh;
+ else
+ cstate <= da2_em;
+ end if;
+
+ when da2_em =>
+ cstate <= da2_er;
+ i_enable <= '1';
+ when da2_er =>
+ cstate <= da2_sa;
+ i_read <= '1';
+ when da2_sa =>
+ cstate <= da2_dr;
+ i_MemAdr <= a2(G_MemoryAddress-1 downto 1);
+ when da2_dr =>
+ cstate <= da2_dm;
+ i_read <= '0';
+ when da2_dm =>
+ cstate <= da2_wait;
+ i_enable <= '0';
+ when da2_wait =>
+ if (o_membusy='1') then
+ cstate <= da2_wait;
+ else
+ cstate <= da2_bfh;
+ end if;
+ when da2_bfh =>
+ if (o_disbusy='1') then
+ cstate <= da2_bfh;
+ else
+ cstate <= da2_fh;
+ end if;
+ when da2_fh =>
+ cstate <= da2_waitfh;
+ i_x <= std_logic_vector(to_unsigned(4,ROWS_BITS));
+ diby <= o_MemDB(15 downto 8);
+ when da2_waitfh =>
+ if (o_disbusy='1') then
+ cstate <= da2_waitfh;
+ else
+ cstate <= da2_bsh;
+ end if;
+ when da2_bsh =>
+ if (o_disbusy='1') then
+ cstate <= da2_bsh;
+ else
+ cstate <= da2_sh;
+ end if;
+ when da2_sh =>
+ cstate <= da2_waitsh;
+ i_x <= std_logic_vector(to_unsigned(5,ROWS_BITS));
+ diby <= o_MemDB(7 downto 0);
+ when da2_waitsh =>
+ if (o_disbusy='1') then
+ cstate <= da2_waitsh;
+ else
+ cstate <= da3_em;
+ end if;
+
+ when da3_em =>
+ cstate <= da3_er;
+ i_enable <= '1';
+ when da3_er =>
+ cstate <= da3_sa;
+ i_read <= '1';
+ when da3_sa =>
+ cstate <= da3_dr;
+ i_MemAdr <= a3(G_MemoryAddress-1 downto 1);
+ when da3_dr =>
+ cstate <= da3_dm;
+ i_read <= '0';
+ when da3_dm =>
+ cstate <= da3_wait;
+ i_enable <= '0';
+ when da3_wait =>
+ if (o_membusy='1') then
+ cstate <= da3_wait;
+ else
+ cstate <= da3_bfh;
+ end if;
+ when da3_bfh =>
+ if (o_disbusy='1') then
+ cstate <= da3_bfh;
+ else
+ cstate <= da3_fh;
+ end if;
+ when da3_fh =>
+ cstate <= da3_waitfh;
+ i_x <= std_logic_vector(to_unsigned(6,ROWS_BITS));
+ diby <= o_MemDB(15 downto 8);
+ when da3_waitfh =>
+ if (o_disbusy='1') then
+ cstate <= da3_waitfh;
+ else
+ cstate <= da3_bsh;
+ end if;
+ when da3_bsh =>
+ if (o_disbusy='1') then
+ cstate <= da3_bsh;
+ else
+ cstate <= da3_sh;
+ end if;
+ when da3_sh =>
+ cstate <= da3_waitsh;
+ i_x <= std_logic_vector(to_unsigned(7,ROWS_BITS));
+ diby <= o_MemDB(7 downto 0);
+ when da3_waitsh =>
+ if (o_disbusy='1') then
+ cstate <= da3_waitsh;
+ else
+ cstate <= dd;
+ end if;
+
+ when dd =>
+ cstate <= dd;
+ draw <= '0';
+ all_pixels <= '1';
+
+ when others => null;
+ end case cstate;
+ end if;
+end process p0;
+
+end Behavioral;
diff --git a/gof/README.md b/gof/README.md
new file mode 100755
index 0000000..f0a9683
--- /dev/null
+++ b/gof/README.md
@@ -0,0 +1,8 @@
+# Gospers's Glider Gun on OLED SSD1306 on Digilent Nexys 2 (Xilinx XC3S1200E)
+
+
+
+
+
+#
+
diff --git a/gof/VID-20201126-225749-3.gif b/gof/VID-20201126-225749-3.gif
new file mode 100755
index 0000000..36a8ea4
Binary files /dev/null and b/gof/VID-20201126-225749-3.gif differ
diff --git a/gof/clock_divider.vhd b/gof/clock_divider.vhd
new file mode 100755
index 0000000..3278099
--- /dev/null
+++ b/gof/clock_divider.vhd
@@ -0,0 +1,63 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:42:10 09/18/2020
+-- Design Name:
+-- Module Name: clock_divider - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_divider is
+Port(
+i_clk : in STD_LOGIC;
+i_board_clock : in INTEGER;
+i_divider : in INTEGER;
+o_clk : out STD_LOGIC
+);
+end clock_divider;
+
+architecture Behavioral of clock_divider is
+begin
+
+p0 : process (i_clk) is
+ variable clk_out : std_logic;
+ variable a : integer := i_board_clock;
+ variable b : integer := i_divider;
+begin
+ if (rising_edge(i_clk)) then
+ if (a <= 0) then
+ clk_out := '1';
+ a := i_board_clock;
+ b := i_divider;
+ else
+ clk_out := '0';
+ a := a - b;
+ end if;
+ end if;
+ o_clk <= clk_out;
+end process p0;
+
+end Behavioral;
+
diff --git a/gof/clock_divider1.vhd b/gof/clock_divider1.vhd
new file mode 100755
index 0000000..fe36c24
--- /dev/null
+++ b/gof/clock_divider1.vhd
@@ -0,0 +1,64 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:42:10 09/18/2020
+-- Design Name:
+-- Module Name: clock_divider - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_memory_content.ALL;
+use WORK.p_constants1.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_divider1 is
+Generic (
+ g_board_clock : integer := G_BOARD_CLOCK;
+ g_divider : integer := 1
+);
+Port (
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+);
+end clock_divider1;
+
+architecture Behavioral of clock_divider1 is
+begin
+
+p0 : process (i_clock) is
+ variable clock_out : std_logic;
+ variable counter : integer := 0;
+begin
+ if (rising_edge(i_clock)) then
+ if (counter = (g_board_clock / g_divider) - 1) then
+ clock_out := '1';
+ counter := 0;
+ else
+ clock_out := '0';
+ counter := counter + 1;
+ end if;
+ end if;
+ o_clock <= clock_out;
+end process p0;
+
+end Behavioral;
diff --git a/gof/example-memory1.png b/gof/example-memory1.png
new file mode 100755
index 0000000..f6c942d
Binary files /dev/null and b/gof/example-memory1.png differ
diff --git a/gof/example-memory2.png b/gof/example-memory2.png
new file mode 100755
index 0000000..06b8b2e
Binary files /dev/null and b/gof/example-memory2.png differ
diff --git a/gof/gof.vhd b/gof/gof.vhd
new file mode 100755
index 0000000..910231c
--- /dev/null
+++ b/gof/gof.vhd
@@ -0,0 +1,64 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:07:54 10/27/2020
+-- Design Name:
+-- Module Name: memory1 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+--library IEEE;
+--use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+-- https://www.conwaylife.com/patterns/gosperglidergun.cells
+-- !Name: Gosper glider gun
+-- !Author: Bill Gosper
+-- !The first known gun and the first known finite pattern with unbounded growth.
+-- !www.conwaylife.com/wiki/index.php?title=Gosper_glider_gun
+-- ........................O
+-- ......................O.O
+-- ............OO......OO............OO
+-- ...........O...O....OO............OO
+-- OO........O.....O...OO
+-- OO........O...O.OO....O.O
+-- ..........O.....O.......O
+-- ...........O...O
+-- ............OO
+
+--entity memory1 is
+--Generic (
+--WIDTH : integer;
+--HEIGHT : integer);
+--Port (
+--i_clk : in STD_LOGIC;
+--i_x : in STD_LOGIC;
+--i_y : in STD_LOGIC;
+--o_bit : out STD_LOGIC);
+--end memory1;
+--
+--architecture Behavioral of memory1 is
+--type array1 is array(0 to WIDTH-1,0 to HEIGHT-1) of std_logic;
+--begin
+--
+--
+--end Behavioral;
+
diff --git a/gof/gof.xise b/gof/gof.xise
new file mode 100755
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@@ -0,0 +1,481 @@
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diff --git a/gof/i2c.vhd b/gof/i2c.vhd
new file mode 100755
index 0000000..9042896
--- /dev/null
+++ b/gof/i2c.vhd
@@ -0,0 +1,269 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:46:01 08/21/2020
+-- Design Name:
+-- Module Name: i2c - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+--
+-- FileName: i2c_master.vhd
+-- Dependencies: none
+-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
+--
+-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
+-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
+-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
+-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
+-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
+-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
+-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
+-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
+--
+-- Version History
+-- Version 1.0 11/01/2012 Scott Larson
+-- Initial Public Release
+-- Version 2.0 06/20/2014 Scott Larson
+-- Added ability to interface with different slaves in the same transaction
+-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
+-- Corrected timing of when ack_error signal clears
+-- Version 2.1 10/21/2014 Scott Larson
+-- Replaced gated clock with clock enable
+-- Adjusted timing of SCL during start and stop conditions
+-- Version 2.2 02/05/2015 Scott Larson
+-- Corrected small SDA glitch introduced in version 2.1
+--
+--------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY i2c_master IS
+ GENERIC(
+ input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
+ bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz
+ PORT(
+ clk : IN STD_LOGIC; --system clock
+ reset_n : IN STD_LOGIC; --active low reset
+ ena : IN STD_LOGIC; --latch in command
+ addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
+ rw : IN STD_LOGIC; --'0' is write, '1' is read
+ data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
+ busy : OUT STD_LOGIC; --indicates transaction in progress
+ data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
+ ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
+ sda : INOUT STD_LOGIC; --serial data output of i2c bus
+ scl : INOUT STD_LOGIC); --serial clock output of i2c bus
+END i2c_master;
+
+ARCHITECTURE logic OF i2c_master IS
+ CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
+ TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
+ SIGNAL state : machine; --state machine
+ SIGNAL data_clk : STD_LOGIC; --data clock for sda
+ SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
+ SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
+ SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
+ SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
+ SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
+ SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
+ SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
+ SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
+ SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
+ SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
+BEGIN
+
+ --generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
+ PROCESS(clk, reset_n)
+ VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
+ BEGIN
+ IF(reset_n = '0') THEN --reset asserted
+ stretch <= '0';
+ count := 0;
+ ELSIF(clk'EVENT AND clk = '1') THEN
+ data_clk_prev <= data_clk; --store previous value of data clock
+ IF(count = divider*4-1) THEN --end of timing cycle
+ count := 0; --reset timer
+ ELSIF(stretch = '0') THEN --clock stretching from slave not detected
+ count := count + 1; --continue clock generation timing
+ END IF;
+ CASE count IS
+ WHEN 0 TO divider-1 => --first 1/4 cycle of clocking
+ scl_clk <= '0';
+ data_clk <= '0';
+ WHEN divider TO divider*2-1 => --second 1/4 cycle of clocking
+ scl_clk <= '0';
+ data_clk <= '1';
+ WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking
+ scl_clk <= '1'; --release scl
+ IF(scl = '0') THEN --detect if slave is stretching clock
+ stretch <= '1';
+ ELSE
+ stretch <= '0';
+ END IF;
+ data_clk <= '1';
+ WHEN OTHERS => --last 1/4 cycle of clocking
+ scl_clk <= '1';
+ data_clk <= '0';
+ END CASE;
+ END IF;
+ END PROCESS;
+
+ --state machine and writing to sda during scl low (data_clk rising edge)
+ PROCESS(clk, reset_n)
+ BEGIN
+ IF(reset_n = '0') THEN --reset asserted
+ state <= ready; --return to initial state
+ busy <= '1'; --indicate not available
+ scl_ena <= '0'; --sets scl high impedance
+ sda_int <= '1'; --sets sda high impedance
+ ack_error <= '0'; --clear acknowledge error flag
+ bit_cnt <= 7; --restarts data bit counter
+ data_rd <= "00000000"; --clear data read port
+ ELSIF(clk'EVENT AND clk = '1') THEN
+ IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
+ CASE state IS
+ WHEN ready => --idle state
+ IF(ena = '1') THEN --transaction requested
+ busy <= '1'; --flag busy
+ addr_rw <= addr & rw; --collect requested slave address and command
+ data_tx <= data_wr; --collect requested data to write
+ state <= start; --go to start bit
+ ELSE --remain idle
+ busy <= '0'; --unflag busy
+ state <= ready; --remain idle
+ END IF;
+ WHEN start => --start bit of transaction
+ busy <= '1'; --resume busy if continuous mode
+ sda_int <= addr_rw(bit_cnt); --set first address bit to bus
+ state <= command; --go to command
+ WHEN command => --address and command byte of transaction
+ IF(bit_cnt = 0) THEN --command transmit finished
+ sda_int <= '1'; --release sda for slave acknowledge
+ bit_cnt <= 7; --reset bit counter for "byte" states
+ state <= slv_ack1; --go to slave acknowledge (command)
+ ELSE --next clock cycle of command state
+ bit_cnt <= bit_cnt - 1; --keep track of transaction bits
+ sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
+ state <= command; --continue with command
+ END IF;
+ WHEN slv_ack1 => --slave acknowledge bit (command)
+ IF(addr_rw(0) = '0') THEN --write command
+ sda_int <= data_tx(bit_cnt); --write first bit of data
+ state <= wr; --go to write byte
+ ELSE --read command
+ sda_int <= '1'; --release sda from incoming data
+ state <= rd; --go to read byte
+ END IF;
+ WHEN wr => --write byte of transaction
+ busy <= '1'; --resume busy if continuous mode
+ IF(bit_cnt = 0) THEN --write byte transmit finished
+ sda_int <= '1'; --release sda for slave acknowledge
+ bit_cnt <= 7; --reset bit counter for "byte" states
+ state <= slv_ack2; --go to slave acknowledge (write)
+ ELSE --next clock cycle of write state
+ bit_cnt <= bit_cnt - 1; --keep track of transaction bits
+ sda_int <= data_tx(bit_cnt-1); --write next bit to bus
+ state <= wr; --continue writing
+ END IF;
+ WHEN rd => --read byte of transaction
+ busy <= '1'; --resume busy if continuous mode
+ IF(bit_cnt = 0) THEN --read byte receive finished
+ IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
+ sda_int <= '0'; --acknowledge the byte has been received
+ ELSE --stopping or continuing with a write
+ sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
+ END IF;
+ bit_cnt <= 7; --reset bit counter for "byte" states
+ data_rd <= data_rx; --output received data
+ state <= mstr_ack; --go to master acknowledge
+ ELSE --next clock cycle of read state
+ bit_cnt <= bit_cnt - 1; --keep track of transaction bits
+ state <= rd; --continue reading
+ END IF;
+ WHEN slv_ack2 => --slave acknowledge bit (write)
+ IF(ena = '1') THEN --continue transaction
+ busy <= '0'; --continue is accepted
+ addr_rw <= addr & rw; --collect requested slave address and command
+ data_tx <= data_wr; --collect requested data to write
+ IF(addr_rw = addr & rw) THEN --continue transaction with another write
+ sda_int <= data_wr(bit_cnt); --write first bit of data
+ state <= wr; --go to write byte
+ ELSE --continue transaction with a read or new slave
+ state <= start; --go to repeated start
+ END IF;
+ ELSE --complete transaction
+ state <= stop; --go to stop bit
+ END IF;
+ WHEN mstr_ack => --master acknowledge bit after a read
+ IF(ena = '1') THEN --continue transaction
+ busy <= '0'; --continue is accepted and data received is available on bus
+ addr_rw <= addr & rw; --collect requested slave address and command
+ data_tx <= data_wr; --collect requested data to write
+ IF(addr_rw = addr & rw) THEN --continue transaction with another read
+ sda_int <= '1'; --release sda from incoming data
+ state <= rd; --go to read byte
+ ELSE --continue transaction with a write or new slave
+ state <= start; --repeated start
+ END IF;
+ ELSE --complete transaction
+ state <= stop; --go to stop bit
+ END IF;
+ WHEN stop => --stop bit of transaction
+ busy <= '0'; --unflag busy
+ state <= ready; --go to idle state
+ END CASE;
+ ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
+ CASE state IS
+ WHEN start =>
+ IF(scl_ena = '0') THEN --starting new transaction
+ scl_ena <= '1'; --enable scl output
+ ack_error <= '0'; --reset acknowledge error output
+ END IF;
+ WHEN slv_ack1 => --receiving slave acknowledge (command)
+ IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
+ ack_error <= '1'; --set error output if no-acknowledge
+ END IF;
+ WHEN rd => --receiving slave data
+ data_rx(bit_cnt) <= sda; --receive current slave data bit
+ WHEN slv_ack2 => --receiving slave acknowledge (write)
+ IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
+ ack_error <= '1'; --set error output if no-acknowledge
+ END IF;
+ WHEN stop =>
+ scl_ena <= '0'; --disable scl
+ WHEN OTHERS =>
+ NULL;
+ END CASE;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ --set sda output
+ WITH state SELECT
+ sda_ena_n <= data_clk_prev WHEN start, --generate start condition
+ NOT data_clk_prev WHEN stop, --generate stop condition
+ sda_int WHEN OTHERS; --set to internal sda signal
+
+ --set scl and sda outputs
+ scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
+ sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
+
+END logic;
+
+
diff --git a/gof/impact_top.ipf b/gof/impact_top.ipf
new file mode 100755
index 0000000..2ee5452
--- /dev/null
+++ b/gof/impact_top.ipf
@@ -0,0 +1,8 @@
+setMode -bs
+setCable -port auto
+Identify -inferir
+identifyMPM
+assignFile -p 1 -file top.bit
+Program -p 1
+closeCable
+quit
diff --git a/gof/isim_glidergun_32x32.png b/gof/isim_glidergun_32x32.png
new file mode 100755
index 0000000..4d35add
Binary files /dev/null and b/gof/isim_glidergun_32x32.png differ
diff --git a/gof/lcd_display.vhd b/gof/lcd_display.vhd
new file mode 100755
index 0000000..6406291
--- /dev/null
+++ b/gof/lcd_display.vhd
@@ -0,0 +1,135 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:24:00 11/28/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/memorymodule/lcd_display.vhd
+-- Project Name: memorymodule
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_memory_content.ALL;
+use WORK.p_constants1.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity lcd_display is
+Generic (
+ LCDClockDivider : integer := G_LCDClockDivider
+);
+Port (
+ i_clock : in std_logic;
+ i_LCDChar : LCDHex;
+ o_anode : out std_logic_vector(G_LCDAnode-1 downto 0);
+ o_segment : out std_logic_vector(G_LCDSegment-1 downto 0)
+);
+end lcd_display;
+
+architecture Behavioral of lcd_display is
+
+ component clock_divider1 is
+ Generic(
+ g_board_clock : integer;
+ g_divider : integer
+ );
+ Port(
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+ );
+ end component clock_divider1;
+ for all : clock_divider1 use entity work.clock_divider1(Behavioral);
+
+ signal clock_divider_1 : std_logic;
+
+begin
+
+ c_clock_divider_1 : clock_divider1
+ Generic Map (
+ g_board_clock => G_BOARD_CLOCK,
+ g_divider => LCDClockDivider
+ )
+ Port Map (
+ i_clock => i_clock,
+ o_clock => clock_divider_1
+ );
+
+ p0 : process (clock_divider_1) is
+ variable count : integer range 0 to G_LCDAnode := 0;
+ begin
+ if (rising_edge(clock_divider_1)) then
+ case count is
+ when 0 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "0111";
+ when 1 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1011";
+ when 2 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1101";
+ when 3 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1110";
+ when others =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1111";
+ end case;
+ if (count < G_LCDAnode-1) then
+ count := count + 1;
+ else
+ count := 0;
+ end if;
+ end if;
+ end process p0;
+
+ p1 : process (clock_divider_1) is
+ variable count : integer range 0 to G_LCDAnode := 0;
+ variable converted_lcdhex : LCDHex;
+ begin
+ if (rising_edge(clock_divider_1)) then
+ if (Is_X(i_LCDChar(count))) then
+ converted_lcdhex := (x"0",x"0",x"0",x"0");
+ else
+ converted_lcdhex := i_LCDChar;
+ end if;
+ case to_integer(unsigned(converted_lcdhex(count))) is
+ when 0 => o_segment <= "1000000"; -- 0
+ when 1 => o_segment <= "1111001"; -- 1
+ when 2 => o_segment <= "0100100"; -- 2
+ when 3 => o_segment <= "0110000"; -- 3
+ when 4 => o_segment <= "0011001"; -- 4
+ when 5 => o_segment <= "0010010"; -- 5
+ when 6 => o_segment <= "0000010"; -- 6
+ when 7 => o_segment <= "1111000"; -- 7
+ when 8 => o_segment <= "0000000"; -- 8
+ when 9 => o_segment <= "0010000"; -- 9
+ when 10 => o_segment <= "0001000"; -- a
+ when 11 => o_segment <= "0000011"; -- b
+ when 12 => o_segment <= "1000110"; -- c
+ when 13 => o_segment <= "0100001"; -- d
+ when 14 => o_segment <= "0000110"; -- e
+ when 15 => o_segment <= "0001110"; -- f
+ when others => null;
+ end case;
+ if (count < G_LCDAnode-1) then
+ count := count + 1;
+ else
+ count := 0;
+ end if;
+ end if;
+ end process p1;
+
+end Behavioral;
diff --git a/gof/memory1.vhd b/gof/memory1.vhd
new file mode 100755
index 0000000..79fe262
--- /dev/null
+++ b/gof/memory1.vhd
@@ -0,0 +1,386 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:07:54 10/27/2020
+-- Design Name:
+-- Module Name: memory1 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_memory_content.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+-- pragma translate_off
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+-- pragma translate_on
+
+entity memory1 is
+Port (
+i_clk : in std_logic;
+i_reset : in std_logic;
+i_copy_content : in std_logic;
+o_copy_content : out std_logic;
+i_enable_byte : in std_logic;
+i_enable_bit : in std_logic;
+i_write_byte : in std_logic;
+i_write_bit : in std_logic;
+i_row : in std_logic_vector(ROWS_BITS-1 downto 0);
+i_col_pixel : in std_logic_vector(COLS_PIXEL_BITS-1 downto 0);
+i_col_block : in std_logic_vector(COLS_BLOCK_BITS-1 downto 0);
+i_byte : in std_logic_vector(BYTE_BITS-1 downto 0);
+i_bit : in std_logic;
+o_byte : out std_logic_vector(BYTE_BITS-1 downto 0);
+o_bit : out std_logic
+);
+end memory1;
+
+architecture Behavioral of memory1 is
+
+component RAMB16_S36
+generic (
+WRITE_MODE : string := "NO_CHANGE"; -- WRITE_FIRST/READ_FIRST/NO_CHANGE
+INIT : bit_vector(35 downto 0) := X"000000000";
+SRVAL : bit_vector(35 downto 0) := X"012345678"
+);
+port (
+DI : in std_logic_vector (31 downto 0);
+DIP : in std_logic_vector (3 downto 0);
+ADDR : in std_logic_vector (8 downto 0);
+EN : in STD_LOGIC;
+WE : in STD_LOGIC;
+SSR : in STD_LOGIC;
+CLK : in STD_LOGIC;
+DO : out std_logic_vector (31 downto 0);
+DOP : out std_logic_vector (3 downto 0)
+);
+end component;
+
+signal DATA_IN : std_logic_vector(WORD_BITS-1 downto 0);
+signal DATA_INP : std_logic_vector(PARITY_BITS-1 downto 0);
+signal ADDRESS : std_logic_vector(BRAM_ADDRESS_BITS-1 downto 0);
+signal ENABLE : std_logic;
+signal WRITE_EN : std_logic;
+signal DATA_OUT : std_logic_vector(WORD_BITS-1 downto 0);
+signal DATA_OUTP : std_logic_vector(PARITY_BITS-1 downto 0);
+
+type p0_states is (idle,start,write_content,done_copy);
+signal p0_state : p0_states;
+signal p0_index : integer range 0 to ROWS - 1;
+signal p0_enable,p1_enable,p2_enable,p3_enable,p4_enable : std_logic;
+signal p0_write_en,p1_write_en,p2_write_en,p3_write_en,p4_write_en : std_logic;
+signal p0_address,p1_address,p2_address,p3_address,p4_address : std_logic_vector(BRAM_ADDRESS_BITS-1 downto 0);
+signal p0_data_in,p1_data_in,p2_data_in,p3_data_in,p4_data_in : std_logic_vector(WORD_BITS-1 downto 0);
+signal p2_obyte : std_logic_vector(BYTE_BITS-1 downto 0);
+signal p4_obit : std_logic;
+
+function vec2str(vec: std_logic_vector) return string is
+ variable result: string(vec'left downto 0);
+ begin
+ for i in vec'range loop
+ if (vec(i) = '1') then
+ result(i) := '1';
+ elsif (vec(i) = '0') then
+ result(i) := '0';
+ elsif (vec(i) = 'X') then
+ result(i) := 'X';
+ elsif (vec(i) = 'U') then
+ result(i) := 'U';
+ else
+ result(i) := '?';
+ end if;
+ end loop;
+ return result;
+ end;
+begin
+
+o_byte <= p2_obyte;
+o_bit <= p4_obit;
+
+p0a : process(i_copy_content,i_enable_byte,i_enable_bit,i_write_byte,i_write_bit,
+p0_enable,p1_enable,p2_enable,p3_enable,p4_enable) is
+ variable t_enable : std_logic_vector(4 downto 0);
+begin
+ t_enable := (i_copy_content,i_enable_byte,i_enable_bit,i_write_byte,i_write_bit);
+-- report "enable " & vec2str(t_enable);
+ case(t_enable) is
+ when "10000" =>
+ ENABLE <= p0_enable;
+ when "01010" =>
+ ENABLE <= p1_enable;
+ when "01000" =>
+ ENABLE <= p2_enable;
+ when "00101" =>
+ ENABLE <= p3_enable;
+ when "00100" =>
+ ENABLE <= p4_enable;
+ when others =>
+ ENABLE <= '0';
+ end case;
+end process p0a;
+
+p1a : process(i_copy_content,i_enable_byte,i_enable_bit,i_write_byte,i_write_bit,
+p0_write_en,p1_write_en,p2_write_en,p3_write_en,p4_write_en) is
+ variable t_write_en : std_logic_vector(4 downto 0);
+begin
+ t_write_en := (i_copy_content,i_enable_byte,i_enable_bit,i_write_byte,i_write_bit);
+-- report "write_en " & vec2str(t_write_en);
+ case(t_write_en) is
+ when "10000" =>
+ WRITE_EN <= p0_write_en;
+ when "01010" =>
+ WRITE_EN <= p1_write_en;
+ when "01000" =>
+ WRITE_EN <= p2_write_en;
+ when "00101" =>
+ WRITE_EN <= p3_write_en;
+ when "00100" =>
+ WRITE_EN <= p4_write_en;
+ when others =>
+ WRITE_EN <= '0';
+ end case;
+end process p1a;
+
+p2a : process(i_copy_content,i_enable_byte,i_enable_bit,i_write_byte,i_write_bit,
+p0_address,p1_address,p2_address,p3_address,p4_address) is
+ variable t_address : std_logic_vector(4 downto 0);
+begin
+ t_address := (i_copy_content,i_enable_byte,i_enable_bit,i_write_byte,i_write_bit);
+-- report "address " & vec2str(t_address);
+ case(t_address) is
+ when "10000" =>
+ ADDRESS <= p0_address;
+ when "01010" =>
+ ADDRESS <= p1_address;
+ when "01000" =>
+ ADDRESS <= p2_address;
+ when "00101" =>
+ ADDRESS <= p3_address;
+ when "00100" =>
+ ADDRESS <= p4_address;
+ when others =>
+ ADDRESS <= (others => '0');
+ end case;
+end process p2a;
+
+p3a : process(i_copy_content,i_enable_byte,i_enable_bit,i_write_byte,i_write_bit,
+p0_data_in,p1_data_in,p2_data_in,p3_data_in,p4_data_in) is
+ variable t_data_in : std_logic_vector(4 downto 0);
+begin
+ t_data_in := (i_copy_content,i_enable_byte,i_enable_bit,i_write_byte,i_write_bit);
+-- report "data_in " & vec2str(t_data_in);
+ case(t_data_in) is
+ when "10000" =>
+ DATA_IN <= p0_data_in;
+ when "01010" =>
+ DATA_IN <= p1_data_in;
+ when "01000" =>
+ DATA_IN <= p2_data_in;
+ when "00101" =>
+ DATA_IN <= p3_data_in;
+ when "00100" =>
+ DATA_IN <= p4_data_in;
+ when others =>
+ DATA_IN <= (others => '0');
+ end case;
+end process p3a;
+
+p0 : process (i_clk,i_reset) is
+begin
+ if (i_reset = '1') then
+ p0_state <= idle;
+ p0_index <= 0;
+ p0_enable <= '0';
+ p0_write_en <= '0';
+ p0_address <= (others => '0');
+ p0_data_in <= (others => '0');
+ o_copy_content <= '0';
+ elsif (rising_edge(i_clk)) then
+ case (p0_state) is
+ when idle =>
+ if (i_copy_content = '1') then
+ p0_state <= start;
+ else
+ p0_state <= idle;
+ end if;
+ p0_state <= start;
+ p0_enable <= '0';
+ p0_write_en <= '0';
+ when start =>
+ p0_state <= write_content;
+ p0_enable <= '1';
+ p0_write_en <= '1';
+ p0_address <= std_logic_vector(to_unsigned(p0_index,BRAM_ADDRESS_BITS));
+ p0_data_in <= memory_content(p0_index);
+ when write_content =>
+ p0_enable <= '0';
+ p0_write_en <= '0';
+ if (p0_index = ROWS-1) then
+ p0_state <= done_copy;
+ p0_index <= 0;
+ else
+ p0_state <= idle;
+ p0_index <= p0_index + 1;
+ end if;
+ when done_copy =>
+ p0_state <= done_copy;
+ o_copy_content <= '1';
+ p0_enable <= '0';
+ p0_write_en <= '0';
+ p0_address <= (others => '0');
+ p0_data_in <= (others => '0');
+ end case;
+ end if;
+end process p0;
+
+p1 : process (i_reset,i_enable_byte,i_write_byte,i_row,DATA_IN,i_byte,DATA_OUT) is
+ variable p1_t0 : std_logic_vector(WORD_BITS-1 downto 0);
+ variable p1_t1 : std_logic_vector(WORD_BITS-1 downto 0);
+begin
+ p1_t0 := DATA_OUT;
+ if (i_reset = '1') then
+ p1_enable <= '0';
+ p1_write_en <= '0';
+ p1_address <= (others => '0');
+ p1_data_in <= (others => '0');
+ p1_t1 := (others => '0');
+ elsif (i_enable_byte = '1' and i_write_byte = '1') then
+ p1_enable <= '1';
+ p1_write_en <= '1';
+ p1_address <= std_logic_vector(to_unsigned(0,BRAM_ADDRESS_BITS-ROWS_BITS)) & i_row;
+ case (to_integer(unsigned(i_col_block))) is
+ when 0 =>
+ p1_t1 := p1_t0(31 downto 8) & i_byte;
+ when 1 =>
+ p1_t1 := p1_t0(31 downto 16) & i_byte & p1_t0(7 downto 0);
+ when 2 =>
+ p1_t1 := p1_t0(31 downto 24) & i_byte & p1_t0(15 downto 0);
+ when 3 =>
+ p1_t1 := i_byte & p1_t0(23 downto 0);
+ when others => null;
+ end case;
+ p1_data_in <= p1_t1;
+ else
+ p1_write_en <= '0';
+ p1_enable <= '0';
+ p1_data_in <= (others => '0');
+ p1_address <= (others => '0');
+ p1_t1 := (others => '0');
+ end if;
+end process p1;
+
+p2 : process (i_reset,i_enable_byte,i_write_byte,i_row,DATA_OUT) is
+ variable p2_t : std_logic_vector(BYTE_BITS-1 downto 0);
+begin
+ if (i_reset = '1') then
+ p2_enable <= '0';
+ p2_write_en <= '0';
+ p2_address <= (others => '0');
+ p2_data_in <= (others => '0');
+ p2_obyte <= (others => '0');
+ p2_t := (others => '0');
+ elsif (i_enable_byte = '1' and i_write_byte = '0') then
+ p2_enable <= '1';
+ p2_write_en <= '0';
+ p2_address <= std_logic_vector(to_unsigned(0,BRAM_ADDRESS_BITS-ROWS_BITS)) & i_row;
+ case (to_integer(unsigned(i_col_block))) is
+ when 0 =>
+ p2_t := DATA_OUT(7 downto 0);
+ when 1 =>
+ p2_t := DATA_OUT(15 downto 8);
+ when 2 =>
+ p2_t := DATA_OUT(23 downto 16);
+ when 3 =>
+ p2_t := DATA_OUT(31 downto 24);
+ when others => null;
+ end case;
+ p2_obyte <= p2_t;
+ else
+ p2_enable <= '0';
+ p2_address <= (others => '0');
+ p2_obyte <= (others => '0');
+ p2_t := (others => '0');
+ end if;
+end process p2;
+
+p3 : process (i_reset,i_enable_bit,i_write_bit,p3_data_in,i_row,i_bit) is
+ variable i : integer range 0 to WORD_BITS-1;
+ variable p3_t : std_logic_vector(WORD_BITS-1 downto 0);
+begin
+ i := to_integer(unsigned(i_col_pixel));
+ p3_t := p3_data_in;
+ if (i_reset = '1') then
+ p3_enable <= '0';
+ p3_write_en <= '0';
+ p3_address <= (others => '0');
+ p3_data_in <= (others => '0');
+ elsif (i_enable_bit = '1' and i_write_bit = '1') then
+ p3_enable <= '1';
+ p3_write_en <= '1';
+ p3_address <= std_logic_vector(to_unsigned(0,BRAM_ADDRESS_BITS-ROWS_BITS)) & i_row;
+ p3_t(i) := i_bit;
+ p3_data_in <= p3_t;
+ else
+ p3_write_en <= '0';
+ p3_enable <= '0';
+ p3_data_in <= (others => '0');
+ p3_address <= (others => '0');
+ end if;
+end process p3;
+
+p4 : process (i_reset,i_enable_bit,i_write_bit,i_row,DATA_OUT) is
+begin
+ if (i_reset = '1') then
+ p4_enable <= '0';
+ p4_write_en <= '0';
+ p4_address <= (others => '0');
+ p4_data_in <= (others => '0');
+ p4_obit <= '0';
+ elsif (i_enable_bit = '1' and i_write_bit = '0') then
+ p4_enable <= '1';
+ p4_write_en <= '0';
+ p4_address <= std_logic_vector(to_unsigned(0,BRAM_ADDRESS_BITS-ROWS_BITS)) & i_row;
+ p4_obit <= DATA_OUT(to_integer(unsigned(i_col_pixel)));
+ else
+ p4_enable <= '0';
+ p4_address <= (others => '0');
+ p4_obit <= '0';
+ end if;
+end process p4;
+
+U_RAMB16_S36: RAMB16_S36
+generic map (
+WRITE_MODE => "WRITE_FIRST",
+INIT => X"000000000",
+SRVAL => X"000000000"
+)
+port map (
+DI => DATA_IN,
+DIP => DATA_INP,
+ADDR => ADDRESS,
+EN => ENABLE,
+WE => WRITE_EN,
+SSR => i_reset,
+CLK => i_clk,
+DO => DATA_OUT,
+DOP => DATA_OUTP
+);
+
+end Behavioral;
diff --git a/gof/memorymodule.vhd b/gof/memorymodule.vhd
new file mode 100755
index 0000000..f42ff29
--- /dev/null
+++ b/gof/memorymodule.vhd
@@ -0,0 +1,188 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:11:00 11/28/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/memorymodule/memorymodule.vhd
+-- Project Name: memorymodule
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_memory_content.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity memorymodule is
+Port (
+i_clock : in std_logic;
+i_enable : in std_logic;
+i_write : in std_logic;
+i_read : in std_logic;
+o_busy : out std_logic;
+i_MemAdr : in MemoryAddressALL;
+i_MemDB : in MemoryDataByte;
+o_MemDB : out MemoryDataByte;
+io_MemOE : out std_logic;
+io_MemWR : out std_logic;
+io_RamAdv : out std_logic;
+io_RamCS : out std_logic;
+io_RamCRE : out std_logic;
+io_RamLB : out std_logic;
+io_RamUB : out std_logic;
+--i_RamWait : in std_logic;
+io_RamClk : out std_logic;
+io_MemAdr : out MemoryAddressALL;
+io_MemDB : inout MemoryDataByte
+);
+end memorymodule;
+
+architecture Behavioral of memorymodule is
+
+ type state is (
+ idle,
+ start,
+ write_setup,
+ read_setup,
+ write_enable,
+ wait1,
+ write_disable,
+ stop,
+ read1,
+ wait2
+ );
+ signal cstate : state;
+
+ signal MemOE : std_logic;
+ signal MemWR : std_logic;
+ signal RamAdv : std_logic;
+ signal RamCS : std_logic;
+ signal RamLB : std_logic;
+ signal RamCRE : std_logic;
+ signal RamUB : std_logic;
+ signal RamClk : std_logic;
+ signal MemAdr : MemoryAddressALL;
+
+begin
+
+ io_MemOE <= MemOE;
+ io_MemWR <= MemWR;
+ io_RamAdv <= RamAdv;
+ io_RamCS <= RamCS;
+ io_RamCRE <= RamCRE;
+ io_RamLB <= RamLB;
+ io_RamUB <= RamUB;
+ io_RamClk <= RamClk;
+ io_MemAdr <= MemAdr;
+
+ RamLB <= '0';
+ RamUB <= '0';
+ RamCRE <= '0';
+ RamAdv <= '0';
+ RamClk <= '0';
+
+ MemAdr <= i_MemAdr when (RamCS = '0' and (MemWR = '0' or MemOE = '0')) else (others => 'Z');
+ o_MemDB <= io_MemDB;
+ io_MemDB <= i_MemDB when (RamCS = '0' and MemWR = '0') else (others => 'Z');
+
+ p0 : process (i_clock) is
+ constant cw : integer := 3; -- XXX 3 is lowlest for properly mm working
+ variable w : integer range 0 to cw - 1 := 0;
+ variable t : std_logic_vector(G_MemoryData-1 downto 0);
+ begin
+ if (rising_edge(i_clock)) then
+ if (w > 0) then -- XXX 40 ns
+ w := w - 1;
+ end if;
+-- if (w = 0) then -- XXX 60 ns
+-- w := cw - 1;
+-- else
+-- w := w - 1;
+-- end if;
+ case cstate is
+ when idle =>
+ if (i_enable = '1') then
+ cstate <= start; -- XXX check CSb
+ else
+ cstate <= idle;
+ end if;
+ when start =>
+ if (i_write = '1') then
+ cstate <= write_setup;
+ elsif (i_read = '1') then
+ cstate <= read_setup;
+ else
+ cstate <= start;
+ end if;
+ RamCS <= '1';
+ MemWR <= '1';
+ MemOE <= '1';
+ when write_setup =>
+ if (w = 0) then
+ cstate <= write_enable;
+ o_busy <= '1';
+ MemOE <= '1';
+ else
+ cstate <= write_setup;
+ end if;
+ when write_enable =>
+ cstate <= wait1;
+ MemWR <= '0';
+ RamCS <= '0';
+ w := cw - 1;
+ when wait1 =>
+ if (w = 0) then
+ cstate <= write_disable;
+ else
+ cstate <= wait1;
+ end if;
+ when write_disable =>
+ cstate <= stop;
+ RamCS <= '1';
+ MemWR <= '1';
+ when read_setup =>
+ if (w = 0) then
+ cstate <= read1;
+ RamCS <= '0';
+ MemOE <= '0';
+ o_busy <= '1';
+ else
+ cstate <= read_setup;
+ end if;
+ when read1 =>
+ cstate <= wait2;
+ w := cw - 1;
+ when wait2 =>
+ if (w = 0) then
+ cstate <= stop;
+ else
+ cstate <= wait2;
+ end if;
+ when stop =>
+ cstate <= idle;
+ o_busy <= '0';
+ RamCS <= '1';
+ MemOE <= '1';
+ when others => null;
+ end case;
+ end if;
+ end process p0;
+
+end Behavioral;
diff --git a/gof/memorymodule_ramb16_s1.vhd b/gof/memorymodule_ramb16_s1.vhd
new file mode 100755
index 0000000..0c374c0
--- /dev/null
+++ b/gof/memorymodule_ramb16_s1.vhd
@@ -0,0 +1,273 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:11:00 11/28/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/memorymodule/memorymodule.vhd
+-- Project Name: memorymodule
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_memory_content.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity memorymodule_ramb16_s1 is
+Port (
+i_clock : in std_logic;
+i_enable : in std_logic;
+i_write : in std_logic;
+i_read : in std_logic;
+o_busy : out std_logic;
+i_MemAdr : in MemoryAddress;
+i_MemDB : in std_logic_vector(0 downto 0);
+o_MemDB : out std_logic_vector(0 downto 0);
+o_MemOE : out std_logic;
+o_MemWR : out std_logic;
+o_RamAdv : out std_logic;
+o_RamCS : out std_logic;
+o_RamCRE : out std_logic;
+o_RamLB : out std_logic;
+o_RamUB : out std_logic;
+--i_RamWait : in std_logic;
+o_RamClk : out std_logic;
+o_MemAdr : out MemoryAddress;
+io_MemDB : inout std_logic_vector(0 downto 0)
+);
+end memorymodule_ramb16_s1;
+
+architecture Behavioral of memorymodule_ramb16_s1 is
+
+type state is (
+idle,
+start,
+write_setup,
+read_setup,
+write_enable,
+wait1,
+write_disable,
+stop,
+read1,
+wait2
+);
+signal cstate : state;
+
+signal MemOE : std_logic;
+signal MemWR : std_logic;
+signal RamAdv : std_logic;
+signal RamCS : std_logic;
+signal RamLB : std_logic;
+signal RamCRE : std_logic;
+signal RamUB : std_logic;
+signal RamClk : std_logic;
+signal MemAdr : MemoryAddress;
+signal MemDB : MemoryDataByte;
+
+signal RAMB16_S1_DO,RAMB16_S1_DI : std_logic_vector(0 downto 0);
+signal RAMB16_S1_ADDR : std_logic_vector(13 downto 0);
+signal RAMB16_S1_CLK,RAMB16_S1_EN,RAMB16_S1_SSR,RAMB16_S1_WE : std_logic;
+
+begin
+
+RAMB16_S1_ADDR(13 downto 0) <= i_MemAdr(14 downto 1) when (RamCS = '0' and (MemWR = '0' or MemOE = '0')) else (others => 'Z');
+o_MemDB(0 downto 0) <= RAMB16_S1_DO(0 downto 0) when (cstate = idle) else (others => 'Z');
+io_MemDB <= RAMB16_S1_DO(0 downto 0) when (RamCS = '0' and MemOE = '0') else (others => 'Z');
+RAMB16_S1_DI(0 downto 0) <= i_MemDB when (RamCS = '0' and MemWR = '0') else (others => 'Z');
+RAMB16_S1_CLK <= i_clock;
+RAMB16_S1_EN <= not RamCS;
+RAMB16_S1_WE <= not MemWR;
+RAMB16_S1_SSR <= '0';
+
+o_MemAdr <= MemAdr;
+o_RamCS <= RamCS;
+o_MemOE <= MemOE;
+o_MemWR <= MemWR;
+
+o_RamAdv <= RamAdv;
+o_RamClk <= RamClk;
+o_RamCRE <= RamCRE;
+o_RamLB <= RamLB;
+o_RamUB <= RamUB;
+
+RamAdv <= '0';
+RamClk <= '0';
+RamCRE <= '0';
+RamLB <= '0';
+RamUB <= '0';
+
+p0 : process (i_clock) is
+ constant cw : integer := 1; -- XXX dont wait in bram
+ variable w : integer range 0 to cw - 1 := 0;
+ variable t : std_logic_vector(G_MemoryData-1 downto 0);
+begin
+ if (rising_edge(i_clock)) then
+ if (w > 0) then
+ w := w - 1;
+ end if;
+ case cstate is
+ when idle =>
+ if (i_enable = '1') then
+ cstate <= start; -- XXX check CSb
+ else
+ cstate <= idle;
+ end if;
+ when start =>
+ if (i_write = '1') then
+ cstate <= write_setup;
+ elsif (i_read = '1') then
+ cstate <= read_setup;
+ else
+ cstate <= start;
+ end if;
+ RamCS <= '1';
+ MemWR <= '1';
+ MemOE <= '1';
+ when write_setup =>
+ if (w = 0) then
+ cstate <= write_enable;
+ o_busy <= '1';
+ MemOE <= '1';
+ else
+ cstate <= write_setup;
+ end if;
+ when write_enable =>
+ cstate <= wait1;
+ MemWR <= '0';
+ RamCS <= '0';
+ w := cw - 1;
+ when wait1 =>
+ if (w = 0) then
+ cstate <= write_disable;
+ else
+ cstate <= wait1;
+ end if;
+ when write_disable =>
+ cstate <= stop;
+ RamCS <= '1';
+ MemWR <= '1';
+ when read_setup =>
+ if (w = 0) then
+ cstate <= read1;
+ RamCS <= '0';
+ MemOE <= '0';
+ o_busy <= '1';
+ else
+ cstate <= read_setup;
+ end if;
+ when read1 =>
+ cstate <= wait2;
+ w := cw - 1;
+ when wait2 =>
+ if (w = 0) then
+ cstate <= stop;
+ else
+ cstate <= wait2;
+ end if;
+ when stop =>
+ cstate <= idle;
+ o_busy <= '0';
+ RamCS <= '1';
+ MemOE <= '1';
+ when others => null;
+ end case;
+ end if;
+end process p0;
+
+RAMB16_S1_inst : RAMB16_S1
+generic map (
+INIT => X"0", -- Value of output RAM registers at startup
+SRVAL => X"0", -- Output value upon SSR assertion
+WRITE_MODE => "NO_CHANGE", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+port map (
+DO => RAMB16_S1_DO,
+ADDR => RAMB16_S1_ADDR,
+CLK => RAMB16_S1_CLK,
+DI => RAMB16_S1_DI,
+EN => RAMB16_S1_EN,
+SSR => RAMB16_S1_SSR,
+WE => RAMB16_S1_WE
+);
+
+end Behavioral;
diff --git a/gof/memorymodule_ramb16_s4.vhd b/gof/memorymodule_ramb16_s4.vhd
new file mode 100755
index 0000000..b435bef
--- /dev/null
+++ b/gof/memorymodule_ramb16_s4.vhd
@@ -0,0 +1,276 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:11:00 11/28/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/memorymodule/memorymodule.vhd
+-- Project Name: memorymodule
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_memory_content.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity memorymodule_ramb16_s4 is
+Port (
+i_clock : in std_logic;
+i_enable : in std_logic;
+i_write : in std_logic;
+i_read : in std_logic;
+o_busy : out std_logic;
+i_MemAdr : in MemoryAddress;
+i_MemDB : in MemoryDataByte;
+o_MemDB : out MemoryDataByte;
+o_MemOE : out std_logic;
+o_MemWR : out std_logic;
+o_RamAdv : out std_logic;
+o_RamCS : out std_logic;
+o_RamCRE : out std_logic;
+o_RamLB : out std_logic;
+o_RamUB : out std_logic;
+--i_RamWait : in std_logic;
+o_RamClk : out std_logic;
+o_MemAdr : out MemoryAddress;
+io_MemDB : inout MemoryDataByte
+);
+end memorymodule_ramb16_s4;
+
+architecture Behavioral of memorymodule_ramb16_s4 is
+
+type state is (
+idle,
+start,
+write_setup,
+read_setup,
+write_enable,
+wait1,
+write_disable,
+stop,
+read1,
+wait2
+);
+signal cstate : state;
+
+signal MemOE : std_logic;
+signal MemWR : std_logic;
+signal RamAdv : std_logic;
+signal RamCS : std_logic;
+signal RamLB : std_logic;
+signal RamCRE : std_logic;
+signal RamUB : std_logic;
+signal RamClk : std_logic;
+signal MemAdr : MemoryAddress;
+signal MemDB : MemoryDataByte;
+
+signal RAMB16_S4_DO,RAMB16_S4_DI : std_logic_vector(3 downto 0);
+signal RAMB16_S4_ADDR : std_logic_vector(11 downto 0);
+signal RAMB16_S4_CLK,RAMB16_S4_EN,RAMB16_S4_SSR,RAMB16_S4_WE : std_logic;
+
+begin
+
+RAMB16_S4_ADDR(11 downto 0) <= i_MemAdr(12 downto 1) when (RamCS = '0' and (MemWR = '0' or MemOE = '0')) else (others => 'Z');
+o_MemDB <= "0000000000000"&RAMB16_S4_DO(2 downto 0) when (cstate = idle) else (others => 'Z');
+io_MemDB <= "0000000000000"&RAMB16_S4_DO(2 downto 0) when (RamCS = '0' and MemOE = '0') else (others => 'Z');
+RAMB16_S4_DI(2 downto 0) <= i_MemDB(2 downto 0) when (RamCS = '0' and MemWR = '0') else (others => 'Z');
+RAMB16_S4_CLK <= i_clock;
+RAMB16_S4_EN <= not RamCS;
+RAMB16_S4_WE <= not MemWR;
+RAMB16_S4_SSR <= '0';
+
+o_MemAdr <= MemAdr;
+o_RamCS <= RamCS;
+o_MemOE <= MemOE;
+o_MemWR <= MemWR;
+
+o_RamAdv <= RamAdv;
+o_RamClk <= RamClk;
+o_RamCRE <= RamCRE;
+o_RamLB <= RamLB;
+o_RamUB <= RamUB;
+
+RamAdv <= '0';
+RamClk <= '0';
+RamCRE <= '0';
+RamLB <= '0';
+RamUB <= '0';
+
+p0 : process (i_clock) is
+ constant cw : integer := 1; -- XXX dont wait in bram
+ variable w : integer range 0 to cw - 1 := 0;
+ variable t : std_logic_vector(G_MemoryData-1 downto 0);
+begin
+ if (rising_edge(i_clock)) then
+ if (w > 0) then
+ w := w - 1;
+ end if;
+ case cstate is
+ when idle =>
+ if (i_enable = '1') then
+ cstate <= start; -- XXX check CSb
+ else
+ cstate <= idle;
+ end if;
+ when start =>
+ if (i_write = '1') then
+ cstate <= write_setup;
+ elsif (i_read = '1') then
+ cstate <= read_setup;
+ else
+ cstate <= start;
+ end if;
+ RamCS <= '1';
+ MemWR <= '1';
+ MemOE <= '1';
+ when write_setup =>
+ if (w = 0) then
+ cstate <= write_enable;
+ o_busy <= '1';
+ MemOE <= '1';
+ else
+ cstate <= write_setup;
+ end if;
+ when write_enable =>
+ cstate <= wait1;
+ MemWR <= '0';
+ RamCS <= '0';
+ w := cw - 1;
+ when wait1 =>
+ if (w = 0) then
+ cstate <= write_disable;
+ else
+ cstate <= wait1;
+ end if;
+ when write_disable =>
+ cstate <= stop;
+ RamCS <= '1';
+ MemWR <= '1';
+ when read_setup =>
+ if (w = 0) then
+ cstate <= read1;
+ RamCS <= '0';
+ MemOE <= '0';
+ o_busy <= '1';
+ else
+ cstate <= read_setup;
+ end if;
+ when read1 =>
+ cstate <= wait2;
+ w := cw - 1;
+ when wait2 =>
+ if (w = 0) then
+ cstate <= stop;
+ else
+ cstate <= wait2;
+ end if;
+ when stop =>
+ cstate <= idle;
+ o_busy <= '0';
+ RamCS <= '1';
+ MemOE <= '1';
+ when others => null;
+ end case;
+ end if;
+end process p0;
+
+-- RAMB16_S4: 4k x 4 Single-Port RAM
+-- Spartan-3E
+-- Xilinx HDL Libraries Guide, version 14.5
+RAMB16_S4_inst : RAMB16_S4
+generic map (
+INIT => X"0", -- Value of output RAM registers at startup
+SRVAL => X"0", -- Output value upon SSR assertion
+WRITE_MODE => "NO_CHANGE", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+port map (
+DO => RAMB16_S4_DO,
+ADDR => RAMB16_S4_ADDR,
+CLK => RAMB16_S4_CLK,
+DI => RAMB16_S4_DI,
+EN => RAMB16_S4_EN,
+SSR => RAMB16_S4_SSR,
+WE => RAMB16_S4_WE
+);
+
+end Behavioral;
diff --git a/gof/my_i2c.vhd b/gof/my_i2c.vhd
new file mode 100755
index 0000000..6ac0de3
--- /dev/null
+++ b/gof/my_i2c.vhd
@@ -0,0 +1,309 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:47:31 08/21/2020
+-- Design Name:
+-- Module Name: power_on - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_constants1.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+use ieee.std_logic_unsigned.all;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity my_i2c is
+generic(
+BOARD_CLOCK : INTEGER := G_BOARD_CLOCK;
+BUS_CLOCK : INTEGER := G_BUS_CLOCK
+);
+port(
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_slave_address : in std_logic_vector(0 to G_SLAVE_ADDRESS_SIZE-1);
+i_bytes_to_send : in std_logic_vector(0 to G_BYTE_SIZE-1);
+i_enable : in std_logic;
+o_busy : out std_logic;
+o_sda : out std_logic;
+o_scl : out std_logic
+);
+end my_i2c;
+
+architecture Behavioral of my_i2c is
+ constant I2C_COUNTER_MAX : integer := (BOARD_CLOCK / BUS_CLOCK) / 4;
+
+ signal clock : std_logic;
+ signal temp_sda : std_logic;
+ signal temp_sck : std_logic;
+ signal instruction_index : integer range 0 to 1;
+
+ type state is (idle,sda_start,start,slave_address,slave_address_lastbit,slave_rw,slave_ack,get_instruction,data,data_lastbit,data_ack,stop,sda_stop);
+ signal c_state,n_state : state;
+
+ type clock_mode is (c0,c1,c2,c3);
+ signal c_cmode,n_cmode : clock_mode;
+
+ constant SLAVE_INDEX_MAX : integer := G_SLAVE_ADDRESS_SIZE;
+ constant SDA_WIDTH_MAX : integer := 2;
+ signal data_index : integer range 0 to G_BYTE_SIZE-1;
+ signal slave_index : integer range 0 to SLAVE_INDEX_MAX-1;
+ signal sda_width: integer range 0 to SDA_WIDTH_MAX-1;
+
+begin
+
+ i2c_clock_process : process (i_clock,i_reset) is
+ variable count : integer range 0 to (I2C_COUNTER_MAX*4)-1;
+ begin
+ if (i_reset = '1') then
+ clock <= '0';
+ count := 0;
+ elsif (rising_edge(i_clock)) then
+ if (count = (I2C_COUNTER_MAX*4)-1) then
+ clock <= '1';
+ count := 0;
+ else
+ clock <= '0';
+ count := count + 1;
+ end if;
+ end if;
+ end process i2c_clock_process;
+
+ i2c_send_sequence_fsm : process (clock,i_reset,i_enable) is
+ begin
+ if (i_reset = '1') then
+ n_state <= idle;
+ n_cmode <= c0;
+ o_busy <= '0';
+ data_index <= 0;
+ slave_index <= 0;
+ sda_width <= 0;
+ temp_sda <= '1';
+ temp_sck <= '1';
+ elsif (rising_edge(clock)) then
+ c_state <= n_state;
+ c_cmode <= n_cmode;
+ case c_cmode is
+ when c0 =>
+ n_cmode <= c1;
+ when c1 =>
+ n_cmode <= c2;
+ when c2 =>
+ n_cmode <= c3;
+ when c3 =>
+ n_cmode <= c0;
+ when others => null;
+ end case;
+ case c_state is
+ when idle =>
+ if (i_enable = '1') then
+ n_state <= sda_start;
+ else
+ n_state <= idle;
+ end if;
+ when sda_start =>
+ instruction_index <= 0;
+ temp_sck <= '1';
+ temp_sda <= '1';
+ n_state <= start;
+ o_busy <= '1';
+ when start =>
+ temp_sda <= '0';
+ n_state <= slave_address;
+ when slave_address =>
+ if (c_cmode /= c1 and c_cmode /= c2 and (c_cmode = c0 or c_cmode = c3)) then
+ temp_sck <= '0';
+ end if;
+ if ((c_cmode = c1 or c_cmode = c2) and c_cmode /= c0 and c_cmode /= c3) then
+ temp_sck <= '1';
+ end if;
+ if (c_cmode = c2 and slave_index = 0) then
+ temp_sda <= '0';
+ end if;
+ if (slave_index = SLAVE_INDEX_MAX-1) then
+ n_state <= slave_address_lastbit;
+ sda_width <= 0;
+ else
+ if (c_cmode = c0) then
+ temp_sda <= i_slave_address(slave_index);
+ if (sda_width = SDA_WIDTH_MAX-1) then
+ slave_index <= slave_index + 1;
+ sda_width <= 0;
+ n_state <= slave_address;
+ else
+ sda_width <= sda_width + 1;
+ n_state <= slave_address;
+ end if;
+ end if;
+ end if;
+ when slave_address_lastbit =>
+ if (c_cmode /= c1 and c_cmode /= c2 and (c_cmode = c0 or c_cmode = c3)) then
+ temp_sck <= '0';
+ end if;
+ if ((c_cmode = c1 or c_cmode = c2) and c_cmode /= c0 and c_cmode /= c3) then
+ temp_sck <= '1';
+ end if;
+ if (c_cmode = c0) then
+ temp_sda <= i_slave_address(SLAVE_INDEX_MAX-1);
+ if (sda_width = SDA_WIDTH_MAX-1) then
+ sda_width <= 0;
+ n_state <= slave_rw;
+ else
+ sda_width <= sda_width + 1;
+ n_state <= slave_address_lastbit;
+ end if;
+ end if;
+ when slave_rw =>
+ if (c_cmode /= c1 and c_cmode /= c2 and (c_cmode = c0 or c_cmode = c3)) then
+ temp_sck <= '0';
+ end if;
+ if ((c_cmode = c1 or c_cmode = c2) and c_cmode /= c0 and c_cmode /= c3) then
+ temp_sck <= '1';
+ end if;
+ if (c_cmode = c0) then
+ temp_sda <= '0';
+ if (sda_width = SDA_WIDTH_MAX-1) then
+ sda_width <= 0;
+ n_state <= slave_ack;
+ else
+ sda_width <= sda_width + 1;
+ n_state <= slave_rw;
+ end if;
+ end if;
+ when slave_ack =>
+ if (c_cmode /= c1 and c_cmode /= c2 and (c_cmode = c0 or c_cmode = c3)) then
+ temp_sck <= '0';
+ end if;
+ if ((c_cmode = c1 or c_cmode = c2) and c_cmode /= c0 and c_cmode /= c3) then
+ temp_sck <= '1';
+ end if;
+ if (c_cmode = c0) then
+ temp_sda <= '1';
+ if (sda_width = SDA_WIDTH_MAX-1) then
+ sda_width <= 0;
+ n_state <= data;
+ else
+ sda_width <= sda_width + 1;
+ n_state <= slave_ack;
+ end if;
+ end if;
+ when get_instruction =>
+ if (i_enable = '1') then
+ n_state <= data;
+ o_busy <= '0';
+ else
+ n_state <= stop;
+ end if;
+ when data =>
+ o_busy <= '1';
+ if (c_cmode /= c1 and c_cmode /= c2 and (c_cmode = c0 or c_cmode = c3)) then
+ temp_sck <= '0';
+ end if;
+ if ((c_cmode = c1 or c_cmode = c2) and c_cmode /= c0 and c_cmode /= c3) then
+ temp_sck <= '1';
+ end if;
+ if (data_index = G_BYTE_SIZE-1) then
+ sda_width <= 0;
+ n_state <= data_lastbit;
+ else
+ if (c_cmode = c0) then
+ temp_sda <= i_bytes_to_send(data_index);
+ if (sda_width = SDA_WIDTH_MAX-1) then
+ data_index <= data_index + 1;
+ sda_width <= 0;
+ n_state <= data;
+ else
+ sda_width <= sda_width + 1;
+ n_state <= data;
+ end if;
+ end if;
+ end if;
+ when data_lastbit =>
+ if (c_cmode /= c1 and c_cmode /= c2 and (c_cmode = c0 or c_cmode = c3)) then
+ temp_sck <= '0';
+ end if;
+ if ((c_cmode = c1 or c_cmode = c2) and c_cmode /= c0 and c_cmode /= c3) then
+ temp_sck <= '1';
+ end if;
+ if (c_cmode = c0) then
+ temp_sda <= i_bytes_to_send(G_BYTE_SIZE-1);
+ if (sda_width = SDA_WIDTH_MAX-1) then
+ sda_width <= sda_width + 1;
+ n_state <= data_lastbit;
+ else
+ sda_width <= 0;
+ n_state <= data_ack;
+ end if;
+ end if;
+ when data_ack =>
+ if (c_cmode /= c1 and c_cmode /= c2 and (c_cmode = c0 or c_cmode = c3)) then
+ temp_sck <= '0';
+ end if;
+ if ((c_cmode = c1 or c_cmode = c2) and c_cmode /= c0 and c_cmode /= c3) then
+ temp_sck <= '1';
+ end if;
+ if (c_cmode = c0) then
+ temp_sda <= '1';
+ if (sda_width = SDA_WIDTH_MAX-1) then
+ instruction_index <= instruction_index + 1;
+ sda_width <= 0;
+ n_state <= get_instruction;
+ data_index <= 0;
+ else
+ sda_width <= sda_width + 1;
+ n_state <= data_ack;
+ end if;
+ end if;
+ when stop =>
+ if (c_cmode /= c1 and c_cmode /= c2 and (c_cmode = c0 or c_cmode = c3)) then
+ temp_sck <= '0';
+ end if;
+ if ((c_cmode = c1 or c_cmode = c2) and c_cmode /= c0 and c_cmode /= c3) then
+ temp_sck <= '1';
+ end if;
+ if (c_cmode = c0) then
+ temp_sda <= '0';
+ if (sda_width = SDA_WIDTH_MAX-1) then
+ sda_width <= 0;
+ n_state <= sda_stop;
+ else
+ sda_width <= sda_width + 1;
+ n_state <= stop;
+ end if;
+ end if;
+ when sda_stop =>
+ temp_sck <= '1';
+ temp_sda <= '1';
+ data_index <= 0;
+ slave_index <= 0;
+ sda_width <= 0;
+ o_busy <= '0';
+ n_state <= idle;
+ when others => null;
+ end case;
+ end if;
+ end process i2c_send_sequence_fsm;
+
+ o_sda <= '0' when temp_sda = '0' else 'Z';
+ o_scl <= '0' when temp_sck = '0' else 'Z';
+
+end architecture Behavioral;
diff --git a/gof/my_spi.vhd b/gof/my_spi.vhd
new file mode 100755
index 0000000..b904c85
--- /dev/null
+++ b/gof/my_spi.vhd
@@ -0,0 +1,135 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:12:21 06/13/2021
+-- Design Name:
+-- Module Name: my_spi - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.st7735r_p_package.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity my_spi is
+generic (
+ C_CLOCK_COUNTER : integer := 50_000_000
+);
+port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_enable : in std_logic;
+ i_data_byte : in BYTE_TYPE;
+ o_cs : out std_logic;
+ o_do : out std_logic;
+ o_ck : out std_logic;
+ o_sended : out std_logic
+);
+end my_spi;
+
+architecture Behavioral of my_spi is
+ signal clock_divider,clock_data : std_logic;
+ signal data_index : integer range BYTE_SIZE - 1 downto 0;
+ signal ck : std_logic;
+begin
+--XXX 50mhz - when send byte : cs=0 = 640ns,ck period = 80ns
+
+ o_cs <= '0' when i_enable = '1' else '1';
+ o_do <= i_data_byte(BYTE_SIZE - 1 - data_index) when i_enable = '1' else '0';
+ o_sended <= '1' when (data_index = BYTE_SIZE - 1 and i_enable = '1') else '0';
+
+ p0 : process (i_clock,i_reset) is
+ variable clock_counter : integer range 0 to C_CLOCK_COUNTER - 1 := 0;
+ begin
+ if (i_reset = '1') then
+ clock_counter := 0;
+ clock_divider <= '0';
+ elsif (rising_edge(i_clock)) then
+ if (i_enable = '1') then
+ if (clock_counter = C_CLOCK_COUNTER/4 - 1) then
+ clock_divider <= not clock_divider;
+ clock_counter := 0;
+ else
+ clock_divider <= clock_divider;
+ clock_counter := clock_counter + 1;
+ end if;
+ else
+ clock_divider <= '0';
+ clock_counter := 0;
+ end if;
+ end if;
+ end process p0;
+
+ p1 : process (clock_divider,i_reset) is
+ begin
+ if (i_reset = '1') then
+ ck <= '0';
+ elsif (rising_edge(clock_divider)) then
+ if (i_enable = '1') then
+ ck <= not ck;
+ else
+ ck <= '0';
+ end if;
+ end if;
+ end process p1;
+ o_ck <= ck;
+
+ p2 : process (clock_data,i_reset) is
+ begin
+ if (i_reset = '1') then
+ data_index <= 0;
+ elsif (rising_edge(clock_data)) then
+ if (i_enable = '1') then
+ if (data_index = BYTE_SIZE - 1) then
+ data_index <= 0;
+ else
+ data_index <= data_index + 1;
+ end if;
+ else
+ data_index <= 0;
+ end if;
+ end if;
+ end process p2;
+
+ p3 : process (clock_divider,i_reset) is
+ constant cd : integer := 2;
+ variable d : integer range 0 to cd - 1;
+ begin
+ if (i_reset = '1') then
+ clock_data <= '0';
+ d := 0;
+ elsif (rising_edge(clock_divider)) then
+ if (i_enable = '1') then
+ if (d = cd - 1) then
+ clock_data <= '1';
+ d := 0;
+ else
+ clock_data <= '0';
+ d := d + 1;
+ end if;
+ else
+ clock_data <= '0';
+ d := 0;
+ end if;
+ end if;
+ end process p3;
+end Behavioral;
diff --git a/gof/oled_display.vhd b/gof/oled_display.vhd
new file mode 100755
index 0000000..5ae4e0d
--- /dev/null
+++ b/gof/oled_display.vhd
@@ -0,0 +1,398 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:47:49 08/21/2020
+-- Design Name:
+-- Module Name: test_oled - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use WORK.p_constants1.ALL;
+
+entity oled_display is
+generic
+(
+GLOBAL_CLK : integer := 50_000_000;
+I2C_CLK : integer := 100_000;
+WIDTH_O : integer := 128;
+HEIGHT_O : integer := 32;
+W_BITS : integer := 7;
+H_BITS : integer := 5;
+BYTE_SIZE : integer := 8);
+port
+(
+signal i_clk : in std_logic;
+signal i_rst : in std_logic;
+signal i_clear : in std_logic;
+signal i_draw : in std_logic;
+signal i_x : in std_logic_vector(W_BITS-1 downto 0);
+signal i_y : in std_logic_vector(H_BITS-1 downto 0);
+signal i_byte : in std_logic_vector(BYTE_SIZE-1 downto 0);
+signal i_all_pixels : in std_logic;
+signal o_busy : out std_logic;
+signal o_display_initialize : inout std_logic;
+--signal o_busy : out std_logic;
+signal io_sda,io_scl : inout std_logic);
+end oled_display;
+
+architecture Behavioral of oled_display is
+
+constant WIDTH : integer := 128; -- XXX
+constant HEIGHT : integer := 4; -- XXX
+
+constant OLED_PAGES_ALL : integer := WIDTH * HEIGHT;
+constant OLED_DATA : integer := to_integer(unsigned'(x"40"));
+constant OLED_COMMAND : integer := to_integer(unsigned'(x"00")); -- 00,80
+constant COUNTER_WAIT1 : integer := 1;
+
+constant NI_INIT : natural := 26;
+type A_INIT is array (0 to NI_INIT-1) of std_logic_vector(BYTE_SIZE-1 downto 0);
+signal init_display : A_INIT :=
+(
+ x"AE" -- display off
+,x"D5",x"80" -- setdisplayclockdiv
+,x"A8",x"1F" -- 00-0f/10-1f - Set Lower Column Start Address for Page Addressing Mode
+,x"D3",x"00" -- display offset
+,x"40" -- set start line
+,x"8D",x"14" -- chargepump
+,x"20",x"10" -- Set Memory Addressing Mode
+,x"A1",x"C8" -- A0/A1,C0/C8 - start from specify four display corner - a0|a1 - segremap , c0|c8 - comscandec
+,x"DA",x"02" -- setcompins
+,x"81",x"8F" -- contrast
+,x"D9",x"F1" -- precharge
+,x"DB",x"40" -- setvcomdetect
+,x"A4" -- displayon resume
+,x"A6" -- normal display
+,x"2E" -- scroll off
+,x"AF" -- display on
+);
+
+constant NI_SET_COORDINATION : natural := 6;
+type A_SET_COORDINATION is array (0 to NI_SET_COORDINATION-1) of std_logic_vector(BYTE_SIZE-1 downto 0);
+signal set_coordination_00 : A_SET_COORDINATION :=
+(x"21",x"00",std_logic_vector(to_unsigned(WIDTH-1,BYTE_SIZE))
+,x"22",x"00",std_logic_vector(to_unsigned(HEIGHT-1,BYTE_SIZE)));
+
+component my_i2c is
+generic(
+BOARD_CLOCK : INTEGER := GLOBAL_CLK;
+BUS_CLOCK : INTEGER := I2C_CLK
+);
+port(
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_slave_address : in std_logic_vector(0 to G_SLAVE_ADDRESS_SIZE-1);
+i_bytes_to_send : in std_logic_vector(0 to G_BYTE_SIZE-1);
+i_enable : in std_logic;
+o_busy : out std_logic;
+o_sda : out std_logic;
+o_scl : out std_logic
+);
+end component my_i2c;
+
+type state is
+(
+ oled_reset,
+ idle,
+ start, -- initialize oled
+ wait0,
+ set_address_1, -- set begin point 0,0
+ wait1, -- wait after initialize
+ send_character, -- send the some data in loop
+ send_character1,
+ wait2, -- disable i2c and wait between transition coordination
+ wait3,
+ set_coordinations,
+ set_address_2, -- set begin point 0,0
+ clear_display_state, -- clear display
+ stop -- when index=counter, i2c disable
+);
+signal c_state : state;
+
+SIGNAL i2c_ena : STD_LOGIC; --i2c enable signal
+SIGNAL i2c_addr : STD_LOGIC_VECTOR(6 DOWNTO 0); --i2c address signal
+SIGNAL i2c_rw : STD_LOGIC; --i2c read/write command signal
+SIGNAL i2c_data_wr : STD_LOGIC_VECTOR(7 DOWNTO 0); --i2c write data
+SIGNAL i2c_busy : STD_LOGIC; --i2c busy signal
+SIGNAL i2c_reset : STD_LOGIC; --i2c busy signal
+SIGNAL busy_prev : STD_LOGIC; --previous value of i2c busy signal
+SIGNAL busy_cnt : INTEGER; -- for i2c, count the clk tick when i2c_busy=1
+
+signal counter : integer range 0 to COUNTER_WAIT1-1;
+signal coord_prev_x : std_logic_vector(W_BITS-1 downto 0);
+signal coord_prev_y : std_logic_vector(H_BITS-1 downto 0);
+
+begin
+
+i2c_addr <= "0111100";
+
+c0 : my_i2c
+GENERIC MAP
+(
+ BOARD_CLOCK => GLOBAL_CLK,
+ BUS_CLOCK => I2C_CLK
+)
+PORT MAP
+(
+ i_clock => i_clk,
+ i_reset => i2c_reset,
+ i_enable => i2c_ena,
+ i_slave_address => i2c_addr,
+ i_bytes_to_send => i2c_data_wr,
+ o_busy => i2c_busy,
+ o_sda => io_sda,
+ o_scl => io_scl
+);
+
+p0 : process (i_clk,i_rst) is
+begin
+ if (i_rst = '1') then
+ c_state <= oled_reset;
+ busy_cnt <= 0;
+ counter <= 0;
+ coord_prev_x <= (others => '0');
+ coord_prev_y <= (others => '0');
+ o_busy <= '0';
+ elsif (rising_edge(i_clk)) then
+ if (i_all_pixels = '1') then
+ c_state <= stop;
+ end if;
+ if (counter > 0) then
+ counter <= counter - 1;
+ end if;
+ case c_state is
+ when oled_reset =>
+ c_state <= start;
+ i2c_reset <= '1';
+ when idle =>
+ busy_cnt <= 0;
+ i2c_reset <= '0';
+ if (i_all_pixels = '1') then
+ c_state <= idle;
+ else
+ if (o_display_initialize = '1') then
+ c_state <= wait0;
+ else
+ c_state <= start;
+ end if;
+ end if;
+ when start =>
+ i2c_reset <= '0';
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_reset <= '0';
+ i2c_ena <= '1'; -- we are busy
+ when 1 =>
+ i2c_data_wr <= std_logic_vector(to_unsigned(OLED_COMMAND,BYTE_SIZE));
+ when 2 to NI_INIT+1 =>
+ i2c_data_wr <= init_display(busy_cnt-2); -- command
+ when NI_INIT+2 =>
+ i2c_ena <= '0';
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ c_state <= set_address_2;
+ end if;
+ when others => null;
+ end case;
+ when set_address_2 =>
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ when 1 =>
+ i2c_data_wr <= std_logic_vector(to_unsigned(OLED_COMMAND,BYTE_SIZE));
+ when 2 to NI_SET_COORDINATION+1 =>
+ i2c_data_wr <= set_coordination_00(busy_cnt-2); -- command
+ when NI_SET_COORDINATION+2 =>
+ i2c_ena <= '0';
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ c_state <= clear_display_state;
+ end if;
+ when others => null;
+ end case;
+ when clear_display_state =>
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ when 1 =>
+ i2c_data_wr <= std_logic_vector(to_unsigned(OLED_DATA,BYTE_SIZE));
+ when 2 to OLED_PAGES_ALL+1 => -- XXX
+ i2c_data_wr <= x"00"; -- command - FF/allpixels,00/blank,F0/zebra
+ when OLED_PAGES_ALL+2 => -- XXX
+ i2c_ena <= '0';
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ c_state <= wait0;
+ end if;
+ when others => null;
+ end case;
+ when wait0 =>
+ o_display_initialize <= '1';
+ if (i_all_pixels = '1') then
+ c_state <= wait0;
+ else
+ c_state <= set_address_1;
+ end if;
+ when set_address_1 =>
+ o_busy <= '0';
+ coord_prev_x <= std_logic_vector(to_unsigned(0,W_BITS));
+ coord_prev_y <= std_logic_vector(to_unsigned(0,H_BITS));
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ when 1 =>
+ i2c_data_wr <= std_logic_vector(to_unsigned(OLED_COMMAND,BYTE_SIZE));
+ when 2 to NI_SET_COORDINATION+1 =>
+ i2c_data_wr <= set_coordination_00(busy_cnt-2); -- command
+ when NI_SET_COORDINATION+2 =>
+ i2c_ena <= '0';
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ c_state <= wait1;
+ o_display_initialize <= '1';
+ end if;
+ when others => null;
+ end case;
+ when wait1 =>
+ i2c_ena <= '0';
+ o_busy <= '0';
+ if (counter = 0) then
+ c_state <= send_character;
+ end if;
+ when send_character =>
+ o_busy <= '1';
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ when 1 =>
+ i2c_data_wr <= std_logic_vector(to_unsigned(OLED_DATA,BYTE_SIZE));
+ when 2 =>
+ i2c_data_wr <= i_byte;
+ when 3 =>
+ i2c_ena <= '0';
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ c_state <= wait3; --wait2;
+ counter <= COUNTER_WAIT1-1;
+ end if;
+ when others => null;
+ end case;
+ when wait2 =>
+ i2c_ena <= '0';
+ o_busy <= '0';
+ coord_prev_x <= i_x;
+ coord_prev_y <= i_y;
+ busy_cnt <= 0;
+ if (counter = 0) then
+ if (coord_prev_y /= i_y) then
+ c_state <= wait3; --wait1;
+ busy_cnt <= 0;
+ counter <= COUNTER_WAIT1-1;
+ else
+ if (coord_prev_x /= i_x) then
+ c_state <= send_character;
+ end if;
+ end if;
+ end if;
+ when wait3 =>
+ o_busy <= '1';
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ when 1 =>
+ i2c_data_wr <= std_logic_vector(to_unsigned(OLED_COMMAND,BYTE_SIZE));
+ when 2 =>
+ i2c_data_wr <= x"22";
+ when 3 =>
+ i2c_data_wr <= std_logic_vector(to_unsigned(0,BYTE_SIZE-H_BITS))&i_y; -- XXX
+ when 4 =>
+-- i2c_data_wr <= std_logic_vector(to_unsigned(HEIGHT-1,BYTE_SIZE));
+ i2c_data_wr <= std_logic_vector(to_unsigned(0,BYTE_SIZE-H_BITS))&i_y; -- XXX
+ when 5 =>
+ i2c_data_wr <= x"21";
+ when 6 =>
+ i2c_data_wr <= std_logic_vector(to_unsigned(0,BYTE_SIZE-W_BITS))&i_x; -- XXX
+ when 7 =>
+-- i2c_data_wr <= std_logic_vector(to_unsigned(WIDTH-1,BYTE_SIZE));
+ i2c_data_wr <= std_logic_vector(to_unsigned(0,BYTE_SIZE-W_BITS))&i_x; -- XXX
+ when 8 =>
+ i2c_ena <= '0';
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ counter <= COUNTER_WAIT1-1;
+ c_state <= send_character1;
+ o_busy <= '0';
+ end if;
+ when others => null;
+ end case;
+ when send_character1 =>
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ i2c_addr <= "0111100"; -- address 3C 3D 78 ; 0111100 0111101 1111000
+ i2c_rw <= '0';
+ i2c_data_wr <= std_logic_vector(to_unsigned(OLED_DATA,BYTE_SIZE));
+ o_busy <= '1';
+ when 1 =>
+ i2c_data_wr <= i_byte;
+ when 2 =>
+ i2c_ena <= '0';
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ c_state <= wait1;
+ o_busy <= '0';
+ end if;
+ when others => null;
+ end case;
+ when stop =>
+ i2c_ena <= '0';
+ c_state <= wait0;--idle;
+ busy_cnt <= 0;
+ i2c_reset <= '0';
+ when others => null;
+ end case;
+ end if;
+end process p0;
+
+end Behavioral;
diff --git a/gof/p_constants1.vhd b/gof/p_constants1.vhd
new file mode 100755
index 0000000..5457f63
--- /dev/null
+++ b/gof/p_constants1.vhd
@@ -0,0 +1,14 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package p_constants1 is
+ constant G_BOARD_CLOCK : INTEGER := 50_000_000;
+ constant G_BUS_CLOCK : INTEGER := 100_000;
+ constant G_BYTE_SIZE : integer := 8;
+ constant G_SLAVE_ADDRESS_SIZE : integer := 7;
+
+ type array1 is array(natural range <>) of std_logic_vector(7 downto 0);
+end p_constants1;
+
+package body p_constants1 is
+end p_constants1;
diff --git a/gof/p_globals.vhd b/gof/p_globals.vhd
new file mode 100755
index 0000000..cf94e11
--- /dev/null
+++ b/gof/p_globals.vhd
@@ -0,0 +1,9 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package p_globals is
+end p_globals;
+
+package body p_globals is
+end p_globals;
+
diff --git a/gof/p_gof_logic.vhd b/gof/p_gof_logic.vhd
new file mode 100755
index 0000000..76421e3
--- /dev/null
+++ b/gof/p_gof_logic.vhd
@@ -0,0 +1,63 @@
+--
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+--
+-- To use any of the example code shown below, uncomment the lines and modify as necessary
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use WORK.p_memory_content.ALL;
+
+package p_gof_logic is
+
+end p_gof_logic;
+
+package body p_gof_logic is
+
+end p_gof_logic;
+
+-- type is
+-- record
+-- : std_logic_vector( 7 downto 0);
+-- : std_logic;
+-- end record;
+--
+-- Declare constants
+--
+-- constant : time := ns;
+-- constant : integer := (signal : in ) return ;
+-- procedure ( : in );
+--
+
+---- Example 1
+-- function (signal : in ) return is
+-- variable : ;
+-- begin
+-- := xor ;
+-- return ;
+-- end ;
+
+---- Example 2
+-- function (signal : in ;
+-- signal : in ) return is
+-- begin
+-- if ( = '1') then
+-- return ;
+-- else
+-- return 'Z';
+-- end if;
+-- end ;
+
+---- Procedure Example
+-- procedure ( : in ) is
+--
+-- begin
+--
+-- end ;
diff --git a/gof/p_memory_content.vhd b/gof/p_memory_content.vhd
new file mode 100755
index 0000000..533fd13
--- /dev/null
+++ b/gof/p_memory_content.vhd
@@ -0,0 +1,575 @@
+--
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+--
+-- To use any of the example code shown below, uncomment the lines and modify as necessary
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package p_memory_content is
+
+-- constant G_BOARD_CLOCK : integer := 50_000_000;
+-- constant G_BUS_CLOCK : integer := 100_000;
+ constant G_ClockDivider : integer := 10000;
+ constant G_MemoryAddress : integer := 24; --17;
+ constant G_MemoryData : integer := 16; --3;
+ constant G_HalfHex : integer := 4;
+ constant G_FullHex : integer := G_HalfHex*2;
+-- constant ROWS : integer := 128;
+-- constant ROWS_BITS : integer := 7;
+-- constant COLS_PIXEL : integer := 32;
+-- constant COLS_PIXEL_BITS : integer := 5;
+-- constant COLS_BLOCK : integer := 4;
+-- constant COLS_BLOCK_BITS : integer := 2;
+-- constant BYTE_BITS : integer := 8;
+-- constant WORD_BITS : integer := COLS_BLOCK*BYTE_BITS;
+ constant G_LCDSegment : integer := 7;
+ constant G_LCDAnode : integer := 4;
+ constant G_LCDClockDivider : integer := 200;
+-- constant G_Button : integer := 4;
+-- constant G_Led : integer := 8;
+ type LCDHex is array(G_LCDAnode-1 downto 0) of std_logic_vector(G_HalfHex-1 downto 0);
+-- type LiveSubArray is array(WORD_BITS-1 downto 0) of std_logic_vector(2 downto 0);
+-- type LiveArrayType is array(ROWS-1 downto 0) of LiveSubArray;
+
+-- constant ROWS : integer := 160; --16; --128;
+-- constant ROWS_BITS : integer := 8; --7;
+-- constant COLS_PIXEL : integer := 128; --32; --160;
+-- constant COLS_PIXEL_BITS : integer := 7; --5;
+-- constant COLS_BLOCK : integer := 4;
+-- constant COLS_BLOCK_BITS : integer := 2;
+
+ constant ROWS : integer := 16; --16; --128;
+ constant ROWS_BITS : integer := 4; --7;
+ constant COLS_PIXEL : integer := 32; --32; --160;
+ constant COLS_PIXEL_BITS : integer := 5; --5;
+ constant COLS_BLOCK : integer := 4;
+ constant COLS_BLOCK_BITS : integer := 2;
+ constant BYTE_BITS : integer := 8;
+ constant WORD_BITS : integer := COLS_BLOCK*BYTE_BITS;
+ constant PARITY_BITS : integer := 4;
+ constant BRAM_ADDRESS_BITS : integer := 9;
+ subtype MemoryAddressALL is std_logic_vector(0 to G_MemoryAddress-1);
+-- subtype MemoryAddress is std_logic_vector(1 to G_MemoryAddress-1);
+-- subtype MemoryDataByte is std_logic_vector(0 to G_MemoryData-1);
+ subtype MemoryAddress is std_logic_vector(G_MemoryAddress-1 downto 1);
+ subtype MemoryDataByte is std_logic_vector(G_MemoryData-1 downto 0);
+
+-- subtype WORD is std_logic_vector(COLS_PIXEL-1 downto 0);
+-- type MEMORY is array(ROWS-1 downto 0) of WORD;
+ subtype WORD is std_logic_vector(0 to WORD_BITS-1);
+ type MEMORY is array(0 to ROWS-1) of WORD;
+
+-- https://www.conwaylife.com/patterns/gosperglidergun.cells
+-- !Name: Gosper glider gun
+-- !Author: Bill Gosper
+-- !The first known gun and the first known finite pattern with unbounded growth.
+-- !www.conwaylife.com/wiki/index.php?title=Gosper_glider_gun
+-- ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-- ........................O...........
+-- ......................O.O...........
+-- ............OO......OO............OO
+-- ...........O...O....OO............OO
+-- OO........O.....O...OO..............
+-- OO........O...O.OO....O.O...........
+-- ..........O.....O.......O...........
+-- ...........O...O....................
+-- ............OO......................
+-- ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+
+
+-- constant memory_content : MEMORY :=
+-- ( -- f 0f 0
+-- ("11111111111111111111111111111111"), -- F
+-- ("10010000000010011001000000001001"),
+-- ("10010000000010011001000000001001"),
+-- ("10010001100010011001000110001001"),
+-- ("10000001100000011000000110000001"),
+-- ("10000001100000011000000110000001"),
+-- ("10011101101110011001110110111001"),
+-- ("10111000000111011011100000011101"), -- 8
+-- ("10000001100000011000000110000001"), -- 7
+-- ("10000001100000011000000110000001"),
+-- ("10110001100011011011000110001101"),
+-- ("10110001100011011011000110001101"),
+-- ("10001100001100011000110000110001"),
+-- ("10001100001100011000110000110001"),
+-- ("10000000000000011000000000000001"), -- 1
+-- ("11111111111111111111111111111111"), -- 0
+-- ("11111111111111111111111111111111"), -- F
+-- ("10010000000010011001000000001001"),
+-- ("10010000000010011001000000001001"),
+-- ("10010001100010011001000110001001"),
+-- ("10000001100000011000000110000001"),
+-- ("10000001100000011000000110000001"),
+-- ("10011101101110011001110110111001"),
+-- ("10111000000111011011100000011101"), -- 8
+-- ("10000001100000011000000110000001"), -- 7
+-- ("10000001100000011000000110000001"),
+-- ("10110001100011011011000110001101"),
+-- ("10110001100011011011000110001101"),
+-- ("10001100001100011000110000110001"),
+-- ("10001100001100011000110000110001"),
+-- ("10000000000000011000000000000001"), -- 1
+-- ("11111111111111111111111111111111"), -- 0
+-- ("11111111111111111111111111111111"), -- F
+-- ("10010000000010011001000000001001"),
+-- ("10010000000010011001000000001001"),
+-- ("10010001100010011001000110001001"),
+-- ("10000001100000011000000110000001"),
+-- ("10000001100000011000000110000001"),
+-- ("10011101101110011001110110111001"),
+-- ("10111000000111011011100000011101"), -- 8
+-- ("10000001100000011000000110000001"), -- 7
+-- ("10000001100000011000000110000001"),
+-- ("10110001100011011011000110001101"),
+-- ("10110001100011011011000110001101"),
+-- ("10001100001100011000110000110001"),
+-- ("10001100001100011000110000110001"),
+-- ("10000000000000011000000000000001"), -- 1
+-- ("11111111111111111111111111111111"), -- 0
+-- ("11111111111111111111111111111111"), -- F
+-- ("10010000000010011001000000001001"),
+-- ("10010000000010011001000000001001"),
+-- ("10010001100010011001000110001001"),
+-- ("10000001100000011000000110000001"),
+-- ("10000001100000011000000110000001"),
+-- ("10011101101110011001110110111001"),
+-- ("10111000000111011011100000011101"), -- 8
+-- ("10000001100000011000000110000001"), -- 7
+-- ("10000001100000011000000110000001"),
+-- ("10110001100011011011000110001101"),
+-- ("10110001100011011011000110001101"),
+-- ("10001100001100011000110000110001"),
+-- ("10001100001100011000110000110001"),
+-- ("10000000000000011000000000000001"), -- 1
+-- ("11111111111111111111111111111111"), -- 0
+-- ("11111111111111111111111111111111"), -- F
+-- ("10010000000010011001000000001001"),
+-- ("10010000000010011001000000001001"),
+-- ("10010001100010011001000110001001"),
+-- ("10000001100000011000000110000001"),
+-- ("10000001100000011000000110000001"),
+-- ("10011101101110011001110110111001"),
+-- ("10111000000111011011100000011101"), -- 8
+-- ("10000001100000011000000110000001"), -- 7
+-- ("10000001100000011000000110000001"),
+-- ("10110001100011011011000110001101"),
+-- ("10110001100011011011000110001101"),
+-- ("10001100001100011000110000110001"),
+-- ("10001100001100011000110000110001"),
+-- ("10000000000000011000000000000001"), -- 1
+-- ("11111111111111111111111111111111"), -- 0
+-- ("11111111111111111111111111111111"), -- F
+-- ("10010000000010011001000000001001"),
+-- ("10010000000010011001000000001001"),
+-- ("10010001100010011001000110001001"),
+-- ("10000001100000011000000110000001"),
+-- ("10000001100000011000000110000001"),
+-- ("10011101101110011001110110111001"),
+-- ("10111000000111011011100000011101"), -- 8
+-- ("10000001100000011000000110000001"), -- 7
+-- ("10000001100000011000000110000001"),
+-- ("10110001100011011011000110001101"),
+-- ("10110001100011011011000110001101"),
+-- ("10001100001100011000110000110001"),
+-- ("10001100001100011000110000110001"),
+-- ("10000000000000011000000000000001"), -- 1
+-- ("11111111111111111111111111111111"), -- 0
+-- ("11111111111111111111111111111111"), -- F
+-- ("10010000000010011001000000001001"),
+-- ("10010000000010011001000000001001"),
+-- ("10010001100010011001000110001001"),
+-- ("10000001100000011000000110000001"),
+-- ("10000001100000011000000110000001"),
+-- ("10011101101110011001110110111001"),
+-- ("10111000000111011011100000011101"), -- 8
+-- ("10000001100000011000000110000001"), -- 7
+-- ("10000001100000011000000110000001"),
+-- ("10110001100011011011000110001101"),
+-- ("10110001100011011011000110001101"),
+-- ("10001100001100011000110000110001"),
+-- ("10001100001100011000110000110001"),
+-- ("10000000000000011000000000000001"), -- 1
+-- ("11111111111111111111111111111111"), -- 0
+-- ("11111111111111111111111111111111"), -- F
+-- ("10010000000010011001000000001001"),
+-- ("10010000000010011001000000001001"),
+-- ("10010001100010011001000110001001"),
+-- ("10000001100000011000000110000001"),
+-- ("10000001100000011000000110000001"),
+-- ("10011101101110011001110110111001"),
+-- ("10111000000111011011100000011101"), -- 8
+-- ("10000001100000011000000110000001"), -- 7
+-- ("10000001100000011000000110000001"),
+-- ("10110001100011011011000110001101"),
+-- ("10110001100011011011000110001101"),
+-- ("10001100001100011000110000110001"),
+-- ("10001100001100011000110000110001"),
+-- ("10000000000000011000000000000001"), -- 1
+-- ("11111111111111111111111111111111") -- 0
+
+-- constant memory_content : MEMORY :=
+-- (
+-- ("00000000000000000000000000000000"),
+-- ("00000000000000000000000000000000"),
+-- ("00000000000000000000000000000000"),
+-- ("00000000000000000000000000000000"),
+-- ("00000000000000000000000000000000"),
+-- ("00000000000000000000000000000000"),
+-- ("00000000000000000000000000000000"),
+-- ("00000000000000000000000000000000"),
+-- ("00000000000000000000000000000000"),
+-- ("00000000000000000000000000000000"),
+-- ("00000000000000000000000000000000"),
+-- ("00000000000000000000000000000010"),
+-- ("00000000000000000000000000000010"),
+-- ("00000000000000000000000000000010"),
+-- ("00000000000000000000000000000000"),
+-- ("00000000000000000000000000000000")
+-- );
+
+ constant memory_content : MEMORY :=
+ (
+ ("11111111111111111111111111111111"),
+ ("10000000000000000000000000000001"),
+ ("10000000000000000000000010000001"),
+ ("10000000000000000000001010000001"),
+ ("10000000000011000000110000000001"),
+ ("10000000000100010000110000000001"),
+ ("11000000001000001000110000000001"),
+ ("11000000001000101100001010000001"),
+ ("10000000001000001000000010000001"),
+ ("10000000000100010000000000000001"),
+ ("10000000000011000000000000000001"),
+ ("10000000000000000000000000000001"),
+ ("10000000000000000000000000000001"),
+ ("10000000000000000000000000000001"),
+ ("10000000000000000000000000000001"),
+ ("11111111111111111111111111111111")
+ );
+
+-- constant memory_content : MEMORY :=
+-- (
+-- ("00000000000000000000000000000000"),
+-- ("00000000000000000000000000000000"),
+-- ("00000000000000000000000010000000"),
+-- ("00000000000000000000001010000000"),
+-- ("00000000000011000000110000000000"),
+-- ("00000000000100010000110000000000"),
+-- ("11000000001000001000110000000000"),
+-- ("11000000001000101100001010000000"),
+-- ("00000000001000001000000010000000"),
+-- ("00000000000100010000000000000000"),
+-- ("00000000000011000000000000000000"),
+-- ("00000000000000000000000000000000"),
+-- ("00000000000000000000000000000000"),
+-- ("00000000000000000000000000000000"),
+-- ("00000000000000000000000000000000"),
+-- ("00000000000000000000000000000000")
+-- );
+
+-- constant memory_content : MEMORY :=
+-- (
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000"),
+-- ("0000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000"),
+-- ("0000000000001100000011000000000000000000000011000000110000000000000000000000110000001100000000000000000000001100000011000000000000000000000011000000110000000000"),
+-- ("0000000000010001000011000000000000000000000100010000110000000000000000000001000100001100000000000000000000010001000011000000000000000000000100010000110000000000"),
+-- ("1100000000100000100011000000000011000000001000001000110000000000110000000010000010001100000000001100000000100000100011000000000011000000001000001000110000000000"),
+-- ("1100000000100010110000101000000011000000001000101100001010000000110000000010001011000010100000001100000000100010110000101000000011000000001000101100001010000000"),
+-- ("0000000000100000100000001000000000000000001000001000000010000000000000000010000010000000100000000000000000100000100000001000000000000000001000001000000010000000"),
+-- ("0000000000010001000000000000000000000000000100010000000000000000000000000001000100000000000000000000000000010001000000000000000000000000000100010000000000000000"),
+-- ("0000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000"),
+-- ("0000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000"),
+-- ("0000000000001100000011000000000000000000000011000000110000000000000000000000110000001100000000000000000000001100000011000000000000000000000011000000110000000000"),
+-- ("0000000000010001000011000000000000000000000100010000110000000000000000000001000100001100000000000000000000010001000011000000000000000000000100010000110000000000"),
+-- ("1100000000100000100011000000000011000000001000001000110000000000110000000010000010001100000000001100000000100000100011000000000011000000001000001000110000000000"),
+-- ("1100000000100010110000101000000011000000001000101100001010000000110000000010001011000010100000001100000000100010110000101000000011000000001000101100001010000000"),
+-- ("0000000000100000100000001000000000000000001000001000000010000000000000000010000010000000100000000000000000100000100000001000000000000000001000001000000010000000"),
+-- ("0000000000010001000000000000000000000000000100010000000000000000000000000001000100000000000000000000000000010001000000000000000000000000000100010000000000000000"),
+-- ("0000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000"),
+-- ("0000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000"),
+-- ("0000000000001100000011000000000000000000000011000000110000000000000000000000110000001100000000000000000000001100000011000000000000000000000011000000110000000000"),
+-- ("0000000000010001000011000000000000000000000100010000110000000000000000000001000100001100000000000000000000010001000011000000000000000000000100010000110000000000"),
+-- ("1100000000100000100011000000000011000000001000001000110000000000110000000010000010001100000000001100000000100000100011000000000011000000001000001000110000000000"),
+-- ("1100000000100010110000101000000011000000001000101100001010000000110000000010001011000010100000001100000000100010110000101000000011000000001000101100001010000000"),
+-- ("0000000000100000100000001000000000000000001000001000000010000000000000000010000010000000100000000000000000100000100000001000000000000000001000001000000010000000"),
+-- ("0000000000010001000000000000000000000000000100010000000000000000000000000001000100000000000000000000000000010001000000000000000000000000000100010000000000000000"),
+-- ("0000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000"),
+-- ("0000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000"),
+-- ("0000000000001100000011000000000000000000000011000000110000000000000000000000110000001100000000000000000000001100000011000000000000000000000011000000110000000000"),
+-- ("0000000000010001000011000000000000000000000100010000110000000000000000000001000100001100000000000000000000010001000011000000000000000000000100010000110000000000"),
+-- ("1100000000100000100011000000000011000000001000001000110000000000110000000010000010001100000000001100000000100000100011000000000011000000001000001000110000000000"),
+-- ("1100000000100010110000101000000011000000001000101100001010000000110000000010001011000010100000001100000000100010110000101000000011000000001000101100001010000000"),
+-- ("0000000000100000100000001000000000000000001000001000000010000000000000000010000010000000100000000000000000100000100000001000000000000000001000001000000010000000"),
+-- ("0000000000010001000000000000000000000000000100010000000000000000000000000001000100000000000000000000000000010001000000000000000000000000000100010000000000000000"),
+-- ("0000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000"),
+-- ("0000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000"),
+-- ("0000000000001100000011000000000000000000000011000000110000000000000000000000110000001100000000000000000000001100000011000000000000000000000011000000110000000000"),
+-- ("0000000000010001000011000000000000000000000100010000110000000000000000000001000100001100000000000000000000010001000011000000000000000000000100010000110000000000"),
+-- ("1100000000100000100011000000000011000000001000001000110000000000110000000010000010001100000000001100000000100000100011000000000011000000001000001000110000000000"),
+-- ("1100000000100010110000101000000011000000001000101100001010000000110000000010001011000010100000001100000000100010110000101000000011000000001000101100001010000000"),
+-- ("0000000000100000100000001000000000000000001000001000000010000000000000000010000010000000100000000000000000100000100000001000000000000000001000001000000010000000"),
+-- ("0000000000010001000000000000000000000000000100010000000000000000000000000001000100000000000000000000000000010001000000000000000000000000000100010000000000000000"),
+-- ("0000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000"),
+-- ("0000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000"),
+-- ("0000000000001100000011000000000000000000000011000000110000000000000000000000110000001100000000000000000000001100000011000000000000000000000011000000110000000000"),
+-- ("0000000000010001000011000000000000000000000100010000110000000000000000000001000100001100000000000000000000010001000011000000000000000000000100010000110000000000"),
+-- ("1100000000100000100011000000000011000000001000001000110000000000110000000010000010001100000000001100000000100000100011000000000011000000001000001000110000000000"),
+-- ("1100000000100010110000101000000011000000001000101100001010000000110000000010001011000010100000001100000000100010110000101000000011000000001000101100001010000000"),
+-- ("0000000000100000100000001000000000000000001000001000000010000000000000000010000010000000100000000000000000100000100000001000000000000000001000001000000010000000"),
+-- ("0000000000010001000000000000000000000000000100010000000000000000000000000001000100000000000000000000000000010001000000000000000000000000000100010000000000000000"),
+-- ("0000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000"),
+-- ("0000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000"),
+-- ("0000000000001100000011000000000000000000000011000000110000000000000000000000110000001100000000000000000000001100000011000000000000000000000011000000110000000000"),
+-- ("0000000000010001000011000000000000000000000100010000110000000000000000000001000100001100000000000000000000010001000011000000000000000000000100010000110000000000"),
+-- ("1100000000100000100011000000000011000000001000001000110000000000110000000010000010001100000000001100000000100000100011000000000011000000001000001000110000000000"),
+-- ("1100000000100010110000101000000011000000001000101100001010000000110000000010001011000010100000001100000000100010110000101000000011000000001000101100001010000000"),
+-- ("0000000000100000100000001000000000000000001000001000000010000000000000000010000010000000100000000000000000100000100000001000000000000000001000001000000010000000"),
+-- ("0000000000010001000000000000000000000000000100010000000000000000000000000001000100000000000000000000000000010001000000000000000000000000000100010000000000000000"),
+-- ("0000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000"),
+-- ("0000000000000000000000101000000000000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000"),
+-- ("0000000000001100000011000000000000000000000011000000110000000000000000000000110000001100000000000000000000001100000011000000000000000000000011000000110000000000"),
+-- ("0000000000010001000011000000000000000000000100010000110000000000000000000001000100001100000000000000000000010001000011000000000000000000000100010000110000000000"),
+-- ("1100000000100000100011000000000011000000001000001000110000000000110000000010000010001100000000001100000000100000100011000000000011000000001000001000110000000000"),
+-- ("1100000000100010110000101000000011000000001000101100001010000000110000000010001011000010100000001100000000100010110000101000000011000000001000101100001010000000"),
+-- ("0000000000100000100000001000000000000000001000001000000010000000000000000010000010000000100000000000000000100000100000001000000000000000001000001000000010000000"),
+-- ("0000000000010001000000000000000000000000000100010000000000000000000000000001000100000000000000000000000000010001000000000000000000000000000100010000000000000000"),
+-- ("0000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
+-- );
+
+-- constant memory_content : MEMORY :=
+-- (
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000"),
+-- ("00000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000"),
+-- ("00000000000011000000110000000000000000000000110000001100000000000000000000001100000011000000000000000000000011000000110000000000"),
+-- ("00000000000100010000110000000000000000000001000100001100000000000000000000010001000011000000000000000000000100010000110000000000"),
+-- ("11000000001000001000110000000000110000000010000010001100000000001100000000100000100011000000000011000000001000001000110000000000"),
+-- ("11000000001000101100001010000000110000000010001011000010100000001100000000100010110000101000000011000000001000101100001010000000"),
+-- ("00000000001000001000000010000000000000000010000010000000100000000000000000100000100000001000000000000000001000001000000010000000"),
+-- ("00000000000100010000000000000000000000000001000100000000000000000000000000010001000000000000000000000000000100010000000000000000"),
+-- ("00000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000"),
+-- ("00000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000"),
+-- ("00000000000011000000110000000000000000000000110000001100000000000000000000001100000011000000000000000000000011000000110000000000"),
+-- ("00000000000100010000110000000000000000000001000100001100000000000000000000010001000011000000000000000000000100010000110000000000"),
+-- ("11000000001000001000110000000000110000000010000010001100000000001100000000100000100011000000000011000000001000001000110000000000"),
+-- ("11000000001000101100001010000000110000000010001011000010100000001100000000100010110000101000000011000000001000101100001010000000"),
+-- ("00000000001000001000000010000000000000000010000010000000100000000000000000100000100000001000000000000000001000001000000010000000"),
+-- ("00000000000100010000000000000000000000000001000100000000000000000000000000010001000000000000000000000000000100010000000000000000"),
+-- ("00000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000"),
+-- ("00000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000"),
+-- ("00000000000011000000110000000000000000000000110000001100000000000000000000001100000011000000000000000000000011000000110000000000"),
+-- ("00000000000100010000110000000000000000000001000100001100000000000000000000010001000011000000000000000000000100010000110000000000"),
+-- ("11000000001000001000110000000000110000000010000010001100000000001100000000100000100011000000000011000000001000001000110000000000"),
+-- ("11000000001000101100001010000000110000000010001011000010100000001100000000100010110000101000000011000000001000101100001010000000"),
+-- ("00000000001000001000000010000000000000000010000010000000100000000000000000100000100000001000000000000000001000001000000010000000"),
+-- ("00000000000100010000000000000000000000000001000100000000000000000000000000010001000000000000000000000000000100010000000000000000"),
+-- ("00000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000"),
+-- ("00000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000"),
+-- ("00000000000011000000110000000000000000000000110000001100000000000000000000001100000011000000000000000000000011000000110000000000"),
+-- ("00000000000100010000110000000000000000000001000100001100000000000000000000010001000011000000000000000000000100010000110000000000"),
+-- ("11000000001000001000110000000000110000000010000010001100000000001100000000100000100011000000000011000000001000001000110000000000"),
+-- ("11000000001000101100001010000000110000000010001011000010100000001100000000100010110000101000000011000000001000101100001010000000"),
+-- ("00000000001000001000000010000000000000000010000010000000100000000000000000100000100000001000000000000000001000001000000010000000"),
+-- ("00000000000100010000000000000000000000000001000100000000000000000000000000010001000000000000000000000000000100010000000000000000"),
+-- ("00000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000"),
+-- ("00000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000"),
+-- ("00000000000011000000110000000000000000000000110000001100000000000000000000001100000011000000000000000000000011000000110000000000"),
+-- ("00000000000100010000110000000000000000000001000100001100000000000000000000010001000011000000000000000000000100010000110000000000"),
+-- ("11000000001000001000110000000000110000000010000010001100000000001100000000100000100011000000000011000000001000001000110000000000"),
+-- ("11000000001000101100001010000000110000000010001011000010100000001100000000100010110000101000000011000000001000101100001010000000"),
+-- ("00000000001000001000000010000000000000000010000010000000100000000000000000100000100000001000000000000000001000001000000010000000"),
+-- ("00000000000100010000000000000000000000000001000100000000000000000000000000010001000000000000000000000000000100010000000000000000"),
+-- ("00000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000"),
+-- ("00000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000"),
+-- ("00000000000011000000110000000000000000000000110000001100000000000000000000001100000011000000000000000000000011000000110000000000"),
+-- ("00000000000100010000110000000000000000000001000100001100000000000000000000010001000011000000000000000000000100010000110000000000"),
+-- ("11000000001000001000110000000000110000000010000010001100000000001100000000100000100011000000000011000000001000001000110000000000"),
+-- ("11000000001000101100001010000000110000000010001011000010100000001100000000100010110000101000000011000000001000101100001010000000"),
+-- ("00000000001000001000000010000000000000000010000010000000100000000000000000100000100000001000000000000000001000001000000010000000"),
+-- ("00000000000100010000000000000000000000000001000100000000000000000000000000010001000000000000000000000000000100010000000000000000"),
+-- ("00000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000"),
+-- ("00000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000"),
+-- ("00000000000011000000110000000000000000000000110000001100000000000000000000001100000011000000000000000000000011000000110000000000"),
+-- ("00000000000100010000110000000000000000000001000100001100000000000000000000010001000011000000000000000000000100010000110000000000"),
+-- ("11000000001000001000110000000000110000000010000010001100000000001100000000100000100011000000000011000000001000001000110000000000"),
+-- ("11000000001000101100001010000000110000000010001011000010100000001100000000100010110000101000000011000000001000101100001010000000"),
+-- ("00000000001000001000000010000000000000000010000010000000100000000000000000100000100000001000000000000000001000001000000010000000"),
+-- ("00000000000100010000000000000000000000000001000100000000000000000000000000010001000000000000000000000000000100010000000000000000"),
+-- ("00000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000"),
+-- ("00000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000"),
+-- ("00000000000011000000110000000000000000000000110000001100000000000000000000001100000011000000000000000000000011000000110000000000"),
+-- ("00000000000100010000110000000000000000000001000100001100000000000000000000010001000011000000000000000000000100010000110000000000"),
+-- ("11000000001000001000110000000000110000000010000010001100000000001100000000100000100011000000000011000000001000001000110000000000"),
+-- ("11000000001000101100001010000000110000000010001011000010100000001100000000100010110000101000000011000000001000101100001010000000"),
+-- ("00000000001000001000000010000000000000000010000010000000100000000000000000100000100000001000000000000000001000001000000010000000"),
+-- ("00000000000100010000000000000000000000000001000100000000000000000000000000010001000000000000000000000000000100010000000000000000"),
+-- ("00000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000"),
+-- ("00000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000"),
+-- ("00000000000011000000110000000000000000000000110000001100000000000000000000001100000011000000000000000000000011000000110000000000"),
+-- ("00000000000100010000110000000000000000000001000100001100000000000000000000010001000011000000000000000000000100010000110000000000"),
+-- ("11000000001000001000110000000000110000000010000010001100000000001100000000100000100011000000000011000000001000001000110000000000"),
+-- ("11000000001000101100001010000000110000000010001011000010100000001100000000100010110000101000000011000000001000101100001010000000"),
+-- ("00000000001000001000000010000000000000000010000010000000100000000000000000100000100000001000000000000000001000001000000010000000"),
+-- ("00000000000100010000000000000000000000000001000100000000000000000000000000010001000000000000000000000000000100010000000000000000"),
+-- ("00000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000"),
+-- ("00000000000000000000001010000000000000000000000000000010100000000000000000000000000000101000000000000000000000000000001010000000"),
+-- ("00000000000011000000110000000000000000000000110000001100000000000000000000001100000011000000000000000000000011000000110000000000"),
+-- ("00000000000100010000110000000000000000000001000100001100000000000000000000010001000011000000000000000000000100010000110000000000"),
+-- ("11000000001000001000110000000000110000000010000010001100000000001100000000100000100011000000000011000000001000001000110000000000"),
+-- ("11000000001000101100001010000000110000000010001011000010100000001100000000100010110000101000000011000000001000101100001010000000"),
+-- ("00000000001000001000000010000000000000000010000010000000100000000000000000100000100000001000000000000000001000001000000010000000"),
+-- ("00000000000100010000000000000000000000000001000100000000000000000000000000010001000000000000000000000000000100010000000000000000"),
+-- ("00000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"),
+-- ("00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
+-- );
+
+end p_memory_content;
+
+package body p_memory_content is
+end p_memory_content;
diff --git a/gof/p_spi.vhd b/gof/p_spi.vhd
new file mode 100755
index 0000000..64848c5
--- /dev/null
+++ b/gof/p_spi.vhd
@@ -0,0 +1,85 @@
+--
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+--
+-- To use any of the example code shown below, uncomment the lines and modify as necessary
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package p_spi is
+
+ -- XXX for simulation
+-- shared variable data_rom_index : integer;
+-- constant R_EDGE : std_logic := '1';
+-- constant F_EDGE : std_logic := '0';
+-- shared variable data_temp : std_logic_vector(0 to BYTE_SIZE-1);
+-- shared variable data_temp_index : integer;
+-- constant Xs : std_logic_vector(0 to BYTE_SIZE - 1) := (others => 'U');
+
+-- function vec2str(vec: std_logic_vector) return string;
+--
+-- procedure check_test(
+-- signal cs : in std_logic;
+-- signal do : in std_logic;
+-- signal ck : in std_logic);
+
+end p_spi;
+
+package body p_spi is
+
+ -- XXX for simulation
+-- function vec2str(vec: std_logic_vector) return string is
+-- variable result: string(0 to vec'right);
+-- begin
+-- for i in vec'range loop
+-- if (vec(i) = '1') then
+-- result(i) := '1';
+-- elsif (vec(i) = '0') then
+-- result(i) := '0';
+-- elsif (vec(i) = 'X') then
+-- result(i) := 'X';
+-- elsif (vec(i) = 'U') then
+-- result(i) := 'U';
+-- else
+-- result(i) := '?';
+-- end if;
+-- end loop;
+-- return result;
+-- end;
+--
+ -- XXX for simulation
+-- procedure check_test(
+-- signal cs : in std_logic;
+-- signal do : in std_logic;
+-- signal ck : in std_logic
+-- ) is
+-- begin
+-- if ((ck'event and ck = R_EDGE) and cs = '0') then
+-- data_temp(data_temp_index) := do;
+-- if (data_temp_index = BYTE_SIZE - 1) then
+-- data_temp_index := 0;
+-- else
+-- data_temp_index := data_temp_index + 1;
+-- end if;
+-- elsif (cs'event and cs = R_EDGE) then
+-- assert (data_rom(data_rom_index) = data_temp)
+-- report "FAIL : (" & integer'image(data_rom_index) & ") " & vec2str(data_temp) & " expect " & vec2str(data_rom(data_rom_index)) severity note;
+-- assert (data_rom(data_rom_index) /= data_temp)
+-- report "OK : (" & integer'image(data_rom_index) & ") " & vec2str(data_temp) & " equals " & vec2str(data_rom(data_rom_index)) severity note;
+-- data_temp_index := 0;
+-- if (data_rom_index = data_size - 1) then
+-- data_rom_index := 0;
+-- assert (false) report "=== END TEST ===" severity note;
+-- else
+-- if (data_temp /= Xs) then -- XXX omit first undefined/uninitialized
+-- data_rom_index := data_rom_index + 1;
+-- end if;
+-- end if;
+-- end if;
+-- end procedure check_test;
+
+end p_spi;
diff --git a/gof/simulate-st7735r_tb_top.sh b/gof/simulate-st7735r_tb_top.sh
new file mode 100755
index 0000000..5720141
--- /dev/null
+++ b/gof/simulate-st7735r_tb_top.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+PROJECT="st7735r_tb_top"
+fuse -intstyle ise -incremental -o ./${PROJECT}_isim_beh.exe -prj ./${PROJECT}_beh.prj work.${PROJECT}
+./${PROJECT}_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb ./${PROJECT}_isim.beh.wdb -view ./${PROJECT}.wcfg
diff --git a/gof/simulate-tb_clock_divider.sh b/gof/simulate-tb_clock_divider.sh
new file mode 100755
index 0000000..7a253a0
--- /dev/null
+++ b/gof/simulate-tb_clock_divider.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+PROJECT="tb_clock_divider"
+fuse -intstyle ise -incremental -o ./${PROJECT}_isim_beh.exe -prj ./${PROJECT}_beh.prj work.${PROJECT}
+./${PROJECT}_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb ./${PROJECT}_isim.beh.wdb -view ./${PROJECT}.wcfg
diff --git a/gof/simulate-tb_memory1_bit.sh b/gof/simulate-tb_memory1_bit.sh
new file mode 100755
index 0000000..0013033
--- /dev/null
+++ b/gof/simulate-tb_memory1_bit.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+PROJECT="tb_memory1_bit"
+fuse -intstyle ise -incremental -o ./${PROJECT}_isim_beh.exe -prj ./${PROJECT}_beh.prj work.${PROJECT}
+./${PROJECT}_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb ./${PROJECT}_isim.beh.wdb -view ./${PROJECT}.wcfg
diff --git a/gof/simulate-tb_memory1_byte.sh b/gof/simulate-tb_memory1_byte.sh
new file mode 100755
index 0000000..746b793
--- /dev/null
+++ b/gof/simulate-tb_memory1_byte.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+PROJECT="tb_memory1_byte"
+fuse -intstyle ise -incremental -o ./${PROJECT}_isim_beh.exe -prj ./${PROJECT}_beh.prj work.${PROJECT}
+./${PROJECT}_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb ./${PROJECT}_isim.beh.wdb -view ./${PROJECT}.wcfg
diff --git a/gof/simulate-tb_memory2.sh b/gof/simulate-tb_memory2.sh
new file mode 100755
index 0000000..734153d
--- /dev/null
+++ b/gof/simulate-tb_memory2.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+PROJECT="tb_memory2"
+fuse -intstyle ise -incremental -o ./${PROJECT}_isim_beh.exe -prj ./${PROJECT}_beh.prj work.${PROJECT}
+./${PROJECT}_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb ./${PROJECT}_isim.beh.wdb -view ./${PROJECT}.wcfg
diff --git a/gof/ssd1306_gof.vhd b/gof/ssd1306_gof.vhd
new file mode 100755
index 0000000..c88771e
--- /dev/null
+++ b/gof/ssd1306_gof.vhd
@@ -0,0 +1,702 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:11:54 09/04/2020
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_memory_content.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity ssd1306_gof is
+generic(
+INPUT_CLOCK : integer := 50_000_000;
+--BUS_CLOCK : integer := 6_000_000; -- increase for speed i2c --XXX scl period=1.28us,start=0.96us,stop=0.16us
+BUS_CLOCK : integer := 100_000; --original
+DIVIDER_CLOCK : integer := 1
+);
+port(
+signal clk : in std_logic;
+signal btn_1 : in std_logic;
+signal btn_2 : in std_logic;
+signal btn_3 : in std_logic;
+signal sda,scl : inout std_logic
+);
+end ssd1306_gof;
+
+architecture Behavioral of ssd1306_gof is
+
+component oled_display is
+generic(
+GLOBAL_CLK : integer;
+I2C_CLK : integer;
+WIDTH_O : integer;
+HEIGHT_O : integer;
+W_BITS : integer;
+H_BITS : integer;
+BYTE_SIZE : integer);
+port(
+signal i_clk : in std_logic;
+signal i_rst : in std_logic;
+signal i_clear : in std_logic;
+signal i_draw : in std_logic;
+signal i_x : in std_logic_vector(W_BITS-1 downto 0);
+signal i_y : in std_logic_vector(H_BITS-1 downto 0);
+signal i_byte : in std_logic_vector(BYTE_SIZE-1 downto 0);
+signal i_all_pixels : in std_logic;
+signal o_display_initialize : inout std_logic;
+signal o_busy : out std_logic;
+signal io_sda,io_scl : inout std_logic);
+end component oled_display;
+
+component BUFG
+port (I : in std_logic;
+O : out std_logic);
+end component;
+
+component clock_divider is
+Port(
+i_clk : in STD_LOGIC;
+i_board_clock : in INTEGER;
+i_divider : in INTEGER;
+o_clk : out STD_LOGIC
+);
+end component clock_divider;
+
+component memory1 is
+Port (
+i_clk : in std_logic;
+i_reset : in std_logic;
+i_copy_content : in std_logic;
+o_copy_content : out std_logic;
+i_enable_byte : in std_logic;
+i_enable_bit : in std_logic;
+i_write_byte : in std_logic;
+i_write_bit : in std_logic;
+i_row : in std_logic_vector(ROWS_BITS-1 downto 0);
+i_col_pixel : in std_logic_vector(COLS_PIXEL_BITS-1 downto 0);
+i_col_block : in std_logic_vector(COLS_BLOCK_BITS-1 downto 0);
+i_byte : in std_logic_vector(BYTE_BITS-1 downto 0);
+i_bit : in std_logic;
+o_byte : out std_logic_vector(BYTE_BITS-1 downto 0);
+o_bit : out std_logic);
+end component memory1;
+
+component RAMB16_S4
+generic (
+WRITE_MODE : string := "NO_CHANGE" ; -- WRITE_FIRST(default)/ READ_FIRST/NO_CHANGE
+INIT : bit_vector(3 downto 0) := X"0";
+SRVAL : bit_vector(3 downto 0) := X"0"
+);
+port (
+DI : in std_logic_vector (3 downto 0);
+ADDR : in std_logic_vector (11 downto 0);
+EN : in STD_LOGIC;
+WE : in STD_LOGIC;
+SSR : in STD_LOGIC;
+CLK : in STD_LOGIC;
+DO : out std_logic_vector (3 downto 0)
+);
+end component;
+
+signal row : std_logic_vector(ROWS_BITS-1 downto 0) := (others => '0');
+signal col_pixel : std_logic_vector(COLS_PIXEL_BITS-1 downto 0) := (others => '0');
+signal col_block : std_logic_vector(COLS_BLOCK_BITS-1 downto 0) := (others => '0');
+signal rst : std_logic;
+signal all_pixels : std_logic;
+signal clk_1s : std_logic;
+signal display_byte : std_logic_vector(BYTE_BITS-1 downto 0);
+signal display_initialize : std_logic;
+signal o_bit : std_logic;
+signal i_reset : std_logic;
+signal display_busy : std_logic;
+
+signal i_mem_e_byte : std_logic;
+signal i_mem_e_bit : std_logic;
+signal i_mem_write_bit : std_logic;
+signal i_bit : std_logic;
+signal i_copy_content,o_copy_content : std_logic;
+
+signal CLK_BUFG : std_logic;
+
+signal DATA_IN : std_logic_vector(3 downto 0);
+signal ADDRESS : std_logic_vector(11 downto 0);
+signal ENABLE : std_logic;
+signal WRITE_EN : std_logic;
+signal DATA_OUT : std_logic_vector(3 downto 0);
+
+type state is (
+idle,
+display_is_initialize,
+memory_enable_byte,
+aaa,
+waitone,
+waitone1,
+update_row,
+update_col,
+set_cd_calculate,
+memory_disable_byte,
+reset_counters_1,
+check_coordinations,
+reset_count_alive,
+memory_enable_bit,
+set_c1a,set_c2a,set_c3a,set_c4a,set_c5a,set_c6a,set_c7a,set_c8a,
+set_c1,c1,set_c2,c2,set_c3,c3,set_c4,c4,set_c5,c5,set_c6,c6,set_c7,c7,set_c8,c8,
+c1_end,c2_end,c3_end,c4_end,c5_end,c6_end,c7_end,c8_end,
+waitfor,
+memory_disable_bit,
+store_count_alive,
+update_row1,
+update_col1,
+reset_counters1,
+memory_enable_bit1,
+get_alive,
+get_alive1,
+bbb,
+enable_write_to_memory,
+set_coords_to_write,
+write_count_alive,
+disable_write_to_memory,
+update_row2,
+update_col2,
+disable_memory,
+stop);
+signal cstate : state;
+
+constant W : integer := 1;
+signal waiting : integer range W-1 downto 0 := 0;
+signal ppX : std_logic_vector(ROWS_BITS-1 downto 0);
+signal ppYb : std_logic_vector(COLS_BLOCK_BITS-1 downto 0);
+signal ppYp : std_logic_vector(COLS_PIXEL_BITS-1 downto 0);
+signal ppXm1 : std_logic_vector(ROWS_BITS-1 downto 0);
+signal ppXp1 : std_logic_vector(ROWS_BITS-1 downto 0);
+signal ppYm1 : std_logic_vector(COLS_PIXEL_BITS-1 downto 0);
+signal ppYp1 : std_logic_vector(COLS_PIXEL_BITS-1 downto 0);
+signal oppX : std_logic_vector(ROWS_BITS-1 downto 0);
+signal oppY : std_logic_vector(COLS_PIXEL_BITS-1 downto 0);
+signal countAlive : std_logic_vector(3 downto 0);
+signal CellAlive : std_logic;
+signal CD : integer := DIVIDER_CLOCK*1_000;
+signal CD_DISPLAY : integer := DIVIDER_CLOCK*1_0; -- XXX
+signal CD_CALCULATE : integer := DIVIDER_CLOCK*100_000; -- XXX
+
+function To_Std_Logic(x_vot : BOOLEAN) return std_ulogic is
+begin
+ if x_vot then
+ return('1');
+ else
+ return('0');
+ end if;
+end function To_Std_Logic;
+
+begin
+
+U_BUFG: BUFG
+port map (
+I => clk,
+O => CLK_BUFG
+);
+
+i_reset <= btn_1;
+
+U_RAMB16_S4: RAMB16_S4
+generic map (
+WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST/READ_FIRST/NO_CHANGE
+INIT => X"0",
+SRVAL => X"0"
+)
+port map (
+DI => DATA_IN,
+ADDR => ADDRESS,
+EN => ENABLE,
+WE => WRITE_EN,
+SSR => i_reset,
+CLK => CLK_BUFG,
+DO => DATA_OUT
+);
+
+clk_div : clock_divider
+port map (
+ i_clk => CLK_BUFG,
+ i_board_clock => INPUT_CLOCK,
+ i_divider => CD,
+ o_clk => clk_1s
+);
+
+c0 : oled_display
+generic map (
+ GLOBAL_CLK => INPUT_CLOCK,
+ I2C_CLK => BUS_CLOCK,
+ WIDTH_O => ROWS,
+ HEIGHT_O => COLS_BLOCK,
+ W_BITS => ROWS_BITS,
+ H_BITS => COLS_BLOCK_BITS,
+ BYTE_SIZE => BYTE_BITS)
+port map (
+ i_clk => CLK_BUFG,
+ i_rst => i_reset,
+ i_clear => btn_2,
+ i_draw => btn_3,
+ i_x => row,
+ i_y => col_block,
+ i_byte => display_byte,
+ i_all_pixels => all_pixels,
+ o_display_initialize => display_initialize,
+ o_busy => display_busy,
+ io_sda => sda,
+ io_scl => scl
+);
+
+m1 : memory1
+port map (
+ i_clk => CLK_BUFG,
+ i_reset => i_reset,
+ i_copy_content => i_copy_content,
+ o_copy_content => o_copy_content,
+ i_enable_byte => i_mem_e_byte,
+ i_enable_bit => i_mem_e_bit,
+ i_write_byte => '0',
+ i_write_bit => i_mem_write_bit,
+ i_row => row,
+ i_col_pixel => col_pixel,
+ i_col_block => col_block,
+ i_byte => (others => 'X'),
+ i_bit => i_bit,
+ o_byte => display_byte,
+ o_bit => o_bit
+);
+
+gof_logic : process (CLK_BUFG,i_reset) is
+ constant W : integer := 10;
+ variable waiting : integer range W-1 downto 0 := 0;
+ variable vppX : integer;-- range 0 to ROWS-1;
+ variable vppYb : integer;-- range 0 to COLS_BLOCK-1;
+ variable vppYp : integer;-- range 0 to COLS_PIXEL-1;
+ variable vppXm1 : integer;-- range -1 to ROWS-1;
+ variable vppXp1 : integer;-- range 0 to ROWS;
+ variable vppYm1 : integer;-- range -1 to COLS_PIXEL-1;
+ variable vppYp1 : integer;-- range 0 to COLS_PIXEL;
+ variable vcountAlive : integer range 0 to 7;
+ variable vCellAlive : boolean;
+begin
+ if (i_reset = '1') then
+ all_pixels <= '0';
+ cstate <= idle;
+ vCellAlive := false;
+ vcountAlive := 0;
+ vppX := 0;
+ vppYb := 0;
+ vppYp := 0;
+ vppXm1 := 0;
+ vppXp1 := 0;
+ vppYm1 := 0;
+ vppYp1 := 0;
+ i_copy_content <= '0';
+ i_mem_e_byte <= '0';
+ i_mem_e_bit <= '0';
+ i_mem_write_bit <= '0';
+ i_bit <= '0';
+ elsif (rising_edge(CLK_BUFG)) then
+ case cstate is
+ -- draw
+ when idle =>
+ if (display_initialize = '1') then
+ cstate <= display_is_initialize;
+ else
+ cstate <= idle;
+ end if;
+ all_pixels <= '0';
+ when display_is_initialize =>
+ cstate <= memory_enable_byte;
+ vppX := 0;
+ vppYb := 0;
+ vppYp := 0;
+ when memory_enable_byte =>
+ cstate <= aaa;
+ i_mem_e_byte <= '1';
+ waiting := W-1;
+ CD <= CD_DISPLAY;
+ when aaa =>
+ if (display_busy = '0') then
+ cstate <= aaa;
+ else
+ cstate <= waitone;
+ end if;
+ when waitone =>
+ cstate <= waitone1;
+ row <= ppX;
+ col_block <= ppYb;
+ when waitone1 =>
+ if (display_busy = '1') then
+ cstate <= waitone1;
+ else
+ cstate <= update_row;
+ end if;
+ when update_row =>
+ if (vppX = ROWS - 1) then
+ cstate <= update_col;
+ else
+ vppX := vppX + 1;
+ cstate <= waitone;
+ waiting := W-1;
+ end if;
+ when update_col =>
+ if (vppYb = COLS_BLOCK - 1) then
+ cstate <= set_cd_calculate;
+ vppYb := 0;
+ vppX := 0;
+ else
+ vppYb := vppYb + 1;
+ cstate <= waitone;
+ waiting := W-1;
+ vppX := 0;
+ end if;
+ when set_cd_calculate =>
+ cstate <= memory_disable_byte;
+ CD <= CD_CALCULATE;
+ when memory_disable_byte =>
+ cstate <= reset_counters_1;
+ i_mem_e_byte <= '0';
+ -- calculate cells
+ when reset_counters_1 =>
+ cstate <= check_coordinations;
+ all_pixels <= '1';
+ vppX := 0;
+ vppYb := 0;
+ vppYp := 0;
+ when check_coordinations =>
+ cstate <= memory_enable_bit;
+ vppXm1 := vppX - 1;
+ if (vppXm1 < 0) then
+ vppXm1 := 0; -- ROWS - 1
+ end if;
+ vppXp1 := vppX + 1;
+ if (vppXp1 > ROWS - 1) then
+ vppXp1 := ROWS - 1; -- 0
+ end if;
+ vppYm1 := vppYp - 1;
+ if (vppYm1 < 0) then
+ vppYm1 := 0; -- COLS_PIXEL - 1
+ end if;
+ vppYp1 := vppYp+1;
+ if (vppYp1 > COLS_PIXEL - 1) then
+ vppYp1 := COLS_PIXEL - 1; -- 0
+ end if;
+ when memory_enable_bit =>
+ cstate <= reset_count_alive;
+ i_mem_e_bit <= '1';
+ i_mem_write_bit <= '0';
+ when reset_count_alive =>
+ cstate <= set_c1a;
+ vcountAlive := 0;
+ countAlive <= (others => '0');
+ when set_c1a =>
+ cstate <= set_c1;
+ i_mem_e_bit <= '1';
+ i_mem_write_bit <= '0';
+ when set_c1 =>
+ cstate <= c1;
+ row <= ppX;
+ col_pixel <= ppYm1;
+ when c1 =>
+ cstate <= c1_end;
+ if (vppYp /= 0) then
+ if (o_bit = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+-- countAlive <= std_logic_vector(to_unsigned(vcountALive,4));
+ end if;
+ when c1_end =>
+ cstate <= set_c2a;
+ i_mem_e_bit <= '0';
+ i_mem_write_bit <= '0';
+ when set_c2a =>
+ cstate <= set_c2;
+ i_mem_e_bit <= '1';
+ i_mem_write_bit <= '0';
+ when set_c2 =>
+ cstate <= c2;
+ row <= ppX;
+ col_pixel <= ppYp1;
+ when c2 =>
+ cstate <= c2_end;
+ if (vppYp /= COLS_PIXEL-1) then
+ if (o_bit = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+-- countAlive <= std_logic_vector(to_unsigned(vcountALive,4));
+ end if;
+ when c2_end =>
+ cstate <= set_c3a;
+ i_mem_e_bit <= '0';
+ i_mem_write_bit <= '0';
+ when set_c3a =>
+ cstate <= set_c3;
+ i_mem_e_bit <= '1';
+ i_mem_write_bit <= '0';
+ when set_c3 =>
+ cstate <= c3;
+ row <= ppXp1;
+ col_pixel <= ppYp;
+ when c3 =>
+ cstate <= c3_end;
+ if (vppX /= ROWS-1) then
+ if (o_bit = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+-- countAlive <= std_logic_vector(to_unsigned(vcountALive,4));
+ end if;
+ when c3_end =>
+ cstate <= set_c4a;
+ i_mem_e_bit <= '0';
+ i_mem_write_bit <= '0';
+ when set_c4a =>
+ cstate <= set_c4;
+ i_mem_e_bit <= '1';
+ i_mem_write_bit <= '0';
+ when set_c4 =>
+ cstate <= c4;
+ row <= ppXm1;
+ col_pixel <= ppYp;
+ when c4 =>
+ cstate <= c4_end;
+ if (vppX /= 0) then
+ if (o_bit = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+-- countAlive <= std_logic_vector(to_unsigned(vcountALive,4));
+ end if;
+ when c4_end =>
+ cstate <= set_c5a;
+ i_mem_e_bit <= '0';
+ i_mem_write_bit <= '0';
+ when set_c5a =>
+ cstate <= set_c5;
+ i_mem_e_bit <= '1';
+ i_mem_write_bit <= '0';
+ when set_c5 =>
+ cstate <= c5;
+ row <= ppXm1;
+ col_pixel <= ppYm1;
+ when c5 =>
+ cstate <= c5_end;
+ if ((vppX /= 0) and (vppYp /= 0)) then
+ if (o_bit = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+-- countAlive <= std_logic_vector(to_unsigned(vcountALive,4));
+ end if;
+ when c5_end =>
+ cstate <= set_c6a;
+ i_mem_e_bit <= '0';
+ i_mem_write_bit <= '0';
+ when set_c6a =>
+ cstate <= set_c6;
+ i_mem_e_bit <= '1';
+ i_mem_write_bit <= '0';
+ when set_c6 =>
+ cstate <= c6;
+ row <= ppXp1;
+ col_pixel <= ppYm1;
+ when c6 =>
+ cstate <= c6_end;
+ if ((vppX /= ROWS-1) and (vppYp /= 0)) then
+ if (o_bit = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+-- countAlive <= std_logic_vector(to_unsigned(vcountALive,4));
+ end if;
+ when c6_end =>
+ cstate <= set_c7a;
+ i_mem_e_bit <= '0';
+ i_mem_write_bit <= '0';
+ when set_c7a =>
+ cstate <= set_c7;
+ i_mem_e_bit <= '1';
+ i_mem_write_bit <= '0';
+ when set_c7 =>
+ cstate <= c7;
+ row <= ppXm1;
+ col_pixel <= ppYp1;
+ when c7 =>
+ cstate <= c7_end;
+ if ((vppX /= 0) and (vppYp /= COLS_PIXEL-1)) then
+ if (o_bit = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+-- countAlive <= std_logic_vector(to_unsigned(vcountALive,4));
+ end if;
+ when c7_end =>
+ cstate <= set_c8a;
+ i_mem_e_bit <= '0';
+ i_mem_write_bit <= '0';
+ when set_c8a =>
+ cstate <= set_c8;
+ i_mem_e_bit <= '1';
+ i_mem_write_bit <= '0';
+ when set_c8 =>
+ cstate <= c8;
+ row <= ppXp1;
+ col_pixel <= ppYp1;
+ when c8 =>
+ cstate <= c8_end;
+ if ((vppX /= ROWS-1) and (vppYp /= COLS_PIXEL-1)) then
+ if (o_bit = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+-- countAlive <= std_logic_vector(to_unsigned(vcountALive,4));
+ end if;
+ when c8_end =>
+ cstate <= waitfor;
+ i_mem_e_bit <= '0';
+ i_mem_write_bit <= '0';
+ when waitfor =>
+ cstate <= memory_disable_bit;
+ countAlive <= std_logic_vector(to_unsigned(vcountALive,4));
+ when memory_disable_bit =>
+ cstate <= store_count_alive;
+ i_mem_e_bit <= '0';
+ ENABLE <= '1';
+ WRITE_EN <= '1';
+ when store_count_alive =>
+ cstate <= update_row1;
+ ADDRESS <= std_logic_vector(to_unsigned(vppX+vppYp*WORD_BITS,12));
+ DATA_IN <= countAlive;
+ report "store_count_alive " & integer'image(to_integer(unsigned(ppX))) & "," & integer'image(to_integer(unsigned(ppYp)));
+ when update_row1 =>
+ ENABLE <= '0';
+ WRITE_EN <= '0';
+ if (vppX = ROWS - 1) then
+ cstate <= update_col1;
+ else
+ vppX := vppX + 1;
+ cstate <= check_coordinations;
+ end if;
+ when update_col1 =>
+ if (vppYp = COLS_PIXEL - 1) then
+ cstate <= reset_counters1;
+ vppYp := 0;
+ else
+ vppYp := vppYp + 1;
+ cstate <= check_coordinations;
+ vppX := 0;
+ end if;
+ -- store bits in memory
+ when reset_counters1 =>
+ cstate <= memory_enable_bit1;
+ vppX := 0;
+ vppYb := 0;
+ vppYp := 0;
+ when memory_enable_bit1 =>
+ cstate <= get_alive;
+ i_mem_e_bit <= '1';
+ i_mem_write_bit <= '0';
+ when get_alive =>
+ cstate <= get_alive1;
+ row <= ppX;
+ col_pixel <= ppYp;
+ when get_alive1 =>
+ cstate <= bbb;
+ if (o_bit = '1') then
+ vCellAlive := true;
+ else
+ vCellAlive := false;
+ end if;
+ report "get_alive1 " & integer'image(to_integer(unsigned(ppX))) & "," & integer'image(to_integer(unsigned(ppYp)));
+ ENABLE <= '1';
+ WRITE_EN <= '0';
+ when bbb =>
+ cstate <= enable_write_to_memory;
+ i_mem_e_bit <= '0';
+ i_mem_write_bit <= '0';
+ when enable_write_to_memory =>
+ cstate <= write_count_alive;
+ i_mem_e_bit <= '1';
+ i_mem_write_bit <= '1';
+ ADDRESS <= std_logic_vector(to_unsigned(vppX+vppYp*WORD_BITS,12));
+ report "enable_write_to_memory " & integer'image(to_integer(unsigned(ppX))) & "," & integer'image(to_integer(unsigned(ppYp)));
+ i_bit <= '0';
+ row <= ppX;
+ col_pixel <= ppYp;
+ when write_count_alive =>
+ cstate <= disable_write_to_memory;
+ if (vCellAlive = true) then
+ if ((to_integer(unsigned(DATA_OUT)) = 2) or (to_integer(unsigned(DATA_OUT)) = 3)) then
+ i_bit <= '1';
+ else
+ i_bit <= '0';
+ end if;
+ elsif (vCellAlive = false) then
+ if (to_integer(unsigned(DATA_OUT)) = 3) then
+ i_bit <= '1';
+ else
+ i_bit <= '0';
+ end if;
+ end if;
+ when disable_write_to_memory =>
+ ENABLE <= '0';
+ WRITE_EN <= '0';
+ cstate <= update_row2;
+ i_mem_e_bit <= '0';
+ i_mem_write_bit <= '0';
+ i_bit <= '0';
+ when update_row2 =>
+ if (vppX = ROWS - 1) then
+ cstate <= update_col2;
+ else
+ vppX := vppX + 1;
+ cstate <= get_alive;
+ end if;
+ when update_col2 =>
+ if (vppYp = COLS_PIXEL - 1) then
+ cstate <= disable_memory;
+ vppYp := 0;
+ vppYb := 0;
+ else
+ vppYp := vppYp + 1;
+ cstate <= get_alive;
+ vppX := 0;
+ end if;
+ when disable_memory =>
+ cstate <= stop;
+-- i_mem_e_bit <= '0';
+-- i_bit <= '0';
+ -- end
+ when stop =>
+ cstate <= idle;
+ when others => null;
+ end case;
+ end if;
+ CellAlive <= To_Std_Logic(vCellAlive);
+ ppX <= std_logic_vector(to_unsigned(vppX,ROWS_BITS));
+ ppYp <= std_logic_vector(to_unsigned(vppYp,COLS_PIXEL_BITS));
+ ppYb <= std_logic_vector(to_unsigned(vppYb,COLS_BLOCK_BITS));
+ ppXm1 <= std_logic_vector(to_unsigned(vppXm1,ROWS_BITS));
+ ppXp1 <= std_logic_vector(to_unsigned(vppXp1,ROWS_BITS));
+ ppYm1 <= std_logic_vector(to_unsigned(vppYm1,COLS_PIXEL_BITS));
+ ppYp1 <= std_logic_vector(to_unsigned(vppYp1,COLS_PIXEL_BITS));
+end process gof_logic;
+
+end Behavioral;
diff --git a/gof/ssd1306_tb_top.vhd b/gof/ssd1306_tb_top.vhd
new file mode 100755
index 0000000..2c09966
--- /dev/null
+++ b/gof/ssd1306_tb_top.vhd
@@ -0,0 +1,125 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:09:48 11/01/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/i2c_test_3/tb_top.vhd
+-- Project Name: i2c_test_3
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+use WORK.p_memory_content.ALL;
+use WORK.p_constants1.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY ssd1306_tb_top IS
+END ssd1306_tb_top;
+
+ARCHITECTURE behavior OF ssd1306_tb_top IS
+
+constant IC : integer := 50_000_000;
+constant BC : integer := 6_000_000;
+constant DC : integer := 10_000;
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT ssd1306_gof
+generic(
+INPUT_CLOCK : integer := G_BOARD_CLOCK;
+BUS_CLOCK : integer := G_BUS_CLOCK; -- increase for speed i2c
+DIVIDER_CLOCK : integer := G_ClockDivider
+);
+port(
+signal clk : in std_logic;
+signal btn_1 : in std_logic;
+signal btn_2 : in std_logic;
+signal btn_3 : in std_logic;
+signal sda,scl : inout std_logic
+);
+END COMPONENT;
+
+signal MemOE : std_logic;
+signal MemWR : std_logic;
+signal RamAdv : std_logic;
+signal RamCS : std_logic;
+signal RamLB : std_logic;
+signal RamUB : std_logic;
+signal RamCRE : std_logic;
+signal RamWait : std_logic;
+signal MemAdr : MemoryAddressALL := (others => 'Z');
+signal MemDB : MemoryDataByte := (others => 'Z');
+
+--Inputs
+signal clk : std_logic := '0';
+signal btn_1 : std_logic := '0';
+signal btn_2 : std_logic := '0';
+signal btn_3 : std_logic := '0';
+
+--BiDirs
+signal sda : std_logic;
+signal scl : std_logic;
+
+-- Clock period definitions
+constant clk_period : time := (1_000_000_000 / IC) * 1 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: ssd1306_gof
+GENERIC MAP (
+INPUT_CLOCK => IC,
+BUS_CLOCK => BC,
+DIVIDER_CLOCK => DC
+)
+PORT MAP (
+clk => clk,
+btn_1 => btn_1,
+btn_2 => btn_2,
+btn_3 => btn_3,
+sda => sda,
+scl => scl
+);
+
+-- Clock process definitions
+clk_process :process
+begin
+clk <= '0';
+wait for clk_period/2;
+clk <= '1';
+wait for clk_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+btn_1 <= '1';
+wait for 100 ns;
+btn_1 <= '0';
+wait for clk_period*10;
+-- insert stimulus here
+wait;
+end process;
+
+END;
diff --git a/gof/ssd1306_tb_top.wcfg b/gof/ssd1306_tb_top.wcfg
new file mode 100755
index 0000000..3106e0d
--- /dev/null
+++ b/gof/ssd1306_tb_top.wcfg
@@ -0,0 +1,622 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ tb
+ label
+
+ clk
+ clk
+
+
+ btn_1
+ btn_1
+
+
+ btn_2
+ btn_2
+
+
+ btn_3
+ btn_3
+
+
+ sda
+ sda
+
+
+ scl
+ scl
+
+
+ ic
+ ic
+
+
+ bc
+ bc
+
+
+ dc
+ dc
+
+
+ clk_period
+ clk_period
+
+
+
+ top
+ label
+
+ display_initialize
+ display_initialize
+
+
+ sda
+ sda
+
+
+ scl
+ scl
+
+
+ all_pixels
+ all_pixels
+
+
+ cstate
+ cstate
+
+
+ clk
+ clk
+
+
+ row[3:0]
+ row[3:0]
+ UNSIGNEDDECRADIX
+
+
+ col_block[1:0]
+ col_block[1:0]
+ UNSIGNEDDECRADIX
+
+
+ col_pixel[4:0]
+ col_pixel[4:0]
+ UNSIGNEDDECRADIX
+
+
+ display_byte[7:0]
+ display_byte[7:0]
+
+
+ i_mem_e_byte
+ i_mem_e_byte
+
+
+ i_mem_e_bit
+ i_mem_e_bit
+
+
+ i_mem_write_bit
+ i_mem_write_bit
+
+
+ i_bit
+ i_bit
+
+
+ o_bit
+ o_bit
+
+
+ clk_1s
+ clk_1s
+
+
+ enable
+ enable
+
+
+ write_en
+ write_en
+
+
+ address[11:0]
+ address[11:0]
+ UNSIGNEDDECRADIX
+
+
+ data_in[3:0]
+ data_in[3:0]
+
+
+ data_out[3:0]
+ data_out[3:0]
+
+
+ ppx[3:0]
+ ppx[3:0]
+ UNSIGNEDDECRADIX
+
+
+ ppyb[1:0]
+ ppyb[1:0]
+ UNSIGNEDDECRADIX
+
+
+ ppyp[4:0]
+ ppyp[4:0]
+ UNSIGNEDDECRADIX
+
+
+ ppxm1[3:0]
+ ppxm1[3:0]
+ UNSIGNEDDECRADIX
+
+
+ ppxp1[3:0]
+ ppxp1[3:0]
+ UNSIGNEDDECRADIX
+
+
+ ppym1[4:0]
+ ppym1[4:0]
+ UNSIGNEDDECRADIX
+
+
+ label
+ ppyp1[4:0]
+ ppyp1[4:0]
+ ppyp1[4:0]
+ UNSIGNEDDECRADIX
+
+
+ countalive[3:0]
+ countalive[3:0]
+ UNSIGNEDDECRADIX
+
+
+ cellalive
+ cellalive
+
+
+
+ c0
+ label
+
+ i_clk
+ i_clk
+
+
+ i_rst
+ i_rst
+
+
+ i_clear
+ i_clear
+
+
+ i_draw
+ i_draw
+
+
+ i_x[3:0]
+ i_x[3:0]
+ UNSIGNEDDECRADIX
+
+
+ i_y[1:0]
+ i_y[1:0]
+ UNSIGNEDDECRADIX
+
+
+ i_byte[7:0]
+ i_byte[7:0]
+ HEXRADIX
+
+
+ i_all_pixels
+ i_all_pixels
+
+
+ o_display_initialize
+ o_display_initialize
+
+
+ o_busy
+ o_busy
+
+
+ io_sda
+ io_sda
+
+
+ io_scl
+ io_scl
+
+
+ i2c_data_wr[7:0]
+ i2c_data_wr[7:0]
+ HEXRADIX
+
+
+ c_state
+ c_state
+
+
+ i2c_ena
+ i2c_ena
+
+
+ i2c_rw
+ i2c_rw
+
+
+ i2c_busy
+ i2c_busy
+
+
+ i2c_reset
+ i2c_reset
+
+
+ busy_prev
+ busy_prev
+
+
+ busy_cnt
+ busy_cnt
+
+
+ counter
+ counter
+
+
+ coord_prev_x[3:0]
+ coord_prev_x[3:0]
+ UNSIGNEDDECRADIX
+
+
+ coord_prev_y[1:0]
+ coord_prev_y[1:0]
+ UNSIGNEDDECRADIX
+
+
+ global_clk
+ global_clk
+
+
+ i2c_clk
+ i2c_clk
+
+
+ width_o
+ width_o
+
+
+ height_o
+ height_o
+
+
+ w_bits
+ w_bits
+
+
+ h_bits
+ h_bits
+
+
+ byte_size
+ byte_size
+
+
+ width
+ width
+
+
+ height
+ height
+
+
+ oled_pages_all
+ oled_pages_all
+
+
+ oled_data
+ oled_data
+
+
+ oled_command
+ oled_command
+
+
+ counter_wait1
+ counter_wait1
+
+
+ ni_init
+ ni_init
+
+
+ ni_set_coordination
+ ni_set_coordination
+
+
+
+ my_i2c
+ label
+
+ i_clock
+ i_clock
+
+
+ i_reset
+ i_reset
+
+
+ i_slave_address[0:6]
+ i_slave_address[0:6]
+
+
+ i_bytes_to_send[0:7]
+ i_bytes_to_send[0:7]
+ HEXRADIX
+
+
+ i_enable
+ i_enable
+
+
+ o_busy
+ o_busy
+
+
+ o_sda
+ o_sda
+
+
+ o_scl
+ o_scl
+
+
+ clock
+ clock
+
+
+ temp_sda
+ temp_sda
+
+
+ temp_sck
+ temp_sck
+
+
+ instruction_index
+ instruction_index
+
+
+ c_state
+ c_state
+
+
+ n_state
+ n_state
+
+
+ c_cmode
+ c_cmode
+
+
+ n_cmode
+ n_cmode
+
+
+ data_index
+ data_index
+
+
+ slave_index
+ slave_index
+
+
+ sda_width
+ sda_width
+
+
+ board_clock
+ board_clock
+
+
+ bus_clock
+ bus_clock
+
+
+ i2c_counter_max
+ i2c_counter_max
+
+
+ slave_index_max
+ slave_index_max
+
+
+ sda_width_max
+ sda_width_max
+
+
+
+ m1
+ label
+
+ i_clk
+ i_clk
+
+
+ i_reset
+ i_reset
+
+
+ i_enable_byte
+ i_enable_byte
+
+
+ i_write_byte
+ i_write_byte
+
+
+ i_enable_bit
+ i_enable_bit
+
+
+ i_write_bit
+ i_write_bit
+
+
+ i_bit
+ i_bit
+
+
+ o_bit
+ o_bit
+
+
+ o_byte[7:0]
+ o_byte[7:0]
+
+
+ i_row[3:0]
+ i_row[3:0]
+ UNSIGNEDDECRADIX
+
+
+ i_col_block[1:0]
+ i_col_block[1:0]
+ UNSIGNEDDECRADIX
+
+
+ i_col_pixel[4:0]
+ i_col_pixel[4:0]
+ UNSIGNEDDECRADIX
+
+
+ i_byte[7:0]
+ i_byte[7:0]
+
+
+ address[8:0]
+ address[8:0]
+ UNSIGNEDDECRADIX
+
+
+ data_in[31:0]
+ data_in[31:0]
+
+
+ enable
+ enable
+
+
+ write_en
+ write_en
+
+
+ data_out[31:0]
+ data_out[31:0]
+
+
+ st
+ st
+
+
+ copy_content
+ copy_content
+
+
+ index
+ index
+
+
+
+ ramb16_s36
+ label
+
+ clk
+ clk
+
+
+ addr[8:0]
+ addr[8:0]
+ UNSIGNEDDECRADIX
+
+
+ di[31:0]
+ di[31:0]
+ HEXRADIX
+
+
+ do[31:0]
+ do[31:0]
+ HEXRADIX
+
+
+ en
+ en
+
+
+ we
+ we
+
+
+
+ ramb16_s4
+ label
+
+ clk
+ clk
+
+
+ do[3:0]
+ do[3:0]
+
+
+ addr[11:0]
+ addr[11:0]
+ UNSIGNEDDECRADIX
+
+
+ di[3:0]
+ di[3:0]
+ UNSIGNEDDECRADIX
+
+
+ en
+ en
+
+
+ we
+ we
+
+
+
diff --git a/gof/st7735r_draw_box.vhd b/gof/st7735r_draw_box.vhd
new file mode 100755
index 0000000..0dede9a
--- /dev/null
+++ b/gof/st7735r_draw_box.vhd
@@ -0,0 +1,485 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:09:37 06/23/2021
+-- Design Name:
+-- Module Name: draw_box - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.st7735r_p_package.ALL;
+use WORK.st7735r_p_screen.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity st7735r_draw_box is
+generic (
+ C_CLOCK_COUNTER : integer
+);
+port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_run : in std_logic;
+ i_sended : in std_logic;
+ i_color : in COLOR_TYPE;
+ i_raxs : in BYTE_TYPE;
+ i_raxe : in BYTE_TYPE;
+ i_rays : in BYTE_TYPE;
+ i_raye : in BYTE_TYPE;
+ i_caxs : in BYTE_TYPE;
+ i_caxe : in BYTE_TYPE;
+ i_cays : in BYTE_TYPE;
+ i_caye : in BYTE_TYPE;
+ o_data : out BYTE_TYPE;
+ o_enable : out std_logic;
+ o_rs : out std_logic;
+ o_initialized : out std_logic
+);
+end st7735r_draw_box;
+
+architecture Behavioral of st7735r_draw_box is
+
+ signal rs,enable,sended,initialized : std_logic;
+ signal send_data,send_command : BYTE_TYPE;
+ signal raxs,raxe,rays,raye,caxs,caxe,cays,caye : BYTE_TYPE;
+ type states is (
+ idle,start,
+ sendracmd,sendracmdw1,sendracmdw1a,
+ sendraxs,sendraxsw1,sendraxsw1a,
+ sendrays,sendraysw1,sendraysw1a,
+ sendraxe,sendraxew1,sendraxew1a,
+ sendraye,sendrayew1,sendrayew1a,
+ sendcacmd,sendcacmdw1,sendcacmdw1a,
+ sendcaxs,sendcaxsw1,sendcaxsw1a,
+ sendcays,sendcaysw1,sendcaysw1a,
+ sendcaxe,sendcaxew1,sendcaxew1a,
+ sendcaye,sendcayew1,sendcayew1a,
+ sendmemwr,sendmemwrw1,sendmemwrw1a,
+ fillarealb,fillarealbw1,fillarealbw1a,
+ fillareahb,fillareahbw1,fillareahbw1a,
+ fillarenaindex,
+ stop);
+ signal state : states;
+
+begin
+
+ o_data <= send_command when rs = '0' else send_data when rs = '1';
+ o_rs <= rs;
+ sended <= i_sended;
+ o_enable <= enable;
+ o_initialized <= initialized;
+ raxs <= i_raxs;
+ raxe <= i_raxe;
+ rays <= i_rays;
+ raye <= i_raye;
+ caxs <= i_caxs;
+ caxe <= i_caxe;
+ cays <= i_cays;
+ caye <= i_caye;
+
+ p0 : process (i_clock,i_reset) is
+ variable w0_index : integer range 0 to 2**25;
+ variable index : integer;
+ variable x,y : integer;
+ begin
+ if (i_reset = '1') then
+ state <= idle;
+ w0_index := 0;
+ enable <= '0';
+ rs <= '0';
+ send_command <= (others => '0');
+ send_data <= (others => '0');
+ initialized <= '0';
+ x := 0;
+ y := 0;
+ index := 0;
+ elsif (rising_edge(i_clock)) then
+ case (state) is
+ when idle =>
+ initialized <= '0';
+ if (i_run = '1') then
+ state <= start;
+ else
+ state <= idle;
+ end if;
+ when start =>
+ state <= sendracmd;
+ when sendracmd =>
+ send_command <= x"2b"; --RASET
+ rs <= '0';
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendracmdw1;
+ else
+ state <= sendracmd;
+ end if;
+ when sendracmdw1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendracmdw1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendracmdw1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendracmdw1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendraxs;
+ w0_index := 0;
+ else
+ state <= sendracmdw1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendraxs => -- c1
+ rs <= '1';
+ send_data <= raxs;
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendraxsw1;
+ else
+ state <= sendraxs;
+ end if;
+ when sendraxsw1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendraxsw1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendraxsw1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendraxsw1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendrays;
+ w0_index := 0;
+ else
+ state <= sendraxsw1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendrays => -- c2
+ rs <= '1';
+ send_data <= raxe;
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendraysw1;
+ else
+ state <= sendrays;
+ end if;
+ when sendraysw1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendraysw1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendraysw1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendraysw1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendraxe;
+ w0_index := 0;
+ else
+ state <= sendraysw1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendraxe => -- c3
+ rs <= '1';
+ send_data <= rays;
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendraxew1;
+ else
+ state <= sendraxe;
+ end if;
+ when sendraxew1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendraxew1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendraxew1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendraxew1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendraye;
+ w0_index := 0;
+ else
+ state <= sendraxew1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendraye => -- c4
+ rs <= '1';
+ send_data <= caxe;
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendrayew1;
+ else
+ state <= sendraye;
+ end if;
+ when sendrayew1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendrayew1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendrayew1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendrayew1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcacmd;
+ w0_index := 0;
+ else
+ state <= sendrayew1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcacmd =>
+ rs <= '0';
+ send_command <= x"2a"; --CASET
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendcacmdw1;
+ else
+ state <= sendcacmd;
+ end if;
+ when sendcacmdw1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcacmdw1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendcacmdw1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcacmdw1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcaxs;
+ w0_index := 0;
+ else
+ state <= sendcacmdw1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcaxs => -- c5
+ rs <= '1';
+ send_data <= caxs;
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendcaxsw1;
+ else
+ state <= sendcaxs;
+ end if;
+ when sendcaxsw1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcaxsw1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendcaxsw1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcaxsw1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcays;
+ w0_index := 0;
+ else
+ state <= sendcaxsw1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcays => -- c6
+ rs <= '1';
+ send_data <= raye;
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendcaysw1;
+ else
+ state <= sendcays;
+ end if;
+ when sendcaysw1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcaysw1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendcaysw1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcaysw1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcaxe;
+ w0_index := 0;
+ else
+ state <= sendcaysw1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcaxe => -- c7
+ rs <= '1';
+ send_data <= cays;
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendcaxew1;
+ else
+ state <= sendcaxe;
+ end if;
+ when sendcaxew1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcaxew1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendcaxew1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcaxew1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcaye;
+ w0_index := 0;
+ else
+ state <= sendcaxew1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcaye => -- c8
+ rs <= '1';
+ send_data <= caye;
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendcayew1;
+ else
+ state <= sendcaye;
+ end if;
+ when sendcayew1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcayew1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendcayew1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcayew1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendmemwr;
+ w0_index := 0;
+ else
+ state <= sendcayew1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendmemwr =>
+ x := to_integer(unsigned(caxe)) - to_integer(unsigned(raxe));
+ y := to_integer(unsigned(caye)) - to_integer(unsigned(raye));
+ rs <= '0';
+ send_command <= x"2c"; --RAMWR
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendmemwrw1;
+ else
+ state <= sendmemwr;
+ end if;
+ when sendmemwrw1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendmemwrw1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendmemwrw1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendmemwrw1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= fillarealb;
+ w0_index := 0;
+ else
+ state <= sendmemwrw1a;
+ w0_index := w0_index + 1;
+ end if;
+ when fillarealb =>
+ rs <= '1';
+ send_data <= i_color(15 downto 8);
+ enable <= '1';
+ if (sended = '1') then
+ state <= fillarealbw1;
+ else
+ state <= fillarealb;
+ end if;
+ when fillarealbw1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= fillarealbw1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= fillarealbw1;
+ w0_index := w0_index + 1;
+ end if;
+ when fillarealbw1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= fillareahb;
+ w0_index := 0;
+ else
+ state <= fillarealbw1a;
+ w0_index := w0_index + 1;
+ end if;
+ when fillareahb =>
+ rs <= '1';
+ send_data <= i_color(7 downto 0);
+ enable <= '1';
+ if (sended = '1') then
+ state <= fillareahbw1;
+ else
+ state <= fillareahb;
+ end if;
+ when fillareahbw1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= fillareahbw1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= fillareahbw1;
+ w0_index := w0_index + 1;
+ end if;
+ when fillareahbw1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= fillarenaindex;
+ w0_index := 0;
+ else
+ state <= fillareahbw1a;
+ w0_index := w0_index + 1;
+ end if;
+ when fillarenaindex =>
+-- if (index = (x*y) - 1) then -- XXX TODO x*y - 1 drop last pixel
+ if (index = 0) then -- XXX one pixel
+ state <= stop;
+ index := 0;
+ enable <= '0';
+ initialized <= '1';
+ else
+ state <= fillarealb;
+ index := index + 1;
+ end if;
+ when stop =>
+ state <= idle;
+ when others =>
+ state <= idle;
+ end case;
+ end if;
+ end process p0;
+
+end Behavioral;
diff --git a/gof/st7735r_gof.vhd b/gof/st7735r_gof.vhd
new file mode 100755
index 0000000..b61e4bd
--- /dev/null
+++ b/gof/st7735r_gof.vhd
@@ -0,0 +1,1290 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:11:54 09/04/2020
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.st7735r_p_package.ALL;
+use WORK.st7735r_p_screen.ALL;
+use WORK.p_memory_content.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity st7735r_gof is
+generic(
+INPUT_CLOCK : integer := 50_000_000; --29_952_000;
+SPI_SPEED_MODE : integer := C_CLOCK_COUNTER_EF
+);
+port(
+clk : in std_logic;
+btn_1 : in std_logic;
+o_cs : out std_logic;
+o_do : out std_logic;
+o_ck : out std_logic;
+o_reset : out std_logic;
+o_rs : out std_logic;
+Led5 : out std_logic;
+Led6 : out std_logic;
+Led7 : out std_logic;
+o_MemOE : out std_logic;
+o_MemWR : out std_logic;
+o_RamAdv : out std_logic;
+o_RamCS : out std_logic;
+o_RamCRE : out std_logic;
+o_RamLB : out std_logic;
+o_RamUB : out std_logic;
+--i_RamWait : in std_logic;
+o_RamClk : out std_logic;
+o_MemAdr : out MemoryAddress;
+io_MemDB : inout MemoryDataByte;
+o_FlashCS : out std_logic
+);
+end entity st7735r_gof;
+
+architecture Behavioral of st7735r_gof is
+
+component my_spi is
+generic (
+C_CLOCK_COUNTER : integer
+);
+port (
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_enable : in std_logic;
+i_data_byte : in BYTE_TYPE;
+o_cs : out std_logic;
+o_do : out std_logic;
+o_ck : out std_logic;
+o_sended : out std_logic
+);
+end component my_spi;
+
+component st7735r_initialize is
+generic (
+C_CLOCK_COUNTER : integer
+);
+port (
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_run : in std_logic;
+i_color : in COLOR_TYPE;
+i_sended : in std_logic;
+o_initialized : out std_logic;
+o_enable : out std_logic;
+o_data_byte : out BYTE_TYPE;
+o_reset : out std_logic;
+o_rs : out std_logic;
+o_cs : out std_logic
+);
+end component st7735r_initialize;
+
+component BUFG
+port (I : in std_logic;
+O : out std_logic);
+end component;
+
+component clock_divider is
+Port(
+i_clk : in STD_LOGIC;
+i_board_clock : in INTEGER;
+i_divider : in INTEGER;
+o_clk : out STD_LOGIC
+);
+end component clock_divider;
+
+component memorymodule_ramb16_s1 is
+Port (
+i_clock : in std_logic;
+i_enable : in std_logic;
+i_write : in std_logic;
+i_read : in std_logic;
+o_busy : out std_logic;
+i_MemAdr : in MemoryAddress;
+i_MemDB : in std_logic_vector(0 downto 0);
+o_MemDB : out std_logic_vector(0 downto 0);
+o_MemOE : out std_logic;
+o_MemWR : out std_logic;
+o_RamAdv : out std_logic;
+o_RamCS : out std_logic;
+o_RamCRE : out std_logic;
+o_RamLB : out std_logic;
+o_RamUB : out std_logic;
+--i_RamWait : in std_logic;
+o_RamClk : out std_logic;
+o_MemAdr : out MemoryAddress;
+io_MemDB : inout std_logic_vector(0 downto 0)
+);
+end component memorymodule_ramb16_s1;
+
+component memorymodule_ramb16_s4 is
+Port (
+i_clock : in std_logic;
+i_enable : in std_logic;
+i_write : in std_logic;
+i_read : in std_logic;
+o_busy : out std_logic;
+i_MemAdr : in MemoryAddress;
+i_MemDB : in MemoryDataByte;
+o_MemDB : out MemoryDataByte;
+o_MemOE : out std_logic;
+o_MemWR : out std_logic;
+o_RamAdv : out std_logic;
+o_RamCS : out std_logic;
+o_RamCRE : out std_logic;
+o_RamLB : out std_logic;
+o_RamUB : out std_logic;
+o_RamClk : out std_logic;
+o_MemAdr : out MemoryAddress;
+io_MemDB : inout MemoryDataByte
+);
+end component memorymodule_ramb16_s4;
+
+type state is (
+set_cd_memorycopy,enable_memory_module,enable_write_fh,copy_first_halfword,disable_write_fh,disable_memory_module,memory_wait_fh,
+check_ranges_write1,check_ranges_write2,idle,display_is_initialize,reset_counters,
+draw_box_state0,
+draw_box_state1,draw_box_state2,draw_box_state3,draw_box_state4,draw_box_state5,draw_box_state6,draw_box_state7,draw_box_state8,draw_box_state9,
+draw_box_state10,draw_box_state11,draw_box_state12,draw_box_state13,draw_box_state14,draw_box_state15,draw_box_state16,draw_box_state17,draw_box_state18,draw_box_state19,
+draw_box_state20,draw_box_state21,draw_box_state22,draw_box_state23,draw_box_state24,draw_box_state25,draw_box_state26,draw_box_state27,draw_box_state28,draw_box_state29,
+set_color1,set_color2,set_color3,
+enable_memory_module_read_fh,enable_read_memory_fh,read_fh,store_fh,disable_read_memory_fh,disable_memory_module_read_fh,memory_busy,
+set_color4,set_color5,set_color6,set_color7,set_color8,set_color9,
+check_colindex,check_rowindex,reset_counters_1,
+check_coordinations,reset_count_alive,
+c1_m_e,c1_m_r_e,c1_s_a,c1_m_r_d,c1_m_d,c1_busy,c1,
+c2_m_e,c2_m_r_e,c2_s_a,c2_m_r_d,c2_m_d,c2_busy,c2,
+c3_m_e,c3_m_r_e,c3_s_a,c3_m_r_d,c3_m_d,c3_busy,c3,
+c4_m_e,c4_m_r_e,c4_s_a,c4_m_r_d,c4_m_d,c4_busy,c4,
+c5_m_e,c5_m_r_e,c5_s_a,c5_m_r_d,c5_m_d,c5_busy,c5,
+c6_m_e,c6_m_r_e,c6_s_a,c6_m_r_d,c6_m_d,c6_busy,c6,
+c7_m_e,c7_m_r_e,c7_s_a,c7_m_r_d,c7_m_d,c7_busy,c7,
+c8_m_e,c8_m_r_e,c8_s_a,c8_m_r_d,c8_m_d,c8_busy,c8,
+store_neighborhood1,store_neighborhood2,store_neighborhood3,store_neighborhood4,store_neighborhood5,store_neighborhood6,
+update_row1,update_col1,reset_counters1,
+check_cell_alive1,check_cell_alive2,check_cell_alive3,check_cell_alive4,check_cell_alive5,check_cell_alive6,check_cell_alive7,
+get_stored_neighborhood1,get_stored_neighborhood2,get_stored_neighborhood3,get_stored_neighborhood4,get_stored_neighborhood5,get_stored_neighborhood6,get_stored_neighborhood7,
+write_new_cellalive1,write_new_cellalive2,write_new_cellalive3,write_new_cellalive4,write_new_cellalive5,write_new_cellalive6,write_new_cellalive7,
+update_row2,update_col2);
+signal cstate : state;
+
+signal i_reset : std_logic;
+signal CLK_BUFG : std_logic;
+
+signal spi_enable,spi_cs,spi_do,spi_ck,spi_sended : std_logic;
+signal spi_data_byte : BYTE_TYPE;
+signal initialize_run,initialize_sended : std_logic;
+signal initialize_initialized,initialize_enable,initialize_reset,initialize_rs : std_logic;
+signal initialize_color : COLOR_TYPE;
+signal initialize_data_byte : BYTE_TYPE;
+signal drawbox_enable,drawbox_rs,drawbox_run : std_logic;
+signal drawbox_data_byte : BYTE_TYPE;
+signal mm1_i_MemAdr,mm2_i_MemAdr : MemoryAddress;
+signal mm1_i_MemDB,mm1_o_MemDB : std_logic_vector(0 downto 0);
+signal mm2_i_MemDB,mm2_o_MemDB : MemoryDataByte;
+signal mm1_i_enable,mm1_i_write,mm1_i_read,mm1_o_busy,mm2_i_enable,mm2_i_write,mm2_i_read,mm2_o_busy : std_logic;
+
+signal MemOE : std_logic;
+signal MemWR : std_logic;
+signal RamAdv : std_logic;
+signal RamCS : std_logic;
+signal RamCRE : std_logic;
+signal RamLB : std_logic;
+signal RamUB : std_logic;
+--signal RamWait : std_logic;
+signal RamClk : std_logic;
+signal MemAdr : MemoryAddress;
+signal MemDB : MemoryDataByte;
+signal FlashCS : std_logic;
+
+begin
+
+o_MemOE <= MemOE;
+o_MemWR <= MemWR;
+o_RamAdv <= RamAdv;
+o_RamCS <= RamCS;
+o_RamCRE <= RamCRE;
+o_RamLB <= RamLB;
+o_RamUB <= RamUB;
+o_RamClk <= RamClk;
+o_MemAdr <= MemAdr;
+io_MemDB <= MemDB;
+o_FlashCS <= FlashCS;
+
+i_reset <= btn_1;
+FlashCS <= '1'; -- flash is always off
+
+o_cs <= spi_cs; -- TODO use initialize_cs mux
+o_do <= spi_do;
+o_ck <= spi_ck;
+
+o_reset <=
+initialize_reset when initialize_run = '1'
+else
+'1';
+
+o_rs <=
+initialize_rs when initialize_run = '1'
+else
+drawbox_rs when drawbox_run = '1'
+else
+'1';
+
+spi_data_byte <=
+initialize_data_byte when initialize_run = '1'
+else
+drawbox_data_byte when drawbox_run = '1'
+else
+(others => '0');
+
+spi_enable <=
+initialize_enable when initialize_run = '1'
+else
+drawbox_enable when drawbox_run = '1'
+else
+'0';
+
+initialize_sended <=
+spi_sended when initialize_run = '1'
+else
+'0';
+
+myspi_entity : my_spi
+generic map (
+C_CLOCK_COUNTER => SPI_SPEED_MODE
+)
+port map (
+i_clock => CLK_BUFG,
+i_reset => i_reset,
+i_enable => spi_enable,
+i_data_byte => spi_data_byte,
+o_cs => spi_cs,
+o_do => spi_do,
+o_ck => spi_ck,
+o_sended => spi_sended
+);
+
+st7735r_initialize_entity : st7735r_initialize
+generic map (
+C_CLOCK_COUNTER => SPI_SPEED_MODE
+)
+port map (
+i_clock => CLK_BUFG,
+i_reset => i_reset,
+i_run => initialize_run,
+i_color => initialize_color,
+i_sended => initialize_sended,
+o_initialized => initialize_initialized,
+o_cs => open,
+o_reset => initialize_reset,
+o_rs => initialize_rs,
+o_enable => initialize_enable,
+o_data_byte => initialize_data_byte
+);
+
+U_BUFG: BUFG
+port map (
+I => clk,
+O => CLK_BUFG
+);
+
+mm1 : memorymodule_ramb16_s1
+Port map (
+i_clock => CLK_BUFG,
+i_enable => mm1_i_enable,
+i_write => mm1_i_write,
+i_read => mm1_i_read,
+o_busy => mm1_o_busy,
+i_MemAdr => mm1_i_MemAdr,
+i_MemDB(0 downto 0) => mm1_i_MemDB,
+o_MemDB(0 downto 0) => mm1_o_MemDB,
+o_MemOE => open,
+o_MemWR => open,
+o_RamAdv => open,
+o_RamCS => open,
+o_RamCRE => open,
+o_RamLB => open,
+o_RamUB => open,
+o_RamClk => open,
+o_MemAdr => open,
+io_MemDB => open
+);
+
+mm2 : memorymodule_ramb16_s4
+Port map (
+i_clock => CLK_BUFG,
+i_enable => mm2_i_enable,
+i_write => mm2_i_write,
+i_read => mm2_i_read,
+o_busy => mm2_o_busy,
+i_MemAdr => mm2_i_MemAdr,
+i_MemDB => mm2_i_MemDB,
+o_MemDB => mm2_o_MemDB,
+o_MemOE => open,
+o_MemWR => open,
+o_RamAdv => open,
+o_RamCS => open,
+o_RamCRE => open,
+o_RamLB => open,
+o_RamUB => open,
+o_RamClk => open,
+o_MemAdr => open,
+io_MemDB => open
+);
+
+gof_logic : process (CLK_BUFG,i_reset) is
+ variable vppX : integer range -1 to ROWS;
+ variable vppYp : integer range -1 to COLS_PIXEL;
+ variable vppXm1 : integer range -1 to ROWS;
+ variable vppXp1 : integer range -1 to ROWS;
+ variable vppYm1 : integer range -1 to COLS_PIXEL;
+ variable vppYp1 : integer range -1 to COLS_PIXEL;
+ variable vcountAlive : integer range 0 to 7;
+ variable vCellAlive,vCellAlive2 : boolean;
+ constant ALL_PIXELS : integer range 0 to (ROWS * COLS_PIXEL) - 1 := (ROWS * COLS_PIXEL) - 1;
+ constant startAddress : integer := 0;
+ variable vstartAddress : integer range 0 to ALL_PIXELS - 1;
+ constant storeAddress : integer := ALL_PIXELS;
+ variable vstoreAddress : integer range (1 * ALL_PIXELS) to (2 * ALL_PIXELS) - 1;
+ variable rowIndex : integer range 0 to ROWS - 1;
+ variable colIndex : integer range 0 to COLS_PIXEL - 1;
+ variable COL : WORD;
+ variable address_cc,address_disp,address_c1,address_c2,address_c3,address_c4,address_c5,address_c6,address_c7,address_c8,address_sca,address_ga,address_ewm,address_wca : std_logic_vector(G_MemoryAddress - 1 downto 1);
+ variable w0_index : integer range 0 to SPI_SPEED_MODE - 1;
+begin
+ if (i_reset = '1') then
+ cstate <= set_cd_memorycopy;
+ elsif (rising_edge(CLK_BUFG)) then
+ case cstate is
+ -- copy memory content
+ when set_cd_memorycopy =>
+ cstate <= enable_memory_module;
+ vppX := 0;
+ vppYp := 0;
+ vppXm1 := 0;
+ vppXp1 := 0;
+ vppYm1 := 0;
+ vppYp1 := 0;
+ initialize_run <= '0';
+ COL := (others => '0');
+ vCellAlive := false;
+ vCellAlive2 := false;
+ vcountAlive := 0;
+ vstartAddress := 0;
+ vstoreAddress := ALL_PIXELS;
+ rowIndex := 0;
+ colIndex := 0;
+ address_cc := (others => '0');
+ address_disp := (others => '0');
+ address_c1 := (others => '0');
+ address_c2 := (others => '0');
+ address_c3 := (others => '0');
+ address_c4 := (others => '0');
+ address_c5 := (others => '0');
+ address_c6 := (others => '0');
+ address_c7 := (others => '0');
+ address_c8 := (others => '0');
+ address_sca := (others => '0');
+ address_ga := (others => '0');
+ address_ewm := (others => '0');
+ address_wca := (others => '0');
+ Led5 <= '1';
+ Led6 <= '1';
+ Led7 <= '1';
+ w0_index := 0;
+ when enable_memory_module =>
+ cstate <= enable_write_fh;
+ mm1_i_enable <= '1';
+ when enable_write_fh =>
+ cstate <= copy_first_halfword;
+ mm1_i_write <= '1';
+ COL := memory_content(rowIndex);
+ when copy_first_halfword =>
+ cstate <= disable_write_fh;
+ address_cc := std_logic_vector(to_unsigned((startAddress + colIndex) + (rowIndex*COLS_PIXEL),G_MemoryAddress-1));
+ mm1_i_MemAdr <= address_cc;
+ mm1_i_MemDB(0) <= COL(colIndex);
+ when disable_write_fh =>
+ cstate <= disable_memory_module;
+ mm1_i_write <= '0';
+ when disable_memory_module =>
+ cstate <= memory_wait_fh;
+ mm1_i_enable <= '0';
+ when memory_wait_fh =>
+ if (mm1_o_busy = '1') then
+ cstate <= memory_wait_fh;
+ else
+ cstate <= check_ranges_write1;
+ end if;
+ when check_ranges_write1 =>
+ if (colIndex = COLS_PIXEL - 1) then
+ cstate <= check_ranges_write2;
+ colIndex := 0;
+ else
+ colIndex := colIndex + 1;
+ cstate <= enable_memory_module;
+ end if;
+ when check_ranges_write2 =>
+ if (rowIndex = ROWS-1) then
+ rowIndex := 0;
+ cstate <= idle;
+ else
+ rowIndex := rowIndex + 1;
+ cstate <= enable_memory_module;
+ end if;
+ when idle =>
+ cstate <= display_is_initialize;
+ initialize_run <= '1';
+ initialize_color <= SCREEN_BLACK;
+ when display_is_initialize =>
+ if (initialize_initialized = '1') then
+ cstate <= reset_counters;
+ else
+ cstate <= display_is_initialize;
+ end if;
+ when reset_counters =>
+ cstate <= draw_box_state0;
+ initialize_run <= '0';
+ drawbox_run <= '1';
+ vppX := 0;
+ vppYp := 0;
+ vstartAddress := 0;
+ vstoreAddress := ALL_PIXELS;
+ rowIndex := 0;
+ colIndex := 0;
+ when draw_box_state0 =>
+ Led5 <= '1';
+ Led6 <= '0';
+ Led7 <= '0';
+ drawbox_data_byte <= x"2b"; --RASET
+ drawbox_rs <= '0';
+ drawbox_enable <= '1';
+ if (spi_sended = '1') then
+ cstate <= draw_box_state1;
+ else
+ cstate <= draw_box_state0;
+ end if;
+ when draw_box_state1 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state2;
+ w0_index := 0;
+ drawbox_enable <= '0';
+ else
+ cstate <= draw_box_state1;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state2 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state3;
+ w0_index := 0;
+ else
+ cstate <= draw_box_state2;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state3 =>
+ drawbox_rs <= '1';
+ drawbox_data_byte <= x"00";
+ drawbox_enable <= '1';
+ if (spi_sended = '1') then
+ cstate <= draw_box_state4;
+ else
+ cstate <= draw_box_state3;
+ end if;
+ when draw_box_state4 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state5;
+ w0_index := 0;
+ drawbox_enable <= '0';
+ else
+ cstate <= draw_box_state4;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state5 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state6;
+ w0_index := 0;
+ else
+ cstate <= draw_box_state5;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state6 =>
+ drawbox_rs <= '1';
+ drawbox_data_byte <= x"00";
+ drawbox_enable <= '1';
+ if (spi_sended = '1') then
+ cstate <= draw_box_state7;
+ else
+ cstate <= draw_box_state6;
+ end if;
+ when draw_box_state7 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state8;
+ w0_index := 0;
+ drawbox_enable <= '0';
+ else
+ cstate <= draw_box_state7;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state8 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state9;
+ w0_index := 0;
+ else
+ cstate <= draw_box_state8;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state9 =>
+ drawbox_rs <= '1';
+ drawbox_data_byte <= x"00";
+ drawbox_enable <= '1';
+ if (spi_sended = '1') then
+ cstate <= draw_box_state10;
+ else
+ cstate <= draw_box_state9;
+ end if;
+ when draw_box_state10 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state11;
+ w0_index := 0;
+ drawbox_enable <= '0';
+ else
+ cstate <= draw_box_state10;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state11 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state12;
+ w0_index := 0;
+ else
+ cstate <= draw_box_state11;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state12 =>
+ drawbox_rs <= '1';
+ drawbox_data_byte <= std_logic_vector(to_unsigned(ROWS-1,BYTE_SIZE));
+ drawbox_enable <= '1';
+ if (spi_sended = '1') then
+ cstate <= draw_box_state13;
+ else
+ cstate <= draw_box_state12;
+ end if;
+ when draw_box_state13 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state14;
+ w0_index := 0;
+ drawbox_enable <= '0';
+ else
+ cstate <= draw_box_state13;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state14 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state15;
+ w0_index := 0;
+ else
+ cstate <= draw_box_state14;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state15 =>
+ drawbox_data_byte <= x"2a"; --CASET
+ drawbox_rs <= '0';
+ drawbox_enable <= '1';
+ if (spi_sended = '1') then
+ cstate <= draw_box_state16;
+ else
+ cstate <= draw_box_state15;
+ end if;
+ when draw_box_state16 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state17;
+ w0_index := 0;
+ drawbox_enable <= '0';
+ else
+ cstate <= draw_box_state16;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state17 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state18;
+ w0_index := 0;
+ else
+ cstate <= draw_box_state17;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state18 =>
+ drawbox_rs <= '1';
+ drawbox_data_byte <= x"00";
+ drawbox_enable <= '1';
+ if (spi_sended = '1') then
+ cstate <= draw_box_state19;
+ else
+ cstate <= draw_box_state18;
+ end if;
+ when draw_box_state19 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state20;
+ w0_index := 0;
+ drawbox_enable <= '0';
+ else
+ cstate <= draw_box_state19;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state20 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state21;
+ w0_index := 0;
+ else
+ cstate <= draw_box_state20;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state21 =>
+ drawbox_rs <= '1';
+ drawbox_data_byte <= x"00";
+ drawbox_enable <= '1';
+ if (spi_sended = '1') then
+ cstate <= draw_box_state22;
+ else
+ cstate <= draw_box_state21;
+ end if;
+ when draw_box_state22 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state23;
+ w0_index := 0;
+ drawbox_enable <= '0';
+ else
+ cstate <= draw_box_state22;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state23 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state24;
+ w0_index := 0;
+ else
+ cstate <= draw_box_state23;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state24 =>
+ drawbox_rs <= '1';
+ drawbox_data_byte <= x"00";
+ drawbox_enable <= '1';
+ if (spi_sended = '1') then
+ cstate <= draw_box_state25;
+ else
+ cstate <= draw_box_state24;
+ end if;
+ when draw_box_state25 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state26;
+ w0_index := 0;
+ drawbox_enable <= '0';
+ else
+ cstate <= draw_box_state25;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state26 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state27;
+ w0_index := 0;
+ else
+ cstate <= draw_box_state26;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state27 =>
+ drawbox_rs <= '1';
+ drawbox_data_byte <= std_logic_vector(to_unsigned(COLS_PIXEL-1,BYTE_SIZE));
+ drawbox_enable <= '1';
+ if (spi_sended = '1') then
+ cstate <= draw_box_state28;
+ else
+ cstate <= draw_box_state27;
+ end if;
+ when draw_box_state28 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= draw_box_state29;
+ w0_index := 0;
+ drawbox_enable <= '0';
+ else
+ cstate <= draw_box_state28;
+ w0_index := w0_index + 1;
+ end if;
+ when draw_box_state29 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= set_color1;
+ w0_index := 0;
+ else
+ cstate <= draw_box_state29;
+ w0_index := w0_index + 1;
+ end if;
+ when set_color1 =>
+ drawbox_rs <= '0';
+ drawbox_data_byte <= x"2c"; --RAMWR
+ drawbox_enable <= '1';
+ if (spi_sended = '1') then
+ cstate <= set_color2;
+ else
+ cstate <= set_color1;
+ end if;
+ when set_color2 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= set_color3;
+ w0_index := 0;
+ drawbox_enable <= '0';
+ else
+ cstate <= set_color2;
+ w0_index := w0_index + 1;
+ end if;
+ when set_color3 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= enable_memory_module_read_fh;
+ w0_index := 0;
+ else
+ cstate <= set_color3;
+ w0_index := w0_index + 1;
+ end if;
+ when enable_memory_module_read_fh =>
+ cstate <= enable_read_memory_fh;
+ mm1_i_enable <= '1';
+ when enable_read_memory_fh =>
+ cstate <= read_fh;
+ mm1_i_read <= '1';
+ when read_fh =>
+ cstate <= store_fh;
+ address_disp := std_logic_vector(to_unsigned((startAddress + colIndex) + (rowIndex*COLS_PIXEL),G_MemoryAddress-1));
+ mm1_i_MemAdr <= address_disp;
+ when store_fh =>
+ cstate <= disable_read_memory_fh;
+ when disable_read_memory_fh =>
+ cstate <= disable_memory_module_read_fh;
+ mm1_i_read <= '0';
+ when disable_memory_module_read_fh =>
+ cstate <= memory_busy;
+ mm1_i_enable <= '0';
+ when memory_busy =>
+ if (mm1_o_busy = '1') then
+ cstate <= memory_busy;
+ else
+ cstate <= set_color4;
+ end if;
+ when set_color4 =>
+ if (mm1_o_MemDB(0) = '1') then
+ drawbox_data_byte <= x"ff";
+ else
+ drawbox_data_byte <= x"00";
+ end if;
+ drawbox_rs <= '1';
+ drawbox_enable <= '1';
+ if (spi_sended = '1') then
+ cstate <= set_color5;
+ else
+ cstate <= set_color4;
+ end if;
+ when set_color5 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= set_color6;
+ w0_index := 0;
+ drawbox_enable <= '0';
+ else
+ cstate <= set_color5;
+ w0_index := w0_index + 1;
+ end if;
+ when set_color6 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= set_color7;
+ w0_index := 0;
+ else
+ cstate <= set_color6;
+ w0_index := w0_index + 1;
+ end if;
+ when set_color7 =>
+ if (mm1_o_MemDB(0) = '1') then
+ drawbox_data_byte <= x"ff";
+ else
+ drawbox_data_byte <= x"00";
+ end if;
+ drawbox_rs <= '1';
+ drawbox_enable <= '1';
+ if (spi_sended = '1') then
+ cstate <= set_color8;
+ else
+ cstate <= set_color7;
+ end if;
+ when set_color8 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= set_color9;
+ w0_index := 0;
+ drawbox_enable <= '0';
+ else
+ cstate <= set_color8;
+ w0_index := w0_index + 1;
+ end if;
+ when set_color9 =>
+ if (w0_index = SPI_SPEED_MODE - 1) then
+ cstate <= check_colindex;
+ w0_index := 0;
+ else
+ cstate <= set_color9;
+ w0_index := w0_index + 1;
+ end if;
+ when check_colindex =>
+ if (colIndex = COLS_PIXEL - 1) then
+ cstate <= check_rowindex;
+ colIndex := 0;
+ else
+ cstate <= enable_memory_module_read_fh;
+ colIndex := colIndex + 1;
+ end if;
+ when check_rowindex =>
+ if (rowIndex = ROWS-1) then
+ cstate <= reset_counters_1;
+ rowIndex := 0;
+ else
+ cstate <= enable_memory_module_read_fh;
+ rowIndex := rowIndex + 1;
+ end if;
+ -- calculate cells
+ when reset_counters_1 =>
+-- cstate <= reset_counters_1; -- XXX stay after show memory content
+ cstate <= check_coordinations;
+ drawbox_run <= '0';
+ vppX := 0;
+ vppYp := 0;
+ Led5 <= '0';
+ Led6 <= '1';
+ Led7 <= '0';
+ when check_coordinations =>
+ cstate <= reset_count_alive;
+ vppXm1 := vppX-1;
+ if (vppXm1 < 0) then
+ vppXm1 := 0; --ROWS - 1;
+ end if;
+ vppXp1 := vppX+1;
+ if (vppXp1 > ROWS-1) then
+ vppXp1 := ROWS - 1; --0;
+ end if;
+ vppYm1 := vppYp-1;
+ if (vppYm1 < 0) then
+ vppYm1 := 0; --COLS_PIXEL - 1;
+ end if;
+ vppYp1 := vppYp+1;
+ if (vppYp1 > COLS_PIXEL-1) then
+ vppYp1 := COLS_PIXEL - 1; --0;
+ end if;
+ when reset_count_alive =>
+ cstate <= c1_m_e;
+ vcountAlive := 0;
+ -- XXX ppX,ppYm1
+ when c1_m_e =>
+ cstate <= c1_m_r_e;
+ mm1_i_enable <= '1';
+ when c1_m_r_e =>
+ cstate <= c1_s_a;
+ mm1_i_read <= '1';
+ when c1_s_a =>
+ cstate <= c1_m_r_d;
+ address_c1 := std_logic_vector(to_unsigned((startAddress + vppYm1) + (vppX*COLS_PIXEL),G_MemoryAddress-1));
+ mm1_i_MemAdr <= address_c1;
+ when c1_m_r_d =>
+ cstate <= c1_m_d;
+ mm1_i_read <= '0';
+ when c1_m_d =>
+ cstate <= c1_busy;
+ mm1_i_enable <= '0';
+ when c1_busy =>
+ if (mm1_o_busy = '1') then
+ cstate <= c1_busy;
+ else
+ cstate <= c1;
+ end if;
+ when c1 =>
+ cstate <= c2_m_e;
+ if (mm1_o_MemDB(0) = '1') then -- XXX *i ?
+ vcountAlive := vcountAlive + 1;
+ end if;
+ -- XXX ppX,ppYp1
+ when c2_m_e =>
+ cstate <= c2_m_r_e;
+ mm1_i_enable <= '1';
+ when c2_m_r_e =>
+ cstate <= c2_s_a;
+ mm1_i_read <= '1';
+ when c2_s_a =>
+ cstate <= c2_m_r_d;
+ address_c2 := std_logic_vector(to_unsigned((startAddress + vppYp1) + (vppX*COLS_PIXEL),G_MemoryAddress-1));
+ mm1_i_MemAdr <= address_c2;
+ when c2_m_r_d =>
+ cstate <= c2_m_d;
+ mm1_i_read <= '0';
+ when c2_m_d =>
+ cstate <= c2_busy;
+ mm1_i_enable <= '0';
+ when c2_busy =>
+ if (mm1_o_busy = '1') then
+ cstate <= c2_busy;
+ else
+ cstate <= c2;
+ end if;
+ when c2 =>
+ cstate <= c3_m_e;
+ if (mm1_o_MemDB(0) = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+ -- XXX ppXp1,ppYp
+ when c3_m_e =>
+ cstate <= c3_m_r_e;
+ mm1_i_enable <= '1';
+ when c3_m_r_e =>
+ cstate <= c3_s_a;
+ mm1_i_read <= '1';
+ when c3_s_a =>
+ cstate <= c3_m_r_d;
+ address_c3 := std_logic_vector(to_unsigned((startAddress + vppYp) + (vppXp1*COLS_PIXEL),G_MemoryAddress-1));
+ mm1_i_MemAdr <= address_c3;
+ when c3_m_r_d =>
+ cstate <= c3_m_d;
+ mm1_i_read <= '0';
+ when c3_m_d =>
+ cstate <= c3_busy;
+ mm1_i_enable <= '0';
+ when c3_busy =>
+ if (mm1_o_busy = '1') then
+ cstate <= c3_busy;
+ else
+ cstate <= c3;
+ end if;
+ when c3 =>
+ cstate <= c4_m_e;
+ if (mm1_o_MemDB(0) = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+ -- XXX ppXm1,ppYp
+ when c4_m_e =>
+ cstate <= c4_m_r_e;
+ mm1_i_enable <= '1';
+ when c4_m_r_e =>
+ cstate <= c4_s_a;
+ mm1_i_read <= '1';
+ when c4_s_a =>
+ cstate <= c4_m_r_d;
+ address_c4 := std_logic_vector(to_unsigned((startAddress + vppYp) + (vppXm1*COLS_PIXEL),G_MemoryAddress-1));
+ mm1_i_MemAdr <= address_c4;
+ when c4_m_r_d =>
+ cstate <= c4_m_d;
+ mm1_i_read <= '0';
+ when c4_m_d =>
+ cstate <= c4_busy;
+ mm1_i_enable <= '0';
+ when c4_busy =>
+ if (mm1_o_busy = '1') then
+ cstate <= c4_busy;
+ else
+ cstate <= c4;
+ end if;
+ when c4 =>
+ cstate <= c5_m_e;
+ if (mm1_o_MemDB(0) = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+ -- XXX ppXm1,ppYm1
+ when c5_m_e =>
+ cstate <= c5_m_r_e;
+ mm1_i_enable <= '1';
+ when c5_m_r_e =>
+ cstate <= c5_s_a;
+ mm1_i_read <= '1';
+ when c5_s_a =>
+ cstate <= c5_m_r_d;
+ address_c5 := std_logic_vector(to_unsigned((startAddress + vppYm1) + (vppXm1*COLS_PIXEL),G_MemoryAddress-1));
+ mm1_i_MemAdr <= address_c5;
+ when c5_m_r_d =>
+ cstate <= c5_m_d;
+ mm1_i_read <= '0';
+ when c5_m_d =>
+ cstate <= c5_busy;
+ mm1_i_enable <= '0';
+ when c5_busy =>
+ if (mm1_o_busy = '1') then
+ cstate <= c5_busy;
+ else
+ cstate <= c5;
+ end if;
+ when c5 =>
+ cstate <= c6_m_e;
+ if (mm1_o_MemDB(0) = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+ -- XXX ppXp1,ppYm1
+ when c6_m_e =>
+ cstate <= c6_m_r_e;
+ mm1_i_enable <= '1';
+ when c6_m_r_e =>
+ cstate <= c6_s_a;
+ mm1_i_read <= '1';
+ when c6_s_a =>
+ cstate <= c6_m_r_d;
+ address_c6 := std_logic_vector(to_unsigned((startAddress + vppYm1) + (vppXp1*COLS_PIXEL),G_MemoryAddress-1));
+ mm1_i_MemAdr <= address_c6;
+ when c6_m_r_d =>
+ cstate <= c6_m_d;
+ mm1_i_read <= '0';
+ when c6_m_d =>
+ cstate <= c6_busy;
+ mm1_i_enable <= '0';
+ when c6_busy =>
+ if (mm1_o_busy = '1') then
+ cstate <= c6_busy;
+ else
+ cstate <= c6;
+ end if;
+ when c6 =>
+ cstate <= c7_m_e;
+ if (mm1_o_MemDB(0) = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+ -- XXX ppXm1,ppYp1
+ when c7_m_e =>
+ cstate <= c7_m_r_e;
+ mm1_i_enable <= '1';
+ when c7_m_r_e =>
+ cstate <= c7_s_a;
+ mm1_i_read <= '1';
+ when c7_s_a =>
+ cstate <= c7_m_r_d;
+ address_c7 := std_logic_vector(to_unsigned((startAddress + vppYp1) + (vppXm1*COLS_PIXEL),G_MemoryAddress-1));
+ mm1_i_MemAdr <= address_c7;
+ when c7_m_r_d =>
+ cstate <= c7_m_d;
+ mm1_i_read <= '0';
+ when c7_m_d =>
+ cstate <= c7_busy;
+ mm1_i_enable <= '0';
+ when c7_busy =>
+ if (mm1_o_busy = '1') then
+ cstate <= c7_busy;
+ else
+ cstate <= c7;
+ end if;
+ when c7 =>
+ cstate <= c8_m_e;
+ if (mm1_o_MemDB(0) = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+ -- XXX ppXp1,ppYp1
+ when c8_m_e =>
+ cstate <= c8_m_r_e;
+ mm1_i_enable <= '1';
+ when c8_m_r_e =>
+ cstate <= c8_s_a;
+ mm1_i_read <= '1';
+ when c8_s_a =>
+ cstate <= c8_m_r_d;
+ address_c8 := std_logic_vector(to_unsigned((startAddress + vppYp1) + (vppXp1*COLS_PIXEL),G_MemoryAddress-1));
+ mm1_i_MemAdr <= address_c8;
+ when c8_m_r_d =>
+ cstate <= c8_m_d;
+ mm1_i_read <= '0';
+ when c8_m_d =>
+ cstate <= c8_busy;
+ mm1_i_enable <= '0';
+ when c8_busy =>
+ if (mm1_o_busy = '1') then
+ cstate <= c8_busy;
+ else
+ cstate <= c8;
+ end if;
+ when c8 =>
+ cstate <= store_neighborhood1;
+ if (mm1_o_MemDB(0) = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+ when store_neighborhood1 =>
+ cstate <= store_neighborhood2;
+ mm2_i_enable <= '1';
+ when store_neighborhood2 =>
+ cstate <= store_neighborhood3;
+ mm2_i_write <= '1';
+ when store_neighborhood3 =>
+ cstate <= store_neighborhood4;
+ address_sca := std_logic_vector(to_unsigned((storeAddress + vppYp) + (vppX*COLS_PIXEL),G_MemoryAddress-1));
+ mm2_i_MemAdr <= address_sca;
+ mm2_i_MemDB <= std_logic_vector(to_unsigned(vcountALive,G_MemoryData));
+ when store_neighborhood4 =>
+ cstate <= store_neighborhood5;
+ mm2_i_write <= '0';
+ when store_neighborhood5 =>
+ cstate <= store_neighborhood6;
+ mm2_i_enable <= '0';
+ when store_neighborhood6 =>
+ if (mm2_o_busy = '1') then
+ cstate <= store_neighborhood6;
+ else
+ cstate <= update_row1;
+ end if;
+ when update_row1 =>
+ if (vppX = ROWS-1) then
+ cstate <= update_col1;
+ else
+ vppX := vppX + 1;
+ cstate <= check_coordinations;
+ end if;
+ when update_col1 =>
+ if (vppYp = COLS_PIXEL-1) then
+ cstate <= reset_counters1;
+ vppYp := 0;
+ else
+ vppYp := vppYp + 1;
+ cstate <= check_coordinations;
+ vppX := 0;
+ end if;
+ -- store bits in memory
+ when reset_counters1 =>
+ cstate <= check_cell_alive1;
+ vppX := 0;
+ vppYp := 0;
+ Led5 <= '0';
+ Led6 <= '0';
+ Led7 <= '1';
+ when check_cell_alive1 =>
+ cstate <= check_cell_alive2;
+ mm1_i_enable <= '1';
+ when check_cell_alive2 =>
+ cstate <= check_cell_alive3;
+ mm1_i_read <= '1';
+ when check_cell_alive3 =>
+ cstate <= check_cell_alive4;
+ address_ga := std_logic_vector(to_unsigned((startAddress + vppYp) + (vppX*COLS_PIXEL),G_MemoryAddress-1));
+ mm1_i_MemAdr <= address_ga;
+ when check_cell_alive4 =>
+ cstate <= check_cell_alive5;
+ mm1_i_read <= '0';
+ when check_cell_alive5 =>
+ cstate <= check_cell_alive6;
+ mm1_i_enable <= '0';
+ when check_cell_alive6 =>
+ if (mm1_o_busy = '1') then
+ cstate <= check_cell_alive6;
+ else
+ cstate <= check_cell_alive7;
+ end if;
+ when check_cell_alive7 =>
+ cstate <= get_stored_neighborhood1;
+ if (mm1_o_MemDB(0) = '1') then
+ vCellAlive := true;
+-- report "get_alive cell at (X,Y)(" & integer'image(vppX) & "," & integer'image(vppYp) & ") = 1 , lower memory data" severity note;
+ else
+ vCellAlive := false;
+-- report "get_alive cell at (X,Y)(" & integer'image(vppX) & "," & integer'image(vppYp) & ") = 0 , lower memory data" severity note;
+ end if;
+ when get_stored_neighborhood1 =>
+ cstate <= get_stored_neighborhood2;
+ mm2_i_enable <= '1';
+ when get_stored_neighborhood2 =>
+ cstate <= get_stored_neighborhood3;
+ mm2_i_read <= '1';
+ when get_stored_neighborhood3 =>
+ cstate <= get_stored_neighborhood4;
+ address_ewm := std_logic_vector(to_unsigned((storeAddress + vppYp) + (vppX*COLS_PIXEL),G_MemoryAddress-1));
+ mm2_i_MemAdr <= address_ewm;
+ when get_stored_neighborhood4 =>
+ cstate <= get_stored_neighborhood5;
+ mm2_i_read <= '0';
+ when get_stored_neighborhood5 =>
+ cstate <= get_stored_neighborhood6;
+ mm2_i_enable <= '0';
+ when get_stored_neighborhood6 =>
+ if (mm2_o_busy = '1') then
+ cstate <= get_stored_neighborhood6;
+ else
+ cstate <= get_stored_neighborhood7;
+ end if;
+ when get_stored_neighborhood7 =>
+ cstate <= write_new_cellalive1;
+ if (vCellAlive = true) then
+ if ((mm2_o_MemDB(G_MemoryData - 1 downto 0) = "010") or (mm2_o_MemDB(G_MemoryData - 1 downto 0) = "011")) then
+ vCellAlive2 := true;
+-- report "previous cell 1,read stored cell at (X,Y)(" & integer'image(vppX) & "," & integer'image(vppYp) & ") = 1 , 2/3" severity note;
+ else
+ vCellAlive2 := false;
+-- report "previous cell 1,read stored cell at (X,Y)(" & integer'image(vppX) & "," & integer'image(vppYp) & ") = 0 , not 2/3" severity note;
+ end if;
+ elsif (vCellAlive = false) then
+ if (mm2_o_MemDB(G_MemoryData - 1 downto 0) = "011") then
+ vCellAlive2 := true;
+-- report "previous cell 0,read stored cell at (X,Y)(" & integer'image(vppX) & "," & integer'image(vppYp) & ") = 1 , 3" severity note;
+ else
+ vCellAlive2 := false;
+-- report "previous cell 0,read stored cell at (X,Y)(" & integer'image(vppX) & "," & integer'image(vppYp) & ") = 0 , not 3" severity note;
+ end if;
+ end if;
+ when write_new_cellalive1 =>
+ cstate <= write_new_cellalive2;
+ mm1_i_enable <= '1';
+ when write_new_cellalive2 =>
+ cstate <= write_new_cellalive3;
+ mm1_i_write <= '1';
+ when write_new_cellalive3 =>
+ cstate <= write_new_cellalive4;
+ address_wca := std_logic_vector(to_unsigned((startAddress + vppYp) + (vppX*COLS_PIXEL),G_MemoryAddress-1));
+ mm1_i_MemAdr <= address_wca;
+ when write_new_cellalive4 =>
+ cstate <= write_new_cellalive5;
+ if (vCellAlive2 = true) then
+ mm1_i_MemDB(0) <= '1';
+-- report "new cell 1,store new cell at (X,Y)(" & integer'image(vppX) & "," & integer'image(vppYp) & ") = 1 , lower memory data" severity note;
+ elsif (vCellAlive2 = false) then
+ mm1_i_MemDB(0) <= '0';
+-- report "new cell 0,store new cell at (X,Y)(" & integer'image(vppX) & "," & integer'image(vppYp) & ") = 0 , lower memory data" severity note;
+ end if;
+ when write_new_cellalive5 =>
+ cstate <= write_new_cellalive6;
+ mm1_i_write <= '0';
+ when write_new_cellalive6 =>
+ cstate <= write_new_cellalive7;
+ mm1_i_enable <= '0';
+ when write_new_cellalive7 =>
+ if (mm1_o_busy = '1') then
+ cstate <= write_new_cellalive7;
+ else
+ cstate <= update_row2;
+ end if;
+ when update_row2 =>
+ if (vppX = ROWS-1) then
+ cstate <= update_col2;
+ else
+ vppX := vppX + 1;
+ cstate <= check_cell_alive1;
+ end if;
+ when update_col2 =>
+ if (vppYp = COLS_PIXEL-1) then
+ cstate <= reset_counters;
+ vppYp := 0;
+ else
+ cstate <= check_cell_alive1;
+ vppYp := vppYp + 1;
+ vppX := 0;
+ end if;
+ end case;
+ end if;
+end process gof_logic;
+
+end architecture Behavioral;
diff --git a/gof/st7735r_initialize.vhd b/gof/st7735r_initialize.vhd
new file mode 100755
index 0000000..bb6dd59
--- /dev/null
+++ b/gof/st7735r_initialize.vhd
@@ -0,0 +1,458 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:41:34 06/14/2021
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.st7735r_p_package.ALL;
+use WORK.st7735r_p_screen.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity st7735r_initialize is
+generic (
+ C_CLOCK_COUNTER : integer
+);
+port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_run : in std_logic;
+ i_color : in COLOR_TYPE;
+ i_sended : in std_logic;
+ o_initialized : out std_logic;
+ o_enable : out std_logic;
+ o_data_byte : out BYTE_TYPE;
+ o_reset : out std_logic;
+ o_rs : out std_logic;
+ o_cs : out std_logic
+);
+end st7735r_initialize;
+
+architecture Behavioral of st7735r_initialize is
+ signal data_byte : BYTE_TYPE;
+ signal sended : std_logic;
+ type states is (
+ idle,
+ -- XXX initialize
+ smallwait0,smallwait1,smallwait2,
+ swreset,initwait0,initwait0a,slpout,initwait1,initwait1a,
+ start,check_index,initwait4,wait0,wait1,initwait4a,
+ noron,initwait2,initwait2a,dispon,initwait3,initwait3a,
+ csup,
+ -- XXX black screen
+ bsinitwait,bsstart,bs_check_index,bswaitdata0,bswait0,bswait1,
+ bswaitdata0a,bsfillbytel,bsfillbytelwait0,bsfillbytelwait0a,
+ bsfillbyteh,bsfillbytehwait0,bsfillbytehwait0a,bsfill_check_index,
+ bscsup,bsfillwait0,bsfillwait1
+ );
+ signal state : states;
+ signal enable,cs,reset,rs,initialized : std_logic;
+ signal data_index : integer range 0 to 2**16-1;
+
+-- signal slv_di : std_logic_vector(15 downto 0);
+
+begin
+
+ o_enable <= enable;
+ o_cs <= cs;
+ o_reset <= reset;
+ o_rs <= rs;
+ o_initialized <= initialized;
+ sended <= i_sended;
+ o_data_byte <= data_byte;
+
+ p0 : process (i_clock,i_reset,sended) is
+ variable w0_index : integer range 0 to 2**25;
+ constant C_CLOCK_COUNTER_7 : integer := C_CLOCK_COUNTER * 7;
+ constant C_CLOCK_COUNTER_150 : integer := C_CLOCK_COUNTER * 150;
+ constant C_CLOCK_COUNTER_500 : integer := C_CLOCK_COUNTER * 500;
+ constant C_CLOCK_COUNTER_10 : integer := C_CLOCK_COUNTER * 10;
+ constant C_CLOCK_COUNTER_100 : integer := C_CLOCK_COUNTER * 100;
+ begin
+-- slv_di <= std_logic_vector(to_unsigned(data_index,16));
+ if (i_reset = '1') then
+ state <= idle;
+ w0_index := 0;
+ data_index <= 0;
+ enable <= '0';
+ cs <= '1';
+ reset <= '1';
+ rs <= '1';
+ initialized <= '0';
+ elsif (rising_edge(i_clock)) then
+ case state is
+ when idle =>
+ initialized <= '0';
+ if (i_run = '1') then
+ state <= smallwait0;
+ else
+ state <= idle;
+ end if;
+ when smallwait0 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= smallwait1;
+ w0_index := 0;
+ reset <= '0';
+ else
+ state <= smallwait0;
+ w0_index := w0_index + 1;
+ cs <= '0';
+ end if;
+ when smallwait1 =>
+ if (w0_index = C_CLOCK_COUNTER_7 - 1) then
+ state <= smallwait2;
+ w0_index := 0;
+ reset <= '1';
+ else
+ state <= smallwait1;
+ w0_index := w0_index + 1;
+ end if;
+ when smallwait2 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= swreset;
+ w0_index := 0;
+ else
+ state <= smallwait2;
+ w0_index := w0_index + 1;
+ end if;
+ when swreset =>
+ data_byte <= x"01";
+ enable <= '1';
+ rs <= '0';
+ if (sended = '1') then
+ state <= initwait0;
+ else
+ state <= swreset;
+ end if;
+ when initwait0 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= initwait0a;
+ w0_index := 0;
+ enable <= '0';
+ rs <= '1';
+ else
+ state <= initwait0;
+ w0_index := w0_index + 1;
+ end if;
+ when initwait0a =>
+ if (w0_index = C_CLOCK_COUNTER_150 - 1) then
+ state <= slpout;
+ w0_index := 0;
+ else
+ state <= initwait0a;
+ w0_index := w0_index + 1;
+ end if;
+ when slpout =>
+ data_byte <= x"11";
+ enable <= '1';
+ rs <= '0';
+ if (sended = '1') then
+ state <= initwait1;
+ else
+ state <= slpout;
+ end if;
+ when initwait1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= initwait1a;
+ w0_index := 0;
+ enable <= '0';
+ rs <= '1';
+ else
+ state <= initwait1;
+ w0_index := w0_index + 1;
+ end if;
+ when initwait1a =>
+ if (w0_index = C_CLOCK_COUNTER_500 - 1) then
+ state <= start;
+ w0_index := 0;
+ else
+ state <= initwait1a;
+ w0_index := w0_index + 1;
+ end if;
+ when start =>
+ data_byte <= data_rom_initscreen(data_index);
+ enable <= '1';
+ if (data_rom_initscreen(data_index + 1) = x"01") then
+ rs <= '0';
+ elsif (data_rom_initscreen(data_index + 1) = x"00") then
+ rs <= '1';
+ end if;
+ if (sended = '1') then
+ state <= check_index;
+ else
+ state <= start;
+ end if;
+ when check_index =>
+ if (data_index = data_size_initscreen - 2) then
+ data_index <= 0;
+ state <= initwait4;
+ else
+ data_index <= data_index + 2;
+ state <= wait0;
+ end if;
+ when wait0 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= wait1;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= wait0;
+ w0_index := w0_index + 1;
+ end if;
+ when wait1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= start;
+ w0_index := 0;
+ else
+ state <= wait1;
+ w0_index := w0_index + 1;
+ end if;
+ when initwait4 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= initwait4a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= initwait4;
+ w0_index := w0_index + 1;
+ end if;
+ when initwait4a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= noron;
+ w0_index := 0;
+ else
+ state <= initwait4a;
+ w0_index := w0_index + 1;
+ end if;
+ when noron =>
+ data_byte <= x"13";
+ enable <= '1';
+ rs <= '0';
+ if (sended = '1') then
+ state <= initwait2;
+ else
+ state <= noron;
+ end if;
+ when initwait2 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= initwait2a;
+ w0_index := 0;
+ enable <= '0';
+ rs <= '1';
+ else
+ state <= initwait2;
+ w0_index := w0_index + 1;
+ end if;
+ when initwait2a =>
+ if (w0_index = C_CLOCK_COUNTER_10 - 1) then
+ state <= dispon;
+ w0_index := 0;
+ else
+ state <= initwait2a;
+ w0_index := w0_index + 1;
+ end if;
+ when dispon =>
+ data_byte <= x"29";
+ enable <= '1';
+ rs <= '0';
+ if (sended = '1') then
+ state <= initwait3;
+ else
+ state <= dispon;
+ end if;
+ when initwait3 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= initwait3a;
+ w0_index := 0;
+ enable <= '0';
+ rs <= '1';
+ else
+ state <= initwait3;
+ w0_index := w0_index + 1;
+ end if;
+ when initwait3a =>
+ if (w0_index = C_CLOCK_COUNTER_100 - 1) then
+ state <= csup;
+ w0_index := 0;
+ else
+ state <= initwait3a;
+ w0_index := w0_index + 1;
+ end if;
+ when csup =>
+ state <= bsinitwait ;
+ enable <= '0';
+ cs <= '1';
+ -----------------------------------------------
+ when bsinitwait =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bsstart;
+ w0_index := 0;
+ else
+ state <= bsinitwait ;
+ w0_index := w0_index + 1;
+ end if;
+ when bsstart =>
+ data_byte <= data_rom_blackscreen(data_index);
+ enable <= '1';
+ if (data_rom_blackscreen(data_index + 1) = x"01") then
+ rs <= '0';
+ elsif (data_rom_blackscreen(data_index + 1) = x"00") then
+ rs <= '1';
+ end if;
+ if (sended = '1') then
+ state <= bs_check_index;
+ else
+ state <= bsstart;
+ end if;
+ when bs_check_index =>
+ if (data_index = data_size_blackscreen - 2) then
+ data_index <= 0;
+ state <= bswaitdata0;
+ else
+ data_index <= data_index + 2;
+ state <= bswait0;
+ end if;
+ when bswait0 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bswait1;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= bswait0;
+ w0_index := w0_index + 1;
+ end if;
+ when bswait1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bsstart;
+ w0_index := 0;
+ else
+ state <= bswait1;
+ w0_index := w0_index + 1;
+ end if;
+ when bswaitdata0 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bswaitdata0a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= bswaitdata0;
+ w0_index := w0_index + 1;
+ end if;
+ when bswaitdata0a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bsfillbytel;
+ w0_index := 0;
+ else
+ state <= bswaitdata0a;
+ w0_index := w0_index + 1;
+ end if;
+ when bsfillbytel =>
+ data_byte <= i_color(15 downto 8);
+ enable <= '1';
+ rs <= '1';
+ if (sended = '1') then
+ state <= bsfillbytelwait0;
+ else
+ state <= bsfillbytel;
+ end if;
+ when bsfillbytelwait0 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bsfillbytelwait0a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= bsfillbytelwait0;
+ w0_index := w0_index + 1;
+ end if;
+ when bsfillbytelwait0a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bsfillbyteh;
+ w0_index := 0;
+ else
+ state <= bsfillbytelwait0a;
+ w0_index := w0_index + 1;
+ end if;
+ when bsfillbyteh =>
+ data_byte <= i_color(7 downto 0);
+ enable <= '1';
+ rs <= '1';
+ if (sended = '1') then
+ state <= bsfillbytehwait0;
+ else
+ state <= bsfillbyteh;
+ end if;
+ when bsfillbytehwait0 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bsfillbytehwait0a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= bsfillbytehwait0;
+ w0_index := w0_index + 1;
+ end if;
+ when bsfillbytehwait0a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bsfill_check_index;
+ w0_index := 0;
+ else
+ state <= bsfillbytehwait0a;
+ w0_index := w0_index + 1;
+ end if;
+ when bsfill_check_index =>
+ if (data_index = SCREEN_FILL - 1) then
+ data_index <= 0;
+ state <= bscsup;
+ initialized <= '1';
+ enable <= '0';
+ else
+ data_index <= data_index + 1;
+ state <= bsfillwait0;
+ end if;
+ when bsfillwait0 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bsfillwait1;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= bsfillwait0;
+ w0_index := w0_index + 1;
+ end if;
+ when bsfillwait1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bsfillbytel;
+ w0_index := 0;
+ else
+ state <= bsfillwait1;
+ w0_index := w0_index + 1;
+ end if;
+ when bscsup =>
+ state <= idle ;
+ cs <= '1';
+ end case;
+ end if;
+ end process p0;
+
+end Behavioral;
+
diff --git a/gof/st7735r_p_package.vhd b/gof/st7735r_p_package.vhd
new file mode 100755
index 0000000..7ce88b3
--- /dev/null
+++ b/gof/st7735r_p_package.vhd
@@ -0,0 +1,27 @@
+--
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+--
+-- To use any of the example code shown below, uncomment the lines and modify as necessary
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package st7735r_p_package is
+
+ constant BYTE_SIZE : integer := 8;
+ subtype BYTE_TYPE is std_logic_vector(BYTE_SIZE - 1 downto 0);
+ constant ABOUT_1coma31_MS: integer := 2**16; --XXX ~1.31ms on 50mhz
+ constant C_CLOCK_COUNTER_S : integer := 2**16; -- XXX slow
+ constant C_CLOCK_COUNTER_F : integer := 2**8; -- XXX fast
+ constant C_CLOCK_COUNTER_VF : integer := 2**4; -- XXX very fast
+ constant C_CLOCK_COUNTER_EF : integer := 2**3; -- XXX extreme fast
+ constant C_CLOCK_COUNTER_MF : integer := 2**2; -- XXX monster fast,not work,this is max in simulation
+
+end st7735r_p_package;
+
+package body st7735r_p_package is
+end st7735r_p_package;
diff --git a/gof/st7735r_p_rom_data.vhd b/gof/st7735r_p_rom_data.vhd
new file mode 100755
index 0000000..19396ba
--- /dev/null
+++ b/gof/st7735r_p_rom_data.vhd
@@ -0,0 +1,35 @@
+--
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+--
+-- To use any of the example code shown below, uncomment the lines and modify as necessary
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use WORK.st7735r_p_package.ALL;
+
+package st7735r_p_rom_data is
+
+ -- in bytes
+ -- 00 - NOP
+ -- 01 color -- initialize screen with fill color index
+ -- 02 color x1 y1 x2 y2 - draw [color] box on [x1,y1] with [x2,y2] dimension
+ constant COUNT_ROM_DATA : integer := 28;
+ type ARRAY_ROM_DATA is array(0 to COUNT_ROM_DATA - 1) of BYTE_TYPE;
+ constant C_ROM_DATA : ARRAY_ROM_DATA := (
+ x"00",
+ x"01",x"02",
+ x"02",x"04",x"10",x"10",x"1f",x"6f",
+ x"02",x"04",x"13",x"13",x"15",x"15",
+ x"02",x"04",x"16",x"16",x"18",x"18",
+ x"02",x"04",x"1a",x"1a",x"1c",x"1c",
+ x"00"
+ );
+
+end st7735r_p_rom_data;
+
+package body st7735r_p_rom_data is
+end st7735r_p_rom_data;
diff --git a/gof/st7735r_p_screen.vhd b/gof/st7735r_p_screen.vhd
new file mode 100755
index 0000000..8cb7334
--- /dev/null
+++ b/gof/st7735r_p_screen.vhd
@@ -0,0 +1,146 @@
+--
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+--
+-- To use any of the example code shown below, uncomment the lines and modify as necessary
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use WORK.st7735r_p_package.ALL;
+
+package st7735r_p_screen is
+
+ -- XXX based on https://github.com/Dungyichao/STM32F4-LCD_ST7735s/blob/master/ST7735/st7735.c
+ -- XXX based on https://github.com/Dungyichao/STM32F4-LCD_ST7735s/blob/master/ST7735/st7735.h
+
+ constant SCREEN_WIDTH : integer := 128;
+ constant SCREEN_HEIGHT : integer := 160;
+ constant SCREEN_AREA : integer := SCREEN_WIDTH * SCREEN_HEIGHT;
+ constant SCREEN_FILL : integer := 2 * SCREEN_AREA;
+
+ subtype COLOR_TYPE is std_logic_vector(15 downto 0);
+ constant SCREEN_BLACK : COLOR_TYPE := x"0000";
+ constant SCREEN_BLUE : COLOR_TYPE := x"001F";
+ constant SCREEN_RED : COLOR_TYPE := x"F800";
+ constant SCREEN_GREEN : COLOR_TYPE := x"07E0";
+ constant SCREEN_CYAN : COLOR_TYPE := x"07FF";
+ constant SCREEN_MAGENTA : COLOR_TYPE := x"F81F";
+ constant SCREEN_YELLOW : COLOR_TYPE := x"FFE0";
+ constant SCREEN_WHITE : COLOR_TYPE := x"FFFF";
+ constant SCREEN_ORANGE : COLOR_TYPE := x"FD60";
+ constant SCREEN_LIGHTGREEN : COLOR_TYPE := x"07EF";
+ constant SCREEN_LIGHTGREY : COLOR_TYPE := x"A514";
+ -- COLOR888_COLOR565(r, g, b) (((r & 0xF8) << 8) | ((g & 0xFC) << 3) | ((b & 0xF8) >> 3))
+
+ constant data_size_initscreen : integer := 83 * 2;
+ type data_array_initscreen is array(0 to data_size_initscreen - 1) of BYTE_TYPE;
+ constant data_rom_initscreen : data_array_initscreen := (
+ x"b1",x"01",--FRMCTR1
+ x"01",x"00",
+ x"2c",x"00",
+ x"2d",x"00",
+ x"b2",x"01",--FRMCTR2
+ x"01",x"00",
+ x"2c",x"00",
+ x"2d",x"00",
+ x"b3",x"01",--FRMCTR3
+ x"01",x"00",
+ x"2c",x"00",
+ x"2d",x"00",
+ x"01",x"00",
+ x"2c",x"00",
+ x"2d",x"00",
+ x"b4",x"01",--INVCTR
+ x"07",x"00",
+ x"c0",x"01",--PWCTR1
+ x"a2",x"00",
+ x"02",x"00",
+ x"84",x"00",
+ x"c1",x"01",--PWCTR2
+ x"c5",x"00",
+ x"c2",x"01",--PWCTR3
+ x"0a",x"00",
+ x"00",x"00",
+ x"c3",x"01",--PWCTR4
+ x"8a",x"00",
+ x"2a",x"00",
+ x"c4",x"01",--PWCTR5
+ x"8a",x"00",
+ x"ee",x"00",
+ x"c5",x"01",--VMCTR1
+ x"0e",x"00",
+ x"20",x"01",--INVOFF
+ x"36",x"01",--MADCTL
+ x"c0",x"00",--ROTATION (ST7735_MADCTL_MX | ST7735_MADCTL_MY) 0x40 | 0x80
+ x"3a",x"01",--COLMOD
+ x"05",x"00",
+ x"2a",x"01",--CASET
+ x"00",x"00",
+ x"00",x"00",
+ x"00",x"00",
+ x"7f",x"00",
+ x"2b",x"01",--RASET
+ x"00",x"00",
+ x"00",x"00",
+ x"00",x"00",
+ x"7f",x"00",
+ x"e0",x"01",--GMCTRP1
+ x"02",x"00",
+ x"1c",x"00",
+ x"07",x"00",
+ x"12",x"00",
+ x"37",x"00",
+ x"32",x"00",
+ x"29",x"00",
+ x"2d",x"00",
+ x"29",x"00",
+ x"25",x"00",
+ x"2b",x"00",
+ x"39",x"00",
+ x"00",x"00",
+ x"01",x"00",
+ x"03",x"00",
+ x"10",x"00",
+ x"e1",x"01",--GMCTRN1
+ x"03",x"00",
+ x"1d",x"00",
+ x"07",x"00",
+ x"06",x"00",
+ x"2e",x"00",
+ x"2c",x"00",
+ x"29",x"00",
+ x"2d",x"00",
+ x"2e",x"00",
+ x"2e",x"00",
+ x"37",x"00",
+ x"3f",x"00",
+ x"00",x"00",
+ x"00",x"00",
+ x"02",x"00",
+ x"10",x"00");
+
+ constant data_size_blackscreen : integer := 11 * 2;
+ type data_array_blackscreen is array(0 to data_size_blackscreen - 1) of BYTE_TYPE;
+ constant data_rom_blackscreen : data_array_blackscreen := (
+ -- XXX sequence for box 1px around
+ -- x"2a",x"01",x"00",x"00",x"01",x"00",x"00",x"00",x"7e",x"00",x"2b",x"01",x"00",x"00",x"01",x"00",x"00",x"00",x"9e",x"00",x"2c",x"01"
+ x"2a",x"01",--CASET
+ x"00",x"00",
+ x"00",x"00",
+ x"00",x"00",
+ x"7f",x"00",
+ x"2b",x"01",--RASET
+ x"00",x"00",
+ x"00",x"00",
+ x"00",x"00",
+ x"9f",x"00",
+ x"2c",x"01" --RAMWR
+ );
+
+end st7735r_p_screen;
+
+package body st7735r_p_screen is
+end st7735r_p_screen;
diff --git a/gof/st7735r_p_store_image_data.vhd b/gof/st7735r_p_store_image_data.vhd
new file mode 100755
index 0000000..2bd5827
--- /dev/null
+++ b/gof/st7735r_p_store_image_data.vhd
@@ -0,0 +1,266 @@
+--
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+--
+-- To use any of the example code shown below, uncomment the lines and modify as necessary
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use WORK.st7735r_p_package.ALL;
+use WORK.p_memory_content.ALL;
+use STD.textio.ALL;
+
+package st7735r_p_store_image_data is
+-- XXX work with memorymodule_bram module
+
+ constant R_EDGE : std_logic := '1';
+ constant F_EDGE : std_logic := '0';
+ subtype byte is std_logic_vector(0 to BYTE_SIZE-1);
+ constant Xs : std_logic_vector(0 to BYTE_SIZE - 1) := (others => 'U');
+
+ type states1 is (idle,start_cs,ck_event,ck_event_increment,stop_cs);
+ shared variable state1 : states1;
+ type states2 is (idle,
+ pattern1,pattern2,pattern3,
+ start,
+ open_file,write_line,wait_done,check_index_rows,check_index_cols,write_file,write_empty_line,close_file,
+ stop);
+ shared variable state2 : states2;
+
+ shared variable data_temp_index : integer;
+
+ shared variable do_temp : byte;
+
+ shared variable done : std_logic;
+ shared variable do_data : byte;
+
+ constant C_FILE_NAME : string := "DataOut.txt";
+ shared variable fstatus : file_open_status;
+ shared variable file_line : line;
+ file fptr : text;
+
+ shared variable index_rows,index_cols : integer;
+ shared variable pattern : string(1 to COLS_PIXEL);
+ constant empty_line : string(1 to COLS_PIXEL) := (others => ' ');
+ function vec2str(vec: std_logic_vector) return string;
+
+ procedure spi_get_byte (
+ signal i_clock : in std_logic;
+ signal i_reset : in std_logic;
+ signal cs : in std_logic;
+ signal do : in std_logic;
+ signal ck : in std_logic;
+ variable done : out std_logic;
+ variable do_data : inout byte
+ );
+
+ procedure st7735r_store_image_fsm (
+ signal i_clock : in std_logic;
+ signal i_reset : in std_logic;
+ signal cs : in std_logic;
+ signal do : in std_logic;
+ signal ck : in std_logic
+ );
+
+end st7735r_p_store_image_data;
+
+package body st7735r_p_store_image_data is
+
+ procedure spi_get_byte (
+ signal i_clock : in std_logic;
+ signal i_reset : in std_logic;
+ signal cs : in std_logic;
+ signal do : in std_logic;
+ signal ck : in std_logic;
+ variable done : out std_logic;
+ variable do_data : inout byte -- XXX default out, inout for report
+ ) is
+ begin
+ if (i_reset = '1') then
+ state1 := idle;
+ data_temp_index := 0;
+ do_temp := (others => '0');
+ done := '0';
+ elsif (rising_edge(i_clock)) then
+ case (state1) is
+ when idle =>
+ state1 := start_cs;
+ data_temp_index := 0;
+ do_temp := (others => '0');
+ done := '0';
+ when start_cs =>
+ if (cs = '0') then
+ state1 := ck_event;
+ else
+ state1 := start_cs;
+ end if;
+ when ck_event =>
+ if (ck = R_EDGE) then
+ state1 := ck_event_increment;
+ do_temp(data_temp_index) := do;
+ else
+ state1 := ck_event;
+ end if;
+ when ck_event_increment =>
+ if (data_temp_index = BYTE_SIZE - 1) then
+ state1 := stop_cs;
+ else
+ state1 := ck_event;
+ data_temp_index := data_temp_index + 1;
+ end if;
+ when stop_cs =>
+ if (cs = '1') then
+ state1 := idle;
+ do_data := do_temp;
+ done := '1';
+-- report "spi_get_byte do_data = " & vec2str(do_data) severity note; -- XXX ok, bin pattern
+ elsif (cs = '0') then
+ state1 := stop_cs;
+ end if;
+ end case;
+ end if;
+ end procedure spi_get_byte;
+
+ procedure st7735r_store_image_fsm (
+ signal i_clock : in std_logic;
+ signal i_reset : in std_logic;
+ signal cs : in std_logic;
+ signal do : in std_logic;
+ signal ck : in std_logic
+ ) is
+ begin
+ if (i_reset = '1') then
+ state2 := open_file;
+ index_rows := 0;
+ index_cols := 0;
+ elsif (rising_edge(i_clock)) then
+ case (state2) is
+ when open_file =>
+ state2 := idle;
+ file_open(fstatus, fptr, C_FILE_NAME, append_mode);
+ when idle =>
+ if (cs = '1') then
+ state2 := idle;
+ else
+ state2 := pattern1;
+ end if;
+ when pattern1 =>
+ if (done = '1') then
+ if (do_data = x"2b") then
+ state2 := pattern2;
+ else
+ state2 := pattern1;
+ end if;
+ else
+ state2 := pattern1;
+ end if;
+ when pattern2 =>
+ if (done = '1') then
+ if (do_data = x"2a") then
+ state2 := pattern3;
+ else
+ state2 := pattern2;
+ end if;
+ else
+ state2 := pattern2;
+ end if;
+ when pattern3 =>
+ if (done = '1') then
+ if (do_data = x"2c") then
+ state2 := write_line;
+ else
+ state2 := pattern3;
+ end if;
+ else
+ state2 := pattern3;
+ end if;
+ when write_line =>
+-- report "index = " & integer'image(index);
+ if (done = '1') then
+ state2 := wait_done;
+ if (do_data = x"ff") then
+ pattern(index_cols + 1) := '*';
+ elsif (do_data = x"00") then
+ pattern(index_cols + 1) := '.';
+ end if;
+ else
+ state2 := write_line;
+ end if;
+ when wait_done =>
+ if (done = '1') then
+ state2 := wait_done;
+ else
+ state2 := check_index_cols;
+ end if;
+ when check_index_cols =>
+ if (index_cols = COLS_PIXEL - 1) then
+ state2 := write_file;
+ index_cols := 0;
+ else
+ state2 := write_line;
+ index_cols := index_cols + 1;
+ end if;
+ when write_file =>
+ state2 := check_index_rows;
+ write(file_line, pattern);
+ writeline(fptr, file_line);
+ when check_index_rows =>
+ if (index_rows = ROWS - 1) then
+ state2 := write_empty_line;
+ index_cols := 0;
+ index_rows := 0;
+ else
+ state2 := write_line;
+ index_rows := index_rows + 1;
+ index_cols := 0;
+ end if;
+ when write_empty_line =>
+ state2 := close_file;
+ write(file_line, empty_line);
+ writeline(fptr, file_line);
+ when close_file =>
+ state2 := stop;
+ file_close(fptr);
+ when stop =>
+ state2 := open_file;
+ when others => null;
+ end case;
+ end if;
+ spi_get_byte(i_clock,i_reset,cs,do,ck,done,do_data);
+ end procedure st7735r_store_image_fsm;
+
+ function vec2str(vec: std_logic_vector) return string is
+ variable result: string(0 to vec'right);
+ begin
+ for i in vec'range loop
+ if (vec(i) = '1') then
+ result(i) := '1';
+ elsif (vec(i) = '0') then
+ result(i) := '0';
+ elsif (vec(i) = 'X') then
+ result(i) := 'X';
+ elsif (vec(i) = 'U') then
+ result(i) := 'U';
+ else
+ result(i) := '?';
+ end if;
+ end loop;
+ return result;
+ end;
+
+-- assert (data_rom(data_rom_index) = data_temp) report "FAIL : (" & integer'image(data_rom_index) & ") " & vec2str(data_temp) & " expect " & vec2str(data_rom(data_rom_index)) severity note;
+-- assert (data_rom(data_rom_index) /= data_temp) report "OK : (" & integer'image(data_rom_index) & ") " & vec2str(data_temp) & " equals " & vec2str(data_rom(data_rom_index)) severity note;
+-- data_temp_index := 0;
+-- if (data_rom_index = data_size - 1) then
+-- data_rom_index := 0;
+-- assert (false) report "=== END TEST ===" severity note;
+-- else
+-- if (data_temp /= Xs) then -- XXX omit first undefined/uninitialized
+-- data_rom_index := data_rom_index + 1;
+-- end if;
+-- end if;
+
+end st7735r_p_store_image_data;
diff --git a/gof/st7735r_tb_top.vhd b/gof/st7735r_tb_top.vhd
new file mode 100755
index 0000000..ea137fa
--- /dev/null
+++ b/gof/st7735r_tb_top.vhd
@@ -0,0 +1,153 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:09:48 11/01/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/i2c_test_3/tb_top.vhd
+-- Project Name: i2c_test_3
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE WORK.st7735r_p_package.ALL;
+USE WORK.p_memory_content.ALL;
+USE WORK.st7735r_p_store_image_data.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY st7735r_tb_top IS
+END st7735r_tb_top;
+
+ARCHITECTURE behavior OF st7735r_tb_top IS
+
+constant IC : integer := 50_000_000; --50_000_000; --29_952_000; --1_000_000;
+constant SPISPEED : integer := C_CLOCK_COUNTER_MF; --C_CLOCK_COUNTER_EF; --C_CLOCK_COUNTER_MF;
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT st7735r_gof
+GENERIC(
+INPUT_CLOCK : integer;
+SPI_SPEED_MODE : integer
+);
+PORT(
+clk : in std_logic;
+btn_1 : in std_logic;
+o_cs : out std_logic;
+o_do : out std_logic;
+o_ck : out std_logic;
+o_reset : out std_logic;
+o_rs : out std_logic;
+Led5 : out std_logic;
+Led6 : out std_logic;
+Led7 : out std_logic;
+o_MemOE : out std_logic;
+o_MemWR : out std_logic;
+o_RamAdv : out std_logic;
+o_RamCS : out std_logic;
+o_RamCRE : out std_logic;
+o_RamLB : out std_logic;
+o_RamUB : out std_logic;
+--i_RamWait : in std_logic;
+o_RamClk : out std_logic;
+o_MemAdr : out MemoryAddress;
+io_MemDB : inout MemoryDataByte;
+o_FlashCS : out std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal clk : std_logic := '0';
+signal btn_1 : std_logic := '0';
+
+--Outputs
+signal o_cs : std_logic;
+signal o_do : std_logic;
+signal o_ck : std_logic;
+signal o_reset : std_logic;
+signal o_rs : std_logic;
+signal o_MemOE,o_MemWR,o_RamAdv,o_RamCS,o_RamLB,o_RamUB,o_RamCRE,i_RamWait,o_RamClk,o_FlashCS : std_logic;
+signal o_MemAdr : MemoryAddress;
+signal io_MemDB : MemoryDataByte;
+signal Led5,Led6,Led7 : std_logic;
+
+-- Clock period definitions
+constant clk_period : time := (1_000_000_000 / IC) * 1 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: st7735r_gof
+GENERIC MAP (
+INPUT_CLOCK => IC,
+SPI_SPEED_MODE => SPISPEED
+)
+PORT MAP (
+clk => clk,
+btn_1 => btn_1,
+o_cs => o_cs,
+o_do => o_do,
+o_ck => o_ck,
+o_reset => o_reset,
+o_rs => o_rs,
+Led5 => Led5,
+Led6 => Led6,
+Led7 => Led7,
+o_MemOE => o_MemOE,
+o_MemWR => o_MemWR,
+o_RamAdv => o_RamAdv,
+o_RamCS => o_RamCS,
+o_RamCRE => o_RamCRE,
+o_RamLB => o_RamLB,
+o_RamUB => o_RamUB,
+--i_RamWait => i_RamWait,
+o_RamClk => o_RamClk,
+o_MemAdr => o_MemAdr,
+io_MemDB => io_MemDB,
+o_FlashCS => o_FlashCS
+);
+
+-- Clock process definitions
+clk_process :process
+begin
+clk <= '0';
+wait for clk_period/2;
+clk <= '1';
+wait for clk_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+btn_1 <= '1';
+wait for 100 ns;
+btn_1 <= '0';
+wait for clk_period*10;
+-- insert stimulus here
+wait;
+end process;
+
+--st7735r_store_image_fsm(clk,btn_1,o_cs,o_do,o_ck); -- XXX for store image in file from st7735r spi
+
+END;
diff --git a/gof/st7735r_top.vhd b/gof/st7735r_top.vhd
new file mode 100755
index 0000000..ab8507d
--- /dev/null
+++ b/gof/st7735r_top.vhd
@@ -0,0 +1,334 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:59:41 06/21/2021
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+--use WORK.p_package.ALL;
+--use WORK.p_screen.ALL;
+--use WORK.p_rom_data.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top is
+Port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ o_cs : out std_logic;
+ o_do : out std_logic;
+ o_ck : out std_logic;
+ o_reset : out std_logic;
+ o_rs : out std_logic
+);
+end top;
+
+architecture Behavioral of top is
+
+ component my_spi is
+ port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_enable : in std_logic;
+ i_data_byte : in BYTE_TYPE;
+ o_cs : out std_logic;
+ o_do : out std_logic;
+ o_ck : out std_logic;
+ o_sended : out std_logic
+ );
+ end component my_spi;
+ signal spi_enable,spi_cs,spi_do,spi_ck,spi_sended : std_logic;
+ signal spi_data_byte : BYTE_TYPE;
+
+ component st7735r_initialize is
+ port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_run : in std_logic;
+ i_color : in COLOR_TYPE;
+ i_sended : in std_logic;
+ o_initialized : out std_logic;
+ o_enable : out std_logic;
+ o_reset : out std_logic;
+ o_rs : out std_logic;
+ o_cs : out std_logic;
+ o_data_byte : out BYTE_TYPE
+ );
+ end component st7735r_initialize;
+ signal initialize_run,initialize_sended : std_logic;
+ signal initialize_initialized,initialize_enable,initialize_reset,initialize_rs,initialize_cs : std_logic;
+ signal initialize_color : COLOR_TYPE;
+ signal initialize_data_byte : BYTE_TYPE;
+
+ component draw_box is
+ port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_run : in std_logic;
+ i_sended : in std_logic;
+ i_color : in COLOR_TYPE;
+ i_raxs : in BYTE_TYPE;
+ i_raxe : in BYTE_TYPE;
+ i_rays : in BYTE_TYPE;
+ i_raye : in BYTE_TYPE;
+ i_caxs : in BYTE_TYPE;
+ i_caxe : in BYTE_TYPE;
+ i_cays : in BYTE_TYPE;
+ i_caye : in BYTE_TYPE;
+ o_data : out BYTE_TYPE;
+ o_enable : out std_logic;
+ o_rs : out std_logic;
+ o_initialized : out std_logic
+ );
+ end component draw_box;
+ signal drawbox_sended,drawbox_enable,drawbox_rs,drawbox_run,drawbox_initialized : std_logic;
+ signal drawbox_raxs,drawbox_raxe,drawbox_rays,drawbox_raye,drawbox_caxs,drawbox_caxe,drawbox_cays,drawbox_caye : BYTE_TYPE;
+ signal drawbox_data : BYTE_TYPE;
+ signal drawbox_color : COLOR_TYPE;
+
+ type states is (
+ idle,
+ start,get_instruction,execute_instruction,
+ get_color,screen_initialize,screen_initialize_finish,
+ get_draw_box,
+ get_draw_box_c1,get_draw_box_c2,get_draw_box_c3,get_draw_box_c4,get_draw_box_c5,get_draw_box_c6,get_draw_box_c7,get_draw_box_c8,
+ get_draw_box_finish,
+ stop);
+ signal state : states;
+
+ signal index0 : integer range 0 to COUNT_ROM_DATA - 1;
+ signal byte_instruciton : BYTE_TYPE;
+
+begin
+
+ o_cs <= spi_cs; -- TODO use initialize_cs mux
+ o_do <= spi_do;
+ o_ck <= spi_ck;
+ o_reset <= initialize_reset when initialize_run = '1' else '1';
+ o_rs <= initialize_rs when initialize_run = '1' else drawbox_rs when drawbox_run = '1' else '1';
+
+ spi_data_byte <= initialize_data_byte when initialize_run = '1' else drawbox_data when drawbox_run = '1' else (others => '0');
+ spi_enable <= initialize_enable when initialize_run = '1' else drawbox_enable when drawbox_run = '1' else '0';
+ initialize_sended <= spi_sended when initialize_run = '1' else '0';
+ drawbox_sended <= spi_sended when drawbox_run = '1' else '0';
+
+ c0 : my_spi
+ port map (
+ i_clock => i_clock,
+ i_reset => i_reset,
+ i_enable => spi_enable,
+ i_data_byte => spi_data_byte,
+ o_cs => spi_cs,
+ o_do => spi_do,
+ o_ck => spi_ck,
+ o_sended => spi_sended
+ );
+
+ c1 : st7735r_initialize
+ port map (
+ i_clock => i_clock,
+ i_reset => i_reset,
+ i_run => initialize_run,
+ i_color => initialize_color,
+ i_sended => initialize_sended,
+ o_initialized => initialize_initialized,
+ o_cs => initialize_cs,
+ o_reset => initialize_reset,
+ o_rs => initialize_rs,
+ o_enable => initialize_enable,
+ o_data_byte => initialize_data_byte
+ );
+
+ c2 : draw_box
+ port map (
+ i_clock => i_clock,
+ i_reset => i_reset,
+ i_run => drawbox_run,
+ i_sended => drawbox_sended,
+ i_color => drawbox_color,
+ i_raxs => drawbox_raxs,
+ i_raxe => drawbox_raxe,
+ i_rays => drawbox_rays,
+ i_raye => drawbox_raye,
+ i_caxs => drawbox_caxs,
+ i_caxe => drawbox_caxe,
+ i_cays => drawbox_cays,
+ i_caye => drawbox_caye,
+ o_data => drawbox_data,
+ o_enable => drawbox_enable,
+ o_rs => drawbox_rs,
+ o_initialized => drawbox_initialized
+ );
+
+ p1 : process (byte_instruciton,initialize_run,drawbox_run) is -- TODO use mux
+ begin
+ if (initialize_run = '1' or drawbox_run = '1') then
+ case (byte_instruciton) is
+ when x"00" =>
+ initialize_color <= SCREEN_BLACK;
+ drawbox_color <= SCREEN_BLACK;
+ when x"01" =>
+ initialize_color <= SCREEN_BLUE;
+ drawbox_color <= SCREEN_BLUE;
+ when x"02" =>
+ initialize_color <= SCREEN_RED;
+ drawbox_color <= SCREEN_RED;
+ when x"03" =>
+ initialize_color <= SCREEN_GREEN;
+ drawbox_color <= SCREEN_GREEN;
+ when x"04" =>
+ initialize_color <= SCREEN_CYAN;
+ drawbox_color <= SCREEN_CYAN;
+ when x"05" =>
+ initialize_color <= SCREEN_MAGENTA;
+ drawbox_color <= SCREEN_MAGENTA;
+ when x"06" =>
+ initialize_color <= SCREEN_YELLOW;
+ drawbox_color <= SCREEN_YELLOW;
+ when x"07" =>
+ initialize_color <= SCREEN_WHITE;
+ drawbox_color <= SCREEN_WHITE;
+ when x"08" =>
+ initialize_color <= SCREEN_ORANGE;
+ drawbox_color <= SCREEN_ORANGE;
+ when x"09" =>
+ initialize_color <= SCREEN_LIGHTGREEN;
+ drawbox_color <= SCREEN_LIGHTGREEN;
+ when x"0a" =>
+ initialize_color <= SCREEN_LIGHTGREY;
+ drawbox_color <= SCREEN_LIGHTGREY;
+ when others =>
+ initialize_color <= SCREEN_BLACK;
+ drawbox_color <= SCREEN_BLACK;
+ end case;
+ else
+ initialize_color <= SCREEN_BLACK;
+ drawbox_color <= SCREEN_BLACK;
+ end if;
+ end process p1;
+
+ p_control : process (i_clock,i_reset,initialize_initialized) is
+ begin
+ if (i_reset = '1') then
+ state <= idle;
+ elsif (rising_edge(i_clock)) then
+ case (state) is
+ when idle =>
+ state <= start;
+ byte_instruciton <= (others => '0');
+ initialize_run <= '0';
+ drawbox_run <= '0';
+ index0 <= 0;
+ drawbox_raxs <= (others => '0');
+ drawbox_raxe <= (others => '0');
+ drawbox_rays <= (others => '0');
+ drawbox_raye <= (others => '0');
+ drawbox_caxs <= (others => '0');
+ drawbox_caxe <= (others => '0');
+ drawbox_cays <= (others => '0');
+ drawbox_caye <= (others => '0');
+ when start =>
+ state <= get_instruction;
+ when get_instruction =>
+ state <= execute_instruction;
+ byte_instruciton <= C_ROM_DATA(index0);
+ index0 <= index0 + 1;
+ when execute_instruction =>
+ case (byte_instruciton) is
+ when x"00" =>
+ state <= get_instruction;
+ when x"01" =>
+ state <= get_color;
+ when x"02" =>
+ state <= get_draw_box;
+ when others => null;
+ end case;
+ when get_color =>
+ state <= screen_initialize;
+ byte_instruciton <= C_ROM_DATA(index0);
+ index0 <= index0 + 1;
+ initialize_run <= '1';
+ when screen_initialize =>
+ if (initialize_initialized = '1') then
+ state <= screen_initialize_finish;
+ initialize_run <= '0';
+ else
+ state <= screen_initialize;
+ end if;
+ when screen_initialize_finish =>
+ state <= start;
+ when get_draw_box =>
+ state <= get_draw_box_c1;
+ byte_instruciton <= C_ROM_DATA(index0);
+ index0 <= index0 + 1;
+ drawbox_run <= '1';
+ when get_draw_box_c1 =>
+ state <= get_draw_box_c2;
+ drawbox_raxs <= x"00";
+ when get_draw_box_c2 =>
+ state <= get_draw_box_c3;
+ drawbox_raxe <= C_ROM_DATA(index0);
+ index0 <= index0 + 1;
+ when get_draw_box_c3 =>
+ state <= get_draw_box_c4;
+ drawbox_rays <= x"00";
+ when get_draw_box_c4 =>
+ state <= get_draw_box_c5;
+ drawbox_raye <= C_ROM_DATA(index0);
+ index0 <= index0 + 1;
+ when get_draw_box_c5 =>
+ state <= get_draw_box_c6;
+ drawbox_caxs <= x"00";
+ when get_draw_box_c6 =>
+ state <= get_draw_box_c7;
+ drawbox_caxe <= C_ROM_DATA(index0);
+ index0 <= index0 + 1;
+ when get_draw_box_c7 =>
+ state <= get_draw_box_c8;
+ drawbox_cays <= x"00";
+ when get_draw_box_c8 =>
+ state <= get_draw_box_finish;
+ drawbox_caye <= C_ROM_DATA(index0);
+ index0 <= index0 + 1;
+ when get_draw_box_finish =>
+ if (drawbox_initialized = '1') then
+ state <= stop;
+ drawbox_run <= '0';
+ else
+ state <= get_draw_box_finish;
+ end if;
+ when stop =>
+ if (index0 = COUNT_ROM_DATA - 1) then
+ state <= stop;
+ else
+ state <= start;
+ end if;
+ when others =>
+ state <= idle;
+ end case;
+ end if;
+ end process p_control;
+
+end Behavioral;
+
diff --git a/gof/synthesis-top.sh b/gof/synthesis-top.sh
new file mode 100755
index 0000000..5326064
--- /dev/null
+++ b/gof/synthesis-top.sh
@@ -0,0 +1,48 @@
+#!/bin/sh
+
+mkdir -p xst/projnav.tmp/
+
+xst -intstyle ise -ifn ./top.xst -ofn ./top.syr
+if [ $? -ne 0 ];
+then
+ echo "error on xst";
+ exit;
+else
+ ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Nexys2_1200General.ucf -p xc3s1200e-fg320-4 top.ngc top.ngd
+ if [ $? -ne 0 ];
+ then
+ echo "error on ngdbuild";
+ exit;
+ else
+ map -intstyle ise -p xc3s1200e-fg320-4 -ol std -timing -cm balanced -ir off -pr off -o top_map.ncd top.ngd top.pcf
+ if [ $? -ne 0 ];
+ then
+ echo "error on map";
+ exit;
+ else
+ par -w -intstyle ise -ol std -rl std -t 1 top_map.ncd top.ncd top.pcf
+ if [ $? -ne 0 ];
+ then
+ echo "error on par";
+ exit;
+ else
+ trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf -ucf Nexys2_1200General.ucf
+ if [ $? -ne 0 ];
+ then
+ echo "error on trce";
+ exit;
+ else
+ bitgen -intstyle ise -f top.ut top.ncd
+ if [ $? -ne 0 ];
+ then
+ echo "error on bitgen";
+ exit;
+ else
+ ls -l top.bit
+ fi
+ fi
+ fi
+ fi
+ fi
+fi
+
diff --git a/gof/tb_clock_divider.vhd b/gof/tb_clock_divider.vhd
new file mode 100755
index 0000000..5de9bb8
--- /dev/null
+++ b/gof/tb_clock_divider.vhd
@@ -0,0 +1,99 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:47:22 11/23/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/gof/tb_clock_divider.vhd
+-- Project Name: gof
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: clock_divider
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_clock_divider IS
+END tb_clock_divider;
+
+ARCHITECTURE behavior OF tb_clock_divider IS
+
+signal BC : INTEGER := 50_000_000;
+
+COMPONENT clock_divider
+PORT(
+ i_clk : IN STD_LOGIC;
+ i_board_clock : IN INTEGER;
+ i_divider : IN INTEGER;
+ o_clk : OUT STD_LOGIC
+);
+END COMPONENT;
+
+--Inputs
+signal i_clk : std_logic;
+
+--Outputs
+signal o_clk : std_logic;
+
+-- Clock period definitions
+constant i_clk_period : time := (1_000_000_000 / BC) * 1 ns;
+
+signal CD : INTEGER; -- divider
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: clock_divider
+PORT MAP (
+ i_clk => i_clk,
+ i_board_clock => BC,
+ i_divider => CD,
+ o_clk => o_clk
+);
+
+-- Clock process definitions
+i_clk_process :process
+begin
+ i_clk <= '0';
+ wait for i_clk_period/2;
+ i_clk <= '1';
+ wait for i_clk_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+ wait for i_clk_period*10;
+ -- insert stimulus here
+ CD <= 40;
+ wait for 100 ms;
+ CD <= 100;
+ wait for 100 ms;
+ CD <= 40;
+ wait for 100 ms;
+ CD <= 100;
+ wait;
+end process;
+
+END;
diff --git a/gof/tb_clock_divider.wcfg b/gof/tb_clock_divider.wcfg
new file mode 100755
index 0000000..c1915fc
--- /dev/null
+++ b/gof/tb_clock_divider.wcfg
@@ -0,0 +1,59 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ tb
+ label
+
+ bc
+ bc
+
+
+ i_clk
+ i_clk
+
+
+ o_clk
+ o_clk
+
+
+ cd
+ cd
+
+
+ i_clk_period
+ i_clk_period
+
+
+
+ uut
+ label
+
+ i_clk
+ i_clk
+
+
+ i_board_clock
+ i_board_clock
+
+
+ i_divider
+ i_divider
+
+
+ o_clk
+ o_clk
+
+
+
diff --git a/gof/tb_memory1_bit.vhd b/gof/tb_memory1_bit.vhd
new file mode 100755
index 0000000..72a2a58
--- /dev/null
+++ b/gof/tb_memory1_bit.vhd
@@ -0,0 +1,764 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:32:08 11/11/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/gof/tb_memory1.vhd
+-- Project Name: gof
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: memory1
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+use WORK.p_memory_content.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_memory1_bit IS
+END tb_memory1_bit;
+
+ARCHITECTURE behavior OF tb_memory1_bit IS
+
+ COMPONENT memory1
+ PORT(
+ i_clk : in std_logic;
+ i_reset : in std_logic;
+ i_enable_byte : in std_logic;
+ i_enable_bit : in std_logic;
+ i_write_byte : in std_logic;
+ i_write_bit : in std_logic;
+ i_row : in std_logic_vector(ROWS_BITS-1 downto 0);
+ i_col_pixel : in std_logic_vector(COLS_PIXEL_BITS-1 downto 0);
+ i_col_block : in std_logic_vector(COLS_BLOCK_BITS-1 downto 0);
+ i_byte : in std_logic_vector(BYTE_BITS-1 downto 0);
+ i_bit : in std_logic;
+ o_byte : out std_logic_vector(BYTE_BITS-1 downto 0);
+ o_bit : out std_logic);
+ END COMPONENT;
+
+ --Inputs - leave bit options and set default byte to 0
+ signal i_clk : std_logic;
+ signal i_reset : std_logic;
+ signal i_enable_byte : std_logic := '0';
+ signal i_enable_bit : std_logic;
+ signal i_write_byte : std_logic := '0';
+ signal i_write_bit : std_logic;
+ signal i_row : std_logic_vector(ROWS_BITS-1 downto 0);
+ signal i_col_pixel : std_logic_vector(COLS_PIXEL_BITS-1 downto 0);
+ signal i_col_block : std_logic_vector(COLS_BLOCK_BITS-1 downto 0) := (others => '0');
+ signal i_byte : std_logic_vector(BYTE_BITS-1 downto 0) := (others => '0');
+ signal i_bit : std_logic;
+
+ --Outputs - leave bit options and set default byte to 0
+ signal o_byte : std_logic_vector(BYTE_BITS-1 downto 0) := (others => '0');
+ signal o_bit : std_logic;
+
+ -- Clock period definitions
+ constant i_clk_period : time := 20 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: memory1 PORT MAP (
+ i_clk => i_clk,
+ i_reset => i_reset,
+ i_enable_byte => i_enable_byte,
+ i_enable_bit => i_enable_bit,
+ i_write_byte => i_write_byte,
+ i_write_bit => i_write_bit,
+ i_row => i_row,
+ i_col_pixel => i_col_pixel,
+ i_col_block => i_col_block,
+ i_byte => i_byte,
+ i_bit => i_bit,
+ o_byte => o_byte,
+ o_bit => o_bit
+ );
+
+ -- Clock process definitions
+ i_clk_process :process
+ begin
+ i_clk <= '0';
+ wait for i_clk_period/2;
+ i_clk <= '1';
+ wait for i_clk_period/2;
+ end process;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ i_reset <= '1';
+ wait for i_clk_period;
+ i_reset <= '0';
+ wait for i_clk_period+i_clk_period/2; -- from rising edge
+
+ --
+ -- 12 random pixels - first/last two have 0 and rest have 1
+ --
+
+ -- enable module
+ i_enable_bit <= '1';
+
+ i_row <= std_logic_vector(to_unsigned(123,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(13,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(29,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(25,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(127,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(116,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(20,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(43,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(9,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(116,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(96,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(0,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(65,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(62,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(28,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(43,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(9,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(29,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(2,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(19,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(16,5));
+ wait for i_clk_period;
+
+ -- disable module
+ i_enable_bit <= '0';
+
+ -- better visible in simulation
+ i_row <= (others => 'U');
+ i_col_pixel <= (others => 'U');
+ i_enable_bit <= 'U';
+
+ wait for 10*i_clk_period;
+
+ --
+ -- 12 writes 1 bit - write sequence 010101010101
+ --
+
+ -- enable module and enable write
+ i_enable_bit <= '1';
+ i_write_bit <= '1';
+
+ i_row <= std_logic_vector(to_unsigned(123,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(13,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(29,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(25,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(127,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(116,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(20,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(43,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(9,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(116,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(96,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(0,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(65,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(62,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(28,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(43,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(9,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(29,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(2,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(19,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(16,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ -- disable module
+ i_enable_bit <= '0';
+ i_write_bit <= '0';
+
+ -- better visible in simulation
+ i_row <= (others => 'U');
+ i_col_pixel <= (others => 'U');
+ i_enable_bit <= 'U';
+ i_write_bit <= 'U';
+ i_bit <= 'U';
+
+ wait for 10*i_clk_period;
+
+ --
+ -- 12 reads the same 1 bit - sequence 010101010101
+ --
+
+ -- enable module
+ i_enable_bit <= '1';
+
+ i_row <= std_logic_vector(to_unsigned(123,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(13,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(29,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(25,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(127,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(116,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(20,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(43,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(9,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(116,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(96,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(0,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(65,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(62,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(28,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(43,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(9,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(29,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(2,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(19,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(16,5));
+ wait for i_clk_period;
+
+ -- disable module
+ i_enable_bit <= '0';
+
+ -- better visible in simulation
+ i_row <= (others => 'U');
+ i_col_pixel <= (others => 'U');
+ i_enable_bit <= 'U';
+
+ wait for 10*i_clk_period;
+
+ --
+ -- 12 writes 1 bit - write sequence 101010101010
+ --
+
+ -- enable module and enable write
+ i_enable_bit <= '1';
+ i_write_bit <= '1';
+
+ i_row <= std_logic_vector(to_unsigned(123,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(13,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(29,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(25,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(127,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(116,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(20,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(43,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(9,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(116,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(96,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(0,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(65,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(62,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(28,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(43,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(9,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(29,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(2,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(19,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(16,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ -- disable module
+ i_enable_bit <= '0';
+ i_write_bit <= '0';
+
+ -- better visible in simulation
+ i_row <= (others => 'U');
+ i_col_pixel <= (others => 'U');
+ i_enable_bit <= 'U';
+ i_write_bit <= 'U';
+ i_bit <= 'U';
+
+ wait for 10*i_clk_period;
+
+ --
+ -- 12 reads the same 1 bit - sequence 101010101010
+ --
+
+ -- enable module
+ i_enable_bit <= '1';
+
+ i_row <= std_logic_vector(to_unsigned(123,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(13,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(29,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(25,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(127,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(116,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(20,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(43,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(9,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(116,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(96,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(0,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(65,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(62,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(28,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(43,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(9,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(29,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(2,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(19,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(16,5));
+ wait for i_clk_period;
+
+ -- disable module
+ i_enable_bit <= '0';
+
+ -- better visible in simulation
+ i_row <= (others => 'U');
+ i_col_pixel <= (others => 'U');
+ i_enable_bit <= 'U';
+
+ wait for 10*i_clk_period;
+
+ --
+ -- 12 writes 1 bit - write sequence 111111111111
+ --
+
+ -- enable module and enable write
+ i_enable_bit <= '1';
+ i_write_bit <= '1';
+
+ i_row <= std_logic_vector(to_unsigned(123,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(13,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(29,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(25,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(127,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(116,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(20,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(43,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(9,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(116,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(96,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(0,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(65,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(62,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(28,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(43,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(9,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(29,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(2,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(19,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(16,5));
+ i_bit <= '1';
+ wait for i_clk_period;
+
+ -- disable module
+ i_enable_bit <= '0';
+ i_write_bit <= '0';
+
+ -- better visible in simulation
+ i_row <= (others => 'U');
+ i_col_pixel <= (others => 'U');
+ i_enable_bit <= 'U';
+ i_write_bit <= 'U';
+ i_bit <= 'U';
+
+ wait for 10*i_clk_period;
+
+ --
+ -- 12 reads the same 1 bit - sequence 111111111111
+ --
+
+ -- enable module
+ i_enable_bit <= '1';
+
+ i_row <= std_logic_vector(to_unsigned(123,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(13,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(29,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(25,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(127,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(116,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(20,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(43,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(9,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(116,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(96,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(0,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(65,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(62,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(28,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(43,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(9,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(29,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(2,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(19,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(16,5));
+ wait for i_clk_period;
+
+ -- disable module
+ i_enable_bit <= '0';
+
+ -- better visible in simulation
+ i_row <= (others => 'U');
+ i_col_pixel <= (others => 'U');
+ i_enable_bit <= 'U';
+
+ wait for 10*i_clk_period;
+
+ --
+ -- 12 writes 1 bit - write sequence 000000000000
+ --
+
+ -- enable module and enable write
+ i_enable_bit <= '1';
+ i_write_bit <= '1';
+
+ i_row <= std_logic_vector(to_unsigned(123,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(13,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(29,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(25,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(127,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(116,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(20,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(43,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(9,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(116,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(96,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(0,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(65,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(62,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(28,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(43,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(9,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(29,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(2,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(19,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(16,5));
+ i_bit <= '0';
+ wait for i_clk_period;
+
+ -- disable module
+ i_enable_bit <= '0';
+ i_write_bit <= '0';
+
+ -- better visible in simulation
+ i_row <= (others => 'U');
+ i_col_pixel <= (others => 'U');
+ i_enable_bit <= 'U';
+ i_write_bit <= 'U';
+ i_bit <= 'U';
+
+ wait for 10*i_clk_period;
+
+ --
+ -- 12 reads the same 1 bit - sequence 000000000000
+ --
+
+ -- enable module
+ i_enable_bit <= '1';
+
+ i_row <= std_logic_vector(to_unsigned(123,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(13,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(29,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(25,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(127,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(116,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(20,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(43,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(9,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(116,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(96,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(0,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(65,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(31,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(62,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(28,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(43,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(9,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(29,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(2,5));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(19,7));
+ i_col_pixel <= std_logic_vector(to_unsigned(16,5));
+ wait for i_clk_period;
+
+ -- disable module
+ i_enable_bit <= '0';
+
+ -- better visible in simulation
+ i_row <= (others => 'U');
+ i_col_pixel <= (others => 'U');
+ i_enable_bit <= 'U';
+
+ wait;
+ end process;
+
+END;
diff --git a/gof/tb_memory1_bit.wcfg b/gof/tb_memory1_bit.wcfg
new file mode 100755
index 0000000..3eec989
--- /dev/null
+++ b/gof/tb_memory1_bit.wcfg
@@ -0,0 +1,71 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ports
+ label
+
+ i_clk
+ i_clk
+
+
+ i_reset
+ i_reset
+
+
+ i_enable_bit
+ i_enable_bit
+
+
+ i_write_bit
+ i_write_bit
+
+
+ i_bit
+ i_bit
+
+
+ pixels
+ label
+
+ i_row[6:0]
+ i_row[6:0]
+ UNSIGNEDDECRADIX
+
+
+ i_col_pixel[4:0]
+ i_col_pixel[4:0]
+ UNSIGNEDDECRADIX
+
+
+ o_bit
+ o_bit
+
+
+ t_col_p1[1:0]
+ t_col_p1[1:0]
+ UNSIGNEDDECRADIX
+
+
+ t_col_p2[2:0]
+ t_col_p2[2:0]
+ UNSIGNEDDECRADIX
+
+
+
+
diff --git a/gof/tb_memory1_bit_beh.prj b/gof/tb_memory1_bit_beh.prj
new file mode 100755
index 0000000..6929dad
--- /dev/null
+++ b/gof/tb_memory1_bit_beh.prj
@@ -0,0 +1,3 @@
+vhdl work "memory1.vhd"
+vhdl work "p_memory_content.vhd"
+vhdl work "tb_memory1_bit.vhd"
diff --git a/gof/tb_memory1_byte.vhd b/gof/tb_memory1_byte.vhd
new file mode 100755
index 0000000..06cf2e2
--- /dev/null
+++ b/gof/tb_memory1_byte.vhd
@@ -0,0 +1,252 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:32:08 11/11/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/gof/tb_memory1.vhd
+-- Project Name: gof
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: memory1
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+use WORK.p_memory_content.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_memory1_byte IS
+END tb_memory1_byte;
+
+ARCHITECTURE behavior OF tb_memory1_byte IS
+
+ COMPONENT memory1
+ PORT(
+ i_clk : in std_logic;
+ i_reset : in std_logic;
+ i_enable_byte : in std_logic;
+ i_enable_bit : in std_logic;
+ i_write_byte : in std_logic;
+ i_write_bit : in std_logic;
+ i_row : in std_logic_vector(ROWS_BITS-1 downto 0);
+ i_col_pixel : in std_logic_vector(COLS_PIXEL_BITS-1 downto 0);
+ i_col_block : in std_logic_vector(COLS_BLOCK_BITS-1 downto 0);
+ i_byte : in std_logic_vector(BYTE_BITS-1 downto 0);
+ i_bit : in std_logic;
+ o_byte : out std_logic_vector(BYTE_BITS-1 downto 0);
+ o_bit : out std_logic);
+ END COMPONENT;
+
+ --Inputs - leave byte options and set default bit to 0
+ signal i_clk : std_logic;
+ signal i_reset : std_logic;
+ signal i_enable_byte : std_logic;
+ signal i_enable_bit : std_logic := '0';
+ signal i_write_byte : std_logic;
+ signal i_write_bit : std_logic := '0';
+ signal i_row : std_logic_vector(ROWS_BITS-1 downto 0);
+ signal i_col_pixel : std_logic_vector(COLS_PIXEL_BITS-1 downto 0) := (others => '0');
+ signal i_col_block : std_logic_vector(COLS_BLOCK_BITS-1 downto 0);
+ signal i_byte : std_logic_vector(BYTE_BITS-1 downto 0);
+ signal i_bit : std_logic := '0';
+
+ --Outputs - leave byte options and set default bit to 0
+ signal o_byte : std_logic_vector(BYTE_BITS-1 downto 0);
+ signal o_bit : std_logic := '0';
+
+ -- Clock period definitions
+ constant i_clk_period : time := 20 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: memory1 PORT MAP (
+ i_clk => i_clk,
+ i_reset => i_reset,
+ i_enable_byte => i_enable_byte,
+ i_enable_bit => i_enable_bit,
+ i_write_byte => i_write_byte,
+ i_write_bit => i_write_bit,
+ i_row => i_row,
+ i_col_pixel => i_col_pixel,
+ i_col_block => i_col_block,
+ i_byte => i_byte,
+ i_bit => i_bit,
+ o_byte => o_byte,
+ o_bit => o_bit
+ );
+
+ -- Clock process definitions
+ i_clk_process :process
+ begin
+ i_clk <= '0';
+ wait for i_clk_period/2;
+ i_clk <= '1';
+ wait for i_clk_period/2;
+ end process;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ i_reset <= '1';
+ wait for i_clk_period;
+ i_reset <= '0';
+ wait for i_clk_period+i_clk_period/2;
+
+ --
+ -- output byte from row 3-10 and col 3
+ --
+
+ -- enable module
+ i_enable_byte <= '1';
+
+ -- 10000000
+ i_row <= std_logic_vector(to_unsigned(3,7));
+ i_col_block <= std_logic_vector(to_unsigned(3,2));
+ wait for i_clk_period;
+
+ -- 01000000
+ i_row <= std_logic_vector(to_unsigned(4,7));
+ i_col_block <= std_logic_vector(to_unsigned(3,2));
+ wait for i_clk_period;
+
+ -- 00100000
+ i_row <= std_logic_vector(to_unsigned(5,7));
+ i_col_block <= std_logic_vector(to_unsigned(3,2));
+ wait for i_clk_period;
+
+ -- 00010000
+ i_row <= std_logic_vector(to_unsigned(6,7));
+ i_col_block <= std_logic_vector(to_unsigned(3,2));
+ wait for i_clk_period;
+
+ -- 00001000
+ i_row <= std_logic_vector(to_unsigned(7,7));
+ i_col_block <= std_logic_vector(to_unsigned(3,2));
+ wait for i_clk_period;
+
+ -- 00000100
+ i_row <= std_logic_vector(to_unsigned(8,7));
+ i_col_block <= std_logic_vector(to_unsigned(3,2));
+ wait for i_clk_period;
+
+ -- 00000010
+ i_row <= std_logic_vector(to_unsigned(9,7));
+ i_col_block <= std_logic_vector(to_unsigned(3,2));
+ wait for i_clk_period;
+
+ -- 00000001
+ i_row <= std_logic_vector(to_unsigned(10,7));
+ i_col_block <= std_logic_vector(to_unsigned(3,2));
+ wait for i_clk_period;
+
+ -- disable module
+ i_enable_byte <= 'U';
+
+ -- better visible in simulation
+ i_row <= (others => 'U');
+ i_col_block <= (others => 'U');
+
+ wait for 10*i_clk_period;
+
+ -- 3 writes block byte in random positions
+
+ -- enable and write to module
+ i_enable_byte <= '1';
+ i_write_byte <= '1';
+
+ -- write 0 where we have ones
+ i_row <= std_logic_vector(to_unsigned(0,7));
+ i_col_block <= std_logic_vector(to_unsigned(3,2));
+ i_byte <= x"55";
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(0,7));
+ i_col_block <= std_logic_vector(to_unsigned(2,2));
+ i_byte <= x"AA";
+ wait for i_clk_period;
+
+ -- write 1 where we have zeros
+ i_row <= std_logic_vector(to_unsigned(65,7));
+ i_col_block <= std_logic_vector(to_unsigned(2,2));
+ i_byte <= x"55";
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(65,7));
+ i_col_block <= std_logic_vector(to_unsigned(1,2));
+ i_byte <= x"AA";
+ wait for i_clk_period;
+
+ -- write 16bit 01...01 to random
+ i_row <= std_logic_vector(to_unsigned(117,7));
+ i_col_block <= std_logic_vector(to_unsigned(2,2));
+ i_byte <= x"55";
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(117,7));
+ i_col_block <= std_logic_vector(to_unsigned(1,2));
+ i_byte <= x"AA";
+ wait for i_clk_period;
+
+ -- disable write
+ i_enable_byte <= 'U';
+ i_write_byte <= 'U';
+ i_row <= (others => 'U');
+ i_col_block <= (others => 'U');
+ i_byte <= (others => 'U');
+
+ wait for 10*i_clk_period;
+
+ -- check the writes
+ i_enable_byte <= '1';
+
+ i_row <= std_logic_vector(to_unsigned(0,7));
+ i_col_block <= std_logic_vector(to_unsigned(3,2));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(0,7));
+ i_col_block <= std_logic_vector(to_unsigned(2,2));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(65,7));
+ i_col_block <= std_logic_vector(to_unsigned(2,2));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(65,7));
+ i_col_block <= std_logic_vector(to_unsigned(1,2));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(117,7));
+ i_col_block <= std_logic_vector(to_unsigned(2,2));
+ wait for i_clk_period;
+
+ i_row <= std_logic_vector(to_unsigned(117,7));
+ i_col_block <= std_logic_vector(to_unsigned(1,2));
+ wait for i_clk_period;
+
+ i_enable_byte <= 'U';
+ i_row <= (others => 'U');
+ i_col_block <= (others => 'U');
+
+ wait;
+ end process;
+
+END;
diff --git a/gof/tb_memory1_byte.wcfg b/gof/tb_memory1_byte.wcfg
new file mode 100755
index 0000000..c2517a7
--- /dev/null
+++ b/gof/tb_memory1_byte.wcfg
@@ -0,0 +1,61 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ports
+ label
+
+ i_clk
+ i_clk
+
+
+ i_reset
+ i_reset
+
+
+ i_enable_byte
+ i_enable_byte
+
+
+ i_write_byte
+ i_write_byte
+
+
+ i_byte[7:0]
+ i_byte[7:0]
+
+
+ blocks
+ label
+
+ i_row[6:0]
+ i_row[6:0]
+ UNSIGNEDDECRADIX
+
+
+ i_col_block[1:0]
+ i_col_block[1:0]
+ UNSIGNEDDECRADIX
+
+
+ o_byte[7:0]
+ o_byte[7:0]
+
+
+
+
diff --git a/gof/tb_memory1_byte_beh.prj b/gof/tb_memory1_byte_beh.prj
new file mode 100755
index 0000000..39bb12d
--- /dev/null
+++ b/gof/tb_memory1_byte_beh.prj
@@ -0,0 +1,3 @@
+vhdl work "memory1.vhd"
+vhdl work "p_memory_content.vhd"
+vhdl work "tb_memory1_byte.vhd"
diff --git a/gof/tb_memory2.vhd b/gof/tb_memory2.vhd
new file mode 100755
index 0000000..c1f0716
--- /dev/null
+++ b/gof/tb_memory2.vhd
@@ -0,0 +1,247 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 23:41:51 11/15/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/gof/tb_memory2.vhd
+-- Project Name: gof
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: memory1
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+use WORK.p_memory_content.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_memory2 IS
+END tb_memory2;
+
+ARCHITECTURE behavior OF tb_memory2 IS
+
+ COMPONENT memory1
+ PORT(
+ i_clk : in std_logic;
+ i_reset : in std_logic;
+ i_copy_content : in std_logic;
+ o_copy_content : out std_logic;
+ i_enable_byte : in std_logic;
+ i_enable_bit : in std_logic;
+ i_write_byte : in std_logic;
+ i_write_bit : in std_logic;
+ i_row : in std_logic_vector(ROWS_BITS-1 downto 0);
+ i_col_pixel : in std_logic_vector(COLS_PIXEL_BITS-1 downto 0);
+ i_col_block : in std_logic_vector(COLS_BLOCK_BITS-1 downto 0);
+ i_byte : in std_logic_vector(BYTE_BITS-1 downto 0);
+ i_bit : in std_logic;
+ o_byte : out std_logic_vector(BYTE_BITS-1 downto 0);
+ o_bit : out std_logic);
+ END COMPONENT;
+
+ --Inputs
+ signal i_clk : std_logic := '0';
+ signal i_reset : std_logic := '0';
+ signal i_enable_byte : std_logic := '0';
+ signal i_enable_bit : std_logic := '0';
+ signal i_write_byte : std_logic := '0';
+ signal i_write_bit : std_logic := '0';
+ signal i_row : std_logic_vector(ROWS_BITS-1 downto 0) := (others => '0');
+ signal i_col_pixel : std_logic_vector(COLS_PIXEL_BITS-1 downto 0) := (others => '0');
+ signal i_col_block : std_logic_vector(COLS_BLOCK_BITS-1 downto 0) := (others => '0');
+ signal i_byte : std_logic_vector(BYTE_BITS-1 downto 0) := (others => '0');
+ signal i_bit : std_logic := '0';
+ signal i_copy_content : std_logic := '0';
+ signal o_copy_content : std_logic;
+
+ --Outputs
+ signal o_bit : std_logic;
+ signal o_byte : std_logic_vector(BYTE_BITS-1 downto 0);
+
+ -- Clock period definitions
+ constant i_clk_period : time := 20 ns;
+
+ type states is (
+ ccstart,ccstop,idle,
+ st1,st2,st3,st4,st5,st5a,
+ st6,st7,st8,st9,st10,
+ st11,st12,st13,st14,st15,st16,
+ stop
+ );
+ signal state : states := ccstart;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: memory1 PORT MAP (
+ i_clk => i_clk,
+ i_reset => i_reset,
+ i_copy_content => i_copy_content,
+ o_copy_content => o_copy_content,
+ i_enable_byte => i_enable_byte,
+ i_enable_bit => i_enable_bit,
+ i_write_byte => i_write_byte,
+ i_write_bit => i_write_bit,
+ i_row => i_row,
+ i_col_pixel => i_col_pixel,
+ i_col_block => i_col_block,
+ i_byte => i_byte,
+ i_bit => i_bit,
+ o_byte => o_byte,
+ o_bit => o_bit
+ );
+
+ -- Clock process definitions
+ i_clk_process :process
+ begin
+ i_clk <= '0';
+ wait for i_clk_period/2;
+ i_clk <= '1';
+ wait for i_clk_period/2;
+ end process;
+
+ i_reset <= '1','0' after i_clk_period;
+
+ -- Stimulus process
+ p0 : process (i_clk) is
+ variable i : integer range 0 to ROWS-1 := 0;
+ variable j : integer range 0 to COLS_BLOCK-1 := 0;
+ variable k : integer range 0 to COLS_PIXEL-1 := 0;
+ begin
+ if (rising_edge(i_clk)) then
+-- i_row <= (others => 'U');
+-- i_col_pixel <= (others => 'U');
+-- i_col_block <= (others => 'U');
+-- i_byte <= (others => 'U');
+ case (state) is
+ when ccstart =>
+ state <= ccstop;
+ i_copy_content <= '1';
+ when ccstop =>
+ if (o_copy_content = '1') then
+ state <= idle;
+ i_copy_content <= '0';
+ else
+ state <= ccstop;
+ i_copy_content <= '1';
+ end if;
+ when idle =>
+ state <= st1;
+ i := 0;
+ j := 0;
+ k := 0;
+ i_row <= (others => '0');
+ i_col_block <= (others => '0');
+ i_col_pixel <= (others => '0');
+ when st1 =>
+ state <= st2;
+ i_enable_byte <= '1';
+ i_write_byte <= '1';
+ when st2 =>
+ state <= st3;
+ i_row <= std_logic_vector(to_unsigned(i,i_row'length));
+ i_col_block <= std_logic_vector(to_unsigned(k,i_col_block'length));
+ i_byte <= memory_content(i)((k*BYTE_BITS+(BYTE_BITS-1)) downto ((k*BYTE_BITS)+0));
+ when st3 =>
+ if (k = COLS_BLOCK - 1) then
+ state <= st4;
+ k := 0;
+ else
+ state <= st2;
+ k := k + 1;
+ end if;
+ when st4 =>
+ if (i = ROWS - 1) then
+ state <= st5;
+ i := 0;
+ else
+ state <= st2;
+ i := i + 1;
+ end if;
+ when st5 =>
+ state <= st5a;
+ i_enable_byte <= '0';
+ i_write_byte <= '0';
+ when st5a =>
+ state <= st6;
+ i := 0;
+ j := 0;
+ k := 0;
+ when st6 =>
+ state <= st7;
+ i_enable_byte <= '1';
+ i_write_byte <= '0';
+ when st7 =>
+ state <= st8;
+ i_row <= std_logic_vector(to_unsigned(i,i_row'length));
+ i_col_block <= std_logic_vector(to_unsigned(k,i_col_block'length));
+ when st8 =>
+ if (k = COLS_BLOCK - 1) then
+ state <= st9;
+ k := 0;
+ else
+ state <= st7;
+ k := k + 1;
+ end if;
+ when st9 =>
+ if (i = ROWS - 1) then
+ state <= st10;
+ i := 0;
+ else
+ state <= st7;
+ i := i + 1;
+ end if;
+ when st10 =>
+ state <= st11;
+ i_enable_byte <= '0';
+ i_write_byte <= '0';
+ when st11 =>
+ state <= st12;
+ i_enable_bit <= '1';
+ i_write_bit <= '1';
+ when st12 =>
+ state <= st13;
+ i_row <= std_logic_vector(to_unsigned(12,i_row'length));
+ i_col_pixel <= std_logic_vector(to_unsigned(12,i_col_pixel'length));
+ i_bit <= '1';
+ when st13 =>
+ state <= st14;
+ i_enable_bit <= '0';
+ i_write_bit <= '0';
+ when st14 =>
+ state <= st15;
+ i_enable_bit <= '1';
+ i_write_bit <= '0';
+ when st15 =>
+ state <= st16;
+ i_row <= std_logic_vector(to_unsigned(12,i_row'length));
+ i_col_pixel <= std_logic_vector(to_unsigned(12,i_col_pixel'length));
+ when st16 =>
+ state <= stop;
+ i_enable_bit <= '0';
+ i_write_bit <= '0';
+ when stop =>
+ state <= stop;
+ when others => null;
+ end case;
+ end if;
+ end process p0;
+END;
diff --git a/gof/tb_memory2.wcfg b/gof/tb_memory2.wcfg
new file mode 100755
index 0000000..d24aa8a
--- /dev/null
+++ b/gof/tb_memory2.wcfg
@@ -0,0 +1,79 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ports
+ label
+
+ i_clk
+ i_clk
+
+
+ i_enable
+ i_enable
+
+
+ blocks
+ label
+
+ i_row[6:0]
+ i_row[6:0]
+ UNSIGNEDDECRADIX
+
+
+ i_col_block[1:0]
+ i_col_block[1:0]
+ UNSIGNEDDECRADIX
+
+
+ o_byte[7:0]
+ o_byte[7:0]
+
+
+
+
+ notused
+ label
+
+ i_write
+ i_write
+
+
+ i_byte[7:0]
+ i_byte[7:0]
+
+
+ pixels
+ label
+
+ i_row[6:0]
+ i_row[6:0]
+ UNSIGNEDDECRADIX
+
+
+ i_col_pixel[4:0]
+ i_col_pixel[4:0]
+ UNSIGNEDDECRADIX
+
+
+ o_bit
+ o_bit
+
+
+
+
diff --git a/gof/tb_memorymodule.vhd b/gof/tb_memorymodule.vhd
new file mode 100755
index 0000000..9cd78be
--- /dev/null
+++ b/gof/tb_memorymodule.vhd
@@ -0,0 +1,150 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:35:05 11/30/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/memorymodule/tb_memorymodule.vhd
+-- Project Name: memorymodule
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: memorymodule
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE WORK.p_globals.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_memorymodule IS
+END tb_memorymodule;
+
+ARCHITECTURE behavior OF tb_memorymodule IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT memorymodule
+ PORT(
+ i_clock : IN std_logic;
+ i_enable : IN std_logic;
+ i_write : IN std_logic;
+ i_read : IN std_logic;
+ i_MemAdr : IN std_logic_vector(23 downto 0);
+ i_MemDB : IN std_logic_vector(15 downto 0);
+ o_MemDB : OUT std_logic_vector(15 downto 0);
+ io_MemOE : OUT std_logic;
+ io_MemWR : OUT std_logic;
+ io_RamAdv : OUT std_logic;
+ io_RamCS : OUT std_logic;
+ io_RamLB : OUT std_logic;
+ io_RamUB : OUT std_logic;
+ io_MemAdr : OUT std_logic_vector(23 downto 0);
+ io_MemDB : INOUT std_logic_vector(15 downto 0)
+ );
+ END COMPONENT;
+
+ --Inputs
+ signal i_clock : std_logic := '0';
+ signal i_enable : std_logic := '0';
+ signal i_write : std_logic := '0';
+ signal i_read : std_logic := '0';
+ signal i_MemAdr : std_logic_vector(23 downto 0) := (others => '0');
+ signal i_MemDB : std_logic_vector(15 downto 0) := (others => '0');
+
+ --BiDirs
+ signal io_MemDB : std_logic_vector(15 downto 0);
+
+ --Outputs
+ signal o_MemDB : std_logic_vector(15 downto 0);
+ signal io_MemOE : std_logic;
+ signal io_MemWR : std_logic;
+ signal io_RamAdv : std_logic;
+ signal io_RamCS : std_logic;
+ signal io_RamLB : std_logic;
+ signal io_RamUB : std_logic;
+ signal io_MemAdr : std_logic_vector(23 downto 0);
+
+ -- Clock period definitions
+ constant i_clock_period : time := (1_000_000_000 / G_BOARD_CLOCK) * 1 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: memorymodule PORT MAP (
+ i_clock => i_clock,
+ i_enable => i_enable,
+ i_write => i_write,
+ i_read => i_read,
+ i_MemAdr => i_MemAdr,
+ i_MemDB => i_MemDB,
+ o_MemDB => o_MemDB,
+ io_MemOE => io_MemOE,
+ io_MemWR => io_MemWR,
+ io_RamAdv => io_RamAdv,
+ io_RamCS => io_RamCS,
+ io_RamLB => io_RamLB,
+ io_RamUB => io_RamUB,
+ io_MemAdr => io_MemAdr,
+ io_MemDB => io_MemDB
+ );
+
+ -- Clock process definitions
+ i_clock_process :process
+ begin
+ i_clock <= '0';
+ wait for i_clock_period/2;
+ i_clock <= '1';
+ wait for i_clock_period/2;
+ end process;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+ -- insert stimulus here
+ -- write
+ wait for i_clock_period*10;
+ i_enable <= '1';
+ wait for i_clock_period;
+ i_write <= '1';
+ wait for i_clock_period;
+ i_MemAdr <= x"222222";
+ i_MemDB <= x"1234";
+ wait for i_clock_period;
+ i_write <= '0';
+ wait for i_clock_period;
+ i_enable <= '0';
+ -- read
+ wait for i_clock_period*10;
+ i_enable <= '1';
+ wait for i_clock_period;
+ i_read <= '1';
+ wait for i_clock_period;
+ i_MemAdr <= x"222222";
+ --i_MemDB <= x"1234";
+ wait for i_clock_period;
+ i_read <= '0';
+ wait for i_clock_period;
+ i_enable <= '0';
+ wait;
+ end process;
+
+END;
diff --git a/gof/tb_my_spi.vhd b/gof/tb_my_spi.vhd
new file mode 100755
index 0000000..1c888ad
--- /dev/null
+++ b/gof/tb_my_spi.vhd
@@ -0,0 +1,132 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:39:23 06/13/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/st7735r/tb_my_spi.vhd
+-- Project Name: st7735r
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: my_spi
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE WORK.p_package.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_my_spi IS
+END tb_my_spi;
+
+ARCHITECTURE behavior OF tb_my_spi IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT my_spi
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+i_enable : IN std_logic;
+i_data_byte : IN std_logic_vector(7 downto 0);
+o_cs : OUT std_logic;
+o_do : OUT std_logic;
+o_ck : INOUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+signal i_enable : std_logic := '0';
+signal i_data_byte : std_logic_vector(7 downto 0) := (others => '0');
+
+--Outputs
+signal o_cs : std_logic;
+signal o_do : std_logic;
+signal o_ck : std_logic;
+
+-- Clock period definitions
+constant i_clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: my_spi PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+i_enable => i_enable,
+i_data_byte => i_data_byte,
+o_cs => o_cs,
+o_do => o_do,
+o_ck => o_ck
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+
+i_reset <= '1';
+wait for i_clock_period*C_CLOCK_COUNTER;
+i_reset <= '0';
+wait for i_clock_period;
+
+-- insert stimulus here
+
+i_enable <= '1';
+i_data_byte <= x"AA";
+--wait for i_clock_period*(BYTE_SIZE+1)*C_CLOCK_COUNTER;
+wait for i_clock_period*BYTE_SIZE*C_CLOCK_COUNTER;
+i_enable <= '0';
+wait for i_clock_period*C_CLOCK_COUNTER*10;
+
+i_enable <= '1';
+i_data_byte <= x"55";
+--wait for i_clock_period*(BYTE_SIZE+1)*C_CLOCK_COUNTER;
+wait for i_clock_period*BYTE_SIZE*C_CLOCK_COUNTER;
+i_enable <= '0';
+wait for i_clock_period*C_CLOCK_COUNTER*10;
+
+i_enable <= '1';
+i_data_byte <= x"00";
+--wait for i_clock_period*(BYTE_SIZE+1)*C_CLOCK_COUNTER;
+wait for i_clock_period*BYTE_SIZE*C_CLOCK_COUNTER;
+i_enable <= '0';
+wait for i_clock_period*C_CLOCK_COUNTER*10;
+
+i_enable <= '1';
+i_data_byte <= x"FF";
+--wait for i_clock_period*(BYTE_SIZE+1)*C_CLOCK_COUNTER;
+wait for i_clock_period*BYTE_SIZE*C_CLOCK_COUNTER;
+i_enable <= '0';
+wait for i_clock_period*C_CLOCK_COUNTER*10;
+
+wait;
+end process;
+
+END;
diff --git a/gof/tb_oled_display.vhd b/gof/tb_oled_display.vhd
new file mode 100755
index 0000000..7d9e352
--- /dev/null
+++ b/gof/tb_oled_display.vhd
@@ -0,0 +1,163 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:51:58 08/28/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/i2c_test_1/tb_test_oled.vhd
+-- Project Name: i2c_test_1
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: test_oled
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_oled_display IS
+END tb_oled_display;
+
+ARCHITECTURE behavior OF tb_oled_display IS
+
+ constant INPUT_CLOCK : integer := 50_000_000;
+ constant BUS_CLOCK : integer := 100_000;
+ constant OLED_WIDTH : integer := 128;
+ constant OLED_HEIGHT : integer := 32;
+ constant OLED_W_BITS : integer := 7;
+ constant OLED_H_BITS : integer := 5;
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT oled_display
+ GENERIC(
+ GLOBAL_CLK : integer;
+ I2C_CLK : integer;
+ WIDTH : integer;
+ HEIGHT : integer;
+ W_BITS : integer;
+ H_BITS : integer);
+ PORT(
+ i_clk : IN std_logic;
+ i_rst : IN std_logic;
+ i_x : in std_logic_vector(W_BITS-1 downto 0);
+ i_y : in std_logic_vector(H_BITS-1 downto 0);
+ i_all_pixels : in std_logic;
+ io_sda : INOUT std_logic;
+ io_scl : INOUT std_logic
+ );
+ END COMPONENT;
+
+ --Inputs
+ signal clk : std_logic := '0';
+ signal rst : std_logic := '0';
+ signal a : std_logic_vector(OLED_W_BITS-1 downto 0) := (others => '0');
+ signal b : std_logic_vector(OLED_H_BITS-1 downto 0) := (others => '0');
+ signal all_pixels : std_logic := '0';
+
+ --BiDirs
+ signal sda : std_logic;
+ signal scl : std_logic;
+
+ -- Clock period definitions
+ constant clk_period : time := 20 ns;
+
+ constant NV : integer := 10;
+ type t_coord_x is array(0 to NV-1) of std_logic_vector(7 downto 0);
+ type t_coord_y is array(0 to NV-1) of std_logic_vector(7 downto 0);
+ signal x_coord : t_coord_x := (x"79",x"78",x"66",x"55",x"44",x"33",x"22",x"11",x"05",x"00");
+ signal y_coord : t_coord_y := (x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"01");
+-- signal x_coord : t_coord_x := (x"00",x"7F",x"00",x"7F");
+-- signal y_coord : t_coord_y := (x"00",x"00",x"1F",x"1F");
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: oled_display
+ GENERIC MAP (
+ GLOBAL_CLK => INPUT_CLOCK,
+ I2C_CLK => BUS_CLOCK,
+ WIDTH => OLED_WIDTH,
+ HEIGHT => OLED_HEIGHT,
+ W_BITS => OLED_W_BITS,
+ H_BITS => OLED_H_BITS)
+ PORT MAP (
+ i_clk => clk,
+ i_rst => rst,
+ i_x => a,
+ i_y => b,
+ i_all_pixels => all_pixels,
+ io_sda => sda,
+ io_scl => scl
+ );
+
+ -- Clock process definitions
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ wait for 20 ns;
+ rst <= '1';
+ wait for 20 ns;
+ rst <= '0';
+ wait for 20 ns;
+ all_pixels <= '0';
+
+ wait for 50 ms;
+ a <= x_coord(0)(OLED_W_BITS-1 downto 0);
+ b <= y_coord(0)(OLED_H_BITS-1 downto 0);
+ wait for 1.05 ms;
+ a <= x_coord(1)(OLED_W_BITS-1 downto 0);
+ b <= y_coord(1)(OLED_H_BITS-1 downto 0);
+ wait for 1.05 ms;
+ a <= x_coord(2)(OLED_W_BITS-1 downto 0);
+ b <= y_coord(2)(OLED_H_BITS-1 downto 0);
+ wait for 1.05 ms;
+ a <= x_coord(3)(OLED_W_BITS-1 downto 0);
+ b <= y_coord(3)(OLED_H_BITS-1 downto 0);
+ wait for 1.05 ms;
+ a <= x_coord(4)(OLED_W_BITS-1 downto 0);
+ b <= y_coord(4)(OLED_H_BITS-1 downto 0);
+ wait for 1.05 ms;
+ a <= x_coord(5)(OLED_W_BITS-1 downto 0);
+ b <= y_coord(5)(OLED_H_BITS-1 downto 0);
+ wait for 1.05 ms;
+ a <= x_coord(6)(OLED_W_BITS-1 downto 0);
+ b <= y_coord(6)(OLED_H_BITS-1 downto 0);
+ wait for 1.05 ms;
+ a <= x_coord(7)(OLED_W_BITS-1 downto 0);
+ b <= y_coord(7)(OLED_H_BITS-1 downto 0);
+ wait for 1.05 ms;
+ a <= x_coord(8)(OLED_W_BITS-1 downto 0);
+ b <= y_coord(8)(OLED_H_BITS-1 downto 0);
+ wait for 1.05 ms;
+ a <= x_coord(9)(OLED_W_BITS-1 downto 0);
+ b <= y_coord(9)(OLED_H_BITS-1 downto 0);
+
+ all_pixels <= '1';
+ end process;
+
+END;
diff --git a/gof/top.vhd b/gof/top.vhd
new file mode 100755
index 0000000..a789c62
--- /dev/null
+++ b/gof/top.vhd
@@ -0,0 +1,1253 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:11:54 09/04/2020
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_memory_content.ALL;
+use WORK.p_constants1.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+-- XXX !!!!!!!!!
+-- XXX NEEDS FIX
+-- XXX NEEDS FIX
+-- XXX NEEDS FIX
+-- XXX NEEDS FIX
+-- XXX NEEDS FIX
+-- XXX NEEDS FIX
+-- XXX NEEDS FIX
+-- XXX NEEDS FIX
+-- XXX NEEDS FIX
+-- XXX NEEDS FIX
+-- XXX NEEDS FIX
+-- XXX NEEDS FIX
+-- XXX NEEDS FIX
+-- XXX NEEDS FIX
+-- XXX NEEDS FIX
+-- XXX !!!!!!!!!
+
+entity top is
+generic(
+INPUT_CLOCK : integer := G_BOARD_CLOCK;
+BUS_CLOCK : integer := G_BUS_CLOCK; -- increase for speed i2c
+DIVIDER_CLOCK : integer := G_ClockDivider;
+g_lcd_clock_divider : integer := G_LCDClockDivider
+);
+port(
+signal clk : in std_logic;
+signal btn_1 : in std_logic;
+signal btn_2 : in std_logic;
+signal btn_3 : in std_logic;
+signal sda,scl : inout std_logic;
+signal io_MemOE : inout std_logic;
+signal io_MemWR : inout std_logic;
+signal io_RamAdv : inout std_logic;
+signal io_RamCS : inout std_logic;
+signal io_RamCRE : inout std_logic;
+signal io_RamLB : inout std_logic;
+signal io_RamUB : inout std_logic;
+signal io_RamWait : inout std_logic;
+signal io_RamClk : inout std_logic;
+signal io_MemAdr : inout MemoryAddressALL;
+signal io_MemDB : inout MemoryDataByte;
+signal seg : inout std_logic_vector(6 downto 0);
+signal an : inout std_logic_vector(3 downto 0);
+signal io_FlashCS : out std_logic
+);
+end top;
+
+architecture Behavioral of top is
+
+component lcd_display is
+Generic (
+ LCDClockDivider : integer := g_lcd_clock_divider
+);
+Port (
+ i_clock : in std_logic;
+ i_LCDChar : LCDHex;
+ o_anode : out std_logic_vector(G_LCDAnode-1 downto 0);
+ o_segment : out std_logic_vector(G_LCDSegment-1 downto 0)
+);
+end component lcd_display;
+--for all : lcd_display use entity WORK.lcd_display(Behavioral);
+
+component oled_display is
+generic(
+GLOBAL_CLK : integer;
+I2C_CLK : integer;
+WIDTH_O : integer;
+HEIGHT_O : integer;
+W_BITS : integer;
+H_BITS : integer;
+BYTE_SIZE : integer);
+port(
+signal i_clk : in std_logic;
+signal i_rst : in std_logic;
+signal i_clear : in std_logic;
+signal i_draw : in std_logic;
+signal i_x : in std_logic_vector(W_BITS-1 downto 0);
+signal i_y : in std_logic_vector(H_BITS-1 downto 0);
+signal i_byte : in std_logic_vector(BYTE_SIZE-1 downto 0);
+signal i_all_pixels : in std_logic;
+signal o_busy : out std_logic;
+signal o_display_initialize : inout std_logic;
+signal io_sda,io_scl : inout std_logic);
+end component oled_display;
+
+component BUFG
+port (I : in std_logic;
+O : out std_logic);
+end component;
+
+component clock_divider is
+Port(
+i_clk : in STD_LOGIC;
+i_board_clock : in INTEGER;
+i_divider : in INTEGER;
+o_clk : out STD_LOGIC
+);
+end component clock_divider;
+
+component memorymodule is
+Port (
+i_clock : in std_logic;
+i_enable : in std_logic;
+i_write : in std_logic;
+i_read : in std_logic;
+o_busy : out std_logic;
+i_MemAdr : in MemoryAddressALL;
+i_MemDB : in MemoryDataByte;
+o_MemDB : out MemoryDataByte;
+io_MemOE : out std_logic;
+io_MemWR : out std_logic;
+io_RamAdv : out std_logic;
+io_RamCS : out std_logic;
+io_RamLB : out std_logic;
+io_RamUB : out std_logic;
+io_RamCRE : out std_logic;
+io_RamClk : out std_logic;
+io_MemAdr : out MemoryAddressALL;
+io_MemDB : inout MemoryDataByte
+);
+end component memorymodule;
+--for all : memorymodule use entity WORK.memorymodule(Behavioral);
+
+--component memory1 is
+--Port (
+--i_clk : in std_logic;
+--i_reset : in std_logic;
+--i_enable_byte : in std_logic;
+--i_enable_bit : in std_logic;
+--i_write_byte : in std_logic;
+--i_write_bit : in std_logic;
+--i_row : in std_logic_vector(ROWS_BITS-1 downto 0);
+--i_col_pixel : in std_logic_vector(COLS_PIXEL_BITS-1 downto 0);
+--i_col_block : in std_logic_vector(COLS_BLOCK_BITS-1 downto 0);
+--i_byte : in std_logic_vector(BYTE_BITS-1 downto 0);
+--i_bit : in std_logic;
+--o_byte : out std_logic_vector(BYTE_BITS-1 downto 0);
+--o_bit : out std_logic);
+--end component memory1;
+--for all : memory1 use entity WORK.memory1(Behavioral);
+
+component RAMB16_S4
+generic (
+WRITE_MODE : string := "NO_CHANGE" ; -- WRITE_FIRST(default)/ READ_FIRST/NO_CHANGE
+INIT : bit_vector(3 downto 0) := X"0";
+SRVAL : bit_vector(3 downto 0) := X"0"
+);
+port (
+DI : in std_logic_vector (3 downto 0);
+ADDR : in std_logic_vector (11 downto 0);
+EN : in STD_LOGIC;
+WE : in STD_LOGIC;
+SSR : in STD_LOGIC;
+CLK : in STD_LOGIC;
+DO : out std_logic_vector (3 downto 0)
+);
+end component;
+
+signal row : std_logic_vector(ROWS_BITS-1 downto 0) := (others => '0');
+signal col_pixel : std_logic_vector(COLS_PIXEL_BITS-1 downto 0) := (others => '0');
+signal col_block : std_logic_vector(COLS_BLOCK_BITS-1 downto 0) := (others => '0');
+signal rst : std_logic;
+signal all_pixels : std_logic;
+signal clk_1s : std_logic;
+signal display_byte : std_logic_vector(BYTE_BITS-1 downto 0);
+signal display_initialize : std_logic;
+signal o_bit : std_logic;
+signal i_reset : std_logic;
+signal draw : std_logic;
+
+signal i_mem_e_byte : std_logic;
+signal i_mem_e_bit : std_logic;
+signal i_mem_write_bit : std_logic;
+signal i_bit : std_logic;
+
+signal CLK_BUFG : std_logic;
+
+signal DATA_IN : std_logic_vector(3 downto 0);
+signal ADDRESS : std_logic_vector(11 downto 0);
+signal ENABLE : std_logic;
+signal WRITE_EN : std_logic;
+signal DATA_OUT : std_logic_vector(3 downto 0);
+
+type state is (
+set_cd_memorycopy,enable_memory_module,enable_write_fh,copy_first_halfword,disable_write_fh,memory_wait_fh,enable_write_sh,copy_second_halfword,disable_write_sh,memory_wait_sh,disable_memory_module,check_ranges_write,
+
+idle,
+display_is_initialize,
+
+enable_memory_module_read_fh,enable_read_memory_fh,read_fh,store_fh,disable_read_memory_fh,disable_memory_module_read_fh,
+send_fh1,send_fh1_waitdisplay,send_fh2,send_fh2_waitdisplay,
+enable_memory_module_read_sh,enable_read_memory_sh,read_sh,store_sh,disable_read_memory_sh,disable_memory_module_read_sh,
+send_sh1,send_sh1_waitdisplay,send_sh2,send_sh2_waitdisplay,
+wait_two_reads,
+check_ranges_read,
+asdf,
+memory_enable_byte,
+waitone,
+update_row,
+update_col,
+set_cd_calculate,
+memory_disable_byte,
+reset_counters_1,
+check_coordinations,
+reset_count_alive,
+memory_enable_bit,
+check_cell_alive_wm,
+c1_mdr,c2_mdr,c3_mdr,c4_mdr,c5_mdr,c6_mdr,c7_mdr,c8_mdr,
+c1_me,c1_mr,c1_md,c2_me,c2_mr,c2_md,c3_me,c3_mr,c3_md,c4_me,c4_mr,c4_md,c5_me,c5_mr,c5_md,c6_me,c6_mr,c6_md,c7_me,c7_mr,c7_md,c8_me,c8_mr,c8_md,
+set_c1,c1,set_c2,c2,set_c3,c3,set_c4,c4,set_c5,c5,set_c6,c6,set_c7,c7,set_c8,c8,
+waitfor,
+memory_disable_bit,
+store_count_alive_me,store_count_alive_we,store_count_alive_sa,store_count_alive,store_count_alive_wd,store_count_alive_md,update_row1,
+memory_sa1,memory_disable_read1,memory_disable_bit1,get_alive,get_alive1,enable_m2,enable_write_to_memory,check_cell_alive_1,check_cell_alive_1a,check_cell_alive_2,check_cell_alive_3,aa,aaa,aaaa,aaaaa,disable_write_to_memory,vvv,
+update_col1,
+store_count_alive_wm,memory_disable_read1_wm,vvv_wm,
+memory_enable_read1,
+reset_counters1,
+memory_enable_bit1,
+set_coords_to_write,
+write_count_alive,
+update_row2,
+update_col2,
+disable_memory,
+stop
+);
+signal cstate : state;
+
+signal i_enable : std_logic;
+signal i_write : std_logic;
+signal i_read : std_logic;
+signal o_membusy : std_logic;
+signal o_disbusy : std_logic;
+signal i_MemAdr : MemoryAddressALL;
+signal i_MemDB : MemoryDataByte;
+signal o_MemDB : MemoryDataByte;
+constant W : integer := 1;
+signal waiting : integer range W-1 downto 0 := 0;
+signal ppX : std_logic_vector(ROWS_BITS-1 downto 0);
+signal ppYb : std_logic_vector(COLS_BLOCK_BITS-1 downto 0);
+signal ppYp : std_logic_vector(COLS_PIXEL_BITS-1 downto 0);
+signal ppXm1 : std_logic_vector(ROWS_BITS-1 downto 0);
+signal ppXp1 : std_logic_vector(ROWS_BITS-1 downto 0);
+signal ppYm1 : std_logic_vector(COLS_PIXEL_BITS-1 downto 0);
+signal ppYp1 : std_logic_vector(COLS_PIXEL_BITS-1 downto 0);
+signal oppX : std_logic_vector(ROWS_BITS-1 downto 0);
+signal oppY : std_logic_vector(COLS_PIXEL_BITS-1 downto 0);
+
+signal countAlive : std_logic_vector(3 downto 0);
+--signal slivearray : std_logic_vector(2 downto 0);
+signal CellAlive : std_logic;
+--signal LiveArray : LiveArrayType;
+signal CD : integer := DIVIDER_CLOCK; -- XXX
+signal CD_DISPLAY : integer := DIVIDER_CLOCK*1; -- XXX
+signal CD_CALCULATE : integer := DIVIDER_CLOCK*10000; -- XXX
+signal CD_COPYMEMORY : integer := DIVIDER_CLOCK; -- XXX
+
+function To_Std_Logic(x_vot : BOOLEAN) return std_ulogic is
+begin
+ if x_vot then
+ return('1');
+ else
+ return('0');
+ end if;
+end function To_Std_Logic;
+
+signal LCDChar : LCDHex;
+
+signal o_Mem1 : MemoryDataByte;
+signal o_Mem2 : MemoryDataByte;
+
+signal MemOE : std_logic;
+signal MemWR : std_logic;
+signal RamAdv : std_logic;
+signal RamCS : std_logic;
+signal RamLB : std_logic;
+signal RamUB : std_logic;
+signal RamCRE : std_logic;
+signal RamClk : std_logic;
+signal MemAdr : MemoryAddressALL;
+signal MemDB : MemoryDataByte;
+
+constant address1 : integer := 8888;
+constant address2 : integer := 9999;
+constant startAddressValue : integer := address1;
+signal startAddress : MemoryAddressALL := std_logic_vector(to_unsigned(startAddressValue,G_MemoryAddress));
+signal startAddress0 : MemoryAddressALL;
+signal startAddress1 : MemoryAddressALL;
+signal stppY : std_logic_vector(31 downto 0);
+
+begin
+
+io_FlashCS <= '1'; -- flash is always off
+
+io_MemOE <= MemOE;
+io_MemWR <= MemWR;
+io_RamAdv <= RamAdv;
+io_RamCS <= RamCS;
+io_RamLB <= RamLB;
+io_RamUB <= RamUB;
+io_RamCRE <= RamCRE;
+io_RamClk <= RamClk;
+io_MemAdr <= MemAdr;
+io_MemDB <= MemDB;
+
+i_reset <= btn_1;
+
+pa : process (clk_1s) is
+ variable flag : boolean := false;
+ variable counter : integer := 0;
+begin
+ if (rising_edge(clk_1s)) then
+ if (flag) then
+ LCDChar <= (MemDB(12 to 15),MemDB(8 to 11),MemDB(4 to 7),MemDB(0 to 3));
+ else
+ LCDChar <= (MemAdr(12 to 15),MemAdr(8 to 11),MemAdr(4 to 7),MemAdr(0 to 3));
+ end if;
+ if (counter < 1) then
+ counter := counter + 1;
+ else
+ flag := not flag;
+ counter := 0;
+ end if;
+ end if;
+end process pa;
+
+c_lcd_display : lcd_display
+Port Map (
+ i_clock => clk,
+ i_LCDChar => LCDChar,
+ o_anode => an,
+ o_segment => seg
+);
+
+U_BUFG: BUFG
+port map (
+I => clk,
+O => CLK_BUFG
+);
+
+i_reset <= btn_1;
+
+U_RAMB16_S4: RAMB16_S4
+port map (
+DI => DATA_IN,
+ADDR => ADDRESS,
+EN => ENABLE,
+WE => WRITE_EN,
+SSR => i_reset,
+CLK => CLK_BUFG,
+DO => DATA_OUT
+);
+
+clk_div : clock_divider
+port map (
+ i_clk => CLK_BUFG,
+ i_board_clock => INPUT_CLOCK,
+ i_divider => CD,
+ o_clk => clk_1s
+);
+
+c0 : oled_display
+generic map (
+ GLOBAL_CLK => INPUT_CLOCK,
+ I2C_CLK => BUS_CLOCK,
+ WIDTH_O => ROWS,
+ HEIGHT_O => COLS_BLOCK,
+ W_BITS => ROWS_BITS,
+ H_BITS => COLS_BLOCK_BITS,
+ BYTE_SIZE => BYTE_BITS)
+port map (
+ i_clk => CLK_BUFG,
+ i_rst => i_reset,
+ i_clear => btn_2,
+ i_draw => draw,
+ i_x => row,
+ i_y => col_block,
+ i_byte => display_byte,
+ i_all_pixels => all_pixels,
+ o_busy => o_disbusy,
+ o_display_initialize => display_initialize,
+ io_sda => sda,
+ io_scl => scl
+);
+
+mm : memorymodule PORT MAP (
+ i_clock => clk_1s,
+ i_enable => i_enable,
+ i_write => i_write,
+ i_read => i_read,
+ o_busy => o_membusy,
+ i_MemAdr => i_MemAdr,
+ i_MemDB => i_MemDB,
+ o_MemDB => o_MemDB,
+ io_MemOE => MemOE,
+ io_MemWR => MemWR,
+ io_RamAdv => RamAdv,
+ io_RamCS => RamCS,
+ io_RamLB => RamLB,
+ io_RamUB => RamUB,
+ io_RamCRE => RamCRE,
+ io_RamClk => RamClk,
+ io_MemAdr => MemAdr,
+ io_MemDB => MemDB
+);
+
+--m1 : memory1
+--port map (
+-- i_clk => CLK_BUFG,
+-- i_reset => i_reset,
+-- i_enable_byte => i_mem_e_byte,
+-- i_enable_bit => i_mem_e_bit,
+-- i_write_byte => '0',
+-- i_write_bit => i_mem_write_bit,
+-- i_row => row,
+-- i_col_pixel => col_pixel,
+-- i_col_block => col_block,
+-- i_byte => (others => 'X'),
+-- i_bit => i_bit,
+-- o_byte => display_byte,
+-- o_bit => o_bit
+--);
+
+gof_logic : process (clk_1s,i_reset) is
+ constant W : integer := 1;
+ variable waiting : integer range W downto 0 := W;
+-- variable waiting : integer range W-1 downto 0 := 0;
+ variable vppX : natural range 0 to ROWS-1;
+ variable vppYb : natural range 0 to COLS_BLOCK-1;
+ variable vppYp : natural range 0 to COLS_PIXEL-1;
+ variable vppXm1 : integer range -1 to ROWS-1;
+ variable vppXp1 : integer range 0 to ROWS;
+ variable vppYm1 : integer range -1 to COLS_PIXEL-1;
+ variable vppYp1 : integer range 0 to COLS_PIXEL;
+ variable vcountAlive : integer range 0 to 15;
+ variable vCellAlive,newCellAlive : boolean;
+ variable m1 : MEMORY := memory_content;
+ variable rowIndex : integer range 0 to ROWS-1;
+ variable tppY : integer;
+ variable t : MemoryDataByte;
+begin
+ if (i_reset = '1') then
+ all_pixels <= '0';
+ vppX := 0;
+ vppYb := 0;
+ vppYp := 0;
+ cstate <= set_cd_memorycopy;
+ elsif (rising_edge(clk_1s)) then
+ startAddress0 <= std_logic_vector(to_unsigned(to_integer(unsigned(startAddress))+0,G_MemoryAddress));
+ startAddress1 <= std_logic_vector(to_unsigned(to_integer(unsigned(startAddress))+1,G_MemoryAddress));
+ if (waiting > 0) then
+ waiting := waiting - 1;
+ end if;
+ case cstate is
+ ----------------------------------------------------------------------------------
+ -- copy memory content
+ when set_cd_memorycopy =>
+ cstate <= enable_memory_module;
+ CD <= CD_COPYMEMORY;
+ startAddress <= std_logic_vector(to_unsigned(startAddressValue,G_MemoryAddress));
+ rowIndex := 0;
+ draw <= '0';
+ when enable_memory_module =>
+ cstate <= enable_write_fh;
+ i_enable <= '1';
+ when enable_write_fh =>
+ cstate <= copy_first_halfword;
+ i_write <= '1';
+ when copy_first_halfword =>
+ cstate <= disable_write_fh;
+ i_MemAdr <= startAddress0(0 to G_MemoryAddress-1);
+ i_MemDB <= m1(rowIndex)(0 to 15);
+ when disable_write_fh =>
+ cstate <= memory_wait_fh;
+ i_write <= '0';
+ when memory_wait_fh =>
+ if (o_membusy = '1') then
+ cstate <= memory_wait_fh;
+ else
+ cstate <= enable_write_sh;
+ end if;
+ when enable_write_sh =>
+ cstate <= copy_second_halfword;
+ i_write <= '1';
+ when copy_second_halfword =>
+ cstate <= disable_write_sh;
+ i_MemAdr <= startAddress1(0 to G_MemoryAddress-1);
+ i_MemDB <= m1(rowIndex)(16 to 31);
+ when disable_write_sh =>
+ cstate <= memory_wait_sh;
+ i_write <= '0';
+ when memory_wait_sh =>
+ if (o_membusy = '1') then
+ cstate <= memory_wait_sh;
+ else
+ cstate <= disable_memory_module;
+ end if;
+ when disable_memory_module =>
+ cstate <= check_ranges_write;
+ i_enable <= '0';
+ when check_ranges_write =>
+ if (rowIndex < ROWS-1) then
+ cstate <= enable_memory_module;
+ startAddress <= std_logic_vector(to_unsigned(to_integer(unsigned(startAddress))+2,G_MemoryAddress));
+ rowIndex := rowIndex + 1;
+ else
+ cstate <= idle;
+ end if;
+ ----------------------------------------------------------------------------------
+ -- display content from memory
+ when idle =>
+ if (display_initialize = '1') then
+ cstate <= display_is_initialize;
+ i_MemDB <= (others=> '0');
+ else
+ cstate <= idle;
+ end if;
+ when display_is_initialize =>
+ cstate <= enable_memory_module_read_fh;
+ vppX := 0;
+ vppYb := 0;
+ vppYp := 0;
+ all_pixels <= '0';
+ startAddress <= std_logic_vector(to_unsigned(startAddressValue,G_MemoryAddress));
+ rowIndex := 0;
+ CD <= CD_DISPLAY;
+ draw <= '1';
+ when enable_memory_module_read_fh =>
+ cstate <= enable_read_memory_fh;
+ i_enable <= '1';
+ when enable_read_memory_fh =>
+ cstate <= read_fh;
+ i_read <= '1';
+ when read_fh =>
+ cstate <= store_fh;
+ i_MemAdr <= startAddress0(0 to G_MemoryAddress-1);
+ when store_fh =>
+ cstate <= disable_read_memory_fh;
+ when disable_read_memory_fh =>
+ cstate <= disable_memory_module_read_fh;
+ i_read <= '0';
+ when disable_memory_module_read_fh =>
+ cstate <= send_fh1;
+ i_enable <= '0';
+ waiting := W;
+ when wait_two_reads =>
+ if (waiting = 0) then
+ cstate <= enable_memory_module_read_sh;
+ else
+ cstate <= wait_two_reads;
+ end if;
+ when enable_memory_module_read_sh =>
+ cstate <= enable_read_memory_sh;
+ i_enable <= '1';
+ when enable_read_memory_sh =>
+ cstate <= read_sh;
+ i_read <= '1';
+ when read_sh =>
+ cstate <= store_sh;
+ i_MemAdr <= startAddress1(0 to G_MemoryAddress-1);
+ when store_sh =>
+ cstate <= disable_read_memory_sh;
+ when disable_read_memory_sh =>
+ cstate <= disable_memory_module_read_sh;
+ i_read <= '0';
+ when disable_memory_module_read_sh =>
+ cstate <= send_sh1;
+ i_enable <= '0';
+ when send_fh1 =>
+ if (o_membusy = '1') then
+ cstate <= send_fh1;
+ else
+ cstate <= send_fh1_waitdisplay;
+ row <= std_logic_vector(to_unsigned(rowIndex,ROWS_BITS));
+ col_block <= std_logic_vector(to_unsigned(0,COLS_BLOCK_BITS));
+ display_byte <= o_MemDB(8 to 15);
+ end if;
+ when send_fh1_waitdisplay =>
+ if (o_disbusy = '1') then
+ cstate <= send_fh1_waitdisplay;
+ else
+ cstate <= send_fh2;
+ end if;
+ when send_fh2 =>
+ if (o_membusy = '1') then
+ cstate <= send_fh2;
+ else
+ cstate <= send_fh2_waitdisplay;
+ row <= std_logic_vector(to_unsigned(rowIndex,ROWS_BITS));
+ col_block <= std_logic_vector(to_unsigned(1,COLS_BLOCK_BITS));
+ display_byte <= o_MemDB(0 to 7);
+ end if;
+ when send_fh2_waitdisplay =>
+ if (o_disbusy = '1') then
+ cstate <= send_fh2_waitdisplay;
+ else
+ cstate <= enable_memory_module_read_sh;
+ end if;
+ when send_sh1 =>
+ if (o_membusy = '1') then
+ cstate <= send_sh1;
+ else
+ cstate <= send_sh1_waitdisplay;
+ row <= std_logic_vector(to_unsigned(rowIndex,ROWS_BITS));
+ col_block <= std_logic_vector(to_unsigned(2,COLS_BLOCK_BITS));
+ display_byte <= o_MemDB(8 to 15);
+ end if;
+ when send_sh1_waitdisplay =>
+ if (o_disbusy = '1') then
+ cstate <= send_sh1_waitdisplay;
+ else
+ cstate <= send_sh2;
+ end if;
+ when send_sh2 =>
+ if (o_membusy = '1') then
+ cstate <= send_sh2;
+ else
+ cstate <= send_sh2_waitdisplay;
+ row <= std_logic_vector(to_unsigned(rowIndex,ROWS_BITS));
+ col_block <= std_logic_vector(to_unsigned(3,COLS_BLOCK_BITS));
+ display_byte <= o_MemDB(0 to 7);
+ end if;
+ when send_sh2_waitdisplay =>
+ if (o_disbusy = '1') then
+ cstate <= send_sh2_waitdisplay;
+ else
+ cstate <= check_ranges_read;
+ end if;
+ when check_ranges_read =>
+ if (rowIndex < ROWS-1) then
+ cstate <= enable_memory_module_read_fh;
+ startAddress <= std_logic_vector(to_unsigned(to_integer(unsigned(startAddress))+2,G_MemoryAddress));
+ rowIndex := rowIndex + 1;
+ else
+ cstate <= set_cd_calculate;
+ all_pixels <= '1';
+ end if;
+ ----------------------------------------------------------------------------------
+ -- calculate cells
+ when set_cd_calculate =>
+ cstate <= reset_counters_1;
+ CD <= CD_CALCULATE;
+ when reset_counters_1 =>
+ cstate <= check_coordinations;
+ all_pixels <= '1';
+ vppX := 0;
+ vppYb := 0;
+ vppYp := 0;
+ when check_coordinations =>
+ cstate <= memory_enable_bit;
+ vppXm1 := vppX-1;
+ if (vppXm1 < 0) then
+ vppXm1 := 0;
+ end if;
+ vppXp1 := vppX+1;
+ if (vppXp1 > ROWS-1) then
+ vppXp1 := ROWS-1;
+ end if;
+ vppYm1 := vppYp-1;
+ if (vppYm1 < 0) then
+ vppYm1 := 0;
+ end if;
+ vppYp1 := vppYp+1;
+ if (vppYp1 > COLS_PIXEL-1) then
+ vppYp1 := COLS_PIXEL-1;
+ end if;
+ when memory_enable_bit =>
+ cstate <= reset_count_alive;
+ when reset_count_alive =>
+ cstate <= c1_me;
+ vcountAlive := 0;
+ countAlive <= "0000";
+ --
+ when c1_me =>
+ cstate <= c1_mr;
+ i_enable <= '1';
+ when c1_mr =>
+ cstate <= set_c1;
+ i_read <= '1';
+ countAlive <= (others => '0');
+ when set_c1 =>
+ cstate <= c1;
+ if (vppYm1 > (COLS_PIXEL/2)-1) then
+ i_MemAdr <= std_logic_vector(to_unsigned(vppX+1,G_MemoryAddress));
+ else
+ i_MemAdr <= std_logic_vector(to_unsigned(vppX+0,G_MemoryAddress));
+ end if;
+ when c1 =>
+ cstate <= c1_mdr;
+ if (vppYp /= 0) then
+ if (vppYm1 > (COLS_PIXEL/2)-1) then
+ tppY := (COLS_PIXEL/2)-vppYm1;
+ if(tppY < 0) then
+ tppY := -tppY;
+ end if;
+ else
+ tppY := vppYm1;
+ end if;
+ if (o_MemDB(tppY) = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+ countAlive <= std_logic_vector(to_unsigned(vcountALive,4));
+ end if;
+ when c1_mdr =>
+ if (o_membusy = '1') then
+ cstate <= c1_mdr;
+ else
+ cstate <= c1_md;
+ i_read <= '0';
+ end if;
+ when c1_md =>
+ cstate <= c2_me;
+ i_enable <= '0';
+ --
+ when c2_me =>
+ cstate <= c2_mr;
+ i_enable <= '1';
+ when c2_mr =>
+ cstate <= set_c2;
+ i_read <= '1';
+ when set_c2 =>
+ cstate <= c2;
+ if (vppYp1 > (COLS_PIXEL/2)-1) then
+ i_MemAdr <= std_logic_vector(to_unsigned(vppX+1,G_MemoryAddress));
+ else
+ i_MemAdr <= std_logic_vector(to_unsigned(vppX+0,G_MemoryAddress));
+ end if;
+ when c2 =>
+ cstate <= c2_mdr;
+ if (vppYp /= COLS_PIXEL-1) then
+ if (vppYp1 > (COLS_PIXEL/2)-1) then
+ tppY := (COLS_PIXEL/2)-vppYp1;
+ if (tppY < 0) then
+ tppY := -tppY;
+ end if;
+ else
+ tppY := vppYp1;
+ end if;
+ if (o_MemDB(tppY) = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+ countAlive <= std_logic_vector(to_unsigned(vcountALive,4));
+ end if;
+ when c2_mdr =>
+ if (o_membusy = '1') then
+ cstate <= c2_mdr;
+ else
+ cstate <= c2_md;
+ i_read <= '0';
+ end if;
+ when c2_md =>
+ cstate <= c3_me;
+ i_enable <= '0';
+ --
+ when c3_me =>
+ cstate <= c3_mr;
+ i_enable <= '1';
+ when c3_mr =>
+ cstate <= set_c3;
+ i_read <= '1';
+ when set_c3 =>
+ cstate <= c3;
+ if (vppYp > (COLS_PIXEL/2)-1) then
+ i_MemAdr <= std_logic_vector(to_unsigned(vppXp1+1,G_MemoryAddress));
+ else
+ i_MemAdr <= std_logic_vector(to_unsigned(vppXp1+0,G_MemoryAddress));
+ end if;
+ when c3 =>
+ cstate <= c3_mdr;
+ if (vppX /= ROWS-1) then
+ if (vppYp > (COLS_PIXEL/2)-1) then
+ tppY := (COLS_PIXEL/2)-vppYp;
+ if (tppY < 0) then
+ tppY := -tppY;
+ end if;
+ else
+ tppY := vppYp;
+ end if;
+ if (o_MemDB(tppY) = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+ countAlive <= std_logic_vector(to_unsigned(vcountALive,4));
+ end if;
+ when c3_mdr =>
+ if (o_membusy = '1') then
+ cstate <= c3_mdr;
+ else
+ cstate <= c3_md;
+ i_read <= '0';
+ end if;
+ when c3_md =>
+ cstate <= c4_me;
+ i_enable <= '0';
+ --
+ when c4_me =>
+ cstate <= c4_mr;
+ i_enable <= '1';
+ when c4_mr =>
+ cstate <= set_c4;
+ i_read <= '1';
+ when set_c4 =>
+ cstate <= c4;
+ if (vppYp > (COLS_PIXEL/2)-1) then
+ i_MemAdr <= std_logic_vector(to_unsigned(vppXm1+1,G_MemoryAddress));
+ else
+ i_MemAdr <= std_logic_vector(to_unsigned(vppXm1+0,G_MemoryAddress));
+ end if;
+ when c4 =>
+ cstate <= c4_mdr;
+ if (vppX /= 0) then
+ if (vppYp > (COLS_PIXEL/2)-1) then
+ tppY := (COLS_PIXEL/2)-vppYp;
+ if (tppY < 0) then
+ tppY := -tppY;
+ end if;
+ else
+ tppY := vppYp;
+ end if;
+ if (o_MemDB(tppY) = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+ countAlive <= std_logic_vector(to_unsigned(vcountALive,4));
+ end if;
+ when c4_mdr =>
+ if (o_membusy = '1') then
+ cstate <= c4_mdr;
+ else
+ cstate <= c4_md;
+ i_read <= '0';
+ end if;
+ when c4_md =>
+ cstate <= c5_me;
+ i_enable <= '0';
+ --
+ when c5_me =>
+ cstate <= c5_mr;
+ i_enable <= '1';
+ when c5_mr =>
+ cstate <= set_c5;
+ i_read <= '1';
+ when set_c5 =>
+ cstate <= c5;
+ if (vppYm1 > (COLS_PIXEL/2)-1) then
+ i_MemAdr <= std_logic_vector(to_unsigned(vppXm1+1,G_MemoryAddress));
+ else
+ i_MemAdr <= std_logic_vector(to_unsigned(vppXm1+0,G_MemoryAddress));
+ end if;
+ when c5 =>
+ cstate <= c5_mdr;
+ if ((vppX /= 0) and (vppYp /= 0)) then
+ if (vppYm1 > (COLS_PIXEL/2)-1) then
+ tppY := (COLS_PIXEL/2)-vppYm1;
+ if (tppY < 0) then
+ tppY := -tppY;
+ end if;
+ else
+ tppY := vppYm1;
+ end if;
+ if (o_MemDB(tppY) = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+ countAlive <= std_logic_vector(to_unsigned(vcountALive,4));
+ end if;
+ when c5_mdr =>
+ if (o_membusy = '1') then
+ cstate <= c5_mdr;
+ else
+ cstate <= c5_md;
+ i_read <= '0';
+ end if;
+ when c5_md =>
+ cstate <= c6_me;
+ i_enable <= '0';
+ --
+ when c6_me =>
+ cstate <= c6_mr;
+ i_enable <= '1';
+ when c6_mr =>
+ cstate <= set_c6;
+ i_read <= '1';
+ when set_c6 =>
+ cstate <= c6;
+ if (vppYm1 > (COLS_PIXEL/2)-1) then
+ i_MemAdr <= std_logic_vector(to_unsigned(vppXp1+1,G_MemoryAddress));
+ else
+ i_MemAdr <= std_logic_vector(to_unsigned(vppXp1+0,G_MemoryAddress));
+ end if;
+ when c6 =>
+ cstate <= c6_mdr;
+ if ((vppX /= ROWS-1) and (vppYp /= 0)) then
+ if (vppYm1 > (COLS_PIXEL/2)-1) then
+ tppY := (COLS_PIXEL/2)-vppYm1;
+ if (tppY < 0) then
+ tppY := -tppY;
+ end if;
+ else
+ tppY := vppYm1;
+ end if;
+ if (o_MemDB(tppY) = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+ countAlive <= std_logic_vector(to_unsigned(vcountALive,4));
+ end if;
+ when c6_mdr =>
+ if (o_membusy = '1') then
+ cstate <= c6_mdr;
+ else
+ cstate <= c6_md;
+ i_read <= '0';
+ end if;
+ when c6_md =>
+ cstate <= c7_me;
+ i_enable <= '0';
+ --
+ when c7_me =>
+ cstate <= c7_mr;
+ i_enable <= '1';
+ when c7_mr =>
+ cstate <= set_c7;
+ i_read <= '1';
+ when set_c7 =>
+ cstate <= c7;
+ if (vppYp1 > (COLS_PIXEL/2)-1) then
+ i_MemAdr <= std_logic_vector(to_unsigned(vppXm1+1,G_MemoryAddress));
+ else
+ i_MemAdr <= std_logic_vector(to_unsigned(vppXm1+0,G_MemoryAddress));
+ end if;
+ when c7 =>
+ cstate <= c7_mdr;
+ if ((vppX /= 0) and (vppYp /= COLS_PIXEL-1)) then
+ if (vppYp1 > (COLS_PIXEL/2)-1) then
+ tppY := (COLS_PIXEL/2)-vppYp1;
+ if (tppY < 0) then
+ tppY := -tppY;
+ end if;
+ else
+ tppY := vppYp1;
+ end if;
+ if (o_MemDB(tppY) = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+ countAlive <= std_logic_vector(to_unsigned(vcountALive,4));
+ end if;
+ when c7_mdr =>
+ if (o_membusy = '1') then
+ cstate <= c7_mdr;
+ else
+ cstate <= c7_md;
+ i_read <= '0';
+ end if;
+ when c7_md =>
+ cstate <= c8_me;
+ i_enable <= '0';
+ --
+ when c8_me =>
+ cstate <= c8_mr;
+ i_enable <= '1';
+ when c8_mr =>
+ cstate <= set_c8;
+ i_read <= '1';
+ when set_c8 =>
+ cstate <= c8;
+ if (vppYp1 > (COLS_PIXEL/2)-1) then
+ i_MemAdr <= std_logic_vector(to_unsigned(vppXp1+1,G_MemoryAddress));
+ else
+ i_MemAdr <= std_logic_vector(to_unsigned(vppXp1+0,G_MemoryAddress));
+ end if;
+ when c8 =>
+ cstate <= c8_mdr;
+ if ((vppX /= ROWS-1) and (vppYp /= COLS_PIXEL-1)) then
+ if (vppYp1 > (COLS_PIXEL/2)-1) then
+ tppY := (COLS_PIXEL/2)-vppYp1;
+ if (tppY < 0) then
+ tppY := -tppY;
+ end if;
+ else
+ tppY := vppYp1;
+ end if;
+ if (o_MemDB(tppY) = '1') then
+ vcountAlive := vcountAlive + 1;
+ end if;
+ countAlive <= std_logic_vector(to_unsigned(vcountALive,4));
+ end if;
+ when waitfor =>
+ cstate <= memory_disable_bit;
+ countAlive <= std_logic_vector(to_unsigned(vcountALive,4));
+ when memory_disable_bit =>
+ cstate <= store_count_alive;
+ i_MemAdr <= std_logic_vector(to_unsigned(6666+vppX+vppYp,G_MemoryAddress));
+ when c8_mdr =>
+ if (o_membusy = '1') then
+ cstate <= c8_mdr;
+ else
+ cstate <= c8_md;
+ i_read <= '0';
+ end if;
+ when c8_md =>
+ cstate <= store_count_alive_me;
+ i_enable <= '0';
+ --
+ when store_count_alive_me =>
+ cstate <= store_count_alive_we;
+ i_enable <= '1';
+ when store_count_alive_we =>
+ cstate <= store_count_alive_sa;
+ i_write <= '1';
+-- when store_count_alive_sa =>
+ when store_count_alive =>
+ cstate <= store_count_alive_wd;
+ i_MemDB <= std_logic_vector(to_unsigned(vcountAlive,G_MemoryData));
+ when store_count_alive_wd =>
+ cstate <= store_count_alive_wm;
+ i_write <= '0';
+ when store_count_alive_wm =>
+ if (o_membusy='1') then
+ cstate <= store_count_alive_wm;
+ else
+ cstate <= store_count_alive_md;
+ end if;
+ when store_count_alive_md =>
+ cstate <= update_row1;
+ i_enable <= '0';
+ ENABLE <= '1';
+ WRITE_EN <= '1';
+ ADDRESS <= std_logic_vector(to_unsigned(vppX+vppYp*WORD_BITS,12));
+ DATA_IN <= countAlive;
+ when update_row1 =>
+ ENABLE <= '0';
+ WRITE_EN <= '0';
+ if (vppX < ROWS-1) then
+ vppX := vppX + 1;
+ cstate <= check_coordinations;
+ else
+ cstate <= update_col1;
+ end if;
+ when update_col1 =>
+ if (vppYp < COLS_PIXEL-1) then
+ vppYp := vppYp + 1;
+ cstate <= check_coordinations;
+ vppX := 0;
+ else
+ cstate <= reset_counters1;
+ vppYp := 0;
+ end if;
+ ----------------------------------------------------------------------------------
+ -- store bits in memory
+ when reset_counters1 =>
+ cstate <= memory_enable_bit1;
+ vppX := 0;
+ vppYb := 0;
+ vppYp := 0;
+ when memory_enable_bit1 =>
+ cstate <= get_alive;
+ i_enable <= '1';
+ when memory_enable_read1 =>
+ cstate <= memory_sa1;
+ i_read <= '1';
+ when memory_sa1 =>
+ cstate <= get_alive;
+ if (vppYp > (COLS_PIXEL/2)-1) then
+ i_MemAdr <= std_logic_vector(to_unsigned(vppX+1,G_MemoryAddress));
+ else
+ i_MemAdr <= std_logic_vector(to_unsigned(vppX+0,G_MemoryAddress));
+ end if;
+ when get_alive =>
+ cstate <= get_alive1;
+ if (vppYp > (COLS_PIXEL/2)-1) then
+ tppY := (COLS_PIXEL/2)-vppYp;
+ if (tppY < 0) then
+ tppY := -tppY;
+ end if;
+ else
+ tppY := vppYp;
+ end if;
+ row <= ppX;
+ col_pixel <= ppYp;
+ when get_alive1 =>
+ cstate <= memory_disable_read1;
+ if (o_MemDB(tppY) = '1') then -- xxx up before read=0
+ vCellAlive := true;
+ else
+ vCellAlive := false;
+ end if;
+ when memory_disable_read1 =>
+ cstate <= memory_disable_read1_wm;
+ i_read <= '0';
+ when memory_disable_read1_wm =>
+ if (o_membusy='1') then
+ cstate <= memory_disable_read1_wm;
+ else
+ cstate <= memory_disable_bit1;
+ end if;
+ when memory_disable_bit1 =>
+ cstate <= enable_m2;
+ i_enable <= '0';
+ when enable_m2 =>
+ cstate <= enable_write_to_memory;
+ i_enable <= '1';
+ when enable_write_to_memory =>
+ cstate <= check_cell_alive_1;
+ i_read <= '1';
+ when check_cell_alive_1 =>
+ cstate <= asdf;
+ i_MemAdr <= std_logic_vector(to_unsigned(6666+vppX+vppYp,G_MemoryAddress));
+ when asdf =>
+ cstate <= check_cell_alive_1a;
+ t := o_MemDB;
+ when check_cell_alive_1a =>
+ cstate <= check_cell_alive_2;
+ if (vCellAlive = true) then
+ if ((to_integer(unsigned(t)) = 2) or (to_integer(unsigned(t)) = 3)) then
+ newCellAlive := true;
+-- cstate <= write_count_alive;
+-- i_mem_write_bit <= '1';
+-- ENABLE <= '1';
+-- WRITE_EN <= '0';
+-- ADDRESS <= std_logic_vector(to_unsigned(vppX+vppYp*WORD_BITS,12));
+-- when write_count_alive =>
+-- cstate <= disable_write_to_memory;
+-- if (vCellAlive = true) then
+-- if ((to_integer(unsigned(DATA_OUT)) = 2) or (to_integer(unsigned(DATA_OUT)) = 3)) then
+-- i_bit <= '1';
+ else
+ newCellAlive := false;
+ end if;
+ elsif (vCellAlive = false) then
+ if ((to_integer(unsigned(t)) = 3)) then
+ newCellAlive := true;
+-- if (to_integer(unsigned(DATA_OUT)) = 3) then
+-- i_bit <= '1';
+ else
+ newCellAlive := false;
+ end if;
+ end if;
+ when check_cell_alive_2 =>
+ cstate <= check_cell_alive_wm;
+ i_read <= '0';
+ when check_cell_alive_wm =>
+ if (o_membusy='1') then
+ cstate <= check_cell_alive_wm;
+ else
+ cstate <= check_cell_alive_3;
+ end if;
+ when check_cell_alive_3 =>
+ cstate <= aa;
+ i_enable <= '0';
+ when aa =>
+ cstate <= aaa;
+ i_enable <= '1';
+ when aaa =>
+ cstate <= aaaa;
+ i_write <= '1';
+ when aaaa =>
+ cstate <= aaaaa;
+ if (vppYp > (COLS_PIXEL/2)-1) then
+ i_MemAdr <= std_logic_vector(to_unsigned(vppX+1,G_MemoryAddress));
+ else
+ i_MemAdr <= std_logic_vector(to_unsigned(vppX+0,G_MemoryAddress));
+ end if;
+ when aaaaa =>
+ cstate <= disable_write_to_memory;
+ if (newCellAlive = true) then
+ i_MemDB(tppY) <= '1';
+ else
+ i_MemDB(tppY) <= '0';
+ end if;
+ when disable_write_to_memory =>
+ cstate <= vvv_wm;
+ i_write <= '0';
+ when vvv_wm =>
+ if (o_membusy='1') then
+ cstate <= vvv_wm;
+ else
+ cstate <= vvv;
+ end if;
+ when vvv =>
+-- ENABLE <= '0';
+-- WRITE_EN <= '0';
+ cstate <= update_row2;
+ i_enable <= '0';
+ when update_row2 =>
+ if (vppX < ROWS-1) then
+ vppX := vppX + 1;
+ cstate <= get_alive;
+ else
+ cstate <= update_col2;
+ end if;
+ when update_col2 =>
+ if (vppYp < COLS_PIXEL-1) then
+ vppYp := vppYp + 1;
+ cstate <= get_alive;
+ vppX := 0;
+ else
+ cstate <= disable_memory;
+ vppYp := 0;
+ vppYb := 0;
+ end if;
+ when disable_memory =>
+ cstate <= stop;
+ i_enable <= '0';
+ ----------------------------------------------------------------------------------
+ -- end
+ when stop =>
+ cstate <= idle;
+ when others => null;
+ end case;
+ end if;
+ CellAlive <= To_Std_Logic(vCellAlive);
+ ppX <= std_logic_vector(to_unsigned(vppX,ROWS_BITS));
+ ppYp <= std_logic_vector(to_unsigned(vppYp,COLS_PIXEL_BITS));
+ ppYb <= std_logic_vector(to_unsigned(vppYb,COLS_BLOCK_BITS));
+ ppXm1 <= std_logic_vector(to_unsigned(vppXm1,ROWS_BITS));
+ ppXp1 <= std_logic_vector(to_unsigned(vppXp1,ROWS_BITS));
+ ppYm1 <= std_logic_vector(to_unsigned(vppYm1,COLS_PIXEL_BITS));
+ ppYp1 <= std_logic_vector(to_unsigned(vppYp1,COLS_PIXEL_BITS));
+ stppY <= std_logic_vector(to_unsigned(tppY,32));
+end process gof_logic;
+
+end Behavioral;
diff --git a/gof/upload.sh b/gof/upload.sh
new file mode 100755
index 0000000..05cabe9
--- /dev/null
+++ b/gof/upload.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
+
+impact -batch impact_top.ipf
diff --git a/gof_glidergun_ssd1306_32x32.gif b/gof_glidergun_ssd1306_32x32.gif
new file mode 100755
index 0000000..b8dcaf4
Binary files /dev/null and b/gof_glidergun_ssd1306_32x32.gif differ
diff --git a/gof_glidergun_st7735r.gif b/gof_glidergun_st7735r.gif
new file mode 100755
index 0000000..9197d7b
Binary files /dev/null and b/gof_glidergun_st7735r.gif differ
diff --git a/hd44780/hd44780.vhd b/hd44780/hd44780.vhd
new file mode 100755
index 0000000..6b0c4d2
--- /dev/null
+++ b/hd44780/hd44780.vhd
@@ -0,0 +1,138 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:57:47 03/25/2021
+-- Design Name:
+-- Module Name: hd44780 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity hd44780 is
+Port (
+ i_clock : in STD_LOGIC;
+ i_reset : in STD_LOGIC;
+ i_enable : in STD_LOGIC;
+ i_data_type : in STD_LOGIC;
+ i_data : in STD_LOGIC_VECTOR (7 downto 0);
+ o_busy : out STD_LOGIC;
+ o_rs : out STD_LOGIC;
+ o_rw : out STD_LOGIC;
+ o_e : out STD_LOGIC;
+ o_db : inout STD_LOGIC_VECTOR (7 downto 0)
+);
+end hd44780;
+
+architecture Behavioral of hd44780 is
+
+ type state_type is (
+ idle,
+ start,
+ wait1,
+ send,
+ wait2,
+ stop
+ );
+ signal state : state_type;
+
+ signal index : integer;
+ signal rs,rw,e : std_logic;
+ signal db : std_logic_vector(7 downto 0);
+
+begin
+
+ o_db <= db when (rs = '0' or rs = '1') else (others => 'Z');
+ o_rs <= rs;
+ o_rw <= rw;
+ o_e <= e;
+
+ p0 : process (i_clock,i_reset) is
+ begin
+ if (i_reset = '1') then
+ state <= idle;
+ index <= 0;
+ rs <= 'Z';
+ rw <= '1';
+ e <= '0';
+ db <= (others => 'Z');
+ o_busy <= '0';
+ elsif (rising_edge(i_clock)) then
+ case (state) is
+ when idle =>
+ if (i_enable = '1') then
+ state <= start;
+ else
+ state <= idle;
+ end if;
+ when start =>
+ state <= wait1;
+ o_busy <= '1';
+ db <= i_data;
+ rw <= '0';
+ e <= '0';
+ if (i_data_type = '0') then -- command
+ rs <= '0';
+ elsif (i_data_type = '1') then -- data
+ rs <= '1';
+ else
+ rs <= 'Z';
+ end if;
+ when wait1 => -- 40 ns
+ if (index = 2) then
+ state <= send;
+ index <= 0;
+ else
+ state <= wait1;
+ index <= index + 1;
+ end if;
+ when send => -- 230 ns
+ state <= wait2;
+ e <= '1';
+ when wait2 => -- 10 ns
+ if (index = 12) then
+ state <= stop;
+ e <= '0';
+ index <= 0;
+ else
+ state <= wait2;
+ index <= index + 1;
+ end if;
+ when stop => -- 10 ns
+ if (index = 1) then
+ state <= idle;
+ db <= (others => 'Z');
+ index <= 0;
+ rs <= 'Z';
+ rw <= '1';
+ o_busy <= '0';
+ else
+ state <= stop;
+ index <= index + 1;
+ end if;
+ end case;
+ end if;
+ end process p0;
+
+end Behavioral;
+
diff --git a/hd44780/hd44780.xise b/hd44780/hd44780.xise
new file mode 100755
index 0000000..12961d3
--- /dev/null
+++ b/hd44780/hd44780.xise
@@ -0,0 +1,355 @@
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diff --git a/hd44780/tb_hd44780.vhd b/hd44780/tb_hd44780.vhd
new file mode 100755
index 0000000..73b56ff
--- /dev/null
+++ b/hd44780/tb_hd44780.vhd
@@ -0,0 +1,123 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:35:28 03/25/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/hd44780/tb_hd44780.vhd
+-- Project Name: hd44780
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: hd44780
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_hd44780 IS
+END tb_hd44780;
+
+ARCHITECTURE behavior OF tb_hd44780 IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT hd44780
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+i_enable : IN std_logic;
+i_data_type : IN std_logic;
+i_data : IN std_logic_vector(7 downto 0);
+o_busy : OUT std_logic;
+o_rs : OUT std_logic;
+o_rw : OUT std_logic;
+o_e : OUT std_logic;
+o_db : INOUT std_logic_vector(7 downto 0)
+);
+END COMPONENT;
+
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+signal i_enable : std_logic := '0';
+signal i_data_type : std_logic := '0';
+signal i_data : std_logic_vector(7 downto 0) := (others => '0');
+
+--BiDirs
+signal o_db : std_logic_vector(7 downto 0);
+
+--Outputs
+signal o_rs : std_logic;
+signal o_rw : std_logic;
+signal o_e : std_logic;
+signal o_busy : std_logic;
+
+-- Clock period definitions
+constant i_clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: hd44780 PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+i_enable => i_enable,
+i_data_type => i_data_type,
+i_data => i_data,
+o_busy => o_busy,
+o_rs => o_rs,
+o_rw => o_rw,
+o_e => o_e,
+o_db => o_db
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+i_reset <= '1';
+wait for 100 ns;
+i_reset <= '0';
+wait for i_clock_period;
+-- insert stimulus here
+i_enable <= '1';
+i_data_type <= '0';
+i_data <= x"38";
+wait until o_busy = '0';
+i_enable <= '0';
+i_data_type <= '1';
+i_data <= x"01";
+
+wait;
+end process;
+
+END;
diff --git a/hd44780/tb_hd44780.wcfg b/hd44780/tb_hd44780.wcfg
new file mode 100755
index 0000000..e74ffc9
--- /dev/null
+++ b/hd44780/tb_hd44780.wcfg
@@ -0,0 +1,114 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ tb
+ label
+
+ i_clock
+ i_clock
+
+
+ i_reset
+ i_reset
+
+
+ i_enable
+ i_enable
+
+
+ i_data_type
+ i_data_type
+
+
+ o_busy
+ o_busy
+
+
+ i_data[7:0]
+ i_data[7:0]
+
+
+ o_db[7:0]
+ o_db[7:0]
+
+
+ o_rs
+ o_rs
+
+
+ o_rw
+ o_rw
+
+
+ o_e
+ o_e
+
+
+ i_clock_period
+ i_clock_period
+
+
+
+ uut
+ label
+
+ i_clock
+ i_clock
+
+
+ state
+ state
+
+
+ index
+ index
+
+
+ i_reset
+ i_reset
+
+
+ i_enable
+ i_enable
+
+
+ i_data_type
+ i_data_type
+
+
+ i_data[7:0]
+ i_data[7:0]
+
+
+ o_busy
+ o_busy
+
+
+ o_rs
+ o_rs
+
+
+ o_rw
+ o_rw
+
+
+ o_e
+ o_e
+
+
+ o_db[7:0]
+ o_db[7:0]
+
+
+
diff --git a/hd44780/tb_top.vhd b/hd44780/tb_top.vhd
new file mode 100755
index 0000000..839f9c9
--- /dev/null
+++ b/hd44780/tb_top.vhd
@@ -0,0 +1,102 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:55:53 03/25/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/hd44780/tb_top.vhd
+-- Project Name: hd44780
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_top IS
+END tb_top;
+
+ARCHITECTURE behavior OF tb_top IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT top
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+o_rs : OUT std_logic;
+o_rw : OUT std_logic;
+o_e : OUT std_logic;
+o_db : INOUT std_logic_vector(7 downto 0)
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+
+--BiDirs
+signal o_db : std_logic_vector(7 downto 0);
+
+--Outputs
+signal o_rs : std_logic;
+signal o_rw : std_logic;
+signal o_e : std_logic;
+
+-- Clock period definitions
+constant i_clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: top PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+o_rs => o_rs,
+o_rw => o_rw,
+o_e => o_e,
+o_db => o_db
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+i_reset <= '1';
+wait for 100 ns;
+i_reset <= '0';
+wait for i_clock_period*10;
+-- insert stimulus here
+
+wait;
+end process;
+
+END;
diff --git a/hd44780/tb_top.wcfg b/hd44780/tb_top.wcfg
new file mode 100755
index 0000000..faa5fab
--- /dev/null
+++ b/hd44780/tb_top.wcfg
@@ -0,0 +1,187 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ tb
+ label
+
+ i_clock
+ i_clock
+
+
+ i_reset
+ i_reset
+
+
+ o_db[7:0]
+ o_db[7:0]
+ HEXRADIX
+
+
+ o_rs
+ o_rs
+
+
+ o_rw
+ o_rw
+
+
+ o_e
+ o_e
+
+
+ i_clock_period
+ i_clock_period
+
+
+
+ top
+ label
+
+ i_clock
+ i_clock
+
+
+ i_reset
+ i_reset
+
+
+ o_rs
+ o_rs
+
+
+ o_rw
+ o_rw
+
+
+ o_e
+ o_e
+
+
+ o_db[7:0]
+ o_db[7:0]
+
+
+ data[7:0]
+ data[7:0]
+
+
+ enable
+ enable
+
+
+ data_type
+ data_type
+
+
+ busy
+ busy
+
+
+ lcd_pattern_type[0:10]
+ lcd_pattern_type[0:10]
+
+
+ lcd_pattern_data[0:10]
+ lcd_pattern_data[0:10]
+
+
+ index
+ index
+
+
+ state
+ state
+
+
+ t_wait_ms
+ t_wait_ms
+
+
+ c_len_lcd_pattern
+ c_len_lcd_pattern
+
+
+ c_wait_ms
+ c_wait_ms
+
+
+
+ mlcd
+ label
+
+ i_clock
+ i_clock
+
+
+ i_reset
+ i_reset
+
+
+ i_enable
+ i_enable
+
+
+ i_data_type
+ i_data_type
+
+
+ i_data[7:0]
+ i_data[7:0]
+
+
+ o_busy
+ o_busy
+
+
+ o_rs
+ o_rs
+
+
+ o_rw
+ o_rw
+
+
+ o_e
+ o_e
+
+
+ o_db[7:0]
+ o_db[7:0]
+
+
+ state
+ state
+
+
+ index
+ index
+
+
+ rs
+ rs
+
+
+ rw
+ rw
+
+
+ e
+ e
+
+
+ db[7:0]
+ db[7:0]
+
+
+
diff --git a/hd44780/top.vhd b/hd44780/top.vhd
new file mode 100755
index 0000000..fa18dc9
--- /dev/null
+++ b/hd44780/top.vhd
@@ -0,0 +1,145 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:33:57 03/25/2021
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top is
+Port (
+ i_clock : in STD_LOGIC;
+ i_reset : in STD_LOGIC;
+ o_rs : out STD_LOGIC;
+ o_rw : out STD_LOGIC;
+ o_e : out STD_LOGIC;
+ o_db : inout STD_LOGIC_VECTOR (7 downto 0)
+);
+end top;
+
+architecture Behavioral of top is
+
+ COMPONENT hd44780 IS
+ Port (
+ i_clock : in STD_LOGIC;
+ i_reset : in STD_LOGIC;
+ i_enable : in STD_LOGIC;
+ i_data_type : in STD_LOGIC;
+ i_data : in STD_LOGIC_VECTOR (7 downto 0);
+ o_busy : out STD_LOGIC;
+ o_rs : out STD_LOGIC;
+ o_rw : out STD_LOGIC;
+ o_e : out STD_LOGIC;
+ o_db : inout STD_LOGIC_VECTOR (7 downto 0)
+ );
+ END COMPONENT hd44780;
+
+ signal data : std_logic_vector(7 downto 0);
+ signal enable,data_type,busy : std_logic;
+
+ constant C_LEN_LCD_PATTERN : integer := 11;
+ type A_LCD_PATTERN_TYPE is array(0 to C_LEN_LCD_PATTERN-1) of std_logic;
+ type A_LCD_PATTERN_DATA is array(0 to C_LEN_LCD_PATTERN-1) of std_logic_vector(7 downto 0);
+ signal LCD_PATTERN_TYPE : A_LCD_PATTERN_TYPE := ('0','0','0','0','0','0','0','1','1','1','1');
+ signal LCD_PATTERN_DATA : A_LCD_PATTERN_DATA := (x"38",x"38",x"38",x"38",x"0F",x"01",x"06",x"41",x"42",x"43",x"44");
+ signal index : integer;
+
+ type state_type is (
+ idle,send,st_busy,st_wait,increment,stop
+ );
+ signal state : state_type;
+
+ constant C_WAIT_MS : integer := 1_000_000;
+ signal t_wait_ms : integer;
+
+begin
+
+ p0 : process (i_clock,i_reset) is
+ begin
+ if (i_reset = '1') then
+ state <= idle;
+ index <= 0;
+ t_wait_ms <= 0;
+ elsif (rising_edge(i_clock)) then
+ case (state) is
+ when idle =>
+ --if (t_wait_ms = 4*C_WAIT_MS-1) then
+ state <= send;
+ enable <= '1';
+ --t_wait_ms <= 0;
+ --else
+ --t_wait_ms <= t_wait_ms + 1;
+ --end if;
+ when send =>
+ state <= st_busy;
+ data_type <= LCD_PATTERN_TYPE(index);
+ data <= LCD_PATTERN_DATA(index);
+ when st_busy =>
+ if (busy = '1') then
+ state <= st_busy;
+ else
+ state <= st_wait;
+ enable <= '0';
+ data <= x"00";
+ end if;
+ when st_wait =>
+ if (t_wait_ms = 4*C_WAIT_MS-1) then
+ state <= increment;
+ t_wait_ms <= 0;
+ else
+ t_wait_ms <= t_wait_ms + 1;
+ end if;
+ when increment =>
+ if (index = C_LEN_LCD_PATTERN-1) then
+ state <= stop;
+ index <= 0;
+ else
+ state <= idle;
+ enable <= '0';
+ index <= index + 1;
+ end if;
+ when stop =>
+ state <= stop;
+ end case;
+ end if;
+ end process p0;
+
+ m_hd44780 : hd44780
+ PORT MAP (
+ i_clock => i_clock,
+ i_reset => i_reset,
+ i_enable => enable,
+ i_data_type => data_type,
+ i_data => data,
+ o_busy => busy,
+ o_rs => o_rs,
+ o_rw => o_rw,
+ o_e => o_e,
+ o_db => o_db
+ );
+
+
+end Behavioral;
diff --git a/ladder_r2r.gif b/ladder_r2r.gif
new file mode 100755
index 0000000..787e238
Binary files /dev/null and b/ladder_r2r.gif differ
diff --git a/lcd_rotate.gif b/lcd_rotate.gif
new file mode 100755
index 0000000..dc8c8bb
Binary files /dev/null and b/lcd_rotate.gif differ
diff --git a/memorydump_93LC46/Nexys2_1200General.ucf b/memorydump_93LC46/Nexys2_1200General.ucf
new file mode 100755
index 0000000..0ad1685
--- /dev/null
+++ b/memorydump_93LC46/Nexys2_1200General.ucf
@@ -0,0 +1,255 @@
+## This file is a general .ucf for Nexys2 rev A board
+## To use it in a project:
+## - remove or comment the lines corresponding to unused pins
+## - rename the used signals according to the project
+
+## Signals Led<7>Led<4> are assigned to pins which change type from s3e500 to other dies using the same package
+## Both versions are provided in this file.
+## Keep only the appropriate one, and remove or comment the other one.
+
+## Clock pin for Nexys 2 Board
+NET "i_clock" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
+#NET "clk" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
+#NET "clk1" LOC = "U9"; # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK, Sch name = GCLK1
+
+## onBoard USB controller
+## NOTE: DEPP and DSTM net names use some of the same pins, if trying to use both DEPP and DSTM use a signle net name for each shared pin.
+
+## Data bus for both the DEPP and DSTM interfaces uncomment lines 19-26 if using either one
+#NET "DB<0>" LOC = "R14"; # Bank = 2, Pin name = IO_L24N_2/A20, Type = DUAL, Sch name = U-FD0
+#NET "DB<1>" LOC = "R13"; # Bank = 2, Pin name = IO_L22N_2/A22, Type = DUAL, Sch name = U-FD1
+#NET "DB<2>" LOC = "P13"; # Bank = 2, Pin name = IO_L22P_2/A23, Type = DUAL, Sch name = U-FD2
+#NET "DB<3>" LOC = "T12"; # Bank = 2, Pin name = IO_L20P_2, Type = I/O, Sch name = U-FD3
+#NET "DB<4>" LOC = "N11"; # Bank = 2, Pin name = IO_L18N_2, Type = I/O, Sch name = U-FD4
+#NET "DB<5>" LOC = "R11"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = U-FD5
+#NET "DB<6>" LOC = "P10"; # Bank = 2, Pin name = IO_L15N_2/D1/GCLK3, Type = DUAL/GCLK, Sch name = U-FD6
+#NET "DB<7>" LOC = "R10"; # Bank = 2, Pin name = IO_L15P_2/D2/GCLK2, Type = DUAL/GCLK, Sch name = U-FD7
+
+## If using the DEPP interface uncomment lines 29-32
+#NET "EppWRITE" LOC = "V16"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-FLAGC
+#NET "EppASTB" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
+#NET "EppDSTB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
+#NET "EppWAIT" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
+
+## If using the DSTM interface uncomment lines 35-44
+#NET "DstmIFCLK" LOC = "T15"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = U-IFCLK
+#NET "DstmSLCS" LOC = "T16"; # Bank = 2, Pin name = IO_L26P_2/VS0/A17, Type = DUAL, Sch name = U-SLCS
+#NET "DstmFLAGA" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
+#NET "DstmFLAGB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
+#NET "DstmADR<0>" LOC = "T14"; # Bank = 2, Pin name = IO_L24P_2/A21, Type = DUAL, Sch name = U-FIFOAD0
+#NET "DstmADR<1>" LOC = "V13"; # Bank = 2, Pin name = IO_L19N_2/VREF_2, Type = VREF, Sch name = U-FIFOAD1
+#NET "DstmSLRD" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
+#NET "DstmSLWR" LOC = "V9"; # Bank = 2, Pin name = IO_L13N_2/D3/GCLK15, Type = DUAL/GCLK, Sch name = U-SLWR
+#NET "DstmSLOE" LOC = "V15"; # Bank = 2, Pin name = IO_L25P_2/VS2/A19, Type = DUAL, Sch name = U-SLOE
+#NET "DstmPKTEND" LOC = "V12"; # Bank = 2, Pin name = IO_L19P_2, Type = I/O, Sch name = U-PKTEND
+
+#NET "UsbMode" LOC = "U15"; # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type = DUAL, Sch name = U-INT0#
+#NET "UsbRdy" LOC = "U13"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-RDY
+
+## onBoard Cellular RAM and StrataFlash
+#NET "io_MemOE" LOC = "T2"; # Bank = 3, Pin name = IO_L24P_3, Type = I/O, Sch name = OE
+#NET "io_MemWR" LOC = "N7"; # Bank = 2, Pin name = IO_L07P_2, Type = I/O, Sch name = WE
+#
+#NET "io_RamAdv" LOC = "J4"; # Bank = 3, Pin name = IO_L11N_3/LHCLK1, Type = LHCLK, Sch name = MT-ADV
+#NET "io_RamCS" LOC = "R6"; # Bank = 2, Pin name = IO_L05P_2, Type = I/O, Sch name = MT-CE
+#NET "io_RamClk" LOC = "H5"; # Bank = 3, Pin name = IO_L08N_3, Type = I/O, Sch name = MT-CLK
+#NET "io_RamCRE" LOC = "P7"; # Bank = 2, Pin name = IO_L07N_2, Type = I/O, Sch name = MT-CRE
+#NET "io_RamLB" LOC = "K5"; # Bank = 3, Pin name = IO_L14N_3/LHCLK7, Type = LHCLK, Sch name = MT-LB
+#NET "io_RamUB" LOC = "K4"; # Bank = 3, Pin name = IO_L13N_3/LHCLK5, Type = LHCLK, Sch name = MT-UB
+#NET "RamWait" LOC = "F5"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = MT-WAIT
+
+#NET "FlashRp" LOC = "T5"; # Bank = 2, Pin name = IO_L04N_2, Type = I/O, Sch name = RP#
+#NET "io_FlashCS" LOC = "R5"; # Bank = 2, Pin name = IO_L04P_2, Type = I/O, Sch name = ST-CE
+#NET "FlashStSts" LOC = "D3"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = ST-STS
+
+#NET "io_MemAdr<1>" LOC = "J1"; # Bank = 3, Pin name = IO_L12P_3/LHCLK2, Type = LHCLK, Sch name = ADR1
+#NET "io_MemAdr<2>" LOC = "J2"; # Bank = 3, Pin name = IO_L12N_3/LHCLK3/IRDY2, Type = LHCLK, Sch name = ADR2
+#NET "io_MemAdr<3>" LOC = "H4"; # Bank = 3, Pin name = IO_L09P_3, Type = I/O, Sch name = ADR3
+#NET "io_MemAdr<4>" LOC = "H1"; # Bank = 3, Pin name = IO_L10N_3, Type = I/O, Sch name = ADR4
+#NET "io_MemAdr<5>" LOC = "H2"; # Bank = 3, Pin name = IO_L10P_3, Type = I/O, Sch name = ADR5
+#NET "io_MemAdr<6>" LOC = "J5"; # Bank = 3, Pin name = IO_L11P_3/LHCLK0, Type = LHCLK, Sch name = ADR6
+#NET "io_MemAdr<7>" LOC = "H3"; # Bank = 3, Pin name = IO_L09N_3, Type = I/O, Sch name = ADR7
+#NET "io_MemAdr<8>" LOC = "H6"; # Bank = 3, Pin name = IO_L08P_3, Type = I/O, Sch name = ADR8
+#NET "io_MemAdr<9>" LOC = "F1"; # Bank = 3, Pin name = IO_L05P_3, Type = I/O, Sch name = ADR9
+#NET "io_MemAdr<10>" LOC = "G3"; # Bank = 3, Pin name = IO_L06P_3, Type = I/O, Sch name = ADR10
+#NET "io_MemAdr<11>" LOC = "G6"; # Bank = 3, Pin name = IO_L07P_3, Type = I/O, Sch name = ADR11
+#NET "io_MemAdr<12>" LOC = "G5"; # Bank = 3, Pin name = IO_L07N_3, Type = I/O, Sch name = ADR12
+#NET "io_MemAdr<13>" LOC = "G4"; # Bank = 3, Pin name = IO_L06N_3/VREF_3, Type = VREF, Sch name = ADR13
+#NET "io_MemAdr<14>" LOC = "F2"; # Bank = 3, Pin name = IO_L05N_3, Type = I/O, Sch name = ADR14
+#NET "io_MemAdr<15>" LOC = "E1"; # Bank = 3, Pin name = IO_L03N_3, Type = I/O, Sch name = ADR15
+#NET "io_MemAdr<16>" LOC = "M5"; # Bank = 3, Pin name = IO_L19P_3, Type = I/O, Sch name = ADR16
+#NET "io_MemAdr<17>" LOC = "E2"; # Bank = 3, Pin name = IO_L03P_3, Type = I/O, Sch name = ADR17
+#NET "io_MemAdr<18>" LOC = "C2"; # Bank = 3, Pin name = IO_L01N_3, Type = I/O, Sch name = ADR18
+#NET "io_MemAdr<19>" LOC = "C1"; # Bank = 3, Pin name = IO_L01P_3, Type = I/O, Sch name = ADR19
+#NET "io_MemAdr<20>" LOC = "D2"; # Bank = 3, Pin name = IO_L02N_3/VREF_3, Type = VREF, Sch name = ADR20
+#NET "io_MemAdr<21>" LOC = "K3"; # Bank = 3, Pin name = IO_L13P_3/LHCLK4/TRDY2, Type = LHCLK, Sch name = ADR21
+#NET "io_MemAdr<22>" LOC = "D1"; # Bank = 3, Pin name = IO_L02P_3, Type = I/O, Sch name = ADR22
+#NET "io_MemAdr<23>" LOC = "K6"; # Bank = 3, Pin name = IO_L14P_3/LHCLK6, Type = LHCLK, Sch name = ADR23
+#
+#NET "io_MemDB<0>" LOC = "L1"; # Bank = 3, Pin name = IO_L15P_3, Type = I/O, Sch name = DB0
+#NET "io_MemDB<1>" LOC = "L4"; # Bank = 3, Pin name = IO_L16N_3, Type = I/O, Sch name = DB1
+#NET "io_MemDB<2>" LOC = "L6"; # Bank = 3, Pin name = IO_L17P_3, Type = I/O, Sch name = DB2
+#NET "io_MemDB<3>" LOC = "M4"; # Bank = 3, Pin name = IO_L18P_3, Type = I/O, Sch name = DB3
+#NET "io_MemDB<4>" LOC = "N5"; # Bank = 3, Pin name = IO_L20N_3, Type = I/O, Sch name = DB4
+#NET "io_MemDB<5>" LOC = "P1"; # Bank = 3, Pin name = IO_L21N_3, Type = I/O, Sch name = DB5
+#NET "io_MemDB<6>" LOC = "P2"; # Bank = 3, Pin name = IO_L21P_3, Type = I/O, Sch name = DB6
+#NET "io_MemDB<7>" LOC = "R2"; # Bank = 3, Pin name = IO_L23N_3, Type = I/O, Sch name = DB7
+#NET "io_MemDB<8>" LOC = "L3"; # Bank = 3, Pin name = IO_L16P_3, Type = I/O, Sch name = DB8
+#NET "io_MemDB<9>" LOC = "L5"; # Bank = 3, Pin name = IO_L17N_3/VREF_3, Type = VREF, Sch name = DB9
+#NET "io_MemDB<10>" LOC = "M3"; # Bank = 3, Pin name = IO_L18N_3, Type = I/O, Sch name = DB10
+#NET "io_MemDB<11>" LOC = "M6"; # Bank = 3, Pin name = IO_L19N_3, Type = I/O, Sch name = DB11
+#NET "io_MemDB<12>" LOC = "L2"; # Bank = 3, Pin name = IO_L15N_3, Type = I/O, Sch name = DB12
+#NET "io_MemDB<13>" LOC = "N4"; # Bank = 3, Pin name = IO_L20P_3, Type = I/O, Sch name = DB13
+#NET "io_MemDB<14>" LOC = "R3"; # Bank = 3, Pin name = IO_L23P_3, Type = I/O, Sch name = DB14
+#NET "io_MemDB<15>" LOC = "T1"; # Bank = 3, Pin name = IO_L24N_3, Type = I/O, Sch name = DB15
+
+## 7 segment display
+#NET "seg<0>" LOC = "L18"; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA
+#NET "seg<1>" LOC = "F18"; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB
+#NET "seg<2>" LOC = "D17"; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC
+#NET "seg<3>" LOC = "D16"; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD
+#NET "seg<4>" LOC = "G14"; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE
+#NET "seg<5>" LOC = "J17"; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
+#NET "seg<6>" LOC = "H14"; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG
+#NET "dp" LOC = "C17"; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP
+
+#NET "an<0>" LOC = "F17"; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0
+#NET "an<1>" LOC = "H17"; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1
+#NET "an<2>" LOC = "C18"; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2
+#NET "an<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3
+
+## Leds
+#NET "JD<7>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
+#NET "JD<6>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
+#NET "JD<5>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
+#NET "JD<4>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
+#NET "Led<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4? s3e500 only
+#NET "Led<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5? s3e500 only
+#NET "Led<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6? s3e500 only
+#NET "Led<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7? s3e500 only
+#NET "Led<4>" LOC = "E16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD4? other than s3e500
+#NET "Led<5>" LOC = "P16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD5? other than s3e500
+#NET "Led<6>" LOC = "E4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD6? other than s3e500
+#NET "Led<7>" LOC = "P4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD7? other than s3e500
+
+## Switches
+#NET "sw<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
+#NET "sw<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
+#NET "sw<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
+#NET "sw<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
+#NET "sw<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
+#NET "sw<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
+#NET "sw<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
+#NET "sw<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7
+
+## Buttons
+NET "i_reset" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
+#NET "btn<0>" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
+#NET "btn<1>" LOC = "D18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = BTN1
+#NET "btn<2>" LOC = "E18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN2
+#NET "btn<3>" LOC = "H13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN3
+
+## VGA Connector
+#NET "vgaRed<1>" LOC = "R9"; # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0
+#NET "vgaRed<2>" LOC = "T8"; # Bank = 2, Pin name = IO_L10N_2, Type = I/O, Sch name = RED1
+#NET "vgaRed<3>" LOC = "R8"; # Bank = 2, Pin name = IO_L10P_2, Type = I/O, Sch name = RED2
+#NET "vgaGreen<1>" LOC = "N8"; # Bank = 2, Pin name = IO_L09N_2, Type = I/O, Sch name = GRN0
+#NET "vgaGreen<2>" LOC = "P8"; # Bank = 2, Pin name = IO_L09P_2, Type = I/O, Sch name = GRN1
+#NET "vgaGreen<3>" LOC = "P6"; # Bank = 2, Pin name = IO_L05N_2, Type = I/O, Sch name = GRN2
+#NET "vgaBlue<2>" LOC = "U5"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = BLU1
+#NET "vgaBlue<3>" LOC = "U4"; # Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DUAL, Sch name = BLU2
+
+#NET "Hsync" LOC = "T4"; # Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type = DUAL, Sch name = HSYNC
+#NET "Vsync" LOC = "U3"; # Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUAL, Sch name = VSYNC
+
+## PS/2 connector
+#NET "PS2C" LOC = "R12"; # Bank = 2, Pin name = IO_L20N_2, Type = I/O, Sch name = PS2C
+#NET "PS2D" LOC = "P11"; # Bank = 2, Pin name = IO_L18P_2, Type = I/O, Sch name = PS2D
+
+## FX2 connector
+#NET "PIO<0>" LOC = "B4"; # Bank = 0, Pin name = IO_L24N_0, Type = I/O, Sch name = R-IO1
+#NET "PIO<1>" LOC = "A4"; # Bank = 0, Pin name = IO_L24P_0, Type = I/O, Sch name = R-IO2
+#NET "PIO<2>" LOC = "C3"; # Bank = 0, Pin name = IO_L25P_0, Type = I/O, Sch name = R-IO3
+#NET "PIO<3>" LOC = "C4"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO4
+#NET "PIO<4>" LOC = "B6"; # Bank = 0, Pin name = IO_L20P_0, Type = I/O, Sch name = R-IO5
+#NET "PIO<5>" LOC = "D5"; # Bank = 0, Pin name = IO_L23N_0/VREF_0, Type = VREF, Sch name = R-IO6
+#NET "PIO<6>" LOC = "C5"; # Bank = 0, Pin name = IO_L23P_0, Type = I/O, Sch name = R-IO7
+#NET "PIO<7>" LOC = "F7"; # Bank = 0, Pin name = IO_L19P_0, Type = I/O, Sch name = R-IO8
+#NET "PIO<8>" LOC = "E7"; # Bank = 0, Pin name = IO_L19N_0/VREF_0, Type = VREF, Sch name = R-IO9
+#NET "PIO<9>" LOC = "A6"; # Bank = 0, Pin name = IO_L20N_0, Type = I/O, Sch name = R-IO10
+#NET "PIO<10>" LOC = "C7"; # Bank = 0, Pin name = IO_L18P_0, Type = I/O, Sch name = R-IO11
+#NET "PIO<11>" LOC = "F8"; # Bank = 0, Pin name = IO_L17N_0, Type = I/O, Sch name = R-IO12
+#NET "PIO<12>" LOC = "D7"; # Bank = 0, Pin name = IO_L18N_0/VREF_0, Type = VREF, Sch name = R-IO13
+#NET "PIO<13>" LOC = "E8"; # Bank = 0, Pin name = IO_L17P_0, Type = I/O, Sch name = R-IO14
+#NET "PIO<14>" LOC = "E9"; # Bank = 0, Pin name = IO_L15P_0, Type = I/O, Sch name = R-IO15
+#NET "PIO<15>" LOC = "C9"; # Bank = 0, Pin name = IO_L14P_0/GCLK10, Type = GCLK, Sch name = R-IO16
+#NET "PIO<16>" LOC = "A8"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO17
+#NET "PIO<17>" LOC = "G9"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO18
+#NET "PIO<18>" LOC = "F9"; # Bank = 0, Pin name = IO_L15N_0, Type = I/O, Sch name = R-IO19
+#NET "PIO<19>" LOC = "D10"; # Bank = 0, Pin name = IO_L11P_0/GCLK4, Type = GCLK, Sch name = R-IO20
+#NET "PIO<20>" LOC = "A10"; # Bank = 0, Pin name = IO_L12N_0/GCLK7, Type = GCLK, Sch name = R-IO21
+#NET "PIO<21>" LOC = "B10"; # Bank = 0, Pin name = IO_L12P_0/GCLK6, Type = GCLK, Sch name = R-IO22
+#NET "PIO<22>" LOC = "A11"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO23
+#NET "PIO<23>" LOC = "D11"; # Bank = 0, Pin name = IO_L09N_0, Type = I/O, Sch name = R-IO24
+#NET "PIO<24>" LOC = "E10"; # Bank = 0, Pin name = IO_L11N_0/GCLK5, Type = GCLK, Sch name = R-IO25
+#NET "PIO<25>" LOC = "B11"; # Bank = 0, Pin name = IO/VREF_0, Type = VREF, Sch name = R-IO26
+#NET "PIO<26>" LOC = "C11"; # Bank = 0, Pin name = IO_L09P_0, Type = I/O, Sch name = R-IO27
+#NET "PIO<27>" LOC = "E11"; # Bank = 0, Pin name = IO_L08P_0, Type = I/O, Sch name = R-IO28
+#NET "PIO<28>" LOC = "F11"; # Bank = 0, Pin name = IO_L08N_0, Type = I/O, Sch name = R-IO29
+#NET "PIO<29>" LOC = "E12"; # Bank = 0, Pin name = IO_L06N_0, Type = I/O, Sch name = R-IO30
+#NET "PIO<30>" LOC = "F12"; # Bank = 0, Pin name = IO_L06P_0, Type = I/O, Sch name = R-IO31
+#NET "PIO<31>" LOC = "A13"; # Bank = 0, Pin name = IO_L05P_0, Type = I/O, Sch name = R-IO32
+#NET "PIO<32>" LOC = "B13"; # Bank = 0, Pin name = IO_L05N_0/VREF_0, Type = VREF, Sch name = R-IO33
+#NET "PIO<33>" LOC = "E13"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO34
+#NET "PIO<34>" LOC = "A14"; # Bank = 0, Pin name = IO_L04N_0, Type = I/O, Sch name = R-IO35
+#NET "PIO<35>" LOC = "C14"; # Bank = 0, Pin name = IO_L03N_0/VREF_0, Type = VREF, Sch name = R-IO36
+#NET "PIO<36>" LOC = "D14"; # Bank = 0, Pin name = IO_L03P_0, Type = I/O, Sch name = R-IO37
+#NET "PIO<37>" LOC = "B14"; # Bank = 0, Pin name = IO_L04P_0, Type = I/O, Sch name = R-IO38
+#NET "PIO<38>" LOC = "A16"; # Bank = 0, Pin name = IO_L01N_0, Type = I/O, Sch name = R-IO39
+#NET "PIO<39>" LOC = "B16"; # Bank = 0, Pin name = IO_L01P_0, Type = I/O, Sch name = R-IO40
+
+## 12 pin connectors
+
+NET "O_CS" LOC = "L15"; # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1
+NET "O_SK" LOC = "K12"; # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2
+NET "O_DI" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
+NET "I_DO" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
+##JA
+#NET "JA<0>" LOC = "L15"; # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1
+#NET "JA<1>" LOC = "K12"; # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2
+#NET "JA<2>" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
+#NET "JA<3>" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
+#NET "JA<4>" LOC = "K13"; # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL, Sch name = JA7
+#NET "JA<5>" LOC = "L16"; # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL, Sch name = JA8
+#NET "JA<6>" LOC = "M14"; # Bank = 1, Pin name = IO_L05P_1, Type = I/O, Sch name = JA9
+#NET "JA<7>" LOC = "M16"; # Bank = 1, Pin name = IO_L07N_1, Type = I/O, Sch name = JA10
+
+##JB
+#NET "JB<0>" LOC = "M13"; # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF, Sch name = JB1
+#NET "JB<1>" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
+#NET "JB<2>" LOC = "R15"; # Bank = 1, Pin name = IO_L03P_1, Type = I/O, Sch name = JB3
+#NET "JB<3>" LOC = "T17"; # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL, Sch name = JB4
+#NET "JB<4>" LOC = "P17"; # Bank = 1, Pin name = IO_L06P_1, Type = I/O, Sch name = JB7
+#NET "JB<5>" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
+#NET "JB<6>" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
+#NET "JB<7>" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
+
+##JC
+#NET "JC<0>" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
+#NET "JC<1>" LOC = "J16"; # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL, Sch name = JC2
+#NET "JC<2>" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
+#NET "JC<3>" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
+#NET "JC<4>" LOC = "H15"; # Bank = 1, Pin name = IO_L17N_1, Type = I/O, Sch name = JC7
+#NET "JC<5>" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
+#NET "JC<6>" LOC = "G16"; # Bank = 1, Pin name = IO_L18N_1, Type = I/O, Sch name = JC9
+#NET "JC<7>" LOC = "J12"; # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL, Sch name = JC10
+
+##JD - NOTE: For other JD pins see LD(3:0) above under "Leds"
+#NET "JD<0>" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
+#NET "JD<1>" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
+#NET "JD<2>" LOC = "N18"; # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3
+#NET "JD<3>" LOC = "P18"; # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4
+
+## RS232 connector
+NET "i_RsRx" LOC = "U6"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = RS-RX
+NET "o_RsTx" LOC = "P9"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = RS-TX
diff --git a/memorydump_93LC46/clock_divider_count.vhd b/memorydump_93LC46/clock_divider_count.vhd
new file mode 100755
index 0000000..c86681d
--- /dev/null
+++ b/memorydump_93LC46/clock_divider_count.vhd
@@ -0,0 +1,75 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:42:10 09/18/2020
+-- Design Name:
+-- Module Name: clock_divider - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_constants.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_divider_count is
+Generic (
+ g_board_clock : integer := G_BOARD_CLOCK_HARDWARE;
+ g_divider : integer := 1
+);
+Port (
+ i_reset : in STD_LOGIC;
+ i_clock : in STD_LOGIC;
+ i_enable : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+);
+end clock_divider_count;
+
+architecture Behavioral of clock_divider_count is
+begin
+
+p0 : process (i_clock,i_reset) is
+ variable clock_out : std_logic;
+ variable counter : integer := 0;
+ variable divider : integer := (g_board_clock / g_divider);
+begin
+ if (i_reset = '1') then
+ counter := 0;
+ clock_out := '0';
+ elsif (rising_edge(i_clock)) then
+ if (i_enable = '1') then
+ if (counter = divider - 1) then
+ clock_out := not clock_out;
+ --clock_out := '1';
+ counter := 0;
+ else
+ --clock_out := '0';
+ counter := counter + 1;
+ end if;
+ else
+ counter := 0;
+ clock_out := '0';
+ end if;
+ end if;
+ o_clock <= clock_out;
+end process p0;
+
+end Behavioral;
diff --git a/memorydump_93LC46/memorydump_93LC46.xise b/memorydump_93LC46/memorydump_93LC46.xise
new file mode 100755
index 0000000..d63c2e1
--- /dev/null
+++ b/memorydump_93LC46/memorydump_93LC46.xise
@@ -0,0 +1,361 @@
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diff --git a/memorydump_93LC46/memorydump_93LC46_digikeyspi.xise b/memorydump_93LC46/memorydump_93LC46_digikeyspi.xise
new file mode 100755
index 0000000..7952eef
--- /dev/null
+++ b/memorydump_93LC46/memorydump_93LC46_digikeyspi.xise
@@ -0,0 +1,361 @@
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diff --git a/memorydump_93LC46/p_constants.vhd b/memorydump_93LC46/p_constants.vhd
new file mode 100755
index 0000000..7d0355d
--- /dev/null
+++ b/memorydump_93LC46/p_constants.vhd
@@ -0,0 +1,43 @@
+--
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+--
+-- To use any of the example code shown below, uncomment the lines and modify as necessary
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package p_constants is
+ constant G_BOARD_CLOCK_HARDWARE : integer := 50_000_000;
+ constant G_BOARD_CLOCK_SIMULATE : integer := 1_000_000;
+ constant G_CLOCK_DIV1 : integer := 50; -- XXX SPI MAX 1MHZ,VCC=3V+/-10%
+ constant NUMBER_BITS : integer := 8;
+ constant G_MemoryAddress : integer := 7; -- XXX 1K 93LC46 128x8 or 64x16
+ constant G_MemoryData : integer := NUMBER_BITS;
+ subtype MemoryAddress is std_logic_vector(G_MemoryAddress-1 downto 0);
+ constant MemoryAddressMAX : MemoryAddress := (others => '1');
+ constant MemoryAddressMIN : MemoryAddress := (others => '0');
+ subtype MemoryDataByte is std_logic_vector(G_MemoryData-1 downto 0);
+ constant MemoryDataByteMAX : MemoryDataByte := (others => '1');
+ constant MemoryDataByteMIN : MemoryDataByte := (others => '0');
+-- constant G_BAUD_RATE : integer := 115200;
+-- constant G_BAUD_RATE : integer := 57600;
+-- constant G_BAUD_RATE : integer := 38400;
+-- constant G_BAUD_RATE : integer := 19200;
+-- constant G_BAUD_RATE : integer := 9600;
+-- constant G_BAUD_RATE : integer := 4800;
+-- constant G_BAUD_RATE : integer := 2400;
+-- constant G_BAUD_RATE : integer := 1200;
+ constant G_BAUD_RATE : integer := 300;
+-- constant G_BR_OVERSAMPLING : integer := 16;
+-- constant G_PARITY : integer := 0;
+-- constant G_PARITY_EO : std_logic := '0'; -- even/odd
+ constant d_width : INTEGER := 2; -- data bus width
+ constant slaves : INTEGER := 1; -- number of spi slaves
+end p_constants;
+
+package body p_constants is
+end p_constants;
diff --git a/memorydump_93LC46/rs232.vhd b/memorydump_93LC46/rs232.vhd
new file mode 100755
index 0000000..50cb656
--- /dev/null
+++ b/memorydump_93LC46/rs232.vhd
@@ -0,0 +1,287 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:54:25 09/08/2020
+-- Design Name:
+-- Module Name: module_1 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_constants.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity rs232 is
+Generic (
+ G_BOARD_CLOCK : integer := G_BOARD_CLOCK_HARDWARE;
+ G_BAUD_RATE : integer := G_BAUD_RATE
+);
+Port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ enable_tx : in STD_LOGIC;
+ enable_rx : in STD_LOGIC;
+ byte_to_send : in STD_LOGIC_VECTOR (G_MemoryData-1 downto 0);
+ byte_received : out STD_LOGIC_VECTOR (G_MemoryData-1 downto 0);
+ busy : out STD_LOGIC;
+ ready : out STD_LOGIC;
+ is_byte_received : out STD_LOGIC;
+ RsTx : out STD_LOGIC;
+ RsRx : in STD_LOGIC
+);
+end rs232;
+
+architecture Behavioral of rs232 is
+
+ constant recv_bits : integer := 10;
+ constant a : integer := (G_BOARD_CLOCK/G_BAUD_RATE);
+
+ signal v_i : std_logic_vector(31 downto 0);
+ signal v_w : std_logic_vector(31 downto 0);
+ signal t_w : std_logic_vector(31 downto 0);
+ signal temp : std_logic_vector(recv_bits - 1 downto 0);
+
+ type state is (
+ idle,
+ start,wstart,
+ b1,wb1,b2,wb2,b3,wb3,b4,wb4,b5,wb5,b6,wb6,b7,wb7,b8,wb8,
+ parity,wparity,
+ stop,wstop
+ );
+ signal c_state : state;
+
+ type s_recv is (
+ idle,
+ start,
+ recv,
+ wait0,
+ increment,
+ stop
+ );
+ signal r_state : s_recv;
+
+begin
+
+ p0 : process (clk,rst) is
+ begin
+ if (rst = '1') then
+ r_state <= idle;
+ v_i <= (others => '0');
+ v_w <= (others => '0');
+ temp <= (others => '0');
+ elsif (rising_edge(clk)) then
+ case (r_state) is
+ when idle =>
+ if (enable_rx = '1') then
+ r_state <= start;
+ v_i <= (others => '0');
+ v_w <= (others => '0');
+ is_byte_received <= '0';
+ elsif (enable_rx = '0') then
+ r_state <= idle;
+ end if;
+ when start =>
+ if (RsRx = '1') then
+ if (to_integer(unsigned(v_i)) = a-1) then
+ r_state <= recv;
+ v_i <= x"00000001"; -- we receive first bit
+ temp(0) <= RsRx;
+ else
+ r_state <= start;
+ v_i <= std_logic_vector(to_unsigned(to_integer(unsigned(v_i)) + 1,32));
+ end if;
+ elsif (RsRx = '0') then
+ r_state <= start;
+ v_i <= (others => '0');
+ end if;
+ when recv =>
+ r_state <= wait0;
+ temp(to_integer(unsigned(v_i))) <= RsRx;
+ when wait0 =>
+ if (to_integer(unsigned(v_w)) = a-1) then
+ r_state <= increment;
+ v_w <= (others => '0');
+ else
+ v_w <= std_logic_vector(to_unsigned(to_integer(unsigned(v_w)) + 1,32));
+ r_state <= wait0;
+ end if;
+ when increment =>
+ if (to_integer(unsigned(v_i)) = recv_bits-1) then
+ r_state <= stop;
+ v_i <= (others => '0');
+ else
+ v_i <= std_logic_vector(to_unsigned(to_integer(unsigned(v_i)) + 1,32));
+ r_state <= recv;
+ end if;
+ when stop =>
+ r_state <= idle;
+ byte_received <= temp(recv_bits-2 downto 1);
+ is_byte_received <= '1';
+ end case;
+ end if;
+ end process p0;
+
+ p1 : process (clk,rst) is
+ begin
+ if (rst = '1') then
+ c_state <= start;
+ busy <= '0';
+ ready <= '1';
+ RsTx <= '0';
+ t_w <= (others => '0');
+ elsif (rising_edge(clk)) then
+ case c_state is
+ when idle =>
+ if (enable_tx = '1') then
+ c_state <= start;
+ end if;
+ when start =>
+ c_state <= wstart;
+ busy <= '1';
+ ready <= '0';
+ RsTx <= '1';
+ when wstart =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ c_state <= b1;
+ t_w <= (others => '0');
+ else
+ c_state <= wstart;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b1 =>
+ c_state <= wb1;
+ RsTx <= byte_to_send(0);
+ when wb1 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ c_state <= b2;
+ t_w <= (others => '0');
+ else
+ c_state <= wb1;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b2 =>
+ c_state <= wb2;
+ RsTx <= byte_to_send(1);
+ when wb2 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ c_state <= b3;
+ t_w <= (others => '0');
+ else
+ c_state <= wb2;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b3 =>
+ c_state <= wb3;
+ RsTx <= byte_to_send(2);
+ when wb3 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ c_state <= b4;
+ t_w <= (others => '0');
+ else
+ c_state <= wb3;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b4 =>
+ c_state <= wb4;
+ RsTx <= byte_to_send(3);
+ when wb4 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ c_state <= b5;
+ t_w <= (others => '0');
+ else
+ c_state <= wb4;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b5 =>
+ c_state <= wb5;
+ RsTx <= byte_to_send(4);
+ when wb5 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ c_state <= b6;
+ t_w <= (others => '0');
+ else
+ c_state <= wb5;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b6 =>
+ c_state <= wb6;
+ RsTx <= byte_to_send(5);
+ when wb6 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ c_state <= b7;
+ t_w <= (others => '0');
+ else
+ c_state <= wb6;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b7 =>
+ c_state <= wb7;
+ RsTx <= byte_to_send(6);
+ when wb7 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ c_state <= b8;
+ t_w <= (others => '0');
+ else
+ c_state <= wb7;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b8 =>
+ c_state <= wb8;
+ RsTx <= byte_to_send(7);
+ when wb8 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ c_state <= parity;
+ t_w <= (others => '0');
+ else
+ c_state <= wb8;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when parity =>
+ c_state <= wparity;
+ RsTx <= byte_to_send(0) xor byte_to_send(1) xor byte_to_send(2) xor byte_to_send(3) xor byte_to_send(4) xor byte_to_send(5) xor byte_to_send(6) xor byte_to_send(7);
+ when wparity =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ c_state <= stop;
+ t_w <= (others => '0');
+ else
+ c_state <= wparity;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when stop =>
+ RsTx <= '0';
+ c_state <= wstop;
+ busy <= '0';
+ ready <= '1';
+ when wstop =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ c_state <= idle;
+ t_w <= (others => '0');
+ else
+ c_state <= wstop;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when others => null;
+ end case;
+ end if;
+ end process p1;
+
+end Behavioral;
diff --git a/memorydump_93LC46/spi_master.vhd b/memorydump_93LC46/spi_master.vhd
new file mode 100755
index 0000000..1448420
--- /dev/null
+++ b/memorydump_93LC46/spi_master.vhd
@@ -0,0 +1,172 @@
+--------------------------------------------------------------------------------
+--
+-- FileName: spi_master.vhd
+-- Dependencies: none
+-- Design Software: Quartus II Version 9.0 Build 132 SJ Full Version
+--
+-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
+-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
+-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
+-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
+-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
+-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
+-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
+-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
+--
+-- Version History
+-- Version 1.0 7/23/2010 Scott Larson
+-- Initial Public Release
+-- Version 1.1 4/11/2013 Scott Larson
+-- Corrected ModelSim simulation error (explicitly reset clk_toggles signal)
+--
+--------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY spi_master IS
+ GENERIC(
+ slaves : INTEGER := 4; --number of spi slaves
+ d_width : INTEGER := 2); --data bus width
+ PORT(
+ clock : IN STD_LOGIC; --system clock
+ reset_n : IN STD_LOGIC; --asynchronous reset
+ enable : IN STD_LOGIC; --initiate transaction
+ cpol : IN STD_LOGIC; --spi clock polarity
+ cpha : IN STD_LOGIC; --spi clock phase
+ cont : IN STD_LOGIC; --continuous mode command
+ clk_div : IN INTEGER; --system clock cycles per 1/2 period of sclk
+ addr : IN INTEGER; --address of slave
+ tx_data : IN STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --data to transmit
+ miso : IN STD_LOGIC; --master in, slave out
+ sclk : BUFFER STD_LOGIC; --spi clock
+ ss_n : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0); --slave select
+ mosi : OUT STD_LOGIC; --master out, slave in
+ busy : OUT STD_LOGIC; --busy / data ready signal
+ rx_data : OUT STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
+END spi_master;
+
+ARCHITECTURE logic OF spi_master IS
+ TYPE machine IS(ready, execute); --state machine data type
+ SIGNAL state : machine; --current state
+ SIGNAL slave : INTEGER; --slave selected for current transaction
+ SIGNAL clk_ratio : INTEGER; --current clk_div
+ SIGNAL count : INTEGER; --counter to trigger sclk from system clock
+ SIGNAL clk_toggles : INTEGER RANGE 0 TO d_width*2 + 1; --count spi clock toggles
+ SIGNAL assert_data : STD_LOGIC; --'1' is tx sclk toggle, '0' is rx sclk toggle
+ SIGNAL continue : STD_LOGIC; --flag to continue transaction
+ SIGNAL rx_buffer : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --receive data buffer
+ SIGNAL tx_buffer : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --transmit data buffer
+ SIGNAL last_bit_rx : INTEGER RANGE 0 TO d_width*2; --last rx data bit location
+BEGIN
+ PROCESS(clock, reset_n)
+ BEGIN
+
+ IF(reset_n = '0') THEN --reset system
+ busy <= '1'; --set busy signal
+ ss_n <= (OTHERS => '1'); --deassert all slave select lines
+ mosi <= 'Z'; --set master out to high impedance
+ rx_data <= (OTHERS => '0'); --clear receive data port
+ state <= ready; --go to ready state when reset is exited
+
+ ELSIF(rising_edge(clock)) THEN
+ CASE state IS --state machine
+
+ WHEN ready =>
+ busy <= '0'; --clock out not busy signal
+ ss_n <= (OTHERS => '1'); --set all slave select outputs high
+ mosi <= 'Z'; --set mosi output high impedance
+ continue <= '0'; --clear continue flag
+
+ --user input to initiate transaction
+ IF(enable = '1') THEN
+ busy <= '1'; --set busy signal
+ IF(addr < slaves) THEN --check for valid slave address
+ slave <= addr; --clock in current slave selection if valid
+ ELSE
+ slave <= 0; --set to first slave if not valid
+ END IF;
+ IF(clk_div = 0) THEN --check for valid spi speed
+ clk_ratio <= 1; --set to maximum speed if zero
+ count <= 1; --initiate system-to-spi clock counter
+ ELSE
+ clk_ratio <= clk_div; --set to input selection if valid
+ count <= clk_div; --initiate system-to-spi clock counter
+ END IF;
+ sclk <= cpol; --set spi clock polarity
+ assert_data <= NOT cpha; --set spi clock phase
+ tx_buffer <= tx_data; --clock in data for transmit into buffer
+ clk_toggles <= 0; --initiate clock toggle counter
+ last_bit_rx <= d_width*2 + conv_integer(cpha) - 1; --set last rx data bit
+ state <= execute; --proceed to execute state
+ ELSE
+ state <= ready; --remain in ready state
+ END IF;
+
+ WHEN execute =>
+ busy <= '1'; --set busy signal
+ ss_n(slave) <= '0'; --set proper slave select output
+
+ --system clock to sclk ratio is met
+ IF(count = clk_ratio) THEN
+ count <= 1; --reset system-to-spi clock counter
+ assert_data <= NOT assert_data; --switch transmit/receive indicator
+ IF(clk_toggles = d_width*2 + 1) THEN
+ clk_toggles <= 0; --reset spi clock toggles counter
+ ELSE
+ clk_toggles <= clk_toggles + 1; --increment spi clock toggles counter
+ END IF;
+
+ --spi clock toggle needed
+ IF(clk_toggles <= d_width*2 AND ss_n(slave) = '0') THEN
+ sclk <= NOT sclk; --toggle spi clock
+ END IF;
+
+ --receive spi clock toggle
+ IF(assert_data = '0' AND clk_toggles < last_bit_rx + 1 AND ss_n(slave) = '0') THEN
+ rx_buffer <= rx_buffer(d_width-2 DOWNTO 0) & miso; --shift in received bit
+ END IF;
+
+ --transmit spi clock toggle
+ IF(assert_data = '1' AND clk_toggles < last_bit_rx) THEN
+ mosi <= tx_buffer(d_width-1); --clock out data bit
+ tx_buffer <= tx_buffer(d_width-2 DOWNTO 0) & '0'; --shift data transmit buffer
+ END IF;
+
+ --last data receive, but continue
+ IF(clk_toggles = last_bit_rx AND cont = '1') THEN
+ tx_buffer <= tx_data; --reload transmit buffer
+ clk_toggles <= last_bit_rx - d_width*2 + 1; --reset spi clock toggle counter
+ continue <= '1'; --set continue flag
+ END IF;
+
+ --normal end of transaction, but continue
+ IF(continue = '1') THEN
+ continue <= '0'; --clear continue flag
+ busy <= '0'; --clock out signal that first receive data is ready
+ rx_data <= rx_buffer; --clock out received data to output port
+ END IF;
+
+ --end of transaction
+ IF((clk_toggles = d_width*2 + 1) AND cont = '0') THEN
+ busy <= '0'; --clock out not busy signal
+ ss_n <= (OTHERS => '1'); --set all slave selects high
+ mosi <= 'Z'; --set mosi output high impedance
+ rx_data <= rx_buffer; --clock out received data to output port
+ state <= ready; --return to ready state
+ ELSE --not end of transaction
+ state <= execute; --remain in execute state
+ END IF;
+
+ ELSE --system clock to sclk ratio not met
+ count <= count + 1; --increment counter
+ state <= execute; --remain in execute state
+ END IF;
+
+ END CASE;
+ END IF;
+ END PROCESS;
+END logic;
diff --git a/memorydump_93LC46/tb_top.vhd b/memorydump_93LC46/tb_top.vhd
new file mode 100755
index 0000000..ccb6519
--- /dev/null
+++ b/memorydump_93LC46/tb_top.vhd
@@ -0,0 +1,118 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:20:50 03/18/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/memorydump_93LC46/tb_top.vhd
+-- Project Name: memorydump_93LC46
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE WORK.p_constants.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_top IS
+END tb_top;
+
+ARCHITECTURE behavior OF tb_top IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT top
+ GENERIC(
+ G_BOARD_CLOCK : integer := G_BOARD_CLOCK_SIMULATE;
+ G_BAUD_RATE : integer := G_BAUD_RATE
+ );
+ PORT(
+ i_clock : IN std_logic;
+ i_reset : IN std_logic;
+ o_cs : OUT std_logic;
+ o_sk : OUT std_logic;
+ o_di : OUT std_logic;
+ i_do : IN std_logic;
+ o_RsTx : OUT std_logic;
+ i_RsRx : IN std_logic
+ );
+ END COMPONENT;
+
+ --Inputs
+ signal i_clock : std_logic := '0';
+ signal i_reset : std_logic := '0';
+ signal i_do : std_logic := 'Z';
+ signal i_RsRx : std_logic := '0';
+
+ --Outputs
+ signal o_cs : std_logic;
+ signal o_sk : std_logic;
+ signal o_di : std_logic;
+ signal o_RsTx : std_logic;
+
+ -- Clock period definitions
+ constant i_clock_period : time := (1_000_000_000/G_BOARD_CLOCK_SIMULATE) * 1 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: top
+ GENERIC MAP (
+ G_BOARD_CLOCK => G_BOARD_CLOCK_SIMULATE,
+ G_BAUD_RATE => G_BAUD_RATE
+ )
+ PORT MAP (
+ i_clock => i_clock,
+ i_reset => i_reset,
+ o_cs => o_cs,
+ o_sk => o_sk,
+ o_di => o_di,
+ i_do => i_do,
+ o_RsTx => o_RsTx,
+ i_RsRx => i_RsRx
+ );
+
+ -- Clock process definitions
+ i_clock_process : process
+ begin
+ i_clock <= '0';
+ wait for i_clock_period/2;
+ i_clock <= '1';
+ wait for i_clock_period/2;
+ end process;
+
+ i_reset <= '1', '0' after i_clock_period;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- insert stimulus here
+-- wait for 2001.45 ms + 250 ns; -- XXX use flag
+-- i_do <= '0';
+-- wait for 4*G_BOARD_CLOCK_SIMULATE*i_clock_period; -- XXX catch the ready on do pin
+-- i_do <= '1';
+-- wait for 200 ns + 1100 ns; -- XXX to re CLK
+-- i_do <= 'Z';
+ wait;
+ end process;
+
+END;
diff --git a/memorydump_93LC46/tb_top.wcfg b/memorydump_93LC46/tb_top.wcfg
new file mode 100755
index 0000000..ecb1b46
--- /dev/null
+++ b/memorydump_93LC46/tb_top.wcfg
@@ -0,0 +1,483 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ tb
+ label
+
+ o_cs
+ o_cs
+
+
+ o_sk
+ o_sk
+
+
+ o_di
+ o_di
+
+
+ i_do
+ i_do
+
+
+ i_clock
+ i_clock
+
+
+ i_reset
+ i_reset
+
+
+ i_rsrx
+ i_rsrx
+
+
+ o_rstx
+ o_rstx
+
+
+ i_clock_period
+ i_clock_period
+
+
+
+ uut
+ label
+
+ i_clock
+ i_clock
+
+
+ i_reset
+ i_reset
+
+
+ memory_address[6:0]
+ memory_address[6:0]
+ HEXRADIX
+
+
+ o_cs
+ o_cs
+
+
+ o_sk
+ o_sk
+
+
+ o_di
+ o_di
+
+
+ i_do
+ i_do
+
+
+ o_rstx
+ o_rstx
+
+
+ i_rsrx
+ i_rsrx
+
+
+ state
+ state
+
+
+ rs232_enable_tx
+ rs232_enable_tx
+
+
+ rs232_enable_rx
+ rs232_enable_rx
+
+
+ rs232_busy
+ rs232_busy
+
+
+ rs232_ready
+ rs232_ready
+
+
+ rs232_is_byte_received
+ rs232_is_byte_received
+
+
+ rs232_byte_to_send[7:0]
+ rs232_byte_to_send[7:0]
+
+
+ rs232_byte_received[7:0]
+ rs232_byte_received[7:0]
+
+
+ cd_o_clock
+ cd_o_clock
+
+
+ cd_o_clock_prev
+ cd_o_clock_prev
+
+
+ cs
+ cs
+
+
+ sk
+ sk
+
+
+ di
+ di
+
+
+ do
+ do
+
+
+ memory_address_index
+ memory_address_index
+
+
+ memory_data[7:0]
+ memory_data[7:0]
+
+
+ memory_data_index
+ memory_data_index
+
+
+ tw_index
+ tw_index
+
+
+ tw_v_wait1[31:0]
+ tw_v_wait1[31:0]
+
+
+ tw_memory_data_1[1:0]
+ tw_memory_data_1[1:0]
+
+
+ tw_memory_address_1[1:0]
+ tw_memory_address_1[1:0]
+
+
+ index
+ index
+
+
+ enable
+ enable
+
+
+ cpol
+ cpol
+
+
+ cpha
+ cpha
+
+
+ cont
+ cont
+
+
+ miso
+ miso
+
+
+ sclk
+ sclk
+
+
+ mosi
+ mosi
+
+
+ busy
+ busy
+
+
+ addr
+ addr
+
+
+ tx_data[1:0]
+ tx_data[1:0]
+
+
+ rx_data[1:0]
+ rx_data[1:0]
+
+
+ ss_n[0:0]
+ ss_n[0:0]
+
+
+ g_board_clock
+ g_board_clock
+
+
+ g_baud_rate
+ g_baud_rate
+
+
+ tw_c_wait1
+ tw_c_wait1
+
+
+ sw
+ sw
+
+
+
+ rs232
+ label
+
+ clk
+ clk
+
+
+ rst
+ rst
+
+
+ enable_tx
+ enable_tx
+
+
+ enable_rx
+ enable_rx
+
+
+ byte_to_send[7:0]
+ byte_to_send[7:0]
+
+
+ byte_received[7:0]
+ byte_received[7:0]
+
+
+ busy
+ busy
+
+
+ ready
+ ready
+
+
+ is_byte_received
+ is_byte_received
+
+
+ rstx
+ rstx
+
+
+ rsrx
+ rsrx
+
+
+ v_i[31:0]
+ v_i[31:0]
+
+
+ v_w[31:0]
+ v_w[31:0]
+
+
+ t_w[31:0]
+ t_w[31:0]
+
+
+ temp[9:0]
+ temp[9:0]
+
+
+ c_state
+ c_state
+
+
+ r_state
+ r_state
+
+
+ g_board_clock
+ g_board_clock
+
+
+ g_baud_rate
+ g_baud_rate
+
+
+ recv_bits
+ recv_bits
+
+
+ a
+ a
+
+
+
+ clkdiv
+ label
+
+ i_reset
+ i_reset
+
+
+ i_clock
+ i_clock
+
+
+ o_clock
+ o_clock
+
+
+ g_board_clock
+ g_board_clock
+
+
+ g_divider
+ g_divider
+
+
+
+ spim
+ label
+
+ clock
+ clock
+
+
+ reset_n
+ reset_n
+
+
+ enable
+ enable
+
+
+ cpol
+ cpol
+
+
+ cpha
+ cpha
+
+
+ cont
+ cont
+
+
+ clk_div
+ clk_div
+
+
+ addr
+ addr
+
+
+ tx_data[1:0]
+ tx_data[1:0]
+
+
+ miso
+ miso
+
+
+ sclk
+ sclk
+
+
+ ss_n[0:0]
+ ss_n[0:0]
+
+
+ mosi
+ mosi
+
+
+ busy
+ busy
+
+
+ rx_data[1:0]
+ rx_data[1:0]
+
+
+ state
+ state
+
+
+ slave
+ slave
+
+
+ clk_ratio
+ clk_ratio
+
+
+ count
+ count
+
+
+ clk_toggles
+ clk_toggles
+
+
+ assert_data
+ assert_data
+
+
+ continue
+ continue
+
+
+ rx_buffer[1:0]
+ rx_buffer[1:0]
+
+
+ tx_buffer[1:0]
+ tx_buffer[1:0]
+
+
+ last_bit_rx
+ last_bit_rx
+
+
+ slaves
+ slaves
+
+
+ d_width
+ d_width
+
+
+
diff --git a/memorydump_93LC46/tb_top_digikeyspi.vhd b/memorydump_93LC46/tb_top_digikeyspi.vhd
new file mode 100755
index 0000000..0c727a2
--- /dev/null
+++ b/memorydump_93LC46/tb_top_digikeyspi.vhd
@@ -0,0 +1,118 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:20:50 03/18/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/memorydump_93LC46/tb_top.vhd
+-- Project Name: memorydump_93LC46
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE WORK.p_constants.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_top_digikeyspi IS
+END tb_top_digikeyspi;
+
+ARCHITECTURE behavior OF tb_top_digikeyspi IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT top_digikeyspi
+ GENERIC(
+ G_BOARD_CLOCK : integer := G_BOARD_CLOCK_SIMULATE;
+ G_BAUD_RATE : integer := G_BAUD_RATE
+ );
+ PORT(
+ i_clock : IN std_logic;
+ i_reset : IN std_logic;
+ o_cs : OUT std_logic;
+ o_sk : OUT std_logic;
+ o_di : OUT std_logic;
+ i_do : IN std_logic;
+ o_RsTx : OUT std_logic;
+ i_RsRx : IN std_logic
+ );
+ END COMPONENT;
+
+ --Inputs
+ signal i_clock : std_logic := '0';
+ signal i_reset : std_logic := '0';
+ signal i_do : std_logic := 'Z';
+ signal i_RsRx : std_logic := '0';
+
+ --Outputs
+ signal o_cs : std_logic;
+ signal o_sk : std_logic;
+ signal o_di : std_logic;
+ signal o_RsTx : std_logic;
+
+ -- Clock period definitions
+ constant i_clock_period : time := (1_000_000_000/G_BOARD_CLOCK_SIMULATE) * 1 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: top_digikeyspi
+ GENERIC MAP (
+ G_BOARD_CLOCK => G_BOARD_CLOCK_SIMULATE,
+ G_BAUD_RATE => G_BAUD_RATE
+ )
+ PORT MAP (
+ i_clock => i_clock,
+ i_reset => i_reset,
+ o_cs => o_cs,
+ o_sk => o_sk,
+ o_di => o_di,
+ i_do => i_do,
+ o_RsTx => o_RsTx,
+ i_RsRx => i_RsRx
+ );
+
+ -- Clock process definitions
+ i_clock_process : process
+ begin
+ i_clock <= '0';
+ wait for i_clock_period/2;
+ i_clock <= '1';
+ wait for i_clock_period/2;
+ end process;
+
+ i_reset <= '1', '0' after i_clock_period;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- insert stimulus here
+-- wait for 2001.45 ms + 250 ns; -- XXX use flag
+-- i_do <= '0';
+-- wait for 4*G_BOARD_CLOCK_SIMULATE*i_clock_period; -- XXX catch the ready on do pin
+-- i_do <= '1';
+-- wait for 200 ns + 1100 ns; -- XXX to re CLK
+-- i_do <= 'Z';
+ wait;
+ end process;
+
+END;
diff --git a/memorydump_93LC46/tb_top_digikeyspi.wcfg b/memorydump_93LC46/tb_top_digikeyspi.wcfg
new file mode 100755
index 0000000..16c443b
--- /dev/null
+++ b/memorydump_93LC46/tb_top_digikeyspi.wcfg
@@ -0,0 +1,474 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ tb
+ label
+
+ i_clock
+ i_clock
+
+
+ i_reset
+ i_reset
+
+
+ i_do
+ i_do
+
+
+ i_rsrx
+ i_rsrx
+
+
+ o_cs
+ o_cs
+
+
+ o_sk
+ o_sk
+
+
+ o_di
+ o_di
+
+
+ o_rstx
+ o_rstx
+
+
+ i_clock_period
+ i_clock_period
+
+
+
+ top
+ label
+
+ i_clock
+ i_clock
+
+
+ i_reset
+ i_reset
+
+
+ o_cs
+ o_cs
+
+
+ o_sk
+ o_sk
+
+
+ o_di
+ o_di
+
+
+ i_do
+ i_do
+
+
+ o_rstx
+ o_rstx
+
+
+ i_rsrx
+ i_rsrx
+
+
+ state
+ state
+
+
+ rs232_enable_tx
+ rs232_enable_tx
+
+
+ rs232_enable_rx
+ rs232_enable_rx
+
+
+ rs232_busy
+ rs232_busy
+
+
+ rs232_ready
+ rs232_ready
+
+
+ rs232_is_byte_received
+ rs232_is_byte_received
+
+
+ rs232_byte_to_send[7:0]
+ rs232_byte_to_send[7:0]
+
+
+ rs232_byte_received[7:0]
+ rs232_byte_received[7:0]
+
+
+ cd_o_clock
+ cd_o_clock
+
+
+ cd_o_clock_prev
+ cd_o_clock_prev
+
+
+ cs
+ cs
+
+
+ sk
+ sk
+
+
+ di
+ di
+
+
+ do
+ do
+
+
+ memory_address[6:0]
+ memory_address[6:0]
+
+
+ memory_address_index
+ memory_address_index
+
+
+ memory_data[7:0]
+ memory_data[7:0]
+
+
+ memory_data_index
+ memory_data_index
+
+
+ tw_index
+ tw_index
+
+
+ tw_v_wait1[31:0]
+ tw_v_wait1[31:0]
+
+
+ tw_memory_data_1[1:0]
+ tw_memory_data_1[1:0]
+
+
+ tw_memory_address_1[1:0]
+ tw_memory_address_1[1:0]
+
+
+ index
+ index
+
+
+ enable
+ enable
+
+
+ cpol
+ cpol
+
+
+ cpha
+ cpha
+
+
+ cont
+ cont
+
+
+ miso
+ miso
+
+
+ sclk
+ sclk
+
+
+ mosi
+ mosi
+
+
+ busy
+ busy
+
+
+ addr
+ addr
+
+
+ tx_data[1:0]
+ tx_data[1:0]
+
+
+ rx_data[1:0]
+ rx_data[1:0]
+
+
+ ss_n[0:0]
+ ss_n[0:0]
+
+
+ g_board_clock
+ g_board_clock
+
+
+ g_baud_rate
+ g_baud_rate
+
+
+ tw_c_wait1
+ tw_c_wait1
+
+
+ sw
+ sw
+
+
+
+ spim
+ label
+
+ clock
+ clock
+
+
+ reset_n
+ reset_n
+
+
+ enable
+ enable
+
+
+ cpol
+ cpol
+
+
+ cpha
+ cpha
+
+
+ cont
+ cont
+
+
+ clk_div
+ clk_div
+
+
+ addr
+ addr
+
+
+ tx_data[1:0]
+ tx_data[1:0]
+
+
+ miso
+ miso
+
+
+ sclk
+ sclk
+
+
+ ss_n[0:0]
+ ss_n[0:0]
+
+
+ mosi
+ mosi
+
+
+ busy
+ busy
+
+
+ rx_data[1:0]
+ rx_data[1:0]
+
+
+ state
+ state
+
+
+ slave
+ slave
+
+
+ clk_ratio
+ clk_ratio
+
+
+ count
+ count
+
+
+ clk_toggles
+ clk_toggles
+
+
+ assert_data
+ assert_data
+
+
+ continue
+ continue
+
+
+ rx_buffer[1:0]
+ rx_buffer[1:0]
+
+
+ tx_buffer[1:0]
+ tx_buffer[1:0]
+
+
+ last_bit_rx
+ last_bit_rx
+
+
+ slaves
+ slaves
+
+
+ d_width
+ d_width
+
+
+
+ rs232
+ label
+
+ clk
+ clk
+
+
+ rst
+ rst
+
+
+ enable_tx
+ enable_tx
+
+
+ enable_rx
+ enable_rx
+
+
+ byte_to_send[7:0]
+ byte_to_send[7:0]
+
+
+ byte_received[7:0]
+ byte_received[7:0]
+
+
+ busy
+ busy
+
+
+ ready
+ ready
+
+
+ is_byte_received
+ is_byte_received
+
+
+ rstx
+ rstx
+
+
+ rsrx
+ rsrx
+
+
+ v_i[31:0]
+ v_i[31:0]
+
+
+ v_w[31:0]
+ v_w[31:0]
+
+
+ t_w[31:0]
+ t_w[31:0]
+
+
+ temp[9:0]
+ temp[9:0]
+
+
+ c_state
+ c_state
+
+
+ r_state
+ r_state
+
+
+ g_board_clock
+ g_board_clock
+
+
+ g_baud_rate
+ g_baud_rate
+
+
+ recv_bits
+ recv_bits
+
+
+ a
+ a
+
+
+
+ clkdiv
+ label
+
+ i_reset
+ i_reset
+
+
+ i_clock
+ i_clock
+
+
+ o_clock
+ o_clock
+
+
+ g_board_clock
+ g_board_clock
+
+
+ g_divider
+ g_divider
+
+
+
diff --git a/memorydump_93LC46/top.vhd b/memorydump_93LC46/top.vhd
new file mode 100755
index 0000000..c7c13ed
--- /dev/null
+++ b/memorydump_93LC46/top.vhd
@@ -0,0 +1,621 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:40:48 03/18/2021
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_constants.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top is
+Generic (
+ G_BOARD_CLOCK : integer := G_BOARD_CLOCK_HARDWARE;
+ G_BAUD_RATE : integer := G_BAUD_RATE
+);
+Port (
+ i_clock : in STD_LOGIC;
+ i_reset : in STD_LOGIC;
+ o_cs : out STD_LOGIC;
+ o_sk : out STD_LOGIC;
+ o_di : out STD_LOGIC;
+ i_do : in STD_LOGIC;
+ o_RsTx : out STD_LOGIC;
+ i_RsRx : in STD_LOGIC
+);
+end top;
+
+architecture Behavioral of top is
+
+ COMPONENT rs232 IS
+ Generic (
+ G_BOARD_CLOCK : integer := G_BOARD_CLOCK;
+ G_BAUD_RATE : integer := G_BAUD_RATE
+ );
+ Port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ enable_tx : in STD_LOGIC;
+ enable_rx : in STD_LOGIC;
+ byte_to_send : in MemoryDataByte;
+ byte_received : out MemoryDataByte;
+ busy : out STD_LOGIC;
+ ready : out STD_LOGIC;
+ is_byte_received : out STD_LOGIC;
+ RsTx : out STD_LOGIC;
+ RsRx : in STD_LOGIC
+ );
+ END COMPONENT rs232;
+
+ COMPONENT clock_divider_count IS
+ Generic (
+ g_board_clock : integer := G_BOARD_CLOCK;
+ g_divider : integer := 1
+ );
+ Port (
+ i_reset : in STD_LOGIC;
+ i_clock : in STD_LOGIC;
+ i_enable : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+ );
+ END COMPONENT clock_divider_count;
+
+ type state_type is (
+ some_wait,
+ start,
+
+ tw_di0,tw_di1,tw_di2,tw_di3,tw_di4, -- send EWEN
+ tw_disable_cs,tw_disable_cs_wait,tw_wait1,tw_enable_cs,
+
+ tv_di0,tv_di1,tv_di2,tv_address,tv_address_increment,tv_data,tv_data_increment, -- write at
+ tv_disable_cs,tv_disable_cs_wait,tv_wait2,tv_enable_cs,tv_enable_cs1,tv_enable_cs_clk,tv_wait1,tv_disable_cs1,tv_wait3, -- in tv_wait1 check the READY/bBUSY
+
+ tu_enable_cs1,tu_di0,tu_di1,tu_di2,tu_di3,tu_di4, -- send EWDS
+ tu_disable_cs,tu_wait1,tu_enable_cs,tu_enable_cs_clk,
+
+ di0,di1,di2,
+ di_address,
+ do_data,
+ di_set_di2,
+ st_rs232_enable_tx,
+ st_rs232_ready,
+ st_rs232_send,
+ st_rs232_waiting,
+ st_rs232_disable_tx,
+ di_address_increment,
+ stop
+ );
+ signal state : state_type;
+
+ signal rs232_enable_tx,rs232_enable_rx,rs232_busy,rs232_ready,rs232_is_byte_received : std_logic;
+ signal rs232_byte_to_send,rs232_byte_received : MemoryDataByte;
+ signal cd_o_clock,cd_o_clock_prev,cd_i_enable : std_logic;
+ signal cs,sk,di,do : std_logic;
+ signal memory_address : MemoryAddress;
+ signal memory_address_index : integer range 0 to G_MemoryAddress-1;
+ signal memory_data : MemoryDataByte;
+ signal memory_data_index : integer range 0 to G_MemoryData-1;
+ constant TW_C_WAIT1 : integer := (4 * (G_BOARD_CLOCK/1000)); -- XXX 4ms
+ signal tw_index : integer;
+ signal tw_v_wait1 : std_logic_vector(31 downto 0);
+ signal tw_memory_data_1 : MemoryDataByte;
+ signal tw_memory_address_1 : MemoryAddress;
+
+ constant SW : integer := G_BOARD_CLOCK/5;
+ signal index : integer;
+
+begin
+
+ c_rs232 : rs232
+ GENERIC MAP (
+ G_BOARD_CLOCK => G_BOARD_CLOCK,
+ G_BAUD_RATE => G_BAUD_RATE
+ )
+ PORT MAP (
+ clk => i_clock,
+ rst => i_reset,
+ enable_tx => rs232_enable_tx,
+ enable_rx => rs232_enable_rx,
+ byte_to_send => rs232_byte_to_send,
+ byte_received => rs232_byte_received,
+ busy => rs232_busy,
+ ready => rs232_ready,
+ is_byte_received => rs232_is_byte_received,
+ RsTx => o_RsTx,
+ RsRx => i_RsRx
+ );
+
+ c_cd_div1 : clock_divider_count -- XXX SPI 1 MHZ
+ GENERIC MAP (
+ g_board_clock => G_BOARD_CLOCK,
+ g_divider => G_BOARD_CLOCK/G_CLOCK_DIV1
+ )
+ PORT MAP (
+ i_reset => i_reset,
+ i_clock => i_clock,
+ i_enable => '1',
+ o_clock => cd_o_clock
+ );
+
+ o_cs <= cs;
+ o_sk <= sk;
+ o_di <= di;
+
+ p0 : process (i_clock,i_reset) is
+ begin
+ if (i_reset = '1') then
+ index <= 0;
+ state <= some_wait;
+ cs <= '0';
+ di <= '0';
+ do <= 'Z';
+ memory_address <= (others => '0');
+ memory_address_index <= 0;
+ memory_data <= (others => '0');
+ memory_data_index <= 0;
+ tw_v_wait1 <= (others => '0');
+ tw_memory_data_1 <= x"FF";
+ tw_memory_address_1 <= "0000010";
+ elsif (rising_edge(i_clock)) then
+ cd_o_clock_prev <= cd_o_clock; -- wait for clock transition
+ sk <= cd_o_clock;
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ di <= '0';
+ end if;
+ case (state) is
+ when some_wait => -- wait
+ if (index = SW-1) then
+ state <= start;
+ index <= 0;
+ cd_i_enable <= '1';
+ --sk <= '0';
+ else
+ state <= some_wait;
+ index <= index + 1;
+ end if;
+ when start => -- start
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tw_di0;
+ --cs <= '1'; -- XXX CS
+ --cd_i_enable <= '1';
+ --sk <= '0';
+ else
+ state <= start;
+ end if;
+
+
+
+
+ when tw_di0 => -- send EWEN
+ cs <= '1'; -- XXX CS
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tw_di1;
+ di <= '1';
+ else
+ state <= tw_di0;
+ end if;
+ when tw_di1 =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tw_di2;
+ di <= '0';
+ else
+ state <= tw_di1;
+ end if;
+ when tw_di2 =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tw_di3;
+ di <= '0';
+ else
+ state <= tw_di2;
+ end if;
+ when tw_di3 =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tw_di4;
+ di <= '1';
+ else
+ state <= tw_di3;
+ end if;
+ when tw_di4 =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tw_disable_cs_wait;
+ --cs <= '0'; -- XXX CS
+ di <= '1';
+ else
+ state <= tw_di4;
+ end if;
+-- when tw_di5 =>
+-- if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+-- state <= tw_disable_cs;
+-- di <= '0';
+-- else
+-- state <= tw_di5;
+-- end if;
+ when tw_disable_cs_wait =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tw_disable_cs;
+ di <= '0';
+ else
+ state <= tw_disable_cs_wait;
+ end if;
+ when tw_disable_cs =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tw_wait1;
+ cs <= '0'; -- XXX CS
+ di <= '0';
+ cd_i_enable <= '0';
+ --sk <= '0';
+ else
+ state <= tw_disable_cs;
+ end if;
+ when tw_wait1 =>
+ if (index = TW_C_WAIT1-1) then
+ state <= tw_enable_cs;
+ cd_i_enable <= '1';
+ --sk <= '0';
+ index <= 0;
+ else
+ state <= tw_wait1;
+ index <= index + 1;
+ end if;
+ when tw_enable_cs =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tv_di0;
+ cs <= '1'; -- XXX CS
+ else
+ state <= tw_enable_cs;
+ end if;
+
+
+
+
+ when tv_di0 => -- write at
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tv_di1;
+ di <= '1';
+ else
+ state <= tv_di0;
+ end if;
+ when tv_di1 =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tv_di2;
+ di <= '0';
+ else
+ state <= tv_di1;
+ end if;
+ when tv_di2 =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tv_address;
+ di <= '1';
+ else
+ state <= tv_di2;
+ end if;
+ when tv_address =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ di <= tw_memory_address_1(memory_address_index);
+ state <= tv_address_increment;
+ else
+ state <= tv_address;
+ end if;
+ when tv_address_increment =>
+ if (memory_address_index = G_MemoryAddress - 1) then
+ state <= tv_data;
+ --di <= tw_memory_address(G_MemoryAddress - 1);
+ memory_address_index <= 0;
+ else
+ state <= tv_address;
+ memory_address_index <= memory_address_index + 1;
+ end if;
+ when tv_data =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ di <= tw_memory_data_1(memory_data_index);
+ state <= tv_data_increment;
+ else
+ state <= tv_data;
+ end if;
+ when tv_data_increment =>
+ if (memory_data_index = G_MemoryData - 1) then
+ state <= tv_disable_cs_wait;
+ --memory_data(G_MemoryData-1) <= i_do;
+ memory_data_index <= 0;
+ else
+ memory_data_index <= memory_data_index + 1;
+ state <= tv_data;
+ end if;
+ when tv_disable_cs_wait =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tv_disable_cs;
+ di <= '0';
+ else
+ state <= tv_disable_cs_wait;
+ end if;
+ when tv_disable_cs =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tv_enable_cs_clk;
+ --di <= tw_memory_data_1(G_MemoryData - 1);
+ cs <= '0'; -- XXX CS
+ --sk <= '0';
+ cd_i_enable <= '0';
+ else
+ state <= tv_disable_cs;
+ end if;
+
+
+ when tv_enable_cs_clk =>
+ state <= tv_enable_cs;
+ cd_i_enable <= '1';
+ when tv_enable_cs =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tv_wait1;
+ cs <= '1'; -- XXX CS
+ else
+ state <= tv_enable_cs;
+ end if;
+ when tv_wait1 => -- XXX check write
+ if (i_do = '1') then
+ state <= tv_disable_cs1;
+ elsif (i_do = '0' or i_do = 'Z') then
+ state <= tv_wait1;
+ end if;
+-- if (to_integer(unsigned(tw_v_wait1)) = SW-1) then
+-- state <= tv_enable_cs;
+-- tw_v_wait1 <= (others => '0');
+-- else
+-- state <= tv_wait1;
+-- tw_v_wait1 <= std_logic_vector(to_unsigned(to_integer(unsigned(tw_v_wait1)) + 1,32));
+-- end if;
+ when tv_disable_cs1 =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tv_wait3;
+ cs <= '0'; -- XXX CS
+ di <= '0';
+ cd_i_enable <= '0';
+ --sk <= '0';
+ else
+ state <= tv_disable_cs1;
+ end if;
+ when tv_wait3 =>
+ if (index = TW_C_WAIT1-1) then
+ state <= tv_wait2;
+ index <= 0;
+ cd_i_enable <= '1';
+ --sk <= '0';
+ else
+ state <= tv_wait3;
+ index <= index + 1;
+ end if;
+
+
+
+ when tv_wait2 =>
+ if (index = TW_C_WAIT1-1) then
+ state <= tu_enable_cs1;
+ cd_i_enable <= '1';
+ --sk <= '0';
+ index <= 0;
+ else
+ state <= tv_wait2;
+ index <= index + 1;
+ cd_i_enable <= '0';
+ --sk <= '0';
+ end if;
+
+
+
+ when tu_enable_cs1 =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tu_di0;
+ cs <= '1'; -- XXX CS
+
+ else
+ state <= tu_enable_cs1;
+ end if;
+ when tu_di0 => -- send EWDS
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tu_di1;
+ di <= '1';
+ else
+ state <= tu_di0;
+ end if;
+ when tu_di1 =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tu_di2;
+ di <= '0';
+ else
+ state <= tu_di1;
+ end if;
+ when tu_di2 =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tu_di3;
+ di <= '0';
+ else
+ state <= tu_di2;
+ end if;
+ when tu_di3 =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tu_di4;
+ di <= '0';
+ else
+ state <= tu_di3;
+ end if;
+ when tu_di4 =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tu_disable_cs;
+ di <= '0';
+ else
+ state <= tu_di4;
+ end if;
+-- when tu_di5 =>
+-- if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+-- state <= tu_disable_cs;
+-- di <= '0';
+-- else
+-- state <= tu_di5;
+-- end if;
+ when tu_disable_cs =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= tu_wait1;
+ cs <= '0'; -- XXX CS
+ di <= '0';
+ cd_i_enable <= '0';
+ --sk <= '0';
+ else
+ state <= tu_disable_cs;
+ end if;
+ when tu_wait1 =>
+ if (index = TW_C_WAIT1-1) then
+ state <= tu_enable_cs_clk;
+ index <= 0;
+ --sk <= '0';
+ else
+ state <= tu_wait1;
+ index <= index + 1;
+ end if;
+ when tu_enable_cs_clk =>
+ state <= tu_enable_cs;
+ cd_i_enable <= '1';
+ when tu_enable_cs =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= di0;
+ cs <= '1'; -- XXX CS
+ else
+ state <= tu_enable_cs;
+ end if;
+
+
+
+
+ when di0 => -- read and send
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= di1;
+ di <= '1';
+ else
+ state <= di0;
+ end if;
+ when di1 =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= di2;
+ di <= '1';
+ else
+ state <= di1;
+ end if;
+ when di2 =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= di_address;
+ di <= '0';
+ else
+ state <= di2;
+ end if;
+ when di_address =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ if (memory_address_index = G_MemoryAddress - 1) then
+ state <= do_data;
+ di <= memory_address(G_MemoryAddress - 1);
+ memory_address_index <= 0;
+ else
+ state <= di_address;
+ di <= memory_address(memory_address_index);
+ memory_address_index <= memory_address_index + 1;
+ end if;
+ else
+ state <= di_address;
+ end if;
+-- when di_set_di1 =>
+-- if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+-- state <= do_data;
+-- di <= '0';
+-- else
+-- state <= di_set_di1;
+-- end if;
+ when do_data =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ if (memory_data_index = G_MemoryData - 1) then
+ state <= di_set_di2;
+ --memory_data(G_MemoryData-1) <= i_do;
+ memory_data_index <= 0;
+ else
+ memory_data(G_MemoryData-1 downto 0) <= memory_data(G_MemoryData-2 downto 0) & i_do;
+ memory_data_index <= memory_data_index + 1;
+ end if;
+ else
+ state <= do_data;
+ end if;
+ when di_set_di2 =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ state <= st_rs232_enable_tx;
+ cs <= '0';
+ cd_i_enable <= '0';
+ --sk <= '0';
+ else
+ state <= di_set_di2;
+ end if;
+ when st_rs232_enable_tx =>
+ state <= st_rs232_ready;
+ cd_i_enable <= '0';
+ rs232_enable_tx <= '1';
+ when st_rs232_ready =>
+ if (rs232_ready = '1') then
+ state <= st_rs232_send;
+ --rs232_byte_to_send <= not ('0' & memory_address); -- XXX for tb
+ rs232_byte_to_send <= not memory_data;
+ else
+ state <= st_rs232_ready;
+ end if;
+ when st_rs232_send =>
+ if (rs232_ready = '0') then
+ state <= st_rs232_waiting;
+ else
+ state <= st_rs232_send;
+ end if;
+ when st_rs232_waiting =>
+ if (rs232_busy = '1') then
+ state <= st_rs232_waiting;
+ else
+ state <= st_rs232_disable_tx;
+ end if;
+ when st_rs232_disable_tx =>
+ state <= di_address_increment;
+ rs232_enable_tx <= '0';
+ when di_address_increment =>
+ if (memory_address = std_logic_vector(to_unsigned(to_integer(unsigned(MemoryAddressMAX)),G_MemoryAddress))) then
+ state <= stop;
+ else
+ memory_address <= std_logic_vector(to_unsigned(to_integer(unsigned(memory_address) + 1),G_MemoryAddress));
+ state <= tu_enable_cs_clk; -- XXX tu_disable_cs , di_set_di1 - omit the addresses
+ --cd_i_enable <= '1';
+ --sk <= '0';
+ end if;
+ when stop =>
+ if (cd_o_clock_prev = '0' and cd_o_clock = '1') then
+ cs <= '0'; -- XXX CS
+ di <= '0';
+ cd_i_enable <= '0';
+ --sk <= '0';
+ end if;
+ when others => null;
+ end case;
+ end if;
+ end process p0;
+
+end Behavioral;
diff --git a/memorydump_93LC46/top_digikeyspi.vhd b/memorydump_93LC46/top_digikeyspi.vhd
new file mode 100755
index 0000000..668a241
--- /dev/null
+++ b/memorydump_93LC46/top_digikeyspi.vhd
@@ -0,0 +1,649 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:40:48 03/18/2021
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_constants.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top_digikeyspi is
+Generic (
+ G_BOARD_CLOCK : integer := G_BOARD_CLOCK_HARDWARE;
+ G_BAUD_RATE : integer := G_BAUD_RATE
+);
+Port (
+ i_clock : in STD_LOGIC;
+ i_reset : in STD_LOGIC;
+ o_cs : out STD_LOGIC;
+ o_sk : out STD_LOGIC;
+ o_di : out STD_LOGIC;
+ i_do : in STD_LOGIC;
+ o_RsTx : out STD_LOGIC;
+ i_RsRx : in STD_LOGIC
+);
+end top_digikeyspi;
+
+architecture Behavioral of top_digikeyspi is
+
+ COMPONENT rs232 IS
+ Generic (
+ G_BOARD_CLOCK : integer := G_BOARD_CLOCK;
+ G_BAUD_RATE : integer := G_BAUD_RATE
+ );
+ Port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ enable_tx : in STD_LOGIC;
+ enable_rx : in STD_LOGIC;
+ byte_to_send : in MemoryDataByte;
+ byte_received : out MemoryDataByte;
+ busy : out STD_LOGIC;
+ ready : out STD_LOGIC;
+ is_byte_received : out STD_LOGIC;
+ RsTx : out STD_LOGIC;
+ RsRx : in STD_LOGIC
+ );
+ END COMPONENT rs232;
+
+ COMPONENT clock_divider_count IS
+ Generic (
+ g_board_clock : integer := G_BOARD_CLOCK;
+ g_divider : integer := 1
+ );
+ Port (
+ i_reset : in STD_LOGIC;
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+ );
+ END COMPONENT clock_divider_count;
+
+ COMPONENT spi_master IS
+ GENERIC(
+ slaves : INTEGER := slaves; --number of spi slaves
+ d_width : INTEGER := d_width); --data bus width
+ PORT(
+ clock : IN STD_LOGIC; --system clock
+ reset_n : IN STD_LOGIC; --asynchronous reset
+ enable : IN STD_LOGIC; --initiate transaction
+ cpol : IN STD_LOGIC; --spi clock polarity
+ cpha : IN STD_LOGIC; --spi clock phase
+ cont : IN STD_LOGIC; --continuous mode command
+ clk_div : IN INTEGER; --system clock cycles per 1/2 period of sclk
+ addr : IN INTEGER; --address of slave
+ tx_data : IN STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --data to transmit
+ miso : IN STD_LOGIC; --master in, slave out
+ sclk : BUFFER STD_LOGIC; --spi clock
+ ss_n : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0); --slave select
+ mosi : OUT STD_LOGIC; --master out, slave in
+ busy : OUT STD_LOGIC; --busy / data ready signal
+ rx_data : OUT STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
+ END COMPONENT spi_master;
+
+ type state_type is (
+ some_wait,
+
+ w_start_ewen,
+ w_send_ewen_1,w_send_ewen_2,w_send_ewen_3,w_send_ewen_4,w_send_ewen_5,
+ w_wait_ewen_1,w_wait_ewen_2,w_wait_ewen_3,w_wait_ewen_4,w_wait_ewen_5,
+ w_stop_ewen,w_stop_ewen_busy,
+ w_verify_on,w_verify,w_verify_off,
+ wait1a,
+
+ w_start_ewds,
+ w_send_ewds_1,w_send_ewds_2,w_send_ewds_3,w_send_ewds_4,w_send_ewds_5,
+ w_wait_ewds_1,w_wait_ewds_2,w_wait_ewds_3,w_wait_ewds_4,w_wait_ewds_5,
+ w_stop_ewds,w_stop_ewds_busy,
+
+ wait1b,
+
+ w_start,
+ w_send1,w_send2,w_send3,w_send4,w_send5,w_send6,w_send7,w_send8,w_send9,
+ w_wait1,w_wait2,w_wait3,w_wait4,w_wait5,w_wait6,w_wait7,w_wait8,w_wait9,
+ off,off_busy,
+
+ wait1c,
+
+ start,
+ send1,send2,send3,send4,send5,
+ wait1,wait2,wait3,wait4,wait5,
+ before_read_data,read_data,read_data_busy,
+ st_rs232_enable_tx,
+ st_rs232_ready,
+ st_rs232_busy,
+ st_rs232_send,
+ st_rs232_waiting,
+ st_rs232_disable_tx,
+ di_address_increment,
+
+ stop
+ );
+ signal state : state_type;
+
+ signal rs232_enable_tx,rs232_enable_rx,rs232_busy,rs232_ready,rs232_is_byte_received : std_logic;
+ signal rs232_byte_to_send,rs232_byte_received : MemoryDataByte;
+ signal cd_o_clock,cd_o_clock_prev : std_logic;
+ signal cs,sk,di,do : std_logic;
+ signal memory_address : MemoryAddress;
+ signal memory_address_index : integer range 0 to G_MemoryAddress-1;
+ signal memory_data : MemoryDataByte;
+ signal memory_data_index : integer range 0 to G_MemoryData-1;
+ constant TW_C_WAIT1 : integer := (4 * (G_BOARD_CLOCK/1000)); -- XXX 4ms
+ signal tw_index : integer;
+ signal tw_v_wait1 : std_logic_vector(31 downto 0);
+ signal tw_memory_data_1 : std_logic_vector(d_width-1 downto 0);
+ signal tw_memory_address_1 : std_logic_vector(d_width-1 downto 0);
+
+ constant SW : integer := TW_C_WAIT1; -- XXX some wait
+ signal index : integer;
+
+ signal enable,cpol,cpha,cont,miso,sclk,mosi,busy : std_logic;
+ signal addr : integer;
+ signal tx_data,rx_data : std_logic_vector(d_width-1 downto 0);
+ signal ss_n : std_logic_vector(slaves-1 downto 0);
+
+begin
+
+ p0 : process (i_clock,i_reset) is
+ begin
+ if (i_reset = '1') then
+ index <= 0;
+ state <= some_wait;
+ cs <= '0';
+ di <= '0';
+ do <= 'Z';
+ memory_address <= (others => '0');
+ memory_address_index <= 0;
+ memory_data <= (others => '0');
+ memory_data_index <= 0;
+ tw_v_wait1 <= (others => '0');
+ tw_memory_data_1 <= (others => '0');
+ tw_memory_address_1 <= (others => '0');
+ elsif (rising_edge(i_clock)) then
+ case (state) is
+ when some_wait => -- wait
+ if (index = SW-1) then
+ state <= w_start_ewen;
+ index <= 0;
+ else
+ state <= some_wait;
+ index <= index + 1;
+ end if;
+
+ when w_start_ewen => -- send ewen
+ state <= w_send_ewen_1;
+ enable <= '1';
+ --cpol <= '0';
+ --cpha <= '0';
+ addr <= 0;
+ cont <= '1';
+ when w_send_ewen_1 =>
+ state <= w_wait_ewen_1;
+ tw_memory_data_1 <= "10";
+ enable <= '1';
+ when w_wait_ewen_1 =>
+ if (busy = '1') then
+ state <= w_wait_ewen_1;
+ else
+ state <= w_send_ewen_2;
+ enable <= '0';
+ end if;
+ when w_send_ewen_2 =>
+ state <= w_wait_ewen_2;
+ tw_memory_data_1 <= "01";
+ enable <= '1';
+ when w_wait_ewen_2 =>
+ if (busy = '1') then
+ state <= w_wait_ewen_2;
+ else
+ state <= w_send_ewen_3;
+ enable <= '0';
+ end if;
+ when w_send_ewen_3 =>
+ state <= w_wait_ewen_3;
+ tw_memory_data_1 <= "1X";
+ enable <= '1';
+ when w_wait_ewen_3 =>
+ if (busy = '1') then
+ state <= w_wait_ewen_3;
+ else
+ state <= w_stop_ewen;
+ enable <= '0';
+ end if;
+ when w_stop_ewen =>
+ state <= w_stop_ewen_busy;
+ tw_memory_data_1 <= "00";
+ enable <= '0';
+ cont <= '0';
+ when w_stop_ewen_busy =>
+ if (busy = '1') then
+ state <= w_stop_ewen_busy;
+ else
+ state <= wait1a;
+ end if;
+
+ when wait1a => -- wait
+ if (index = SW-1) then
+ state <= w_start;
+ index <= 0;
+ else
+ state <= wait1a;
+ index <= index + 1;
+ end if;
+
+ when w_start => -- write at
+ state <= w_send1;
+ enable <= '1';
+ --cpol <= '0';
+ --cpha <= '0';
+ addr <= 0;
+ cont <= '1';
+ when w_send1 =>
+ state <= w_wait1;
+ tw_memory_data_1 <= "10";
+ enable <= '1';
+ when w_wait1 =>
+ if (busy = '1') then
+ state <= w_wait1;
+ else
+ state <= w_send2;
+ enable <= '0';
+ end if;
+ when w_send2 =>
+ state <= w_wait2;
+ tw_memory_data_1 <= "10";
+ enable <= '1';
+ when w_wait2 =>
+ if (busy = '1') then
+ state <= w_wait2;
+ else
+ state <= w_send3;
+ enable <= '0';
+ end if;
+ when w_send3 =>
+ state <= w_wait3;
+ tw_memory_data_1 <= "00";
+ enable <= '1';
+ when w_wait3 =>
+ if (busy = '1') then
+ state <= w_wait3;
+ else
+ state <= w_send4;
+ enable <= '0';
+ end if;
+ when w_send4 =>
+ state <= w_wait4;
+ tw_memory_data_1 <= "00";
+ enable <= '1';
+ when w_wait4 =>
+ if (busy = '1') then
+ state <= w_wait4;
+ else
+ state <= w_send5;
+ enable <= '0';
+ end if;
+ when w_send5 =>
+ state <= w_wait5;
+ tw_memory_data_1 <= "11"; -- XXX 3
+ enable <= '1';
+ when w_wait5 =>
+ if (busy = '1') then
+ state <= w_wait5;
+ else
+ state <= w_send6;
+ enable <= '0';
+ end if;
+ when w_send6 =>
+ state <= w_wait6;
+ tw_memory_data_1 <= "00";
+ enable <= '1';
+ when w_wait6 =>
+ if (busy = '1') then
+ state <= w_wait6;
+ else
+ state <= w_send7;
+ enable <= '0';
+ end if;
+ when w_send7 =>
+ state <= w_wait7;
+ tw_memory_data_1 <= "00";
+ enable <= '1';
+ when w_wait7 =>
+ if (busy = '1') then
+ state <= w_wait7;
+ else
+ state <= w_send8;
+ enable <= '0';
+ end if;
+ when w_send8 =>
+ state <= w_wait8;
+ tw_memory_data_1 <= "00";
+ enable <= '1';
+ when w_wait8 =>
+ if (busy = '1') then
+ state <= w_wait8;
+ else
+ state <= w_send9;
+ enable <= '0';
+ end if;
+ when w_send9 =>
+ state <= w_wait9;
+ tw_memory_data_1 <= "00";
+ enable <= '1';
+ when w_wait9 =>
+ if (busy = '1') then
+ state <= w_wait9;
+ else
+ state <= off;
+ end if;
+ when off =>
+ state <= off_busy;
+ --tw_memory_data_1 <= "00";
+ enable <= '0';
+ cont <= '0';
+ when off_busy =>
+ if (busy = '1') then
+ state <= off_busy;
+ else
+ state <= w_verify_on;
+ end if;
+ when w_verify_on =>
+ state <= w_verify;
+ enable <= '1';
+ addr <= 0;
+ cont <= '0';
+ when w_verify =>
+ if (rx_data(0) = '1' or rx_data(1) = '1') then
+ state <= w_verify_off;
+ else
+ state <= w_verify;
+ end if;
+ when w_verify_off =>
+ state <= wait1b;
+ addr <= 0;
+ enable <= '0';
+ cont <= '0';
+ when wait1b => -- wait
+ if (index = SW-1) then
+ state <= w_start_ewds;
+ index <= 0;
+ else
+ state <= wait1b;
+ index <= index + 1;
+ end if;
+
+ when w_start_ewds => -- send ewds
+ state <= w_send_ewds_1;
+ enable <= '1';
+ --cpol <= '0';
+ --cpha <= '0';
+ addr <= 0;
+ cont <= '1';
+ when w_send_ewds_1 =>
+ state <= w_wait_ewds_1;
+ tw_memory_data_1 <= "10";
+ enable <= '1';
+ when w_wait_ewds_1 =>
+ if (busy = '1') then
+ state <= w_wait_ewds_1;
+ else
+ state <= w_send_ewds_2;
+ enable <= '0';
+ end if;
+ when w_send_ewds_2 =>
+ state <= w_wait_ewds_2;
+ tw_memory_data_1 <= "00";
+ enable <= '1';
+ when w_wait_ewds_2 =>
+ if (busy = '1') then
+ state <= w_wait_ewds_2;
+ else
+ state <= w_send_ewds_3;
+ enable <= '0';
+ end if;
+ when w_send_ewds_3 =>
+ state <= w_wait_ewds_3;
+ tw_memory_data_1 <= "0X";
+ enable <= '1';
+ when w_wait_ewds_3 =>
+ if (busy = '1') then
+ state <= w_wait_ewds_3;
+ else
+ state <= w_stop_ewds;
+ enable <= '0';
+ end if;
+ when w_stop_ewds =>
+ state <= w_stop_ewds_busy;
+ tw_memory_data_1 <= "00";
+ enable <= '0';
+ cont <= '0';
+ when w_stop_ewds_busy =>
+ if (busy = '1') then
+ state <= w_stop_ewds_busy;
+ else
+ state <= wait1c;
+ end if;
+
+ when wait1c => -- wait
+ if (index = SW-1) then
+ state <= start;
+ index <= 0;
+ else
+ state <= wait1c;
+ index <= index + 1;
+ end if;
+
+ when start => -- send address
+ enable <= '1';
+ state <= send1;
+ --cpol <= '0';
+ --cpha <= '0';
+ addr <= 0;
+ cont <= '1';
+ when send1 =>
+ state <= wait1;
+ tw_memory_data_1 <= "11";
+ enable <= '1';
+ when wait1 =>
+ if (busy = '1') then
+ state <= wait1;
+ else
+ state <= send2;
+ enable <= '0';
+ end if;
+ when send2 =>
+ state <= wait2;
+ tw_memory_data_1 <= "0" & memory_address(6);
+ enable <= '1';
+ when wait2 =>
+ if (busy = '1') then
+ state <= wait2;
+ else
+ state <= send3;
+ enable <= '0';
+ end if;
+ when send3 =>
+ state <= wait3;
+ tw_memory_data_1 <= memory_address(5 downto 4);
+ enable <= '1';
+ when wait3 =>
+ if (busy = '1') then
+ state <= wait3;
+ else
+ state <= send4;
+ enable <= '0';
+ end if;
+ when send4 =>
+ state <= wait4;
+ tw_memory_data_1 <= memory_address(3 downto 2);
+ enable <= '1';
+ when wait4 =>
+ if (busy = '1') then
+ state <= wait4;
+ else
+ state <= send5;
+ enable <= '0';
+ end if;
+ when send5 =>
+ state <= wait5;
+ tw_memory_data_1 <= memory_address(1 downto 0);
+ enable <= '1';
+ when wait5 =>
+ if (busy = '1') then
+ state <= wait5;
+ else
+ state <= before_read_data;
+ enable <= '0';
+ end if;
+ when before_read_data =>
+ state <= read_data;
+ enable <= '1';
+ tw_memory_data_1 <= (others => '0');
+ cont <= '1';
+ index <= 0;
+ when read_data => -- read data
+ if (index = (G_MemoryData/d_width)) then
+ state <= st_rs232_enable_tx;
+ index <= 0;
+ enable <= '0';
+ cont <= '0';
+ else
+ memory_data <= memory_data(G_MemoryData-d_width-1 downto 0) & rx_data;
+ --memory_data <= rx_data & memory_data(G_MemoryData-d_width-1 downto 0);
+ state <= read_data_busy;
+ end if;
+ when read_data_busy =>
+ if (busy = '1') then
+ state <= read_data_busy;
+ else
+ state <= read_data;
+ index <= index + 1;
+ end if;
+ when st_rs232_enable_tx => -- send rs232 tx
+ state <= st_rs232_ready;
+ rs232_enable_tx <= '1';
+ when st_rs232_ready =>
+ if (rs232_ready = '1') then
+ state <= st_rs232_busy;
+ --rs232_byte_to_send <= not ('0' & memory_address); -- XXX for tb
+ rs232_byte_to_send <= not memory_data;
+ else
+ state <= st_rs232_ready;
+ end if;
+ when st_rs232_busy =>
+ if (rs232_ready = '1') then
+ state <= st_rs232_busy;
+ else
+ state <= st_rs232_send;
+ end if;
+ when st_rs232_send =>
+ if (rs232_ready = '0') then
+ state <= st_rs232_waiting;
+ else
+ state <= st_rs232_send;
+ end if;
+ when st_rs232_waiting =>
+ if (rs232_busy = '1') then
+ state <= st_rs232_waiting;
+ else
+ state <= st_rs232_disable_tx;
+ end if;
+ when st_rs232_disable_tx =>
+ state <= di_address_increment;
+ rs232_enable_tx <= '0';
+ when di_address_increment =>
+ if (memory_address = std_logic_vector(to_unsigned(to_integer(unsigned(MemoryAddressMAX)),G_MemoryAddress))) then
+ state <= stop;
+ else
+ memory_address <= std_logic_vector(to_unsigned(to_integer(unsigned(memory_address) + 1),G_MemoryAddress));
+ state <= start;
+ end if;
+ when stop =>
+ state <= stop;
+ when others => null;
+ end case;
+ end if;
+ end process p0;
+
+ spim : spi_master
+ GENERIC MAP (
+ slaves => slaves,
+ d_width => d_width
+ )
+ PORT MAP (
+ clock => i_clock,
+ reset_n => not i_reset,
+ enable => enable,
+ cpol => '1',
+ cpha => '0',
+ cont => cont,
+ clk_div => G_CLOCK_DIV1,
+ addr => addr,
+ tx_data => tw_memory_data_1,
+ miso => miso,
+ sclk => sclk,
+ ss_n => ss_n,
+ mosi => mosi,
+ busy => busy,
+ rx_data => rx_data
+ );
+
+ c_rs232 : rs232
+ GENERIC MAP (
+ G_BOARD_CLOCK => G_BOARD_CLOCK,
+ G_BAUD_RATE => G_BAUD_RATE
+ )
+ PORT MAP (
+ clk => i_clock,
+ rst => i_reset,
+ enable_tx => rs232_enable_tx,
+ enable_rx => rs232_enable_rx,
+ byte_to_send => rs232_byte_to_send,
+ byte_received => rs232_byte_received,
+ busy => rs232_busy,
+ ready => rs232_ready,
+ is_byte_received => rs232_is_byte_received,
+ RsTx => o_RsTx,
+ RsRx => i_RsRx
+ );
+
+ c_cd_div1 : clock_divider_count -- XXX SPI 1 MHZ
+ GENERIC MAP (
+ g_board_clock => G_BOARD_CLOCK,
+ g_divider => G_BOARD_CLOCK/G_CLOCK_DIV1
+ )
+ PORT MAP (
+ i_reset => i_reset,
+ i_clock => i_clock,
+ o_clock => cd_o_clock
+ );
+
+ o_cs <= not ss_n(0);
+ o_sk <= sclk;
+ o_di <= mosi;
+ miso <= i_do;
+
+end Behavioral;
diff --git a/memorydump_93LC46/usage.txt b/memorydump_93LC46/usage.txt
new file mode 100755
index 0000000..56097a4
--- /dev/null
+++ b/memorydump_93LC46/usage.txt
@@ -0,0 +1,10 @@
+# file ~/.minirc.dfl
+# Machine-generated file - use setup menu in minicom to change parameters.
+pu port /dev/ttyUSB0
+pu baudrate 9600
+pu linewrap Yes
+pu displayhex Yes
+
+rm -rf minicom.cap && minicom -C minicom.cap
+xxd -plain -revert minicom.cap | hexdump -Cv | less
+
diff --git a/memorydump_AT27C256R/Nexys2_1200General.ucf b/memorydump_AT27C256R/Nexys2_1200General.ucf
new file mode 100755
index 0000000..38ffbd5
--- /dev/null
+++ b/memorydump_AT27C256R/Nexys2_1200General.ucf
@@ -0,0 +1,250 @@
+## This file is a general .ucf for Nexys2 rev A board
+## To use it in a project:
+## - remove or comment the lines corresponding to unused pins
+## - rename the used signals according to the project
+
+## Signals Led<7>Led<4> are assigned to pins which change type from s3e500 to other dies using the same package
+## Both versions are provided in this file.
+## Keep only the appropriate one, and remove or comment the other one.
+
+## Clock pin for Nexys 2 Board
+NET "clk" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
+#NET "clk1" LOC = "U9"; # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK, Sch name = GCLK1
+
+## onBoard USB controller
+## NOTE: DEPP and DSTM net names use some of the same pins, if trying to use both DEPP and DSTM use a signle net name for each shared pin.
+
+## Data bus for both the DEPP and DSTM interfaces uncomment lines 19-26 if using either one
+#NET "DB<0>" LOC = "R14"; # Bank = 2, Pin name = IO_L24N_2/A20, Type = DUAL, Sch name = U-FD0
+#NET "DB<1>" LOC = "R13"; # Bank = 2, Pin name = IO_L22N_2/A22, Type = DUAL, Sch name = U-FD1
+#NET "DB<2>" LOC = "P13"; # Bank = 2, Pin name = IO_L22P_2/A23, Type = DUAL, Sch name = U-FD2
+#NET "DB<3>" LOC = "T12"; # Bank = 2, Pin name = IO_L20P_2, Type = I/O, Sch name = U-FD3
+#NET "DB<4>" LOC = "N11"; # Bank = 2, Pin name = IO_L18N_2, Type = I/O, Sch name = U-FD4
+#NET "DB<5>" LOC = "R11"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = U-FD5
+#NET "DB<6>" LOC = "P10"; # Bank = 2, Pin name = IO_L15N_2/D1/GCLK3, Type = DUAL/GCLK, Sch name = U-FD6
+#NET "DB<7>" LOC = "R10"; # Bank = 2, Pin name = IO_L15P_2/D2/GCLK2, Type = DUAL/GCLK, Sch name = U-FD7
+
+## If using the DEPP interface uncomment lines 29-32
+#NET "EppWRITE" LOC = "V16"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-FLAGC
+#NET "EppASTB" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
+#NET "EppDSTB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
+#NET "EppWAIT" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
+
+## If using the DSTM interface uncomment lines 35-44
+#NET "DstmIFCLK" LOC = "T15"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = U-IFCLK
+#NET "DstmSLCS" LOC = "T16"; # Bank = 2, Pin name = IO_L26P_2/VS0/A17, Type = DUAL, Sch name = U-SLCS
+#NET "DstmFLAGA" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
+#NET "DstmFLAGB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
+#NET "DstmADR<0>" LOC = "T14"; # Bank = 2, Pin name = IO_L24P_2/A21, Type = DUAL, Sch name = U-FIFOAD0
+#NET "DstmADR<1>" LOC = "V13"; # Bank = 2, Pin name = IO_L19N_2/VREF_2, Type = VREF, Sch name = U-FIFOAD1
+#NET "DstmSLRD" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
+#NET "DstmSLWR" LOC = "V9"; # Bank = 2, Pin name = IO_L13N_2/D3/GCLK15, Type = DUAL/GCLK, Sch name = U-SLWR
+#NET "DstmSLOE" LOC = "V15"; # Bank = 2, Pin name = IO_L25P_2/VS2/A19, Type = DUAL, Sch name = U-SLOE
+#NET "DstmPKTEND" LOC = "V12"; # Bank = 2, Pin name = IO_L19P_2, Type = I/O, Sch name = U-PKTEND
+
+#NET "UsbMode" LOC = "U15"; # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type = DUAL, Sch name = U-INT0#
+#NET "UsbRdy" LOC = "U13"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-RDY
+
+## onBoard Cellular RAM and StrataFlash
+#NET "io_MemOE" LOC = "T2"; # Bank = 3, Pin name = IO_L24P_3, Type = I/O, Sch name = OE
+#NET "io_MemWR" LOC = "N7"; # Bank = 2, Pin name = IO_L07P_2, Type = I/O, Sch name = WE
+#
+#NET "io_RamAdv" LOC = "J4"; # Bank = 3, Pin name = IO_L11N_3/LHCLK1, Type = LHCLK, Sch name = MT-ADV
+#NET "io_RamCS" LOC = "R6"; # Bank = 2, Pin name = IO_L05P_2, Type = I/O, Sch name = MT-CE
+#NET "io_RamClk" LOC = "H5"; # Bank = 3, Pin name = IO_L08N_3, Type = I/O, Sch name = MT-CLK
+#NET "io_RamCRE" LOC = "P7"; # Bank = 2, Pin name = IO_L07N_2, Type = I/O, Sch name = MT-CRE
+#NET "io_RamLB" LOC = "K5"; # Bank = 3, Pin name = IO_L14N_3/LHCLK7, Type = LHCLK, Sch name = MT-LB
+#NET "io_RamUB" LOC = "K4"; # Bank = 3, Pin name = IO_L13N_3/LHCLK5, Type = LHCLK, Sch name = MT-UB
+#NET "RamWait" LOC = "F5"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = MT-WAIT
+
+#NET "FlashRp" LOC = "T5"; # Bank = 2, Pin name = IO_L04N_2, Type = I/O, Sch name = RP#
+#NET "io_FlashCS" LOC = "R5"; # Bank = 2, Pin name = IO_L04P_2, Type = I/O, Sch name = ST-CE
+#NET "FlashStSts" LOC = "D3"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = ST-STS
+
+#NET "io_MemAdr<1>" LOC = "J1"; # Bank = 3, Pin name = IO_L12P_3/LHCLK2, Type = LHCLK, Sch name = ADR1
+#NET "io_MemAdr<2>" LOC = "J2"; # Bank = 3, Pin name = IO_L12N_3/LHCLK3/IRDY2, Type = LHCLK, Sch name = ADR2
+#NET "io_MemAdr<3>" LOC = "H4"; # Bank = 3, Pin name = IO_L09P_3, Type = I/O, Sch name = ADR3
+#NET "io_MemAdr<4>" LOC = "H1"; # Bank = 3, Pin name = IO_L10N_3, Type = I/O, Sch name = ADR4
+#NET "io_MemAdr<5>" LOC = "H2"; # Bank = 3, Pin name = IO_L10P_3, Type = I/O, Sch name = ADR5
+#NET "io_MemAdr<6>" LOC = "J5"; # Bank = 3, Pin name = IO_L11P_3/LHCLK0, Type = LHCLK, Sch name = ADR6
+#NET "io_MemAdr<7>" LOC = "H3"; # Bank = 3, Pin name = IO_L09N_3, Type = I/O, Sch name = ADR7
+#NET "io_MemAdr<8>" LOC = "H6"; # Bank = 3, Pin name = IO_L08P_3, Type = I/O, Sch name = ADR8
+#NET "io_MemAdr<9>" LOC = "F1"; # Bank = 3, Pin name = IO_L05P_3, Type = I/O, Sch name = ADR9
+#NET "io_MemAdr<10>" LOC = "G3"; # Bank = 3, Pin name = IO_L06P_3, Type = I/O, Sch name = ADR10
+#NET "io_MemAdr<11>" LOC = "G6"; # Bank = 3, Pin name = IO_L07P_3, Type = I/O, Sch name = ADR11
+#NET "io_MemAdr<12>" LOC = "G5"; # Bank = 3, Pin name = IO_L07N_3, Type = I/O, Sch name = ADR12
+#NET "io_MemAdr<13>" LOC = "G4"; # Bank = 3, Pin name = IO_L06N_3/VREF_3, Type = VREF, Sch name = ADR13
+#NET "io_MemAdr<14>" LOC = "F2"; # Bank = 3, Pin name = IO_L05N_3, Type = I/O, Sch name = ADR14
+#NET "io_MemAdr<15>" LOC = "E1"; # Bank = 3, Pin name = IO_L03N_3, Type = I/O, Sch name = ADR15
+#NET "io_MemAdr<16>" LOC = "M5"; # Bank = 3, Pin name = IO_L19P_3, Type = I/O, Sch name = ADR16
+#NET "io_MemAdr<17>" LOC = "E2"; # Bank = 3, Pin name = IO_L03P_3, Type = I/O, Sch name = ADR17
+#NET "io_MemAdr<18>" LOC = "C2"; # Bank = 3, Pin name = IO_L01N_3, Type = I/O, Sch name = ADR18
+#NET "io_MemAdr<19>" LOC = "C1"; # Bank = 3, Pin name = IO_L01P_3, Type = I/O, Sch name = ADR19
+#NET "io_MemAdr<20>" LOC = "D2"; # Bank = 3, Pin name = IO_L02N_3/VREF_3, Type = VREF, Sch name = ADR20
+#NET "io_MemAdr<21>" LOC = "K3"; # Bank = 3, Pin name = IO_L13P_3/LHCLK4/TRDY2, Type = LHCLK, Sch name = ADR21
+#NET "io_MemAdr<22>" LOC = "D1"; # Bank = 3, Pin name = IO_L02P_3, Type = I/O, Sch name = ADR22
+#NET "io_MemAdr<23>" LOC = "K6"; # Bank = 3, Pin name = IO_L14P_3/LHCLK6, Type = LHCLK, Sch name = ADR23
+#
+#NET "io_MemDB<0>" LOC = "L1"; # Bank = 3, Pin name = IO_L15P_3, Type = I/O, Sch name = DB0
+#NET "io_MemDB<1>" LOC = "L4"; # Bank = 3, Pin name = IO_L16N_3, Type = I/O, Sch name = DB1
+#NET "io_MemDB<2>" LOC = "L6"; # Bank = 3, Pin name = IO_L17P_3, Type = I/O, Sch name = DB2
+#NET "io_MemDB<3>" LOC = "M4"; # Bank = 3, Pin name = IO_L18P_3, Type = I/O, Sch name = DB3
+#NET "io_MemDB<4>" LOC = "N5"; # Bank = 3, Pin name = IO_L20N_3, Type = I/O, Sch name = DB4
+#NET "io_MemDB<5>" LOC = "P1"; # Bank = 3, Pin name = IO_L21N_3, Type = I/O, Sch name = DB5
+#NET "io_MemDB<6>" LOC = "P2"; # Bank = 3, Pin name = IO_L21P_3, Type = I/O, Sch name = DB6
+#NET "io_MemDB<7>" LOC = "R2"; # Bank = 3, Pin name = IO_L23N_3, Type = I/O, Sch name = DB7
+#NET "io_MemDB<8>" LOC = "L3"; # Bank = 3, Pin name = IO_L16P_3, Type = I/O, Sch name = DB8
+#NET "io_MemDB<9>" LOC = "L5"; # Bank = 3, Pin name = IO_L17N_3/VREF_3, Type = VREF, Sch name = DB9
+#NET "io_MemDB<10>" LOC = "M3"; # Bank = 3, Pin name = IO_L18N_3, Type = I/O, Sch name = DB10
+#NET "io_MemDB<11>" LOC = "M6"; # Bank = 3, Pin name = IO_L19N_3, Type = I/O, Sch name = DB11
+#NET "io_MemDB<12>" LOC = "L2"; # Bank = 3, Pin name = IO_L15N_3, Type = I/O, Sch name = DB12
+#NET "io_MemDB<13>" LOC = "N4"; # Bank = 3, Pin name = IO_L20P_3, Type = I/O, Sch name = DB13
+#NET "io_MemDB<14>" LOC = "R3"; # Bank = 3, Pin name = IO_L23P_3, Type = I/O, Sch name = DB14
+#NET "io_MemDB<15>" LOC = "T1"; # Bank = 3, Pin name = IO_L24N_3, Type = I/O, Sch name = DB15
+
+## 7 segment display
+#NET "seg<0>" LOC = "L18"; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA
+#NET "seg<1>" LOC = "F18"; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB
+#NET "seg<2>" LOC = "D17"; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC
+#NET "seg<3>" LOC = "D16"; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD
+#NET "seg<4>" LOC = "G14"; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE
+#NET "seg<5>" LOC = "J17"; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
+#NET "seg<6>" LOC = "H14"; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG
+#NET "dp" LOC = "C17"; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP
+
+#NET "an<0>" LOC = "F17"; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0
+#NET "an<1>" LOC = "H17"; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1
+#NET "an<2>" LOC = "C18"; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2
+#NET "an<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3
+
+## Leds
+NET "JD<7>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
+NET "JD<6>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
+NET "JD<5>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
+NET "JD<4>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
+#NET "Led<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4? s3e500 only
+#NET "Led<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5? s3e500 only
+#NET "Led<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6? s3e500 only
+#NET "Led<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7? s3e500 only
+#NET "Led<4>" LOC = "E16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD4? other than s3e500
+#NET "Led<5>" LOC = "P16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD5? other than s3e500
+#NET "Led<6>" LOC = "E4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD6? other than s3e500
+#NET "Led<7>" LOC = "P4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD7? other than s3e500
+
+## Switches
+#NET "sw<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
+#NET "sw<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
+#NET "sw<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
+#NET "sw<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
+#NET "sw<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
+#NET "sw<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
+#NET "sw<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
+#NET "sw<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7
+
+## Buttons
+NET "btn0" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
+#NET "btn<0>" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
+#NET "btn<1>" LOC = "D18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = BTN1
+#NET "btn<2>" LOC = "E18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN2
+#NET "btn<3>" LOC = "H13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN3
+
+## VGA Connector
+#NET "vgaRed<1>" LOC = "R9"; # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0
+#NET "vgaRed<2>" LOC = "T8"; # Bank = 2, Pin name = IO_L10N_2, Type = I/O, Sch name = RED1
+#NET "vgaRed<3>" LOC = "R8"; # Bank = 2, Pin name = IO_L10P_2, Type = I/O, Sch name = RED2
+#NET "vgaGreen<1>" LOC = "N8"; # Bank = 2, Pin name = IO_L09N_2, Type = I/O, Sch name = GRN0
+#NET "vgaGreen<2>" LOC = "P8"; # Bank = 2, Pin name = IO_L09P_2, Type = I/O, Sch name = GRN1
+#NET "vgaGreen<3>" LOC = "P6"; # Bank = 2, Pin name = IO_L05N_2, Type = I/O, Sch name = GRN2
+#NET "vgaBlue<2>" LOC = "U5"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = BLU1
+#NET "vgaBlue<3>" LOC = "U4"; # Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DUAL, Sch name = BLU2
+
+#NET "Hsync" LOC = "T4"; # Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type = DUAL, Sch name = HSYNC
+#NET "Vsync" LOC = "U3"; # Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUAL, Sch name = VSYNC
+
+## PS/2 connector
+#NET "PS2C" LOC = "R12"; # Bank = 2, Pin name = IO_L20N_2, Type = I/O, Sch name = PS2C
+#NET "PS2D" LOC = "P11"; # Bank = 2, Pin name = IO_L18P_2, Type = I/O, Sch name = PS2D
+
+## FX2 connector
+#NET "PIO<0>" LOC = "B4"; # Bank = 0, Pin name = IO_L24N_0, Type = I/O, Sch name = R-IO1
+#NET "PIO<1>" LOC = "A4"; # Bank = 0, Pin name = IO_L24P_0, Type = I/O, Sch name = R-IO2
+#NET "PIO<2>" LOC = "C3"; # Bank = 0, Pin name = IO_L25P_0, Type = I/O, Sch name = R-IO3
+#NET "PIO<3>" LOC = "C4"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO4
+#NET "PIO<4>" LOC = "B6"; # Bank = 0, Pin name = IO_L20P_0, Type = I/O, Sch name = R-IO5
+#NET "PIO<5>" LOC = "D5"; # Bank = 0, Pin name = IO_L23N_0/VREF_0, Type = VREF, Sch name = R-IO6
+#NET "PIO<6>" LOC = "C5"; # Bank = 0, Pin name = IO_L23P_0, Type = I/O, Sch name = R-IO7
+#NET "PIO<7>" LOC = "F7"; # Bank = 0, Pin name = IO_L19P_0, Type = I/O, Sch name = R-IO8
+#NET "PIO<8>" LOC = "E7"; # Bank = 0, Pin name = IO_L19N_0/VREF_0, Type = VREF, Sch name = R-IO9
+#NET "PIO<9>" LOC = "A6"; # Bank = 0, Pin name = IO_L20N_0, Type = I/O, Sch name = R-IO10
+#NET "PIO<10>" LOC = "C7"; # Bank = 0, Pin name = IO_L18P_0, Type = I/O, Sch name = R-IO11
+#NET "PIO<11>" LOC = "F8"; # Bank = 0, Pin name = IO_L17N_0, Type = I/O, Sch name = R-IO12
+#NET "PIO<12>" LOC = "D7"; # Bank = 0, Pin name = IO_L18N_0/VREF_0, Type = VREF, Sch name = R-IO13
+#NET "PIO<13>" LOC = "E8"; # Bank = 0, Pin name = IO_L17P_0, Type = I/O, Sch name = R-IO14
+#NET "PIO<14>" LOC = "E9"; # Bank = 0, Pin name = IO_L15P_0, Type = I/O, Sch name = R-IO15
+#NET "PIO<15>" LOC = "C9"; # Bank = 0, Pin name = IO_L14P_0/GCLK10, Type = GCLK, Sch name = R-IO16
+#NET "PIO<16>" LOC = "A8"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO17
+#NET "PIO<17>" LOC = "G9"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO18
+#NET "PIO<18>" LOC = "F9"; # Bank = 0, Pin name = IO_L15N_0, Type = I/O, Sch name = R-IO19
+#NET "PIO<19>" LOC = "D10"; # Bank = 0, Pin name = IO_L11P_0/GCLK4, Type = GCLK, Sch name = R-IO20
+#NET "PIO<20>" LOC = "A10"; # Bank = 0, Pin name = IO_L12N_0/GCLK7, Type = GCLK, Sch name = R-IO21
+#NET "PIO<21>" LOC = "B10"; # Bank = 0, Pin name = IO_L12P_0/GCLK6, Type = GCLK, Sch name = R-IO22
+#NET "PIO<22>" LOC = "A11"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO23
+#NET "PIO<23>" LOC = "D11"; # Bank = 0, Pin name = IO_L09N_0, Type = I/O, Sch name = R-IO24
+#NET "PIO<24>" LOC = "E10"; # Bank = 0, Pin name = IO_L11N_0/GCLK5, Type = GCLK, Sch name = R-IO25
+#NET "PIO<25>" LOC = "B11"; # Bank = 0, Pin name = IO/VREF_0, Type = VREF, Sch name = R-IO26
+#NET "PIO<26>" LOC = "C11"; # Bank = 0, Pin name = IO_L09P_0, Type = I/O, Sch name = R-IO27
+#NET "PIO<27>" LOC = "E11"; # Bank = 0, Pin name = IO_L08P_0, Type = I/O, Sch name = R-IO28
+#NET "PIO<28>" LOC = "F11"; # Bank = 0, Pin name = IO_L08N_0, Type = I/O, Sch name = R-IO29
+#NET "PIO<29>" LOC = "E12"; # Bank = 0, Pin name = IO_L06N_0, Type = I/O, Sch name = R-IO30
+#NET "PIO<30>" LOC = "F12"; # Bank = 0, Pin name = IO_L06P_0, Type = I/O, Sch name = R-IO31
+#NET "PIO<31>" LOC = "A13"; # Bank = 0, Pin name = IO_L05P_0, Type = I/O, Sch name = R-IO32
+#NET "PIO<32>" LOC = "B13"; # Bank = 0, Pin name = IO_L05N_0/VREF_0, Type = VREF, Sch name = R-IO33
+#NET "PIO<33>" LOC = "E13"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO34
+#NET "PIO<34>" LOC = "A14"; # Bank = 0, Pin name = IO_L04N_0, Type = I/O, Sch name = R-IO35
+#NET "PIO<35>" LOC = "C14"; # Bank = 0, Pin name = IO_L03N_0/VREF_0, Type = VREF, Sch name = R-IO36
+#NET "PIO<36>" LOC = "D14"; # Bank = 0, Pin name = IO_L03P_0, Type = I/O, Sch name = R-IO37
+#NET "PIO<37>" LOC = "B14"; # Bank = 0, Pin name = IO_L04P_0, Type = I/O, Sch name = R-IO38
+#NET "PIO<38>" LOC = "A16"; # Bank = 0, Pin name = IO_L01N_0, Type = I/O, Sch name = R-IO39
+#NET "PIO<39>" LOC = "B16"; # Bank = 0, Pin name = IO_L01P_0, Type = I/O, Sch name = R-IO40
+
+## 12 pin connectors
+
+##JA
+NET "JA<0>" LOC = "L15"; # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1
+NET "JA<1>" LOC = "K12"; # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2
+#NET "JA<2>" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
+#NET "JA<3>" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
+#NET "JA<4>" LOC = "K13"; # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL, Sch name = JA7
+#NET "JA<5>" LOC = "L16"; # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL, Sch name = JA8
+#NET "JA<6>" LOC = "M14"; # Bank = 1, Pin name = IO_L05P_1, Type = I/O, Sch name = JA9
+#NET "JA<7>" LOC = "M16"; # Bank = 1, Pin name = IO_L07N_1, Type = I/O, Sch name = JA10
+
+##JB
+NET "JB<0>" LOC = "M13"; # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF, Sch name = JB1
+NET "JB<1>" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
+NET "JB<2>" LOC = "R15"; # Bank = 1, Pin name = IO_L03P_1, Type = I/O, Sch name = JB3
+NET "JB<3>" LOC = "T17"; # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL, Sch name = JB4
+NET "JB<4>" LOC = "P17"; # Bank = 1, Pin name = IO_L06P_1, Type = I/O, Sch name = JB7
+NET "JB<5>" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
+NET "JB<6>" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
+NET "JB<7>" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
+
+##JC
+NET "JC<0>" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
+NET "JC<1>" LOC = "J16"; # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL, Sch name = JC2
+NET "JC<2>" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
+NET "JC<3>" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
+NET "JC<4>" LOC = "H15"; # Bank = 1, Pin name = IO_L17N_1, Type = I/O, Sch name = JC7
+NET "JC<5>" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
+NET "JC<6>" LOC = "G16"; # Bank = 1, Pin name = IO_L18N_1, Type = I/O, Sch name = JC9
+#NET "JC<7>" LOC = "J12"; # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL, Sch name = JC10
+
+##JD - NOTE: For other JD pins see LD(3:0) above under "Leds"
+NET "JD<0>" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
+NET "JD<1>" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
+NET "JD<2>" LOC = "N18"; # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3
+NET "JD<3>" LOC = "P18"; # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4
+
+## RS232 connector
+#NET "RsRx" LOC = "U6"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = RS-RX
+NET "RsTx" LOC = "P9"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = RS-TX
diff --git a/memorydump_AT27C256R/clock_divider_count.vhd b/memorydump_AT27C256R/clock_divider_count.vhd
new file mode 100755
index 0000000..fe5a524
--- /dev/null
+++ b/memorydump_AT27C256R/clock_divider_count.vhd
@@ -0,0 +1,67 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:42:10 09/18/2020
+-- Design Name:
+-- Module Name: clock_divider - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_constants.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_divider_count is
+Generic (
+ g_board_clock : integer := G_BOARD_CLOCK;
+ g_divider : integer := 1
+);
+Port (
+ i_reset : in STD_LOGIC;
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+);
+end clock_divider_count;
+
+architecture Behavioral of clock_divider_count is
+begin
+
+p0 : process (i_clock,i_reset) is
+ variable clock_out : std_logic;
+ variable counter : integer := 0;
+ variable divider : integer := (g_board_clock / g_divider);
+begin
+ if (i_reset = '1') then
+ counter := 0;
+ elsif (rising_edge(i_clock)) then
+ if (counter = divider - 1) then
+ clock_out := '1';
+ counter := 0;
+ else
+ clock_out := '0';
+ counter := counter + 1;
+ end if;
+ end if;
+ o_clock <= clock_out;
+end process p0;
+
+end Behavioral;
diff --git a/memorydump_AT27C256R/clock_divider_sub.vhd b/memorydump_AT27C256R/clock_divider_sub.vhd
new file mode 100755
index 0000000..c1cdc88
--- /dev/null
+++ b/memorydump_AT27C256R/clock_divider_sub.vhd
@@ -0,0 +1,67 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:42:10 09/18/2020
+-- Design Name:
+-- Module Name: clock_divider - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_divider_sub is
+Port(
+i_clk : in STD_LOGIC;
+i_rst : in STD_LOGIC;
+i_board_clock : in INTEGER;
+i_divider : in INTEGER;
+o_clk : out STD_LOGIC
+);
+end clock_divider_sub;
+
+architecture Behavioral of clock_divider_sub is
+begin
+
+p0 : process (i_clk,i_rst) is
+ variable clk_out : std_logic;
+ variable a : integer := i_board_clock;
+ variable b : integer := i_divider;
+begin
+ if (i_rst = '1') then
+ a := i_board_clock;
+ b := i_divider;
+ elsif (rising_edge(i_clk)) then
+ if (a <= 0) then
+ clk_out := '1';
+ a := i_board_clock;
+ b := i_divider;
+ else
+ clk_out := '0';
+ a := a - b;
+ end if;
+ end if;
+ o_clk <= clk_out;
+end process p0;
+
+end Behavioral;
+
diff --git a/memorydump_AT27C256R/fifo.vhd b/memorydump_AT27C256R/fifo.vhd
new file mode 100755
index 0000000..6169e06
--- /dev/null
+++ b/memorydump_AT27C256R/fifo.vhd
@@ -0,0 +1,109 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:47:51 02/02/2021
+-- Design Name:
+-- Module Name: fifo - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity fifo is
+Generic (
+ WIDTH : integer := 8;
+ HEIGHT : integer := 1
+);
+Port (
+ i_clk1 : in STD_LOGIC;
+ i_clk2 : in STD_LOGIC;
+ i_rst : in STD_LOGIC;
+ i_data : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ o_data : out STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ o_full : out STD_LOGIC;
+ o_empty : out STD_LOGIC;
+ o_memory_index : out std_logic_vector(HEIGHT-1 downto 0)
+);
+end fifo;
+
+-- fifo one clock
+
+architecture Behavioral of fifo is
+
+ type memory_t is array(0 to HEIGHT-1) of std_logic_vector(WIDTH-1 downto 0);
+ signal memory : memory_t;
+ signal index : integer range 0 to HEIGHT:= 0;
+ signal full,empty : std_logic;
+ signal r,w : integer range 0 to HEIGHT-1:= 0;
+
+begin
+
+ empty <= '1' when (index=0) else '0';
+ full <= '1' when (index=HEIGHT-1) else '0';
+
+ o_memory_index <= std_logic_vector(to_unsigned(index,HEIGHT));
+ o_full <= full;
+ o_empty <= empty;
+
+ pc : process (i_clk1,i_rst) is
+ begin
+ if (i_rst = '1') then
+ index <= 0;
+ elsif (rising_edge(i_clk1)) then
+ if (index = HEIGHT-1) then
+ index <= 0;
+ else
+ index <= index + 1;
+ end if;
+ end if;
+ end process pc;
+
+ pa : process (i_clk1,w,i_rst) is
+ begin
+ if (i_rst = '1') then
+ w <= 0;
+ elsif (rising_edge(i_clk1)) then
+ memory(w) <= i_data;
+ if (w=HEIGHT-1) then
+ w <= 0;
+ else
+ w <= w + 1;
+ end if;
+ end if;
+ end process pa;
+
+ pb : process (i_clk1,r,i_rst) is
+ begin
+ if (i_rst = '1') then
+ r <= 0;
+ elsif (rising_edge(i_clk1)) then
+ o_data <= memory(r);
+ if (r=HEIGHT-1) then
+ r <= 0;
+ else
+ r <= r + 1;
+ end if;
+ end if;
+ end process pb;
+
+end Behavioral;
diff --git a/memorydump_AT27C256R/fifo.wcfg b/memorydump_AT27C256R/fifo.wcfg
new file mode 100755
index 0000000..6d824a2
--- /dev/null
+++ b/memorydump_AT27C256R/fifo.wcfg
@@ -0,0 +1,67 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ clk1
+ clk1
+
+
+ clk2
+ clk2
+
+
+ data_in[7:0]
+ data_in[7:0]
+ HEXRADIX
+
+
+ data_out[7:0]
+ data_out[7:0]
+ HEXRADIX
+
+
+ full
+ full
+
+
+ empty
+ empty
+
+
+ width
+ width
+
+
+ height
+ height
+
+
+ clk1_period
+ clk1_period
+
+
+ clk2_period
+ clk2_period
+
+
+ memory[0:3]
+ memory[0:3]
+ HEXRADIX
+
+
+ o_memory_index[3:0]
+ o_memory_index[3:0]
+ UNSIGNEDDECRADIX
+
+
diff --git a/memorydump_AT27C256R/impact_top.ipf b/memorydump_AT27C256R/impact_top.ipf
new file mode 100755
index 0000000..2ee5452
--- /dev/null
+++ b/memorydump_AT27C256R/impact_top.ipf
@@ -0,0 +1,8 @@
+setMode -bs
+setCable -port auto
+Identify -inferir
+identifyMPM
+assignFile -p 1 -file top.bit
+Program -p 1
+closeCable
+quit
diff --git a/memorydump_AT27C256R/logicanalyser.xise b/memorydump_AT27C256R/logicanalyser.xise
new file mode 100755
index 0000000..0156116
--- /dev/null
+++ b/memorydump_AT27C256R/logicanalyser.xise
@@ -0,0 +1,389 @@
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
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+
+
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+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
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+
+
+
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+
+
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+
+
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+
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+
+
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+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
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+
+
+
+
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+
+
+
+
+
+
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+
+
+
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+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
diff --git a/memorydump_AT27C256R/memorymodule.vhd b/memorydump_AT27C256R/memorymodule.vhd
new file mode 100755
index 0000000..b151bfc
--- /dev/null
+++ b/memorydump_AT27C256R/memorymodule.vhd
@@ -0,0 +1,133 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:11:00 11/28/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/memorymodule/memorymodule.vhd
+-- Project Name: memorymodule
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_constants.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity memorymodule is
+Port (
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_enable : in std_logic;
+i_read : in std_logic;
+o_busy : out std_logic;
+i_MemAdr : in MemoryAddressALL;
+io_MemOE : out std_logic;
+io_RamCS : out std_logic;
+io_MemAdr : out MemoryAddressALL
+);
+end memorymodule;
+
+architecture Behavioral of memorymodule is
+
+ type state is (
+ idle,
+ start,
+ read_setup,
+ read_current,
+ read_wait,
+ stop
+ );
+ signal cstate : state;
+
+ signal MemOE : std_logic;
+ signal RamCS : std_logic;
+ signal MemAdr : MemoryAddressALL;
+
+begin
+
+ io_MemOE <= MemOE;
+ io_RamCS <= RamCS;
+ io_MemAdr <= MemAdr;
+
+ MemAdr <= i_MemAdr when (RamCS = '0' and MemOE = '0') else (others => 'Z');
+
+ p0 : process (i_clock,i_reset) is
+ constant cw : integer := (G_BOARD_CLOCK/G_BAUD_RATE);
+ variable w : integer range 0 to cw-1;
+ variable t : std_logic_vector(G_MemoryData-1 downto 0);
+ variable tz : std_logic_vector(G_MemoryData-1 downto 0);
+ begin
+ if (i_reset = '1') then
+ w := 0;
+ t := (others => '0');
+ tz := (others => 'Z');
+ RamCS <= '1';
+ MemOE <= '1';
+ elsif (rising_edge(i_clock)) then
+ if (w = cw-1) then
+ w := 0;
+ else
+ w := w + 1;
+ end if;
+ case cstate is
+ when idle =>
+ if (i_enable = '1') then
+ cstate <= start; -- XXX check CSb
+ else
+ cstate <= idle;
+ end if;
+ when start =>
+ if (i_read = '1') then
+ cstate <= read_setup;
+ else
+ cstate <= start;
+ end if;
+ RamCS <= '1';
+ MemOE <= '1';
+ when read_setup =>
+ if (w = cw-1) then
+ cstate <= read_current;
+ RamCS <= '0';
+ MemOE <= '1';
+ o_busy <= '1';
+ else
+ cstate <= read_setup;
+ end if;
+ when read_current =>
+ cstate <= read_wait;
+ MemOE <= '0';
+ w := 0;
+ when read_wait =>
+ if (w = cw-1) then
+ cstate <= stop;
+ else
+ cstate <= read_wait;
+ end if;
+ when stop =>
+ cstate <= idle;
+ o_busy <= '0';
+ RamCS <= '1';
+ MemOE <= '1';
+ when others => null;
+ end case;
+ end if;
+ end process p0;
+
+end Behavioral;
diff --git a/memorydump_AT27C256R/p_constants.vhd b/memorydump_AT27C256R/p_constants.vhd
new file mode 100755
index 0000000..6044af7
--- /dev/null
+++ b/memorydump_AT27C256R/p_constants.vhd
@@ -0,0 +1,38 @@
+--
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+--
+-- To use any of the example code shown below, uncomment the lines and modify as necessary
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package p_constants is
+ constant G_BOARD_CLOCK : integer := 50_000_000;
+ constant NUMBER_BITS : integer := 8;
+ constant G_MemoryAddress : integer := 16; -- XXX 15 bit addr - AT27C256R
+ constant G_MemoryData : integer := NUMBER_BITS;
+ subtype MemoryAddress is std_logic_vector(G_MemoryAddress-1 downto 0);
+ subtype MemoryAddressALL is std_logic_vector(G_MemoryAddress-1 downto 0);
+ subtype MemoryDataByte is std_logic_vector(G_MemoryData-1 downto 0);
+-- constant FIFO_WIDTH : integer := NUMBER_BITS;
+-- constant FIFO_HEIGHT : integer := 1;
+-- constant G_BAUD_RATE : integer := 115200;
+-- constant G_BAUD_RATE : integer := 57600;
+-- constant G_BAUD_RATE : integer := 38400;
+-- constant G_BAUD_RATE : integer := 19200;
+ constant G_BAUD_RATE : integer := 9600;
+-- constant G_BAUD_RATE : integer := 4800;
+-- constant G_BAUD_RATE : integer := 2400;
+-- constant G_BAUD_RATE : integer := 1200;
+-- constant G_BAUD_RATE : integer := 300;
+-- constant G_BR_OVERSAMPLING : integer := 16;
+-- constant G_PARITY : integer := 0;
+-- constant G_PARITY_EO : std_logic := '0'; -- even/odd
+end p_constants;
+
+package body p_constants is
+end p_constants;
diff --git a/memorydump_AT27C256R/rs232.vhd b/memorydump_AT27C256R/rs232.vhd
new file mode 100755
index 0000000..88fb60f
--- /dev/null
+++ b/memorydump_AT27C256R/rs232.vhd
@@ -0,0 +1,132 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:54:25 09/08/2020
+-- Design Name:
+-- Module Name: module_1 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity rs232 is
+Generic (
+ G_BOARD_CLOCK : integer := 50_000_000;
+ G_BAUD_RATE : integer := 9_600
+);
+Port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ enable : in STD_LOGIC;
+ byte_to_send : in STD_LOGIC_VECTOR (7 downto 0);
+ busy : out STD_LOGIC;
+ ready : out STD_LOGIC;
+ RsTx : out STD_LOGIC
+);
+end rs232;
+
+architecture Behavioral of rs232 is
+
+ signal clk_div1 : std_logic;
+
+ type state is (start,b1,b2,b3,b4,b5,b6,b7,b8,parity,stop);
+ signal c_state : state := start;
+
+begin
+
+ p_dv : process (clk,rst) is
+ constant COUNTER_BAUD_RATE_MAX : integer := (G_BOARD_CLOCK/G_BAUD_RATE);
+ variable counter_baud_rate : integer := 0;
+ begin
+ if (rst = '1') then
+ counter_baud_rate := 0;
+ elsif (rising_edge(clk)) then
+ if (counter_baud_rate = COUNTER_BAUD_RATE_MAX-1) then
+ clk_div1 <= '1';
+ counter_baud_rate := 0;
+ else
+ clk_div1 <= '0';
+ counter_baud_rate := counter_baud_rate + 1;
+ end if;
+ end if;
+ end process p_dv;
+
+ p0 : process (clk_div1,rst) is
+ begin
+ if (rst = '1') then
+ c_state <= start;
+ busy <= '0';
+ ready <= '1';
+ RsTx <= '0';
+ elsif (rising_edge(clk_div1)) then
+ case c_state is
+ when start =>
+ if (enable = '1') then
+ c_state <= b1;
+ busy <= '1';
+ ready <= '0';
+ RsTx <= '1';
+ elsif (enable = '0') then
+ c_state <= start;
+ busy <= '0';
+ ready <= '1';
+ RsTx <= '0';
+ end if;
+ when b1 =>
+ c_state <= b2;
+ RsTx <= byte_to_send(0);
+ when b2 =>
+ c_state <= b3;
+ RsTx <= byte_to_send(1);
+ when b3 =>
+ c_state <= b4;
+ RsTx <= byte_to_send(2);
+ when b4 =>
+ c_state <= b5;
+ RsTx <= byte_to_send(3);
+ when b5 =>
+ c_state <= b6;
+ RsTx <= byte_to_send(4);
+ when b6 =>
+ c_state <= b7;
+ RsTx <= byte_to_send(5);
+ when b7 =>
+ c_state <= b8;
+ RsTx <= byte_to_send(6);
+ when b8 =>
+ c_state <= parity;
+ RsTx <= byte_to_send(7);
+ when parity =>
+ c_state <= stop;
+ RsTx <= byte_to_send(0) xor byte_to_send(1) xor byte_to_send(2) xor byte_to_send(3) xor byte_to_send(4) xor byte_to_send(5) xor byte_to_send(6) xor byte_to_send(7);
+ when stop =>
+ RsTx <= '0';
+ c_state <= start;
+ busy <= '0';
+ ready <= '1';
+ when others => null;
+ end case;
+ end if;
+ end process p0;
+
+end Behavioral;
diff --git a/memorydump_AT27C256R/rs232.wcfg b/memorydump_AT27C256R/rs232.wcfg
new file mode 100755
index 0000000..549601d
--- /dev/null
+++ b/memorydump_AT27C256R/rs232.wcfg
@@ -0,0 +1,51 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ clk
+ clk
+
+
+ rst
+ rst
+
+
+ rx
+ rx
+
+
+ tx
+ tx
+
+
+ byte_to_send[7:0]
+ byte_to_send[7:0]
+
+
+ clk_div1
+ clk_div1
+
+
+ c_state
+ c_state
+
+
+ busy
+ busy
+
+
+ ready
+ ready
+
+
diff --git a/memorydump_AT27C256R/simulate-tb_top.sh b/memorydump_AT27C256R/simulate-tb_top.sh
new file mode 100755
index 0000000..8deb2eb
--- /dev/null
+++ b/memorydump_AT27C256R/simulate-tb_top.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+PROJECT="tb_top"
+fuse -intstyle ise -incremental -o ./${PROJECT}_isim_beh.exe -prj ./${PROJECT}_beh.prj work.${PROJECT}
+./${PROJECT}_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb ./${PROJECT}_isim.beh.wdb -view ./${PROJECT}.wcfg
diff --git a/memorydump_AT27C256R/synthesis-top.sh b/memorydump_AT27C256R/synthesis-top.sh
new file mode 100755
index 0000000..5326064
--- /dev/null
+++ b/memorydump_AT27C256R/synthesis-top.sh
@@ -0,0 +1,48 @@
+#!/bin/sh
+
+mkdir -p xst/projnav.tmp/
+
+xst -intstyle ise -ifn ./top.xst -ofn ./top.syr
+if [ $? -ne 0 ];
+then
+ echo "error on xst";
+ exit;
+else
+ ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Nexys2_1200General.ucf -p xc3s1200e-fg320-4 top.ngc top.ngd
+ if [ $? -ne 0 ];
+ then
+ echo "error on ngdbuild";
+ exit;
+ else
+ map -intstyle ise -p xc3s1200e-fg320-4 -ol std -timing -cm balanced -ir off -pr off -o top_map.ncd top.ngd top.pcf
+ if [ $? -ne 0 ];
+ then
+ echo "error on map";
+ exit;
+ else
+ par -w -intstyle ise -ol std -rl std -t 1 top_map.ncd top.ncd top.pcf
+ if [ $? -ne 0 ];
+ then
+ echo "error on par";
+ exit;
+ else
+ trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf -ucf Nexys2_1200General.ucf
+ if [ $? -ne 0 ];
+ then
+ echo "error on trce";
+ exit;
+ else
+ bitgen -intstyle ise -f top.ut top.ncd
+ if [ $? -ne 0 ];
+ then
+ echo "error on bitgen";
+ exit;
+ else
+ ls -l top.bit
+ fi
+ fi
+ fi
+ fi
+ fi
+fi
+
diff --git a/memorydump_AT27C256R/tb_fifo.vhd b/memorydump_AT27C256R/tb_fifo.vhd
new file mode 100755
index 0000000..51237ad
--- /dev/null
+++ b/memorydump_AT27C256R/tb_fifo.vhd
@@ -0,0 +1,147 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:46:11 02/02/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/logicanalyser/tb_fifo.vhd
+-- Project Name: logicanalyser
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: fifo
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_fifo IS
+END tb_fifo;
+
+ARCHITECTURE behavior OF tb_fifo IS
+ constant WIDTH : integer := 8;
+ constant HEIGHT : integer := 4;
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT fifo
+ GENERIC(
+ WIDTH: integer := WIDTH;
+ HEIGHT : integer := HEIGHT
+ );
+ PORT(
+ i_clk1 : IN std_logic;
+ i_clk2 : IN std_logic;
+ i_data : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ o_data : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+ o_full : OUT std_logic;
+ o_empty : OUT std_logic;
+ o_memory_index : out std_logic_vector(HEIGHT-1 downto 0)
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal clk1 : std_logic := '0';
+ signal clk2 : std_logic := '0';
+ signal data_in : STD_LOGIC_VECTOR(WIDTH-1 downto 0) := x"00";
+
+ --Outputs
+ signal data_out : STD_LOGIC_VECTOR(WIDTH-1 downto 0) := x"00";
+ signal full : std_logic;
+ signal empty : std_logic;
+ signal memory_index : std_logic_vector(HEIGHT-1 downto 0);
+
+ -- Clock period definitions
+ constant clk1_period : time := 20 ns;
+ constant clk2_period : time := 1920 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: fifo PORT MAP (
+ i_clk1 => clk1,
+ i_clk2 => clk2,
+ i_data => data_in,
+ o_data => data_out,
+ o_full => full,
+ o_empty => empty,
+ o_memory_index => memory_index
+ );
+
+ -- Clock process definitions
+ clk1_process :process
+ begin
+ clk1 <= '0';
+ wait for clk1_period/2;
+ clk1 <= '1';
+ wait for clk1_period/2;
+ if (full='1') then
+ wait until empty='1';
+ end if;
+ end process;
+
+ clk2_process :process
+ begin
+ clk2 <= '0';
+ wait for clk2_period/2;
+ clk2 <= '1';
+ wait for clk2_period/2;
+ if (empty='1') then
+ wait until full='1';
+ end if;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ --wait for 100 ns;
+
+ --wait for clk1_period*10;
+
+ -- insert stimulus here
+
+data_in <= x"12";
+wait until rising_edge(clk1);
+data_in <= x"23";
+wait until rising_edge(clk1);
+data_in <= x"34";
+wait until rising_edge(clk1);
+data_in <= x"45";
+wait until rising_edge(clk1);
+data_in <= x"56";
+wait until rising_edge(clk1);
+data_in <= x"67";
+wait until rising_edge(clk1);
+data_in <= x"78";
+wait until rising_edge(clk1);
+data_in <= x"89";
+wait until rising_edge(clk1);
+data_in <= x"90";
+wait until rising_edge(clk1);
+data_in <= x"00";
+wait until rising_edge(clk1);
+wait;
+
+ end process;
+
+END;
diff --git a/memorydump_AT27C256R/tb_rs232.vhd b/memorydump_AT27C256R/tb_rs232.vhd
new file mode 100755
index 0000000..24c538b
--- /dev/null
+++ b/memorydump_AT27C256R/tb_rs232.vhd
@@ -0,0 +1,105 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:00:19 09/08/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/rs232_1/tbmodule_1.vhd
+-- Project Name: rs232_1
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: module_1
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_rs232 IS END tb_rs232;
+
+ARCHITECTURE behavior OF tb_rs232 IS
+
+ constant NUMBER_BITS : integer := 8;
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT rs232
+ PORT(
+ clk : IN std_logic;
+ rst : IN std_logic;
+ byte_to_send : IN std_logic_vector (NUMBER_BITS-1 downto 0);
+ RsTx : OUT std_logic;
+ RsRx : IN std_logic
+ );
+ END COMPONENT;
+
+ --Inputs
+ signal clk : std_logic;
+ signal rst : std_logic;
+ signal byte_to_send : std_logic_vector (NUMBER_BITS-1 downto 0);
+ signal rx : std_logic;
+
+ --Outputs
+ signal tx : std_logic;
+
+ -- Clock period definitions
+ constant clk_period : time := 20 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: rs232 PORT MAP (
+ clk => clk,
+ rst => rst,
+ byte_to_send => byte_to_send,
+ RsTx => tx,
+ RsRx => rx
+ );
+
+ -- Clock process definitions
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ rst <= '1';
+ wait for 100 ns;
+ rst <= '0';
+ --wait for clk_period*10;
+ -- insert stimulus here
+ byte_to_send <= "10101010";
+ wait for 20 ms;
+ byte_to_send <= "00000000";
+ wait for 20 ms;
+ byte_to_send <= "01010101";
+ wait for 20 ms;
+ byte_to_send <= "11111111";
+ wait for 20 ms;
+
+ wait;
+ end process;
+
+END;
diff --git a/memorydump_AT27C256R/tb_top.vhd b/memorydump_AT27C256R/tb_top.vhd
new file mode 100755
index 0000000..1b29671
--- /dev/null
+++ b/memorydump_AT27C256R/tb_top.vhd
@@ -0,0 +1,110 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:29:18 02/24/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/logicanalyser/tb_top.vhd
+-- Project Name: logicanalyser
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_top IS
+END tb_top;
+
+ARCHITECTURE behavior OF tb_top IS
+
+ -- Constants
+ constant G_BOARD_CLOCK : integer := 50_000_000;
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT top
+ PORT(
+ clk : IN std_logic;
+ btn0 : IN std_logic;
+ RsTx : OUT std_logic;
+ JA : INOUT std_logic_vector(1 downto 0);
+ JB : INOUT std_logic_vector(7 downto 0);
+ JC : INOUT std_logic_vector(6 downto 0);
+ JD : INOUT std_logic_vector(7 downto 0)
+ );
+ END COMPONENT;
+
+ --Inputs
+ signal clk : std_logic := '0';
+ signal rst : std_logic := '0';
+ signal RsRx : std_logic := '0';
+ signal JA : std_logic_vector(1 downto 0) := (others => '0');
+ signal JB : std_logic_vector(7 downto 0) := (others => '0');
+ signal JC : std_logic_vector(6 downto 0) := (others => '0');
+ signal JD : std_logic_vector(7 downto 0) := (others => '0');
+
+ --Outputs
+ signal RsTx : std_logic;
+
+ -- Clock period definitions
+ constant clk_period : time := (1_000_000_000/G_BOARD_CLOCK) * 1 ns;
+
+ signal finish_simulation : std_logic := '0';
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut_top : top
+ PORT MAP (
+ clk => clk,
+ btn0 => rst,
+ RsTx => RsTx,
+ JA => JA,
+ JB => JB,
+ JC => JC,
+ JD => JD
+ );
+
+ -- Clock process definitions
+ clk_process :process
+ begin
+ while finish_simulation = '0' loop
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end loop;
+ wait;
+ end process;
+
+ rst <= '1', '0' after clk_period;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- insert stimulus here
+
+ wait;
+ end process;
+
+END;
diff --git a/memorydump_AT27C256R/tb_top.wcfg b/memorydump_AT27C256R/tb_top.wcfg
new file mode 100755
index 0000000..0061939
--- /dev/null
+++ b/memorydump_AT27C256R/tb_top.wcfg
@@ -0,0 +1,260 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ tb
+ label
+
+ clk
+ clk
+
+
+ rst
+ rst
+
+
+ rsrx
+ rsrx
+
+
+ ja[1:0]
+ ja[1:0]
+
+
+ jb[7:0]
+ jb[7:0]
+
+
+ jc[6:0]
+ jc[6:0]
+
+
+ jd[7:0]
+ jd[7:0]
+
+
+ rstx
+ rstx
+
+
+ finish_simulation
+ finish_simulation
+
+
+ g_board_clock
+ g_board_clock
+
+
+ clk_period
+ clk_period
+
+
+
+ top
+ label
+
+ clk
+ clk
+
+
+ btn0
+ btn0
+
+
+ rstx
+ rstx
+
+
+ ja[1:0]
+ ja[1:0]
+
+
+ jb[7:0]
+ jb[7:0]
+
+
+ jc[6:0]
+ jc[6:0]
+
+
+ jd[7:0]
+ jd[7:0]
+
+
+ reset
+ reset
+
+
+ busy
+ busy
+
+
+ ready
+ ready
+
+
+ enable
+ enable
+
+
+ data_in[7:0]
+ data_in[7:0]
+
+
+ state
+ state
+
+
+ memory_address_out[14:0]
+ memory_address_out[14:0]
+
+
+ memory_address[14:0]
+ memory_address[14:0]
+
+
+ memory_address_max[14:0]
+ memory_address_max[14:0]
+
+
+ memory_data_in[7:0]
+ memory_data_in[7:0]
+
+
+ memory_ce
+ memory_ce
+
+
+ memory_oe
+ memory_oe
+
+
+ memory_enable
+ memory_enable
+
+
+ memory_read
+ memory_read
+
+
+ memory_busy
+ memory_busy
+
+
+
+ mm
+ label
+
+ i_clock
+ i_clock
+
+
+ i_reset
+ i_reset
+
+
+ i_enable
+ i_enable
+
+
+ i_read
+ i_read
+
+
+ o_busy
+ o_busy
+
+
+ i_memadr[14:0]
+ i_memadr[14:0]
+
+
+ io_memoe
+ io_memoe
+
+
+ io_ramcs
+ io_ramcs
+
+
+ io_memadr[14:0]
+ io_memadr[14:0]
+
+
+ cstate
+ cstate
+
+
+ memoe
+ memoe
+
+
+ ramcs
+ ramcs
+
+
+ memadr[14:0]
+ memadr[14:0]
+
+
+
+ uart
+ label
+
+ clk
+ clk
+
+
+ rst
+ rst
+
+
+ enable
+ enable
+
+
+ byte_to_send[7:0]
+ byte_to_send[7:0]
+
+
+ busy
+ busy
+
+
+ ready
+ ready
+
+
+ rstx
+ rstx
+
+
+ clk_div1
+ clk_div1
+
+
+ c_state
+ c_state
+
+
+ g_board_clock
+ g_board_clock
+
+
+ g_baud_rate
+ g_baud_rate
+
+
+
diff --git a/memorydump_AT27C256R/top.vhd b/memorydump_AT27C256R/top.vhd
new file mode 100755
index 0000000..ce333d8
--- /dev/null
+++ b/memorydump_AT27C256R/top.vhd
@@ -0,0 +1,238 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 10:15:50 01/29/2021
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_constants.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top is
+Port (
+ clk : in STD_LOGIC;
+ btn0 : in STD_LOGIC;
+ RsTx : out STD_LOGIC;
+ JA : inout STD_LOGIC_VECTOR(1 downto 0);
+ JB : inout STD_LOGIC_VECTOR(7 downto 0);
+ JC : inout STD_LOGIC_VECTOR(6 downto 0);
+ JD : inout STD_LOGIC_VECTOR(7 downto 0)
+);
+end top;
+
+architecture Behavioral of top is
+
+ COMPONENT rs232 is
+ GENERIC (
+ G_BOARD_CLOCK : integer := G_BOARD_CLOCK;
+ G_BAUD_RATE : integer := G_BAUD_RATE
+ );
+ PORT(
+ clk : IN std_logic;
+ rst : IN std_logic;
+ enable : in STD_LOGIC;
+ byte_to_send : IN std_logic_vector (NUMBER_BITS-1 downto 0);
+ busy : OUT std_logic;
+ ready : OUT std_logic;
+ RsTx : OUT std_logic
+ );
+ END COMPONENT rs232;
+
+ COMPONENT memorymodule IS
+ Port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_enable : in std_logic;
+ i_read : in std_logic;
+ o_busy : out std_logic;
+ i_MemAdr : in MemoryAddressALL;
+ io_MemOE : out std_logic;
+ io_RamCS : out std_logic;
+ io_MemAdr : out MemoryAddressALL
+ );
+ END COMPONENT memorymodule;
+
+ signal reset : std_logic;
+ signal busy,ready : std_logic;
+ signal enable : std_logic;
+ signal data_in : MemoryDataByte;
+
+-- -- XXX test pattern
+-- constant ARRAY_LENGTH : integer := 11;
+-- type ARRAY_BYTES is array(0 to ARRAY_LENGTH-1) of std_logic_vector(NUMBER_BITS-1 downto 0);
+-- signal bytes : ARRAY_BYTES := (x"30",x"31",x"32",x"33",x"34",x"35",x"36",x"37",x"38",x"39",x"20");
+
+ type state_type is (
+ st_memory_enable,
+ st_memory_read_enable,
+ st_memory_wait0,
+ st_memory_read_disable,
+ st_memory_disable,
+ st_send,
+ st_increment,
+ st_waiting,
+ st_increment_address,
+ st_stop);
+ signal state : state_type := st_memory_enable;
+
+ signal memory_address_out,memory_address,memory_address_max : MemoryAddressALL;
+ signal memory_data_in : MemoryDataByte;
+ signal memory_ce : std_logic;
+ signal memory_oe : std_logic;
+ signal memory_enable,memory_read,memory_busy : std_logic;
+
+begin
+
+ reset <= btn0;
+
+ JA(0) <= memory_ce;
+ JA(1) <= memory_oe;
+ memory_data_in(0) <= JD(0);
+ memory_data_in(1) <= JD(1);
+ memory_data_in(2) <= JD(2);
+ memory_data_in(3) <= JD(3);
+ memory_data_in(4) <= JD(4);
+ memory_data_in(5) <= JD(5);
+ memory_data_in(6) <= JD(6);
+ memory_data_in(7) <= JD(7);
+ JB(0) <= memory_address_out(0);
+ JB(1) <= memory_address_out(1);
+ JB(2) <= memory_address_out(2);
+ JB(3) <= memory_address_out(3);
+ JB(4) <= memory_address_out(4);
+ JB(5) <= memory_address_out(5);
+ JB(6) <= memory_address_out(6);
+ JB(7) <= memory_address_out(7);
+ JC(0) <= memory_address_out(8);
+ JC(1) <= memory_address_out(9);
+ JC(2) <= memory_address_out(10);
+ JC(3) <= memory_address_out(11);
+ JC(4) <= memory_address_out(12);
+ JC(5) <= memory_address_out(13);
+ JC(6) <= memory_address_out(14);
+
+ mm: memorymodule
+ PORT MAP (
+ i_clock => clk,
+ i_reset => reset,
+ i_enable => memory_enable,
+ i_read => memory_read,
+ o_busy => memory_busy,
+ i_MemAdr => memory_address,
+ io_MemOE => memory_oe,
+ io_RamCS => memory_ce,
+ io_MemAdr => memory_address_out
+ );
+
+ uut_rs232 : rs232
+ GENERIC MAP (
+ G_BOARD_CLOCK => G_BOARD_CLOCK,
+ G_BAUD_RATE => G_BAUD_RATE
+ )
+ PORT MAP (
+ clk => clk,
+ rst => reset,
+ enable => enable,
+ byte_to_send => data_in,
+ busy => busy,
+ ready => ready,
+ RsTx => RsTx
+ );
+
+ p0 : process (clk,reset) is
+-- variable index : integer range 0 to ARRAY_LENGTH-1 := 0; -- XXX test pattern
+ begin
+ if (reset = '1') then
+-- index := 0; -- XXX test pattern
+ state <= st_memory_enable;
+ enable <= '0';
+ memory_address_max <= (others => '1');
+ memory_address <= (others => '0');
+ memory_enable <= '0';
+ memory_read <= '0';
+ elsif (rising_edge(clk)) then
+ case (state) is
+ when st_memory_enable =>
+ state <= st_memory_read_enable;
+ memory_enable <= '1';
+ when st_memory_read_enable =>
+ state <= st_memory_wait0;
+ memory_read <= '1';
+ when st_memory_wait0 =>
+ if (memory_busy = '1') then
+ state <= st_memory_wait0;
+ else
+ state <= st_memory_read_disable;
+ end if;
+ when st_memory_read_disable =>
+ state <= st_memory_disable;
+ memory_read <= '0';
+ when st_memory_disable =>
+ state <= st_send;
+ memory_enable <= '0';
+-- memory_data_in <= not bytes(index); -- XXX test pattern
+ when st_send =>
+ --REPORT integer'image(G_BOARD_CLOCK) SEVERITY NOTE;
+ enable <= '1';
+ if (ready = '1') then
+-- data_in <= not bytes(index); -- XXX test pattern
+-- data_in <= memory_data_in; -- XXX test pattern
+ data_in <= not memory_data_in;
+ state <= st_increment;
+ else
+ state <= st_send;
+ end if;
+ when st_increment =>
+ if (ready = '0') then
+ state <= st_waiting;
+-- if (index < ARRAY_LENGTH-1) then -- XXX test pattern
+-- index := index + 1;
+-- else
+-- index := 0;
+-- end if;
+ else
+ state <= st_increment;
+ end if;
+ when st_waiting =>
+ if (busy = '1') then
+ enable <= '0';
+ state <= st_waiting;
+ else
+ state <= st_increment_address;
+ end if;
+ when st_increment_address =>
+ if (memory_address = std_logic_vector(to_unsigned(to_integer(unsigned(memory_address_max) - 1),G_MemoryAddress))) then
+ state <= st_stop;
+ else
+ memory_address <= std_logic_vector(to_unsigned(to_integer(unsigned(memory_address) + 1),G_MemoryAddress));
+ state <= st_memory_enable;
+ end if;
+ when st_stop =>
+ state <= st_stop;
+ end case;
+ end if;
+ end process p0;
+
+end Behavioral;
diff --git a/memorydump_AT27C256R/upload.sh b/memorydump_AT27C256R/upload.sh
new file mode 100755
index 0000000..05cabe9
--- /dev/null
+++ b/memorydump_AT27C256R/upload.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
+
+impact -batch impact_top.ipf
diff --git a/memorymodule/Nexys2_1200General.ucf b/memorymodule/Nexys2_1200General.ucf
new file mode 100755
index 0000000..1758dca
--- /dev/null
+++ b/memorymodule/Nexys2_1200General.ucf
@@ -0,0 +1,250 @@
+## This file is a general .ucf for Nexys2 rev A board
+## To use it in a project:
+## - remove or comment the lines corresponding to unused pins
+## - rename the used signals according to the project
+
+## Signals Led<7>Led<4> are assigned to pins which change type from s3e500 to other dies using the same package
+## Both versions are provided in this file.
+## Keep only the appropriate one, and remove or comment the other one.
+
+
+## Clock pin for Nexys 2 Board
+NET "i_clock" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
+#NET "clk1" LOC = "U9"; # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK, Sch name = GCLK1
+
+## onBoard USB controller
+## NOTE: DEPP and DSTM net names use some of the same pins, if trying to use both DEPP and DSTM use a signle net name for each shared pin.
+
+## Data bus for both the DEPP and DSTM interfaces uncomment lines 19-26 if using either one
+#NET "DB<0>" LOC = "R14"; # Bank = 2, Pin name = IO_L24N_2/A20, Type = DUAL, Sch name = U-FD0
+#NET "DB<1>" LOC = "R13"; # Bank = 2, Pin name = IO_L22N_2/A22, Type = DUAL, Sch name = U-FD1
+#NET "DB<2>" LOC = "P13"; # Bank = 2, Pin name = IO_L22P_2/A23, Type = DUAL, Sch name = U-FD2
+#NET "DB<3>" LOC = "T12"; # Bank = 2, Pin name = IO_L20P_2, Type = I/O, Sch name = U-FD3
+#NET "DB<4>" LOC = "N11"; # Bank = 2, Pin name = IO_L18N_2, Type = I/O, Sch name = U-FD4
+#NET "DB<5>" LOC = "R11"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = U-FD5
+#NET "DB<6>" LOC = "P10"; # Bank = 2, Pin name = IO_L15N_2/D1/GCLK3, Type = DUAL/GCLK, Sch name = U-FD6
+#NET "DB<7>" LOC = "R10"; # Bank = 2, Pin name = IO_L15P_2/D2/GCLK2, Type = DUAL/GCLK, Sch name = U-FD7
+
+## If using the DEPP interface uncomment lines 29-32
+#NET "EppWRITE" LOC = "V16"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-FLAGC
+#NET "EppASTB" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
+#NET "EppDSTB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
+#NET "EppWAIT" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
+
+## If using the DSTM interface uncomment lines 35-44
+#NET "DstmIFCLK" LOC = "T15"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = U-IFCLK
+#NET "DstmSLCS" LOC = "T16"; # Bank = 2, Pin name = IO_L26P_2/VS0/A17, Type = DUAL, Sch name = U-SLCS
+#NET "DstmFLAGA" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
+#NET "DstmFLAGB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
+#NET "DstmADR<0>" LOC = "T14"; # Bank = 2, Pin name = IO_L24P_2/A21, Type = DUAL, Sch name = U-FIFOAD0
+#NET "DstmADR<1>" LOC = "V13"; # Bank = 2, Pin name = IO_L19N_2/VREF_2, Type = VREF, Sch name = U-FIFOAD1
+#NET "DstmSLRD" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
+#NET "DstmSLWR" LOC = "V9"; # Bank = 2, Pin name = IO_L13N_2/D3/GCLK15, Type = DUAL/GCLK, Sch name = U-SLWR
+#NET "DstmSLOE" LOC = "V15"; # Bank = 2, Pin name = IO_L25P_2/VS2/A19, Type = DUAL, Sch name = U-SLOE
+#NET "DstmPKTEND" LOC = "V12"; # Bank = 2, Pin name = IO_L19P_2, Type = I/O, Sch name = U-PKTEND
+
+#NET "UsbMode" LOC = "U15"; # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type = DUAL, Sch name = U-INT0#
+#NET "UsbRdy" LOC = "U13"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-RDY
+
+## onBoard Cellular RAM and StrataFlash
+NET "io_MemOE" LOC = "T2"; # Bank = 3, Pin name = IO_L24P_3, Type = I/O, Sch name = OE
+NET "io_MemWR" LOC = "N7"; # Bank = 2, Pin name = IO_L07P_2, Type = I/O, Sch name = WE
+
+NET "io_RamAdv" LOC = "J4"; # Bank = 3, Pin name = IO_L11N_3/LHCLK1, Type = LHCLK, Sch name = MT-ADV
+NET "io_RamCS" LOC = "R6"; # Bank = 2, Pin name = IO_L05P_2, Type = I/O, Sch name = MT-CE
+NET "io_RamClk" LOC = "H5"; # Bank = 3, Pin name = IO_L08N_3, Type = I/O, Sch name = MT-CLK
+NET "io_RamCRE" LOC = "P7"; # Bank = 2, Pin name = IO_L07N_2, Type = I/O, Sch name = MT-CRE
+NET "io_RamLB" LOC = "K5"; # Bank = 3, Pin name = IO_L14N_3/LHCLK7, Type = LHCLK, Sch name = MT-LB
+NET "io_RamUB" LOC = "K4"; # Bank = 3, Pin name = IO_L13N_3/LHCLK5, Type = LHCLK, Sch name = MT-UB
+NET "io_RamWait" LOC = "F5"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = MT-WAIT
+
+#NET "FlashRp" LOC = "T5"; # Bank = 2, Pin name = IO_L04N_2, Type = I/O, Sch name = RP#
+#NET "FlashCS" LOC = "R5"; # Bank = 2, Pin name = IO_L04P_2, Type = I/O, Sch name = ST-CE
+#NET "FlashStSts" LOC = "D3"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = ST-STS
+
+NET "io_MemAdr<1>" LOC = "J1"; # Bank = 3, Pin name = IO_L12P_3/LHCLK2, Type = LHCLK, Sch name = ADR1
+NET "io_MemAdr<2>" LOC = "J2"; # Bank = 3, Pin name = IO_L12N_3/LHCLK3/IRDY2, Type = LHCLK, Sch name = ADR2
+NET "io_MemAdr<3>" LOC = "H4"; # Bank = 3, Pin name = IO_L09P_3, Type = I/O, Sch name = ADR3
+NET "io_MemAdr<4>" LOC = "H1"; # Bank = 3, Pin name = IO_L10N_3, Type = I/O, Sch name = ADR4
+NET "io_MemAdr<5>" LOC = "H2"; # Bank = 3, Pin name = IO_L10P_3, Type = I/O, Sch name = ADR5
+NET "io_MemAdr<6>" LOC = "J5"; # Bank = 3, Pin name = IO_L11P_3/LHCLK0, Type = LHCLK, Sch name = ADR6
+NET "io_MemAdr<7>" LOC = "H3"; # Bank = 3, Pin name = IO_L09N_3, Type = I/O, Sch name = ADR7
+NET "io_MemAdr<8>" LOC = "H6"; # Bank = 3, Pin name = IO_L08P_3, Type = I/O, Sch name = ADR8
+NET "io_MemAdr<9>" LOC = "F1"; # Bank = 3, Pin name = IO_L05P_3, Type = I/O, Sch name = ADR9
+NET "io_MemAdr<10>" LOC = "G3"; # Bank = 3, Pin name = IO_L06P_3, Type = I/O, Sch name = ADR10
+NET "io_MemAdr<11>" LOC = "G6"; # Bank = 3, Pin name = IO_L07P_3, Type = I/O, Sch name = ADR11
+NET "io_MemAdr<12>" LOC = "G5"; # Bank = 3, Pin name = IO_L07N_3, Type = I/O, Sch name = ADR12
+NET "io_MemAdr<13>" LOC = "G4"; # Bank = 3, Pin name = IO_L06N_3/VREF_3, Type = VREF, Sch name = ADR13
+NET "io_MemAdr<14>" LOC = "F2"; # Bank = 3, Pin name = IO_L05N_3, Type = I/O, Sch name = ADR14
+NET "io_MemAdr<15>" LOC = "E1"; # Bank = 3, Pin name = IO_L03N_3, Type = I/O, Sch name = ADR15
+NET "io_MemAdr<16>" LOC = "M5"; # Bank = 3, Pin name = IO_L19P_3, Type = I/O, Sch name = ADR16
+NET "io_MemAdr<17>" LOC = "E2"; # Bank = 3, Pin name = IO_L03P_3, Type = I/O, Sch name = ADR17
+NET "io_MemAdr<18>" LOC = "C2"; # Bank = 3, Pin name = IO_L01N_3, Type = I/O, Sch name = ADR18
+NET "io_MemAdr<19>" LOC = "C1"; # Bank = 3, Pin name = IO_L01P_3, Type = I/O, Sch name = ADR19
+NET "io_MemAdr<20>" LOC = "D2"; # Bank = 3, Pin name = IO_L02N_3/VREF_3, Type = VREF, Sch name = ADR20
+NET "io_MemAdr<21>" LOC = "K3"; # Bank = 3, Pin name = IO_L13P_3/LHCLK4/TRDY2, Type = LHCLK, Sch name = ADR21
+NET "io_MemAdr<22>" LOC = "D1"; # Bank = 3, Pin name = IO_L02P_3, Type = I/O, Sch name = ADR22
+NET "io_MemAdr<23>" LOC = "K6"; # Bank = 3, Pin name = IO_L14P_3/LHCLK6, Type = LHCLK, Sch name = ADR23
+
+NET "io_MemDB<0>" LOC = "L1"; # Bank = 3, Pin name = IO_L15P_3, Type = I/O, Sch name = DB0
+NET "io_MemDB<1>" LOC = "L4"; # Bank = 3, Pin name = IO_L16N_3, Type = I/O, Sch name = DB1
+NET "io_MemDB<2>" LOC = "L6"; # Bank = 3, Pin name = IO_L17P_3, Type = I/O, Sch name = DB2
+NET "io_MemDB<3>" LOC = "M4"; # Bank = 3, Pin name = IO_L18P_3, Type = I/O, Sch name = DB3
+NET "io_MemDB<4>" LOC = "N5"; # Bank = 3, Pin name = IO_L20N_3, Type = I/O, Sch name = DB4
+NET "io_MemDB<5>" LOC = "P1"; # Bank = 3, Pin name = IO_L21N_3, Type = I/O, Sch name = DB5
+NET "io_MemDB<6>" LOC = "P2"; # Bank = 3, Pin name = IO_L21P_3, Type = I/O, Sch name = DB6
+NET "io_MemDB<7>" LOC = "R2"; # Bank = 3, Pin name = IO_L23N_3, Type = I/O, Sch name = DB7
+NET "io_MemDB<8>" LOC = "L3"; # Bank = 3, Pin name = IO_L16P_3, Type = I/O, Sch name = DB8
+NET "io_MemDB<9>" LOC = "L5"; # Bank = 3, Pin name = IO_L17N_3/VREF_3, Type = VREF, Sch name = DB9
+NET "io_MemDB<10>" LOC = "M3"; # Bank = 3, Pin name = IO_L18N_3, Type = I/O, Sch name = DB10
+NET "io_MemDB<11>" LOC = "M6"; # Bank = 3, Pin name = IO_L19N_3, Type = I/O, Sch name = DB11
+NET "io_MemDB<12>" LOC = "L2"; # Bank = 3, Pin name = IO_L15N_3, Type = I/O, Sch name = DB12
+NET "io_MemDB<13>" LOC = "N4"; # Bank = 3, Pin name = IO_L20P_3, Type = I/O, Sch name = DB13
+NET "io_MemDB<14>" LOC = "R3"; # Bank = 3, Pin name = IO_L23P_3, Type = I/O, Sch name = DB14
+NET "io_MemDB<15>" LOC = "T1"; # Bank = 3, Pin name = IO_L24N_3, Type = I/O, Sch name = DB15
+
+## 7 segment display
+NET "o_seg<0>" LOC = "L18"; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA
+NET "o_seg<1>" LOC = "F18"; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB
+NET "o_seg<2>" LOC = "D17"; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC
+NET "o_seg<3>" LOC = "D16"; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD
+NET "o_seg<4>" LOC = "G14"; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE
+NET "o_seg<5>" LOC = "J17"; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
+NET "o_seg<6>" LOC = "H14"; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG
+NET "o_dp" LOC = "C17"; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP
+
+NET "o_an<0>" LOC = "F17"; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0
+NET "o_an<1>" LOC = "H17"; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1
+NET "o_an<2>" LOC = "C18"; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2
+NET "o_an<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3
+
+## Leds
+NET "o_Led<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
+NET "o_Led<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
+NET "o_Led<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
+NET "o_Led<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
+#NET "Led<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4? s3e500 only
+#NET "Led<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5? s3e500 only
+#NET "Led<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6? s3e500 only
+#NET "Led<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7? s3e500 only
+NET "o_Led<4>" LOC = "E16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD4? other than s3e500
+NET "o_Led<5>" LOC = "P16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD5? other than s3e500
+NET "o_Led<6>" LOC = "E4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD6? other than s3e500
+NET "o_Led<7>" LOC = "P4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD7? other than s3e500
+
+## Switches
+NET "i_sw<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
+NET "i_sw<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
+NET "i_sw<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
+NET "i_sw<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
+NET "i_sw<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
+NET "i_sw<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
+NET "i_sw<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
+NET "i_sw<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7
+
+## Buttons
+NET "i_btn<0>" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
+NET "i_btn<1>" LOC = "D18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = BTN1
+NET "i_btn<2>" LOC = "E18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN2
+NET "i_btn<3>" LOC = "H13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN3
+
+## VGA Connector
+#NET "vgaRed<1>" LOC = "R9"; # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0
+#NET "vgaRed<2>" LOC = "T8"; # Bank = 2, Pin name = IO_L10N_2, Type = I/O, Sch name = RED1
+#NET "vgaRed<3>" LOC = "R8"; # Bank = 2, Pin name = IO_L10P_2, Type = I/O, Sch name = RED2
+#NET "vgaGreen<1>" LOC = "N8"; # Bank = 2, Pin name = IO_L09N_2, Type = I/O, Sch name = GRN0
+#NET "vgaGreen<2>" LOC = "P8"; # Bank = 2, Pin name = IO_L09P_2, Type = I/O, Sch name = GRN1
+#NET "vgaGreen<3>" LOC = "P6"; # Bank = 2, Pin name = IO_L05N_2, Type = I/O, Sch name = GRN2
+#NET "vgaBlue<2>" LOC = "U5"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = BLU1
+#NET "vgaBlue<3>" LOC = "U4"; # Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DUAL, Sch name = BLU2
+
+#NET "Hsync" LOC = "T4"; # Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type = DUAL, Sch name = HSYNC
+#NET "Vsync" LOC = "U3"; # Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUAL, Sch name = VSYNC
+
+## PS/2 connector
+#NET "PS2C" LOC = "R12"; # Bank = 2, Pin name = IO_L20N_2, Type = I/O, Sch name = PS2C
+#NET "PS2D" LOC = "P11"; # Bank = 2, Pin name = IO_L18P_2, Type = I/O, Sch name = PS2D
+
+## FX2 connector
+#NET "PIO<0>" LOC = "B4"; # Bank = 0, Pin name = IO_L24N_0, Type = I/O, Sch name = R-IO1
+#NET "PIO<1>" LOC = "A4"; # Bank = 0, Pin name = IO_L24P_0, Type = I/O, Sch name = R-IO2
+#NET "PIO<2>" LOC = "C3"; # Bank = 0, Pin name = IO_L25P_0, Type = I/O, Sch name = R-IO3
+#NET "PIO<3>" LOC = "C4"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO4
+#NET "PIO<4>" LOC = "B6"; # Bank = 0, Pin name = IO_L20P_0, Type = I/O, Sch name = R-IO5
+#NET "PIO<5>" LOC = "D5"; # Bank = 0, Pin name = IO_L23N_0/VREF_0, Type = VREF, Sch name = R-IO6
+#NET "PIO<6>" LOC = "C5"; # Bank = 0, Pin name = IO_L23P_0, Type = I/O, Sch name = R-IO7
+#NET "PIO<7>" LOC = "F7"; # Bank = 0, Pin name = IO_L19P_0, Type = I/O, Sch name = R-IO8
+#NET "PIO<8>" LOC = "E7"; # Bank = 0, Pin name = IO_L19N_0/VREF_0, Type = VREF, Sch name = R-IO9
+#NET "PIO<9>" LOC = "A6"; # Bank = 0, Pin name = IO_L20N_0, Type = I/O, Sch name = R-IO10
+#NET "PIO<10>" LOC = "C7"; # Bank = 0, Pin name = IO_L18P_0, Type = I/O, Sch name = R-IO11
+#NET "PIO<11>" LOC = "F8"; # Bank = 0, Pin name = IO_L17N_0, Type = I/O, Sch name = R-IO12
+#NET "PIO<12>" LOC = "D7"; # Bank = 0, Pin name = IO_L18N_0/VREF_0, Type = VREF, Sch name = R-IO13
+#NET "PIO<13>" LOC = "E8"; # Bank = 0, Pin name = IO_L17P_0, Type = I/O, Sch name = R-IO14
+#NET "PIO<14>" LOC = "E9"; # Bank = 0, Pin name = IO_L15P_0, Type = I/O, Sch name = R-IO15
+#NET "PIO<15>" LOC = "C9"; # Bank = 0, Pin name = IO_L14P_0/GCLK10, Type = GCLK, Sch name = R-IO16
+#NET "PIO<16>" LOC = "A8"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO17
+#NET "PIO<17>" LOC = "G9"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO18
+#NET "PIO<18>" LOC = "F9"; # Bank = 0, Pin name = IO_L15N_0, Type = I/O, Sch name = R-IO19
+#NET "PIO<19>" LOC = "D10"; # Bank = 0, Pin name = IO_L11P_0/GCLK4, Type = GCLK, Sch name = R-IO20
+#NET "PIO<20>" LOC = "A10"; # Bank = 0, Pin name = IO_L12N_0/GCLK7, Type = GCLK, Sch name = R-IO21
+#NET "PIO<21>" LOC = "B10"; # Bank = 0, Pin name = IO_L12P_0/GCLK6, Type = GCLK, Sch name = R-IO22
+#NET "PIO<22>" LOC = "A11"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO23
+#NET "PIO<23>" LOC = "D11"; # Bank = 0, Pin name = IO_L09N_0, Type = I/O, Sch name = R-IO24
+#NET "PIO<24>" LOC = "E10"; # Bank = 0, Pin name = IO_L11N_0/GCLK5, Type = GCLK, Sch name = R-IO25
+#NET "PIO<25>" LOC = "B11"; # Bank = 0, Pin name = IO/VREF_0, Type = VREF, Sch name = R-IO26
+#NET "PIO<26>" LOC = "C11"; # Bank = 0, Pin name = IO_L09P_0, Type = I/O, Sch name = R-IO27
+#NET "PIO<27>" LOC = "E11"; # Bank = 0, Pin name = IO_L08P_0, Type = I/O, Sch name = R-IO28
+#NET "PIO<28>" LOC = "F11"; # Bank = 0, Pin name = IO_L08N_0, Type = I/O, Sch name = R-IO29
+#NET "PIO<29>" LOC = "E12"; # Bank = 0, Pin name = IO_L06N_0, Type = I/O, Sch name = R-IO30
+#NET "PIO<30>" LOC = "F12"; # Bank = 0, Pin name = IO_L06P_0, Type = I/O, Sch name = R-IO31
+#NET "PIO<31>" LOC = "A13"; # Bank = 0, Pin name = IO_L05P_0, Type = I/O, Sch name = R-IO32
+#NET "PIO<32>" LOC = "B13"; # Bank = 0, Pin name = IO_L05N_0/VREF_0, Type = VREF, Sch name = R-IO33
+#NET "PIO<33>" LOC = "E13"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO34
+#NET "PIO<34>" LOC = "A14"; # Bank = 0, Pin name = IO_L04N_0, Type = I/O, Sch name = R-IO35
+#NET "PIO<35>" LOC = "C14"; # Bank = 0, Pin name = IO_L03N_0/VREF_0, Type = VREF, Sch name = R-IO36
+#NET "PIO<36>" LOC = "D14"; # Bank = 0, Pin name = IO_L03P_0, Type = I/O, Sch name = R-IO37
+#NET "PIO<37>" LOC = "B14"; # Bank = 0, Pin name = IO_L04P_0, Type = I/O, Sch name = R-IO38
+#NET "PIO<38>" LOC = "A16"; # Bank = 0, Pin name = IO_L01N_0, Type = I/O, Sch name = R-IO39
+#NET "PIO<39>" LOC = "B16"; # Bank = 0, Pin name = IO_L01P_0, Type = I/O, Sch name = R-IO40
+
+## 12 pin connectors
+
+##JA
+#NET "JA<0>" LOC = "L15"; # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1
+#NET "JA<1>" LOC = "K12"; # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2
+#NET "JA<2>" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
+#NET "JA<3>" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
+#NET "JA<4>" LOC = "K13"; # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL, Sch name = JA7
+#NET "JA<5>" LOC = "L16"; # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL, Sch name = JA8
+#NET "JA<6>" LOC = "M14"; # Bank = 1, Pin name = IO_L05P_1, Type = I/O, Sch name = JA9
+#NET "JA<7>" LOC = "M16"; # Bank = 1, Pin name = IO_L07N_1, Type = I/O, Sch name = JA10
+
+##JB
+#NET "JB<0>" LOC = "M13"; # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF, Sch name = JB1
+#NET "JB<1>" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
+#NET "JB<2>" LOC = "R15"; # Bank = 1, Pin name = IO_L03P_1, Type = I/O, Sch name = JB3
+#NET "JB<3>" LOC = "T17"; # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL, Sch name = JB4
+#NET "JB<4>" LOC = "P17"; # Bank = 1, Pin name = IO_L06P_1, Type = I/O, Sch name = JB7
+#NET "JB<5>" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
+#NET "JB<6>" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
+#NET "JB<7>" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
+
+##JC
+#NET "JC<0>" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
+#NET "JC<1>" LOC = "J16"; # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL, Sch name = JC2
+#NET "JC<2>" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
+#NET "JC<3>" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
+#NET "JC<4>" LOC = "H15"; # Bank = 1, Pin name = IO_L17N_1, Type = I/O, Sch name = JC7
+#NET "JC<5>" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
+#NET "JC<6>" LOC = "G16"; # Bank = 1, Pin name = IO_L18N_1, Type = I/O, Sch name = JC9
+#NET "JC<7>" LOC = "J12"; # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL, Sch name = JC10
+
+##JD - NOTE: For other JD pins see LD(3:0) above under "Leds"
+#NET "JD<0>" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
+#NET "JD<1>" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
+#NET "JD<2>" LOC = "N18"; # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3
+#NET "JD<3>" LOC = "P18"; # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4
+
+## RS232 connector
+#NET "RsRx" LOC = "U6"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = RS-RX
+#NET "RsTx" LOC = "P9"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = RS-TX
diff --git a/memorymodule/clock_divider.vhd b/memorymodule/clock_divider.vhd
new file mode 100755
index 0000000..41a82f9
--- /dev/null
+++ b/memorymodule/clock_divider.vhd
@@ -0,0 +1,65 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:42:10 09/18/2020
+-- Design Name:
+-- Module Name: clock_divider - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_globals.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_divider is
+Generic (
+ g_board_clock : integer := G_BOARD_CLOCK;
+ g_divider : integer
+);
+Port (
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+);
+end clock_divider;
+
+architecture Behavioral of clock_divider is
+ constant clock_divider : integer := g_board_clock / g_divider;
+begin
+
+p0 : process (i_clock) is
+ variable clock_out : std_logic;
+ variable counter : integer := 0;
+begin
+ if (rising_edge(i_clock)) then
+ if (counter = clock_divider-1) then
+ clock_out := '1';
+ counter := 0;
+ else
+ clock_out := '0';
+ counter := counter + 1;
+ end if;
+ end if;
+ o_clock <= clock_out;
+end process p0;
+
+end Behavioral;
+
diff --git a/memorymodule/impact_top.ipf b/memorymodule/impact_top.ipf
new file mode 100755
index 0000000..2ee5452
--- /dev/null
+++ b/memorymodule/impact_top.ipf
@@ -0,0 +1,8 @@
+setMode -bs
+setCable -port auto
+Identify -inferir
+identifyMPM
+assignFile -p 1 -file top.bit
+Program -p 1
+closeCable
+quit
diff --git a/memorymodule/isim.cmd b/memorymodule/isim.cmd
new file mode 100755
index 0000000..fff18e8
--- /dev/null
+++ b/memorymodule/isim.cmd
@@ -0,0 +1,3 @@
+onerror {resume}
+wave add /
+run 1000 ns;
diff --git a/memorymodule/lcd_display.vhd b/memorymodule/lcd_display.vhd
new file mode 100755
index 0000000..a5c11b6
--- /dev/null
+++ b/memorymodule/lcd_display.vhd
@@ -0,0 +1,130 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:24:00 11/28/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/memorymodule/lcd_display.vhd
+-- Project Name: memorymodule
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_globals.ALL;
+use WORK.p_lcd_display.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity lcd_display is
+Generic (
+ LCDClockDivider : integer := G_LCDClockDivider
+);
+Port (
+ i_clock : in std_logic;
+ i_LCDChar : LCDHex;
+ o_anode : out std_logic_vector(G_LCDAnode-1 downto 0);
+ o_segment : out std_logic_vector(G_LCDSegment-1 downto 0)
+);
+end lcd_display;
+
+architecture Behavioral of lcd_display is
+
+ component clock_divider is
+ Generic(
+ g_board_clock : integer;
+ g_divider : integer
+ );
+ Port(
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+ );
+ end component clock_divider;
+ for all : clock_divider use entity work.clock_divider(Behavioral);
+
+ signal clock_divider_1 : std_logic;
+
+begin
+
+ c_clock_divider_1 : clock_divider
+ Generic Map (
+ g_board_clock => G_BOARD_CLOCK,
+ g_divider => LCDClockDivider
+ )
+ Port Map (
+ i_clock => i_clock,
+ o_clock => clock_divider_1
+ );
+
+ p0 : process (clock_divider_1) is
+ variable count : integer range 0 to G_LCDAnode := 0;
+ begin
+ if (rising_edge(clock_divider_1)) then
+ case count is
+ when 0 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "0111";
+ when 1 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1011";
+ when 2 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1101";
+ when 3 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1110";
+ when others =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1111";
+ end case;
+ if (count < G_LCDAnode-1) then
+ count := count + 1;
+ else
+ count := 0;
+ end if;
+ end if;
+ end process p0;
+
+ p1 : process (clock_divider_1) is
+ variable count : integer range 0 to G_LCDAnode := 0;
+ begin
+ if (rising_edge(clock_divider_1)) then
+ case to_integer(unsigned(i_LCDChar(count))) is
+ when 0 => o_segment <= "1000000"; -- 0
+ when 1 => o_segment <= "1111001"; -- 1
+ when 2 => o_segment <= "0100100"; -- 2
+ when 3 => o_segment <= "0110000"; -- 3
+ when 4 => o_segment <= "0011001"; -- 4
+ when 5 => o_segment <= "0010010"; -- 5
+ when 6 => o_segment <= "0000010"; -- 6
+ when 7 => o_segment <= "1111000"; -- 7
+ when 8 => o_segment <= "0000000"; -- 8
+ when 9 => o_segment <= "0010000"; -- 9
+ when 10 => o_segment <= "0001000"; -- a
+ when 11 => o_segment <= "0000011"; -- b
+ when 12 => o_segment <= "1000110"; -- c
+ when 13 => o_segment <= "0100001"; -- d
+ when 14 => o_segment <= "0000110"; -- e
+ when 15 => o_segment <= "0001110"; -- f
+ when others => null;
+ end case;
+ if (count < G_LCDAnode-1) then
+ count := count + 1;
+ else
+ count := 0;
+ end if;
+ end if;
+ end process p1;
+
+end Behavioral;
+
diff --git a/memorymodule/memorymodule.vhd b/memorymodule/memorymodule.vhd
new file mode 100755
index 0000000..133b199
--- /dev/null
+++ b/memorymodule/memorymodule.vhd
@@ -0,0 +1,54 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:11:00 11/28/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/memorymodule/memorymodule.vhd
+-- Project Name: memorymodule
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+-- use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity memorymodule is
+Port (
+i_clk : in std_logic;
+MemOE : inout std_logic;
+MemWR : inout std_logic;
+RamAdv : inout std_logic;
+RamCS : inout std_logic;
+RamClk : inout std_logic;
+RamCRE : inout std_logic;
+RamLB : inout std_logic;
+RamUB : inout std_logic;
+RamWait : inout std_logic;
+MemAdr : inout std_logic_vector(23 downto 0);
+MemDB : inout std_logic_vector(15 downto 0)
+);
+end memorymodule;
+
+architecture Behavioral of memorymodule is
+
+begin
+
+end Behavioral;
+
diff --git a/memorymodule/p_globals.vhd b/memorymodule/p_globals.vhd
new file mode 100755
index 0000000..fc4728e
--- /dev/null
+++ b/memorymodule/p_globals.vhd
@@ -0,0 +1,22 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package p_globals is
+
+ constant G_BOARD_CLOCK : integer := 50_000_000;
+ constant G_LCDSegment : integer := 7;
+ constant G_LCDAnode : integer := 4;
+ constant G_LCDClockDivider : integer := 200;
+ constant G_MemoryAddress : integer := 24;
+ constant G_MemoryData : integer := 16;
+ constant G_Switch : integer := 8;
+ constant G_Button : integer := 4;
+ constant G_Led : integer := 8;
+ constant G_HalfHex : integer := 4;
+ constant G_FullHex : integer := G_HalfHex*2;
+
+end p_globals;
+
+package body p_globals is
+end p_globals;
+
diff --git a/memorymodule/p_lcd_display.vhd b/memorymodule/p_lcd_display.vhd
new file mode 100755
index 0000000..7bcf763
--- /dev/null
+++ b/memorymodule/p_lcd_display.vhd
@@ -0,0 +1,13 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use WORK.p_globals.ALL;
+
+package p_lcd_display is
+
+ type LCDHex is array(G_LCDAnode-1 downto 0) of std_logic_vector(G_HalfHex-1 downto 0);
+
+end p_lcd_display;
+
+package body p_lcd_display is
+end p_lcd_display;
+
diff --git a/memorymodule/simulate-tb_top.sh b/memorymodule/simulate-tb_top.sh
new file mode 100755
index 0000000..8deb2eb
--- /dev/null
+++ b/memorymodule/simulate-tb_top.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+PROJECT="tb_top"
+fuse -intstyle ise -incremental -o ./${PROJECT}_isim_beh.exe -prj ./${PROJECT}_beh.prj work.${PROJECT}
+./${PROJECT}_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb ./${PROJECT}_isim.beh.wdb -view ./${PROJECT}.wcfg
diff --git a/memorymodule/synthesis-top.sh b/memorymodule/synthesis-top.sh
new file mode 100755
index 0000000..5326064
--- /dev/null
+++ b/memorymodule/synthesis-top.sh
@@ -0,0 +1,48 @@
+#!/bin/sh
+
+mkdir -p xst/projnav.tmp/
+
+xst -intstyle ise -ifn ./top.xst -ofn ./top.syr
+if [ $? -ne 0 ];
+then
+ echo "error on xst";
+ exit;
+else
+ ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Nexys2_1200General.ucf -p xc3s1200e-fg320-4 top.ngc top.ngd
+ if [ $? -ne 0 ];
+ then
+ echo "error on ngdbuild";
+ exit;
+ else
+ map -intstyle ise -p xc3s1200e-fg320-4 -ol std -timing -cm balanced -ir off -pr off -o top_map.ncd top.ngd top.pcf
+ if [ $? -ne 0 ];
+ then
+ echo "error on map";
+ exit;
+ else
+ par -w -intstyle ise -ol std -rl std -t 1 top_map.ncd top.ncd top.pcf
+ if [ $? -ne 0 ];
+ then
+ echo "error on par";
+ exit;
+ else
+ trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf -ucf Nexys2_1200General.ucf
+ if [ $? -ne 0 ];
+ then
+ echo "error on trce";
+ exit;
+ else
+ bitgen -intstyle ise -f top.ut top.ncd
+ if [ $? -ne 0 ];
+ then
+ echo "error on bitgen";
+ exit;
+ else
+ ls -l top.bit
+ fi
+ fi
+ fi
+ fi
+ fi
+fi
+
diff --git a/memorymodule/tb_top.vhd b/memorymodule/tb_top.vhd
new file mode 100755
index 0000000..ab49410
--- /dev/null
+++ b/memorymodule/tb_top.vhd
@@ -0,0 +1,122 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:34:00 11/28/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/memorymodule/tb_top.vhd
+-- Project Name: memorymodule
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE WORK.p_globals.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_top IS
+END tb_top;
+
+ARCHITECTURE behavior OF tb_top IS
+
+ component top is
+ Generic (
+ g_board_clock : integer := G_BOARD_CLOCK;
+ g_clock_divider : integer := 100;
+ g_lcd_clock_divider : integer := 50_000_000
+ );
+ Port (
+ i_clock : in std_logic;
+ io_MemOE : inout std_logic;
+ io_MemWR : inout std_logic;
+ io_RamAdv : inout std_logic;
+ io_RamCS : inout std_logic;
+ io_RamClk : inout std_logic;
+ io_RamCRE : inout std_logic;
+ io_RamLB : inout std_logic;
+ io_RamUB : inout std_logic;
+ io_RamWait : inout std_logic;
+ io_MemAdr : inout std_logic_vector(G_MemoryAddress-1 downto 0);
+ io_MemDB : inout std_logic_vector(G_MemoryData-1 downto 0);
+ i_sw : in std_logic_vector(G_Switch-1 downto 0);
+ i_btn : in std_logic_vector(G_Button-1 downto 0);
+ o_seg : out std_logic_vector(G_LCDSegment-1 downto 0);
+ o_dp : out std_logic;
+ o_an : out std_logic_vector(G_LCDAnode-1 downto 0);
+ o_Led : out std_logic_vector(G_Led-1 downto 0)
+ );
+ end component top;
+ for all : top use entity WORK.top(Behavioral);
+
+ constant clk_period : time := (1_000_000_000 / G_BOARD_CLOCK) * 1 ns;
+
+ signal clk : std_logic := '0';
+ signal sw : std_logic_vector(G_Switch-1 downto 0);
+ signal btn : std_logic_vector(G_Button-1 downto 0);
+ signal seg : std_logic_vector(G_LCDSegment-1 downto 0);
+ signal dp : std_logic;
+ signal an : std_logic_vector(G_LCDAnode-1 downto 0);
+ signal Led : std_logic_vector(G_Led-1 downto 0);
+
+BEGIN
+
+ uut : top
+ Port Map (
+ i_clock => clk,
+ io_MemOE => open,
+ io_MemWR => open,
+ io_RamAdv => open,
+ io_RamCS => open,
+ io_RamClk => open,
+ io_RamCRE => open,
+ io_RamLB => open,
+ io_RamUB => open,
+ io_RamWait => open,
+ io_MemAdr => open,
+ io_MemDB => open,
+ i_sw => sw,
+ i_btn => btn,
+ o_seg => seg,
+ o_dp => dp,
+ o_an => an,
+ o_Led => led
+ );
+
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ -- wait for 100 ns;
+ -- wait for clk_period*10;
+ -- insert stimulus here
+ wait;
+ end process;
+
+END;
+
diff --git a/memorymodule/tb_top.wcfg b/memorymodule/tb_top.wcfg
new file mode 100755
index 0000000..6cd294c
--- /dev/null
+++ b/memorymodule/tb_top.wcfg
@@ -0,0 +1,130 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ i_clock
+ i_clock
+
+
+ o_clock
+ o_clock
+
+
+ o_seg[6:0]
+ o_seg[6:0]
+
+
+ o_an[3:0]
+ o_an[3:0]
+
+
+ lcdchar[3:0]
+ lcdchar[3:0]
+ HEXRADIX
+
+
+ io_memoe
+ io_memoe
+
+
+ io_memwr
+ io_memwr
+
+
+ io_ramadv
+ io_ramadv
+
+
+ io_ramcs
+ io_ramcs
+
+
+ io_ramclk
+ io_ramclk
+
+
+ io_ramcre
+ io_ramcre
+
+
+ io_ramlb
+ io_ramlb
+
+
+ io_ramub
+ io_ramub
+
+
+ io_ramwait
+ io_ramwait
+
+
+ io_memadr[23:0]
+ io_memadr[23:0]
+
+
+ io_memdb[15:0]
+ io_memdb[15:0]
+
+
+ i_sw[7:0]
+ i_sw[7:0]
+
+
+ i_btn[3:0]
+ i_btn[3:0]
+
+
+ o_dp
+ o_dp
+
+
+ o_led[7:0]
+ o_led[7:0]
+
+
+ clk
+ clk
+
+
+ sw[7:0]
+ sw[7:0]
+
+
+ btn[3:0]
+ btn[3:0]
+
+
+ seg[6:0]
+ seg[6:0]
+
+
+ dp
+ dp
+
+
+ an[3:0]
+ an[3:0]
+
+
+ led[7:0]
+ led[7:0]
+
+
+ clk_period
+ clk_period
+
+
diff --git a/memorymodule/tb_top_beh.prj b/memorymodule/tb_top_beh.prj
new file mode 100755
index 0000000..52b106a
--- /dev/null
+++ b/memorymodule/tb_top_beh.prj
@@ -0,0 +1,8 @@
+vhdl work "p_globals.vhd"
+vhdl work "clock_divider.vhd"
+vhdl work "p_lcd_display.vhd"
+vhdl work "lcd_display.vhd"
+vhdl work "memorymodule.vhd"
+vhdl work "top.vhd"
+vhdl work "tb_top.vhd"
+
diff --git a/memorymodule/top.prj b/memorymodule/top.prj
new file mode 100755
index 0000000..993b81d
--- /dev/null
+++ b/memorymodule/top.prj
@@ -0,0 +1,7 @@
+vhdl work "p_globals.vhd"
+vhdl work "clock_divider.vhd"
+vhdl work "p_lcd_display.vhd"
+vhdl work "lcd_display.vhd"
+vhdl work "memorymodule.vhd"
+vhdl work "top.vhd"
+
diff --git a/memorymodule/top.ut b/memorymodule/top.ut
new file mode 100755
index 0000000..1c9e99e
--- /dev/null
+++ b/memorymodule/top.ut
@@ -0,0 +1,22 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:1
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:Yes
+-g DriveDone:No
diff --git a/memorymodule/top.vhd b/memorymodule/top.vhd
new file mode 100755
index 0000000..7e24d34
--- /dev/null
+++ b/memorymodule/top.vhd
@@ -0,0 +1,140 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:21:00 11/28/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/memorymodule/top.vhd
+-- Project Name: memorymodule
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_globals.ALL;
+use WORK.p_lcd_display.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top is
+Generic (
+g_board_clock : integer := G_BOARD_CLOCK;
+g_clock_divider : integer := 3;
+g_lcd_clock_divider : integer := G_LCDClockDivider
+);
+Port (
+i_clock : in std_logic;
+io_MemOE : inout std_logic;
+io_MemWR : inout std_logic;
+io_RamAdv : inout std_logic;
+io_RamCS : inout std_logic;
+io_RamClk : inout std_logic;
+io_RamCRE : inout std_logic;
+io_RamLB : inout std_logic;
+io_RamUB : inout std_logic;
+io_RamWait : inout std_logic;
+io_MemAdr : inout std_logic_vector(G_MemoryAddress-1 downto 0);
+io_MemDB : inout std_logic_vector(G_MemoryData-1 downto 0);
+i_sw : in std_logic_vector(G_Switch-1 downto 0);
+i_btn : in std_logic_vector(G_Button-1 downto 0);
+o_seg : out std_logic_vector(G_LCDSegment-1 downto 0);
+o_dp : out std_logic;
+o_an : out std_logic_vector(G_LCDAnode-1 downto 0);
+o_Led : out std_logic_vector(G_Led-1 downto 0)
+);
+end top;
+
+architecture Behavioral of top is
+
+ component clock_divider is
+ Generic (
+ g_divider : integer
+ );
+ Port (
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+ );
+ end component clock_divider;
+ for all : clock_divider use entity WORK.clock_divider(Behavioral);
+
+ component lcd_display is
+ Generic (
+ LCDClockDivider : integer := G_LCDClockDivider
+ );
+ Port (
+ i_clock : in std_logic;
+ i_LCDChar : LCDHex;
+ o_anode : out std_logic_vector(G_LCDAnode-1 downto 0);
+ o_segment : out std_logic_vector(G_LCDSegment-1 downto 0)
+ );
+ end component lcd_display;
+ for all : lcd_display use entity WORK.lcd_display(Behavioral);
+
+ signal LCDChar : LCDHex;
+ signal o_clock : std_logic;
+
+begin
+
+ c_clock_divider : clock_divider
+ Generic Map (
+ g_divider => g_clock_divider
+ )
+ Port Map (
+ i_clock => i_clock,
+ o_clock => o_clock
+ );
+
+ c_lcd_display : lcd_display
+ Port Map (
+ i_clock => i_clock,
+ i_LCDChar => LCDChar,
+ o_anode => o_an,
+ o_segment => o_seg
+ );
+
+ scroll_left : process (o_clock) is
+ type hex_table is array(15 downto 0) of std_logic_vector(G_HalfHex-1 downto 0);
+ variable hex : hex_table := (x"0",x"1",x"2",x"3",x"4",x"5",x"6",x"7",x"8",x"9",x"a",x"b",x"c",x"d",x"e",x"f");
+ variable i : integer range 0 to hex'length := 0;
+ begin
+ if (rising_edge(o_clock)) then
+ if (i < hex'length) then
+ LCDChar <= hex(i)&LCDChar(G_LCDAnode-1 downto 1);
+ i := i + 1;
+ else
+ i := 0;
+ end if;
+ end if;
+ end process scroll_left;
+
+ o_Led <= i_sw;
+ o_dp <= '1'; -- off all dot points
+ io_MemOE <= 'Z';
+ io_MemWR <= 'Z';
+ io_RamAdv <= 'Z';
+ io_RamCS <= 'Z';
+ io_RamClk <= 'Z';
+ io_RamCRE <= 'Z';
+ io_RamLB <= 'Z';
+ io_RamUB <= 'Z';
+ io_RamWait <= 'Z';
+ io_MemDB <= (others => 'Z');
+ io_MemAdr <= (others => 'Z');
+
+end Behavioral;
+
diff --git a/memorymodule/top.xst b/memorymodule/top.xst
new file mode 100755
index 0000000..393111c
--- /dev/null
+++ b/memorymodule/top.xst
@@ -0,0 +1,57 @@
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn top.prj
+-use_new_parser no
+-ifmt mixed
+-ofn top
+-ofmt NGC
+-p xc3s1200e-4-fg320
+-top top
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/memorymodule/upload.sh b/memorymodule/upload.sh
new file mode 100755
index 0000000..05cabe9
--- /dev/null
+++ b/memorymodule/upload.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
+
+impact -batch impact_top.ipf
diff --git a/myown_i2c/FF_D_PE.vhd b/myown_i2c/FF_D_PE.vhd
new file mode 100755
index 0000000..b0a119a
--- /dev/null
+++ b/myown_i2c/FF_D_PE.vhd
@@ -0,0 +1,60 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FF_D_POSITIVE_EDGE is
+port (
+S : in std_logic;
+R : in std_logic;
+C : in std_logic;
+D : in STD_LOGIC;
+Q1,Q2:inout STD_LOGIC);
+end entity FF_D_POSITIVE_EDGE;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Classical_positive-edge-triggered_D_flip-flop
+architecture Behavioral_D_PE of FF_D_POSITIVE_EDGE is
+
+--component GAND is
+--generic (delay_and:time := 0 ns);
+--port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+--end component GAND;
+--component GN is
+--generic (delay_not:time := 0 ns);
+--port (A:in STD_LOGIC;B:out STD_LOGIC);
+--end component GN;
+--for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+--for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+--signal X,Y,Z,V,W,O,sa,sb,sc,sd,se,sf:STD_LOGIC;
+--constant DELAY_AND : time := 1 ps;
+--constant DELAY_NOT : time := 1 ps;
+
+constant WAIT_NAND3 : time := 0 ps;
+signal setu,setd,resetu,resetd : std_logic;
+
+begin
+
+--rst1 <= D when i_reset = '0' else '0';
+--g1: GAND generic map (DELAY_AND) port map (rst1,X,sa);
+--g2: GN generic map (DELAY_NOT) port map(sa,Y);
+--g3: GAND generic map (DELAY_AND) port map (Y,O,sb);
+--g4: GN generic map (DELAY_NOT) port map(sb,X);
+--rst2 <= C when i_reset = '0' else '0';
+--g5: GAND generic map (DELAY_AND) port map (rst2,V,sc);
+--g6: GN generic map (DELAY_NOT) port map(sc,Z);
+--g7: GAND generic map (DELAY_AND) port map (Z,Y,sd);
+--g8: GN generic map (DELAY_NOT) port map(sd,V);
+--rst3 <= Q2 when i_reset = '0' else '0';
+--g9: GAND generic map (DELAY_AND) port map (Z,rst3,se);
+--gA: GN generic map (DELAY_NOT) port map(se,Q1);
+--gB: GAND generic map (DELAY_AND) port map (X,Q1,sf);
+--gC: GN generic map (DELAY_NOT) port map(sf,Q2);
+--gD: GAND generic map (DELAY_AND) port map (C,Z,O);
+
+-- https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29#/media/File:Edge_triggered_D_flip_flop_with_set_and_reset.svg
+g1 : Q1 <= not (S and setd and Q2) after 0 ps;
+g2 : Q2 <= not (Q1 and resetu and R) after 1 ns;
+g3 : setu <= not (S and resetd and setd) after 0 ps;
+g4 : setd <= not (setu and C and R) after 1 ns;
+g5 : resetu <= not (setd and C and resetd) after 1 ns;
+g6 : resetd <= not (resetu and D and R) after 1 ns;
+
+end architecture Behavioral_D_PE;
diff --git a/myown_i2c/FF_E_LATCH.vhd b/myown_i2c/FF_E_LATCH.vhd
new file mode 100755
index 0000000..7b35eba
--- /dev/null
+++ b/myown_i2c/FF_E_LATCH.vhd
@@ -0,0 +1,95 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FF_E_LATCH is
+generic (
+delay_and : time := 0 ns;
+delay_and3 : time := 0 ns;
+delay_not : time := 0 ns;
+delay_nand2 : time := 0 ns;
+delay_nand3 : time := 0 ns
+);
+port (D,E_H,E_L:in STD_LOGIC;Q:out STD_LOGIC);
+end entity FF_E_LATCH;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Earle_latch
+architecture Behavioral_E_LATCH of FF_E_LATCH is
+component GAND is
+generic (delay_and : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GAND3 is
+generic (delay_and3 : time := 0 ns);
+port (A,B,C:in STD_LOGIC;D:out STD_LOGIC);
+end component GAND3;
+component GN is
+generic (delay_not : time := 0 ns);
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GAND3 use entity WORK.GATE_AND3(GATE_AND3_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc,sd,se,sf,sg,sh,si:STD_LOGIC;
+signal qout : std_logic;
+begin
+Q <= qout;
+g1: GAND generic map (delay_and) port map (A => E_H, B => D, C => sa);
+g2: GN generic map (delay_not) port map (A => sa, B => sb);
+g3: GAND generic map (delay_and) port map (A => D, B => qout, C => sc);
+g4: GN generic map (delay_not) port map (A => sc, B =>sd);
+g5: GAND generic map (delay_and) port map (A => qout, B => E_L, C => se);
+g6: GN generic map (delay_not) port map (A => se, B => sf);
+g7: GAND3 generic map (delay_and3) port map (A => sb, B => sd, C => sf, D => sh);
+g8: GN generic map (delay_not) port map (A => sh, B => qout);
+end architecture Behavioral_E_LATCH;
+
+architecture LUT_E_LATCH of FF_E_LATCH is
+component GAND is
+generic (delay_and : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GAND3 is
+generic (delay_and3 : time := 0 ns);
+port (A,B,C:in STD_LOGIC;D:out STD_LOGIC);
+end component GAND3;
+component GN is
+generic (delay_not : time := 0 ns);
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_LUT);
+for all : GAND3 use entity WORK.GATE_AND3(GATE_AND3_LUT);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_LUT);
+signal sa,sb,sc,sd,se,sf,sg,sh,si:STD_LOGIC;
+signal qout : std_logic;
+begin
+Q <= qout;
+g1: GAND generic map (delay_and) port map (A => E_H, B => D, C => sa);
+g2: GN generic map (delay_not) port map (A => sa, B => sb);
+g3: GAND generic map (delay_and) port map (A => D, B => qout, C => sc);
+g4: GN generic map (delay_not) port map (A => sc, B => sd);
+g5: GAND generic map (delay_and) port map (A => qout, B => E_L, C => se);
+g6: GN generic map (delay_not) port map (A => se, B => sf);
+g7: GAND3 generic map (delay_and3) port map (A => sb, B => sd, C => sf, D => sh);
+g8: GN generic map (delay_not) port map (A => sh, B => qout);
+end architecture LUT_E_LATCH;
+
+architecture LUT_E_LATCH_NAND of FF_E_LATCH is
+component GNAND2 is
+generic (delay_nand2 : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GNAND2;
+component GNAND3 is
+generic (delay_nand3 : time := 0 ns);
+port (A,B,C:in STD_LOGIC;D:out STD_LOGIC);
+end component GNAND3;
+for all : GNAND2 use entity WORK.GATE_NAND2(GATE_NAND2_LUT);
+for all : GNAND3 use entity WORK.GATE_NAND3(GATE_NAND3_LUT);
+signal sb,sd,sf:STD_LOGIC := '0';
+signal qout : std_logic;
+begin
+Q <= qout;
+g1: GNAND2 generic map (delay_nand2) port map (A => E_H, B => D, C => sb);
+g2: GNAND2 generic map (delay_nand2) port map (A => D, B => qout, C => sd);
+g3: GNAND2 generic map (delay_nand2) port map (A => qout, B => E_L, C => sf);
+g4: GNAND3 generic map (delay_nand3) port map (A => sb, B => sd, C => sf, D => qout);
+end architecture LUT_E_LATCH_NAND;
diff --git a/myown_i2c/FF_JK.vhd b/myown_i2c/FF_JK.vhd
new file mode 100755
index 0000000..d852ae4
--- /dev/null
+++ b/myown_i2c/FF_JK.vhd
@@ -0,0 +1,380 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity FF_JK is
+generic (
+ delay_and : time := 0 ns;
+ delay_nand : time := 0 ns;
+ delay_nand3 : time := 0 ns;
+ delay_nand4 : time := 0 ns;
+ delay_not : time := 0 ns
+);
+port (
+ i_r : in STD_LOGIC;
+ J,K,C : in STD_LOGIC;
+ Q1 : out STD_LOGIC;
+ Q2 : out STD_LOGIC
+);
+end entity FF_JK;
+
+architecture LUT of FF_JK is
+
+-- constant W_NOT : time := delay_not;
+-- constant W_NAND2 : time := 0 ns;
+-- constant W_NAND3 : time := delay_nand3;
+-- constant W_NAND4 : time := delay_nand4;
+ constant W_Q1MS : time := 1 ns; -- XXX fix metastable
+ constant W_Q2MS : time := 0 ns; -- XXX fix metastable
+-- constant W_C : time := 0 ns;
+-- constant W_NOTC : time := 0 ns;
+-- constant W_J : time := 0 ns;
+-- constant W_K : time := 0 ns;
+
+ signal sa,sb,sc,sd : std_logic;
+ signal se,sg : std_logic;
+ signal sh,sj : std_logic;
+ signal sk,sn : std_logic;
+ signal so,sp : std_logic;
+ signal sr,ss : std_logic;
+ signal st,su : std_logic;
+ signal sw,sx : std_logic;
+ signal sy,sz : std_logic;
+ signal i_rb : std_logic;
+ signal q1out : std_logic;
+ signal q2out : std_logic;
+
+ component GATE_AND is
+ generic (
+ delay_and : TIME := 0 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_AND;
+-- for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+ for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_LUT);
+
+ component GATE_NAND is
+ Generic (
+ DELAY_NAND : time := 0 ns
+ );
+ Port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_NAND;
+-- for all : GATE_NAND use entity WORK.GATE_NAND(GATE_NAND_BEHAVIORAL_1);
+ for all : GATE_NAND use entity WORK.GATE_NAND(GATE_NAND_LUT);
+
+ component GATE_NAND3 is
+ Generic (
+ DELAY_NAND3 : time := 0 ns
+ );
+ Port (
+ A,B,C : in STD_LOGIC;
+ D : out STD_LOGIC
+ );
+ end component GATE_NAND3;
+-- for all : GATE_NAND3 use entity WORK.GATE_NAND3(GATE_NAND3_BEHAVIORAL_1);
+ for all : GATE_NAND3 use entity WORK.GATE_NAND3(GATE_NAND3_LUT);
+
+ component GATE_NAND4 is
+ Generic (
+ DELAY_NAND4 : time := 0 ns
+ );
+ Port (
+ A,B,C,D : in STD_LOGIC;
+ E : out STD_LOGIC
+ );
+ end component GATE_NAND4;
+-- for all : GATE_NAND4 use entity WORK.GATE_NAND4(GATE_NAND4_BEHAVIORAL_1);
+ for all : GATE_NAND4 use entity WORK.GATE_NAND4(GATE_NAND4_LUT);
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 0 ns
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+-- for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+begin
+
+ Q1 <= q1out after W_Q1MS;
+ Q2 <= q2out after W_Q2MS;
+
+-- sa <= C after W_C;
+ -- clock bar
+ clock_b : GATE_NOT GENERIC MAP (delay_not => delay_not)
+ PORT MAP (A=>C,B=>sb);
+-- sb <= not C after W_NOTC;
+-- sc <= j after W_J;
+-- sd <= k after W_K;
+
+ -- reset bar
+ i_rbar : GATE_NOT GENERIC MAP (delay_not => delay_not)
+ PORT MAP (A=>i_r,B=>i_rb);
+
+ -- nand3 1u plus i_r bar
+ nand3_1u : GATE_NAND4 GENERIC MAP (delay_nand4 => delay_nand4)
+ PORT MAP (A=>C,B=>j,C=>q2out,D=>i_rb,E=>sg);
+-- se <= not (sa and sc and q2 and not i_r);
+-- sg <= se after W_NAND3;
+
+ -- nand3 1d
+ nand3_1d : GATE_NAND3 GENERIC MAP (delay_nand3 => delay_nand3)
+ PORT MAP (A=>C,B=>k,C=>q1out,D=>sj);
+-- sh <= not (sa and sd and q1);
+-- sj <= sh after W_NAND3;
+
+ -- nand2 1u
+ nand2_1u_1 : GATE_NAND GENERIC MAP (delay_nand => delay_nand)
+ PORT MAP (A=>sg,B=>sp,C=>sn);
+-- sk <= sg nand sp;
+-- sn <= sk after W_NAND2;
+
+ -- nand2 1d plus i_r bar
+ nand2_1d_1 : GATE_NAND3 GENERIC MAP (delay_nand3 => delay_nand3)
+ PORT MAP (A=>sj,B=>sn,C=>i_rb,D=>sp);
+-- so <= not (sj and sn and not i_r);
+-- sp <= so after 1 ns;
+
+ -- nand2 1u
+ nand2_1u_2 : GATE_NAND GENERIC MAP (delay_nand => delay_nand)
+ PORT MAP (A=>sn,B=>sb,C=>ss);
+-- sr <= sn nand sb;
+-- ss <= sr after W_NAND2;
+
+ -- nand2 1d
+ nand2_1d_2 : GATE_NAND GENERIC MAP (delay_nand => delay_nand)
+ PORT MAP (A=>sp,B=>sb,C=>su);
+-- st <= sp nand sb;
+-- su <= st after W_NAND2;
+
+ -- nand2 q1
+ nand2_q1 : GATE_NAND GENERIC MAP (delay_nand => delay_nand)
+ PORT MAP (A=>ss,B=>q2out,C=>sx);
+-- sw <= ss nand q2;
+-- sx <= sw after 1 ns;
+
+ -- nand2 q2
+ nand2_q2 : GATE_NAND GENERIC MAP (delay_nand => delay_nand)
+ PORT MAP (A=>su,B=>q1out,C=>sz);
+-- sy <= su nand q1;
+-- sz <= sy after W_NAND2;
+
+ q1_out : GATE_AND GENERIC MAP (delay_and => W_Q1MS)
+ PORT MAP (A=>sx,B=>i_rb,C=>q1out);
+-- q1 <= sx and not i_r after 1 ns; -- XXX metastable
+-- q2_out : BUF PORT MAP (I=>sz,O=>q2);
+-- q2 <= sz after W_Q2MS;
+
+ q2_out : GATE_AND GENERIC MAP (delay_and => W_Q2MS)
+ PORT MAP (A=>sz,B=>i_rb,C=>q2out);
+
+end architecture LUT;
+
+--architecture structural of FF_JK is
+-- constant W_NAND2 : time := 0 ns;
+-- constant W_NAND3 : time := 0 ns;
+-- constant W_Q1MS : time := 0 ns;
+-- constant W_Q2MS : time := 0 ns;
+-- constant W_C : time := 0 ns;
+-- constant W_NOTC : time := 0 ns;
+-- constant W_J : time := 0 ns;
+-- constant W_K : time := 0 ns;
+--
+-- signal sa,sb,sc,sd : std_logic := '0';
+-- signal se,sg : std_logic := '0';
+-- signal sh,sj : std_logic := '0';
+-- signal sk,sn : std_logic := '0';
+-- signal so,sp : std_logic := '0';
+-- signal sr,ss : std_logic := '0';
+-- signal st,su : std_logic := '0';
+-- signal sw,sx : std_logic := '0';
+-- signal sy,sz : std_logic := '0';
+--begin
+--
+-- sa <= C after W_C;
+-- sb <= not C after W_NOTC;
+-- sc <= j after W_J;
+-- sd <= k after W_K;
+--
+-- -- nand3 1u
+-- se <= not (sa and sc and q2 and not i_r);
+-- sg <= se after W_NAND3;
+--
+-- -- nand3 1d
+-- sh <= not (sa and sd and q1);
+-- sj <= sh after W_NAND3;
+--
+-- -- nand2 1u
+-- sk <= sg nand sp;
+-- sn <= sk after W_NAND2;
+--
+-- -- nand2 1d
+-- so <= not (sj and sn and not i_r);
+-- sp <= so after 1 ns;
+--
+-- -- nand2 1u
+-- sr <= sn nand sb;
+-- ss <= sr after W_NAND2;
+--
+-- -- nand2 1d
+-- st <= sp nand sb;
+-- su <= st after W_NAND2;
+--
+-- -- nand2 q1
+-- sw <= ss nand q2;
+-- sx <= sw after 1 ns;
+--
+-- -- nand2 q2
+-- sy <= su nand q1;
+-- sz <= sy after W_NAND2;
+--
+-- q1 <= sx and not i_r after 1 ns; -- XXX metastable
+-- q2 <= sz after W_Q2MS;
+--
+--end architecture Structural;
+
+---- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#JK_flip-flop
+---- XXX strange operation
+--architecture Behavioral_FF_JK of FF_JK is
+--component GAND is
+--port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+--end component GAND;
+--component FF_SR_NOR is
+--port (S,R:in STD_LOGIC;Q1,Q2:inout STD_LOGIC);
+--end component FF_SR_NOR;
+----component GNOT is
+----generic (delay_not : TIME := 0 ns);
+----port (A:in STD_LOGIC;B:out STD_LOGIC);
+----end component GNOT;
+----for all : GNOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+--for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+--for all : FF_SR_NOR use entity WORK.FF_SR(Behavioral_NOR);
+----for all : FF_SR_NOR use entity WORK.FF_SR(Behavioral_NAND);
+----for all : FF_SR_NOR use entity WORK.FF_SR(Behavioral_ANDOR);
+----for all : FF_SR_NOR use entity WORK.FF_SR(Behavioral_NOT_S_NOT_R);
+--signal sa,sb,sc,sd: STD_LOGIC;
+----signal n1,n2 : STD_LOGIC;
+--begin
+--g1: GAND port map (K,C,sa);
+--g2: GAND port map (sa,Q1,sb);
+----gn1 : GNOT port map (sb,n1);
+--g3: GAND port map (C,J,sc);
+--g4: GAND port map (sc,Q2,sd);
+----gn2 : GNOT port map (sd,n2);
+--g5: FF_SR_NOR port map (sb,sd,Q1,Q2);
+--end architecture Behavioral_FF_JK;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#JK_flip-flop
+--architecture Structural of FF_JK is
+--component GAND is port (A,B:in STD_LOGIC;C:out STD_LOGIC); end component GAND;
+--component GOR is port (A,B:in STD_LOGIC;C:out STD_LOGIC); end component GOR;
+--component GNOT is port (A:in STD_LOGIC;B:out STD_LOGIC); end component GNOT;
+--for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+--for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+--for all : GNOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+--signal sa,sb,sc,sd,se,sf,sg,sh,si,sj : std_logic;
+--begin
+--g1 : GAND port map (J,C,sa);
+--g2 : GAND port map (K,C,sb);
+--
+--g3 : GAND port map (sa,Q2,sc);
+--
+--g4 : GNOT port map (sb,sd);
+--g5 : GAND port map (sd,Q1,se);
+--
+--g6 : GOR port map (sc,se,sf);
+--g7 : GNOT port map (sf,sg);
+--Q1 <= sf;
+--Q2 <= sg;
+--end architecture Structural;
+
+--architecture Structural of FF_JK is
+----component GAND is port (A,B:in STD_LOGIC;C:out STD_LOGIC); end component GAND;
+----component GOR is port (A,B:in STD_LOGIC;C:out STD_LOGIC); end component GOR;
+----component GNOT is port (A:in STD_LOGIC;B:out STD_LOGIC); end component GNOT;
+----for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+----for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+----for all : GNOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+--signal sa,sb,sc,sd,se,sf,sg,sh,si,sj : std_logic := '0';
+--constant clock_period : time := 1 ns;
+--begin
+--g1 : sa <= J and C;
+--sb <= sa and Q2 after clock_period;
+--
+--g2 : sc <= K and C;
+--sd <= sc and Q1 after clock_period;
+--
+--g3 : se <= sb nor Q2 after clock_period;
+--
+--g4 : sf <= sd nor Q1 after clock_period;
+--
+--Q1 <= se;
+--Q2 <= sf;
+--end architecture Structural;
+
+
+
+-- p0 : process (C,j,k,q1,q2) is
+-- variable sa,sb,sc,sd : std_logic;
+-- variable se,sf,sg : std_logic;
+-- variable sh,si,sj : std_logic;
+-- variable sk,sn : std_logic;
+-- variable so,sp : std_logic := '0';
+-- variable sr,ss : std_logic := '0';
+-- variable st,su : std_logic;
+-- variable sw,sx : std_logic;
+-- variable sy,sz : std_logic;
+-- begin
+-- sa := C;
+-- sb := not C;
+-- sc := j;
+-- sd := k;
+--
+-- -- nand3 1u
+-- se := sa and sc;
+-- sf := se and q2;
+-- sg := not sf;
+--
+-- -- nand3 1d
+-- sh := sa and sd;
+-- si := sh and q1;
+-- sj := not si;
+--
+-- -- nand2 1u
+-- sk := sg and sp;
+-- sn := not sk;
+--
+-- -- nand2 1d
+-- so := sj and sn;
+-- sp := not so;
+--
+-- -- nand2 1u
+-- sr := sn and sb;
+-- ss := not sr;
+--
+-- -- nand2 1d
+-- st := sp and sb;
+-- su := not st;
+--
+-- -- nand2 q1
+-- sw := ss and q2;
+-- sx := not sw;
+--
+-- -- nand2 q2
+-- sy := su and q1;
+-- sz := not sy;
+--
+-- q1 <= sx;
+-- q2 <= sy;
+-- end process p0;
diff --git a/myown_i2c/MUX_21.vhd b/myown_i2c/MUX_21.vhd
new file mode 100755
index 0000000..1dcc3c6
--- /dev/null
+++ b/myown_i2c/MUX_21.vhd
@@ -0,0 +1,41 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity MUX_21 is
+generic (
+delay_and : TIME := 0 ns;
+delay_or : TIME := 0 ns;
+delay_not : TIME := 0 ns
+);
+port (
+S,A,B:in STD_LOGIC;
+C:out STD_LOGIC
+);
+end entity MUX_21;
+
+architecture MUX_21_LUT_1 of MUX_21 is
+component GATE_AND is
+generic (delay_and : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GATE_AND;
+component GATE_OR is
+generic (delay_or : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GATE_OR;
+component GATE_NOT is
+generic (delay_not : time := 0 ns);
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GATE_NOT;
+--for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_LUT);
+--for all : GATE_OR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+for all : GATE_OR use entity WORK.GATE_OR(GATE_OR_LUT);
+--for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+signal sa,sb,sc : STD_LOGIC;
+begin
+g1: GATE_NOT generic map (delay_not) port map (S,sa);
+g3: GATE_AND generic map (delay_and) port map (B,S,sb);
+g4: GATE_AND generic map (delay_and) port map (A,sa,sc);
+g5: GATE_OR generic map (delay_or) port map (sb,sc,C);
+end architecture MUX_21_LUT_1;
diff --git a/myown_i2c/MUX_41.vhd b/myown_i2c/MUX_41.vhd
new file mode 100755
index 0000000..c1c722f
--- /dev/null
+++ b/myown_i2c/MUX_41.vhd
@@ -0,0 +1,76 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:36:59 01/18/2022
+-- Design Name:
+-- Module Name: MUX_41 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity MUX_41 is
+generic (
+delay_and : TIME := 0 ns;
+delay_or : TIME := 0 ns;
+delay_not : TIME := 0 ns
+);
+port (
+S1,S2,A,B,C,D:in STD_LOGIC;
+E:out STD_LOGIC
+);
+end MUX_41;
+
+architecture Behavioral of MUX_41 is
+
+ component MUX_21 is
+ generic (
+ delay_and : TIME := 0 ns;
+ delay_or : TIME := 0 ns;
+ delay_not : TIME := 0 ns
+ );
+ port (
+ S,A,B:in STD_LOGIC;
+ C:out STD_LOGIC
+ );
+ end component MUX_21;
+ for all : MUX_21 use entity WORK.MUX_21(MUX_21_LUT_1);
+
+ signal m1_out,m2_out : std_logic;
+
+begin
+
+ m1 : MUX_21
+ generic map (delay_and => delay_and, delay_or => delay_or, delay_not => delay_not)
+ port map (S => S1, A => A, B => B, C => m1_out);
+
+ m2 : MUX_21
+ generic map (delay_and => delay_and, delay_or => delay_or, delay_not => delay_not)
+ port map (S => S1, A => C, B => D, C => m2_out);
+
+ mout : MUX_21
+ generic map (delay_and => delay_and, delay_or => delay_or, delay_not => delay_not)
+ port map (S => S2, A => m1_out, B => m2_out, C => E);
+
+end Behavioral;
+
diff --git a/myown_i2c/MUX_81.vhd b/myown_i2c/MUX_81.vhd
new file mode 100755
index 0000000..41edbfb
--- /dev/null
+++ b/myown_i2c/MUX_81.vhd
@@ -0,0 +1,90 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:45:09 01/20/2022
+-- Design Name:
+-- Module Name: MUX_81 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity MUX_81 is
+generic (
+delay_and : TIME := 0 ns;
+delay_or : TIME := 0 ns;
+delay_not : TIME := 0 ns
+);
+port (
+signal in0,in1,in2,in3,in4,in5,in6,in7 : in std_logic;
+signal s0,s1,s2 : in std_logic;
+signal o : out std_logic
+);
+end MUX_81;
+
+architecture Behavioral of MUX_81 is
+
+ component MUX_21 is
+ generic (
+ delay_and : TIME := 0 ns;
+ delay_or : TIME := 0 ns;
+ delay_not : TIME := 0 ns
+ );
+ port (
+ S,A,B:in STD_LOGIC;
+ C:out STD_LOGIC
+ );
+ end component MUX_21;
+ for all : MUX_21 use entity WORK.MUX_21(MUX_21_LUT_1);
+
+ component MUX_41 is
+ generic (
+ delay_and : TIME := 0 ns;
+ delay_or : TIME := 0 ns;
+ delay_not : TIME := 0 ns
+ );
+ port (
+ S1,S2,A,B,C,D:in STD_LOGIC;
+ E:out STD_LOGIC
+ );
+ end component MUX_41;
+ for all : MUX_41 use entity WORK.MUX_41(Behavioral);
+
+ signal m1out,m2out : std_logic;
+
+begin
+
+ m1 : MUX_41
+ generic map (delay_and => delay_and, delay_or => delay_or, delay_not => delay_not)
+ port map (S1 => s0, S2 => s1, A => in0, B => in1, C => in2, D => in3, E => m1out);
+
+ m2 : MUX_41
+ generic map (delay_and => delay_and, delay_or => delay_or, delay_not => delay_not)
+ port map (S1 => s0, S2 => s1, A => in4, B => in5, C => in6, D => in7, E => m2out);
+
+ mout : MUX_21
+ generic map (delay_and => delay_and, delay_or => delay_or, delay_not => delay_not)
+ port map (S => s2, A => m1out, B => m2out, C => o);
+
+end Behavioral;
+
diff --git a/myown_i2c/Nexys2_1200General.ucf b/myown_i2c/Nexys2_1200General.ucf
new file mode 100755
index 0000000..6b1a09e
--- /dev/null
+++ b/myown_i2c/Nexys2_1200General.ucf
@@ -0,0 +1,334 @@
+## This file is a general .ucf for Nexys2 rev A board
+## To use it in a project:
+## - remove or comment the lines corresponding to unused pins
+## - rename the used signals according to the project
+
+## Signals Led<7>Led<4> are assigned to pins which change type from s3e500 to other dies using the same package
+## Both versions are provided in this file.
+## Keep only the appropriate one, and remove or comment the other one.
+
+TIMESPEC TS01 = FROM : FFS : TO : FFS : 0.125 us;
+TIMESPEC TS02 = FROM : PADS : TO : FFS : 0.125 us;
+TIMESPEC TS03 = FROM : FFS : TO : PADS : 0.125 us;
+TIMESPEC TS04 = FROM : PADS : TO : PADS : 0.125 us;
+#TIMESPEC TS05 = FROM : PADS : TO : RAMS : 0.125 us;
+#TIMESPEC TS06 = FROM : RAMS : TO : PADS : 0.125 us;
+
+NET "i_clock" LOC = "B8"; # BOARD CLK
+NET "i_clock" TNM_NET = sys_clk;
+TIMESPEC TS_sys_clk = PERIOD sys_clk 0.125 us HIGH 50%;
+NET "i_reset" LOC = "B18";
+NET "i_reset" TIG;
+NET "i_slave_address<0>" TIG;
+NET "i_slave_address<1>" TIG;
+NET "i_slave_address<2>" TIG;
+NET "i_slave_address<3>" TIG;
+NET "i_slave_address<4>" TIG;
+NET "i_slave_address<5>" TIG;
+NET "i_slave_address<6>" TIG;
+NET "i_slave_rw" TIG;
+NET "i_bytes_to_send<0>" TIG;
+NET "i_bytes_to_send<1>" TIG;
+NET "i_bytes_to_send<2>" TIG;
+NET "i_bytes_to_send<3>" TIG;
+NET "i_bytes_to_send<4>" TIG;
+NET "i_bytes_to_send<5>" TIG;
+NET "i_bytes_to_send<6>" TIG;
+NET "i_bytes_to_send<7>" TIG;
+#NET "i_enable" TIG;
+#NET "o_sda" LOC = "L15";
+#NET "o_Scl" LOC = "K12";
+
+#NET "I_CLOCK" LOC = "B8";
+#NET "O_SDA" LOC = "L15";
+#NET "O_SCL" LOC = "K12";
+#NET "I_RESET" LOC = "B18";
+#NET "I_BUTTON" LOC = "D18";
+
+#NET "I_CLK" LOC = "B8"; # BOARD CLK
+#NET "I_CLK" LOC = "U9"; # SOCKET CLK
+#NET "I_CLK" TNM_NET "I_CLK";
+#TIMESPEC "TS_CLK" = PERIOD "I_CLK" 20 ns HIGH 50%;
+#NET "I_RST" LOC = "B18";
+#NET "I_REFRESH" LOC = "D18";
+#NET "IO_SDA" LOC = "L15";
+#NET "IO_SCL" LOC = "K12";
+
+#INST "c1/Mcount_count_cy<3>11" LOC=SLICE_X56Y116:SLICE_X58Y119;
+#INST "c1/count_cmp_eq0000" LOC=SLICE_X56Y116:SLICE_X58Y119;
+#INST "c1/Mcount_count_xor<0>11" LOC=SLICE_X56Y116:SLICE_X58Y119;
+#INST "c1/count_4" LOC=SLICE_X56Y116:SLICE_X58Y119;
+#INST "c1/count_0" LOC=SLICE_X56Y116:SLICE_X58Y119;
+#INST "c1/count_1" LOC=SLICE_X56Y116:SLICE_X58Y119;
+#INST "c1/count_5" LOC=SLICE_X56Y116:SLICE_X58Y119;
+#INST "c1/count_2" LOC=SLICE_X56Y116:SLICE_X58Y119;
+#INST "c1/count_3" LOC=SLICE_X56Y116:SLICE_X58Y119;
+#INST "c1/count_cmp_eq0000_SW0" LOC=SLICE_X56Y116:SLICE_X58Y119;
+#INST "c1/Mcount_count_xor<4>11" LOC=SLICE_X56Y116:SLICE_X58Y119;
+#INST "c1/Mcount_count_xor<3>112" LOC=SLICE_X56Y116:SLICE_X58Y119;
+#INST "c1/Mcount_count_xor<3>111" LOC=SLICE_X56Y116:SLICE_X58Y119;
+#INST "c1/Mcount_count_xor<1>11" LOC=SLICE_X56Y116:SLICE_X58Y119;
+#INST "c1/Mcount_count_xor<2>11" LOC=SLICE_X56Y116:SLICE_X58Y119;
+#INST "c1/Mcount_count_cy<3>11" LOC=SLICE_X56Y116:SLICE_X58Y119;
+#INST "c1/Mcount_count_xor<5>11" LOC=SLICE_X56Y116:SLICE_X58Y119;
+
+##NET "SDA" PULLUP;
+#NET "O_SCL" LOC = "K12";
+##NET "SCL" PULLUP;
+#NET "I_RESET" LOC = "B18";
+#NET "I_BUTTON" LOC = "D18";
+##NET "BTN_1" PULLUP;
+##NET "BTN_2" LOC = "D18";
+##NET "BTN_2" PULLUP;
+##NET "BTN_3" LOC = "E18";
+##NET "BTN_3" PULLUP;
+##NET "BTN_4" LOC = "H13";
+##NET "BTN_4" PULLUP;
+
+#NET "I_CLK" LOC = "B8";
+#NET "I_RST" LOC = "B18";
+#NET "I_REFRESH" LOC = "D18";
+#NET "IO_SDA" LOC = "L15";
+#NET "IO_SCL" LOC = "K12";
+
+## Clock pin for Nexys 2 Board
+#NET "clk" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
+#NET "clk1" LOC = "U9"; # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK, Sch name = GCLK1
+
+## onBoard USB controller
+## NOTE: DEPP and DSTM net names use some of the same pins, if trying to use both DEPP and DSTM use a signle net name for each shared pin.
+
+## Data bus for both the DEPP and DSTM interfaces uncomment lines 19-26 if using either one
+#NET "DB<0>" LOC = "R14"; # Bank = 2, Pin name = IO_L24N_2/A20, Type = DUAL, Sch name = U-FD0
+#NET "DB<1>" LOC = "R13"; # Bank = 2, Pin name = IO_L22N_2/A22, Type = DUAL, Sch name = U-FD1
+#NET "DB<2>" LOC = "P13"; # Bank = 2, Pin name = IO_L22P_2/A23, Type = DUAL, Sch name = U-FD2
+#NET "DB<3>" LOC = "T12"; # Bank = 2, Pin name = IO_L20P_2, Type = I/O, Sch name = U-FD3
+#NET "DB<4>" LOC = "N11"; # Bank = 2, Pin name = IO_L18N_2, Type = I/O, Sch name = U-FD4
+#NET "DB<5>" LOC = "R11"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = U-FD5
+#NET "DB<6>" LOC = "P10"; # Bank = 2, Pin name = IO_L15N_2/D1/GCLK3, Type = DUAL/GCLK, Sch name = U-FD6
+#NET "DB<7>" LOC = "R10"; # Bank = 2, Pin name = IO_L15P_2/D2/GCLK2, Type = DUAL/GCLK, Sch name = U-FD7
+
+## If using the DEPP interface uncomment lines 29-32
+#NET "EppWRITE" LOC = "V16"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-FLAGC
+#NET "EppASTB" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
+#NET "EppDSTB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
+#NET "EppWAIT" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
+
+## If using the DSTM interface uncomment lines 35-44
+#NET "DstmIFCLK" LOC = "T15"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = U-IFCLK
+#NET "DstmSLCS" LOC = "T16"; # Bank = 2, Pin name = IO_L26P_2/VS0/A17, Type = DUAL, Sch name = U-SLCS
+#NET "DstmFLAGA" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
+#NET "DstmFLAGB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
+#NET "DstmADR<0>" LOC = "T14"; # Bank = 2, Pin name = IO_L24P_2/A21, Type = DUAL, Sch name = U-FIFOAD0
+#NET "DstmADR<1>" LOC = "V13"; # Bank = 2, Pin name = IO_L19N_2/VREF_2, Type = VREF, Sch name = U-FIFOAD1
+#NET "DstmSLRD" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
+#NET "DstmSLWR" LOC = "V9"; # Bank = 2, Pin name = IO_L13N_2/D3/GCLK15, Type = DUAL/GCLK, Sch name = U-SLWR
+#NET "DstmSLOE" LOC = "V15"; # Bank = 2, Pin name = IO_L25P_2/VS2/A19, Type = DUAL, Sch name = U-SLOE
+#NET "DstmPKTEND" LOC = "V12"; # Bank = 2, Pin name = IO_L19P_2, Type = I/O, Sch name = U-PKTEND
+
+#NET "UsbMode" LOC = "U15"; # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type = DUAL, Sch name = U-INT0#
+#NET "UsbRdy" LOC = "U13"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-RDY
+
+## onBoard Cellular RAM and StrataFlash
+#NET "MemOE" LOC = "T2"; # Bank = 3, Pin name = IO_L24P_3, Type = I/O, Sch name = OE
+#NET "MemWR" LOC = "N7"; # Bank = 2, Pin name = IO_L07P_2, Type = I/O, Sch name = WE
+
+#NET "RamAdv" LOC = "J4"; # Bank = 3, Pin name = IO_L11N_3/LHCLK1, Type = LHCLK, Sch name = MT-ADV
+#NET "RamCS" LOC = "R6"; # Bank = 2, Pin name = IO_L05P_2, Type = I/O, Sch name = MT-CE
+#NET "RamClk" LOC = "H5"; # Bank = 3, Pin name = IO_L08N_3, Type = I/O, Sch name = MT-CLK
+#NET "RamCRE" LOC = "P7"; # Bank = 2, Pin name = IO_L07N_2, Type = I/O, Sch name = MT-CRE
+#NET "RamLB" LOC = "K5"; # Bank = 3, Pin name = IO_L14N_3/LHCLK7, Type = LHCLK, Sch name = MT-LB
+#NET "RamUB" LOC = "K4"; # Bank = 3, Pin name = IO_L13N_3/LHCLK5, Type = LHCLK, Sch name = MT-UB
+#NET "RamWait" LOC = "F5"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = MT-WAIT
+
+#NET "FlashRp" LOC = "T5"; # Bank = 2, Pin name = IO_L04N_2, Type = I/O, Sch name = RP#
+#NET "FlashCS" LOC = "R5"; # Bank = 2, Pin name = IO_L04P_2, Type = I/O, Sch name = ST-CE
+#NET "FlashStSts" LOC = "D3"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = ST-STS
+
+#NET "MemAdr<1>" LOC = "J1"; # Bank = 3, Pin name = IO_L12P_3/LHCLK2, Type = LHCLK, Sch name = ADR1
+#NET "MemAdr<2>" LOC = "J2"; # Bank = 3, Pin name = IO_L12N_3/LHCLK3/IRDY2, Type = LHCLK, Sch name = ADR2
+#NET "MemAdr<3>" LOC = "H4"; # Bank = 3, Pin name = IO_L09P_3, Type = I/O, Sch name = ADR3
+#NET "MemAdr<4>" LOC = "H1"; # Bank = 3, Pin name = IO_L10N_3, Type = I/O, Sch name = ADR4
+#NET "MemAdr<5>" LOC = "H2"; # Bank = 3, Pin name = IO_L10P_3, Type = I/O, Sch name = ADR5
+#NET "MemAdr<6>" LOC = "J5"; # Bank = 3, Pin name = IO_L11P_3/LHCLK0, Type = LHCLK, Sch name = ADR6
+#NET "MemAdr<7>" LOC = "H3"; # Bank = 3, Pin name = IO_L09N_3, Type = I/O, Sch name = ADR7
+#NET "MemAdr<8>" LOC = "H6"; # Bank = 3, Pin name = IO_L08P_3, Type = I/O, Sch name = ADR8
+#NET "MemAdr<9>" LOC = "F1"; # Bank = 3, Pin name = IO_L05P_3, Type = I/O, Sch name = ADR9
+#NET "MemAdr<10>" LOC = "G3"; # Bank = 3, Pin name = IO_L06P_3, Type = I/O, Sch name = ADR10
+#NET "MemAdr<11>" LOC = "G6"; # Bank = 3, Pin name = IO_L07P_3, Type = I/O, Sch name = ADR11
+#NET "MemAdr<12>" LOC = "G5"; # Bank = 3, Pin name = IO_L07N_3, Type = I/O, Sch name = ADR12
+#NET "MemAdr<13>" LOC = "G4"; # Bank = 3, Pin name = IO_L06N_3/VREF_3, Type = VREF, Sch name = ADR13
+#NET "MemAdr<14>" LOC = "F2"; # Bank = 3, Pin name = IO_L05N_3, Type = I/O, Sch name = ADR14
+#NET "MemAdr<15>" LOC = "E1"; # Bank = 3, Pin name = IO_L03N_3, Type = I/O, Sch name = ADR15
+#NET "MemAdr<16>" LOC = "M5"; # Bank = 3, Pin name = IO_L19P_3, Type = I/O, Sch name = ADR16
+#NET "MemAdr<17>" LOC = "E2"; # Bank = 3, Pin name = IO_L03P_3, Type = I/O, Sch name = ADR17
+#NET "MemAdr<18>" LOC = "C2"; # Bank = 3, Pin name = IO_L01N_3, Type = I/O, Sch name = ADR18
+#NET "MemAdr<19>" LOC = "C1"; # Bank = 3, Pin name = IO_L01P_3, Type = I/O, Sch name = ADR19
+#NET "MemAdr<20>" LOC = "D2"; # Bank = 3, Pin name = IO_L02N_3/VREF_3, Type = VREF, Sch name = ADR20
+#NET "MemAdr<21>" LOC = "K3"; # Bank = 3, Pin name = IO_L13P_3/LHCLK4/TRDY2, Type = LHCLK, Sch name = ADR21
+#NET "MemAdr<22>" LOC = "D1"; # Bank = 3, Pin name = IO_L02P_3, Type = I/O, Sch name = ADR22
+#NET "MemAdr<23>" LOC = "K6"; # Bank = 3, Pin name = IO_L14P_3/LHCLK6, Type = LHCLK, Sch name = ADR23
+
+#NET "MemDB<0>" LOC = "L1"; # Bank = 3, Pin name = IO_L15P_3, Type = I/O, Sch name = DB0
+#NET "MemDB<1>" LOC = "L4"; # Bank = 3, Pin name = IO_L16N_3, Type = I/O, Sch name = DB1
+#NET "MemDB<2>" LOC = "L6"; # Bank = 3, Pin name = IO_L17P_3, Type = I/O, Sch name = DB2
+#NET "MemDB<3>" LOC = "M4"; # Bank = 3, Pin name = IO_L18P_3, Type = I/O, Sch name = DB3
+#NET "MemDB<4>" LOC = "N5"; # Bank = 3, Pin name = IO_L20N_3, Type = I/O, Sch name = DB4
+#NET "MemDB<5>" LOC = "P1"; # Bank = 3, Pin name = IO_L21N_3, Type = I/O, Sch name = DB5
+#NET "MemDB<6>" LOC = "P2"; # Bank = 3, Pin name = IO_L21P_3, Type = I/O, Sch name = DB6
+#NET "MemDB<7>" LOC = "R2"; # Bank = 3, Pin name = IO_L23N_3, Type = I/O, Sch name = DB7
+#NET "MemDB<8>" LOC = "L3"; # Bank = 3, Pin name = IO_L16P_3, Type = I/O, Sch name = DB8
+#NET "MemDB<9>" LOC = "L5"; # Bank = 3, Pin name = IO_L17N_3/VREF_3, Type = VREF, Sch name = DB9
+#NET "MemDB<10>" LOC = "M3"; # Bank = 3, Pin name = IO_L18N_3, Type = I/O, Sch name = DB10
+#NET "MemDB<11>" LOC = "M6"; # Bank = 3, Pin name = IO_L19N_3, Type = I/O, Sch name = DB11
+#NET "MemDB<12>" LOC = "L2"; # Bank = 3, Pin name = IO_L15N_3, Type = I/O, Sch name = DB12
+#NET "MemDB<13>" LOC = "N4"; # Bank = 3, Pin name = IO_L20P_3, Type = I/O, Sch name = DB13
+#NET "MemDB<14>" LOC = "R3"; # Bank = 3, Pin name = IO_L23P_3, Type = I/O, Sch name = DB14
+#NET "MemDB<15>" LOC = "T1"; # Bank = 3, Pin name = IO_L24N_3, Type = I/O, Sch name = DB15
+
+## 7 segment display
+#NET "seg<0>" LOC = "L18"; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA
+#NET "seg<1>" LOC = "F18"; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB
+#NET "seg<2>" LOC = "D17"; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC
+#NET "seg<3>" LOC = "D16"; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD
+#NET "seg<4>" LOC = "G14"; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE
+#NET "seg<5>" LOC = "J17"; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
+#NET "seg<6>" LOC = "H14"; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG
+#NET "dp" LOC = "C17"; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP
+
+#NET "an<0>" LOC = "F17"; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0
+#NET "an<1>" LOC = "H17"; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1
+#NET "an<2>" LOC = "C18"; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2
+#NET "an<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3
+
+## Leds
+#NET "Led<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
+#NET "Led<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
+#NET "Led<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
+#NET "Led<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
+#NET "Led<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4? s3e500 only
+#NET "Led<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5? s3e500 only
+#NET "Led<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6? s3e500 only
+#NET "Led<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7? s3e500 only
+#NET "Led<4>" LOC = "E16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD4? other than s3e500
+#NET "Led<5>" LOC = "P16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD5? other than s3e500
+#NET "Led<6>" LOC = "E4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD6? other than s3e500
+#NET "Led<7>" LOC = "P4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD7? other than s3e500
+
+## Switches
+#NET "sw<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
+#NET "sw<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
+#NET "sw<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
+#NET "sw<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
+#NET "sw<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
+#NET "sw<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
+#NET "sw<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
+#NET "sw<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7
+
+## Buttons
+#NET "btn<0>" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
+#NET "btn<1>" LOC = "D18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = BTN1
+#NET "btn<2>" LOC = "E18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN2
+#NET "btn<3>" LOC = "H13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN3
+
+## VGA Connector
+#NET "vgaRed<1>" LOC = "R9"; # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0
+#NET "vgaRed<2>" LOC = "T8"; # Bank = 2, Pin name = IO_L10N_2, Type = I/O, Sch name = RED1
+#NET "vgaRed<3>" LOC = "R8"; # Bank = 2, Pin name = IO_L10P_2, Type = I/O, Sch name = RED2
+#NET "vgaGreen<1>" LOC = "N8"; # Bank = 2, Pin name = IO_L09N_2, Type = I/O, Sch name = GRN0
+#NET "vgaGreen<2>" LOC = "P8"; # Bank = 2, Pin name = IO_L09P_2, Type = I/O, Sch name = GRN1
+#NET "vgaGreen<3>" LOC = "P6"; # Bank = 2, Pin name = IO_L05N_2, Type = I/O, Sch name = GRN2
+#NET "vgaBlue<2>" LOC = "U5"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = BLU1
+#NET "vgaBlue<3>" LOC = "U4"; # Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DUAL, Sch name = BLU2
+
+#NET "Hsync" LOC = "T4"; # Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type = DUAL, Sch name = HSYNC
+#NET "Vsync" LOC = "U3"; # Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUAL, Sch name = VSYNC
+
+## PS/2 connector
+#NET "PS2C" LOC = "R12"; # Bank = 2, Pin name = IO_L20N_2, Type = I/O, Sch name = PS2C
+#NET "PS2D" LOC = "P11"; # Bank = 2, Pin name = IO_L18P_2, Type = I/O, Sch name = PS2D
+
+## FX2 connector
+#NET "PIO<0>" LOC = "B4"; # Bank = 0, Pin name = IO_L24N_0, Type = I/O, Sch name = R-IO1
+#NET "PIO<1>" LOC = "A4"; # Bank = 0, Pin name = IO_L24P_0, Type = I/O, Sch name = R-IO2
+#NET "PIO<2>" LOC = "C3"; # Bank = 0, Pin name = IO_L25P_0, Type = I/O, Sch name = R-IO3
+#NET "PIO<3>" LOC = "C4"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO4
+#NET "PIO<4>" LOC = "B6"; # Bank = 0, Pin name = IO_L20P_0, Type = I/O, Sch name = R-IO5
+#NET "PIO<5>" LOC = "D5"; # Bank = 0, Pin name = IO_L23N_0/VREF_0, Type = VREF, Sch name = R-IO6
+#NET "PIO<6>" LOC = "C5"; # Bank = 0, Pin name = IO_L23P_0, Type = I/O, Sch name = R-IO7
+#NET "PIO<7>" LOC = "F7"; # Bank = 0, Pin name = IO_L19P_0, Type = I/O, Sch name = R-IO8
+#NET "PIO<8>" LOC = "E7"; # Bank = 0, Pin name = IO_L19N_0/VREF_0, Type = VREF, Sch name = R-IO9
+#NET "PIO<9>" LOC = "A6"; # Bank = 0, Pin name = IO_L20N_0, Type = I/O, Sch name = R-IO10
+#NET "PIO<10>" LOC = "C7"; # Bank = 0, Pin name = IO_L18P_0, Type = I/O, Sch name = R-IO11
+#NET "PIO<11>" LOC = "F8"; # Bank = 0, Pin name = IO_L17N_0, Type = I/O, Sch name = R-IO12
+#NET "PIO<12>" LOC = "D7"; # Bank = 0, Pin name = IO_L18N_0/VREF_0, Type = VREF, Sch name = R-IO13
+#NET "PIO<13>" LOC = "E8"; # Bank = 0, Pin name = IO_L17P_0, Type = I/O, Sch name = R-IO14
+#NET "PIO<14>" LOC = "E9"; # Bank = 0, Pin name = IO_L15P_0, Type = I/O, Sch name = R-IO15
+#NET "PIO<15>" LOC = "C9"; # Bank = 0, Pin name = IO_L14P_0/GCLK10, Type = GCLK, Sch name = R-IO16
+#NET "PIO<16>" LOC = "A8"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO17
+#NET "PIO<17>" LOC = "G9"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO18
+#NET "PIO<18>" LOC = "F9"; # Bank = 0, Pin name = IO_L15N_0, Type = I/O, Sch name = R-IO19
+#NET "PIO<19>" LOC = "D10"; # Bank = 0, Pin name = IO_L11P_0/GCLK4, Type = GCLK, Sch name = R-IO20
+#NET "PIO<20>" LOC = "A10"; # Bank = 0, Pin name = IO_L12N_0/GCLK7, Type = GCLK, Sch name = R-IO21
+#NET "PIO<21>" LOC = "B10"; # Bank = 0, Pin name = IO_L12P_0/GCLK6, Type = GCLK, Sch name = R-IO22
+#NET "PIO<22>" LOC = "A11"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO23
+#NET "PIO<23>" LOC = "D11"; # Bank = 0, Pin name = IO_L09N_0, Type = I/O, Sch name = R-IO24
+#NET "PIO<24>" LOC = "E10"; # Bank = 0, Pin name = IO_L11N_0/GCLK5, Type = GCLK, Sch name = R-IO25
+#NET "PIO<25>" LOC = "B11"; # Bank = 0, Pin name = IO/VREF_0, Type = VREF, Sch name = R-IO26
+#NET "PIO<26>" LOC = "C11"; # Bank = 0, Pin name = IO_L09P_0, Type = I/O, Sch name = R-IO27
+#NET "PIO<27>" LOC = "E11"; # Bank = 0, Pin name = IO_L08P_0, Type = I/O, Sch name = R-IO28
+#NET "PIO<28>" LOC = "F11"; # Bank = 0, Pin name = IO_L08N_0, Type = I/O, Sch name = R-IO29
+#NET "PIO<29>" LOC = "E12"; # Bank = 0, Pin name = IO_L06N_0, Type = I/O, Sch name = R-IO30
+#NET "PIO<30>" LOC = "F12"; # Bank = 0, Pin name = IO_L06P_0, Type = I/O, Sch name = R-IO31
+#NET "PIO<31>" LOC = "A13"; # Bank = 0, Pin name = IO_L05P_0, Type = I/O, Sch name = R-IO32
+#NET "PIO<32>" LOC = "B13"; # Bank = 0, Pin name = IO_L05N_0/VREF_0, Type = VREF, Sch name = R-IO33
+#NET "PIO<33>" LOC = "E13"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO34
+#NET "PIO<34>" LOC = "A14"; # Bank = 0, Pin name = IO_L04N_0, Type = I/O, Sch name = R-IO35
+#NET "PIO<35>" LOC = "C14"; # Bank = 0, Pin name = IO_L03N_0/VREF_0, Type = VREF, Sch name = R-IO36
+#NET "PIO<36>" LOC = "D14"; # Bank = 0, Pin name = IO_L03P_0, Type = I/O, Sch name = R-IO37
+#NET "PIO<37>" LOC = "B14"; # Bank = 0, Pin name = IO_L04P_0, Type = I/O, Sch name = R-IO38
+#NET "PIO<38>" LOC = "A16"; # Bank = 0, Pin name = IO_L01N_0, Type = I/O, Sch name = R-IO39
+#NET "PIO<39>" LOC = "B16"; # Bank = 0, Pin name = IO_L01P_0, Type = I/O, Sch name = R-IO40
+
+## 12 pin connectors
+
+##JA
+#NET "JA<0>" LOC = "L15"; # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1
+#NET "JA<1>" LOC = "K12"; # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2
+#NET "JA<2>" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
+#NET "JA<3>" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
+#NET "JA<4>" LOC = "K13"; # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL, Sch name = JA7
+#NET "JA<5>" LOC = "L16"; # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL, Sch name = JA8
+#NET "JA<6>" LOC = "M14"; # Bank = 1, Pin name = IO_L05P_1, Type = I/O, Sch name = JA9
+#NET "JA<7>" LOC = "M16"; # Bank = 1, Pin name = IO_L07N_1, Type = I/O, Sch name = JA10
+
+##JB
+#NET "JB<0>" LOC = "M13"; # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF, Sch name = JB1
+#NET "JB<1>" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
+#NET "JB<2>" LOC = "R15"; # Bank = 1, Pin name = IO_L03P_1, Type = I/O, Sch name = JB3
+#NET "JB<3>" LOC = "T17"; # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL, Sch name = JB4
+#NET "JB<4>" LOC = "P17"; # Bank = 1, Pin name = IO_L06P_1, Type = I/O, Sch name = JB7
+#NET "JB<5>" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
+#NET "JB<6>" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
+#NET "JB<7>" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
+
+##JC
+#NET "JC<0>" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
+#NET "JC<1>" LOC = "J16"; # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL, Sch name = JC2
+#NET "JC<2>" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
+#NET "JC<3>" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
+#NET "JC<4>" LOC = "H15"; # Bank = 1, Pin name = IO_L17N_1, Type = I/O, Sch name = JC7
+#NET "JC<5>" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
+#NET "JC<6>" LOC = "G16"; # Bank = 1, Pin name = IO_L18N_1, Type = I/O, Sch name = JC9
+#NET "JC<7>" LOC = "J12"; # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL, Sch name = JC10
+
+##JD - NOTE: For other JD pins see LD(3:0) above under "Leds"
+#NET "JD<0>" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
+#NET "JD<1>" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
+#NET "JD<2>" LOC = "N18"; # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3
+#NET "JD<3>" LOC = "P18"; # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4
+
+## RS232 connector
+#NET "RsRx" LOC = "U6"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = RS-RX
+#NET "RsTx" LOC = "P9"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = RS-TX
+
diff --git a/myown_i2c/TB_MUX21.vhd b/myown_i2c/TB_MUX21.vhd
new file mode 100755
index 0000000..d79a02c
--- /dev/null
+++ b/myown_i2c/TB_MUX21.vhd
@@ -0,0 +1,108 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:26:17 01/21/2022
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/myown_i2c/TB_MUX21.vhd
+-- Project Name: myown_i2c
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: MUX_21
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY TB_MUX21 IS
+END TB_MUX21;
+
+ARCHITECTURE behavior OF TB_MUX21 IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT MUX_21
+PORT(
+S : IN std_logic;
+A : IN std_logic;
+B : IN std_logic;
+C : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal S : std_logic := '0';
+signal A : std_logic := '0';
+signal B : std_logic := '0';
+
+--Outputs
+signal C : std_logic;
+
+constant clock_period : time := 10 ns;
+signal clock : std_logic;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: MUX_21 PORT MAP (
+S => S,
+A => A,
+B => B,
+C => C
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc : process
+begin
+-- hold reset state for 100 ns.
+wait for 100 ns;
+wait for clock_period*10;
+-- insert stimulus here
+A <= '1';
+B <= '0';
+S <= '0';
+wait for clock_period;
+A <= '1';
+B <= '0';
+S <= '1';
+wait for clock_period;
+A <= '0';
+B <= '1';
+S <= '0';
+wait for clock_period;
+A <= '0';
+B <= '1';
+S <= '1';
+wait for clock_period;
+
+wait;
+end process;
+
+END;
diff --git a/myown_i2c/TB_MUX_41.vhd b/myown_i2c/TB_MUX_41.vhd
new file mode 100755
index 0000000..f0f3cd4
--- /dev/null
+++ b/myown_i2c/TB_MUX_41.vhd
@@ -0,0 +1,115 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:11:49 01/21/2022
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/myown_i2c/TB_MUX_41.vhd
+-- Project Name: myown_i2c
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: MUX_41
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY TB_MUX_41 IS
+END TB_MUX_41;
+
+ARCHITECTURE behavior OF TB_MUX_41 IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT MUX_41
+PORT(
+S1 : IN std_logic;
+S2 : IN std_logic;
+A : IN std_logic;
+B : IN std_logic;
+C : IN std_logic;
+D : IN std_logic;
+E : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal S1 : std_logic := '0';
+signal S2 : std_logic := '0';
+signal A : std_logic := '0';
+signal B : std_logic := '0';
+signal C : std_logic := '0';
+signal D : std_logic := '0';
+
+--Outputs
+signal E : std_logic;
+
+constant clock_period : time := 10 ns;
+signal clock : std_logic;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: MUX_41 PORT MAP (
+S1 => S1,
+S2 => S2,
+A => A,
+B => B,
+C => C,
+D => D,
+E => E
+);
+
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc : process
+ variable t : std_logic_vector(1 downto 0);
+begin
+-- hold reset state for 100 ns.
+wait for 100 ns;
+--A <= '1'; wait for clock_period;
+--B <= '1'; wait for clock_period;
+--C <= '1'; wait for clock_period;
+--D <= '1'; wait for clock_period;
+wait for clock_period*10;
+-- insert stimulus here
+l0 : for i in 0 to 3 loop
+ t := std_logic_vector(to_unsigned(i,2));
+ case (i) is
+ when 0 => A <= '1'; B <= '0'; C <= '0'; D <= '0';
+ when 1 => A <= '0'; B <= '1'; C <= '0'; D <= '0';
+ when 2 => A <= '0'; B <= '0'; C <= '1'; D <= '0';
+ when 3 => A <= '0'; B <= '0'; C <= '0'; D <= '1';
+ end case;
+ S1 <= t(0);
+ S2 <= t(1);
+ wait for clock_period*10;
+end loop l0;
+wait;
+end process;
+
+END;
diff --git a/myown_i2c/TB_MUX_81.vhd b/myown_i2c/TB_MUX_81.vhd
new file mode 100755
index 0000000..0ee8fb1
--- /dev/null
+++ b/myown_i2c/TB_MUX_81.vhd
@@ -0,0 +1,140 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:03:35 01/21/2022
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/myown_i2c/TB_MUX_81.vhd
+-- Project Name: myown_i2c
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: MUX_81
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY TB_MUX_81 IS
+END TB_MUX_81;
+
+ARCHITECTURE behavior OF TB_MUX_81 IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT MUX_81
+PORT(
+in0 : IN std_logic;
+in1 : IN std_logic;
+in2 : IN std_logic;
+in3 : IN std_logic;
+in4 : IN std_logic;
+in5 : IN std_logic;
+in6 : IN std_logic;
+in7 : IN std_logic;
+s0 : IN std_logic;
+s1 : IN std_logic;
+s2 : IN std_logic;
+o : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal in0 : std_logic := '0';
+signal in1 : std_logic := '0';
+signal in2 : std_logic := '0';
+signal in3 : std_logic := '0';
+signal in4 : std_logic := '0';
+signal in5 : std_logic := '0';
+signal in6 : std_logic := '0';
+signal in7 : std_logic := '0';
+signal s0 : std_logic := '0';
+signal s1 : std_logic := '0';
+signal s2 : std_logic := '0';
+
+--Outputs
+signal o : std_logic;
+
+constant clock_period : time := 10 ns;
+signal clock : std_logic;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: MUX_81 PORT MAP (
+in0 => in0,
+in1 => in1,
+in2 => in2,
+in3 => in3,
+in4 => in4,
+in5 => in5,
+in6 => in6,
+in7 => in7,
+s0 => s0,
+s1 => s1,
+s2 => s2,
+o => o
+);
+
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc : process
+ variable t : std_logic_vector(2 downto 0);
+begin
+-- hold reset state for 100 ns.
+wait for 100 ns;
+--in0 <= '1'; wait for clock_period;
+--in1 <= '1'; wait for clock_period;
+--in2 <= '1'; wait for clock_period;
+--in3 <= '1'; wait for clock_period;
+--in4 <= '1'; wait for clock_period;
+--in5 <= '1'; wait for clock_period;
+--in6 <= '1'; wait for clock_period;
+--in7 <= '1'; wait for clock_period;
+wait for clock_period*10;
+-- insert stimulus here
+l0 : for i in 0 to 7 loop
+ t := std_logic_vector(to_unsigned(i,3));
+ case (i) is
+ when 0 => in0 <= '1'; in1 <= '0'; in2 <= '0'; in3 <= '0'; in4 <= '0'; in5 <= '0'; in6 <= '0'; in7 <= '0';
+ when 1 => in0 <= '0'; in1 <= '1'; in2 <= '0'; in3 <= '0'; in4 <= '0'; in5 <= '0'; in6 <= '0'; in7 <= '0';
+ when 2 => in0 <= '0'; in1 <= '0'; in2 <= '1'; in3 <= '0'; in4 <= '0'; in5 <= '0'; in6 <= '0'; in7 <= '0';
+ when 3 => in0 <= '0'; in1 <= '0'; in2 <= '0'; in3 <= '1'; in4 <= '0'; in5 <= '0'; in6 <= '0'; in7 <= '0';
+ when 4 => in0 <= '0'; in1 <= '0'; in2 <= '0'; in3 <= '0'; in4 <= '1'; in5 <= '0'; in6 <= '0'; in7 <= '0';
+ when 5 => in0 <= '0'; in1 <= '0'; in2 <= '0'; in3 <= '0'; in4 <= '0'; in5 <= '1'; in6 <= '0'; in7 <= '0';
+ when 6 => in0 <= '0'; in1 <= '0'; in2 <= '0'; in3 <= '0'; in4 <= '0'; in5 <= '0'; in6 <= '1'; in7 <= '0';
+ when 7 => in0 <= '0'; in1 <= '0'; in2 <= '0'; in3 <= '0'; in4 <= '0'; in5 <= '0'; in6 <= '0'; in7 <= '1';
+ end case;
+ s0 <= t(0);
+ s1 <= t(1);
+ s2 <= t(2);
+ wait for clock_period;
+end loop l0;
+wait;
+end process;
+
+END;
diff --git a/myown_i2c/convert_glcdfont.awk b/myown_i2c/convert_glcdfont.awk
new file mode 100755
index 0000000..7bb43a6
--- /dev/null
+++ b/myown_i2c/convert_glcdfont.awk
@@ -0,0 +1,43 @@
+# simple convert hex digits in glcdfont.c to VHDL hex table
+# src file : https://github.com/adafruit/Adafruit-GFX-Library/blob/master/glcdfont.c
+# usage : awk -f this_file.awk glcdfont.c
+
+
+BEGIN {
+ FPAT="(0x[0-9ABCDEF]+[0-9ABCDEF]+[, ]+{0,5})";
+ global_index = 0;
+ global_row_index = 0;
+ table_name = "GLCDFONTC";
+}
+{
+ #printf("%d:\t%s\n",NR,$0);
+ if (NF > 0) {
+ #print "NF = ", NF
+ for (i = 1; i <= NF; i++) {
+ array_line[global_index] = (global_row_index*5)":"$0;
+ #printf("$%d = <%s>\n", i, $i)
+ array_hex[global_index] = substr($i,3,2); # "0xXX, -> XX"
+ #printf("x\"%s\",\n",temp[global_index]);
+ global_index++;
+ }
+ global_row_index++;
+ #printf("\n");
+ }
+}
+END {
+ printf("constant NUMBER_%s : natural := %d;\n",table_name,global_index);
+ printf("type ARRAY_%s is array (0 to NUMBER_%s-1) of std_logic_vector(7 downto 0);\n",table_name,table_name);
+ printf("signal %s : ARRAY_%s :=\n",table_name,table_name);
+ printf("(\n");
+ for (i = 0; i < length(array_hex); i++) {
+ if (i % 5 == 0) {
+ printf("\n\t -- %s\n",array_line[i]);
+ }
+ if (i == length(array_hex)-1) {
+ printf("\tx\"%s\"\n",array_hex[i]);
+ } else {
+ printf("\tx\"%s\",\n",array_hex[i]);
+ }
+ }
+ printf(");\n");
+}
diff --git a/myown_i2c/example_simulation.png b/myown_i2c/example_simulation.png
new file mode 100755
index 0000000..d6bd53d
Binary files /dev/null and b/myown_i2c/example_simulation.png differ
diff --git a/myown_i2c/gate_and.vhd b/myown_i2c/gate_and.vhd
new file mode 100755
index 0000000..83a974c
--- /dev/null
+++ b/myown_i2c/gate_and.vhd
@@ -0,0 +1,37 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_AND is
+generic (
+delay_and : TIME := 0 ns
+);
+port (
+A,B : in STD_LOGIC;
+C : out STD_LOGIC
+);
+end entity GATE_AND;
+
+architecture GATE_AND_BEHAVIORAL_1 of GATE_AND is
+begin
+C <= A and B after delay_and;
+end architecture GATE_AND_BEHAVIORAL_1;
+
+architecture GATE_AND_LUT of GATE_AND is
+ signal T : std_logic;
+begin
+-- LUT2: 2-input Look-Up Table with general output
+-- Spartan-3
+-- Xilinx HDL Libraries Guide, version 14.7
+LUT2_inst : LUT2
+generic map (
+ INIT => "1000")
+port map (
+ O => T, -- LUT general output
+ I0 => A, -- LUT input
+ I1 => B -- LUT input
+);
+-- End of LUT2_inst instantiation
+C <= T after delay_and;
+end architecture GATE_AND_LUT;
diff --git a/myown_i2c/gate_and3.vhd b/myown_i2c/gate_and3.vhd
new file mode 100755
index 0000000..43ca989
--- /dev/null
+++ b/myown_i2c/gate_and3.vhd
@@ -0,0 +1,54 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 09:50:05 09/12/2021
+-- Design Name:
+-- Module Name: gate_and3 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_AND3 is
+generic (
+delay_and3 : TIME := 0 ns
+);
+port (
+A,B,C : in STD_LOGIC;
+D : out STD_LOGIC
+);
+end entity GATE_AND3;
+
+architecture GATE_AND3_BEHAVIORAL_1 of GATE_AND3 is
+begin
+D <= (A and B and C) after delay_and3;
+end architecture GATE_AND3_BEHAVIORAL_1;
+
+architecture GATE_AND3_LUT of GATE_AND3 is
+ signal T : std_logic;
+begin
+LUT3_inst : LUT3
+generic map (
+ INIT => "10000000")
+port map (
+ O => T,
+ I0 => A,
+ I1 => B,
+ I2 => C
+);
+D <= T after delay_and3;
+end architecture GATE_AND3_LUT;
diff --git a/myown_i2c/gate_nand.vhd b/myown_i2c/gate_nand.vhd
new file mode 100755
index 0000000..a0aace4
--- /dev/null
+++ b/myown_i2c/gate_nand.vhd
@@ -0,0 +1,63 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 09:50:05 09/12/2021
+-- Design Name:
+-- Module Name: gate_and3 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity GATE_NAND is
+Generic (
+delay_nand : time := 0 ns
+);
+Port (
+A,B : in STD_LOGIC;
+C : out STD_LOGIC
+);
+end GATE_NAND;
+
+architecture GATE_NAND_BEHAVIORAL_1 of GATE_NAND is
+begin
+C <= A nand B after DELAY_NAND;
+end GATE_NAND_BEHAVIORAL_1;
+
+architecture GATE_NAND_LUT of GATE_NAND is
+ signal T : std_logic;
+begin
+-- LUT2: 2-input Look-Up Table with general output
+-- Spartan-3
+-- Xilinx HDL Libraries Guide, version 14.7
+gate_nand_LUT2_L : LUT2
+generic map (
+ INIT => "0111")
+port map (
+ O => T, -- LUT local output
+ I0 => A, -- LUT input
+ I1 => B -- LUT input
+);
+-- End of LUT2_inst instantiation
+C <= T after DELAY_NAND;
+end architecture GATE_NAND_LUT;
diff --git a/myown_i2c/gate_nand2.vhd b/myown_i2c/gate_nand2.vhd
new file mode 100755
index 0000000..81436cb
--- /dev/null
+++ b/myown_i2c/gate_nand2.vhd
@@ -0,0 +1,38 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_NAND2 is
+generic (
+delay_nand2 : TIME := 0 ns
+);
+port (
+A,B : in STD_LOGIC;
+C : out STD_LOGIC
+);
+end entity GATE_NAND2;
+
+architecture GATE_NAND2_BEHAVIORAL_1 of GATE_NAND2 is
+begin
+--C <= not (A and B) after delay_nand2;
+C <= A nand B after delay_nand2;
+end architecture GATE_NAND2_BEHAVIORAL_1;
+
+architecture GATE_NAND2_LUT of GATE_NAND2 is
+ signal T : std_logic;
+begin
+-- LUT2: 2-input Look-Up Table with general output
+-- Spartan-3
+-- Xilinx HDL Libraries Guide, version 14.7
+LUT2_inst : LUT2
+generic map (
+ INIT => "0111")
+port map (
+ O => T, -- LUT general output
+ I0 => A, -- LUT input
+ I1 => B -- LUT input
+);
+-- End of LUT2_inst instantiation
+C <= T after delay_nand2;
+end architecture GATE_NAND2_LUT;
diff --git a/myown_i2c/gate_nand3.vhd b/myown_i2c/gate_nand3.vhd
new file mode 100755
index 0000000..1bddf4d
--- /dev/null
+++ b/myown_i2c/gate_nand3.vhd
@@ -0,0 +1,61 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 09:50:05 09/12/2021
+-- Design Name:
+-- Module Name: gate_and3 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity GATE_NAND3 is
+generic (
+delay_nand3 : TIME := 0 ns
+);
+port (
+A,B,C : in STD_LOGIC;
+D : out STD_LOGIC
+);
+end entity GATE_NAND3;
+
+architecture GATE_NAND3_BEHAVIORAL_1 of GATE_NAND3 is
+begin
+--C <= not (A and B and C) after delay_nand3;
+D <= (A nand B) nand C after delay_nand3;
+end architecture GATE_NAND3_BEHAVIORAL_1;
+
+architecture GATE_NAND3_LUT of GATE_NAND3 is
+ signal T : std_logic;
+begin
+LUT3_inst : LUT3
+generic map (
+ INIT => "01111111")
+port map (
+ O => T,
+ I0 => A,
+ I1 => B,
+ I2 => C
+);
+D <= T after delay_nand3;
+end architecture GATE_NAND3_LUT;
diff --git a/myown_i2c/gate_nand4.vhd b/myown_i2c/gate_nand4.vhd
new file mode 100755
index 0000000..15c5b11
--- /dev/null
+++ b/myown_i2c/gate_nand4.vhd
@@ -0,0 +1,67 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 09:50:05 09/12/2021
+-- Design Name:
+-- Module Name: gate_and3 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity GATE_NAND4 is
+Generic (
+DELAY_NAND4 : time := 1 ps
+);
+Port (
+A,B,C,D : in STD_LOGIC;
+E : out STD_LOGIC
+);
+end GATE_NAND4;
+
+architecture GATE_NAND4_BEHAVIORAL_1 of GATE_NAND4 is
+ signal T : std_logic;
+begin
+T <= not (A and B and C and D);
+E <= T after DELAY_NAND4;
+end GATE_NAND4_BEHAVIORAL_1;
+
+architecture GATE_NAND4_LUT of GATE_NAND4 is
+-- signal T : std_logic;
+begin
+-- LUT4: 4-input Look-Up Table with general output
+-- Spartan-3
+-- Xilinx HDL Libraries Guide, version 14.7
+gate_nand4_LUT4_L : LUT4
+generic map (
+ INIT => X"7FFF")
+port map (
+ O => E, -- LUT local output
+ I0 => A, -- LUT input
+ I1 => B, -- LUT input
+ I2 => C, -- LUT input
+ I3 => D -- LUT input
+);
+-- End of LUT4_inst instantiation
+--E <= T after DELAY_NAND4;
+end architecture GATE_NAND4_LUT;
\ No newline at end of file
diff --git a/myown_i2c/gate_nor2.vhd b/myown_i2c/gate_nor2.vhd
new file mode 100755
index 0000000..268f24c
--- /dev/null
+++ b/myown_i2c/gate_nor2.vhd
@@ -0,0 +1,38 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_NOR2 is
+generic (
+delay_nor2 : TIME := 0 ns
+);
+port (
+A,B : in STD_LOGIC;
+C : out STD_LOGIC
+);
+end entity GATE_NOR2;
+
+architecture GATE_NOR2_BEHAVIORAL_1 of GATE_NOR2 is
+begin
+--C <= not (A or B) after delay_nor2;
+C <= A nor B after delay_nor2;
+end architecture GATE_NOR2_BEHAVIORAL_1;
+
+architecture GATE_NOR2_LUT of GATE_NOR2 is
+ signal T : std_logic;
+begin
+-- LUT2: 2-input Look-Up Table with general output
+-- Spartan-3
+-- Xilinx HDL Libraries Guide, version 14.7
+LUT2_inst : LUT2
+generic map (
+ INIT => "0001")
+port map (
+ O => T, -- LUT general output
+ I0 => A, -- LUT input
+ I1 => B -- LUT input
+);
+-- End of LUT2_inst instantiation
+C <= T after delay_nor2;
+end architecture GATE_NOR2_LUT;
diff --git a/myown_i2c/gate_not.vhd b/myown_i2c/gate_not.vhd
new file mode 100755
index 0000000..b3abf38
--- /dev/null
+++ b/myown_i2c/gate_not.vhd
@@ -0,0 +1,37 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_NOT is
+generic (
+delay_not : TIME := 0 ns
+);
+port (
+A : in STD_LOGIC;
+B : out STD_LOGIC
+);
+end entity GATE_NOT;
+
+architecture GATE_NOT_BEHAVIORAL_1 of GATE_NOT is
+begin
+B <= not A after delay_not;
+end architecture GATE_NOT_BEHAVIORAL_1;
+
+architecture GATE_NOT_LUT of GATE_NOT is
+ signal T : std_logic;
+begin
+-- LUT2: 2-input Look-Up Table with general output
+-- Spartan-3
+-- Xilinx HDL Libraries Guide, version 14.7
+LUT2_inst : LUT2
+generic map (
+ INIT => "0001")
+port map (
+ O => T, -- LUT general output
+ I0 => A, -- LUT input
+ I1 => A -- LUT input
+);
+-- End of LUT2_inst instantiation
+B <= T after delay_not;
+end architecture GATE_NOT_LUT;
diff --git a/myown_i2c/gate_or.vhd b/myown_i2c/gate_or.vhd
new file mode 100755
index 0000000..57297f3
--- /dev/null
+++ b/myown_i2c/gate_or.vhd
@@ -0,0 +1,37 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_OR is
+generic (
+delay_or : TIME := 0 ns
+);
+port (
+A,B : in STD_LOGIC;
+C : out STD_LOGIC
+);
+end entity GATE_OR;
+
+architecture GATE_OR_BEHAVIORAL_1 of GATE_OR is
+begin
+C <= A or B after delay_or;
+end architecture GATE_OR_BEHAVIORAL_1;
+
+architecture GATE_OR_LUT of GATE_OR is
+ signal T : std_logic;
+begin
+-- LUT2: 2-input Look-Up Table with general output
+-- Spartan-3
+-- Xilinx HDL Libraries Guide, version 14.7
+LUT2_inst : LUT2
+generic map (
+ INIT => "1110")
+port map (
+ O => T, -- LUT general output
+ I0 => A, -- LUT input
+ I1 => B -- LUT input
+);
+-- End of LUT2_inst instantiation
+C <= T after delay_or;
+end architecture GATE_OR_LUT;
diff --git a/myown_i2c/glcdfont.vhd b/myown_i2c/glcdfont.vhd
new file mode 100755
index 0000000..4b65d5d
--- /dev/null
+++ b/myown_i2c/glcdfont.vhd
@@ -0,0 +1,1823 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity glcdfont is
+port (
+signal i_clk : in std_logic;
+signal i_index : in std_logic_vector(10 downto 0);
+signal o_character : out std_logic_vector(7 downto 0)
+);
+end entity glcdfont;
+
+architecture behavioral_glcdfont of glcdfont is
+
+constant NUMBER_GLCDFONTC : natural := 1275;
+type ARRAY_GLCDFONTC is array (0 to NUMBER_GLCDFONTC-1) of std_logic_vector(7 downto 0);
+constant GLCDFONTC : ARRAY_GLCDFONTC :=
+(
+
+ -- 0: 0x00, 0x00, 0x00, 0x00, 0x00,
+ x"00",
+ x"00",
+ x"00",
+ x"00",
+ x"00",
+
+ -- 5: 0x3E, 0x5B, 0x4F, 0x5B, 0x3E,
+ x"3E",
+ x"5B",
+ x"4F",
+ x"5B",
+ x"3E",
+
+ -- 10: 0x3E, 0x6B, 0x4F, 0x6B, 0x3E,
+ x"3E",
+ x"6B",
+ x"4F",
+ x"6B",
+ x"3E",
+
+ -- 15: 0x1C, 0x3E, 0x7C, 0x3E, 0x1C,
+ x"1C",
+ x"3E",
+ x"7C",
+ x"3E",
+ x"1C",
+
+ -- 20: 0x18, 0x3C, 0x7E, 0x3C, 0x18,
+ x"18",
+ x"3C",
+ x"7E",
+ x"3C",
+ x"18",
+
+ -- 25: 0x1C, 0x57, 0x7D, 0x57, 0x1C,
+ x"1C",
+ x"57",
+ x"7D",
+ x"57",
+ x"1C",
+
+ -- 30: 0x1C, 0x5E, 0x7F, 0x5E, 0x1C,
+ x"1C",
+ x"5E",
+ x"7F",
+ x"5E",
+ x"1C",
+
+ -- 35: 0x00, 0x18, 0x3C, 0x18, 0x00,
+ x"00",
+ x"18",
+ x"3C",
+ x"18",
+ x"00",
+
+ -- 40: 0xFF, 0xE7, 0xC3, 0xE7, 0xFF,
+ x"FF",
+ x"E7",
+ x"C3",
+ x"E7",
+ x"FF",
+
+ -- 45: 0x00, 0x18, 0x24, 0x18, 0x00,
+ x"00",
+ x"18",
+ x"24",
+ x"18",
+ x"00",
+
+ -- 50: 0xFF, 0xE7, 0xDB, 0xE7, 0xFF,
+ x"FF",
+ x"E7",
+ x"DB",
+ x"E7",
+ x"FF",
+
+ -- 55: 0x30, 0x48, 0x3A, 0x06, 0x0E,
+ x"30",
+ x"48",
+ x"3A",
+ x"06",
+ x"0E",
+
+ -- 60: 0x26, 0x29, 0x79, 0x29, 0x26,
+ x"26",
+ x"29",
+ x"79",
+ x"29",
+ x"26",
+
+ -- 65: 0x40, 0x7F, 0x05, 0x05, 0x07,
+ x"40",
+ x"7F",
+ x"05",
+ x"05",
+ x"07",
+
+ -- 70: 0x40, 0x7F, 0x05, 0x25, 0x3F,
+ x"40",
+ x"7F",
+ x"05",
+ x"25",
+ x"3F",
+
+ -- 75: 0x5A, 0x3C, 0xE7, 0x3C, 0x5A,
+ x"5A",
+ x"3C",
+ x"E7",
+ x"3C",
+ x"5A",
+
+ -- 80: 0x7F, 0x3E, 0x1C, 0x1C, 0x08,
+ x"7F",
+ x"3E",
+ x"1C",
+ x"1C",
+ x"08",
+
+ -- 85: 0x08, 0x1C, 0x1C, 0x3E, 0x7F,
+ x"08",
+ x"1C",
+ x"1C",
+ x"3E",
+ x"7F",
+
+ -- 90: 0x14, 0x22, 0x7F, 0x22, 0x14,
+ x"14",
+ x"22",
+ x"7F",
+ x"22",
+ x"14",
+
+ -- 95: 0x5F, 0x5F, 0x00, 0x5F, 0x5F,
+ x"5F",
+ x"5F",
+ x"00",
+ x"5F",
+ x"5F",
+
+ -- 100: 0x06, 0x09, 0x7F, 0x01, 0x7F,
+ x"06",
+ x"09",
+ x"7F",
+ x"01",
+ x"7F",
+
+ -- 105: 0x00, 0x66, 0x89, 0x95, 0x6A,
+ x"00",
+ x"66",
+ x"89",
+ x"95",
+ x"6A",
+
+ -- 110: 0x60, 0x60, 0x60, 0x60, 0x60,
+ x"60",
+ x"60",
+ x"60",
+ x"60",
+ x"60",
+
+ -- 115: 0x94, 0xA2, 0xFF, 0xA2, 0x94,
+ x"94",
+ x"A2",
+ x"FF",
+ x"A2",
+ x"94",
+
+ -- 120: 0x08, 0x04, 0x7E, 0x04, 0x08,
+ x"08",
+ x"04",
+ x"7E",
+ x"04",
+ x"08",
+
+ -- 125: 0x10, 0x20, 0x7E, 0x20, 0x10,
+ x"10",
+ x"20",
+ x"7E",
+ x"20",
+ x"10",
+
+ -- 130: 0x08, 0x08, 0x2A, 0x1C, 0x08,
+ x"08",
+ x"08",
+ x"2A",
+ x"1C",
+ x"08",
+
+ -- 135: 0x08, 0x1C, 0x2A, 0x08, 0x08,
+ x"08",
+ x"1C",
+ x"2A",
+ x"08",
+ x"08",
+
+ -- 140: 0x1E, 0x10, 0x10, 0x10, 0x10,
+ x"1E",
+ x"10",
+ x"10",
+ x"10",
+ x"10",
+
+ -- 145: 0x0C, 0x1E, 0x0C, 0x1E, 0x0C,
+ x"0C",
+ x"1E",
+ x"0C",
+ x"1E",
+ x"0C",
+
+ -- 150: 0x30, 0x38, 0x3E, 0x38, 0x30,
+ x"30",
+ x"38",
+ x"3E",
+ x"38",
+ x"30",
+
+ -- 155: 0x06, 0x0E, 0x3E, 0x0E, 0x06,
+ x"06",
+ x"0E",
+ x"3E",
+ x"0E",
+ x"06",
+
+ -- 160: 0x00, 0x00, 0x00, 0x00, 0x00,
+ x"00",
+ x"00",
+ x"00",
+ x"00",
+ x"00",
+
+ -- 165: 0x00, 0x00, 0x5F, 0x00, 0x00,
+ x"00",
+ x"00",
+ x"5F",
+ x"00",
+ x"00",
+
+ -- 170: 0x00, 0x07, 0x00, 0x07, 0x00,
+ x"00",
+ x"07",
+ x"00",
+ x"07",
+ x"00",
+
+ -- 175: 0x14, 0x7F, 0x14, 0x7F, 0x14,
+ x"14",
+ x"7F",
+ x"14",
+ x"7F",
+ x"14",
+
+ -- 180: 0x24, 0x2A, 0x7F, 0x2A, 0x12,
+ x"24",
+ x"2A",
+ x"7F",
+ x"2A",
+ x"12",
+
+ -- 185: 0x23, 0x13, 0x08, 0x64, 0x62,
+ x"23",
+ x"13",
+ x"08",
+ x"64",
+ x"62",
+
+ -- 190: 0x36, 0x49, 0x56, 0x20, 0x50,
+ x"36",
+ x"49",
+ x"56",
+ x"20",
+ x"50",
+
+ -- 195: 0x00, 0x08, 0x07, 0x03, 0x00,
+ x"00",
+ x"08",
+ x"07",
+ x"03",
+ x"00",
+
+ -- 200: 0x00, 0x1C, 0x22, 0x41, 0x00,
+ x"00",
+ x"1C",
+ x"22",
+ x"41",
+ x"00",
+
+ -- 205: 0x00, 0x41, 0x22, 0x1C, 0x00,
+ x"00",
+ x"41",
+ x"22",
+ x"1C",
+ x"00",
+
+ -- 210: 0x2A, 0x1C, 0x7F, 0x1C, 0x2A,
+ x"2A",
+ x"1C",
+ x"7F",
+ x"1C",
+ x"2A",
+
+ -- 215: 0x08, 0x08, 0x3E, 0x08, 0x08,
+ x"08",
+ x"08",
+ x"3E",
+ x"08",
+ x"08",
+
+ -- 220: 0x00, 0x80, 0x70, 0x30, 0x00,
+ x"00",
+ x"80",
+ x"70",
+ x"30",
+ x"00",
+
+ -- 225: 0x08, 0x08, 0x08, 0x08, 0x08,
+ x"08",
+ x"08",
+ x"08",
+ x"08",
+ x"08",
+
+ -- 230: 0x00, 0x00, 0x60, 0x60, 0x00,
+ x"00",
+ x"00",
+ x"60",
+ x"60",
+ x"00",
+
+ -- 235: 0x20, 0x10, 0x08, 0x04, 0x02,
+ x"20",
+ x"10",
+ x"08",
+ x"04",
+ x"02",
+
+ -- 240: 0x3E, 0x51, 0x49, 0x45, 0x3E,
+ x"3E",
+ x"51",
+ x"49",
+ x"45",
+ x"3E",
+
+ -- 245: 0x00, 0x42, 0x7F, 0x40, 0x00,
+ x"00",
+ x"42",
+ x"7F",
+ x"40",
+ x"00",
+
+ -- 250: 0x72, 0x49, 0x49, 0x49, 0x46,
+ x"72",
+ x"49",
+ x"49",
+ x"49",
+ x"46",
+
+ -- 255: 0x21, 0x41, 0x49, 0x4D, 0x33,
+ x"21",
+ x"41",
+ x"49",
+ x"4D",
+ x"33",
+
+ -- 260: 0x18, 0x14, 0x12, 0x7F, 0x10,
+ x"18",
+ x"14",
+ x"12",
+ x"7F",
+ x"10",
+
+ -- 265: 0x27, 0x45, 0x45, 0x45, 0x39,
+ x"27",
+ x"45",
+ x"45",
+ x"45",
+ x"39",
+
+ -- 270: 0x3C, 0x4A, 0x49, 0x49, 0x31,
+ x"3C",
+ x"4A",
+ x"49",
+ x"49",
+ x"31",
+
+ -- 275: 0x41, 0x21, 0x11, 0x09, 0x07,
+ x"41",
+ x"21",
+ x"11",
+ x"09",
+ x"07",
+
+ -- 280: 0x36, 0x49, 0x49, 0x49, 0x36,
+ x"36",
+ x"49",
+ x"49",
+ x"49",
+ x"36",
+
+ -- 285: 0x46, 0x49, 0x49, 0x29, 0x1E,
+ x"46",
+ x"49",
+ x"49",
+ x"29",
+ x"1E",
+
+ -- 290: 0x00, 0x00, 0x14, 0x00, 0x00,
+ x"00",
+ x"00",
+ x"14",
+ x"00",
+ x"00",
+
+ -- 295: 0x00, 0x40, 0x34, 0x00, 0x00,
+ x"00",
+ x"40",
+ x"34",
+ x"00",
+ x"00",
+
+ -- 300: 0x00, 0x08, 0x14, 0x22, 0x41,
+ x"00",
+ x"08",
+ x"14",
+ x"22",
+ x"41",
+
+ -- 305: 0x14, 0x14, 0x14, 0x14, 0x14,
+ x"14",
+ x"14",
+ x"14",
+ x"14",
+ x"14",
+
+ -- 310: 0x00, 0x41, 0x22, 0x14, 0x08,
+ x"00",
+ x"41",
+ x"22",
+ x"14",
+ x"08",
+
+ -- 315: 0x02, 0x01, 0x59, 0x09, 0x06,
+ x"02",
+ x"01",
+ x"59",
+ x"09",
+ x"06",
+
+ -- 320: 0x3E, 0x41, 0x5D, 0x59, 0x4E,
+ x"3E",
+ x"41",
+ x"5D",
+ x"59",
+ x"4E",
+
+ -- 325: 0x7C, 0x12, 0x11, 0x12, 0x7C,
+ x"7C",
+ x"12",
+ x"11",
+ x"12",
+ x"7C",
+
+ -- 330: 0x7F, 0x49, 0x49, 0x49, 0x36,
+ x"7F",
+ x"49",
+ x"49",
+ x"49",
+ x"36",
+
+ -- 335: 0x3E, 0x41, 0x41, 0x41, 0x22,
+ x"3E",
+ x"41",
+ x"41",
+ x"41",
+ x"22",
+
+ -- 340: 0x7F, 0x41, 0x41, 0x41, 0x3E,
+ x"7F",
+ x"41",
+ x"41",
+ x"41",
+ x"3E",
+
+ -- 345: 0x7F, 0x49, 0x49, 0x49, 0x41,
+ x"7F",
+ x"49",
+ x"49",
+ x"49",
+ x"41",
+
+ -- 350: 0x7F, 0x09, 0x09, 0x09, 0x01,
+ x"7F",
+ x"09",
+ x"09",
+ x"09",
+ x"01",
+
+ -- 355: 0x3E, 0x41, 0x41, 0x51, 0x73,
+ x"3E",
+ x"41",
+ x"41",
+ x"51",
+ x"73",
+
+ -- 360: 0x7F, 0x08, 0x08, 0x08, 0x7F,
+ x"7F",
+ x"08",
+ x"08",
+ x"08",
+ x"7F",
+
+ -- 365: 0x00, 0x41, 0x7F, 0x41, 0x00,
+ x"00",
+ x"41",
+ x"7F",
+ x"41",
+ x"00",
+
+ -- 370: 0x20, 0x40, 0x41, 0x3F, 0x01,
+ x"20",
+ x"40",
+ x"41",
+ x"3F",
+ x"01",
+
+ -- 375: 0x7F, 0x08, 0x14, 0x22, 0x41,
+ x"7F",
+ x"08",
+ x"14",
+ x"22",
+ x"41",
+
+ -- 380: 0x7F, 0x40, 0x40, 0x40, 0x40,
+ x"7F",
+ x"40",
+ x"40",
+ x"40",
+ x"40",
+
+ -- 385: 0x7F, 0x02, 0x1C, 0x02, 0x7F,
+ x"7F",
+ x"02",
+ x"1C",
+ x"02",
+ x"7F",
+
+ -- 390: 0x7F, 0x04, 0x08, 0x10, 0x7F,
+ x"7F",
+ x"04",
+ x"08",
+ x"10",
+ x"7F",
+
+ -- 395: 0x3E, 0x41, 0x41, 0x41, 0x3E,
+ x"3E",
+ x"41",
+ x"41",
+ x"41",
+ x"3E",
+
+ -- 400: 0x7F, 0x09, 0x09, 0x09, 0x06,
+ x"7F",
+ x"09",
+ x"09",
+ x"09",
+ x"06",
+
+ -- 405: 0x3E, 0x41, 0x51, 0x21, 0x5E,
+ x"3E",
+ x"41",
+ x"51",
+ x"21",
+ x"5E",
+
+ -- 410: 0x7F, 0x09, 0x19, 0x29, 0x46,
+ x"7F",
+ x"09",
+ x"19",
+ x"29",
+ x"46",
+
+ -- 415: 0x26, 0x49, 0x49, 0x49, 0x32,
+ x"26",
+ x"49",
+ x"49",
+ x"49",
+ x"32",
+
+ -- 420: 0x03, 0x01, 0x7F, 0x01, 0x03,
+ x"03",
+ x"01",
+ x"7F",
+ x"01",
+ x"03",
+
+ -- 425: 0x3F, 0x40, 0x40, 0x40, 0x3F,
+ x"3F",
+ x"40",
+ x"40",
+ x"40",
+ x"3F",
+
+ -- 430: 0x1F, 0x20, 0x40, 0x20, 0x1F,
+ x"1F",
+ x"20",
+ x"40",
+ x"20",
+ x"1F",
+
+ -- 435: 0x3F, 0x40, 0x38, 0x40, 0x3F,
+ x"3F",
+ x"40",
+ x"38",
+ x"40",
+ x"3F",
+
+ -- 440: 0x63, 0x14, 0x08, 0x14, 0x63,
+ x"63",
+ x"14",
+ x"08",
+ x"14",
+ x"63",
+
+ -- 445: 0x03, 0x04, 0x78, 0x04, 0x03,
+ x"03",
+ x"04",
+ x"78",
+ x"04",
+ x"03",
+
+ -- 450: 0x61, 0x59, 0x49, 0x4D, 0x43,
+ x"61",
+ x"59",
+ x"49",
+ x"4D",
+ x"43",
+
+ -- 455: 0x00, 0x7F, 0x41, 0x41, 0x41,
+ x"00",
+ x"7F",
+ x"41",
+ x"41",
+ x"41",
+
+ -- 460: 0x02, 0x04, 0x08, 0x10, 0x20,
+ x"02",
+ x"04",
+ x"08",
+ x"10",
+ x"20",
+
+ -- 465: 0x00, 0x41, 0x41, 0x41, 0x7F,
+ x"00",
+ x"41",
+ x"41",
+ x"41",
+ x"7F",
+
+ -- 470: 0x04, 0x02, 0x01, 0x02, 0x04,
+ x"04",
+ x"02",
+ x"01",
+ x"02",
+ x"04",
+
+ -- 475: 0x40, 0x40, 0x40, 0x40, 0x40,
+ x"40",
+ x"40",
+ x"40",
+ x"40",
+ x"40",
+
+ -- 480: 0x00, 0x03, 0x07, 0x08, 0x00,
+ x"00",
+ x"03",
+ x"07",
+ x"08",
+ x"00",
+
+ -- 485: 0x20, 0x54, 0x54, 0x78, 0x40,
+ x"20",
+ x"54",
+ x"54",
+ x"78",
+ x"40",
+
+ -- 490: 0x7F, 0x28, 0x44, 0x44, 0x38,
+ x"7F",
+ x"28",
+ x"44",
+ x"44",
+ x"38",
+
+ -- 495: 0x38, 0x44, 0x44, 0x44, 0x28,
+ x"38",
+ x"44",
+ x"44",
+ x"44",
+ x"28",
+
+ -- 500: 0x38, 0x44, 0x44, 0x28, 0x7F,
+ x"38",
+ x"44",
+ x"44",
+ x"28",
+ x"7F",
+
+ -- 505: 0x38, 0x54, 0x54, 0x54, 0x18,
+ x"38",
+ x"54",
+ x"54",
+ x"54",
+ x"18",
+
+ -- 510: 0x00, 0x08, 0x7E, 0x09, 0x02,
+ x"00",
+ x"08",
+ x"7E",
+ x"09",
+ x"02",
+
+ -- 515: 0x18, 0xA4, 0xA4, 0x9C, 0x78,
+ x"18",
+ x"A4",
+ x"A4",
+ x"9C",
+ x"78",
+
+ -- 520: 0x7F, 0x08, 0x04, 0x04, 0x78,
+ x"7F",
+ x"08",
+ x"04",
+ x"04",
+ x"78",
+
+ -- 525: 0x00, 0x44, 0x7D, 0x40, 0x00,
+ x"00",
+ x"44",
+ x"7D",
+ x"40",
+ x"00",
+
+ -- 530: 0x20, 0x40, 0x40, 0x3D, 0x00,
+ x"20",
+ x"40",
+ x"40",
+ x"3D",
+ x"00",
+
+ -- 535: 0x7F, 0x10, 0x28, 0x44, 0x00,
+ x"7F",
+ x"10",
+ x"28",
+ x"44",
+ x"00",
+
+ -- 540: 0x00, 0x41, 0x7F, 0x40, 0x00,
+ x"00",
+ x"41",
+ x"7F",
+ x"40",
+ x"00",
+
+ -- 545: 0x7C, 0x04, 0x78, 0x04, 0x78,
+ x"7C",
+ x"04",
+ x"78",
+ x"04",
+ x"78",
+
+ -- 550: 0x7C, 0x08, 0x04, 0x04, 0x78,
+ x"7C",
+ x"08",
+ x"04",
+ x"04",
+ x"78",
+
+ -- 555: 0x38, 0x44, 0x44, 0x44, 0x38,
+ x"38",
+ x"44",
+ x"44",
+ x"44",
+ x"38",
+
+ -- 560: 0xFC, 0x18, 0x24, 0x24, 0x18,
+ x"FC",
+ x"18",
+ x"24",
+ x"24",
+ x"18",
+
+ -- 565: 0x18, 0x24, 0x24, 0x18, 0xFC,
+ x"18",
+ x"24",
+ x"24",
+ x"18",
+ x"FC",
+
+ -- 570: 0x7C, 0x08, 0x04, 0x04, 0x08,
+ x"7C",
+ x"08",
+ x"04",
+ x"04",
+ x"08",
+
+ -- 575: 0x48, 0x54, 0x54, 0x54, 0x24,
+ x"48",
+ x"54",
+ x"54",
+ x"54",
+ x"24",
+
+ -- 580: 0x04, 0x04, 0x3F, 0x44, 0x24,
+ x"04",
+ x"04",
+ x"3F",
+ x"44",
+ x"24",
+
+ -- 585: 0x3C, 0x40, 0x40, 0x20, 0x7C,
+ x"3C",
+ x"40",
+ x"40",
+ x"20",
+ x"7C",
+
+ -- 590: 0x1C, 0x20, 0x40, 0x20, 0x1C,
+ x"1C",
+ x"20",
+ x"40",
+ x"20",
+ x"1C",
+
+ -- 595: 0x3C, 0x40, 0x30, 0x40, 0x3C,
+ x"3C",
+ x"40",
+ x"30",
+ x"40",
+ x"3C",
+
+ -- 600: 0x44, 0x28, 0x10, 0x28, 0x44,
+ x"44",
+ x"28",
+ x"10",
+ x"28",
+ x"44",
+
+ -- 605: 0x4C, 0x90, 0x90, 0x90, 0x7C,
+ x"4C",
+ x"90",
+ x"90",
+ x"90",
+ x"7C",
+
+ -- 610: 0x44, 0x64, 0x54, 0x4C, 0x44,
+ x"44",
+ x"64",
+ x"54",
+ x"4C",
+ x"44",
+
+ -- 615: 0x00, 0x08, 0x36, 0x41, 0x00,
+ x"00",
+ x"08",
+ x"36",
+ x"41",
+ x"00",
+
+ -- 620: 0x00, 0x00, 0x77, 0x00, 0x00,
+ x"00",
+ x"00",
+ x"77",
+ x"00",
+ x"00",
+
+ -- 625: 0x00, 0x41, 0x36, 0x08, 0x00,
+ x"00",
+ x"41",
+ x"36",
+ x"08",
+ x"00",
+
+ -- 630: 0x02, 0x01, 0x02, 0x04, 0x02,
+ x"02",
+ x"01",
+ x"02",
+ x"04",
+ x"02",
+
+ -- 635: 0x3C, 0x26, 0x23, 0x26, 0x3C,
+ x"3C",
+ x"26",
+ x"23",
+ x"26",
+ x"3C",
+
+ -- 640: 0x1E, 0xA1, 0xA1, 0x61, 0x12,
+ x"1E",
+ x"A1",
+ x"A1",
+ x"61",
+ x"12",
+
+ -- 645: 0x3A, 0x40, 0x40, 0x20, 0x7A,
+ x"3A",
+ x"40",
+ x"40",
+ x"20",
+ x"7A",
+
+ -- 650: 0x38, 0x54, 0x54, 0x55, 0x59,
+ x"38",
+ x"54",
+ x"54",
+ x"55",
+ x"59",
+
+ -- 655: 0x21, 0x55, 0x55, 0x79, 0x41,
+ x"21",
+ x"55",
+ x"55",
+ x"79",
+ x"41",
+
+ -- 660: 0x22, 0x54, 0x54, 0x78, 0x42, // a-umlaut
+ x"22",
+ x"54",
+ x"54",
+ x"78",
+ x"42",
+
+ -- 665: 0x21, 0x55, 0x54, 0x78, 0x40,
+ x"21",
+ x"55",
+ x"54",
+ x"78",
+ x"40",
+
+ -- 670: 0x20, 0x54, 0x55, 0x79, 0x40,
+ x"20",
+ x"54",
+ x"55",
+ x"79",
+ x"40",
+
+ -- 675: 0x0C, 0x1E, 0x52, 0x72, 0x12,
+ x"0C",
+ x"1E",
+ x"52",
+ x"72",
+ x"12",
+
+ -- 680: 0x39, 0x55, 0x55, 0x55, 0x59,
+ x"39",
+ x"55",
+ x"55",
+ x"55",
+ x"59",
+
+ -- 685: 0x39, 0x54, 0x54, 0x54, 0x59,
+ x"39",
+ x"54",
+ x"54",
+ x"54",
+ x"59",
+
+ -- 690: 0x39, 0x55, 0x54, 0x54, 0x58,
+ x"39",
+ x"55",
+ x"54",
+ x"54",
+ x"58",
+
+ -- 695: 0x00, 0x00, 0x45, 0x7C, 0x41,
+ x"00",
+ x"00",
+ x"45",
+ x"7C",
+ x"41",
+
+ -- 700: 0x00, 0x02, 0x45, 0x7D, 0x42,
+ x"00",
+ x"02",
+ x"45",
+ x"7D",
+ x"42",
+
+ -- 705: 0x00, 0x01, 0x45, 0x7C, 0x40,
+ x"00",
+ x"01",
+ x"45",
+ x"7C",
+ x"40",
+
+ -- 710: 0x7D, 0x12, 0x11, 0x12, 0x7D, // A-umlaut
+ x"7D",
+ x"12",
+ x"11",
+ x"12",
+ x"7D",
+
+ -- 715: 0xF0, 0x28, 0x25, 0x28, 0xF0,
+ x"F0",
+ x"28",
+ x"25",
+ x"28",
+ x"F0",
+
+ -- 720: 0x7C, 0x54, 0x55, 0x45, 0x00,
+ x"7C",
+ x"54",
+ x"55",
+ x"45",
+ x"00",
+
+ -- 725: 0x20, 0x54, 0x54, 0x7C, 0x54,
+ x"20",
+ x"54",
+ x"54",
+ x"7C",
+ x"54",
+
+ -- 730: 0x7C, 0x0A, 0x09, 0x7F, 0x49,
+ x"7C",
+ x"0A",
+ x"09",
+ x"7F",
+ x"49",
+
+ -- 735: 0x32, 0x49, 0x49, 0x49, 0x32,
+ x"32",
+ x"49",
+ x"49",
+ x"49",
+ x"32",
+
+ -- 740: 0x3A, 0x44, 0x44, 0x44, 0x3A, // o-umlaut
+ x"3A",
+ x"44",
+ x"44",
+ x"44",
+ x"3A",
+
+ -- 745: 0x32, 0x4A, 0x48, 0x48, 0x30,
+ x"32",
+ x"4A",
+ x"48",
+ x"48",
+ x"30",
+
+ -- 750: 0x3A, 0x41, 0x41, 0x21, 0x7A,
+ x"3A",
+ x"41",
+ x"41",
+ x"21",
+ x"7A",
+
+ -- 755: 0x3A, 0x42, 0x40, 0x20, 0x78,
+ x"3A",
+ x"42",
+ x"40",
+ x"20",
+ x"78",
+
+ -- 760: 0x00, 0x9D, 0xA0, 0xA0, 0x7D,
+ x"00",
+ x"9D",
+ x"A0",
+ x"A0",
+ x"7D",
+
+ -- 765: 0x3D, 0x42, 0x42, 0x42, 0x3D, // O-umlaut
+ x"3D",
+ x"42",
+ x"42",
+ x"42",
+ x"3D",
+
+ -- 770: 0x3D, 0x40, 0x40, 0x40, 0x3D,
+ x"3D",
+ x"40",
+ x"40",
+ x"40",
+ x"3D",
+
+ -- 775: 0x3C, 0x24, 0xFF, 0x24, 0x24,
+ x"3C",
+ x"24",
+ x"FF",
+ x"24",
+ x"24",
+
+ -- 780: 0x48, 0x7E, 0x49, 0x43, 0x66,
+ x"48",
+ x"7E",
+ x"49",
+ x"43",
+ x"66",
+
+ -- 785: 0x2B, 0x2F, 0xFC, 0x2F, 0x2B,
+ x"2B",
+ x"2F",
+ x"FC",
+ x"2F",
+ x"2B",
+
+ -- 790: 0xFF, 0x09, 0x29, 0xF6, 0x20,
+ x"FF",
+ x"09",
+ x"29",
+ x"F6",
+ x"20",
+
+ -- 795: 0xC0, 0x88, 0x7E, 0x09, 0x03,
+ x"C0",
+ x"88",
+ x"7E",
+ x"09",
+ x"03",
+
+ -- 800: 0x20, 0x54, 0x54, 0x79, 0x41,
+ x"20",
+ x"54",
+ x"54",
+ x"79",
+ x"41",
+
+ -- 805: 0x00, 0x00, 0x44, 0x7D, 0x41,
+ x"00",
+ x"00",
+ x"44",
+ x"7D",
+ x"41",
+
+ -- 810: 0x30, 0x48, 0x48, 0x4A, 0x32,
+ x"30",
+ x"48",
+ x"48",
+ x"4A",
+ x"32",
+
+ -- 815: 0x38, 0x40, 0x40, 0x22, 0x7A,
+ x"38",
+ x"40",
+ x"40",
+ x"22",
+ x"7A",
+
+ -- 820: 0x00, 0x7A, 0x0A, 0x0A, 0x72,
+ x"00",
+ x"7A",
+ x"0A",
+ x"0A",
+ x"72",
+
+ -- 825: 0x7D, 0x0D, 0x19, 0x31, 0x7D,
+ x"7D",
+ x"0D",
+ x"19",
+ x"31",
+ x"7D",
+
+ -- 830: 0x26, 0x29, 0x29, 0x2F, 0x28,
+ x"26",
+ x"29",
+ x"29",
+ x"2F",
+ x"28",
+
+ -- 835: 0x26, 0x29, 0x29, 0x29, 0x26,
+ x"26",
+ x"29",
+ x"29",
+ x"29",
+ x"26",
+
+ -- 840: 0x30, 0x48, 0x4D, 0x40, 0x20,
+ x"30",
+ x"48",
+ x"4D",
+ x"40",
+ x"20",
+
+ -- 845: 0x38, 0x08, 0x08, 0x08, 0x08,
+ x"38",
+ x"08",
+ x"08",
+ x"08",
+ x"08",
+
+ -- 850: 0x08, 0x08, 0x08, 0x08, 0x38,
+ x"08",
+ x"08",
+ x"08",
+ x"08",
+ x"38",
+
+ -- 855: 0x2F, 0x10, 0xC8, 0xAC, 0xBA,
+ x"2F",
+ x"10",
+ x"C8",
+ x"AC",
+ x"BA",
+
+ -- 860: 0x2F, 0x10, 0x28, 0x34, 0xFA,
+ x"2F",
+ x"10",
+ x"28",
+ x"34",
+ x"FA",
+
+ -- 865: 0x00, 0x00, 0x7B, 0x00, 0x00,
+ x"00",
+ x"00",
+ x"7B",
+ x"00",
+ x"00",
+
+ -- 870: 0x08, 0x14, 0x2A, 0x14, 0x22,
+ x"08",
+ x"14",
+ x"2A",
+ x"14",
+ x"22",
+
+ -- 875: 0x22, 0x14, 0x2A, 0x14, 0x08,
+ x"22",
+ x"14",
+ x"2A",
+ x"14",
+ x"08",
+
+ -- 880: 0xAA, 0x00, 0x55, 0x00, 0xAA,
+ x"AA",
+ x"00",
+ x"55",
+ x"00",
+ x"AA",
+
+ -- 885: 0xAA, 0x55, 0xAA, 0x55, 0xAA,
+ x"AA",
+ x"55",
+ x"AA",
+ x"55",
+ x"AA",
+
+ -- 890: 0x00, 0x00, 0x00, 0xFF, 0x00,
+ x"00",
+ x"00",
+ x"00",
+ x"FF",
+ x"00",
+
+ -- 895: 0x10, 0x10, 0x10, 0xFF, 0x00,
+ x"10",
+ x"10",
+ x"10",
+ x"FF",
+ x"00",
+
+ -- 900: 0x14, 0x14, 0x14, 0xFF, 0x00,
+ x"14",
+ x"14",
+ x"14",
+ x"FF",
+ x"00",
+
+ -- 905: 0x10, 0x10, 0xFF, 0x00, 0xFF,
+ x"10",
+ x"10",
+ x"FF",
+ x"00",
+ x"FF",
+
+ -- 910: 0x10, 0x10, 0xF0, 0x10, 0xF0,
+ x"10",
+ x"10",
+ x"F0",
+ x"10",
+ x"F0",
+
+ -- 915: 0x14, 0x14, 0x14, 0xFC, 0x00,
+ x"14",
+ x"14",
+ x"14",
+ x"FC",
+ x"00",
+
+ -- 920: 0x14, 0x14, 0xF7, 0x00, 0xFF,
+ x"14",
+ x"14",
+ x"F7",
+ x"00",
+ x"FF",
+
+ -- 925: 0x00, 0x00, 0xFF, 0x00, 0xFF,
+ x"00",
+ x"00",
+ x"FF",
+ x"00",
+ x"FF",
+
+ -- 930: 0x14, 0x14, 0xF4, 0x04, 0xFC,
+ x"14",
+ x"14",
+ x"F4",
+ x"04",
+ x"FC",
+
+ -- 935: 0x14, 0x14, 0x17, 0x10, 0x1F,
+ x"14",
+ x"14",
+ x"17",
+ x"10",
+ x"1F",
+
+ -- 940: 0x10, 0x10, 0x1F, 0x10, 0x1F,
+ x"10",
+ x"10",
+ x"1F",
+ x"10",
+ x"1F",
+
+ -- 945: 0x14, 0x14, 0x14, 0x1F, 0x00,
+ x"14",
+ x"14",
+ x"14",
+ x"1F",
+ x"00",
+
+ -- 950: 0x10, 0x10, 0x10, 0xF0, 0x00,
+ x"10",
+ x"10",
+ x"10",
+ x"F0",
+ x"00",
+
+ -- 955: 0x00, 0x00, 0x00, 0x1F, 0x10,
+ x"00",
+ x"00",
+ x"00",
+ x"1F",
+ x"10",
+
+ -- 960: 0x10, 0x10, 0x10, 0x1F, 0x10,
+ x"10",
+ x"10",
+ x"10",
+ x"1F",
+ x"10",
+
+ -- 965: 0x10, 0x10, 0x10, 0xF0, 0x10,
+ x"10",
+ x"10",
+ x"10",
+ x"F0",
+ x"10",
+
+ -- 970: 0x00, 0x00, 0x00, 0xFF, 0x10,
+ x"00",
+ x"00",
+ x"00",
+ x"FF",
+ x"10",
+
+ -- 975: 0x10, 0x10, 0x10, 0x10, 0x10,
+ x"10",
+ x"10",
+ x"10",
+ x"10",
+ x"10",
+
+ -- 980: 0x10, 0x10, 0x10, 0xFF, 0x10,
+ x"10",
+ x"10",
+ x"10",
+ x"FF",
+ x"10",
+
+ -- 985: 0x00, 0x00, 0x00, 0xFF, 0x14,
+ x"00",
+ x"00",
+ x"00",
+ x"FF",
+ x"14",
+
+ -- 990: 0x00, 0x00, 0xFF, 0x00, 0xFF,
+ x"00",
+ x"00",
+ x"FF",
+ x"00",
+ x"FF",
+
+ -- 995: 0x00, 0x00, 0x1F, 0x10, 0x17,
+ x"00",
+ x"00",
+ x"1F",
+ x"10",
+ x"17",
+
+ -- 1000: 0x00, 0x00, 0xFC, 0x04, 0xF4,
+ x"00",
+ x"00",
+ x"FC",
+ x"04",
+ x"F4",
+
+ -- 1005: 0x14, 0x14, 0x17, 0x10, 0x17,
+ x"14",
+ x"14",
+ x"17",
+ x"10",
+ x"17",
+
+ -- 1010: 0x14, 0x14, 0xF4, 0x04, 0xF4,
+ x"14",
+ x"14",
+ x"F4",
+ x"04",
+ x"F4",
+
+ -- 1015: 0x00, 0x00, 0xFF, 0x00, 0xF7,
+ x"00",
+ x"00",
+ x"FF",
+ x"00",
+ x"F7",
+
+ -- 1020: 0x14, 0x14, 0x14, 0x14, 0x14,
+ x"14",
+ x"14",
+ x"14",
+ x"14",
+ x"14",
+
+ -- 1025: 0x14, 0x14, 0xF7, 0x00, 0xF7,
+ x"14",
+ x"14",
+ x"F7",
+ x"00",
+ x"F7",
+
+ -- 1030: 0x14, 0x14, 0x14, 0x17, 0x14,
+ x"14",
+ x"14",
+ x"14",
+ x"17",
+ x"14",
+
+ -- 1035: 0x10, 0x10, 0x1F, 0x10, 0x1F,
+ x"10",
+ x"10",
+ x"1F",
+ x"10",
+ x"1F",
+
+ -- 1040: 0x14, 0x14, 0x14, 0xF4, 0x14,
+ x"14",
+ x"14",
+ x"14",
+ x"F4",
+ x"14",
+
+ -- 1045: 0x10, 0x10, 0xF0, 0x10, 0xF0,
+ x"10",
+ x"10",
+ x"F0",
+ x"10",
+ x"F0",
+
+ -- 1050: 0x00, 0x00, 0x1F, 0x10, 0x1F,
+ x"00",
+ x"00",
+ x"1F",
+ x"10",
+ x"1F",
+
+ -- 1055: 0x00, 0x00, 0x00, 0x1F, 0x14,
+ x"00",
+ x"00",
+ x"00",
+ x"1F",
+ x"14",
+
+ -- 1060: 0x00, 0x00, 0x00, 0xFC, 0x14,
+ x"00",
+ x"00",
+ x"00",
+ x"FC",
+ x"14",
+
+ -- 1065: 0x00, 0x00, 0xF0, 0x10, 0xF0,
+ x"00",
+ x"00",
+ x"F0",
+ x"10",
+ x"F0",
+
+ -- 1070: 0x10, 0x10, 0xFF, 0x10, 0xFF,
+ x"10",
+ x"10",
+ x"FF",
+ x"10",
+ x"FF",
+
+ -- 1075: 0x14, 0x14, 0x14, 0xFF, 0x14,
+ x"14",
+ x"14",
+ x"14",
+ x"FF",
+ x"14",
+
+ -- 1080: 0x10, 0x10, 0x10, 0x1F, 0x00,
+ x"10",
+ x"10",
+ x"10",
+ x"1F",
+ x"00",
+
+ -- 1085: 0x00, 0x00, 0x00, 0xF0, 0x10,
+ x"00",
+ x"00",
+ x"00",
+ x"F0",
+ x"10",
+
+ -- 1090: 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ x"FF",
+ x"FF",
+ x"FF",
+ x"FF",
+ x"FF",
+
+ -- 1095: 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
+ x"F0",
+ x"F0",
+ x"F0",
+ x"F0",
+ x"F0",
+
+ -- 1100: 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+ x"FF",
+ x"FF",
+ x"FF",
+ x"00",
+ x"00",
+
+ -- 1105: 0x00, 0x00, 0x00, 0xFF, 0xFF,
+ x"00",
+ x"00",
+ x"00",
+ x"FF",
+ x"FF",
+
+ -- 1110: 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
+ x"0F",
+ x"0F",
+ x"0F",
+ x"0F",
+ x"0F",
+
+ -- 1115: 0x38, 0x44, 0x44, 0x38, 0x44,
+ x"38",
+ x"44",
+ x"44",
+ x"38",
+ x"44",
+
+ -- 1120: 0xFC, 0x4A, 0x4A, 0x4A, 0x34, // sharp-s or beta
+ x"FC",
+ x"4A",
+ x"4A",
+ x"4A",
+ x"34",
+
+ -- 1125: 0x7E, 0x02, 0x02, 0x06, 0x06,
+ x"7E",
+ x"02",
+ x"02",
+ x"06",
+ x"06",
+
+ -- 1130: 0x02, 0x7E, 0x02, 0x7E, 0x02,
+ x"02",
+ x"7E",
+ x"02",
+ x"7E",
+ x"02",
+
+ -- 1135: 0x63, 0x55, 0x49, 0x41, 0x63,
+ x"63",
+ x"55",
+ x"49",
+ x"41",
+ x"63",
+
+ -- 1140: 0x38, 0x44, 0x44, 0x3C, 0x04,
+ x"38",
+ x"44",
+ x"44",
+ x"3C",
+ x"04",
+
+ -- 1145: 0x40, 0x7E, 0x20, 0x1E, 0x20,
+ x"40",
+ x"7E",
+ x"20",
+ x"1E",
+ x"20",
+
+ -- 1150: 0x06, 0x02, 0x7E, 0x02, 0x02,
+ x"06",
+ x"02",
+ x"7E",
+ x"02",
+ x"02",
+
+ -- 1155: 0x99, 0xA5, 0xE7, 0xA5, 0x99,
+ x"99",
+ x"A5",
+ x"E7",
+ x"A5",
+ x"99",
+
+ -- 1160: 0x1C, 0x2A, 0x49, 0x2A, 0x1C,
+ x"1C",
+ x"2A",
+ x"49",
+ x"2A",
+ x"1C",
+
+ -- 1165: 0x4C, 0x72, 0x01, 0x72, 0x4C,
+ x"4C",
+ x"72",
+ x"01",
+ x"72",
+ x"4C",
+
+ -- 1170: 0x30, 0x4A, 0x4D, 0x4D, 0x30,
+ x"30",
+ x"4A",
+ x"4D",
+ x"4D",
+ x"30",
+
+ -- 1175: 0x30, 0x48, 0x78, 0x48, 0x30,
+ x"30",
+ x"48",
+ x"78",
+ x"48",
+ x"30",
+
+ -- 1180: 0xBC, 0x62, 0x5A, 0x46, 0x3D,
+ x"BC",
+ x"62",
+ x"5A",
+ x"46",
+ x"3D",
+
+ -- 1185: 0x3E, 0x49, 0x49, 0x49, 0x00,
+ x"3E",
+ x"49",
+ x"49",
+ x"49",
+ x"00",
+
+ -- 1190: 0x7E, 0x01, 0x01, 0x01, 0x7E,
+ x"7E",
+ x"01",
+ x"01",
+ x"01",
+ x"7E",
+
+ -- 1195: 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
+ x"2A",
+ x"2A",
+ x"2A",
+ x"2A",
+ x"2A",
+
+ -- 1200: 0x44, 0x44, 0x5F, 0x44, 0x44,
+ x"44",
+ x"44",
+ x"5F",
+ x"44",
+ x"44",
+
+ -- 1205: 0x40, 0x51, 0x4A, 0x44, 0x40,
+ x"40",
+ x"51",
+ x"4A",
+ x"44",
+ x"40",
+
+ -- 1210: 0x40, 0x44, 0x4A, 0x51, 0x40,
+ x"40",
+ x"44",
+ x"4A",
+ x"51",
+ x"40",
+
+ -- 1215: 0x00, 0x00, 0xFF, 0x01, 0x03,
+ x"00",
+ x"00",
+ x"FF",
+ x"01",
+ x"03",
+
+ -- 1220: 0xE0, 0x80, 0xFF, 0x00, 0x00,
+ x"E0",
+ x"80",
+ x"FF",
+ x"00",
+ x"00",
+
+ -- 1225: 0x08, 0x08, 0x6B, 0x6B, 0x08,
+ x"08",
+ x"08",
+ x"6B",
+ x"6B",
+ x"08",
+
+ -- 1230: 0x36, 0x12, 0x36, 0x24, 0x36,
+ x"36",
+ x"12",
+ x"36",
+ x"24",
+ x"36",
+
+ -- 1235: 0x06, 0x0F, 0x09, 0x0F, 0x06,
+ x"06",
+ x"0F",
+ x"09",
+ x"0F",
+ x"06",
+
+ -- 1240: 0x00, 0x00, 0x18, 0x18, 0x00,
+ x"00",
+ x"00",
+ x"18",
+ x"18",
+ x"00",
+
+ -- 1245: 0x00, 0x00, 0x10, 0x10, 0x00,
+ x"00",
+ x"00",
+ x"10",
+ x"10",
+ x"00",
+
+ -- 1250: 0x30, 0x40, 0xFF, 0x01, 0x01,
+ x"30",
+ x"40",
+ x"FF",
+ x"01",
+ x"01",
+
+ -- 1255: 0x00, 0x1F, 0x01, 0x01, 0x1E,
+ x"00",
+ x"1F",
+ x"01",
+ x"01",
+ x"1E",
+
+ -- 1260: 0x00, 0x19, 0x1D, 0x17, 0x12,
+ x"00",
+ x"19",
+ x"1D",
+ x"17",
+ x"12",
+
+ -- 1265: 0x00, 0x3C, 0x3C, 0x3C, 0x3C,
+ x"00",
+ x"3C",
+ x"3C",
+ x"3C",
+ x"3C",
+
+ -- 1270: 0x00, 0x00, 0x00, 0x00, 0x00
+ x"00",
+ x"00",
+ x"00",
+ x"00",
+ x"00"
+);
+
+begin
+
+-- XXX to long par
+p0 : process (i_clk) is
+ variable index : integer range 0 to NUMBER_GLCDFONTC-1;
+begin
+ if (rising_edge(i_clk)) then
+ index := to_integer(unsigned(i_index))+1;
+ o_character <= GLCDFONTC(index);
+ end if;
+end process p0;
+
+--p0 : process (i_index) is
+--begin
+-- o_character <= GLCDFONTC(to_integer(unsigned(i_index)));
+--end process p0;
+
+end architecture behavioral_glcdfont;
diff --git a/myown_i2c/i2c.vhd b/myown_i2c/i2c.vhd
new file mode 100755
index 0000000..9042896
--- /dev/null
+++ b/myown_i2c/i2c.vhd
@@ -0,0 +1,269 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:46:01 08/21/2020
+-- Design Name:
+-- Module Name: i2c - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+--
+-- FileName: i2c_master.vhd
+-- Dependencies: none
+-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
+--
+-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
+-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
+-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
+-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
+-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
+-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
+-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
+-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
+--
+-- Version History
+-- Version 1.0 11/01/2012 Scott Larson
+-- Initial Public Release
+-- Version 2.0 06/20/2014 Scott Larson
+-- Added ability to interface with different slaves in the same transaction
+-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
+-- Corrected timing of when ack_error signal clears
+-- Version 2.1 10/21/2014 Scott Larson
+-- Replaced gated clock with clock enable
+-- Adjusted timing of SCL during start and stop conditions
+-- Version 2.2 02/05/2015 Scott Larson
+-- Corrected small SDA glitch introduced in version 2.1
+--
+--------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY i2c_master IS
+ GENERIC(
+ input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
+ bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz
+ PORT(
+ clk : IN STD_LOGIC; --system clock
+ reset_n : IN STD_LOGIC; --active low reset
+ ena : IN STD_LOGIC; --latch in command
+ addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
+ rw : IN STD_LOGIC; --'0' is write, '1' is read
+ data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
+ busy : OUT STD_LOGIC; --indicates transaction in progress
+ data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
+ ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
+ sda : INOUT STD_LOGIC; --serial data output of i2c bus
+ scl : INOUT STD_LOGIC); --serial clock output of i2c bus
+END i2c_master;
+
+ARCHITECTURE logic OF i2c_master IS
+ CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
+ TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
+ SIGNAL state : machine; --state machine
+ SIGNAL data_clk : STD_LOGIC; --data clock for sda
+ SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
+ SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
+ SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
+ SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
+ SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
+ SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
+ SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
+ SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
+ SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
+ SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
+BEGIN
+
+ --generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
+ PROCESS(clk, reset_n)
+ VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
+ BEGIN
+ IF(reset_n = '0') THEN --reset asserted
+ stretch <= '0';
+ count := 0;
+ ELSIF(clk'EVENT AND clk = '1') THEN
+ data_clk_prev <= data_clk; --store previous value of data clock
+ IF(count = divider*4-1) THEN --end of timing cycle
+ count := 0; --reset timer
+ ELSIF(stretch = '0') THEN --clock stretching from slave not detected
+ count := count + 1; --continue clock generation timing
+ END IF;
+ CASE count IS
+ WHEN 0 TO divider-1 => --first 1/4 cycle of clocking
+ scl_clk <= '0';
+ data_clk <= '0';
+ WHEN divider TO divider*2-1 => --second 1/4 cycle of clocking
+ scl_clk <= '0';
+ data_clk <= '1';
+ WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking
+ scl_clk <= '1'; --release scl
+ IF(scl = '0') THEN --detect if slave is stretching clock
+ stretch <= '1';
+ ELSE
+ stretch <= '0';
+ END IF;
+ data_clk <= '1';
+ WHEN OTHERS => --last 1/4 cycle of clocking
+ scl_clk <= '1';
+ data_clk <= '0';
+ END CASE;
+ END IF;
+ END PROCESS;
+
+ --state machine and writing to sda during scl low (data_clk rising edge)
+ PROCESS(clk, reset_n)
+ BEGIN
+ IF(reset_n = '0') THEN --reset asserted
+ state <= ready; --return to initial state
+ busy <= '1'; --indicate not available
+ scl_ena <= '0'; --sets scl high impedance
+ sda_int <= '1'; --sets sda high impedance
+ ack_error <= '0'; --clear acknowledge error flag
+ bit_cnt <= 7; --restarts data bit counter
+ data_rd <= "00000000"; --clear data read port
+ ELSIF(clk'EVENT AND clk = '1') THEN
+ IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
+ CASE state IS
+ WHEN ready => --idle state
+ IF(ena = '1') THEN --transaction requested
+ busy <= '1'; --flag busy
+ addr_rw <= addr & rw; --collect requested slave address and command
+ data_tx <= data_wr; --collect requested data to write
+ state <= start; --go to start bit
+ ELSE --remain idle
+ busy <= '0'; --unflag busy
+ state <= ready; --remain idle
+ END IF;
+ WHEN start => --start bit of transaction
+ busy <= '1'; --resume busy if continuous mode
+ sda_int <= addr_rw(bit_cnt); --set first address bit to bus
+ state <= command; --go to command
+ WHEN command => --address and command byte of transaction
+ IF(bit_cnt = 0) THEN --command transmit finished
+ sda_int <= '1'; --release sda for slave acknowledge
+ bit_cnt <= 7; --reset bit counter for "byte" states
+ state <= slv_ack1; --go to slave acknowledge (command)
+ ELSE --next clock cycle of command state
+ bit_cnt <= bit_cnt - 1; --keep track of transaction bits
+ sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
+ state <= command; --continue with command
+ END IF;
+ WHEN slv_ack1 => --slave acknowledge bit (command)
+ IF(addr_rw(0) = '0') THEN --write command
+ sda_int <= data_tx(bit_cnt); --write first bit of data
+ state <= wr; --go to write byte
+ ELSE --read command
+ sda_int <= '1'; --release sda from incoming data
+ state <= rd; --go to read byte
+ END IF;
+ WHEN wr => --write byte of transaction
+ busy <= '1'; --resume busy if continuous mode
+ IF(bit_cnt = 0) THEN --write byte transmit finished
+ sda_int <= '1'; --release sda for slave acknowledge
+ bit_cnt <= 7; --reset bit counter for "byte" states
+ state <= slv_ack2; --go to slave acknowledge (write)
+ ELSE --next clock cycle of write state
+ bit_cnt <= bit_cnt - 1; --keep track of transaction bits
+ sda_int <= data_tx(bit_cnt-1); --write next bit to bus
+ state <= wr; --continue writing
+ END IF;
+ WHEN rd => --read byte of transaction
+ busy <= '1'; --resume busy if continuous mode
+ IF(bit_cnt = 0) THEN --read byte receive finished
+ IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
+ sda_int <= '0'; --acknowledge the byte has been received
+ ELSE --stopping or continuing with a write
+ sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
+ END IF;
+ bit_cnt <= 7; --reset bit counter for "byte" states
+ data_rd <= data_rx; --output received data
+ state <= mstr_ack; --go to master acknowledge
+ ELSE --next clock cycle of read state
+ bit_cnt <= bit_cnt - 1; --keep track of transaction bits
+ state <= rd; --continue reading
+ END IF;
+ WHEN slv_ack2 => --slave acknowledge bit (write)
+ IF(ena = '1') THEN --continue transaction
+ busy <= '0'; --continue is accepted
+ addr_rw <= addr & rw; --collect requested slave address and command
+ data_tx <= data_wr; --collect requested data to write
+ IF(addr_rw = addr & rw) THEN --continue transaction with another write
+ sda_int <= data_wr(bit_cnt); --write first bit of data
+ state <= wr; --go to write byte
+ ELSE --continue transaction with a read or new slave
+ state <= start; --go to repeated start
+ END IF;
+ ELSE --complete transaction
+ state <= stop; --go to stop bit
+ END IF;
+ WHEN mstr_ack => --master acknowledge bit after a read
+ IF(ena = '1') THEN --continue transaction
+ busy <= '0'; --continue is accepted and data received is available on bus
+ addr_rw <= addr & rw; --collect requested slave address and command
+ data_tx <= data_wr; --collect requested data to write
+ IF(addr_rw = addr & rw) THEN --continue transaction with another read
+ sda_int <= '1'; --release sda from incoming data
+ state <= rd; --go to read byte
+ ELSE --continue transaction with a write or new slave
+ state <= start; --repeated start
+ END IF;
+ ELSE --complete transaction
+ state <= stop; --go to stop bit
+ END IF;
+ WHEN stop => --stop bit of transaction
+ busy <= '0'; --unflag busy
+ state <= ready; --go to idle state
+ END CASE;
+ ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
+ CASE state IS
+ WHEN start =>
+ IF(scl_ena = '0') THEN --starting new transaction
+ scl_ena <= '1'; --enable scl output
+ ack_error <= '0'; --reset acknowledge error output
+ END IF;
+ WHEN slv_ack1 => --receiving slave acknowledge (command)
+ IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
+ ack_error <= '1'; --set error output if no-acknowledge
+ END IF;
+ WHEN rd => --receiving slave data
+ data_rx(bit_cnt) <= sda; --receive current slave data bit
+ WHEN slv_ack2 => --receiving slave acknowledge (write)
+ IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
+ ack_error <= '1'; --set error output if no-acknowledge
+ END IF;
+ WHEN stop =>
+ scl_ena <= '0'; --disable scl
+ WHEN OTHERS =>
+ NULL;
+ END CASE;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ --set sda output
+ WITH state SELECT
+ sda_ena_n <= data_clk_prev WHEN start, --generate start condition
+ NOT data_clk_prev WHEN stop, --generate stop condition
+ sda_int WHEN OTHERS; --set to internal sda signal
+
+ --set scl and sda outputs
+ scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
+ sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
+
+END logic;
+
+
diff --git a/myown_i2c/ic_74hc73.vhd b/myown_i2c/ic_74hc73.vhd
new file mode 100755
index 0000000..ab6252a
--- /dev/null
+++ b/myown_i2c/ic_74hc73.vhd
@@ -0,0 +1,168 @@
+-- --------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:03:46 02/02/2022
+-- Design Name:
+-- Module Name: ic_74hc73 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ic_74hc73 is
+port (
+ signal i_j : in std_logic;
+ signal i_k : in std_logic;
+ signal i_r : in std_logic;
+ signal i_cpb : in std_logic;
+ signal o_q : out std_logic;
+ signal o_qb : out std_logic
+);
+end ic_74hc73;
+
+architecture Behavioral of ic_74hc73 is
+
+ constant delay_not : time := 0 ns;
+ constant delay_and : time := 0 ns;
+ constant delay_nand : time := 0 ns;
+ constant delay_nor2 : time := 0 ns;
+
+ component transmission_gate_rl is
+ generic (
+ delay_ba : time := 0 ns;
+ delay_baz : time := 0 ns
+ );
+ port (
+ io_a : inout std_logic;
+ io_b : in std_logic;
+ i_s : in std_logic;
+ i_sb : in std_logic
+ );
+ end component transmission_gate_rl;
+ for all : transmission_gate_rl use entity WORK.transmission_gate_rl(Behavioral);
+
+ component transmission_gate_lr is
+ generic (
+ delay_ab : time := 0 ns;
+ delay_abz : time := 0 ns
+ );
+ port (
+ io_a : in std_logic;
+ io_b : inout std_logic;
+ i_s : in std_logic;
+ i_sb : in std_logic
+ );
+ end component transmission_gate_lr;
+ for all : transmission_gate_lr use entity WORK.transmission_gate_lr(Behavioral);
+
+ component GATE_AND is
+ generic (delay_and : TIME := delay_and);
+ port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+ end component GATE_AND;
+ for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_LUT);
+
+ component GATE_NOR2 is
+ generic (delay_nor2 : TIME := delay_nor2);
+ port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+ end component GATE_NOR2;
+ for all : GATE_NOR2 use entity WORK.GATE_NOR2(GATE_NOR2_LUT);
+
+ component GATE_NOT is
+ generic (delay_not : TIME := delay_not);
+ port (A : in STD_LOGIC; B : out STD_LOGIC);
+ end component GATE_NOT;
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+-- for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+
+ component GATE_NAND is
+ Generic (delay_nand : time := delay_nand);
+ Port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+ end component GATE_NAND;
+ for all : GATE_NAND use entity WORK.GATE_NAND(GATE_NAND_LUT);
+
+ signal cp,cp_not1,cp_not2,cp_not3 : std_logic;
+ signal s,sb : std_logic;
+ signal nor2_1,nor2_2,nor2_3,nor2_4,nor2_5 : std_logic;
+ signal j_nor2,k_and : std_logic;
+ signal tg1_b,tg2_b,tg3_b,tg4_b : std_logic;
+ signal r1,r2,nor2_r1_cp,k_not,k_nor2,j_not,j_and,i_jk,g4_out,g8_not,g8_not1 : std_logic;
+
+ constant const_tg : time := 1 ns;
+ constant tg1_ab : time := const_tg;
+ constant tg1_abz : time := const_tg;
+ constant tg1_ba : time := const_tg;
+ constant tg1_baz : time := const_tg;
+ constant tg2_ab : time := const_tg;
+ constant tg2_abz : time := const_tg;
+ constant tg2_ba : time := const_tg;
+ constant tg2_baz : time := const_tg;
+ constant tg3_ab : time := const_tg;
+ constant tg3_abz : time := const_tg;
+ constant tg3_ba : time := const_tg;
+ constant tg3_baz : time := const_tg;
+ constant tg4_ab : time := const_tg;
+ constant tg4_abz : time := const_tg;
+ constant tg4_ba : time := const_tg;
+ constant tg4_baz : time := const_tg;
+
+begin
+
+ g1 : GATE_NOT port map (A => i_r, B => r1);
+ g2 : GATE_NOT port map (A => r1, B => r2);
+ g0 : GATE_NOT port map (A => i_cpb, B => cp);
+ g3 : GATE_NOR2 port map (A => r1, B => cp, C => nor2_r1_cp);
+ sb <= nor2_r1_cp;
+ g4 : GATE_NOT port map (A => nor2_r1_cp, B => s);
+
+ k_nor2_not_inst : GATE_NOT port map (A => i_k, B =>k_not);
+ k_nor2_inst : GATE_NOR2 port map (A => k_not, B => tg3_b, C => k_nor2);
+ j_and_not_inst : GATE_NOT port map (A => i_j, B =>j_not);
+ j_and_inst : GATE_AND port map (A => tg3_b, B => j_not, C => j_and);
+ jk_nor2_inst : GATE_NOR2 port map (A => k_nor2, B => j_and, C => i_jk);
+
+ tg1_lr : transmission_gate_lr generic map (delay_ab => tg1_ab,delay_abz => tg1_abz) port map (io_a => i_jk, io_b => tg1_b, i_s => sb, i_sb => s);
+ tg1_rl : transmission_gate_rl generic map (delay_ba => tg1_ba,delay_baz => tg1_baz) port map (io_a => tg1_b, io_b => i_jk, i_s => sb, i_sb => s);
+
+ g5 : GATE_NAND port map (A => tg1_b, B => r2, C => g4_out);
+
+ tg2_lr : transmission_gate_lr generic map (delay_ab => tg2_ab,delay_abz => tg2_abz) port map (io_a => tg1_b, io_b => tg2_b, i_s => sb, i_sb => s);
+ tg2_rl : transmission_gate_rl generic map (delay_ba => tg2_ba,delay_baz => tg2_baz) port map (io_a => tg2_b, io_b => tg1_b, i_s => sb, i_sb => s);
+
+ g6 : GATE_NOT port map (A => g4_out, B => tg2_b);
+
+ tg3_lr : transmission_gate_lr generic map (delay_ab => tg3_ab,delay_abz => tg3_abz) port map (io_a => g4_out, io_b => tg3_b, i_s => sb, i_sb => s);
+ tg3_rl : transmission_gate_rl generic map (delay_ba => tg3_ba,delay_baz => tg3_baz) port map (io_a => tg3_b, io_b => g4_out, i_s => sb, i_sb => s);
+
+ tg4_lr : transmission_gate_lr generic map (delay_ab => tg4_ab,delay_abz => tg4_abz) port map (io_a => tg3_b, io_b => tg4_b, i_s => sb, i_sb => s);
+ tg4_rl : transmission_gate_rl generic map (delay_ba => tg4_ba,delay_baz => tg4_baz) port map (io_a => tg4_b, io_b => tg3_b, i_s => sb, i_sb => s);
+
+ g8 : GATE_NOT port map (A => tg3_b, B => g8_not);
+
+ g7 : GATE_NOT port map (A => g8_not, B => tg4_b);
+
+ g9 : GATE_NOT port map (A => g8_not, B => o_qb);
+ g10 : GATE_NOT port map (A => g8_not, B => g8_not1);
+ g11 : GATE_NOT port map (A => g8_not1, B => o_q);
+
+end Behavioral;
+
diff --git a/myown_i2c/ic_hef4027b.vhd b/myown_i2c/ic_hef4027b.vhd
new file mode 100755
index 0000000..64e5e29
--- /dev/null
+++ b/myown_i2c/ic_hef4027b.vhd
@@ -0,0 +1,134 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:51:52 01/31/2022
+-- Design Name:
+-- Module Name: ic_hef4027b - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ic_hef4027b is
+port (
+ signal i_cp : in std_logic;
+ signal i_j : in std_logic;
+ signal i_k : in std_logic;
+ signal i_cd : in std_logic;
+ signal i_sd : in std_logic;
+ signal o_q : out std_logic;
+ signal o_qb : out std_logic
+);
+end ic_hef4027b;
+
+architecture Behavioral of ic_hef4027b is
+
+ constant delay_not : time := 0 ns;
+ constant delay_and : time := 0 ns;
+ constant delay_nor2 : time := 0 ns;
+
+ component transmission_gate_rl is
+ generic (
+ delay_ba : time := 0 ns;
+ delay_baz : time := 0 ns
+ );
+ port (
+ io_a : inout std_logic;
+ io_b : in std_logic;
+ i_s : in std_logic;
+ i_sb : in std_logic
+ );
+ end component transmission_gate_rl;
+ for all : transmission_gate_rl use entity WORK.transmission_gate_rl(Behavioral);
+
+ component transmission_gate_lr is
+ generic (
+ delay_ab : time := 0 ns;
+ delay_abz : time := 0 ns
+ );
+ port (
+ io_a : in std_logic;
+ io_b : inout std_logic;
+ i_s : in std_logic;
+ i_sb : in std_logic
+ );
+ end component transmission_gate_lr;
+ for all : transmission_gate_lr use entity WORK.transmission_gate_lr(Behavioral);
+
+ component GATE_AND is
+ generic (delay_and : TIME := delay_and);
+ port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+ end component GATE_AND;
+ for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_LUT);
+
+ component GATE_NOR2 is
+ generic (delay_nor2 : TIME := delay_nor2);
+ port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+ end component GATE_NOR2;
+ for all : GATE_NOR2 use entity WORK.GATE_NOR2(GATE_NOR2_LUT);
+
+ component GATE_NOT is
+ generic (delay_not : TIME := delay_not);
+ port (A : in STD_LOGIC; B : out STD_LOGIC);
+ end component GATE_NOT;
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ signal cp,cp_not1,cp_not2,cp_not3 : std_logic;
+ signal s,sb : std_logic;
+ signal nor2_1,nor2_2,nor2_3,nor2_4,nor2_5 : std_logic;
+ signal j_nor2,k_and : std_logic;
+ signal tg1_b,tg2_b,tg3_b : std_logic;
+
+begin
+
+-- cp_not_inst1 : GATE_NOT port map (A => i_cp, B => cp_not1);
+-- cp_not_inst2 : GATE_NOT port map (A => i_cp, B => cp_not2);
+ cp_not_inst3 : GATE_NOT port map (A => i_cp, B => cp_not3);
+-- s <= cp_not2;
+ s <= i_cp;
+ sb <= cp_not3;
+
+ j_nor2_inst : GATE_NOR2 port map (A => i_j, B => nor2_4, C => j_nor2);
+ k_and_inst : GATE_AND port map (A => nor2_4, B => i_k, C => k_and);
+ nor2_1_inst : GATE_NOR2 port map (A => j_nor2, B => k_and, C => nor2_1);
+
+ tg1_lr : transmission_gate_lr generic map (delay_ab => 1 ns,delay_abz => 1 ns) port map (io_a => nor2_1, io_b => tg1_b, i_s => sb, i_sb => s);
+ tg1_rl : transmission_gate_rl generic map (delay_ba => 1 ns,delay_baz => 1 ns) port map (io_a => tg1_b, io_b => nor2_1, i_s => sb, i_sb => s);
+ nor2_2_inst : GATE_NOR2 port map (A => tg1_b, B => i_sd, C => nor2_2);
+
+ nor2_3_inst : GATE_NOR2 port map (A => nor2_2, B => i_cd, C => nor2_3);
+ tg2_lr : transmission_gate_lr generic map (delay_ab => 1 ns,delay_abz => 1 ns) port map (io_a => nor2_3, io_b => tg1_b, i_s => s, i_sb => sb);
+ tg2_rl : transmission_gate_rl generic map (delay_ba => 1 ns,delay_baz => 1 ns) port map (io_a => tg1_b, io_b => nor2_3, i_s => s, i_sb => sb);
+
+ tg3_lr : transmission_gate_lr generic map (delay_ab => 1 ns,delay_abz => 1 ns) port map (io_a => nor2_2, io_b => tg3_b, i_s => s, i_sb => sb);
+ tg3_rl : transmission_gate_rl generic map (delay_ba => 1 ns,delay_baz => 1 ns) port map (io_a => tg3_b, io_b => nor2_2, i_s => s, i_sb => sb);
+ nor2_4_inst : GATE_NOR2 port map (A => tg3_b, B => i_cd, C => nor2_4);
+
+ nor2_5_inst : GATE_NOR2 port map (A => nor2_4, B => i_sd, C => nor2_5);
+ tg4_lr : transmission_gate_lr generic map (delay_ab => 1 ns,delay_abz => 1 ns) port map (io_a => nor2_5, io_b => tg3_b, i_s => sb, i_sb => s);
+ tg4_rl : transmission_gate_rl generic map (delay_ba => 1 ns,delay_baz => 1 ns) port map (io_a => tg3_b, io_b => nor2_5, i_s => sb, i_sb => s);
+
+ g1_not_inst : GATE_NOT port map (A => tg3_b, B => o_q);
+ g2_not_inst : GATE_NOT port map (A => nor2_4, B => o_qb);
+
+end Behavioral;
diff --git a/myown_i2c/my_i2c.vhd b/myown_i2c/my_i2c.vhd
new file mode 100755
index 0000000..c9f4f71
--- /dev/null
+++ b/myown_i2c/my_i2c.vhd
@@ -0,0 +1,308 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:47:31 08/21/2020
+-- Design Name:
+-- Module Name: power_on - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_constants1.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity my_i2c is
+generic(
+BOARD_CLOCK : INTEGER := G_BOARD_CLOCK;
+BUS_CLOCK : INTEGER := G_BUS_CLOCK
+);
+port(
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_slave_address : in std_logic_vector(0 to G_SLAVE_ADDRESS_SIZE-1);
+i_bytes_to_send : in std_logic_vector(0 to G_BYTE_SIZE-1);
+i_enable : in std_logic;
+o_busy : out std_logic;
+o_sda : out std_logic;
+o_scl : out std_logic
+);
+end my_i2c;
+
+architecture Behavioral of my_i2c is
+ constant I2C_COUNTER_MAX : integer := (BOARD_CLOCK / BUS_CLOCK) / 4;
+
+ signal clock : std_logic;
+ signal temp_sda : std_logic;
+ signal temp_sck : std_logic;
+ signal instruction_index : integer range 0 to 1;
+
+ type state is (idle,sda_start,start,slave_address,slave_address_lastbit,slave_rw,slave_ack,get_instruction,data,data_lastbit,data_ack,stop,sda_stop);
+ signal c_state,n_state : state;
+
+ type clock_mode is (c0,c1,c2,c3);
+ signal c_cmode,n_cmode : clock_mode;
+
+ constant SLAVE_INDEX_MAX : integer := G_SLAVE_ADDRESS_SIZE;
+ constant SDA_WIDTH_MAX : integer := 2;
+ signal data_index : integer range 0 to G_BYTE_SIZE-1;
+ signal slave_index : integer range 0 to SLAVE_INDEX_MAX-1;
+ signal sda_width: integer range 0 to SDA_WIDTH_MAX-1;
+
+begin
+
+ i2c_clock_process : process (i_clock,i_reset) is
+ variable count : integer range 0 to (I2C_COUNTER_MAX*4)-1;
+ begin
+ if (i_reset = '1') then
+ clock <= '0';
+ count := 0;
+ elsif (rising_edge(i_clock)) then
+ if (count = (I2C_COUNTER_MAX*4)-1) then
+ clock <= '1';
+ count := 0;
+ else
+ clock <= '0';
+ count := count + 1;
+ end if;
+ end if;
+ end process i2c_clock_process;
+
+ i2c_send_sequence_fsm : process (clock,i_reset,i_enable) is
+ begin
+ if (i_reset = '1') then
+ n_state <= idle;
+ n_cmode <= c0;
+ o_busy <= '0';
+ data_index <= 0;
+ slave_index <= 0;
+ sda_width <= 0;
+ temp_sda <= '1';
+ temp_sck <= '1';
+ elsif (rising_edge(clock)) then
+ c_state <= n_state;
+ c_cmode <= n_cmode;
+ case c_cmode is
+ when c0 =>
+ n_cmode <= c1;
+ when c1 =>
+ n_cmode <= c2;
+ when c2 =>
+ n_cmode <= c3;
+ when c3 =>
+ n_cmode <= c0;
+ when others => null;
+ end case;
+ case c_state is
+ when idle =>
+ if (i_enable = '1') then
+ n_state <= sda_start;
+ else
+ n_state <= idle;
+ end if;
+ when sda_start =>
+ instruction_index <= 0;
+ temp_sck <= '1';
+ temp_sda <= '1';
+ n_state <= start;
+ o_busy <= '1';
+ when start =>
+ temp_sda <= '0';
+ n_state <= slave_address;
+ when slave_address =>
+ if (c_cmode /= c1 and c_cmode /= c2 and (c_cmode = c0 or c_cmode = c3)) then
+ temp_sck <= '0';
+ end if;
+ if ((c_cmode = c1 or c_cmode = c2) and c_cmode /= c0 and c_cmode /= c3) then
+ temp_sck <= '1';
+ end if;
+ if (c_cmode = c2 and slave_index = 0) then
+ temp_sda <= '0';
+ end if;
+ if (slave_index = SLAVE_INDEX_MAX-1) then
+ n_state <= slave_address_lastbit;
+ sda_width <= 0;
+ else
+ if (c_cmode = c0) then
+ temp_sda <= i_slave_address(slave_index);
+ if (sda_width = SDA_WIDTH_MAX-1) then
+ slave_index <= slave_index + 1;
+ sda_width <= 0;
+ n_state <= slave_address;
+ else
+ sda_width <= sda_width + 1;
+ n_state <= slave_address;
+ end if;
+ end if;
+ end if;
+ when slave_address_lastbit =>
+ if (c_cmode /= c1 and c_cmode /= c2 and (c_cmode = c0 or c_cmode = c3)) then
+ temp_sck <= '0';
+ end if;
+ if ((c_cmode = c1 or c_cmode = c2) and c_cmode /= c0 and c_cmode /= c3) then
+ temp_sck <= '1';
+ end if;
+ if (c_cmode = c0) then
+ temp_sda <= i_slave_address(SLAVE_INDEX_MAX-1);
+ if (sda_width = SDA_WIDTH_MAX-1) then
+ sda_width <= 0;
+ n_state <= slave_rw;
+ else
+ sda_width <= sda_width + 1;
+ n_state <= slave_address_lastbit;
+ end if;
+ end if;
+ when slave_rw =>
+ if (c_cmode /= c1 and c_cmode /= c2 and (c_cmode = c0 or c_cmode = c3)) then
+ temp_sck <= '0';
+ end if;
+ if ((c_cmode = c1 or c_cmode = c2) and c_cmode /= c0 and c_cmode /= c3) then
+ temp_sck <= '1';
+ end if;
+ if (c_cmode = c0) then
+ temp_sda <= '0';
+ if (sda_width = SDA_WIDTH_MAX-1) then
+ sda_width <= 0;
+ n_state <= slave_ack;
+ else
+ sda_width <= sda_width + 1;
+ n_state <= slave_rw;
+ end if;
+ end if;
+ when slave_ack =>
+ if (c_cmode /= c1 and c_cmode /= c2 and (c_cmode = c0 or c_cmode = c3)) then
+ temp_sck <= '0';
+ end if;
+ if ((c_cmode = c1 or c_cmode = c2) and c_cmode /= c0 and c_cmode /= c3) then
+ temp_sck <= '1';
+ end if;
+ if (c_cmode = c0) then
+ temp_sda <= '1';
+ if (sda_width = SDA_WIDTH_MAX-1) then
+ sda_width <= 0;
+ n_state <= data;
+ else
+ sda_width <= sda_width + 1;
+ n_state <= slave_ack;
+ end if;
+ end if;
+ when get_instruction =>
+ if (i_enable = '1') then
+ n_state <= data;
+ o_busy <= '0';
+ else
+ n_state <= stop;
+ end if;
+ when data =>
+ o_busy <= '1';
+ if (c_cmode /= c1 and c_cmode /= c2 and (c_cmode = c0 or c_cmode = c3)) then
+ temp_sck <= '0';
+ end if;
+ if ((c_cmode = c1 or c_cmode = c2) and c_cmode /= c0 and c_cmode /= c3) then
+ temp_sck <= '1';
+ end if;
+ if (data_index = G_BYTE_SIZE-1) then
+ sda_width <= 0;
+ n_state <= data_lastbit;
+ else
+ if (c_cmode = c0) then
+ temp_sda <= i_bytes_to_send(data_index);
+ if (sda_width = SDA_WIDTH_MAX-1) then
+ data_index <= data_index + 1;
+ sda_width <= 0;
+ n_state <= data;
+ else
+ sda_width <= sda_width + 1;
+ n_state <= data;
+ end if;
+ end if;
+ end if;
+ when data_lastbit =>
+ if (c_cmode /= c1 and c_cmode /= c2 and (c_cmode = c0 or c_cmode = c3)) then
+ temp_sck <= '0';
+ end if;
+ if ((c_cmode = c1 or c_cmode = c2) and c_cmode /= c0 and c_cmode /= c3) then
+ temp_sck <= '1';
+ end if;
+ if (c_cmode = c0) then
+ temp_sda <= i_bytes_to_send(G_BYTE_SIZE-1);
+ if (sda_width = SDA_WIDTH_MAX-1) then
+ sda_width <= sda_width + 1;
+ n_state <= data_lastbit;
+ else
+ sda_width <= 0;
+ n_state <= data_ack;
+ end if;
+ end if;
+ when data_ack =>
+ if (c_cmode /= c1 and c_cmode /= c2 and (c_cmode = c0 or c_cmode = c3)) then
+ temp_sck <= '0';
+ end if;
+ if ((c_cmode = c1 or c_cmode = c2) and c_cmode /= c0 and c_cmode /= c3) then
+ temp_sck <= '1';
+ end if;
+ if (c_cmode = c0) then
+ temp_sda <= '1';
+ if (sda_width = SDA_WIDTH_MAX-1) then
+ instruction_index <= instruction_index + 1;
+ sda_width <= 0;
+ n_state <= get_instruction;
+ data_index <= 0;
+ else
+ sda_width <= sda_width + 1;
+ n_state <= data_ack;
+ end if;
+ end if;
+ when stop =>
+ if (c_cmode /= c1 and c_cmode /= c2 and (c_cmode = c0 or c_cmode = c3)) then
+ temp_sck <= '0';
+ end if;
+ if ((c_cmode = c1 or c_cmode = c2) and c_cmode /= c0 and c_cmode /= c3) then
+ temp_sck <= '1';
+ end if;
+ if (c_cmode = c0) then
+ temp_sda <= '0';
+ if (sda_width = SDA_WIDTH_MAX-1) then
+ sda_width <= 0;
+ n_state <= sda_stop;
+ else
+ sda_width <= sda_width + 1;
+ n_state <= stop;
+ end if;
+ end if;
+ when sda_stop =>
+ temp_sck <= '1';
+ temp_sda <= '1';
+ data_index <= 0;
+ slave_index <= 0;
+ sda_width <= 0;
+ o_busy <= '0';
+ n_state <= idle;
+ when others => null;
+ end case;
+ end if;
+ end process i2c_send_sequence_fsm;
+
+ o_sda <= '0' when temp_sda = '0' else 'Z';
+ o_scl <= '0' when temp_sck = '0' else 'Z';
+
+end architecture Behavioral;
diff --git a/myown_i2c/my_i2c_fsm.vhd b/myown_i2c/my_i2c_fsm.vhd
new file mode 100755
index 0000000..135ae84
--- /dev/null
+++ b/myown_i2c/my_i2c_fsm.vhd
@@ -0,0 +1,531 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:47:31 08/21/2020
+-- Design Name:
+-- Module Name: power_on - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_constants1.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity my_i2c_fsm is
+generic(
+BOARD_CLOCK : INTEGER := G_BOARD_CLOCK;
+BUS_CLOCK : INTEGER := G_BUS_CLOCK
+);
+port(
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_slave_address : in std_logic_vector(0 to G_SLAVE_ADDRESS_SIZE-1);
+i_bytes_to_send : in std_logic_vector(0 to G_BYTE_SIZE-1);
+i_enable : in std_logic;
+o_busy : out std_logic;
+o_byte_sended : out std_logic;
+o_sda : out std_logic;
+o_scl : out std_logic
+);
+end my_i2c_fsm;
+
+architecture Behavioral of my_i2c_fsm is
+
+ signal clock : std_logic;
+ signal temp_sda : std_logic;
+ signal temp_sck : std_logic;
+
+ type state is (
+ idle,
+ sda_start,
+ start,
+ slave_address,
+ slave_address_lastbit,
+ slave_rw,
+ slave_ack,
+ data,
+ data_ack,
+ stop,
+ sda_stop
+ );
+ signal c_state_i2c_fsm,n_state_i2c_fsm : state;
+
+ type clock_mode is (c0,c1,c2,c3);
+ signal c_cmode0,n_cmode0 : clock_mode;
+ signal c_cmode0_rc_clock : std_logic;
+
+ component ripple_counter is
+ Generic (
+ N : integer := 32;
+ MAX : integer := 1
+ );
+ Port (
+ i_clock : in std_logic;
+ i_cpb : in std_logic;
+ i_mrb : in std_logic;
+ i_ud : in std_logic;
+ o_q : inout std_logic_vector(N-1 downto 0)
+ );
+ end component ripple_counter;
+ constant RC0_N : integer := 4;
+ constant RC0_MAX : integer := G_BYTE_SIZE;
+ signal rc0_cpb,rc0_mrb : std_logic;
+ signal rc0_q : std_logic_vector(RC0_N-1 downto 0);
+ signal rc0_ping : std_logic;
+ constant RC1_N : integer := 4;
+ constant RC1_MAX : integer := G_BYTE_SIZE;
+ signal rc1_cpb,rc1_mrb : std_logic;
+ signal rc1_q : std_logic_vector(RC1_N-1 downto 0);
+ signal rc1_ping : std_logic;
+ constant RC2_N : integer := 4;
+ constant RC2_MAX : integer := G_BYTE_SIZE;
+ signal rc2_cpb,rc2_mrb : std_logic;
+ signal rc2_q : std_logic_vector(RC2_N-1 downto 0);
+ signal rc2_ping : std_logic;
+
+-- attribute KEEP : string;
+-- attribute KEEP of clock : signal is "yes";
+-- attribute KEEP of i_clock : signal is "yes";
+-- attribute CLOCK_SIGNAL : string;
+-- attribute CLOCK_SIGNAL of clock : signal is "yes"; --{yes | no};
+-- attribute CLOCK_SIGNAL of i_clock : signal is "yes"; --{yes | no};
+-- attribute CLOCK_SIGNAL of temp_sck : signal is "no"; --{yes | no};
+-- attribute CLOCK_SIGNAL of temp_sda : signal is "no"; --{yes | no};
+-- attribute BUFFER_TYPE : string;
+-- attribute BUFFER_TYPE of clock : signal is "BUFG"; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
+-- attribute BUFFER_TYPE of i_clock : signal is "NONE"; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
+-- attribute BUFFER_TYPE of temp_sck : signal is "none"; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
+-- attribute BUFFER_TYPE of temp_sda : signal is "none"; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
+
+ constant I2C_COUNTER_MAX : integer := BOARD_CLOCK / BUS_CLOCK;
+ signal count : integer range 0 to I2C_COUNTER_MAX-1;
+
+-- attribute loc : string;
+-- attribute loc of {signal_name | label_name }: {signal |label} is "location ";
+-- attribute loc of "count" : signal is "SLICE_X64Y92:SLICE_X79Y105";
+-- attribute loc of "entity_rc0" : label is "SLICE_X64Y92:SLICE_X79Y105";
+-- attribute loc of "entity_rc1" : label is "SLICE_X64Y92:SLICE_X79Y105";
+-- attribute loc of "entity_rc2" : label is "SLICE_X64Y92:SLICE_X79Y105";
+
+ signal pu : std_logic;
+
+begin
+
+ entity_rc0 : ripple_counter
+ Generic map (N => RC0_N, MAX => RC0_MAX)
+ Port map (
+ i_clock => c_cmode0_rc_clock,
+ i_cpb => rc0_cpb,
+ i_mrb => rc0_mrb,
+ i_ud => '1',
+ o_q => rc0_q
+ );
+
+ entity_rc1 : ripple_counter
+ Generic map (N => RC1_N, MAX => RC1_MAX)
+ Port map (
+ i_clock => c_cmode0_rc_clock,
+ i_cpb => rc1_cpb,
+ i_mrb => rc1_mrb,
+ i_ud => '1',
+ o_q => rc1_q
+ );
+
+ entity_rc2 : ripple_counter
+ Generic map (N => RC2_N, MAX => RC2_MAX)
+ Port map (
+ i_clock => c_cmode0_rc_clock,
+ i_cpb => rc2_cpb,
+ i_mrb => rc2_mrb,
+ i_ud => '1',
+ o_q => rc2_q
+ );
+
+ i2c_clock_process : process (i_clock) is
+ begin
+ if (rising_edge(i_clock)) then
+ if (i_reset = '1') then
+ clock <= '0';
+ count <= 0;
+ elsif (count = I2C_COUNTER_MAX-1) then
+ clock <= '1';
+ count <= 0;
+ else
+ clock <= '0';
+ count <= count + 1;
+ end if;
+ end if;
+ end process i2c_clock_process;
+
+ clock_mode_0_seq : process (clock) is
+ begin
+ if (rising_edge(clock)) then
+ if (i_reset = '1') then
+ c_cmode0 <= c0;
+ else
+ c_cmode0 <= n_cmode0;
+ end if;
+ end if;
+ end process clock_mode_0_seq;
+
+ clock_mode_0_com : process (c_cmode0) is
+ begin
+ n_cmode0 <= c_cmode0;
+ c_cmode0_rc_clock <= '0';
+ case c_cmode0 is
+ when c0 =>
+ n_cmode0 <= c1;
+ c_cmode0_rc_clock <= '1';
+ when c1 =>
+ n_cmode0 <= c2;
+ c_cmode0_rc_clock <= '0';
+ when c2 =>
+ n_cmode0 <= c3;
+ c_cmode0_rc_clock <= '0';
+ when c3 =>
+ n_cmode0 <= c0;
+ c_cmode0_rc_clock <= '0';
+ when others =>
+ n_cmode0 <= c0;
+ c_cmode0_rc_clock <= '0';
+ end case;
+ end process clock_mode_0_com;
+
+ p2 : process (clock) is
+ begin
+ if (rising_edge(clock)) then
+ if (i_reset = '1') then
+ c_state_i2c_fsm <= idle;
+ else
+ c_state_i2c_fsm <= n_state_i2c_fsm;
+ end if;
+ end if;
+ end process p2;
+
+ i2c_send_sequence_fsm : process (c_state_i2c_fsm,c_cmode0,i_enable,i_slave_address,i_bytes_to_send
+ ,temp_sda,temp_sck) is
+ variable vtemp_sda,vtemp_sck : std_logic;
+ variable index1,index2 : integer range 0 to 7;
+ begin
+ n_state_i2c_fsm <= c_state_i2c_fsm;
+-- vtemp_sda := temp_sda;
+-- vtemp_sck := temp_sck;
+ index1 := to_integer(unsigned(rc0_q));
+ index2 := to_integer(unsigned(rc1_q));
+ case c_state_i2c_fsm is
+ when idle =>
+ o_byte_sended <= '0';
+ rc0_mrb <= '1';
+ rc1_mrb <= '1';
+ rc2_mrb <= '1';
+ rc0_cpb <= '0';
+ rc1_cpb <= '0';
+ rc2_cpb <= '0';
+ o_busy <= '0';
+ if (c_cmode0 = c0) then
+ vtemp_sda := '1';
+ vtemp_sck := '1';
+ end if;
+ if (c_cmode0 /= c0) then
+ vtemp_sda := temp_sda;
+ vtemp_sck := temp_sck;
+ end if;
+ if (i_enable = '1') then
+ n_state_i2c_fsm <= sda_start;
+ else
+ n_state_i2c_fsm <= idle;
+ end if;
+ when sda_start =>
+ o_byte_sended <= '0';
+ rc0_mrb <= '0';
+ rc1_mrb <= '0';
+ rc2_mrb <= '0';
+ rc0_cpb <= '0';
+ rc1_cpb <= '0';
+ rc2_cpb <= '0';
+ if (c_cmode0 = c0) then
+ vtemp_sck := '1';
+ vtemp_sda := '1';
+ n_state_i2c_fsm <= start;
+ end if;
+ if (c_cmode0 /= c0) then
+ vtemp_sck := temp_sck;
+ vtemp_sda := temp_sda;
+ n_state_i2c_fsm <= sda_start;
+ end if;
+ o_busy <= '1';
+ when start =>
+ o_byte_sended <= '0';
+ rc0_mrb <= '0';
+ rc1_mrb <= '0';
+ rc2_mrb <= '0';
+ rc0_cpb <= '0';
+ rc1_cpb <= '0';
+ rc2_cpb <= '0';
+ if (c_cmode0 = c0) then
+ vtemp_sda := '0';
+ vtemp_sck := '1';
+ n_state_i2c_fsm <= slave_address;
+ end if;
+ if (c_cmode0 /= c0) then
+ vtemp_sda := temp_sda;
+ vtemp_sck := temp_sck;
+ n_state_i2c_fsm <= start;
+ end if;
+ o_busy <= '1';
+ when slave_address =>
+ o_byte_sended <= '0';
+ rc0_mrb <= '0';
+ rc1_mrb <= '0';
+ rc2_mrb <= '0';
+ rc0_cpb <= '1';
+ rc1_cpb <= '0';
+ rc2_cpb <= '0';
+ o_busy <= '1';
+ if (c_cmode0 /= c1 and c_cmode0 /= c2 and (c_cmode0 = c0 or c_cmode0 = c3)) then
+ vtemp_sck := '0';
+ end if;
+ if ((c_cmode0 = c1 or c_cmode0 = c2) and c_cmode0 /= c0 and c_cmode0 /= c3) then
+ vtemp_sck := '1';
+ end if;
+ if (index1 = G_SLAVE_ADDRESS_SIZE-1) then
+ vtemp_sda := temp_sda;
+ n_state_i2c_fsm <= slave_address_lastbit;
+ else
+ if (c_cmode0 = c0) then
+ vtemp_sda := i_slave_address(index1);
+ n_state_i2c_fsm <= slave_address;
+ end if;
+ if (c_cmode0 /= c0) then
+ vtemp_sda := temp_sda;
+ n_state_i2c_fsm <= slave_address;
+ end if;
+ end if;
+ when slave_address_lastbit =>
+ o_byte_sended <= '0';
+ rc0_mrb <= '0';
+ rc1_mrb <= '0';
+ rc2_mrb <= '0';
+ rc0_cpb <= '0';
+ rc1_cpb <= '0';
+ rc2_cpb <= '0';
+ o_busy <= '1';
+ if (c_cmode0 /= c1 and c_cmode0 /= c2 and (c_cmode0 = c0 or c_cmode0 = c3)) then
+ vtemp_sck := '0';
+ end if;
+ if ((c_cmode0 = c1 or c_cmode0 = c2) and c_cmode0 /= c0 and c_cmode0 /= c3) then
+ vtemp_sck := '1';
+ else
+ vtemp_sck := '0';
+ end if;
+ if (c_cmode0 = c0) then
+ vtemp_sda := i_slave_address(G_SLAVE_ADDRESS_SIZE-1);
+ n_state_i2c_fsm <= slave_rw;
+ end if;
+ if (c_cmode0 /= c0) then
+ vtemp_sda := temp_sda;
+ n_state_i2c_fsm <= slave_address_lastbit;
+ end if;
+ when slave_rw =>
+ o_byte_sended <= '0';
+ rc0_mrb <= '0';
+ rc1_mrb <= '0';
+ rc2_mrb <= '0';
+ rc0_cpb <= '0';
+ rc1_cpb <= '0';
+ rc2_cpb <= '0';
+ o_busy <= '1';
+ if (c_cmode0 /= c1 and c_cmode0 /= c2 and (c_cmode0 = c0 or c_cmode0 = c3)) then
+ vtemp_sck := '0';
+ end if;
+ if ((c_cmode0 = c1 or c_cmode0 = c2) and c_cmode0 /= c0 and c_cmode0 /= c3) then
+ vtemp_sck := '1';
+ else
+ vtemp_sck := '0';
+ end if;
+ if (c_cmode0 = c0) then
+ vtemp_sda := '0';
+ n_state_i2c_fsm <= slave_ack;
+ end if;
+ if (c_cmode0 /= c0) then
+ vtemp_sda := temp_sda;
+ n_state_i2c_fsm <= slave_rw;
+ end if;
+ when slave_ack =>
+ o_byte_sended <= '0';
+ rc0_mrb <= '0';
+ rc1_mrb <= '0';
+ rc2_mrb <= '0';
+ rc0_cpb <= '0';
+ rc1_cpb <= '0';
+ rc2_cpb <= '0';
+ o_busy <= '1';
+ if (c_cmode0 /= c1 and c_cmode0 /= c2 and (c_cmode0 = c0 or c_cmode0 = c3)) then
+ vtemp_sck := '0';
+ end if;
+ if ((c_cmode0 = c1 or c_cmode0 = c2) and c_cmode0 /= c0 and c_cmode0 /= c3) then
+ vtemp_sck := '1';
+ else
+ vtemp_sck := '0';
+ end if;
+ if (c_cmode0 = c0) then
+ vtemp_sda := '1';
+ n_state_i2c_fsm <= data;
+ end if;
+ if (c_cmode0 /= c0) then
+ vtemp_sda := '0';
+ n_state_i2c_fsm <= slave_ack;
+ end if;
+ when data =>
+ o_byte_sended <= '0';
+ rc0_mrb <= '0';
+ rc1_mrb <= '0';
+ rc2_mrb <= '0';
+ rc0_cpb <= '0';
+ rc1_cpb <= '1';
+ rc2_cpb <= '0';
+ o_busy <= '1';
+ if (c_cmode0 /= c1 and c_cmode0 /= c2 and (c_cmode0 = c0 or c_cmode0 = c3)) then
+ vtemp_sck := '0';
+ end if;
+ if ((c_cmode0 = c1 or c_cmode0 = c2) and c_cmode0 /= c0 and c_cmode0 /= c3) then
+ vtemp_sck := '1';
+ else
+ vtemp_sck := '0';
+ end if;
+ if (c_cmode0 = c0) then
+ vtemp_sda := i_bytes_to_send(index2);
+ if (index2 = G_BYTE_SIZE-1) then
+ n_state_i2c_fsm <= data_ack;
+ else
+ n_state_i2c_fsm <= data;
+ end if;
+ end if;
+ if (c_cmode0 /= c0) then
+ vtemp_sda := temp_sda;
+ end if;
+ when data_ack =>
+ rc0_mrb <= '0';
+ rc1_mrb <= '0';
+ rc2_mrb <= '0';
+ rc0_cpb <= '0';
+ rc1_cpb <= '0';
+ rc2_cpb <= '1';
+ if (c_cmode0 /= c1 and c_cmode0 /= c2 and (c_cmode0 = c0 or c_cmode0 = c3)) then
+ vtemp_sck := '0';
+ end if;
+ if ((c_cmode0 = c1 or c_cmode0 = c2) and c_cmode0 /= c0 and c_cmode0 /= c3) then
+ vtemp_sck := '1';
+ else
+ vtemp_sck := '0';
+ end if;
+ if (c_cmode0 = c0) then
+ vtemp_sda := '1';
+ end if;
+ if (c_cmode0 /= c0) then
+ vtemp_sda := temp_sda;
+ end if;
+ if (i_enable = '1') then
+ if (to_integer(unsigned(rc2_q)) = RC2_MAX-7) then
+ n_state_i2c_fsm <= data;
+ o_busy <= '0';
+ o_byte_sended <= '1';
+ rc2_mrb <= '1';
+ else
+ n_state_i2c_fsm <= data_ack;
+ o_busy <= '1';
+ o_byte_sended <= '0';
+ rc2_mrb <= '0';
+ end if;
+ else
+ if (to_integer(unsigned(rc2_q)) = RC2_MAX-7) then
+ n_state_i2c_fsm <= stop;
+ o_busy <= '1';
+ o_byte_sended <= '0';
+ rc2_mrb <= '1';
+ else
+ n_state_i2c_fsm <= data_ack;
+ o_busy <= '1';
+ o_byte_sended <= '0';
+ rc2_mrb <= '0';
+ end if;
+ end if;
+ when stop =>
+ o_busy <= '1';
+ o_byte_sended <= '0';
+ rc0_mrb <= '0';
+ rc1_mrb <= '0';
+ rc2_mrb <= '0';
+ rc0_cpb <= '0';
+ rc1_cpb <= '0';
+ rc2_cpb <= '0';
+ if (c_cmode0 = c0) then
+ vtemp_sda := '0';
+ vtemp_sck := '1';
+ n_state_i2c_fsm <= sda_stop;
+ end if;
+ if (c_cmode0 /= c0) then
+ vtemp_sda := temp_sda;
+ vtemp_sck := temp_sck;
+ n_state_i2c_fsm <= stop;
+ end if;
+ when sda_stop =>
+ rc0_mrb <= '0';
+ rc1_mrb <= '0';
+ rc2_mrb <= '0';
+ rc0_cpb <= '0';
+ rc1_cpb <= '0';
+ rc2_cpb <= '0';
+ o_byte_sended <= '0';
+ if (c_cmode0 = c0) then
+ vtemp_sck := '1';
+ vtemp_sda := '1';
+ n_state_i2c_fsm <= idle;
+ end if;
+ if (c_cmode0 /= c0) then
+ vtemp_sck := temp_sck;
+ vtemp_sda := temp_sda;
+ n_state_i2c_fsm <= sda_stop;
+ end if;
+ o_busy <= '1';
+ when others =>
+ n_state_i2c_fsm <= idle;
+ o_byte_sended <= '0';
+ rc0_mrb <= '1';
+ rc1_mrb <= '1';
+ rc2_mrb <= '1';
+ rc0_cpb <= '0';
+ rc1_cpb <= '0';
+ rc2_cpb <= '0';
+ o_busy <= '0';
+ vtemp_sda := temp_sda;
+ vtemp_sck := temp_sck;
+ end case;
+ temp_sda <= vtemp_sda;
+ temp_sck <= vtemp_sck;
+ end process i2c_send_sequence_fsm;
+
+ o_sda <= '0' when temp_sda = '0' else 'Z';
+ o_scl <= '0' when temp_sck = '0' else 'Z';
+
+end architecture Behavioral;
diff --git a/myown_i2c/my_i2c_pc.vhd b/myown_i2c/my_i2c_pc.vhd
new file mode 100755
index 0000000..001f88e
--- /dev/null
+++ b/myown_i2c/my_i2c_pc.vhd
@@ -0,0 +1,437 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date:
+-- Design Name:
+-- Module Name:
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_constants1.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity my_i2c_pc is
+port(
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_slave_address : in std_logic_vector(0 to G_SLAVE_ADDRESS_SIZE-1);
+i_slave_rw : in std_logic;
+i_bytes_to_send : in std_logic_vector(0 to G_BYTE_SIZE-1);
+i_enable : in std_logic;
+o_busy : out std_logic;
+o_sda : out std_logic;
+o_scl : out std_logic
+);
+end my_i2c_pc;
+
+architecture Behavioral of my_i2c_pc is
+
+ constant N : integer := 20;
+
+ constant delay_and : time := 0 ns;
+ constant delay_or : time := 0 ns;
+ constant delay_not : time := 0 ns;
+ constant delay_nand : time := 0 ns;
+ constant delay_nor2 : time := 0 ns;
+ constant delay_nand2 : time := 0 ns;
+ constant delay_nand3 : time := 0 ns;
+ constant delay_and3 : time := 0 ns;
+ constant ADDRESS_SIZE : integer := 7;
+ constant BYTE_SIZE : integer := 8;
+ constant QMUX_SIZE : integer := N/2;
+
+ component GATE_NOT is
+ generic (delay_not : TIME := 0 ns);
+ port (A : in STD_LOGIC; B : out STD_LOGIC);
+ end component GATE_NOT;
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+-- for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ component GATE_OR is
+ generic (delay_or : TIME := 0 ns);
+ port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+ end component GATE_OR;
+ for all : GATE_OR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+-- for all : GATE_OR use entity WORK.GATE_OR(GATE_OR_LUT);
+
+ component GATE_AND is
+ generic (delay_and : TIME := 0 ns);
+ port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+ end component GATE_AND;
+ for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+-- for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_LUT);
+
+ component GATE_NAND is
+ generic (delay_nand : TIME := 0 ns);
+ port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+ end component GATE_NAND;
+-- for all : GATE_NAND use entity WORK.GATE_NAND(GATE_NAND_BEHAVIORAL_1);
+ for all : GATE_NAND use entity WORK.GATE_NAND(GATE_NAND_LUT);
+
+-- component GATE_NOR2 is
+-- generic (delay_nor2 : TIME := 0 ns);
+-- port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+-- end component GATE_NOR2;
+-- for all : GATE_NOR2 use entity WORK.GATE_NOR2(GATE_NOR2_BEHAVIORAL_1);
+---- for all : GATE_NOR2 use entity WORK.GATE_NOR2(GATE_NOR2_LUT);
+
+ component MUX_21 is
+ generic (delay_and : TIME := 0 ns; delay_or : TIME := 0 ns; delay_not : TIME := 0 ns);
+ port (S,A,B:in STD_LOGIC; C:out STD_LOGIC);
+ end component MUX_21;
+ for all : MUX_21 use entity WORK.MUX_21(MUX_21_LUT_1);
+
+ component MUX_41 is
+ generic (delay_and : TIME := 0 ns; delay_or : TIME := 0 ns; delay_not : TIME := 0 ns);
+ port (S1,S2,A,B,C,D:in STD_LOGIC; E:out STD_LOGIC);
+ end component MUX_41;
+ for all : MUX_41 use entity WORK.MUX_41(Behavioral);
+
+ component MUX_81 is
+ generic (delay_and : TIME := 0 ns; delay_or : TIME := 0 ns; delay_not : TIME := 0 ns);
+ port (in0,in1,in2,in3,in4,in5,in6,in7 : in std_logic; s0,s1,s2 : in std_logic; o : out std_logic);
+ end component MUX_81;
+ for all : MUX_81 use entity WORK.MUX_81(Behavioral);
+
+ signal sda_chain : std_logic_vector(N-1 downto 0);
+ signal sda_condition_chain_start : std_logic_vector(N/2-1 downto 0);
+ signal sda_condition_chain_stop : std_logic_vector(N/2-1 downto 0);
+ signal sda_start_condition_out : std_logic;
+ signal sda_start_condition : std_logic;
+ signal sda_stop_condition_out : std_logic;
+ signal sda_stop_condition : std_logic;
+-- signal qmux : std_logic_vector(QMUX_SIZE-1 downto 0);
+-- signal qnmux : std_logic_vector(QMUX_SIZE-1 downto 0);
+ signal encoder_main : std_logic_vector(2 downto 0);
+-- signal all1_slv : std_logic_vector(N-1 downto 0);
+-- signal all1 : std_logic;
+-- signal all0_slv : std_logic_vector(N-1 downto 0);
+-- signal all0 : std_logic;
+ signal left1_slv : std_logic_vector(N-1 downto 0);
+ signal left1 : std_logic;
+-- signal right1_slv : std_logic_vector(N-1 downto 0);
+-- signal right1 : std_logic;
+-- signal left0_slv : std_logic_vector(N-1 downto 0);
+-- signal left0 : std_logic;
+-- signal right0_slv : std_logic_vector(N-1 downto 0);
+-- signal right0 : std_logic;
+ signal clock : std_logic;
+ signal t1 : std_logic;
+-- signal t2 : std_logic;
+ signal amux : std_logic_vector(ADDRESS_SIZE+1+1 downto 0);
+ signal acopy : std_logic_vector(ADDRESS_SIZE-1 downto 0);
+ signal encoder_address : std_logic_vector(2 downto 0);
+ signal addressmux : std_logic;
+ signal dmux : std_logic_vector(BYTE_SIZE+1 downto 0); -- byte size + ack
+ signal dcopy : std_logic_vector(BYTE_SIZE-1 downto 0);
+ signal encoder_data : std_logic_vector(3 downto 0);
+ signal datamux : std_logic;
+ signal datamux_ack : std_logic;
+ signal t3,t4 : std_logic;
+ signal t5 : std_logic;
+ signal sda : std_logic;
+ signal t4_not_left1 : std_logic;
+ signal t3_temp,t4_temp : std_logic;
+
+begin
+
+-- -- all N 1
+-- all1_generate : for i in 0 to N-1 generate
+-- all1_first : if (i=0) generate
+-- all1_f : GATE_AND generic map (delay_and => delay_and) port map (A => sda_chain(i), B => sda_chain(i+1), C => all1_slv(i));
+-- end generate all1_first;
+-- all1_middle : if (i>0 and i delay_and) port map (A => all1_slv(i-1), B => sda_chain(i), C => all1_slv(i));
+-- end generate all1_middle;
+-- all1_last : if (i=N-1) generate
+-- all1_l : GATE_AND generic map (delay_and => delay_and) port map (A => all1_slv(i-1), B => sda_chain(i), C => all1_slv(i));
+-- all1 <= all1_slv(i);
+-- end generate all1_last;
+-- end generate all1_generate;
+
+-- -- all N 0
+-- all0_generate : for i in 0 to N-1 generate
+-- all0_first : if (i=0) generate
+-- all0_f : GATE_NAND generic map (delay_nand => delay_nand) port map (A => not sda_chain(i), B => not sda_chain(i+1), C => all0_slv(i));
+-- end generate all0_first;
+-- all0_middle : if (i>0 and i delay_nand) port map (A => not all0_slv(i-1), B => not sda_chain(i), C => all0_slv(i));
+-- end generate all0_middle;
+-- all0_last : if (i=N-1) generate
+-- all0_l : GATE_AND generic map (delay_and => delay_and) port map (A => not all0_slv(i-1), B => not sda_chain(i), C => all0_slv(i));
+-- all0 <= all0_slv(i);
+-- end generate all0_last;
+-- end generate all0_generate;
+---- pd0 : KEEPER port map (O => all0);
+
+ -- N/2 left have 1, N/2 right have 0
+ left1_generate : for i in 0 to N-1 generate
+ left1_first : if (i=0) generate
+ left1_f : GATE_NAND generic map (delay_nand => delay_nand) port map (A => not sda_chain(i), B => not sda_chain(i+1), C => left1_slv(i));
+ end generate left1_first;
+ left1_first1 : if (i>0 and i delay_nand) port map (A => not left1_slv(i-1), B => not sda_chain(i), C => left1_slv(i));
+ end generate left1_first1;
+ left1_middle : if (i=N/2) generate
+ left1_m1 : GATE_AND generic map (delay_and => delay_and) port map (A => not left1_slv(i-1), B => sda_chain(i), C => left1_slv(i));
+ end generate left1_middle;
+ left1_last : if (i>N/2 and i delay_and) port map (A => left1_slv(i-1), B => sda_chain(i), C => left1_slv(i));
+ end generate left1_last;
+ left1_last1 : if (i=N-1) generate
+ left1_l1 : GATE_AND generic map (delay_and => delay_and) port map (A => left1_slv(i-1), B => sda_chain(i), C => left1_slv(i));
+ left1 <= left1_slv(i);
+-- right0 <= left1_slv(i);
+-- right0_slv <= left1_slv;
+ end generate left1_last1;
+ end generate left1_generate;
+--left1_bufgce : BUFGCE port map (I => left1_slv(N-1), CE => not left1_slv(N-1), O => left1);
+
+ -- N/2 right have 1, N/2 left have 0
+-- right1_generate : for i in 0 to N-1 generate
+-- right1_first : if (i=0) generate
+-- right1_f : GATE_AND generic map (delay_and => delay_and) port map (A => sda_chain(i), B => sda_chain(i+1), C => right1_slv(i));
+-- end generate right1_first;
+-- right1_first1 : if (i>0 and i delay_and) port map (A => right1_slv(i-1), B => sda_chain(i), C => right1_slv(i));
+-- end generate right1_first1;
+-- right1_middle : if (i=N/2) generate
+-- right1_m1 : GATE_NAND generic map (delay_nand => delay_nand) port map (A => right1_slv(i-1), B => not sda_chain(i), C => right1_slv(i));
+-- end generate right1_middle;
+-- right1_last : if (i>N/2 and i delay_nand) port map (A => not right1_slv(i-1), B => not sda_chain(i), C => right1_slv(i));
+-- end generate right1_last;
+-- right1_last1 : if (i=N-1) generate
+-- right1_l1 : GATE_NAND generic map (delay_nand => delay_nand) port map (A => not right1_slv(i-1), B => not sda_chain(i), C => right1_slv(i));
+-- right1 <= not right1_slv(i);
+-- left0 <= not right1_slv(i);
+-- left0_slv <= right1_slv;
+-- end generate right1_last1;
+-- end generate right1_generate;
+
+-- generate N latch chain
+sda_chain_generate : for i in 0 to N-1 generate
+ sda_chain_first : if (i=0) generate
+ sda_chain_f : LDCPE generic map (INIT => '0') port map (Q => sda_chain(i), D => clock, CLR => i_reset, G => i_clock, GE => not i_clock, PRE => '0');
+ end generate sda_chain_first;
+ sda_chain_middle : if (i>0 and i '0') port map (Q => sda_chain(i), D => sda_chain(i-1), CLR => i_reset, G => i_clock, GE => not i_clock, PRE => '0');
+ end generate sda_chain_middle;
+ sda_chain_last : if (i=N-1) generate
+ sda_chain_l : LDCPE generic map (INIT => '0') port map (Q => sda_chain(i), D => sda_chain(i-1), CLR => i_reset, G => i_clock, GE => not i_clock, PRE => '0');
+ end generate sda_chain_last;
+end generate sda_chain_generate;
+
+sda_start_condition <= sda_condition_chain_start(N/2-1);
+sda_start_condition_generate : for i in 0 to N/2-1 generate
+ sda_start_condition_first : if (i=N/2-1) generate
+ sda_start_condition_f : GATE_NAND generic map (delay_nand => delay_nand) port map (A => not sda_condition_chain_start(i-1), B => sda_chain(i), C => sda_condition_chain_start(i));
+ end generate sda_start_condition_first;
+ sda_start_condition_middle : if (i>0 and i delay_nand) port map (A => not sda_condition_chain_start(i-1), B => sda_chain(i), C => sda_condition_chain_start(i));
+ end generate sda_start_condition_middle;
+ sda_start_condition_last : if (i=0) generate
+ sda_start_condition_l : GATE_NAND generic map (delay_nand => delay_nand) port map (A => '1', B => sda_chain(i), C => sda_condition_chain_start(i));
+ end generate sda_start_condition_last;
+end generate sda_start_condition_generate;
+
+sda_stop_condition <= sda_condition_chain_stop(N/2-1);
+sda_stop_condition_generate : for i in 0 to N/2-1 generate
+ sda_stop_condition_first : if (i=0) generate
+ sda_stop_condition_f : GATE_NAND generic map (delay_nand => delay_nand) port map (A => '0', B => not sda_chain(i), C => sda_condition_chain_stop(i));
+ end generate sda_stop_condition_first;
+ sda_stop_condition_middle : if (i>0 and i delay_nand) port map (A => not sda_condition_chain_stop(i-1), B => sda_chain(i), C => sda_condition_chain_stop(i));
+ end generate sda_stop_condition_middle;
+ sda_stop_condition_last : if (i=N/2-1) generate
+ sda_stop_condition_l : GATE_NAND generic map (delay_nand => delay_nand) port map (A => sda_condition_chain_stop(i-1), B => not sda_chain(i), C => sda_condition_chain_stop(i));
+ end generate sda_stop_condition_last;
+end generate sda_stop_condition_generate;
+
+sda_start_condition_out <= sda_start_condition when clock = '1' else '0';
+--sdasc_inst1 : LDCPE generic map (INIT => '1') port map (Q => sda_start_condition_out, D => '1', CLR => not sda_start_condition and i_enable, G => i_clock, GE => not i_clock, PRE => sda_start_condition and i_enable);
+
+sda_stop_condition_out <= sda_stop_condition when clock = '1' else '0';
+--sdasc_inst2 : LDCPE generic map (INIT => '1') port map (Q => sda_stop_condition_out, D => '1', CLR => not sda_stop_condition and i_enable, G => i_clock, GE => not i_clock, PRE => sda_stop_condition and i_enable);
+
+t1 <= sda_chain(N-1) and i_enable;
+MUXCY_inst : MUXCY port map (O => clock, CI => '0', DI => '1', S => t1);
+
+--t2 <= i_enable and not all1;
+--mux_chain_generate : for i in 0 to QMUX_SIZE-1 generate
+-- a : if (i=0) generate
+-- chaina : LDCPE generic map (INIT => '0') port map (Q => qmux(i), D => '1', CLR => qmux(QMUX_SIZE-1), G => all1, GE => t2, PRE => '0');
+-- end generate a;
+-- b : if (i>0 and i '0') port map (Q => qmux(i), D => qmux(i-1), CLR => qmux(QMUX_SIZE-1), G => all1, GE => t2, PRE => '0');
+-- end generate b;
+-- c : if (i=QMUX_SIZE-1) generate
+-- chainc : LDCPE generic map (INIT => '0') port map (Q => qmux(i), D => qmux(i-1), CLR => qmux(QMUX_SIZE-1), G => all1, GE => t2, PRE => '0');
+-- end generate c;
+--end generate mux_chain_generate;
+
+-- in3 - ACK
+m81_main_inst : MUX_81 generic map (delay_and => delay_and, delay_or => delay_or, delay_not => delay_not) port map (S0 => encoder_main(0), S1 => encoder_main(1), S2 => encoder_main(2), in0 => sda_start_condition_out, in1 => addressmux, in2 => i_slave_rw, in3 => '1', in4 => datamux_ack, in5 => sda_stop_condition_out, in6 => '0', in7 => '1', o => sda);
+
+OBUFT_sda_data_inst : OBUFT generic map (DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map (O => o_sda, I => sda, T => sda);
+
+OBUFT_scl_clock_inst : OBUFT generic map (DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW") port map (O => o_scl, I => clock, T => clock);
+
+pencoder_main : process (amux,dmux,i_enable) is
+ constant size : integer := amux'length + dmux'length + 1;
+ variable t : std_logic_vector(size-1 downto 0);
+begin
+ t := amux&dmux&i_enable;
+ if (std_match(t,"000000000000000000001")) then encoder_main <= "000"; -- start
+
+ elsif (std_match(t,"000000000100000000001")) then encoder_main <= "001"; -- address 0
+ elsif (std_match(t,"000000001100000000001")) then encoder_main <= "001"; -- address 1
+ elsif (std_match(t,"000000011100000000001")) then encoder_main <= "001"; -- address 2
+ elsif (std_match(t,"000000111100000000001")) then encoder_main <= "001"; -- address 3
+ elsif (std_match(t,"000001111100000000001")) then encoder_main <= "001"; -- address 4
+ elsif (std_match(t,"000011111100000000001")) then encoder_main <= "001"; -- address 5
+ elsif (std_match(t,"000111111100000000001")) then encoder_main <= "001"; -- address 6
+ elsif (std_match(t,"001111111100000000001")) then encoder_main <= "010"; -- rw
+ elsif (std_match(t,"011111111100000000001")) then encoder_main <= "011"; -- ack
+
+ elsif (std_match(t,"111111111100000000011")) then encoder_main <= "100"; -- data 0
+ elsif (std_match(t,"111111111100000000111")) then encoder_main <= "100"; -- data 1
+ elsif (std_match(t,"111111111100000001111")) then encoder_main <= "100"; -- data 2
+ elsif (std_match(t,"111111111100000011111")) then encoder_main <= "100"; -- data 3
+ elsif (std_match(t,"111111111100000111111")) then encoder_main <= "100"; -- data 4
+ elsif (std_match(t,"111111111100001111111")) then encoder_main <= "100"; -- data 5
+ elsif (std_match(t,"111111111100011111111")) then encoder_main <= "100"; -- data 6
+ elsif (std_match(t,"111111111100111111111")) then encoder_main <= "100"; -- data 7
+ elsif (std_match(t,"111111111101111111111")) then encoder_main <= "100"; -- ack
+
+ elsif (std_match(t,"--------------------0")) then encoder_main <= "101"; -- stop
+ else encoder_main <= "XXX";
+ end if;
+end process pencoder_main;
+
+address_chain_generate : for i in 0 to ADDRESS_SIZE+1+1 generate
+ address_chain_first : if (i=0) generate
+ address_chain_f : LDCPE generic map (INIT => '0') port map (Q => amux(i), D => '1', CLR => '0', G => left1, GE => not left1, PRE => '0');
+ end generate address_chain_first;
+ address_chain_middle : if (i>0 and i '0') port map (Q => amux(i), D => amux(i-1), CLR => '0', G => left1, GE => not left1, PRE => '0');
+ end generate address_chain_middle;
+ address_chain_last : if (i=ADDRESS_SIZE+1+1) generate
+ address_chain_l : LDCPE generic map (INIT => '0') port map (Q => amux(i), D => amux(i-1), CLR => '0', G => left1, GE => not left1, PRE => '0');
+ end generate address_chain_last;
+end generate address_chain_generate;
+
+pencoder_address : process (amux) is
+begin
+ if (amux = "0000000001") then encoder_address <= "000";
+ elsif (amux = "0000000011") then encoder_address <= "001";
+ elsif (amux = "0000000111") then encoder_address <= "010";
+ elsif (amux = "0000001111") then encoder_address <= "011";
+ elsif (amux = "0000011111") then encoder_address <= "100";
+ elsif (amux = "0000111111") then encoder_address <= "101";
+ elsif (amux = "0001111111") then encoder_address <= "110";
+ elsif (amux = "0011111111") then encoder_address <= "111";
+-- elsif (amux = "00111111111") then encoder_address <= "000";
+-- elsif (amux = "00111111111") then encoder_address <= "001";
+-- elsif (amux = "01111111111") then encoder_address <= "010";
+-- elsif (amux = "11111111111") then encoder_address <= "011";
+ else
+ encoder_address <= "XXX";
+ end if;
+end process pencoder_address;
+
+mux81_address_inst : MUX_81 generic map (delay_and => delay_and, delay_or => delay_or, delay_not => delay_not) port map (in0 => acopy(0), in1 => acopy(1), in2 => acopy(2), in3 => acopy(3), in4 => acopy(4), in5 => acopy(5), in6 => acopy(6), in7 => i_slave_rw, s0 => encoder_address(0), s1 => encoder_address(1), s2 => encoder_address(2), o => addressmux);
+
+address_chain_copy_generate : for i in 0 to ADDRESS_SIZE-1 generate
+ address_chain_copy_first : if (i=0) generate
+ address_chain_copy_f : LDCPE generic map (INIT => '0') port map (Q => acopy(i), D => '0', CLR => not i_slave_address(i), G => left1, GE => left1, PRE => i_slave_address(i));
+ end generate address_chain_copy_first;
+ address_chain_copy_middle : if (i>0 and i '0') port map (Q => acopy(i), D => acopy(i-1), CLR => not i_slave_address(i), G => left1, GE => left1, PRE => i_slave_address(i));
+ end generate address_chain_copy_middle;
+ address_chain_copy_last : if (i=ADDRESS_SIZE-1) generate
+ address_chain_copy_l : LDCPE generic map (INIT => '0') port map (Q => acopy(i), D => acopy(i-1), CLR => not i_slave_address(i), G => left1, GE => left1, PRE => i_slave_address(i));
+ end generate address_chain_copy_last;
+end generate address_chain_copy_generate;
+
+--t3 <= amux(N/2-1) and left1;
+--t4 <= amux(N/2-1) and not left1;
+t3_and : GATE_AND generic map (delay_and => delay_and) port map (A => amux(N/2-1), B => left1, C => t3_temp);
+--t3_bufgce : BUFGCE port map (I => left1, CE => amux(ADDRESS_SIZE+1), O => t3_temp);
+t3_ldcpe : LDCPE generic map (INIT => '0') port map (Q => t3, D => t3_temp, CLR => '0', G => '1', GE => '1', PRE => '0');
+t4_not : GATE_NOT generic map (delay_not => delay_not) port map (A => left1, B => t4_not_left1);
+t4_and : GATE_AND generic map (delay_and => delay_and) port map (A => amux(N/2-1), B => t4_not_left1, C => t4_temp);
+--t4_bufgce : BUFGCE port map (I => t4_not_left1, CE => amux(ADDRESS_SIZE+1), O => t4_temp);
+t4_ldcpe : LDCPE generic map (INIT => '0') port map (Q => t4, D => t4_temp, CLR => '0', G => '1', GE => '1', PRE => '0');
+
+o_busy <= dmux(0);
+data_chain_generate : for i in 0 to BYTE_SIZE+1 generate
+ data_chain_first : if (i=0) generate
+ data_chain_f : LDCPE generic map (INIT => '0') port map (Q => dmux(i), D => '1', CLR => dmux(BYTE_SIZE+1), G => t3, GE => left1, PRE => '0');
+ end generate data_chain_first;
+ data_chain_middle : if (i>0 and i '0') port map (Q => dmux(i), D => dmux(i-1), CLR => dmux(BYTE_SIZE+1), G => t4, GE => left1, PRE => '0');
+ end generate data_chain_middle;
+ data_chain_last : if (i=BYTE_SIZE+1) generate
+ data_chain_l : LDCPE generic map (INIT => '0') port map (Q => dmux(i), D => dmux(i-1), CLR => dmux(BYTE_SIZE+1), G => t4, GE => left1, PRE => '0');
+ end generate data_chain_last;
+end generate data_chain_generate;
+
+pencoder_data : process (dmux) is
+begin
+ if (dmux = "0000000000") then encoder_data <= "0000";
+ elsif (dmux = "0000000001") then encoder_data <= "0001";
+ elsif (dmux = "0000000011") then encoder_data <= "0010";
+ elsif (dmux = "0000000111") then encoder_data <= "0011";
+ elsif (dmux = "0000001111") then encoder_data <= "0100";
+ elsif (dmux = "0000011111") then encoder_data <= "0101";
+ elsif (dmux = "0000111111") then encoder_data <= "0110";
+ elsif (dmux = "0001111111") then encoder_data <= "0111";
+ elsif (dmux = "0011111111") then encoder_data <= "1000";
+ elsif (dmux = "0111111111") then encoder_data <= "1001";
+ elsif (dmux = "1111111111") then encoder_data <= "1010";
+ else
+ encoder_data <= "XXXX";
+ end if;
+end process pencoder_data;
+
+-- B - ack
+t5 <= encoder_data(0) and not encoder_data(1) and not encoder_data(2) and encoder_data(3);
+mux21_datamux_ack_inst : MUX_21 generic map (delay_and => delay_and, delay_or => delay_or, delay_not => delay_not) port map (S => t5, A => datamux, B => '1', C => datamux_ack);
+
+mux81_data_inst : MUX_81 generic map (delay_and => delay_and, delay_or => delay_or, delay_not => delay_not) port map (in0 => dcopy(0), in1 => dcopy(1), in2 => dcopy(2), in3 => dcopy(3), in4 => dcopy(4), in5 => dcopy(5), in6 => dcopy(6), in7 => dcopy(7), s0 => encoder_data(0), s1 => encoder_data(1), s2 => encoder_data(2), o => datamux);
+
+data_chain_copy_generate : for i in 0 to BYTE_SIZE-1 generate
+ data_chain_copy_first : if (i=0) generate
+ data_chain_copy_f : LDCPE generic map (INIT => '0') port map (Q => dcopy(i), D => '0', CLR => not i_bytes_to_send(i), G => left1, GE => left1, PRE => i_bytes_to_send(i));
+ end generate data_chain_copy_first;
+ data_chain_copy_middle : if (i>0 and i '0') port map (Q => dcopy(i), D => dcopy(i-1), CLR => not i_bytes_to_send(i), G => left1, GE => left1, PRE => i_bytes_to_send(i));
+ end generate data_chain_copy_middle;
+ data_chain_copy_last : if (i=BYTE_SIZE-1) generate
+ data_chain_copy_l : LDCPE generic map (INIT => '0') port map (Q => dcopy(i), D => dcopy(i-1), CLR => not i_bytes_to_send(i), G => left1, GE => left1, PRE => i_bytes_to_send(i));
+ end generate data_chain_copy_last;
+end generate data_chain_copy_generate;
+
+end architecture Behavioral;
diff --git a/myown_i2c/my_i2c_pc2.vhd b/myown_i2c/my_i2c_pc2.vhd
new file mode 100755
index 0000000..f2e5241
--- /dev/null
+++ b/myown_i2c/my_i2c_pc2.vhd
@@ -0,0 +1,1142 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date:
+-- Design Name:
+-- Module Name:
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_constants1.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity my_i2c_pc2 is
+port(
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_slave_address : in std_logic_vector(0 to G_SLAVE_ADDRESS_SIZE-1);
+i_slave_rw : in std_logic;
+i_bytes_to_send : in std_logic_vector(0 to G_BYTE_SIZE-1);
+i_enable : in std_logic;
+--o_busy : out std_logic;
+o_sda : out std_logic;
+o_scl : out std_logic
+);
+end my_i2c_pc2;
+
+architecture Behavioral of my_i2c_pc2 is
+
+ constant N : integer := 10;
+
+ constant delay_and : time := 0 ns;
+ constant delay_or : time := 0 ns;
+ constant delay_not : time := 0 ns;
+ constant delay_nand : time := 0 ns; -- XXX 0 make osc on behav
+ constant delay_nor2 : time := 0 ns;
+ constant delay_nand2 : time := 0 ns;
+ constant delay_nand3 : time := 0 ns;
+ constant delay_nand4 : time := 0 ns;
+ constant delay_and3 : time := 0 ns;
+ constant delay_mr : time := 0 ns;
+ constant ADDRESS_SIZE : integer := 7;
+ constant BYTE_SIZE : integer := 8;
+ constant ADDRESS_SIZE_RW_ACK : integer := ADDRESS_SIZE + 1 + 1;
+ constant BYTE_SIZE_ACK : integer := BYTE_SIZE + 1;
+
+ --
+ COMPONENT AND8_gate IS
+ PORT( I0,I1,I2,I3,I4,I5,I6,I7: IN std_logic;
+ O: OUT std_logic );
+ END COMPONENT;
+ --
+ COMPONENT NAND8_gate IS
+ PORT( I0,I1,I2,I3,I4,I5,I6,I7: IN std_logic;
+ O: OUT std_logic );
+ END COMPONENT;
+ --
+ COMPONENT OR8_gate IS
+ PORT( I0,I1,I2,I3,I4,I5,I6,I7: IN std_logic;
+ O: OUT std_logic );
+ END COMPONENT;
+ --
+ COMPONENT NOR8_gate IS
+ PORT( I0,I1,I2,I3,I4,I5,I6,I7: IN std_logic;
+ O: OUT std_logic );
+ END COMPONENT;
+ --
+ COMPONENT Multiplexer_16_1 IS
+ PORT( I0: IN std_logic;
+ I1: IN std_logic;
+ I2: IN std_logic;
+ I3: IN std_logic;
+ I4: IN std_logic;
+ I5: IN std_logic;
+ I6: IN std_logic;
+ I7: IN std_logic;
+ I8: IN std_logic;
+ I9: IN std_logic;
+ I10: IN std_logic;
+ I11: IN std_logic;
+ I12: IN std_logic;
+ I13: IN std_logic;
+ I14: IN std_logic;
+ I15: IN std_logic;
+ S3: IN std_logic;
+ S2: IN std_logic;
+ S1: IN std_logic;
+ S0: IN std_logic;
+ Q: OUT std_logic );
+ END COMPONENT;
+
+ COMPONENT PiPoE8 IS
+ PORT( Ck : IN std_logic;
+ nCL: IN std_logic;
+ E : IN std_logic;
+ P7 : IN std_logic;
+ P6 : IN std_logic;
+ P5 : IN std_logic;
+ P4 : IN std_logic;
+ P3 : IN std_logic;
+ P2 : IN std_logic;
+ P1 : IN std_logic;
+ P0 : IN std_logic;
+ Q7 : OUT std_logic;
+ Q6 : OUT std_logic;
+ Q5 : OUT std_logic;
+ Q4 : OUT std_logic;
+ Q3 : OUT std_logic;
+ Q2 : OUT std_logic;
+ Q1 : OUT std_logic;
+ Q0 : OUT std_logic );
+ END COMPONENT;
+
+SIGNAL S001: std_logic;
+ SIGNAL S002: std_logic;
+ SIGNAL S003: std_logic;
+ SIGNAL S004: std_logic;
+ SIGNAL S005: std_logic;
+ SIGNAL S006: std_logic;
+ SIGNAL S007: std_logic;
+ SIGNAL S008: std_logic;
+ SIGNAL S009: std_logic;
+ SIGNAL S010: std_logic;
+ SIGNAL S011: std_logic;
+ SIGNAL S012: std_logic;
+ SIGNAL S013: std_logic;
+ SIGNAL S014: std_logic;
+ SIGNAL S015: std_logic;
+ SIGNAL S016: std_logic;
+ SIGNAL S017: std_logic;
+ SIGNAL S018: std_logic;
+ SIGNAL S019: std_logic;
+ SIGNAL S020: std_logic;
+ SIGNAL S021: std_logic;
+ SIGNAL S022: std_logic;
+ SIGNAL S023: std_logic;
+ SIGNAL S024: std_logic;
+ SIGNAL S025: std_logic;
+ SIGNAL S026: std_logic;
+ SIGNAL S027: std_logic;
+ SIGNAL S028: std_logic;
+ SIGNAL S029: std_logic;
+ SIGNAL S030: std_logic;
+ SIGNAL S031: std_logic;
+ SIGNAL S032: std_logic;
+ SIGNAL S033: std_logic;
+ SIGNAL S034: std_logic;
+ SIGNAL S035: std_logic;
+ SIGNAL S036: std_logic;
+ SIGNAL S037: std_logic;
+ SIGNAL S038: std_logic;
+ SIGNAL S039: std_logic;
+ SIGNAL S040: std_logic;
+ SIGNAL S041: std_logic;
+ SIGNAL S042: std_logic;
+ SIGNAL S043: std_logic;
+ SIGNAL S044: std_logic;
+ SIGNAL S045: std_logic;
+ SIGNAL S046: std_logic;
+ SIGNAL S047: std_logic;
+ SIGNAL S048: std_logic;
+ SIGNAL S049: std_logic;
+ SIGNAL S050: std_logic;
+ SIGNAL S051: std_logic;
+ SIGNAL S052: std_logic;
+ SIGNAL S053: std_logic;
+ SIGNAL S054: std_logic;
+ SIGNAL S055: std_logic;
+ SIGNAL S056: std_logic;
+ SIGNAL S057: std_logic;
+ SIGNAL S058: std_logic;
+ SIGNAL S059: std_logic;
+ SIGNAL S060: std_logic;
+ SIGNAL S061: std_logic;
+ SIGNAL S062: std_logic;
+ SIGNAL S063: std_logic;
+ SIGNAL S064: std_logic;
+ SIGNAL S065: std_logic;
+ SIGNAL S066: std_logic;
+ SIGNAL S067: std_logic;
+ SIGNAL S068: std_logic;
+ SIGNAL S069: std_logic;
+ SIGNAL S070: std_logic;
+ SIGNAL S071: std_logic;
+ SIGNAL S072: std_logic;
+ SIGNAL S073: std_logic;
+ SIGNAL S074: std_logic;
+ SIGNAL S075: std_logic;
+ SIGNAL S076: std_logic;
+ SIGNAL S077: std_logic;
+ SIGNAL S078: std_logic;
+ SIGNAL S079: std_logic;
+ SIGNAL S080: std_logic;
+ SIGNAL S081: std_logic;
+ SIGNAL S082: std_logic;
+ SIGNAL S083: std_logic;
+ SIGNAL S084: std_logic;
+ SIGNAL S085: std_logic;
+ SIGNAL S086: std_logic;
+ SIGNAL S087: std_logic;
+ SIGNAL S088: std_logic;
+ SIGNAL S089: std_logic;
+ SIGNAL S090: std_logic;
+ SIGNAL S091: std_logic;
+ SIGNAL S092: std_logic;
+ SIGNAL S093: std_logic;
+
+ component FF_JK is
+ generic (delay_and : time := delay_and; delay_nand : time := delay_nand; delay_nand3 : time := delay_nand3; delay_nand4 : time := delay_nand4; delay_not : time := delay_not);
+ port (i_r : in STD_LOGIC; J,K,C : in STD_LOGIC; Q1 : out STD_LOGIC; Q2 : out STD_LOGIC);
+ end component FF_JK;
+ for all : FF_JK use entity WORK.FF_JK(LUT);
+
+ component ripple_counter is
+ generic (N : integer := 32; MAX : integer := 1; delay_and : time := delay_and; delay_nand : time := delay_nand; delay_nand3 : time := delay_nand3; delay_nand4 : time := delay_nand4; delay_not : time := delay_not; delay_or : time := delay_or; delay_mr : time := delay_mr);
+ port (i_clock : in std_logic; i_cpb : in std_logic; i_mrb : in std_logic; i_ud : in std_logic; o_q : inout std_logic_vector(N-1 downto 0));
+ end component ripple_counter;
+ for all : ripple_counter use entity WORK.ripple_counter(Behavioral);
+
+ component GATE_NOT is
+ generic (delay_not : TIME := delay_not);
+ port (A : in STD_LOGIC; B : out STD_LOGIC);
+ end component GATE_NOT;
+-- for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ component GATE_OR is
+ generic (delay_or : TIME := delay_or);
+ port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+ end component GATE_OR;
+-- for all : GATE_OR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+ for all : GATE_OR use entity WORK.GATE_OR(GATE_OR_LUT);
+
+ component GATE_AND is
+ generic (delay_and : TIME := delay_and);
+ port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+ end component GATE_AND;
+-- for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+ for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_LUT);
+
+ component GATE_NAND is
+ generic (delay_nand : TIME := delay_nand);
+ port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+ end component GATE_NAND;
+-- for all : GATE_NAND use entity WORK.GATE_NAND(GATE_NAND_BEHAVIORAL_1);
+ for all : GATE_NAND use entity WORK.GATE_NAND(GATE_NAND_LUT);
+
+ component MUX_21 is
+ generic (delay_and : TIME := delay_and; delay_or : TIME := delay_or; delay_not : TIME := delay_not);
+ port (S,A,B:in STD_LOGIC; C:out STD_LOGIC);
+ end component MUX_21;
+ for all : MUX_21 use entity WORK.MUX_21(MUX_21_LUT_1);
+
+ component MUX_41 is
+ generic (delay_and : TIME := delay_and; delay_or : TIME := delay_or; delay_not : TIME := delay_not);
+ port (S1,S2,A,B,C,D:in STD_LOGIC; E:out STD_LOGIC);
+ end component MUX_41;
+ for all : MUX_41 use entity WORK.MUX_41(Behavioral);
+
+ component MUX_81 is
+ generic (delay_and : TIME := delay_and; delay_or : TIME := delay_or; delay_not : TIME := delay_not);
+ port (in0,in1,in2,in3,in4,in5,in6,in7 : in std_logic; s0,s1,s2 : in std_logic; o : out std_logic);
+ end component MUX_81;
+ for all : MUX_81 use entity WORK.MUX_81(Behavioral);
+
+ signal clock : std_logic;
+ signal clock_chain : std_logic_vector(N-1 downto 0);
+ constant clock_all0_constant : std_logic_vector(N-1 downto 0) := (others => '0');
+ constant clock_all1_constant : std_logic_vector(N-1 downto 0) := (others => '1');
+
+ signal data : std_logic;
+
+ constant sda_condition_count : integer := N;
+ constant sda_condition_bits : integer := 4;
+ signal sda_start : std_logic_vector(sda_condition_bits-1 downto 0);
+ signal sda_stop : std_logic_vector(sda_condition_bits-1 downto 0);
+ signal sda_condition_stop_flag : std_logic;
+ constant sda_condition_stop_constant : std_logic_vector(sda_condition_bits-1 downto 0) := std_logic_vector(to_unsigned(sda_condition_count-1,sda_condition_bits));
+ signal sda_start_counter_stop_flag : std_logic;
+
+ signal reset_or,reset_counter : std_logic;
+ signal sda_start_ldcpe,sda_stop_ldcpe : std_logic;
+ signal ffjkq1,ffjkq2 : std_logic_vector(7 downto 0);
+ signal t1,t2,t3,t4 : std_logic;
+ signal rc_start : std_logic_vector(7 downto 0) := "00000000";
+ signal rc_start_1 : std_logic_vector(7 downto 0);
+-- signal rc_start_mux : std_logic_vector(7 downto 0);
+ signal mux81_rc_start_select : std_logic_vector(2 downto 0) := "000";
+ type ta is array(integer range <>) of std_logic_vector(sda_condition_bits-1 downto 0);
+ signal rc_q : ta(0 to 7);
+ constant RC_MAIN_BITS : integer := 6;
+ signal rc_main : std_logic_vector(RC_MAIN_BITS-1 downto 0);
+ signal tick : std_logic_vector(7 downto 0);
+ signal tick_clock_all0 : std_logic;
+ signal tick_clock_all1 : std_logic;
+ signal a1 : std_logic;
+ signal a2 : std_logic;
+ signal reset_a1 : std_logic;
+ signal omit_first_reset : std_logic;
+ signal mux81_address_slave_select : std_logic_vector (G_SLAVE_ADDRESS_SIZE-1 downto 0);
+ signal mux81_address_slave_out : std_logic;
+ signal mux81_bytes_to_send_select : std_logic_vector (G_BYTE_SIZE-1 downto 0);
+ signal mux81_bytes_to_send_out : std_logic;
+
+ signal mux81_address_slave_select_wait_reset : std_logic_vector (G_SLAVE_ADDRESS_SIZE-1 downto 0);
+ signal rc_as_ldcpe : std_logic;
+
+ signal mux81_bytes_to_send_select_wait_reset : std_logic_vector (G_BYTE_SIZE-1 downto 0);
+ signal rc_b2s_ldcpe : std_logic;
+
+ signal rc_mm : std_logic_vector(8-1 downto 0);
+ signal rc_as_b2s_ldcpe : std_logic;
+
+ signal m81_main_s0 : std_logic;
+ signal m81_main_s1 : std_logic;
+ signal m81_main_s2 : std_logic;
+
+signal flag_start,flag_address,flag_data,flag_ack,flag_stop : std_logic;
+-- rc_mm_start <= '1' when rc_mm = x"00" else '0';
+-- rc_mm_address <= '1' when rc_mm = x"07" else '0';
+-- rc_mm_data <= '1' when rc_mm = x"57" else '0';
+-- rc_mm_ack <= '1' when rc_mm = x"a7" else '0';
+-- rc_mm_stop <= '1' when rc_mm = x"b4" else '0';
+
+ signal rc_mm_start,rc_mm_address,rc_mm_data,rc_mm_ack,rc_mm_stop : std_logic;
+
+ signal start_temp,address_temp,data_temp,ack_temp,stop_temp : std_logic_vector (7 downto 0);
+ signal enable_start,enable_address,enable_data,enable_ack,enable_stop : std_logic;
+
+ signal wait_reset_ldcpe_pre : std_logic;
+
+begin
+
+ p0 : process (i_clock,i_reset) is
+ constant C_W : integer := N-1;
+ variable vw : integer range 0 to C_W;
+ type states is (a,b,c);
+ variable state : states;
+ begin
+ if (i_reset = '1') then
+ state := a;
+ vw := 0;
+ elsif (rising_edge(i_clock)) then
+ case (state) is
+ when a =>
+ rc_start <= "00000001";
+ if (vw = C_W) then
+ state := b;
+ vw := 0;
+ else
+ state := a;
+ vw := vw + 1;
+ end if;
+ when b =>
+ rc_start <= "00000010";
+ if (vw = C_W) then
+ state := c;
+ vw := 0;
+ else
+ state := b;
+ vw := vw + 1;
+ end if;
+ when c =>
+ rc_start <= "00000100";
+ if (vw = C_W) then
+ state := a;
+ vw := 0;
+ else
+ state := c;
+ vw := vw + 1;
+ end if;
+ end case;
+ end if;
+ end process p0;
+
+ start_stop_flag : a1 <= '1' when rc_main = std_logic_vector(to_unsigned(N/2,RC_MAIN_BITS)) else '0';
+ address_data_flag : a2 <= '1' when rc_main = std_logic_vector(to_unsigned(13,RC_MAIN_BITS)) else '0';
+ reset_a1 <= '1' when rc_main = std_logic_vector(to_unsigned(N*2,RC_MAIN_BITS)) else '0';
+ t1 <= i_reset or reset_a1;
+ t2 <= reset_a1 and omit_first_reset;
+ t3 <= a1 and not reset_a1 and omit_first_reset;
+ t4 <= '1' and not reset_or;
+
+ tick_clock_all0 <= '1' when clock_chain = clock_all0_constant else '0';
+ tick_clock_all1 <= '1' when clock_chain = clock_all1_constant else '0';
+ reset_counter <= '1' when rc_q(0) = sda_condition_stop_constant else '0';
+
+ or_reset_conter_inst : GATE_OR
+ port map (
+ A => i_reset,
+ B => reset_counter,
+ C => reset_or);
+
+ generate_mux21_rc_mrb : for i in 0 to 7 generate
+ mux21_rc_mrb : MUX_21
+ port map (
+ S => rc_start(i),
+ A => '1',
+ B => '0',
+ C => rc_start_1(i));
+ end generate generate_mux21_rc_mrb;
+
+ ripple_counter_main : ripple_counter
+ generic map (N => RC_MAIN_BITS,MAX => N*2)
+ port map (
+ i_clock => i_clock,
+ i_cpb => '1',
+ i_mrb => t1,
+ i_ud => '1',
+ o_q => rc_main);
+
+ sda_start_ldcpe_inst : LDCPE generic map (INIT => '1')
+ port map (
+ Q => sda_start_ldcpe,
+ D => '0',
+ CLR => '0',
+ G => a1,
+ GE => a1,
+ PRE => '0');
+
+ sda_stop_ldcpe_inst_prev : LDCPE generic map (INIT => '0')
+ port map (
+ Q => omit_first_reset,
+ D => '1',
+ CLR => a1,
+ G => a1,
+ GE => a1,
+ PRE => reset_a1);
+
+ sda_stop_ldcpe_inst : LDCPE generic map (INIT => '0')
+ port map (
+ Q => sda_stop_ldcpe,
+ D => t2,
+ CLR => '0',
+ G => a1,
+ GE => not a1,
+ PRE => t3);
+
+ sda_start_counter : ripple_counter
+ generic map (N => sda_condition_bits,MAX => 2**sda_condition_bits-1)
+ port map (
+ i_clock => i_clock,
+ i_cpb => not tick_clock_all0,
+ i_mrb => rc_start_1(0),
+ i_ud => '1',
+ o_q => rc_q(0));
+
+ sda_stop_counter : ripple_counter
+ generic map (N => sda_condition_bits,MAX => 2**sda_condition_bits-1)
+ port map (
+ i_clock => i_clock,
+ i_cpb => t4,
+ i_mrb => rc_start_1(1),
+ i_ud => '1',
+ o_q => rc_q(1));
+
+ rc0 : ripple_counter
+ generic map (N => sda_condition_bits,MAX => 2**sda_condition_bits-1)
+ port map (
+ i_clock => i_clock,
+ i_cpb => '1',
+ i_mrb => rc_start_1(2),
+ i_ud => '1',
+ o_q => rc_q(2));
+
+ g1 : for i in 0 to 7 generate
+ tick(i) <= '1' when rc_q(i) = sda_condition_stop_constant else '0';
+ end generate g1;
+
+ g0 : for i in 0 to 7 generate
+ ffjk : FF_JK
+ port map (
+ i_r => i_reset,
+ J => '1',
+ K => '1',
+ C => tick(i),
+ Q1 => ffjkq1(i),
+ Q2 => ffjkq2(i));
+ end generate g0;
+
+ generate_clock_chain : for i in 0 to N-1 generate
+ clock_chain_first : if (i=0) generate
+ clock_chain_f : LDCPE
+ port map (
+ Q => clock_chain(i),
+ D => clock,
+ CLR => i_reset,
+ G => i_clock,
+ GE => not i_clock,
+ PRE => '0');
+ end generate clock_chain_first;
+ clock_chain_rest : if (i>0) generate
+ clock_chain_r : LDCPE
+ port map (
+ Q => clock_chain(i),
+ D => clock_chain(i-1),
+ CLR => '0',
+ G => i_clock,
+ GE => not i_clock,
+ PRE => '0');
+ end generate clock_chain_rest;
+ end generate generate_clock_chain;
+
+ mux21_clock_chain_tick : MUXCY
+ port map (
+ O => clock,
+ CI => '0',
+ DI => '1',
+ S => clock_chain(N-1));
+
+ OBUFT_scl_clock_inst : OBUFT -- output clock line, works
+ port map (
+ O => o_scl,
+ I => clock,
+ T => clock);
+
+ OBUFT_sda_data_inst : OBUFT -- output sda line
+ port map (
+ O => o_sda,
+ I => data,
+ T => data);
+
+ mux21_sda_start_counter_stop : MUX_21
+ port map (
+ S => reset_or,
+ A => '1',
+ B => '0',
+ C => sda_start_counter_stop_flag);
+
+ rc_address_slave_bytes_to_send_wait_reset : ripple_counter
+ generic map (N => 8,MAX => 2**8-1)
+ port map (
+ i_clock => rc_main(0),
+ i_cpb => '1',
+ i_mrb => i_reset,
+ i_ud => '1',
+ o_q => rc_mm);
+
+ wait_reset_ldcpe_pre <= not rc_mm(0) and
+ not rc_mm(1) and
+ not rc_mm(2) and
+ not rc_mm(3) and
+ rc_mm(4) and
+ not rc_mm(5) and
+ not rc_mm(6) and
+ not rc_mm(7);
+
+ rc_address_slave_bytes_to_send_wait_reset_ldcpe : LDCPE generic map (INIT => '0')
+ port map (
+ Q => rc_as_b2s_ldcpe,
+ D => '1',
+ CLR => '0',
+ G => '0',
+ GE => '0',
+ PRE => wait_reset_ldcpe_pre);
+
+ ripple_counter_mux81_address_slave : ripple_counter
+ generic map (N => G_SLAVE_ADDRESS_SIZE,MAX => 2**G_SLAVE_ADDRESS_SIZE-1)
+ port map (
+ i_clock => a2,
+ i_cpb => '1',
+ i_mrb => not rc_as_b2s_ldcpe,
+ i_ud => '1',
+ o_q => mux81_address_slave_select);
+
+ ripple_counter_mux81_bytes_to_send : ripple_counter
+ generic map (N => G_BYTE_SIZE,MAX => 2**G_BYTE_SIZE-1)
+ port map (
+ i_clock => a2,
+ i_cpb => '1',
+ i_mrb => not rc_as_b2s_ldcpe,
+ i_ud => '1',
+ o_q => mux81_bytes_to_send_select);
+
+ mux81_address_slave : MUX_81
+ port map (
+ S0 => mux81_address_slave_select(0),
+ S1 => mux81_address_slave_select(1),
+ S2 => mux81_address_slave_select(2),
+ in0 => i_slave_address(0),
+ in1 => i_slave_address(1),
+ in2 => i_slave_address(2),
+ in3 => i_slave_address(3),
+ in4 => i_slave_address(4),
+ in5 => i_slave_address(5),
+ in6 => i_slave_address(6),
+ in7 => i_slave_rw,
+ o => mux81_address_slave_out);
+
+ mux81_bytes_to_send : MUX_81
+ port map (
+ S0 => mux81_bytes_to_send_select(0),
+ S1 => mux81_bytes_to_send_select(1),
+ S2 => mux81_bytes_to_send_select(2),
+ in0 => i_bytes_to_send(0),
+ in1 => i_bytes_to_send(1),
+ in2 => i_bytes_to_send(2),
+ in3 => i_bytes_to_send(3),
+ in4 => i_bytes_to_send(4),
+ in5 => i_bytes_to_send(5),
+ in6 => i_bytes_to_send(6),
+ in7 => i_bytes_to_send(7),
+ o => mux81_bytes_to_send_out);
+
+
+ C262_start: PiPoE8 PORT MAP ( i_clock, not i_reset, enable_start,
+ rc_mm(7), rc_mm(6), rc_mm(5), rc_mm(4), rc_mm(3), rc_mm(2), rc_mm(1), rc_mm(0),
+ start_temp(7), start_temp(6), start_temp(5), start_temp(4), start_temp(3), start_temp(2), start_temp(1), start_temp(0) );
+ C2379: NOR8_gate PORT MAP (
+ rc_mm(0), rc_mm(1), rc_mm(2), rc_mm(3), rc_mm(4), rc_mm(5), rc_mm(6), rc_mm(7), enable_start);
+ C2380: NAND8_gate PORT MAP (
+ start_temp(7), start_temp(6), start_temp(5), start_temp(4), start_temp(3), start_temp(2), start_temp(1), start_temp(0), flag_start );
+
+ C268_address: PiPoE8 PORT MAP ( i_clock, not i_reset, enable_address,
+ rc_mm(7), rc_mm(6), rc_mm(5), rc_mm(4), rc_mm(3), rc_mm(2), rc_mm(1), rc_mm(0),
+ address_temp(7), address_temp(6), address_temp(5), address_temp(4), address_temp(3), address_temp(2), address_temp(1), address_temp(0) );
+ C887: AND8_gate PORT MAP (
+ rc_mm(0), rc_mm(1), rc_mm(2), not rc_mm(3), not rc_mm(4), not rc_mm(5), not rc_mm(6), not rc_mm(7), enable_address );
+ C1163: OR8_gate PORT MAP (
+ address_temp(0), address_temp(1), address_temp(2), address_temp(3), address_temp(4), address_temp(5), address_temp(6), address_temp(7), flag_address);
+
+ C893_data: PiPoE8 PORT MAP ( i_clock, not i_reset, enable_data,
+ rc_mm(7), rc_mm(6), rc_mm(5), rc_mm(4), rc_mm(3), rc_mm(2), rc_mm(1), rc_mm(0),
+ data_temp(7), data_temp(6), data_temp(5), data_temp(4), data_temp(3), data_temp(2), data_temp(1), data_temp(0) );
+ C614: AND8_gate PORT MAP (
+ rc_mm(0), rc_mm(1), rc_mm(2), not rc_mm(3), rc_mm(4), not rc_mm(5), rc_mm(6), not rc_mm(7), enable_data );
+ C1182: OR8_gate PORT MAP (
+ data_temp(0), data_temp(1), data_temp(2), data_temp(3), data_temp(4), data_temp(5), data_temp(6), data_temp(7), flag_data );
+
+ C1310_ack: PiPoE8 PORT MAP ( i_clock, not i_reset, enable_ack,
+ rc_mm(7), rc_mm(6), rc_mm(5), rc_mm(4), rc_mm(3), rc_mm(2), rc_mm(1), rc_mm(0),
+ ack_temp(7), ack_temp(6), ack_temp(5), ack_temp(4), ack_temp(3), ack_temp(2), ack_temp(1), ack_temp(0) );
+ C548: AND8_gate PORT MAP (
+ rc_mm(0), rc_mm(1), rc_mm(2), not rc_mm(3), not rc_mm(4), rc_mm(5), not rc_mm(6), rc_mm(7), enable_ack);
+ C1198: OR8_gate PORT MAP (
+ ack_temp(0), ack_temp(1), ack_temp(2), ack_temp(3), ack_temp(4), ack_temp(5), ack_temp(6), ack_temp(7), flag_ack );
+
+ C1628_stop: PiPoE8 PORT MAP ( i_clock, not i_reset, enable_stop,
+ rc_mm(7), rc_mm(6), rc_mm(5), rc_mm(4), rc_mm(3), rc_mm(2), rc_mm(1), rc_mm(0),
+ stop_temp(7), stop_temp(6), stop_temp(5), stop_temp(4), stop_temp(3), stop_temp(2), stop_temp(1), stop_temp(0) );
+ C1629: OR8_gate PORT MAP (
+ not rc_mm(0), not rc_mm(1), rc_mm(2), not rc_mm(3), rc_mm(4), rc_mm(5), not rc_mm(6), rc_mm(7), enable_stop );
+ C1741: AND8_gate PORT MAP (
+ stop_temp(0), stop_temp(1), stop_temp(2), stop_temp(3), stop_temp(4), stop_temp(5), stop_temp(6), stop_temp(7), flag_stop );
+
+-- m81_main_inst : MUX_81 -- main multiplexing
+-- port map (
+-- S0 => m81_main_s0,
+-- S1 => m81_main_s1,
+-- S2 => m81_main_s2,
+-- in0 => sda_start_ldcpe, -- start condition
+-- in1 => mux81_address_slave_out, -- address 7b
+-- in2 => mux81_bytes_to_send_out, -- data 8b
+-- in3 => '1', -- wait for ack/nack - Z on sda
+-- in4 => sda_stop_ldcpe, -- stop condition
+-- in5 => '0', -- not used
+-- in6 => '0', -- not used
+-- in7 => '0', -- not used
+-- o => data); -- out to OBUFT_sda_data_inst
+
+ C2497: Multiplexer_16_1 PORT MAP (
+ sda_start_ldcpe,
+ mux81_address_slave_out,
+ '0',
+ mux81_bytes_to_send_out,
+ '0',
+ '0',
+ '0',
+ '1', -- acl
+ '0',
+ '0',
+ '0',
+ '0',
+ '0',
+ '0',
+ '0',
+ sda_stop_ldcpe,
+ flag_stop,
+ flag_ack,
+ flag_data,
+ flag_address,
+ data );
+
+end architecture Behavioral;
+
+------------------------------------------------------------
+-- Deeds (Digital Electronics Education and Design Suite)
+-- VHDL Code generated on (20.03.2024, 17:15:41)
+-- by Deeds (Digital Circuit Simulator)(Deeds-DcS)
+-- Ver. 2.50.200 (Feb 18, 2022)
+-- Copyright (c) 2002-2022 University of Genoa, Italy
+-- Web Site: https://www.digitalelectronicsdeeds.com
+------------------------------------------------------------
+
+--------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+ENTITY AND8_gate IS
+ PORT( I0,I1,I2,I3,I4,I5,I6,I7: IN std_logic;
+ O: OUT std_logic );
+END AND8_gate;
+
+--------------------------------------------------------------------
+ARCHITECTURE behavioral OF AND8_gate IS
+BEGIN
+ O <= (I0 and I1 and I2 and I3 and I4 and I5 and I6 and I7);
+END behavioral;
+
+
+--------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+ENTITY NAND8_gate IS
+ PORT( I0,I1,I2,I3,I4,I5,I6,I7: IN std_logic;
+ O: OUT std_logic );
+END NAND8_gate;
+
+--------------------------------------------------------------------
+ARCHITECTURE behavioral OF NAND8_gate IS
+BEGIN
+ O <= (not (I0 and I1 and I2 and I3 and I4 and I5 and I6 and I7));
+END behavioral;
+
+
+--------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+ENTITY OR8_gate IS
+ PORT( I0,I1,I2,I3,I4,I5,I6,I7: IN std_logic;
+ O: OUT std_logic );
+END OR8_gate;
+
+--------------------------------------------------------------------
+ARCHITECTURE behavioral OF OR8_gate IS
+BEGIN
+ O <= (I0 or I1 or I2 or I3 or I4 or I5 or I6 or I7);
+END behavioral;
+
+
+--------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+ENTITY NOR8_gate IS
+ PORT( I0,I1,I2,I3,I4,I5,I6,I7: IN std_logic;
+ O: OUT std_logic );
+END NOR8_gate;
+
+--------------------------------------------------------------------
+ARCHITECTURE behavioral OF NOR8_gate IS
+BEGIN
+ O <= (not (I0 or I1 or I2 or I3 or I4 or I5 or I6 or I7));
+END behavioral;
+
+
+--------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+ENTITY Multiplexer_16_1 IS
+
+ PORT( I0: IN std_logic;
+ I1: IN std_logic;
+ I2: IN std_logic;
+ I3: IN std_logic;
+ I4: IN std_logic;
+ I5: IN std_logic;
+ I6: IN std_logic;
+ I7: IN std_logic;
+ I8: IN std_logic;
+ I9: IN std_logic;
+ I10: IN std_logic;
+ I11: IN std_logic;
+ I12: IN std_logic;
+ I13: IN std_logic;
+ I14: IN std_logic;
+ I15: IN std_logic;
+ S3: IN std_logic;
+ S2: IN std_logic;
+ S1: IN std_logic;
+ S0: IN std_logic;
+ Q: OUT std_logic );
+END Multiplexer_16_1;
+
+--------------------------------------------------------------------
+ARCHITECTURE behavioral OF Multiplexer_16_1 IS
+BEGIN
+ Q <= I0 when ((S3 = '0') and (S2 = '0') and (S1 = '0') and (S0 = '0')) else
+ I1 when ((S3 = '0') and (S2 = '0') and (S1 = '0') and (S0 = '1')) else
+ I2 when ((S3 = '0') and (S2 = '0') and (S1 = '1') and (S0 = '0')) else
+ I3 when ((S3 = '0') and (S2 = '0') and (S1 = '1') and (S0 = '1')) else
+ I4 when ((S3 = '0') and (S2 = '1') and (S1 = '0') and (S0 = '0')) else
+ I5 when ((S3 = '0') and (S2 = '1') and (S1 = '0') and (S0 = '1')) else
+ I6 when ((S3 = '0') and (S2 = '1') and (S1 = '1') and (S0 = '0')) else
+ I7 when ((S3 = '0') and (S2 = '1') and (S1 = '1') and (S0 = '1')) else
+ I8 when ((S3 = '1') and (S2 = '0') and (S1 = '0') and (S0 = '0')) else
+ I9 when ((S3 = '1') and (S2 = '0') and (S1 = '0') and (S0 = '1')) else
+ I10 when ((S3 = '1') and (S2 = '0') and (S1 = '1') and (S0 = '0')) else
+ I11 when ((S3 = '1') and (S2 = '0') and (S1 = '1') and (S0 = '1')) else
+ I12 when ((S3 = '1') and (S2 = '1') and (S1 = '0') and (S0 = '0')) else
+ I13 when ((S3 = '1') and (S2 = '1') and (S1 = '0') and (S0 = '1')) else
+ I14 when ((S3 = '1') and (S2 = '1') and (S1 = '1') and (S0 = '0')) else
+ I15 when ((S3 = '1') and (S2 = '1') and (S1 = '1') and (S0 = '1')) else 'X';
+END behavioral;
+
+--------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+ENTITY Decoder_4_16 IS
+
+ PORT( A3: IN std_logic;
+ A2: IN std_logic;
+ A1: IN std_logic;
+ A0: IN std_logic;
+ EN: IN std_logic;
+ Y0 : OUT std_logic;
+ Y1 : OUT std_logic;
+ Y2 : OUT std_logic;
+ Y3 : OUT std_logic;
+ Y4 : OUT std_logic;
+ Y5 : OUT std_logic;
+ Y6 : OUT std_logic;
+ Y7 : OUT std_logic;
+ Y8 : OUT std_logic;
+ Y9 : OUT std_logic;
+ Y10: OUT std_logic;
+ Y11: OUT std_logic;
+ Y12: OUT std_logic;
+ Y13: OUT std_logic;
+ Y14: OUT std_logic;
+ Y15: OUT std_logic );
+END Decoder_4_16;
+
+--------------------------------------------------------------------
+ARCHITECTURE behavioral OF Decoder_4_16 IS
+ SIGNAL aNumber: std_logic_vector( 4 downto 0 );
+BEGIN
+ aNumber <= EN & A3 & A2 & A1 & A0;
+ with aNumber select
+ Y0 <= '0' when "00000", '0' when "00001", '0' when "00010", '0' when "00011",
+ '0' when "00100", '0' when "00101", '0' when "00110", '0' when "00111",
+ '0' when "01000", '0' when "01001", '0' when "01010", '0' when "01011",
+ '0' when "01100", '0' when "01101", '0' when "01110", '0' when "01111",
+ '1' when "10000", '0' when "10001", '0' when "10010", '0' when "10011",
+ '0' when "10100", '0' when "10101", '0' when "10110", '0' when "10111",
+ '0' when "11000", '0' when "11001", '0' when "11010", '0' when "11011",
+ '0' when "11100", '0' when "11101", '0' when "11110", '0' when "11111",
+ 'X' when others;
+ with aNumber select
+ Y1 <= '0' when "00000", '0' when "00001", '0' when "00010", '0' when "00011",
+ '0' when "00100", '0' when "00101", '0' when "00110", '0' when "00111",
+ '0' when "01000", '0' when "01001", '0' when "01010", '0' when "01011",
+ '0' when "01100", '0' when "01101", '0' when "01110", '0' when "01111",
+ '0' when "10000", '1' when "10001", '0' when "10010", '0' when "10011",
+ '0' when "10100", '0' when "10101", '0' when "10110", '0' when "10111",
+ '0' when "11000", '0' when "11001", '0' when "11010", '0' when "11011",
+ '0' when "11100", '0' when "11101", '0' when "11110", '0' when "11111",
+ 'X' when others;
+ with aNumber select
+ Y2 <= '0' when "00000", '0' when "00001", '0' when "00010", '0' when "00011",
+ '0' when "00100", '0' when "00101", '0' when "00110", '0' when "00111",
+ '0' when "01000", '0' when "01001", '0' when "01010", '0' when "01011",
+ '0' when "01100", '0' when "01101", '0' when "01110", '0' when "01111",
+ '0' when "10000", '0' when "10001", '1' when "10010", '0' when "10011",
+ '0' when "10100", '0' when "10101", '0' when "10110", '0' when "10111",
+ '0' when "11000", '0' when "11001", '0' when "11010", '0' when "11011",
+ '0' when "11100", '0' when "11101", '0' when "11110", '0' when "11111",
+ 'X' when others;
+ with aNumber select
+ Y3 <= '0' when "00000", '0' when "00001", '0' when "00010", '0' when "00011",
+ '0' when "00100", '0' when "00101", '0' when "00110", '0' when "00111",
+ '0' when "01000", '0' when "01001", '0' when "01010", '0' when "01011",
+ '0' when "01100", '0' when "01101", '0' when "01110", '0' when "01111",
+ '0' when "10000", '0' when "10001", '0' when "10010", '1' when "10011",
+ '0' when "10100", '0' when "10101", '0' when "10110", '0' when "10111",
+ '0' when "11000", '0' when "11001", '0' when "11010", '0' when "11011",
+ '0' when "11100", '0' when "11101", '0' when "11110", '0' when "11111",
+ 'X' when others;
+ with aNumber select
+ Y4 <= '0' when "00000", '0' when "00001", '0' when "00010", '0' when "00011",
+ '0' when "00100", '0' when "00101", '0' when "00110", '0' when "00111",
+ '0' when "01000", '0' when "01001", '0' when "01010", '0' when "01011",
+ '0' when "01100", '0' when "01101", '0' when "01110", '0' when "01111",
+ '0' when "10000", '0' when "10001", '0' when "10010", '0' when "10011",
+ '1' when "10100", '0' when "10101", '0' when "10110", '0' when "10111",
+ '0' when "11000", '0' when "11001", '0' when "11010", '0' when "11011",
+ '0' when "11100", '0' when "11101", '0' when "11110", '0' when "11111",
+ 'X' when others;
+ with aNumber select
+ Y5 <= '0' when "00000", '0' when "00001", '0' when "00010", '0' when "00011",
+ '0' when "00100", '0' when "00101", '0' when "00110", '0' when "00111",
+ '0' when "01000", '0' when "01001", '0' when "01010", '0' when "01011",
+ '0' when "01100", '0' when "01101", '0' when "01110", '0' when "01111",
+ '0' when "10000", '0' when "10001", '0' when "10010", '0' when "10011",
+ '0' when "10100", '1' when "10101", '0' when "10110", '0' when "10111",
+ '0' when "11000", '0' when "11001", '0' when "11010", '0' when "11011",
+ '0' when "11100", '0' when "11101", '0' when "11110", '0' when "11111",
+ 'X' when others;
+ with aNumber select
+ Y6 <= '0' when "00000", '0' when "00001", '0' when "00010", '0' when "00011",
+ '0' when "00100", '0' when "00101", '0' when "00110", '0' when "00111",
+ '0' when "01000", '0' when "01001", '0' when "01010", '0' when "01011",
+ '0' when "01100", '0' when "01101", '0' when "01110", '0' when "01111",
+ '0' when "10000", '0' when "10001", '0' when "10010", '0' when "10011",
+ '0' when "10100", '0' when "10101", '1' when "10110", '0' when "10111",
+ '0' when "11000", '0' when "11001", '0' when "11010", '0' when "11011",
+ '0' when "11100", '0' when "11101", '0' when "11110", '0' when "11111",
+ 'X' when others;
+ with aNumber select
+ Y7 <= '0' when "00000", '0' when "00001", '0' when "00010", '0' when "00011",
+ '0' when "00100", '0' when "00101", '0' when "00110", '0' when "00111",
+ '0' when "01000", '0' when "01001", '0' when "01010", '0' when "01011",
+ '0' when "01100", '0' when "01101", '0' when "01110", '0' when "01111",
+ '0' when "10000", '0' when "10001", '0' when "10010", '0' when "10011",
+ '0' when "10100", '0' when "10101", '0' when "10110", '1' when "10111",
+ '0' when "11000", '0' when "11001", '0' when "11010", '0' when "11011",
+ '0' when "11100", '0' when "11101", '0' when "11110", '0' when "11111",
+ 'X' when others;
+ with aNumber select
+ Y8 <= '0' when "00000", '0' when "00001", '0' when "00010", '0' when "00011",
+ '0' when "00100", '0' when "00101", '0' when "00110", '0' when "00111",
+ '0' when "01000", '0' when "01001", '0' when "01010", '0' when "01011",
+ '0' when "01100", '0' when "01101", '0' when "01110", '0' when "01111",
+ '0' when "10000", '0' when "10001", '0' when "10010", '0' when "10011",
+ '0' when "10100", '0' when "10101", '0' when "10110", '0' when "10111",
+ '1' when "11000", '0' when "11001", '0' when "11010", '0' when "11011",
+ '0' when "11100", '0' when "11101", '0' when "11110", '0' when "11111",
+ 'X' when others;
+ with aNumber select
+ Y9 <= '0' when "00000", '0' when "00001", '0' when "00010", '0' when "00011",
+ '0' when "00100", '0' when "00101", '0' when "00110", '0' when "00111",
+ '0' when "01000", '0' when "01001", '0' when "01010", '0' when "01011",
+ '0' when "01100", '0' when "01101", '0' when "01110", '0' when "01111",
+ '0' when "10000", '0' when "10001", '0' when "10010", '0' when "10011",
+ '0' when "10100", '0' when "10101", '0' when "10110", '0' when "10111",
+ '0' when "11000", '1' when "11001", '0' when "11010", '0' when "11011",
+ '0' when "11100", '0' when "11101", '0' when "11110", '0' when "11111",
+ 'X' when others;
+ with aNumber select
+ Y10<= '0' when "00000", '0' when "00001", '0' when "00010", '0' when "00011",
+ '0' when "00100", '0' when "00101", '0' when "00110", '0' when "00111",
+ '0' when "01000", '0' when "01001", '0' when "01010", '0' when "01011",
+ '0' when "01100", '0' when "01101", '0' when "01110", '0' when "01111",
+ '0' when "10000", '0' when "10001", '0' when "10010", '0' when "10011",
+ '0' when "10100", '0' when "10101", '0' when "10110", '0' when "10111",
+ '0' when "11000", '0' when "11001", '1' when "11010", '0' when "11011",
+ '0' when "11100", '0' when "11101", '0' when "11110", '0' when "11111",
+ 'X' when others;
+ with aNumber select
+ Y11<= '0' when "00000", '0' when "00001", '0' when "00010", '0' when "00011",
+ '0' when "00100", '0' when "00101", '0' when "00110", '0' when "00111",
+ '0' when "01000", '0' when "01001", '0' when "01010", '0' when "01011",
+ '0' when "01100", '0' when "01101", '0' when "01110", '0' when "01111",
+ '0' when "10000", '0' when "10001", '0' when "10010", '0' when "10011",
+ '0' when "10100", '0' when "10101", '0' when "10110", '0' when "10111",
+ '0' when "11000", '0' when "11001", '0' when "11010", '1' when "11011",
+ '0' when "11100", '0' when "11101", '0' when "11110", '0' when "11111",
+ 'X' when others;
+ with aNumber select
+ Y12<= '0' when "00000", '0' when "00001", '0' when "00010", '0' when "00011",
+ '0' when "00100", '0' when "00101", '0' when "00110", '0' when "00111",
+ '0' when "01000", '0' when "01001", '0' when "01010", '0' when "01011",
+ '0' when "01100", '0' when "01101", '0' when "01110", '0' when "01111",
+ '0' when "10000", '0' when "10001", '0' when "10010", '0' when "10011",
+ '0' when "10100", '0' when "10101", '0' when "10110", '0' when "10111",
+ '0' when "11000", '0' when "11001", '0' when "11010", '0' when "11011",
+ '1' when "11100", '0' when "11101", '0' when "11110", '0' when "11111",
+ 'X' when others;
+ with aNumber select
+ Y13<= '0' when "00000", '0' when "00001", '0' when "00010", '0' when "00011",
+ '0' when "00100", '0' when "00101", '0' when "00110", '0' when "00111",
+ '0' when "01000", '0' when "01001", '0' when "01010", '0' when "01011",
+ '0' when "01100", '0' when "01101", '0' when "01110", '0' when "01111",
+ '0' when "10000", '0' when "10001", '0' when "10010", '0' when "10011",
+ '0' when "10100", '0' when "10101", '0' when "10110", '0' when "10111",
+ '0' when "11000", '0' when "11001", '0' when "11010", '0' when "11011",
+ '0' when "11100", '1' when "11101", '0' when "11110", '0' when "11111",
+ 'X' when others;
+ with aNumber select
+ Y14<= '0' when "00000", '0' when "00001", '0' when "00010", '0' when "00011",
+ '0' when "00100", '0' when "00101", '0' when "00110", '0' when "00111",
+ '0' when "01000", '0' when "01001", '0' when "01010", '0' when "01011",
+ '0' when "01100", '0' when "01101", '0' when "01110", '0' when "01111",
+ '0' when "10000", '0' when "10001", '0' when "10010", '0' when "10011",
+ '0' when "10100", '0' when "10101", '0' when "10110", '0' when "10111",
+ '0' when "11000", '0' when "11001", '0' when "11010", '0' when "11011",
+ '0' when "11100", '0' when "11101", '1' when "11110", '0' when "11111",
+ 'X' when others;
+ with aNumber select
+ Y15<= '0' when "00000", '0' when "00001", '0' when "00010", '0' when "00011",
+ '0' when "00100", '0' when "00101", '0' when "00110", '0' when "00111",
+ '0' when "01000", '0' when "01001", '0' when "01010", '0' when "01011",
+ '0' when "01100", '0' when "01101", '0' when "01110", '0' when "01111",
+ '0' when "10000", '0' when "10001", '0' when "10010", '0' when "10011",
+ '0' when "10100", '0' when "10101", '0' when "10110", '0' when "10111",
+ '0' when "11000", '0' when "11001", '0' when "11010", '0' when "11011",
+ '0' when "11100", '0' when "11101", '0' when "11110", '1' when "11111",
+ 'X' when others;
+END behavioral;
+
+--------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY CounterUDE8 IS
+ PORT( Ck : IN std_logic;
+ nCL: IN std_logic;
+ ENP: IN std_logic;
+ UD : IN std_logic;
+ Q7 : OUT std_logic;
+ Q6 : OUT std_logic;
+ Q5 : OUT std_logic;
+ Q4 : OUT std_logic;
+ Q3 : OUT std_logic;
+ Q2 : OUT std_logic;
+ Q1 : OUT std_logic;
+ Q0 : OUT std_logic;
+ Tc : OUT std_logic );
+END CounterUDE8;
+
+--------------------------------------------------------------------
+ARCHITECTURE behavioral OF CounterUDE8 IS
+BEGIN
+ CountUDE8: PROCESS( Ck, nCL, ENP, UD )
+ variable aCnt: unsigned( 7 downto 0 );
+ BEGIN
+ if (nCL = '0') then aCnt := (others =>'0');
+ elsif (nCL = '1') then
+ if (Ck'event) AND (Ck='1') then
+ if (ENP = '1') then
+ if (UD = '1') then
+ if (aCnt < "11111111") then aCnt := aCnt + 1;
+ else aCnt := (others =>'0');
+ end if;
+ elsif (UD = '0') then
+ if (aCnt > "00000000") then aCnt := aCnt - 1;
+ else aCnt := (others =>'1');
+ end if;
+ else aCnt := (others =>'X'); -- (UD: Unknown)
+ END IF;
+ elsif not(ENP ='0') then aCnt := (others =>'X'); -- (ENP: Unknown)
+ END IF;
+ END IF;
+ else aCnt := (others =>'X'); -- (nCL: Unknown)
+ END IF;
+ --
+ Tc <= (aCnt(7) and aCnt(6) and aCnt(5) and aCnt(4) and aCnt(3) and aCnt(2) and aCnt(1) and aCnt(0) and UD) or
+ (not(aCnt(7) or aCnt(6) or aCnt(5) or aCnt(4) or aCnt(3) or aCnt(2) or aCnt(1) or aCnt(0) or UD));
+ --
+ Q7 <= aCnt(7);
+ Q6 <= aCnt(6);
+ Q5 <= aCnt(5);
+ Q4 <= aCnt(4);
+ Q3 <= aCnt(3);
+ Q2 <= aCnt(2);
+ Q1 <= aCnt(1);
+ Q0 <= aCnt(0);
+ --
+ END PROCESS;
+END behavioral;
+
+--------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+ENTITY PiPoE8 IS
+ PORT( Ck : IN std_logic;
+ nCL: IN std_logic;
+ E : IN std_logic;
+ P7 : IN std_logic;
+ P6 : IN std_logic;
+ P5 : IN std_logic;
+ P4 : IN std_logic;
+ P3 : IN std_logic;
+ P2 : IN std_logic;
+ P1 : IN std_logic;
+ P0 : IN std_logic;
+ Q7 : OUT std_logic;
+ Q6 : OUT std_logic;
+ Q5 : OUT std_logic;
+ Q4 : OUT std_logic;
+ Q3 : OUT std_logic;
+ Q2 : OUT std_logic;
+ Q1 : OUT std_logic;
+ Q0 : OUT std_logic );
+END PiPoE8;
+
+
+--------------------------------------------------------------------
+ARCHITECTURE behavioral OF PiPoE8 IS
+BEGIN
+ RegPiPoE8: PROCESS( Ck, nCL )
+ variable aReg: std_logic_vector( 7 downto 0 );
+ BEGIN
+ if (nCL = '0') then aReg := (others =>'0');
+ elsif (nCL = '1') then
+ if (Ck'event) AND (Ck='1') THEN -- Positive Edge -----------
+ if (E = '1') then
+ aReg := (P7 & P6 & P5 & P4 & P3 & P2 & P1 & P0);
+ elsif not(E = '0') then
+ aReg := (others =>'X');
+ END IF;
+ END IF;
+ else aReg := (others =>'X');
+ END IF;
+
+ Q7 <= aReg(7);
+ Q6 <= aReg(6);
+ Q5 <= aReg(5);
+ Q4 <= aReg(4);
+ Q3 <= aReg(3);
+ Q2 <= aReg(2);
+ Q1 <= aReg(1);
+ Q0 <= aReg(0);
+
+ END PROCESS;
+END behavioral;
diff --git a/myown_i2c/myown_i2c.xise b/myown_i2c/myown_i2c.xise
new file mode 100755
index 0000000..5ea3eeb
--- /dev/null
+++ b/myown_i2c/myown_i2c.xise
@@ -0,0 +1,537 @@
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diff --git a/myown_i2c/p_constants1.vhd b/myown_i2c/p_constants1.vhd
new file mode 100755
index 0000000..3a4bce9
--- /dev/null
+++ b/myown_i2c/p_constants1.vhd
@@ -0,0 +1,20 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package p_constants1 is
+ constant G_BOARD_CLOCK : INTEGER := 50_000_000;
+ constant G_BUS_CLOCK : INTEGER := 400_000;
+ constant G_BYTE_SIZE : integer := 8;
+ constant G_SLAVE_ADDRESS_SIZE : integer := 7;
+
+-- i2c oled 128x32 initialization sequence
+ constant BYTES_SEQUENCE_LENGTH : natural := 27;
+ type ARRAY_BYTE_SEQUENCE is array(0 to BYTES_SEQUENCE_LENGTH-1) of std_logic_vector(0 to G_BYTE_SIZE-1);
+ constant sequence : ARRAY_BYTE_SEQUENCE :=
+ (x"00",x"AE",x"D5",x"80",x"A8",x"1F",x"D3",x"00",x"40",x"8D",x"14",x"20",x"00",x"A1",x"C8",x"DA",x"02",x"81",x"8F",x"D9",x"F1",x"DB",x"40",x"A4",x"A6",x"2E",x"AF");
+
+ type array1 is array(natural range <>) of std_logic_vector(7 downto 0);
+end p_constants1;
+
+package body p_constants1 is
+end p_constants1;
diff --git a/myown_i2c/power_on.vhd b/myown_i2c/power_on.vhd
new file mode 100755
index 0000000..82ec884
--- /dev/null
+++ b/myown_i2c/power_on.vhd
@@ -0,0 +1,146 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:47:31 08/21/2020
+-- Design Name:
+-- Module Name: power_on - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_constants1.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+use ieee.std_logic_unsigned.all;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity power_on is
+port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ o_sda : out std_logic;
+ o_scl : out std_logic
+);
+end power_on;
+
+architecture Behavioral of power_on is
+
+ component my_i2c_pc is
+ port(
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_slave_address : in std_logic_vector(0 to G_SLAVE_ADDRESS_SIZE-1);
+ i_slave_rw : in std_logic;
+ i_bytes_to_send : in std_logic_vector(0 to G_BYTE_SIZE-1);
+ i_enable : in std_logic;
+ o_busy : out std_logic;
+ o_sda : out std_logic;
+ o_scl : out std_logic
+ );
+ end component my_i2c_pc;
+ for all : my_i2c_pc use entity WORK.my_i2c_pc(Behavioral);
+
+ signal enable,busy : std_logic;
+-- signal prev_busy : std_logic;
+ signal bytes_to_send : std_logic_vector(0 to G_BYTE_SIZE-1);
+ signal clock : std_logic;
+
+begin
+
+ clock_process : process (i_reset,i_clock) is
+-- constant clock_period : time := 18.368 us;
+-- constant clock_period : time := 467.36 ns;
+ constant clock_period : integer := 467; -- ns
+ constant board_period : integer := 20; -- ns
+ constant t : integer := (clock_period / board_period);
+ variable v : integer range 0 to t-1;
+ begin
+ if (i_reset = '1') then
+ v := 0;
+ clock <= '0';
+ report integer'image(clock_period) & "," & integer'image(board_period) & "," & integer'image(t);
+ elsif (rising_edge(i_clock)) then
+ if (v = t-1) then
+ v := 0;
+ clock <= '1';
+ else
+ v := v + 1;
+ clock <= '0';
+ end if;
+ end if;
+ end process clock_process;
+
+ my_i2c_entity : my_i2c_pc
+ PORT MAP (
+ i_clock => clock,
+ i_reset => i_reset,
+ i_slave_address => "0111100",
+ i_slave_rw => '1',
+ i_bytes_to_send => bytes_to_send,
+ i_enable => enable,
+ o_busy => busy,
+ o_sda => o_sda,
+ o_scl => o_scl
+ );
+
+-- p1 : process (i_reset,i_clock) is
+-- begin
+-- if (i_reset = '1') then
+-- prev_busy <= '0';
+-- elsif (rising_edge(i_clock)) then
+-- prev_busy <= busy;
+-- end if;
+-- end process p1;
+
+ p0 : process (busy,i_reset) is
+ variable v1 : integer;
+ begin
+ if (i_reset = '1') then
+ enable <= '1';
+ v1 := 0;
+ bytes_to_send <= sequence(v1);
+ elsif (rising_edge(busy)) then
+-- prev_busy <= busy;
+-- if (prev_busy = '0' and busy = '1') then
+ bytes_to_send <= sequence(v1);
+-- else
+ if (v1 = BYTES_SEQUENCE_LENGTH-1) then
+ v1 := 0;
+ enable <= '0';
+-- if (prev_busy = '1' and busy = '0') then
+-- enable <= '0';
+-- else
+-- enable <= '1';
+-- end if;
+ else
+ v1 := v1 + 1;
+ enable <= '1';
+-- if (prev_busy = '0' and busy = '1') then
+-- enable <= '0';
+-- else
+-- enable <= '1';
+-- end if;
+ end if;
+-- end if;
+ end if;
+ end process;
+
+end Behavioral;
diff --git a/myown_i2c/ripple_counter.vhd b/myown_i2c/ripple_counter.vhd
new file mode 100755
index 0000000..4d64d2b
--- /dev/null
+++ b/myown_i2c/ripple_counter.vhd
@@ -0,0 +1,179 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:32:30 05/04/2021
+-- Design Name:
+-- Module Name: ripple_counter - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity ripple_counter is
+Generic (
+N : integer := 32;
+MAX : integer := 1;
+delay_and : time := 0 ns;
+delay_nand : time := 0 ns;
+delay_nand3 : time := 0 ns;
+delay_nand4 : time := 0 ns;
+delay_not : time := 0 ns;
+delay_or : time := 0 ns;
+delay_mr : time := 0 ns
+);
+Port (
+i_clock : in std_logic;
+i_cpb : in std_logic;
+i_mrb : in std_logic;
+i_ud : in std_logic;
+o_q : inout std_logic_vector(N-1 downto 0)
+);
+end ripple_counter;
+
+architecture Behavioral of ripple_counter is
+
+ component FF_JK is
+ generic (
+ delay_and : time := 0 ns;
+ delay_nand : time := 0 ns;
+ delay_nand3 : time := 0 ns;
+ delay_nand4 : time := 0 ns;
+ delay_not : time := 0 ns
+ );
+ port (
+ i_r:in STD_LOGIC;
+ J,K,C:in STD_LOGIC;
+ Q1:out STD_LOGIC;
+ Q2:out STD_LOGIC
+ );
+ end component FF_JK;
+ for all : FF_JK use entity WORK.FF_JK(LUT);
+
+ component GATE_AND is
+ generic (
+ delay_and : TIME := 0 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_AND;
+-- for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+ for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_LUT);
+
+ component GATE_OR is
+ generic (
+ delay_or : TIME := 0 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_OR;
+-- for all : GATE_OR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+ for all : GATE_OR use entity WORK.GATE_OR(GATE_OR_LUT);
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 0 ns
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+-- for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ signal cp,mr : std_logic;
+ signal q1,q2 : std_logic_vector(N-1 downto 0);
+ signal ping,ping1,ping2 : std_logic;
+ signal ffjk_and_u,ffjk_and_d,ffjk_or : std_logic_vector(N-1 downto 0); -- XXX omit last FF JK
+ signal ud,udb : std_logic;
+ signal gated_clock : std_logic;
+ constant a : std_logic_vector(N-1 downto 0) := std_logic_vector(to_unsigned(MAX,N));
+ constant b : std_logic_vector(N-1 downto 0) := std_logic_vector(to_unsigned(0,N));
+
+-- constant WAIT_AND : time := 0 ps;
+-- constant WAIT_OR : time := 0 ps;
+-- constant WAIT_NOT : time := 0 ps;
+
+-- attribute CLOCK_SIGNAL : string;
+-- attribute CLOCK_SIGNAL of i_clock : signal is "yes"; --{yes | no};
+-- attribute BUFFER_TYPE : string;
+-- attribute BUFFER_TYPE of i_clock : signal is "BUFG"; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
+
+-- attribute loc : string;
+-- attribute loc of {signal_name | label_name }: {signal |label} is "location ";
+-- attribute loc of "g0_and_u" : label is "SLICE_X64Y92:SLICE_X79Y92";
+-- attribute loc of "g0_and_d" : label is "SLICE_X64Y94:SLICE_X79Y94";
+-- attribute loc of "g0_or" : label is "SLICE_X64Y93:SLICE_X79Y93";
+
+begin
+
+ ffjk_or(N-1) <= '0';
+ gand_lut2 : GATE_AND generic map (delay_and => delay_and) port map (A=>i_clock,B=>cp,C=>gated_clock); -- XXX ~20mhz
+-- BUFGCE_inst : BUFGCE port map ( -- XXX ~40mhz
+-- O => gated_clock, -- Clock buffer ouptput
+-- CE => cp, -- Clock enable input
+-- I => i_clock -- Clock buffer input
+-- );
+ ud <= i_ud;
+ o_q <= q1;
+ cp <= i_cpb;
+ mr <= '1' after delay_mr when (q1 = a or i_mrb = '1') else '0' after delay_mr;
+
+ g0_not_clock : GATE_NOT generic map (delay_not => delay_not) port map (A=>ud,B=>udb);
+
+ g0_and_u : for i in 0 to N-1 generate -- XXX omit last FF JK
+ g0_and_u_first : if (i=0) generate
+ g0_and_u_first : GATE_AND generic map (delay_and => delay_and) port map (A=>q1(i),B=>ud,C=>ffjk_and_u(i));
+ end generate g0_and_u_first;
+ g0_and_u_chain : if (i>0) generate
+ g0_and_u_chain : GATE_AND generic map (delay_and => delay_and) port map (A=>q1(i),B=>ffjk_and_u(i-1),C=>ffjk_and_u(i));
+ end generate g0_and_u_chain;
+ end generate g0_and_u;
+
+ g0_and_d : for i in 0 to N-1 generate -- XXX omit last FF JK
+ g0_and_d_first : if (i=0) generate
+ g0_and_d_first : GATE_AND generic map (delay_and => delay_and) port map (A=>q2(i),B=>udb,C=>ffjk_and_d(i)); -- XXX udb make unconnected
+ end generate g0_and_d_first;
+ g0_and_d_chain : if (i>0) generate
+ g0_and_d_chain : GATE_AND generic map (delay_and => delay_and) port map (A=>q2(i),B=>ffjk_and_d(i-1),C=>ffjk_and_d(i));
+ end generate g0_and_d_chain;
+ end generate g0_and_d;
+
+ g0_or : for i in 0 to N-1 generate -- XXX omit last FF JK
+ g0_or_chain : GATE_OR generic map (delay_or => delay_or) port map (A=>ffjk_and_u(i),B=>ffjk_and_d(i),C=>ffjk_or(i));
+ end generate g0_or;
+
+ g0 : for i in 0 to N-1 generate
+ ffjk_first : if (i=0) generate
+ ffjk_first : FF_JK generic map (delay_and => delay_and, delay_nand => delay_nand, delay_nand3 => delay_nand3, delay_nand4 => delay_nand4, delay_not => delay_not) port map (i_r=>mr,J=>cp,K=>cp,C=>gated_clock,Q1=>q1(i),Q2=>q2(i));
+ end generate ffjk_first;
+ ffjk_chain : if (i>0) generate
+ ffjk_chain : FF_JK generic map (delay_and => delay_and, delay_nand => delay_nand, delay_nand3 => delay_nand3, delay_nand4 => delay_nand4, delay_not => delay_not) port map (i_r=>mr,J=>ffjk_or(i-1),K=>ffjk_or(i-1),C=>gated_clock,Q1=>q1(i),Q2=>q2(i));
+ end generate ffjk_chain;
+ end generate g0;
+
+end Behavioral;
diff --git a/myown_i2c/simulate-tb_power_on.sh b/myown_i2c/simulate-tb_power_on.sh
new file mode 100755
index 0000000..e642e3f
--- /dev/null
+++ b/myown_i2c/simulate-tb_power_on.sh
@@ -0,0 +1,4 @@
+#!/bin/sh
+PROJECT="tb_power_on"
+fuse -intstyle ise -incremental -o ./${PROJECT}_isim_beh.exe -prj ./${PROJECT}_beh.prj work.${PROJECT}
+./${PROJECT}_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb ./${PROJECT}_isim.beh.wdb -view ./${PROJECT}.wcfg
diff --git a/myown_i2c/tb_ff_e_latch.vhd b/myown_i2c/tb_ff_e_latch.vhd
new file mode 100755
index 0000000..954589f
--- /dev/null
+++ b/myown_i2c/tb_ff_e_latch.vhd
@@ -0,0 +1,158 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:24:33 01/12/2022
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/weirdboyjim_circuits/TB_FF_E_LATCH.vhd
+-- Project Name: weirdboyjim_circuits
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: FF_E_LATCH
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY TB_FF_E_LATCH IS
+END TB_FF_E_LATCH;
+
+ARCHITECTURE behavior OF TB_FF_E_LATCH IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT FF_E_LATCH
+GENERIC(
+delay_and : time := 0 ns;
+delay_and3 : time := 0 ns;
+delay_not : time := 0 ns;
+delay_nand2 : time := 0 ns;
+delay_nand3 : time := 0 ns
+);
+PORT(
+D : IN std_logic;
+E_H : IN std_logic;
+E_L : IN std_logic;
+Q : OUT std_logic
+);
+END COMPONENT FF_E_LATCH;
+--for all : FF_E_LATCH use entity WORK.FF_E_LATCH(Behavioral_E_LATCH);
+--for all : FF_E_LATCH use entity WORK.FF_E_LATCH(LUT_E_LATCH);
+for all : FF_E_LATCH use entity WORK.FF_E_LATCH(LUT_E_LATCH_NAND);
+
+
+--Inputs
+signal D : std_logic := '0';
+signal E_H : std_logic := '0';
+signal E_L : std_logic := '0';
+
+--Outputs
+signal Q : std_logic;
+
+constant clock_period : time := 20 ns;
+signal clock : std_logic;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: FF_E_LATCH
+GENERIC MAP (
+delay_and => 0 ns,
+delay_and3 => 0 ns,
+delay_not => 0 ns,
+delay_nand2 => 1 ns,
+delay_nand3 => 0 ns
+)
+PORT MAP (
+D => D,
+E_H => E_H,
+E_L => E_L,
+Q => Q
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+D <= not clock;
+-- Stimulus process
+stim_proc: process
+begin
+E_H <= '0';
+E_L <= '1';
+wait for 15 ns;
+E_H <= '1';
+E_L <= '0';
+wait for 10 ns;
+E_H <= '0';
+E_L <= '1';
+wait for 10 ns;
+E_H <= '1';
+E_L <= '0';
+wait for 6 ns;
+E_H <= '0';
+E_L <= '1';
+wait for 4 ns;
+E_H <= '1';
+E_L <= '0';
+wait for 10 ns;
+E_H <= '0';
+E_L <= '1';
+wait for 10 ns;
+E_H <= '1';
+E_L <= '0';
+wait for 15 ns;
+E_H <= '0';
+E_L <= '1';
+wait for 5 ns;
+E_H <= '1';
+E_L <= '0';
+wait for 15 ns;
+E_H <= '0';
+E_L <= '1';
+wait for 20 ns;
+E_H <= '1';
+E_L <= '0';
+wait for 5 ns;
+E_H <= '0';
+E_L <= '1';
+wait for 10 ns;
+E_H <= '1';
+E_L <= '0';
+wait for 5 ns;
+E_H <= '0';
+E_L <= '1';
+wait for 5 ns;
+E_H <= '1';
+E_L <= '0';
+wait for 10 ns;
+E_H <= '0';
+E_L <= '1';
+wait for 10 ns;
+report "done" severity failure;
+end process;
+
+END;
diff --git a/myown_i2c/tb_glcdfont.vhd b/myown_i2c/tb_glcdfont.vhd
new file mode 100755
index 0000000..bd837aa
--- /dev/null
+++ b/myown_i2c/tb_glcdfont.vhd
@@ -0,0 +1,112 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:47:46 09/04/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/i2c_test_1/tb_glcdfont.vhd
+-- Project Name: i2c_test_1
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: glcdfont
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_glcdfont IS END tb_glcdfont;
+
+ARCHITECTURE behavior OF tb_glcdfont IS
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT glcdfont
+ PORT(
+ i_clk : IN std_logic;
+ i_index : IN std_logic_vector(11 downto 0);
+ o_character : OUT std_logic_vector(7 downto 0)
+ );
+ END COMPONENT;
+
+ -- Inputs
+ signal i_clk : std_logic;
+ signal i_index : std_logic_vector(11 downto 0) := (others => '0');
+
+ -- Outputs
+ signal o_character : std_logic_vector(7 downto 0);
+
+ constant clock_period : time := 10 ns;
+ constant NUMBER_GLCDFONTC : natural := 1275; -- from tested file
+
+BEGIN
+ -- Instantiate the Unit Under Test (UUT)
+ uut: glcdfont PORT MAP (
+ i_clk => i_clk,
+ i_index => i_index,
+ o_character => o_character
+ );
+
+ -- Clock process definitions
+ clock_process :process
+ begin
+ i_clk <= '0';
+ wait for clock_period/2;
+ i_clk <= '1';
+ wait for clock_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- insert stimulus here
+ i_index <= std_logic_vector(to_unsigned(0,i_index'length));
+ wait for 10 ns;
+ i_index <= std_logic_vector(to_unsigned(5,i_index'length));
+ wait for 10 ns;
+ i_index <= std_logic_vector(to_unsigned(10,i_index'length));
+ wait for 10 ns;
+ i_index <= std_logic_vector(to_unsigned(15,i_index'length));
+ wait for 10 ns;
+ i_index <= std_logic_vector(to_unsigned(20,i_index'length));
+ wait for 10 ns;
+ i_index <= std_logic_vector(to_unsigned(25,i_index'length));
+ wait for 10 ns;
+ i_index <= std_logic_vector(to_unsigned(30,i_index'length));
+ wait for 10 ns;
+ i_index <= std_logic_vector(to_unsigned(35,i_index'length));
+ wait for 10 ns;
+ i_index <= std_logic_vector(to_unsigned(40,i_index'length));
+ wait for 10 ns;
+ i_index <= std_logic_vector(to_unsigned(45,i_index'length));
+ wait for 10 ns;
+ i_index <= std_logic_vector(to_unsigned(NUMBER_GLCDFONTC-25-1,i_index'length));
+ wait for 10 ns;
+ i_index <= std_logic_vector(to_unsigned(NUMBER_GLCDFONTC-20-1,i_index'length));
+ wait for 10 ns;
+ i_index <= std_logic_vector(to_unsigned(NUMBER_GLCDFONTC-15-1,i_index'length));
+ wait for 10 ns;
+ i_index <= std_logic_vector(to_unsigned(NUMBER_GLCDFONTC-10-1,i_index'length));
+ wait for 10 ns;
+ i_index <= std_logic_vector(to_unsigned(NUMBER_GLCDFONTC-5-1,i_index'length));
+ wait for 10 ns;
+ i_index <= std_logic_vector(to_unsigned(NUMBER_GLCDFONTC-1,i_index'length));
+ wait for 10 ns;
+ end process;
+END;
diff --git a/myown_i2c/tb_ic_74hc73.vhd b/myown_i2c/tb_ic_74hc73.vhd
new file mode 100755
index 0000000..a553969
--- /dev/null
+++ b/myown_i2c/tb_ic_74hc73.vhd
@@ -0,0 +1,159 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:32:10 02/02/2022
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/myown_i2c/tb_ic_74hc73.vhd
+-- Project Name: myown_i2c
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: ic_74hc73
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ic_74hc73 IS
+END tb_ic_74hc73;
+
+ARCHITECTURE behavior OF tb_ic_74hc73 IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT ic_74hc73
+PORT(
+i_j : IN std_logic;
+i_k : IN std_logic;
+i_r : IN std_logic;
+i_cpb : IN std_logic;
+o_q : OUT std_logic;
+o_qb : OUT std_logic
+);
+END COMPONENT;
+
+
+--Inputs
+signal i_j : std_logic := '0';
+signal i_k : std_logic := '0';
+signal i_r : std_logic := '1';
+signal i_cpb : std_logic := '0';
+
+--Outputs
+signal o_q : std_logic;
+signal o_qb : std_logic;
+
+constant clock_period : time := 20 ns;
+constant cp_period : time := 20 ns;
+signal clock : std_logic;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: ic_74hc73 PORT MAP (
+i_j => i_j,
+i_k => i_k,
+i_r => i_r,
+i_cpb => i_cpb,
+o_q => o_q,
+o_qb => o_qb
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+--i_cpb <= clock;
+i_cpb <=
+'1' after (200 ns + 50 * clock_period),
+'0' after (200 ns + 50 * clock_period) + cp_period,
+'1' after (200 ns + 100 * clock_period),
+'0' after (200 ns + 100 * clock_period) + cp_period,
+'1' after (200 ns + 150 * clock_period),
+'0' after (200 ns + 150 * clock_period) + cp_period,
+'1' after (200 ns + 200 * clock_period),
+'0' after (200 ns + 200 * clock_period) + cp_period,
+
+'1' after (200 ns + 250 * clock_period),
+'0' after (200 ns + 250 * clock_period) + cp_period,
+
+'1' after (200 ns + 300 * clock_period),
+'0' after (200 ns + 300 * clock_period) + cp_period,
+
+'1' after (200 ns + 350 * clock_period),
+'0' after (200 ns + 350 * clock_period) + cp_period,
+
+'1' after (1000 ns + 400 * clock_period),
+'0' after (1000 ns + 400 * clock_period) + cp_period,
+'1' after (1200 ns + 400 * clock_period),
+'0' after (1200 ns + 400 * clock_period) + cp_period,
+'1' after (1400 ns + 400 * clock_period),
+'0' after (1400 ns + 400 * clock_period) + cp_period,
+'1' after (1600 ns + 400 * clock_period),
+'0' after (1600 ns + 400 * clock_period) + cp_period,
+'1' after (1800 ns + 400 * clock_period),
+'0' after (1800 ns + 400 * clock_period) + cp_period
+;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+wait for 100 ns;
+wait for clock_period*10;
+-- insert stimulus here
+-- XXX 75HC73.pdf p.3 t.3
+-- nQ=L nQb=H asynchronous reset
+i_r <= '0';
+i_j <= '1';
+i_k <= '1';
+wait for 100*clock_period;
+-- nQ=q nQb=nq hold nochange
+i_r <= '1';
+i_j <= '0';
+i_k <= '0';
+wait for 100*clock_period;
+-- nQ=0 nQb=1 load 0 reset
+i_r <= '1';
+i_j <= '0';
+i_k <= '1';
+wait for 100*clock_period;
+-- nQ=1 nQb=0 load 1 set
+i_r <= '1';
+i_j <= '1';
+i_k <= '0';
+wait for 100*clock_period;
+-- nQ=nq nQb=q toggle
+i_r <= '1';
+i_j <= '1';
+i_k <= '1';
+wait for 100*clock_period;
+
+report "done" severity failure;
+
+end process;
+
+END;
diff --git a/myown_i2c/tb_ic_hef4027b.vhd b/myown_i2c/tb_ic_hef4027b.vhd
new file mode 100755
index 0000000..22d1c75
--- /dev/null
+++ b/myown_i2c/tb_ic_hef4027b.vhd
@@ -0,0 +1,195 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:23:30 01/31/2022
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/myown_i2c/tb_ic_hef4027b.vhd
+-- Project Name: myown_i2c
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: ic_hef4027b
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ic_hef4027b IS
+END tb_ic_hef4027b;
+
+ARCHITECTURE behavior OF tb_ic_hef4027b IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT ic_hef4027b
+PORT(
+i_cp : IN std_logic;
+i_j : IN std_logic;
+i_k : IN std_logic;
+i_cd : IN std_logic;
+i_sd : IN std_logic;
+o_q : OUT std_logic;
+o_qb : OUT std_logic
+);
+END COMPONENT;
+
+
+--Inputs
+signal i_cp : std_logic := '0';
+signal i_j : std_logic := '0';
+signal i_k : std_logic := '0';
+signal i_cd : std_logic := '0';
+signal i_sd : std_logic := '0';
+
+--Outputs
+signal o_q : std_logic;
+signal o_qb : std_logic;
+
+constant clock_period : time := 20 ns;
+constant cp_period : time := 33.333 ns; -- max 99
+signal clock : std_logic;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: ic_hef4027b PORT MAP (
+i_cp => i_cp,
+i_j => i_j,
+i_k => i_k,
+i_cd => i_cd,
+i_sd => i_sd,
+o_q => o_q,
+o_qb => o_qb
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+i_cp <=
+-- no change
+'1' after (10*cp_period + 30 * clock_period),
+'0' after (10*cp_period + 30 * clock_period) + cp_period,
+'1' after (10*cp_period + 40 * clock_period),
+'0' after (10*cp_period + 40 * clock_period) + cp_period,
+'1' after (10*cp_period + 50 * clock_period),
+'0' after (10*cp_period + 50 * clock_period) + cp_period,
+'1' after (10*cp_period + 60 * clock_period),
+'0' after (10*cp_period + 60 * clock_period) + cp_period,
+
+'1' after (10*cp_period + 70 * clock_period),
+'0' after (10*cp_period + 70 * clock_period) + cp_period,
+
+'1' after (10*cp_period + 80 * clock_period),
+'0' after (10*cp_period + 80 * clock_period) + cp_period,
+
+'1' after (10*cp_period + 90 * clock_period),
+'0' after (10*cp_period + 90 * clock_period) + cp_period,
+
+'1' after (10*cp_period + 0 ns + 100 * clock_period),
+'0' after (10*cp_period + 0 ns + 100 * clock_period) + cp_period,
+'1' after (10*cp_period + 100 ns + 100 * clock_period),
+'0' after (10*cp_period + 100 ns + 100 * clock_period) + cp_period,
+'1' after (10*cp_period + 200 ns + 100 * clock_period),
+'0' after (10*cp_period + 200 ns + 100 * clock_period) + cp_period,
+'1' after (10*cp_period + 300 ns + 100 * clock_period),
+'0' after (10*cp_period + 300 ns + 100 * clock_period) + cp_period,
+'1' after (10*cp_period + 400 ns + 100 * clock_period),
+'0' after (10*cp_period + 400 ns + 100 * clock_period) + cp_period
+
+;
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+wait for 100 ns;
+-- insert stimulus here
+-- XXX HEF4027B.pdf p.3 s.7
+-- nQ=H nQb=L
+i_sd <= '1';
+i_cd <= '0';
+i_j <= 'X';
+i_k <= 'X';
+wait for clock_period*10;
+-- nQ=L nQb=H
+i_sd <= '0';
+i_cd <= '1';
+i_j <= 'X';
+i_k <= 'X';
+wait for clock_period*10;
+-- nQ=H nQb=H
+i_sd <= '1';
+i_cd <= '1';
+i_j <= 'X';
+i_k <= 'X';
+wait for clock_period*10;
+-- nQ=nochange nQb=nochange
+i_sd <= '0';
+i_cd <= '0';
+i_j <= '0';
+i_k <= '0';
+wait for clock_period*10;
+-- nQ=nochange nQb=nochange
+i_sd <= '0';
+i_cd <= '0';
+i_j <= '0';
+i_k <= '0';
+wait for clock_period*10;
+-- nQ=nochange nQb=nochange
+i_sd <= '0';
+i_cd <= '0';
+i_j <= '0';
+i_k <= '0';
+wait for clock_period*10;
+-- nQ=nochange nQb=nochange
+i_sd <= '0';
+i_cd <= '0';
+i_j <= '0';
+i_k <= '0';
+wait for clock_period*10;
+-- nQ=H nQb=L
+i_sd <= '0';
+i_cd <= '0';
+i_j <= '0';
+i_k <= '1';
+wait for clock_period*10;
+-- nQ=L nQb=H
+i_sd <= '0';
+i_cd <= '0';
+i_j <= '1';
+i_k <= '0';
+wait for clock_period*10;
+-- nQ=nQb nQb=nQ
+i_sd <= '0';
+i_cd <= '0';
+i_j <= '1';
+i_k <= '1';
+wait for clock_period*10*10;
+
+report "done" severity failure;
+end process;
+
+END;
diff --git a/myown_i2c/tb_my_i2c_pc.vhd b/myown_i2c/tb_my_i2c_pc.vhd
new file mode 100755
index 0000000..ebb3d80
--- /dev/null
+++ b/myown_i2c/tb_my_i2c_pc.vhd
@@ -0,0 +1,129 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:43:49 01/17/2022
+-- Design Name:
+-- Module Name:
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: my_i2c_pc
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_my_i2c_pc IS
+END tb_my_i2c_pc;
+
+ARCHITECTURE behavior OF tb_my_i2c_pc IS
+
+constant N : integer := 20;
+
+COMPONENT my_i2c_pc
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+i_slave_address : IN std_logic_vector(0 to 6);
+i_slave_rw : in std_logic;
+i_bytes_to_send : IN std_logic_vector(0 to 7);
+i_enable : IN std_logic;
+o_busy : OUT std_logic;
+o_sda : OUT std_logic;
+o_scl : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+signal i_slave_address : std_logic_vector(0 to 6) := "0011110";
+signal i_slave_rw : std_logic := '1';
+signal i_bytes_to_send : std_logic_vector(0 to 7);
+signal i_enable : std_logic := '0';
+
+--Outputs
+signal o_busy : std_logic;
+signal o_sda : std_logic;
+signal o_scl : std_logic;
+
+-- Clock period definitions
+--constant i_clock_period : time := 18.368 us;
+constant i_clock_period : time := 0.23368*2 us;
+
+constant V : integer := 5;
+constant T : time := (1+7+1+1+(3*V*(8+1))+1) * i_clock_period; -- start,address,rw,ack,N byte+ack,stop
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: my_i2c_pc
+PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+i_slave_rw => i_slave_rw,
+i_slave_address => i_slave_address,
+i_bytes_to_send => i_bytes_to_send,
+i_enable => i_enable,
+o_busy => o_busy,
+o_sda => o_sda,
+o_scl => o_scl
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+i_reset <= '1', '0' after 2000 ns;
+--i_reset <= i_clock;
+
+--i_enable <= '1', '0' after T * N;
+--i_enable <= '1';
+
+-- Stimulus process
+stim_proc : process
+ type adata is array(0 to V-1) of std_logic_vector(7 downto 0);
+ variable vdata : adata := (
+ "00000000",
+ "11010101",
+ "00101010",
+ "11010101",
+ "00101010"
+ );
+begin
+i_enable <= '1';
+l0 : for i in 0 to V-1 loop
+ i_bytes_to_send <= vdata(i);
+ wait until o_busy = '1';
+end loop l0;
+wait for 10*i_clock_period;
+i_enable <= '0';
+wait for (T+time(2000 ns));
+report "done" severity failure;
+end process;
+
+END;
diff --git a/myown_i2c/tb_my_i2c_pc2.vhd b/myown_i2c/tb_my_i2c_pc2.vhd
new file mode 100755
index 0000000..cfdc9c5
--- /dev/null
+++ b/myown_i2c/tb_my_i2c_pc2.vhd
@@ -0,0 +1,142 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:23:05 01/28/2022
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/myown_i2c/tb_my_i2c_pc2.vhd
+-- Project Name: myown_i2c
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: my_i2c_pc2
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_my_i2c_pc2 IS
+END tb_my_i2c_pc2;
+
+ARCHITECTURE behavior OF tb_my_i2c_pc2 IS
+
+constant N : integer := 20;
+
+COMPONENT my_i2c_pc2
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+i_slave_address : IN std_logic_vector(0 to 6);
+i_slave_rw : in std_logic;
+i_bytes_to_send : IN std_logic_vector(0 to 7);
+i_enable : IN std_logic;
+--o_busy : OUT std_logic;
+o_sda : OUT std_logic;
+o_scl : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+signal i_slave_address : std_logic_vector(0 to 6) := "0111111";
+signal i_slave_rw : std_logic := '0';
+signal i_bytes_to_send : std_logic_vector(0 to 7);
+signal i_enable : std_logic := '0';
+
+--Outputs
+signal o_busy : std_logic;
+signal o_sda : std_logic;
+signal o_scl : std_logic;
+
+-- Clock period definitions
+--constant i_clock_period : time := 18.368 us;
+--constant i_clock_period : time := 0.23368*2 us;
+constant i_clock_period : time := 0.125 us; -- 400 khz - 2.5us / N (line ~50)
+
+constant V : integer := 6; -- num bytes to send
+constant T : time := (1+7+1+(V*(8+1))+1) * i_clock_period; -- start,address,rw,ack,N byte+ack,stop
+--constant T : time := 0 * i_clock_period;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: my_i2c_pc2
+PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+i_slave_rw => i_slave_rw,
+i_slave_address => i_slave_address,
+i_bytes_to_send => i_bytes_to_send,
+i_enable => i_enable,
+--o_busy => o_busy,
+o_sda => o_sda,
+o_scl => o_scl
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+--i_reset <= '1', '0' after 2000 ns;
+i_reset <= '1', '0' after 5*i_clock_period;
+--i_reset <= i_clock;
+
+i_enable <= '1', '0' after T * N;
+--i_enable <= '1';
+
+-- Stimulus process
+stim_proc : process
+ type adata is array(0 to V-1) of std_logic_vector(7 downto 0);
+ variable vdata : adata := (
+ "00000000",
+ "11010101",
+ "00101010",
+ "11010101",
+ "00101010",
+ "01111111"
+ );
+begin
+--i_enable <= '1';
+l0 : for i in 0 to V-1 loop
+ i_bytes_to_send <= vdata(i);
+-- wait until o_busy = '1';
+end loop l0;
+--wait for 10*i_clock_period;
+--i_enable <= '0';
+wait for (T*6);
+report "done" severity failure;
+end process;
+
+--stim_proc : process
+--begin
+--i_enable <= '1';
+--wait for 10000*i_clock_period;
+--i_enable <= '0';
+--wait for i_clock_period;
+--report "done" severity failure;
+--end process;
+
+END;
diff --git a/myown_i2c/tb_power_on.vhd b/myown_i2c/tb_power_on.vhd
new file mode 100755
index 0000000..29c215f
--- /dev/null
+++ b/myown_i2c/tb_power_on.vhd
@@ -0,0 +1,113 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:38:18 08/25/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/oled_128x32_1/tb_power_on.vhd
+-- Project Name: oled_128x32_1
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: power_on
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE WORK.p_constants1.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_power_on IS
+END tb_power_on;
+
+ARCHITECTURE behavior OF tb_power_on IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT power_on
+ PORT(
+ i_clock : IN std_logic;
+ i_reset : IN std_logic;
+ o_sda : OUT std_logic;
+ o_scl : OUT std_logic
+ );
+ END COMPONENT;
+
+ --Inputs
+ signal clock : std_logic := '0';
+ signal reset : std_logic := '0';
+
+ --Outputs
+ signal sda : std_logic;
+ signal scl : std_logic;
+
+ -- Clock period definitions
+ constant clock_period_50Mhz : time := (1_000_000_000/G_BOARD_CLOCK) * 1 ns;
+ signal clock_50mhz : std_logic;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: power_on PORT MAP (
+ i_clock => clock_50mhz,
+ i_reset => reset,
+ o_sda => sda,
+ o_scl => scl
+ );
+
+ -- Clock process definitions
+ clock_process_50MHZ : process
+ begin
+ clock_50mhz <= '0';
+ wait for clock_period_50Mhz/2;
+ clock_50mhz <= '1';
+ wait for clock_period_50Mhz/2;
+ end process;
+
+-- clock_process : process (reset,clock_50mhz) is
+---- constant clock_period : time := 18.368 us;
+-- constant clock_period : time := 0.23368*2 us;
+-- constant t : integer := (clock_period / clock_period_50Mhz);
+-- variable v : integer range 0 to t-1;
+-- begin
+-- if (reset = '1') then
+-- v := 0;
+-- report "t : " & integer'image(t);
+-- elsif (rising_edge(clock_50mhz)) then
+-- if (v = t-1) then
+-- v := 0;
+-- clock <= '1';
+-- else
+-- v := v + 1;
+-- clock <= '0';
+-- end if;
+-- end if;
+-- end process clock_process;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ reset <= '1';
+ wait for clock_period_50mhz;
+ reset <= '0';
+ wait for 5000 us;
+ report "done" severity failure;
+ end process;
+
+END;
diff --git a/myown_i2c/tb_power_on.wcfg b/myown_i2c/tb_power_on.wcfg
new file mode 100755
index 0000000..74f8f92
--- /dev/null
+++ b/myown_i2c/tb_power_on.wcfg
@@ -0,0 +1,105 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ tb
+ label
+
+ clock
+ clock
+
+
+ reset
+ reset
+
+
+ button
+ button
+
+
+ sda
+ sda
+
+
+ scl
+ scl
+
+
+ clock_50mhz
+ clock_50mhz
+
+
+ clock_period_50mhz
+ clock_period_50mhz
+
+
+
+ uut
+ label
+
+ i_clock
+ i_clock
+
+
+ i_reset
+ i_reset
+
+
+ i_button
+ i_button
+
+
+ o_sda
+ o_sda
+
+
+ o_scl
+ o_scl
+
+
+ enable
+ enable
+
+
+ busy
+ busy
+
+
+ prev_busy
+ prev_busy
+
+
+ bytes_to_send[0:7]
+ bytes_to_send[0:7]
+ HEXRADIX
+
+
+ clock
+ clock
+
+
+
diff --git a/myown_i2c/tb_ripple_counter.vhd b/myown_i2c/tb_ripple_counter.vhd
new file mode 100755
index 0000000..95d9125
--- /dev/null
+++ b/myown_i2c/tb_ripple_counter.vhd
@@ -0,0 +1,187 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:55:32 05/04/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_ripple_counter.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: ripple_counter
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ripple_counter IS
+END tb_ripple_counter;
+
+ARCHITECTURE behavior OF tb_ripple_counter IS
+
+constant N : integer := 8;
+constant MAX : integer := 130;
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT ripple_counter
+GENERIC(
+N : integer;
+MAX : integer;
+delay_and : time := 0 ns;
+delay_nand : time := 0 ns;
+delay_nand3 : time := 0 ns;
+delay_nand4 : time := 0 ns;
+delay_not : time := 0 ns;
+delay_or : time := 0 ns;
+delay_mr : time := 0 ns
+);
+PORT(
+i_clock : IN std_logic;
+i_cpb : IN std_logic;
+i_mrb : IN std_logic;
+i_ud : IN std_logic;
+o_q : INOUT std_logic_vector(N-1 downto 0)
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_cpb : std_logic := '0';
+signal i_mrb : std_logic := '0';
+signal i_ud : std_logic := '0';
+
+--BiDirs
+signal o_q : std_logic_vector(N-1 downto 0);
+
+signal clock : std_logic := '0';
+constant clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: ripple_counter
+GENERIC MAP (
+N => N,
+MAX => MAX,
+delay_and => 0 ns,
+delay_nand => 0 ns,
+delay_nand3 => 0 ns,
+delay_nand4 => 0 ns,
+delay_not => 0 ns,
+delay_or => 0 ns,
+delay_mr => clock_period
+)
+PORT MAP (
+i_clock => clock,
+i_cpb => i_cpb,
+i_mrb => i_mrb,
+i_ud => i_ud,
+o_q => o_q
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+
+---- insert stimulus here
+
+-- reset, ok 0 when reset=1
+wait for clock_period;
+i_mrb <= '1';
+wait for 25*clock_period;
+i_mrb <= '0';
+
+-- wait some time, count down when ud=0
+wait for 100*clock_period;
+
+-- mrb,cpb must be 1 to reset and start count
+i_mrb <= '1';
+i_cpb <= '1';
+i_ud <= '1'; -- count up
+wait for 1*clock_period;
+i_mrb <= '0'; -- start counting
+wait for 4*MAX*clock_period; -- wait MAX ticks
+i_cpb <= '0'; -- ok, count from 0 to MAX-2, MAX-1=0 then ping
+i_ud <= '0';
+
+-- wait some time
+wait for 100*clock_period;
+
+-- dont want reset, reset in middle cpb
+wait for clock_period;
+i_cpb <= '1';
+i_ud <= '0'; -- count down
+wait for (MAX*clock_period)/2 - 241 ns;
+i_mrb <= '1';
+wait for clock_period;
+i_mrb <= '0';
+wait for (MAX*clock_period)/2 + 241 ns;
+wait for (MAX*clock_period)/2 - 123 ns;
+i_mrb <= '1';
+wait for clock_period;
+i_mrb <= '0';
+wait for (MAX*clock_period)/2 + 123 ns;
+wait for (MAX*clock_period)/2 - 177 ns;
+i_mrb <= '1';
+wait for clock_period;
+i_mrb <= '0';
+wait for (MAX*clock_period)/2 + 177 ns;
+wait for (MAX*clock_period)/2 - 89 ns;
+i_mrb <= '1';
+wait for clock_period;
+i_mrb <= '0';
+wait for (MAX*clock_period)/2 + 89 ns;
+i_cpb <= '0'; -- strange
+i_ud <= '0';
+
+-- wait some time, not count, stay on 1
+wait for 100*clock_period;
+
+-- mrb,cpb must be 1 to reset and start count
+wait for clock_period;
+i_mrb <= '1';
+i_cpb <= '1';
+i_ud <= '0'; -- count down
+wait for 1*clock_period; -- wait for reset
+i_mrb <= '0'; -- start counting
+wait for 4*MAX*clock_period;
+i_cpb <= '0'; -- strange
+i_ud <= '0';
+
+wait for 10*clock_period; -- XXX reset
+i_mrb <= '1';
+wait for 100*clock_period;
+i_mrb <= '0';
+
+report "done" severity failure;
+
+end process;
+
+END;
diff --git a/myown_i2c/tb_test_oled.vhd b/myown_i2c/tb_test_oled.vhd
new file mode 100755
index 0000000..37a42fe
--- /dev/null
+++ b/myown_i2c/tb_test_oled.vhd
@@ -0,0 +1,107 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:51:58 08/28/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/i2c_test_1/tb_test_oled.vhd
+-- Project Name: i2c_test_1
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: test_oled
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE WORK.p_constants1.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_test_oled IS
+END tb_test_oled;
+
+ARCHITECTURE behavior OF tb_test_oled IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT test_oled
+ GENERIC (
+ g_board_clock : integer := G_BOARD_CLOCK;
+ g_bus_clock : integer := G_BUS_CLOCK
+ );
+ PORT(
+ i_clk : IN std_logic;
+ i_rst : IN std_logic;
+ i_refresh : IN std_logic;
+ io_sda : INOUT std_logic;
+ io_scl : INOUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal clk : std_logic := '0';
+ signal rst : std_logic := '0';
+ signal refresh : std_logic := '0';
+
+ --BiDirs
+ signal sda : std_logic;
+ signal scl : std_logic;
+
+ -- Clock period definitions
+ constant clk_period : time := (1_000_000_000/G_BOARD_CLOCK) * 1 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: test_oled
+ GENERIC MAP (
+ G_BOARD_CLOCK => G_BOARD_CLOCK,
+ G_BUS_CLOCK => G_BUS_CLOCK
+ )
+ PORT MAP (
+ i_clk => clk,
+ i_rst => rst,
+ i_refresh => refresh,
+ io_sda => sda,
+ io_scl => scl
+ );
+
+ -- Clock process definitions
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+rst <= '1','0' after clk_period;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+-- wait for 60 ms;
+-- refresh <= '1';
+-- wait for 20 ns;
+-- refresh <= '0';
+ wait for 110 ms;
+ report "tb done" severity failure;
+ end process;
+
+END;
diff --git a/tb_test_oled.vhd b/myown_i2c/tb_test_oled_fsm.vhd
old mode 100644
new mode 100755
similarity index 85%
rename from tb_test_oled.vhd
rename to myown_i2c/tb_test_oled_fsm.vhd
index ce14a55..c965207
--- a/tb_test_oled.vhd
+++ b/myown_i2c/tb_test_oled_fsm.vhd
@@ -27,23 +27,23 @@
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-USE WORK.p_pkg1.ALL;
+USE WORK.p_constants1.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-ENTITY tb_test_oled IS
-END tb_test_oled;
+ENTITY tb_test_oled_fsm IS
+END tb_test_oled_fsm;
-ARCHITECTURE behavior OF tb_test_oled IS
+ARCHITECTURE behavior OF tb_test_oled_fsm IS
-- Component Declaration for the Unit Under Test (UUT)
- COMPONENT test_oled
+ COMPONENT test_oled_fsm
PORT(
i_clk : IN std_logic;
- i_char : in array1;
+ i_rst : IN std_logic;
io_sda : INOUT std_logic;
io_scl : INOUT std_logic
);
@@ -52,7 +52,7 @@ ARCHITECTURE behavior OF tb_test_oled IS
--Inputs
signal clk : std_logic := '0';
- signal char : array1(0 to 1) := ("000101000101","000101111101");
+ signal rst : std_logic := '0';
--BiDirs
signal sda : std_logic;
@@ -64,9 +64,9 @@ ARCHITECTURE behavior OF tb_test_oled IS
BEGIN
-- Instantiate the Unit Under Test (UUT)
- uut: test_oled PORT MAP (
+ uut: test_oled_fsm PORT MAP (
i_clk => clk,
- i_char => char,
+ i_rst => rst,
io_sda => sda,
io_scl => scl
);
@@ -79,7 +79,9 @@ BEGIN
clk <= '1';
wait for clk_period/2;
end process;
-
+
+rst <= '1','0' after clk_period;
+
-- Stimulus process
stim_proc: process
begin
diff --git a/myown_i2c/tb_top.vhd b/myown_i2c/tb_top.vhd
new file mode 100755
index 0000000..4434650
--- /dev/null
+++ b/myown_i2c/tb_top.vhd
@@ -0,0 +1,98 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:26:03 07/27/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/myown_i2c/tb_top.vhd
+-- Project Name: myown_i2c
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_top IS
+END tb_top;
+
+ARCHITECTURE behavior OF tb_top IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT top
+PORT(
+clk : IN std_logic;
+rst : IN std_logic;
+--btn_1 : IN std_logic;
+sda : OUT std_logic;
+scl : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal clk : std_logic := '0';
+signal btn_1 : std_logic := '0';
+signal rst : std_logic := '0';
+
+--Outputs
+signal sda : std_logic;
+signal scl : std_logic;
+
+-- Clock period definitions
+constant clk_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: top PORT MAP (
+clk => clk,
+rst => rst,
+--btn_1 => btn_1,
+sda => sda,
+scl => scl
+);
+
+-- Clock process definitions
+clk_process :process
+begin
+clk <= '0';
+wait for clk_period/2;
+clk <= '1';
+wait for clk_period/2;
+end process;
+
+rst <= '1', '0' after clk_period;
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+wait for 100 ns;
+btn_1 <= '1';
+wait for 100 ns;
+btn_1 <= '0';
+wait for 5000 us;
+-- insert stimulus here
+report "done" severity failure;
+wait;
+end process;
+
+END;
diff --git a/myown_i2c/test_oled.vhd b/myown_i2c/test_oled.vhd
new file mode 100755
index 0000000..e031504
--- /dev/null
+++ b/myown_i2c/test_oled.vhd
@@ -0,0 +1,303 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:47:49 08/21/2020
+-- Design Name:
+-- Module Name: test_oled - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use WORK.p_constants1.ALL;
+
+entity test_oled is
+generic (
+g_board_clock : integer := G_BOARD_CLOCK;
+g_bus_clock : integer := G_BUS_CLOCK
+);
+port
+(
+signal i_clk : in std_logic;
+signal i_rst : in std_logic;
+signal i_refresh : in std_logic;
+signal io_sda,io_scl : inout std_logic
+);
+end test_oled;
+
+architecture Behavioral of test_oled is
+
+constant i_char : array1(0 to 5) := (x"30",x"31",x"32",x"33",x"34",x"35");
+
+constant GCLK : integer := g_board_clock;
+constant BCLK : integer := g_bus_clock;
+
+constant OLED_WIDTH : integer := 128;
+constant OLED_HEIGHT : integer := 32;
+constant OLED_PAGES_ALL : integer := OLED_WIDTH * ((OLED_HEIGHT + 7) / 8);
+constant OLED_DATA : std_logic_vector(0 to G_BYTE_SIZE-1) := x"40";
+constant OLED_COMMAND : std_logic_vector(0 to G_BYTE_SIZE-1) := x"00"; -- 00,80
+
+-- i2c oled 128x32 initialization sequence
+constant BYTES_SEQUENCE_LENGTH : natural := 26;
+type ARRAY_BYTE_SEQUENCE is array(0 to BYTES_SEQUENCE_LENGTH-1) of std_logic_vector(0 to G_BYTE_SIZE-1);
+constant sequence : ARRAY_BYTE_SEQUENCE := (
+x"AE",x"D5",x"80",x"A8",x"1F",x"D3",x"00",x"40",x"8D",
+x"14",x"20",x"00",x"A1",x"C8",x"DA",x"02",x"81",x"8F",
+x"D9",x"F1",x"DB",x"40",x"A4",x"A6",x"2E",x"AF");
+
+constant NI_SET_COORDINATION : natural := 6;
+type A_SET_COORDINATION is array (0 to NI_SET_COORDINATION-1) of std_logic_vector(7 downto 0);
+constant set_coordination : A_SET_COORDINATION := (
+x"21",x"00",std_logic_vector(to_unsigned(OLED_WIDTH-1,8)),
+x"22",x"00",std_logic_vector(to_unsigned(4-1,8))
+);
+
+SIGNAL i2c_ena : STD_LOGIC; --i2c enable signal
+SIGNAL i2c_addr : STD_LOGIC_VECTOR(6 DOWNTO 0); --i2c address signal
+SIGNAL i2c_rw : STD_LOGIC; --i2c read/write command signal
+SIGNAL i2c_data_wr : STD_LOGIC_VECTOR(0 to G_BYTE_SIZE-1); --i2c write data
+SIGNAL i2c_busy : STD_LOGIC; --i2c busy signal
+SIGNAL i2c_reset : STD_LOGIC; --i2c busy signal
+SIGNAL busy_prev : STD_LOGIC; --previous value of i2c busy signal
+
+signal busy_cnt : INTEGER range 0 to OLED_PAGES_ALL + 3; -- for i2c, count the clk tick when i2c_busy=1
+signal index_character : INTEGER range 0 to 1275 - 1;
+signal current_character : std_logic_vector(7 downto 0);
+
+component glcdfont is
+port(
+ i_clk : in std_logic;
+ i_index : in std_logic_vector(10 downto 0);
+ o_character : out std_logic_vector(7 downto 0)
+);
+end component glcdfont;
+for all : glcdfont use entity WORK.glcdfont(behavioral_glcdfont);
+
+COMPONENT my_i2c IS
+GENERIC (
+ BOARD_CLOCK : INTEGER := G_BOARD_CLOCK;
+ BUS_CLOCK : INTEGER := G_BUS_CLOCK
+);
+PORT (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_slave_address : std_logic_vector(0 to G_SLAVE_ADDRESS_SIZE-1);
+ i_bytes_to_send : in std_logic_vector(0 to G_BYTE_SIZE-1);
+ i_enable : in std_logic;
+ o_busy : out std_logic;
+ o_sda : out std_logic;
+ o_scl : out std_logic
+);
+END COMPONENT my_i2c;
+
+type state is
+(
+ idle, -- reset i2c
+ start, -- initialize oled
+ set_address_1, -- set begin point 0,0
+ clear_display_state_1, -- clear display and power on
+ set_address_2, -- set begin point 0,0
+ send_character, -- send the some data/text array
+ check_character_index, -- check have char
+ stop -- when index=counter, i2c disable
+);
+signal c_state : state;
+
+signal glcdfont_character : std_logic_vector(7 downto 0);
+signal glcdfont_index : std_logic_vector(10 downto 0);
+
+--attribute CLOCK_SIGNAL : string;
+--attribute CLOCK_SIGNAL of i_clk : signal is "yes"; --{yes | no};
+--attribute BUFFER_TYPE : string;
+--attribute BUFFER_TYPE of i_clk : signal is "BUFGP"; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
+
+begin
+
+i2c_addr <= "0111100"; -- 3C
+
+c0 : glcdfont
+port map
+(
+ i_clk => i_clk,
+ i_index => glcdfont_index,
+ o_character => glcdfont_character
+);
+
+c1 : my_i2c
+GENERIC MAP (
+ BOARD_CLOCK => GCLK,
+ BUS_CLOCK => BCLK
+)
+PORT MAP (
+ i_clock => i_clk,
+ i_reset => i_rst,
+ i_slave_address => i2c_addr,
+ i_bytes_to_send => i2c_data_wr,
+ i_enable => i2c_ena,
+ o_busy => i2c_busy,
+ o_sda => io_sda,
+ o_scl => io_scl
+);
+
+p0 : process (i_clk) is
+begin
+ if (rising_edge(i_clk)) then
+ if (i_rst = '1') then
+ c_state <= idle;
+ busy_cnt <= 0;
+ index_character <= 0;
+ glcdfont_index <= (others => '0');
+ i2c_reset <= '1';
+ else
+ case c_state is
+ when idle =>
+ c_state <= start;
+ i2c_reset <= '1';
+ when start =>
+ i2c_reset <= '0';
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ when 1 =>
+ i2c_data_wr <= OLED_COMMAND;
+ when 2 to BYTES_SEQUENCE_LENGTH+1 =>
+ i2c_data_wr <= sequence(busy_cnt-2); -- command
+ when BYTES_SEQUENCE_LENGTH+2 =>
+ i2c_ena <= '0';
+ i2c_data_wr <= (others => '0');
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ c_state <= set_address_1;
+ end if;
+ when others => null;
+ end case;
+ when set_address_1 =>
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ when 1 =>
+ i2c_data_wr <= OLED_COMMAND;
+ when 2 to NI_SET_COORDINATION+1 =>
+ i2c_data_wr <= set_coordination(busy_cnt-2); -- command
+ when NI_SET_COORDINATION+2 =>
+ i2c_ena <= '0';
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ c_state <= clear_display_state_1;
+ end if;
+ when others => null;
+ end case;
+ when clear_display_state_1 =>
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ when 1 =>
+ i2c_data_wr <= OLED_DATA;
+ when 2 to OLED_PAGES_ALL+1 =>
+ i2c_data_wr <= x"00"; -- command - FF/allpixels,00/blank,F0/zebra
+ when OLED_PAGES_ALL+2 =>
+ i2c_ena <= '0';
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ c_state <= set_address_2;
+ end if;
+ when others => null;
+ end case;
+ when set_address_2 =>
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ when 1 =>
+ i2c_data_wr <= OLED_COMMAND;
+ when 2 to NI_SET_COORDINATION+1 =>
+ i2c_data_wr <= set_coordination(busy_cnt-2); -- command
+ when NI_SET_COORDINATION+2 =>
+ i2c_ena <= '0';
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ c_state <= send_character;
+ end if;
+ when others => null;
+ end case;
+ when send_character =>
+ busy_prev <= i2c_busy;
+ if (busy_prev = '0' and i2c_busy = '1') then
+ busy_cnt <= busy_cnt + 1;
+ end if;
+ case busy_cnt is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ current_character <= i_char(index_character);
+ when 1 =>
+ i2c_data_wr <= x"40";
+ when 2 =>
+ glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(current_character))*5+0,glcdfont_index'length));
+ i2c_data_wr <= glcdfont_character;
+ when 3 =>
+ glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(current_character))*5+1,glcdfont_index'length));
+ i2c_data_wr <= glcdfont_character;
+ when 4 =>
+ glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(current_character))*5+2,glcdfont_index'length));
+ i2c_data_wr <= glcdfont_character;
+ when 5 =>
+ glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(current_character))*5+3,glcdfont_index'length));
+ i2c_data_wr <= glcdfont_character;
+ when 6 =>
+ glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(current_character))*5+4,glcdfont_index'length));
+ i2c_data_wr <= glcdfont_character;
+ when 7 =>
+ i2c_ena <= '0';
+ if (i2c_busy = '0') then
+ busy_cnt <= 0;
+ c_state <= check_character_index;
+ end if;
+ when others => null;
+ end case;
+ when check_character_index =>
+ if (index_character = i_char'length-1) then
+ c_state <= stop;
+ index_character <= 0;
+ else
+ c_state <= send_character;
+ index_character <= index_character + 1;
+ end if;
+ when stop =>
+ i2c_ena <= '0';
+-- c_state <= idle;
+ when others => null;
+ end case;
+ end if;
+ end if;
+end process p0;
+
+end Behavioral;
+
+
diff --git a/myown_i2c/test_oled_fsm.vhd b/myown_i2c/test_oled_fsm.vhd
new file mode 100755
index 0000000..6a0fd00
--- /dev/null
+++ b/myown_i2c/test_oled_fsm.vhd
@@ -0,0 +1,493 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:47:49 08/21/2020
+-- Design Name:
+-- Module Name: test_oled - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use WORK.p_constants1.ALL;
+
+-- WIP dont work, ~5-8mhz
+entity test_oled_fsm is
+generic (
+g_board_clock : integer := 50_000_000;
+g_bus_clock : integer := 100_000
+);
+port
+(
+signal i_clk : in std_logic;
+signal i_rst : in std_logic;
+signal io_sda,io_scl : inout std_logic
+);
+end test_oled_fsm;
+
+architecture Behavioral of test_oled_fsm is
+
+constant i_char : array1(0 to 5) := (x"30",x"31",x"32",x"33",x"34",x"35");
+
+constant GCLK : integer := g_board_clock;
+constant BCLK : integer := g_bus_clock;
+
+constant OLED_WIDTH : integer := 128;
+constant OLED_HEIGHT : integer := 32;
+constant OLED_PAGES_ALL : integer := OLED_WIDTH * ((OLED_HEIGHT + 7) / 8);
+constant OLED_DATA : integer := to_integer(unsigned'(x"40"));
+constant OLED_COMMAND : integer := to_integer(unsigned'(x"00")); -- 00,80
+
+constant NI_SET_COORDINATION : natural := 6;
+type A_SET_COORDINATION is array (0 to NI_SET_COORDINATION-1) of std_logic_vector(7 downto 0);
+constant set_coordination : A_SET_COORDINATION := (x"21",x"00",std_logic_vector(to_unsigned(OLED_WIDTH-1,8)),x"22",x"00",std_logic_vector(to_unsigned(OLED_HEIGHT-1,8)));
+
+SIGNAL i2c_ena : STD_LOGIC; --i2c enable signal
+SIGNAL i2c_addr : STD_LOGIC_VECTOR(6 DOWNTO 0); --i2c address signal
+SIGNAL i2c_data_wr : STD_LOGIC_VECTOR(0 to G_BYTE_SIZE-1); --i2c write data
+SIGNAL i2c_busy : STD_LOGIC; --i2c busy signal
+SIGNAL i2c_reset : STD_LOGIC; --i2c busy signal
+SIGNAL busy_prev : STD_LOGIC; --previous value of i2c busy signal
+
+signal current_character : std_logic_vector(7 downto 0);
+signal byte_sended : std_logic;
+
+component glcdfont is
+port(
+ i_clk : in std_logic;
+ i_index : in std_logic_vector(10 downto 0);
+ o_character : out std_logic_vector(7 downto 0)
+);
+end component glcdfont;
+for all : glcdfont use entity WORK.glcdfont(behavioral_glcdfont);
+
+component my_i2c_fsm is
+generic(
+BOARD_CLOCK : INTEGER := G_BOARD_CLOCK;
+BUS_CLOCK : INTEGER := G_BUS_CLOCK
+);
+port(
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_slave_address : in std_logic_vector(0 to G_SLAVE_ADDRESS_SIZE-1);
+i_bytes_to_send : in std_logic_vector(0 to G_BYTE_SIZE-1);
+i_enable : in std_logic;
+o_busy : out std_logic;
+o_byte_sended : out std_logic;
+o_sda : out std_logic;
+o_scl : out std_logic
+);
+end component my_i2c_fsm;
+
+type state is
+(
+ idle, -- reset i2c
+ start, -- initialize oled
+ set_address_1, -- set begin point 0,0
+ set_address_2, -- set begin point 0,0
+ send_character, -- send the some data/text array
+ check_character_index, -- check have char
+ stop -- when index=counter, i2c disable
+);
+signal c_state_test_oled_fsm,n_state_test_oled_fsm : state;
+
+signal glcdfont_character : std_logic_vector(7 downto 0);
+signal glcdfont_index : std_logic_vector(10 downto 0);
+
+component ripple_counter is
+Generic (
+N : integer := 32;
+MAX : integer := 1
+);
+Port (
+i_clock : in std_logic;
+i_cpb : in std_logic;
+i_mrb : in std_logic;
+i_ud : in std_logic;
+o_q : inout std_logic_vector(N-1 downto 0)
+);
+end component ripple_counter;
+constant RC0_N : integer := 6;
+constant RC0_MAX : integer := BYTES_SEQUENCE_LENGTH+3;
+signal rc0_cpb,rc0_mrb : std_logic;
+signal rc0_q : std_logic_vector(RC0_N-1 downto 0);
+signal rc0_ping : std_logic;
+constant RC1_N : integer := 4;
+constant RC1_MAX : integer := 7;
+signal rc1_cpb,rc1_mrb : std_logic;
+signal rc1_q : std_logic_vector(RC1_N-1 downto 0);
+signal rc1_ping : std_logic;
+constant RC2_N : integer := 4;
+constant RC2_MAX : integer := 6;
+signal rc2_cpb,rc2_mrb : std_logic;
+signal rc2_q : std_logic_vector(RC2_N-1 downto 0);
+signal rc2_ping : std_logic;
+
+signal character_sended : std_logic;
+
+attribute CLOCK_SIGNAL : string;
+attribute CLOCK_SIGNAL of i_clk : signal is "yes"; --{yes | no};
+--attribute CLOCK_SIGNAL of byte_sended : signal is "no"; --{yes | no};
+--attribute BUFFER_TYPE : string;
+--attribute BUFFER_TYPE of i_clk : signal is "BUFGP"; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
+--attribute BUFFER_TYPE of byte_sended : signal is "none"; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
+
+begin
+
+i2c_addr <= "0111100"; -- 3C
+--i2c_addr <= "1111111"; -- 3C
+--i2c_addr <= "0000000"; -- 3C
+
+c0 : glcdfont
+port map
+(
+ i_clk => byte_sended,
+ i_index => glcdfont_index,
+ o_character => glcdfont_character
+);
+
+c1 : my_i2c_fsm
+GENERIC MAP
+(
+ BOARD_CLOCK => GCLK,
+ BUS_CLOCK => BCLK
+)
+PORT MAP
+(
+ i_clock => i_clk,
+ i_reset => i2c_reset,
+ i_enable => i2c_ena,
+ i_slave_address => i2c_addr,
+ i_bytes_to_send => i2c_data_wr,
+ o_busy => i2c_busy,
+ o_byte_sended => byte_sended,
+ o_sda => io_sda,
+ o_scl => io_scl
+);
+
+test_oled_fsm_entity_rc0 : ripple_counter
+Generic map (N => RC0_N, MAX => RC0_MAX)
+Port map (
+i_clock => byte_sended,
+i_cpb => rc0_cpb,
+i_mrb => rc0_mrb,
+i_ud => '1',
+o_q => rc0_q
+);
+
+test_oled_fsm_entity_rc1 : ripple_counter
+Generic map (N => RC1_N, MAX => RC1_MAX)
+Port map (
+i_clock => byte_sended,
+i_cpb => rc1_cpb,
+i_mrb => rc1_mrb,
+i_ud => '1',
+o_q => rc1_q
+);
+
+test_oled_fsm_entity_rc2 : ripple_counter
+Generic map (N => RC2_N, MAX => RC2_MAX)
+Port map (
+i_clock => character_sended,
+i_cpb => rc2_cpb,
+i_mrb => rc2_mrb,
+i_ud => '1',
+o_q => rc2_q
+);
+
+test_oled_fsm_p1 : process (i_clk,i_rst) is
+begin
+ if (i_rst = '1') then
+ c_state_test_oled_fsm <= idle;
+ elsif (rising_edge(i_clk)) then
+ c_state_test_oled_fsm <= n_state_test_oled_fsm;
+ end if;
+end process test_oled_fsm_p1;
+
+test_oled_fsm_p0 : process (c_state_test_oled_fsm,i2c_busy,glcdfont_character,busy_prev) is
+ variable index : integer range 0 to 6;
+begin
+ n_state_test_oled_fsm <= c_state_test_oled_fsm;
+ case c_state_test_oled_fsm is
+ when idle =>
+ n_state_test_oled_fsm <= start;
+ i2c_reset <= '1';
+ busy_prev <= '0';
+ i2c_ena <= '0';
+ i2c_data_wr <= (others => '0');
+ current_character <= (others => '0');
+ glcdfont_index <= (others => '0');
+ rc0_mrb <= '1';
+ rc0_cpb <= '0';
+ rc1_mrb <= '1';
+ rc1_cpb <= '0';
+ rc2_mrb <= '1';
+ rc2_cpb <= '0';
+ index := 0;
+ character_sended <= '0';
+ when start =>
+ index := 0;
+ character_sended <= '0';
+ i2c_reset <= '0';
+ busy_prev <= i2c_busy;
+ rc0_mrb <= '0';
+ rc1_mrb <= '0';
+ rc1_cpb <= '0';
+ rc2_cpb <= '0';
+-- rc0_cpb <= '0';
+ rc2_mrb <= '0';
+ if (busy_prev = '0' and i2c_busy = '1') then
+ rc0_cpb <= '0';
+ else
+ rc0_cpb <= '1';
+ end if;
+ case to_integer(unsigned(rc0_q)) is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ i2c_data_wr <= (others => '0');
+ current_character <= (others => '0');
+ glcdfont_index <= (others => '0');
+ when 1 to BYTES_SEQUENCE_LENGTH =>
+ i2c_ena <= '1';
+ i2c_data_wr <= sequence(to_integer(unsigned(rc0_q))-1); -- command
+ current_character <= (others => '0');
+ glcdfont_index <= (others => '0');
+ when BYTES_SEQUENCE_LENGTH+1 =>
+ i2c_ena <= '1';
+ i2c_data_wr <= (others => '0');
+ current_character <= (others => '0');
+ glcdfont_index <= (others => '0');
+-- if (i2c_busy = '0') then
+-- i2c_ena <= '0';
+ rc0_mrb <= '1';
+ n_state_test_oled_fsm <= set_address_1;
+-- end if;
+ when BYTES_SEQUENCE_LENGTH+2 =>
+ i2c_ena <= '0';
+ when others =>
+ i2c_ena <= '0';
+ i2c_data_wr <= (others => '0');
+ glcdfont_index <= (others => '0');
+ current_character <= (others => '0');
+ end case;
+ when set_address_1 =>
+ index := 0;
+ character_sended <= '0';
+ busy_prev <= i2c_busy;
+ rc0_mrb <= '0';
+ rc1_cpb <= '0';
+-- rc0_cpb <= '0';
+ rc2_mrb <= '0';
+ rc1_mrb <= '0';
+ rc2_cpb <= '0';
+ i2c_reset <= '0';
+ if (busy_prev = '0' and i2c_busy = '1') then
+ rc0_cpb <= '0';
+ else
+ rc0_cpb <= '1';
+ end if;
+ case to_integer(unsigned(rc0_q)) is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ i2c_data_wr <= (others => '0');
+ current_character <= (others => '0');
+ glcdfont_index <= (others => '0');
+ when 1 to NI_SET_COORDINATION =>
+ i2c_ena <= '1';
+ i2c_data_wr <= set_coordination(to_integer(unsigned(rc0_q))-1); -- command
+ current_character <= (others => '0');
+ glcdfont_index <= (others => '0');
+ when NI_SET_COORDINATION+1 =>
+ i2c_ena <= '1';
+ i2c_data_wr <= (others => '0');
+ current_character <= (others => '0');
+ glcdfont_index <= (others => '0');
+ if (i2c_busy = '0') then
+-- i2c_ena <= '0';
+ rc0_mrb <= '1';
+ n_state_test_oled_fsm <= set_address_2; --clear_display_state_1;
+ end if;
+ when others =>
+ i2c_ena <= '0';
+ i2c_data_wr <= (others => '0');
+ glcdfont_index <= (others => '0');
+ current_character <= (others => '0');
+ end case;
+ when set_address_2 =>
+ index := 0;
+ character_sended <= '0';
+ i2c_reset <= '0';
+ current_character <= (others => '0');
+ glcdfont_index <= (others => '0');
+ busy_prev <= i2c_busy;
+ rc0_mrb <= '0';
+ rc1_cpb <= '0';
+ rc2_cpb <= '0';
+-- rc0_cpb <= '0';
+ rc2_mrb <= '0';
+ rc1_mrb <= '0';
+ if (busy_prev = '0' and i2c_busy = '1') then
+ rc0_cpb <= '0';
+ else
+ rc0_cpb <= '1';
+ end if;
+ case to_integer(unsigned(rc0_q)) is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ i2c_data_wr <= (others => '0');
+ current_character <= (others => '0');
+ glcdfont_index <= (others => '0');
+ when 1 to NI_SET_COORDINATION =>
+ i2c_ena <= '1';
+ i2c_data_wr <= set_coordination(to_integer(unsigned(rc0_q))-1); -- command
+ current_character <= (others => '0');
+ glcdfont_index <= (others => '0');
+ when NI_SET_COORDINATION+1 =>
+ i2c_ena <= '1';
+ i2c_data_wr <= (others => '0');
+ current_character <= (others => '0');
+ glcdfont_index <= (others => '0');
+ if (i2c_busy = '0') then
+-- i2c_ena <= '0';
+ rc0_mrb <= '1';
+ n_state_test_oled_fsm <= send_character;
+ character_sended <= '1';
+ end if;
+ when others =>
+ i2c_ena <= '0';
+ i2c_data_wr <= (others => '0');
+ glcdfont_index <= (others => '0');
+ current_character <= (others => '0');
+ end case;
+ when send_character =>
+ index := to_integer(unsigned(rc2_q));
+ character_sended <= '0';
+ i2c_reset <= '0';
+ busy_prev <= i2c_busy;
+ glcdfont_index <= (others => '0');
+ rc0_mrb <= '0';
+ rc1_mrb <= '0';
+ rc1_cpb <= '1';
+ rc2_mrb <= '0';
+ rc2_cpb <= '1';
+ rc0_cpb <= '0';
+ busy_prev <= '0';
+-- if (busy_prev = '0' and i2c_busy = '1') then
+-- rc1_mrb <= '1';
+-- else
+-- rc1_mrb <= '0';
+-- end if;
+ case to_integer(unsigned(rc1_q)) is
+ when 0 =>
+ i2c_ena <= '1'; -- we are busy
+ current_character <= (others => '0');
+ i2c_data_wr <= (others => '0');
+ glcdfont_index <= (others => '0');
+ when 1 =>
+ i2c_ena <= '1';
+ current_character <= i_char(index);
+ glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(current_character))*5+0,glcdfont_index'length));
+ i2c_data_wr <= glcdfont_character;
+ when 2 =>
+ i2c_ena <= '1';
+ current_character <= i_char(index);
+ glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(current_character))*5+1,glcdfont_index'length));
+ i2c_data_wr <= glcdfont_character;
+ when 3 =>
+ i2c_ena <= '1';
+ current_character <= i_char(index);
+ glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(current_character))*5+2,glcdfont_index'length));
+ i2c_data_wr <= glcdfont_character;
+ when 4 =>
+ i2c_ena <= '1';
+ current_character <= i_char(index);
+ glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(current_character))*5+3,glcdfont_index'length));
+ i2c_data_wr <= glcdfont_character;
+ when 5 =>
+ i2c_ena <= '1';
+ current_character <= i_char(index);
+ glcdfont_index <= std_logic_vector(to_unsigned(to_integer(unsigned(current_character))*5+4,glcdfont_index'length));
+ i2c_data_wr <= glcdfont_character;
+ when 6 =>
+ i2c_ena <= '1';
+ current_character <= (others => '0');
+ i2c_data_wr <= (others => '0');
+ glcdfont_index <= (others => '0');
+ if (i2c_busy = '0') then
+-- i2c_ena <= '0';
+ rc1_mrb <= '1';
+ n_state_test_oled_fsm <= check_character_index;
+ end if;
+ when others =>
+ i2c_ena <= '0';
+ i2c_data_wr <= (others => '0');
+ glcdfont_index <= (others => '0');
+ current_character <= (others => '0');
+ end case;
+ when check_character_index =>
+ index := 0;
+ rc0_mrb <= '0';
+ rc2_cpb <= '1';
+ rc1_cpb <= '1';
+ rc0_cpb <= '0';
+ rc2_mrb <= '0';
+ rc1_mrb <= '0';
+ busy_prev <= '0';
+ i2c_ena <= '0';
+ i2c_reset <= '0';
+ i2c_data_wr <= (others => '0');
+ current_character <= (others => '0');
+ glcdfont_index <= (others => '0');
+ character_sended <= '1';
+ if (to_integer(unsigned(rc2_q)) = i_char'length - 1) then
+ n_state_test_oled_fsm <= stop;
+ rc1_mrb <= '0';
+ else
+ n_state_test_oled_fsm <= send_character;
+ end if;
+ when stop =>
+ index := 0;
+-- n_state_test_oled_fsm <= idle;
+ rc2_cpb <= '0';
+ rc0_cpb <= '0';
+ rc0_mrb <= '0';
+ rc1_cpb <= '0';
+ rc2_mrb <= '0';
+ rc1_mrb <= '0';
+ character_sended <= '0';
+ busy_prev <= '0';
+ i2c_ena <= '0';
+ i2c_reset <= '0';
+ i2c_data_wr <= (others => '0');
+ current_character <= (others => '0');
+ glcdfont_index <= (others => '0');
+ when others =>
+ rc0_mrb <= '1';
+ busy_prev <= '0';
+ i2c_ena <= '0';
+ rc1_cpb <= '0';
+ rc2_cpb <= '0';
+ i2c_reset <= '0';
+ glcdfont_index <= (others => '0');
+ rc0_cpb <= '0';
+ current_character <= (others => '0');
+ i2c_data_wr <= (others => '0');
+ character_sended <= '0';
+ rc2_mrb <= '1';
+ rc1_mrb <= '1';
+ end case;
+end process test_oled_fsm_p0;
+
+end Behavioral;
+
diff --git a/myown_i2c/top.vhd b/myown_i2c/top.vhd
new file mode 100755
index 0000000..53d09a7
--- /dev/null
+++ b/myown_i2c/top.vhd
@@ -0,0 +1,68 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:56:44 09/07/2020
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top is
+Port(
+clk : in STD_LOGIC;
+rst : in STD_LOGIC;
+--btn_1 : in STD_LOGIC;
+sda : out STD_LOGIC;
+scl : out STD_LOGIC
+);
+end top;
+
+architecture Behavioral of top is
+
+component power_on is
+port
+(
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+-- i_button : in std_logic;
+ o_sda : out std_logic;
+ o_scl : out std_logic
+);
+end component power_on;
+for all : power_on use entity WORK.power_on(Behavioral);
+
+begin
+
+c0 : power_on
+port map
+(
+ i_clock => clk,
+ i_reset => rst,
+-- i_button => btn_1,
+ o_sda => sda,
+ o_scl => scl
+);
+
+end Behavioral;
diff --git a/myown_i2c/transmission_gate_lr.vhd b/myown_i2c/transmission_gate_lr.vhd
new file mode 100755
index 0000000..f75e89f
--- /dev/null
+++ b/myown_i2c/transmission_gate_lr.vhd
@@ -0,0 +1,48 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:20:23 07/01/2021
+-- Design Name:
+-- Module Name: transmission_gate_lr - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity transmission_gate_lr is
+generic (
+ delay_ab : time := 0 ns;
+ delay_abz : time := 0 ns
+);
+port (
+ io_a : in std_logic;
+ io_b : inout std_logic;
+ i_s : in std_logic;
+ i_sb : in std_logic
+);
+end transmission_gate_lr;
+
+architecture Behavioral of transmission_gate_lr is
+begin
+ io_b <= io_a after delay_ab when i_s = '1' and i_sb = '0' else 'Z' after delay_abz when i_s = '0' and i_sb = '1';
+end Behavioral;
diff --git a/myown_i2c/transmission_gate_rl.vhd b/myown_i2c/transmission_gate_rl.vhd
new file mode 100755
index 0000000..2ede7d4
--- /dev/null
+++ b/myown_i2c/transmission_gate_rl.vhd
@@ -0,0 +1,48 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:20:23 07/01/2021
+-- Design Name:
+-- Module Name: transmission_gate_rl - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity transmission_gate_rl is
+generic (
+ delay_ba : time := 0 ns;
+ delay_baz : time := 0 ns
+);
+port (
+ io_a : inout std_logic;
+ io_b : in std_logic;
+ i_s : in std_logic;
+ i_sb : in std_logic
+);
+end transmission_gate_rl;
+
+architecture Behavioral of transmission_gate_rl is
+begin
+ io_a <= io_b after delay_ba when i_s = '0' and i_sb = '1' else 'Z' after delay_baz when i_s = '1' and i_sb = '0';
+end Behavioral;
diff --git a/network_repeater_100bT4/arbiter.vhd b/network_repeater_100bT4/arbiter.vhd
new file mode 100755
index 0000000..5dcfb95
--- /dev/null
+++ b/network_repeater_100bT4/arbiter.vhd
@@ -0,0 +1,102 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:12:47 06/12/2021
+-- Design Name:
+-- Module Name: arbiter - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity arbiter8 is
+port (
+ txclk : in std_logic;
+ areset : in std_logic;
+ activity1 : in std_logic;
+ activity2 : in std_logic;
+ activity3 : in std_logic;
+ activity4 : in std_logic;
+ activity5 : in std_logic;
+ activity6 : in std_logic;
+ activity7 : in std_logic;
+ activity8 : in std_logic;
+ sel1 : out std_logic;
+ sel2 : out std_logic;
+ sel3 : out std_logic;
+ sel4 : out std_logic;
+ sel5 : out std_logic;
+ sel6 : out std_logic;
+ sel7 : out std_logic;
+ sel8 : out std_logic;
+ nosel : out std_logic;
+ carrier : out std_logic;
+ collision : out std_logic
+);
+end arbiter8;
+
+use work.portetop_pkg.all;
+
+architecture archarbiter8 of arbiter8 is
+ signal colin,carin : std_logic;
+ signal activityin1,activityin2,activityin3,activityin4,activityin5,activityin6,activityin7,activityin8 : std_logic;
+ signal noactivity : std_logic;
+begin
+ u1 : rdff1 port map (txclk,areset,activity1,sel1);
+ u2 : rdff1 port map (txclk,areset,activity2,sel2);
+ u3 : rdff1 port map (txclk,areset,activity3,sel3);
+ u4 : rdff1 port map (txclk,areset,activity4,sel4);
+ u5 : rdff1 port map (txclk,areset,activity5,sel5);
+ u6 : rdff1 port map (txclk,areset,activity6,sel6);
+ u7 : rdff1 port map (txclk,areset,activity7,sel7);
+ u8 : rdff1 port map (txclk,areset,activity8,sel8);
+
+-- u9 : pdff1 port map (txclk,areset,noactivity,nosel);
+ u9 : rdff1 port map (txclk,areset,noactivity,nosel);
+
+ u10 : rdff1 port map (txclk,areset,colin,collision);
+ u11 : rdff1 port map (txclk,areset,carin,carrier);
+
+ activityin1 <= activity1;
+ activityin2 <= activity2 and not activity1;
+ activityin3 <= activity3 and not (activity1 or activity2);
+ activityin4 <= activity4 and not (activity1 or activity2 or activity3);
+ activityin5 <= activity5 and not (activity1 or activity2 or activity3 or activity4);
+ activityin6 <= activity6 and not (activity1 or activity2 or activity3 or activity4 or activity5);
+ activityin7 <= activity7 and not (activity1 or activity2 or activity3 or activity4 or activity5 or activity6);
+ activityin8 <= activity8 and not (activity1 or activity2 or activity3 or activity4 or activity5 or activity6 or activity7);
+
+ noactivity <= not (activity1 or activity2 or activity3 or activity4 or activity5 or activity6 or activity7 or activity8);
+
+ colin <=
+ (activity1 and (activity2 or activity3 or activity4 or activity5 or activity6 or activity7 or activity8)) or
+ (activity2 and (activity1 or activity3 or activity4 or activity5 or activity6 or activity7 or activity8)) or
+ (activity3 and (activity1 or activity2 or activity4 or activity5 or activity6 or activity7 or activity8)) or
+ (activity4 and (activity1 or activity2 or activity3 or activity5 or activity6 or activity7 or activity8)) or
+ (activity5 and (activity1 or activity2 or activity3 or activity4 or activity6 or activity7 or activity8)) or
+ (activity6 and (activity1 or activity2 or activity3 or activity4 or activity5 or activity7 or activity8)) or
+ (activity7 and (activity1 or activity2 or activity3 or activity4 or activity5 or activity6 or activity8)) or
+ (activity8 and (activity1 or activity2 or activity3 or activity4 or activity5 or activity6 or activity7));
+
+ carin <= activity1 or activity2 or activity3 or activity4 or activity5 or activity6 or activity7 or activity8;
+end archarbiter8;
diff --git a/network_repeater_100bT4/ascount.vhd b/network_repeater_100bT4/ascount.vhd
new file mode 100755
index 0000000..187f0e8
--- /dev/null
+++ b/network_repeater_100bT4/ascount.vhd
@@ -0,0 +1,58 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:51:33 06/12/2021
+-- Design Name:
+-- Module Name: ascount - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ascount is
+generic (CounterSize: integer := 2);
+port (
+ clk,areset,sreset,enable : in std_logic;
+ count : inout std_logic_vector(CounterSize-1 downto 0)
+);
+end ascount;
+
+--use work.std_math.all;
+
+architecture archascount of ascount is
+begin
+ p1 : process (areset,clk) is
+ begin
+ if (areset = '1') then
+ count <= (others => '0');
+ elsif (rising_edge(clk)) then
+ if (sreset = '1') then
+ count <= (others => '0');
+ elsif (enable = '1') then
+ count <= std_logic_vector(to_unsigned(to_integer(unsigned(count)) + 1,CounterSize));
+ else
+ count <= count;
+ end if;
+ end if;
+ end process p1;
+end archascount;
diff --git a/network_repeater_100bT4/clockmux8.vhd b/network_repeater_100bT4/clockmux8.vhd
new file mode 100755
index 0000000..c127e7b
--- /dev/null
+++ b/network_repeater_100bT4/clockmux8.vhd
@@ -0,0 +1,64 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:31:03 06/12/2021
+-- Design Name:
+-- Module Name: clockmux8 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clockmux8 is
+port (
+ areset : in std_logic;
+ sreset : in std_logic;
+ clk1 : in std_logic;
+ clk2 : in std_logic;
+ clk3 : in std_logic;
+ clk4 : in std_logic;
+ clk5 : in std_logic;
+ clk6 : in std_logic;
+ clk7 : in std_logic;
+ clk8 : in std_logic;
+ clk9 : in std_logic;
+ sel1 : in std_logic;
+ sel2 : in std_logic;
+ sel3 : in std_logic;
+ sel4 : in std_logic;
+ sel5 : in std_logic;
+ sel6 : in std_logic;
+ sel7 : in std_logic;
+ sel8 : in std_logic;
+ sel9 : in std_logic;
+ rxclk : out std_logic
+);
+end clockmux8;
+
+architecture Behavioral of clockmux8 is
+
+begin
+
+
+end Behavioral;
+
diff --git a/network_repeater_100bT4/control.vhd b/network_repeater_100bT4/control.vhd
new file mode 100755
index 0000000..2b63441
--- /dev/null
+++ b/network_repeater_100bT4/control.vhd
@@ -0,0 +1,274 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:45:57 06/12/2021
+-- Design Name:
+-- Module Name: control - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity control is
+port (
+ txclk : in std_logic;
+ areset : in std_logic;
+ carrier : in std_logic;
+ collision : in std_logic;
+ rx_error : in std_logic; -- rx pma
+ rx_dv : in std_logic; -- found sfd
+ symbolend1 : in std_logic; -- end symbol line 1
+ symbolend2 : in std_logic; -- end symbol line 2
+ symbolend3 : in std_logic; -- end symbol line 3
+ symbolclr : out std_logic;
+ symbolinc : out std_logic;
+ symbol1 : out std_logic_vector(1 downto 0); -- selects
+ symbol2 : out std_logic_vector(1 downto 0); -- special
+ symbol3 : out std_logic_vector(1 downto 0); -- symbols
+ switch1 : out std_logic; -- selects special/data symbols
+ switch2 : out std_logic; -- selects special/data symbols
+ switch3 : out std_logic; -- selects special/data symbols
+ wptrclr : out std_logic;
+ wptrinc : out std_logic;
+ rptrclr : out std_logic;
+ rptrinc : out std_logic;
+ txdata : out std_logic;
+ idle : out std_logic;
+ preamble : out std_logic;
+ data : out std_logic;
+ col : out std_logic;
+ prescale : out std_logic
+);
+end control;
+
+use work.portetop_pkg.all;
+
+architecture archcontrol of control is
+ type states1 is (IDLE_STATE1,PRE1_STATE1,PRE2_STATE1,PRE3_STATE1,DATA_STATE1,JAM_STATE1,NOSFD_STATE1,ERROR_STATE1);
+ type states2 is (IDLE_STATE2,PRE1_STATE2,PRE2_STATE2,PRE3_STATE2,DATA_STATE2,JAM_STATE2,NOSFD_STATE2,ERROR_STATE2);
+ type states3 is (IDLE_STATE3,PRE1_STATE3,PRE2_STATE3,PRE3_STATE3,DATA_STATE3,JAM_STATE3,NOSFD_STATE3,ERROR_STATE3);
+ signal state1,newstate1 : states1;
+ signal state2,newstate2 : states2;
+ signal state3,newstate3 : states3;
+ signal carrierd,carrierdd : std_logic;
+ signal error,rx_dv_in,rx_error_in : std_logic;
+ signal no_sfd,no_sfd_in,no_data,data_valid : std_logic;
+ signal prescale_in : std_logic;
+ signal pout : std_logic_vector(9 downto 0);
+ constant jam : std_logic_vector(1 downto 0) := "00";
+ constant pre : std_logic_vector(1 downto 0) := "00";
+ constant sosb : std_logic_vector(1 downto 0) := "01";
+ constant bad : std_logic_vector(1 downto 0) := "10";
+ constant zero : std_logic_vector(1 downto 0) := "11";
+ constant fifodata : std_logic := '1';
+ constant symboldata : std_logic := '0';
+ signal vdd : std_logic := '1';
+ signal vss : std_logic := '0';
+begin
+ u1 : rsynch port map (txclk,areset,carrier,carrierdd);
+ u3 : rsynch port map (txclk,areset,rx_error_in,error);
+ u5 : rdff1 port map (txclk,areset,rx_dv_in,data_valid);
+ u7 : rdff1 port map (txclk,areset,no_sfd_in,no_data);
+ u8 : ascount generic map (10) port map (txclk,areset,vss,vdd,pout);
+ u9 : rdff1 port map (txclk,areset,prescale_in,prescale);
+ rx_dv_in <= carrierdd and rx_dv;
+ rx_error_in <= carrierdd and rx_error;
+ wptrclr <= not (rx_dv_in and not collision);
+ no_sfd_in <= (no_sfd or no_data) and carrier;
+ prescale_in <= '1' when pout = "11111111" else '0';
+ wptrinc <= '1';
+ rptrinc <= '1';
+ symbolinc <= '1';
+ p0 : process (carrier,collision,symbolend3,data_valid,error,state3) is
+ begin
+ case state3 is
+ when IDLE_STATE3 =>
+ symbol3 <= zero;
+ switch3 <= symboldata;
+ symbolclr <= '1';
+ rptrclr <= '1';
+ preamble <= '0';
+ data <= '0';
+ no_sfd <= '0';
+ idle <= '1';
+ col <= '0';
+ txdata <= '0';
+ if (collision = '1') then
+ newstate3 <= JAM_STATE3;
+ elsif (carrier = '1') then
+ newstate3 <= PRE1_STATE3;
+ else
+ newstate3 <= IDLE_STATE3;
+ end if;
+ when PRE1_STATE3 =>
+ symbol3 <= pre;
+ switch3 <= symboldata;
+ symbolclr <= '0';
+ rptrclr <= '1';
+ preamble <= '1';
+ data <= '0';
+ no_sfd <= '0';
+ idle <= '0';
+ col <= '0';
+ txdata <= '1';
+ if (carrier = '0') then
+ newstate3 <= IDLE_STATE3;
+ elsif (collision = '1') then
+ newstate3 <= JAM_STATE3;
+ elsif (symbolend3 = '1') then
+ newstate3 <= PRE2_STATE3;
+ else
+ newstate3 <= PRE1_STATE3;
+ end if;
+ when PRE2_STATE3 =>
+ symbol3 <= pre;
+ switch3 <= symboldata;
+ symbolclr <= '0';
+ rptrclr <= '1';
+ preamble <= '1';
+ data <= '0';
+ no_sfd <= '0';
+ idle <= '0';
+ col <= '0';
+ txdata <= '1';
+ if (carrier = '0') then
+ newstate3 <= IDLE_STATE3;
+ elsif (collision = '1') then
+ newstate3 <= JAM_STATE3;
+ elsif (symbolend3 = '1') then
+ newstate3 <= PRE3_STATE3;
+ else
+ newstate3 <= PRE2_STATE3;
+ end if;
+ when PRE3_STATE3 =>
+ symbol3 <= sosb;
+ switch3 <= symboldata;
+ symbolclr <= '0';
+ rptrclr <= '1';
+ preamble <= '1';
+ data <= '0';
+ no_sfd <= '0';
+ idle <= '0';
+ col <= '0';
+ txdata <= '1';
+ if (carrier = '0') then
+ newstate3 <= IDLE_STATE3;
+ elsif (collision = '1') then
+ newstate3 <= JAM_STATE3;
+ elsif (symbolend3 = '1' and error = '1') then
+ newstate3 <= ERROR_STATE3;
+ elsif (symbolend3 = '1' and data_valid = '0') then
+ newstate3 <= NOSFD_STATE3;
+ elsif (symbolend3 = '1' and data_valid = '1') then
+ newstate3 <= DATA_STATE3;
+ else
+ newstate3 <= PRE3_STATE3;
+ end if;
+ when DATA_STATE3 =>
+ symbol3 <= jam;
+ switch3 <= fifodata;
+ symbolclr <= '0';
+ rptrclr <= '0';
+ preamble <= '0';
+ data <= '1';
+ no_sfd <= '0';
+ idle <= '0';
+ col <= '0';
+ txdata <= '1';
+ if (carrier = '0') then
+ newstate3 <= IDLE_STATE3;
+ elsif (collision = '1') then
+ newstate3 <= JAM_STATE3;
+ elsif (symbolend3 = '1' and error = '1') then
+ newstate3 <= ERROR_STATE3;
+ else
+ newstate3 <= DATA_STATE3;
+ end if;
+ when JAM_STATE3 =>
+ symbol3 <= jam;
+ switch3 <= symboldata;
+ symbolclr <= '0';
+ rptrclr <= '1';
+ preamble <= '0';
+ data <= '0';
+ no_sfd <= '0';
+ idle <= '0';
+ col <= '1';
+ txdata <= '1';
+ if (carrier = '0') then
+ newstate3 <= IDLE_STATE3;
+ else
+ newstate3 <= JAM_STATE3;
+ end if;
+ when NOSFD_STATE3 =>
+ symbol3 <= jam;
+ switch3 <= symboldata;
+ symbolclr <= '0';
+ rptrclr <= '0';
+ preamble <= '0';
+ data <= '1';
+ no_sfd <= '1';
+ idle <= '0';
+ col <= '0';
+ txdata <= '1';
+ if (carrier = '0') then
+ newstate3 <= IDLE_STATE3;
+ elsif (collision = '1') then
+ newstate3 <= JAM_STATE3;
+ elsif (symbolend3 = '1' and error = '1') then
+ newstate3 <= ERROR_STATE3;
+ else
+ newstate3 <= NOSFD_STATE3;
+ end if;
+ when ERROR_STATE3 =>
+ symbol3 <= bad;
+ switch3 <= symboldata;
+ symbolclr <= '0';
+ rptrclr <= '0';
+ preamble <= '0';
+ data <= '1';
+ no_sfd <= '0';
+ idle <= '0';
+ col <= '0';
+ txdata <= '1';
+ if (carrier = '0') then
+ newstate3 <= IDLE_STATE3;
+ elsif (collision = '1') then
+ newstate3 <= JAM_STATE3;
+ else
+ newstate3 <= ERROR_STATE3;
+ end if;
+ end case;
+ end process p0;
+
+ p1 : process (txclk,areset) is
+ begin
+ if (areset = '1') then
+ state3 <= idle_state3;
+ elsif (rising_edge(txclk)) then
+ state3 <= newstate3;
+ else
+
+ end if;
+ end process p1;
+end archcontrol;
diff --git a/network_repeater_100bT4/core.vhd b/network_repeater_100bT4/core.vhd
new file mode 100755
index 0000000..3d5014c
--- /dev/null
+++ b/network_repeater_100bT4/core.vhd
@@ -0,0 +1,160 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:39:13 06/12/2021
+-- Design Name:
+-- Module Name: core - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity core is
+port (
+ reset : in std_logic;
+ clk : in std_logic; -- cktpad for txclk
+ rxd5 : in std_logic;
+ rxd4 : in std_logic;
+ rxd3 : in std_logic;
+ rxd2 : in std_logic;
+ rxd1 : in std_logic;
+ rxd0 : in std_logic;
+ rx_dv : in std_logic;
+ rx_er : in std_logic;
+ clk1 : in std_logic;
+ crs1 : in std_logic;
+ enable1_bar : in std_logic;
+ link1_bar : in std_logic;
+ clk2 : in std_logic;
+ crs2 : in std_logic;
+ enable2_bar : in std_logic;
+ link2_bar : in std_logic;
+ clk3 : in std_logic;
+ crs3 : in std_logic;
+ enable3_bar : in std_logic;
+ link3_bar : in std_logic;
+ clk4 : in std_logic;
+ crs4 : in std_logic;
+ enable4_bar : in std_logic;
+ link4_bar : in std_logic;
+ clk5 : in std_logic;
+ crs5 : in std_logic;
+ enable5_bar : in std_logic;
+ link5_bar : in std_logic;
+ clk6 : in std_logic;
+ crs6 : in std_logic;
+ enable6_bar : in std_logic;
+ link6_bar : in std_logic;
+ clk7 : in std_logic;
+ crs7 : in std_logic;
+ enable7_bar : in std_logic;
+ link7_bar : in std_logic;
+ clk8 : in std_logic;
+ crs8 : in std_logic;
+ enable8_bar : in std_logic;
+ link8_bar : in std_logic;
+ rx_en1 : out std_logic;
+ tx_en1 : out std_logic;
+ partition1_bar : inout std_logic;
+ jabber1_bar : inout std_logic;
+ rx_en2 : out std_logic;
+ tx_en2 : out std_logic;
+ partition2_bar : inout std_logic;
+ jabber2_bar : inout std_logic;
+ rx_en3 : out std_logic;
+ tx_en3 : out std_logic;
+ partition3_bar : inout std_logic;
+ jabber3_bar : inout std_logic;
+ rx_en4 : out std_logic;
+ tx_en4 : out std_logic;
+ partition4_bar : inout std_logic;
+ jabber4_bar : inout std_logic;
+ rx_en5 : out std_logic;
+ tx_en5 : out std_logic;
+ partition5_bar : inout std_logic;
+ jabber5_bar : inout std_logic;
+ rx_en6 : out std_logic;
+ tx_en6 : out std_logic;
+ partition6_bar : inout std_logic;
+ jabber6_bar : inout std_logic;
+ rx_en7 : out std_logic;
+ tx_en7 : out std_logic;
+ partition7_bar : inout std_logic;
+ jabber7_bar : inout std_logic;
+ rx_en8 : out std_logic;
+ tx_en8 : out std_logic;
+ partition8_bar : inout std_logic;
+ jabber8_bar : inout std_logic;
+ txd5 : out std_logic;
+ txd4 : out std_logic;
+ txd3 : out std_logic;
+ txd2 : out std_logic;
+ txd1 : out std_logic;
+ txd0 : out std_logic;
+ txdata : inout std_logic; -- tx_enall
+ idle : out std_logic;
+ preamble : out std_logic;
+ data : out std_logic;
+ jam : inout std_logic;
+ collision : inout std_logic;
+ wptr2 : out std_logic;
+ wptr1 : out std_logic;
+ wptr0 : out std_logic;
+ rptr2 : out std_logic;
+ rptr1 : out std_logic;
+ rptr0 : out std_logic
+);
+end core;
+
+use work.portetop_pkg.all;
+
+architecture archcore of core is
+ signal txclk1,nosel,areset,sel1,sel2,sel3,sel4 : std_logic;
+ signal sel5,sel6,sel7,sel8,rxclk,txclk : std_logic;
+ signal activity1,activity2,activity3,activity4,activity5,activity6,activity7,activity8 : std_logic;
+ signal carrier : std_logic;
+ signal wptrclr,wptrinc,rptrclr,rptrinc,symbolinc : std_logic;
+ signal switch1,switch2,switch3 : std_logic;
+ signal symbolend1,symbolend2,symbolend3 : std_logic;
+ signal symbolclr : std_logic;
+ signal symbol1,symbol2,symbol3 : std_logic_vector(1 downto 0);
+ signal dmuxout : std_logic_vector(5 downto 0);
+ signal prescale : std_logic;
+begin
+ u1 : clockmux8 port map (areset,clk1,clk2,clk3,clk4,clk5,clk6,clk7,clk8,txclk1,sel1,sel2,sel3,sel4,sel5,sel6,sel7,sel8,nosel,rxclk);
+ u2 : arbiter8 port map (txclk,areset,activity1,activity2,activity3,activity4,activity5,activity6,activity7,activity8,sel1,sel2,sel3,sel4,sel5,sel6,sel7,sel8,nosel,carrier,collision);
+ u3 : fifo port map (rxclk,txclk,areset,wptrclr,wptrinc,rptrclr,rptrinc,rxd5,rxd4,rxd3,rxd2,rxd1,rxd0,dmuxout,wptr2,wptr1,wptr0,rptr2,rptr1,rptr0);
+ u4 : symbolmux port map (txclk,areset,symbolclr,symbolinc,switch1,switch2,switch3,symbol1,symbol2,symbol3,dmuxout,symbolend1,symbolend2,symbolend3,txd5,txd4,txd3,txd2,txd1,txd0);
+ u5 : control port map (txclk,areset,carrier,collision,rx_er,rx_dv,symbolend1,symbolend2,symbolend3,symbolclr,symbolinc,symbol1,symbol2,symbol3,switch1,switch2,switch3,wptrclr,wptrinc,rptrclr,rptrinc,txdata,idle,preamble,data,jam,prescale);
+ u6 : porte port map (txclk,areset,crs1,enable1_bar,link1_bar,sel1,carrier,collision,jam,txdata,prescale,rx_en1,tx_en1,activity1,jabber1_bar,partition1_bar);
+ u7 : porte port map (txclk,areset,crs2,enable2_bar,link2_bar,sel2,carrier,collision,jam,txdata,prescale,rx_en2,tx_en2,activity2,jabber2_bar,partition2_bar);
+ u8 : porte port map (txclk,areset,crs3,enable3_bar,link3_bar,sel3,carrier,collision,jam,txdata,prescale,rx_en3,tx_en3,activity3,jabber3_bar,partition3_bar);
+ u9 : porte port map (txclk,areset,crs4,enable4_bar,link4_bar,sel4,carrier,collision,jam,txdata,prescale,rx_en4,tx_en4,activity4,jabber4_bar,partition4_bar);
+ u10 : porte port map (txclk,areset,crs5,enable5_bar,link5_bar,sel5,carrier,collision,jam,txdata,prescale,rx_en5,tx_en5,activity5,jabber5_bar,partition5_bar);
+ u11 : porte port map (txclk,areset,crs6,enable6_bar,link6_bar,sel6,carrier,collision,jam,txdata,prescale,rx_en6,tx_en6,activity6,jabber6_bar,partition6_bar);
+ u12 : porte port map (txclk,areset,crs7,enable7_bar,link7_bar,sel7,carrier,collision,jam,txdata,prescale,rx_en7,tx_en7,activity7,jabber7_bar,partition7_bar);
+ u13 : porte port map (txclk,areset,crs8,enable8_bar,link8_bar,sel8,carrier,collision,jam,txdata,prescale,rx_en8,tx_en8,activity8,jabber8_bar,partition8_bar);
+ txclk <= clk;
+ txclk1 <= clk;
+ areset <= reset;
+end archcore;
diff --git a/network_repeater_100bT4/fifo.vhd b/network_repeater_100bT4/fifo.vhd
new file mode 100755
index 0000000..dff6ec8
--- /dev/null
+++ b/network_repeater_100bT4/fifo.vhd
@@ -0,0 +1,103 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:33:10 06/12/2021
+-- Design Name:
+-- Module Name: fifo - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity fifo is
+port (
+ rxclk : in std_logic; -- from clk mux circuit
+ txclk : in std_logic; -- txclk ref
+ areset : in std_logic;
+ wptrclr : in std_logic;
+ wptrinc : in std_logic;
+ rptrclr : in std_logic;
+ rptrinc : in std_logic;
+ rxd0 : in std_logic;
+ rxd1 : in std_logic;
+ rxd2 : in std_logic;
+ rxd3 : in std_logic;
+ rxd4 : in std_logic;
+ rxd5 : in std_logic;
+ dmuxout : out std_logic_vector(5 downto 0);
+ wptr2 : out std_logic;
+ wptr1 : out std_logic;
+ wptr0 : out std_logic;
+ rptr2 : out std_logic;
+ rptr1 : out std_logic;
+ rptr0 : out std_logic
+);
+end fifo;
+
+use work.portetop_pkg.all;
+
+architecture archfifo of fifo is
+ signal rptr,wptr : std_logic_vector(2 downto 0);
+ signal qout0,qout1,qout2,qout3,qout4,qout5,qout6,qout7,rxd : std_logic_vector(5 downto 0);
+ signal en : std_logic_vector(7 downto 0);
+begin
+ u1 : rreg generic map (6) port map (rxclk,areset,en(0),rxd,qout0);
+ u2 : rreg generic map (6) port map (rxclk,areset,en(1),rxd,qout1);
+ u3 : rreg generic map (6) port map (rxclk,areset,en(2),rxd,qout2);
+ u4 : rreg generic map (6) port map (rxclk,areset,en(3),rxd,qout3);
+ u5 : rreg generic map (6) port map (rxclk,areset,en(4),rxd,qout4);
+ u6 : rreg generic map (6) port map (rxclk,areset,en(5),rxd,qout5);
+ u7 : rreg generic map (6) port map (rxclk,areset,en(6),rxd,qout6);
+ u8 : rreg generic map (6) port map (rxclk,areset,en(7),rxd,qout7);
+
+ u10 : ascount generic map (3) port map (rxclk,areset,wptrclr,wptrinc,wptr);
+ u11 : ascount generic map (3) port map (txclk,areset,rptrclr,rptrinc,rptr);
+
+ rxd <= (rxd5,rxd4,rxd3,rxd2,rxd1,rxd0);
+ wptr2 <= wptr(2);
+ wptr1 <= wptr(1);
+ wptr0 <= wptr(0);
+ rptr2 <= rptr(2);
+ rptr1 <= rptr(1);
+ rptr0 <= rptr(0);
+
+ with rptr select dmuxout <=
+ qout0 when "000",
+ qout0 when "001",
+ qout0 when "010",
+ qout0 when "011",
+ qout0 when "100",
+ qout0 when "101",
+ qout0 when "110",
+ qout0 when others;
+
+ with wptr select en <=
+ "00000001" when "000",
+ "00000010" when "001",
+ "00000100" when "010",
+ "00001000" when "011",
+ "00010000" when "100",
+ "00100000" when "101",
+ "01000000" when "110",
+ "10000000" when others;
+end archfifo;
diff --git a/network_repeater_100bT4/network_repeater_100bT4.xise b/network_repeater_100bT4/network_repeater_100bT4.xise
new file mode 100755
index 0000000..1998fbf
--- /dev/null
+++ b/network_repeater_100bT4/network_repeater_100bT4.xise
@@ -0,0 +1,446 @@
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diff --git a/network_repeater_100bT4/porte.vhd b/network_repeater_100bT4/porte.vhd
new file mode 100755
index 0000000..41b03ac
--- /dev/null
+++ b/network_repeater_100bT4/porte.vhd
@@ -0,0 +1,222 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:58:02 06/12/2021
+-- Design Name:
+-- Module Name: porte - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity porte is
+port (
+ txclk : in std_logic;
+ areset : in std_logic;
+ crs : in std_logic; -- carrier sense
+ enable_bar : in std_logic;
+ link_bar : in std_logic; -- pma link ok
+ selected : in std_logic; -- arbiter s
+ carrier : in std_logic; -- arbiter c
+ collision : in std_logic; -- arbiter c
+ jam : in std_logic; -- control j
+ txdata : in std_logic; -- control tx data
+ prescale : in std_logic; -- counter prescale
+ rx_en : out std_logic;
+ tx_en : out std_logic;
+ activity : out std_logic;
+ jabber_bar : inout std_logic;
+ partition_bar : inout std_logic
+);
+end porte;
+
+use work.portetop_pkg.all;
+
+architecture archporte of porte is
+ type states is (CLEAR_STATE, IDLE_STATE, CWATCH_STATE, CCOUNT_STATE, PWAIT_STATE, PHOLD_STATE, PCWATCH_STATE, WAIT_STATE);
+-- attribute state_encoding of states : type is one_hot_one;
+ signal state, newstate : states;
+ signal crsdd, link_bardd, enable_bardd : std_logic;
+ signal transmit, copyd, copyin, collisiond : std_logic;
+ signal jabcnt : std_logic_vector(3 downto 0);
+ signal jabberclr, jabberinc : std_logic;
+ signal quietd : std_logic;
+ signal cccnt : std_logic_vector(6 downto 0);
+ signal cclimit, nocoldone : std_logic;
+ signal nocolcnt : std_logic_vector(7 downto 0);
+ signal ccclr, ccinc, nocolclr, nocolinc : std_logic;
+ signal carpres,tx_eni : std_logic;
+begin
+ u0 : rsynch port map (txclk, areset, crs, crsdd);
+ u1 : psynch port map (txclk, areset, link_bar, link_bardd);
+ u2 : psynch port map (txclk, areset, enable_bar, enable_bardd);
+ u3 : rdff1 port map (txclk, areset, tx_eni, tx_en);
+ u4 : rdff1 port map (txclk, areset, copyin, copyd);
+ u5 : rdff1 port map (txclk, areset, collision, collisiond);
+ u6 : ascount generic map (4) port map (txclk, areset, jabberclr, jabberinc, jabcnt);
+ u7 : ascount generic map (7) port map (txclk, areset, ccclr, ccinc, cccnt);
+ u8 : ascount generic map (8) port map (txclk, areset, nocolclr, nocolinc, nocolcnt);
+
+ carpres <= crsdd and not enable_bardd;
+ activity <= carpres and not link_bardd and jabber_bar and partition_bar;
+ rx_en <= not enable_bardd and not link_bardd and selected and collision;
+ tx_eni <= not enable_bardd and not link_bardd and jabber_bar and transmit;
+ copyin <= carrier and not selected;
+ transmit <= txdata and (copyd or collisiond);
+ jabber_bar <= not (jabcnt(3) and jabcnt(2));
+ jabberclr <= not carpres;
+ jabberinc <= carpres and prescale and jabber_bar;
+ quietd <= not copyd;
+ cclimit <= cccnt(6);
+ nocoldone <= nocolcnt(7);
+
+ p1 : process (state, carpres, collisiond, copyd, quietd, nocoldone, cclimit, enable_bardd) is
+ begin
+ case state is
+ when CLEAR_STATE =>
+ partition_bar <= '1';
+ ccclr <= '1';
+ ccinc <= '0';
+ nocolclr <= '1';
+ nocolinc <= '0';
+ if (enable_bardd = '1') then
+ newstate <= CLEAR_STATE;
+ elsif (quietd = '1') then
+ newstate <= IDLE_STATE;
+ else
+ newstate <= CLEAR_STATE;
+ end if;
+ when IDLE_STATE =>
+ partition_bar <= '1';
+ ccclr <= '0';
+ ccinc <= '0';
+ nocolclr <= '1';
+ nocolinc <= '0';
+ if (enable_bardd = '1') then
+ newstate <= CLEAR_STATE;
+ elsif (carpres = '1') then
+ newstate <= CWATCH_STATE;
+ else
+ newstate <= IDLE_STATE;
+ end if;
+ when CWATCH_STATE =>
+ partition_bar <= '1';
+ ccclr <= '0';
+ ccinc <= collisiond;
+ nocolclr <= '0';
+ nocolinc <= '1';
+ if (enable_bardd = '1') then
+ newstate <= CLEAR_STATE;
+ elsif (collisiond = '1') then
+ newstate <= CCOUNT_STATE;
+ elsif (carpres = '0') then
+ newstate <= IDLE_STATE;
+ elsif (nocoldone = '1') then
+ newstate <= CLEAR_STATE;
+ else
+ newstate <= CWATCH_STATE;
+ end if;
+ when CCOUNT_STATE =>
+ partition_bar <= '1';
+ ccclr <= '0';
+ ccinc <= '0';
+ nocolclr <= '1';
+ nocolinc <= '0';
+ if (enable_bardd = '1') then
+ newstate <= CLEAR_STATE;
+ elsif (cclimit = '1') then
+ newstate <= PWAIT_STATE;
+ elsif (carpres = '0' and quietd = '1') then
+ newstate <= IDLE_STATE;
+ else
+ newstate <= CCOUNT_STATE;
+ end if;
+ when PWAIT_STATE =>
+ partition_bar <= '0';
+ ccclr <= '0';
+ ccinc <= '0';
+ nocolclr <= '1';
+ nocolinc <= '0';
+ if (enable_bardd = '1') then
+ newstate <= CLEAR_STATE;
+ elsif (carpres = '0' and quietd = '1') then
+ newstate <= PHOLD_STATE;
+ else
+ newstate <= PWAIT_STATE;
+ end if;
+ when PHOLD_STATE =>
+ partition_bar <= '0';
+ ccclr <= '0';
+ ccinc <= '0';
+ nocolclr <= '1';
+ nocolinc <= '0';
+ if (enable_bardd = '1') then
+ newstate <= CLEAR_STATE;
+ elsif (collisiond = '1' or copyd = '1') then
+ newstate <= PCWATCH_STATE;
+ else
+ newstate <= PHOLD_STATE;
+ end if;
+ when PCWATCH_STATE =>
+ partition_bar <= '0';
+ ccclr <= '0';
+ ccinc <= '0';
+ nocolclr <= '0';
+ nocolinc <= '1';
+ if (enable_bardd = '1') then
+ newstate <= CLEAR_STATE;
+ elsif (carpres = '1') then
+ newstate <= PWAIT_STATE;
+ elsif (quietd = '0') then
+ newstate <= PHOLD_STATE;
+ elsif (nocoldone = '1' and copyd = '1') then
+ newstate <= WAIT_STATE;
+ else
+ newstate <= PCWATCH_STATE;
+ end if;
+ when WAIT_STATE =>
+ partition_bar <= '0';
+ ccclr <= '1';
+ ccinc <= '0';
+ nocolclr <= '1';
+ nocolinc <= '0';
+ if (enable_bardd = '1') then
+ newstate <= CLEAR_STATE;
+ elsif (carpres = '0' and quietd = '1') then
+ newstate <= IDLE_STATE;
+ else
+ newstate <= WAIT_STATE;
+ end if;
+ end case;
+ end process p1;
+
+ p1clk : process (txclk,areset) is
+ begin
+ if (areset = '1') then
+ state <= clear_state;
+ elsif (rising_edge(txclk)) then
+ state <= newstate;
+ end if;
+ end process p1clk;
+
+end archporte;
diff --git a/network_repeater_100bT4/portetop_pkg.vhd b/network_repeater_100bT4/portetop_pkg.vhd
new file mode 100755
index 0000000..64748f2
--- /dev/null
+++ b/network_repeater_100bT4/portetop_pkg.vhd
@@ -0,0 +1,216 @@
+--
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+--
+-- To use any of the example code shown below, uncomment the lines and modify as necessary
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package portetop_pkg is
+component rreg
+generic (size : integer := 2);
+port (
+ clk,reset,load : in std_logic;
+ d : in std_logic_vector(size-1 downto 0);
+ q : inout std_logic_vector(size-1 downto 0)
+);
+end component;
+component reg
+generic (size : integer := 2);
+port (
+ clk,reset : in std_logic;
+ rst,pst : in std_logic;
+ d : in std_logic_vector(size-1 downto 0);
+ q : inout std_logic_vector(size-1 downto 0)
+);
+end component;
+component rsynch port (
+ clk,reset : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+);
+end component;
+component psynch port (
+ clk,reset : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+);
+end component;
+component rdff
+generic (size : integer := 2);
+port (
+ clk,reset : in std_logic;
+ d : in std_logic_vector(size-1 downto 0);
+ q : out std_logic_vector(size-1 downto 0)
+);
+end component;
+component rdff1 port (
+ clk,reset : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+);
+end component;
+component ascount
+ generic (CounterSize : integer := 2);
+ port (
+ clk,areset,sreset,enable : in std_logic;
+ count : inout std_logic_vector(CounterSize-1 downto 0)
+);
+end component;
+component clockmux8
+port (
+ areset : in std_logic;
+ sreset : in std_logic;
+ clk1 : in std_logic;
+ clk2 : in std_logic;
+ clk3 : in std_logic;
+ clk4 : in std_logic;
+ clk5 : in std_logic;
+ clk6 : in std_logic;
+ clk7 : in std_logic;
+ clk8 : in std_logic;
+ clk9 : in std_logic;
+ sel1 : in std_logic;
+ sel2 : in std_logic;
+ sel3 : in std_logic;
+ sel4 : in std_logic;
+ sel5 : in std_logic;
+ sel6 : in std_logic;
+ sel7 : in std_logic;
+ sel8 : in std_logic;
+ sel9 : in std_logic;
+ rxclk : out std_logic
+);
+end component;
+component arbiter8
+port (
+ txclk : in std_logic;
+ areset : in std_logic;
+ activity1 : in std_logic;
+ activity2 : in std_logic;
+ activity3 : in std_logic;
+ activity4 : in std_logic;
+ activity5 : in std_logic;
+ activity6 : in std_logic;
+ activity7 : in std_logic;
+ activity8 : in std_logic;
+ sel1 : out std_logic;
+ sel2 : out std_logic;
+ sel3 : out std_logic;
+ sel4 : out std_logic;
+ sel5 : out std_logic;
+ sel6 : out std_logic;
+ sel7 : out std_logic;
+ sel8 : out std_logic;
+ nosel : out std_logic;
+ carrier : out std_logic;
+ collision : out std_logic
+);
+end component;
+component fifo
+port (
+ rxclk : in std_logic; -- from clk mux circuit
+ txclk : in std_logic; -- txclk ref
+ areset : in std_logic;
+ wptrclr : in std_logic;
+ wptrinc : in std_logic;
+ rptrclr : in std_logic;
+ rptrinc : in std_logic;
+ rxd0 : in std_logic;
+ rxd1 : in std_logic;
+ rxd2 : in std_logic;
+ rxd3 : in std_logic;
+ rxd4 : in std_logic;
+ rxd5 : in std_logic;
+ dmuxout : out std_logic_vector(5 downto 0);
+ wptr2 : out std_logic;
+ wptr1 : out std_logic;
+ wptr0 : out std_logic;
+ rptr2 : out std_logic;
+ rptr1 : out std_logic;
+ rptr0 : out std_logic
+);
+end component;
+component symbolmux
+port (
+ txclk : in std_logic;
+ areset : in std_logic;
+ symbolclr : in std_logic;
+ symbolinc : in std_logic;
+ switch1 : in std_logic; -- line 1 d/s switch control
+ switch2 : in std_logic;
+ switch3 : in std_logic;
+ symbol1 : in std_logic_vector(1 downto 0); -- line 1 symbol mux ctrl
+ symbol2 : in std_logic_vector(1 downto 0);
+ symbol3 : in std_logic_vector(1 downto 0);
+ dmuxout : in std_logic_vector(5 downto 0); -- fifo data input
+ symbolend1 : buffer std_logic;
+ symbolend2 : out std_logic;
+ symbolend3 : out std_logic;
+ txd5 : out std_logic;
+ txd4 : out std_logic;
+ txd3 : out std_logic;
+ txd2 : out std_logic;
+ txd1 : out std_logic;
+ txd0 : out std_logic
+);
+end component;
+component porte
+port (
+ txclk : in std_logic;
+ areset : in std_logic;
+ crs : in std_logic; -- carrier sense
+ enable_bar : in std_logic;
+ link_bar : in std_logic; -- pma link ok
+ selected : in std_logic; -- arbiter s
+ carrier : in std_logic; -- arbiter c
+ collision : in std_logic; -- arbiter c
+ jam : in std_logic; -- control j
+ txdata : in std_logic; -- control tx data
+ prescale : in std_logic; -- counter prescale
+ rx_en : out std_logic;
+ tx_en : out std_logic;
+ activity : out std_logic;
+ jabber_bar : inout std_logic;
+ partition_bar : inout std_logic
+);
+end component;
+component control
+port (
+ txclk : in std_logic;
+ areset : in std_logic;
+ carrier : in std_logic;
+ collision : in std_logic;
+ rx_error : in std_logic; -- rx pma
+ rx_dv : in std_logic; -- found sfd
+ symbolend1 : in std_logic; -- end symbol line 1
+ symbolend2 : in std_logic; -- end symbol line 2
+ symbolend3 : in std_logic; -- end symbol line 3
+ symbolclr : out std_logic;
+ symbolinc : out std_logic;
+ symbol1 : out std_logic_vector(1 downto 0); -- selects
+ symbol2 : out std_logic_vector(1 downto 0); -- special
+ symbol3 : out std_logic_vector(1 downto 0); -- symbols
+ switch1 : out std_logic; -- selects special/data symbols
+ switch2 : out std_logic; -- selects special/data symbols
+ switch3 : out std_logic; -- selects special/data symbols
+ wptrclr : out std_logic;
+ wptrinc : out std_logic;
+ rptrclr : out std_logic;
+ rptrinc : out std_logic;
+ txdata : out std_logic;
+ idle : out std_logic;
+ preamble : out std_logic;
+ data : out std_logic;
+ col : out std_logic;
+ prescale : out std_logic
+);
+end component;
+end portetop_pkg;
+
+package body portetop_pkg is
+end portetop_pkg;
diff --git a/network_repeater_100bT4/psynch.vhd b/network_repeater_100bT4/psynch.vhd
new file mode 100755
index 0000000..faa2afb
--- /dev/null
+++ b/network_repeater_100bT4/psynch.vhd
@@ -0,0 +1,52 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:00:51 06/12/2021
+-- Design Name:
+-- Module Name: psynch - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity psynch is
+port (
+ clk,reset : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+);
+end psynch;
+
+architecture archpsynch of psynch is
+ signal temp : std_logic;
+begin
+ p1 : process (reset,clk) is
+ begin
+ if (reset = '1') then
+ q <= '1';
+ elsif (rising_edge(clk)) then
+ temp <= d;
+ q <= temp;
+ end if;
+ end process p1;
+end archpsynch;
diff --git a/network_repeater_100bT4/rdff.vhd b/network_repeater_100bT4/rdff.vhd
new file mode 100755
index 0000000..64ad185
--- /dev/null
+++ b/network_repeater_100bT4/rdff.vhd
@@ -0,0 +1,51 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:37:13 06/12/2021
+-- Design Name:
+-- Module Name: rdff - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity rdff is
+generic (size : integer := 2);
+port (
+ clk,reset : in std_logic;
+ d : in std_logic_vector(size-1 downto 0);
+ q : out std_logic_vector(size-1 downto 0)
+);
+end rdff;
+
+architecture archrdff of rdff is
+begin
+ p1 : process (reset,clk) is
+ begin
+ if (reset = '1') then
+ q <= (others => '0');
+ elsif(rising_edge(clk)) then
+ q <= d;
+ end if;
+ end process p1;
+end archrdff;
diff --git a/network_repeater_100bT4/rdff1.vhd b/network_repeater_100bT4/rdff1.vhd
new file mode 100755
index 0000000..137caf9
--- /dev/null
+++ b/network_repeater_100bT4/rdff1.vhd
@@ -0,0 +1,50 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:33:52 06/12/2021
+-- Design Name:
+-- Module Name: rdff1 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity rdff1 is
+port (
+ clk,reset : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+);
+end rdff1;
+
+architecture archrdff1 of rdff1 is
+begin
+ p1 : process (reset,clk) is
+ begin
+ if (reset = '1') then
+ q <= '0';
+ elsif (rising_edge(clk)) then
+ q <= d;
+ end if;
+ end process p1;
+end archrdff1;
diff --git a/network_repeater_100bT4/reg.vhd b/network_repeater_100bT4/reg.vhd
new file mode 100755
index 0000000..da06654
--- /dev/null
+++ b/network_repeater_100bT4/reg.vhd
@@ -0,0 +1,58 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:47:28 06/12/2021
+-- Design Name:
+-- Module Name: reg - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity reg is
+generic (size : integer := 2);
+port (
+ clk,load: in std_logic;
+ rst,pst : in std_logic;
+ d : in std_logic_vector(size-1 downto 0);
+ q : inout std_logic_vector(size-1 downto 0)
+);
+end reg;
+
+architecture archreg of reg is
+begin
+ p1 : process (clk) is
+ begin
+ if (rst = '1') then
+ q <= (others => '0');
+ elsif (pst = '1') then
+ q <= (others => '1');
+ elsif (rising_edge(clk)) then
+ if (load = '1') then
+ q <= d;
+ else
+ q <= q;
+ end if;
+ end if;
+ end process p1;
+end archreg;
diff --git a/network_repeater_100bT4/rreg.vhd b/network_repeater_100bT4/rreg.vhd
new file mode 100755
index 0000000..aa9a4a9
--- /dev/null
+++ b/network_repeater_100bT4/rreg.vhd
@@ -0,0 +1,55 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:43:55 06/12/2021
+-- Design Name:
+-- Module Name: rreg - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity rreg is
+generic (size : integer := 2);
+port (
+ clk,reset,load : in std_logic;
+ d : in std_logic_vector(size-1 downto 0);
+ q : inout std_logic_vector(size-1 downto 0)
+);
+end rreg;
+
+architecture archrreg of rreg is
+begin
+ p1 : process (clk,reset) is
+ begin
+ if (reset = '1') then
+ q <= (others => '0');
+ elsif (rising_edge(clk)) then
+ if (load = '1') then
+ q <= d;
+ else
+ q <= q;
+ end if;
+ end if;
+ end process p1;
+end archrreg;
diff --git a/network_repeater_100bT4/rreg1.vhd b/network_repeater_100bT4/rreg1.vhd
new file mode 100755
index 0000000..f02a649
--- /dev/null
+++ b/network_repeater_100bT4/rreg1.vhd
@@ -0,0 +1,54 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:40:31 06/12/2021
+-- Design Name:
+-- Module Name: rreg1 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity rreg1 is
+port (
+ clk,reset,load : in std_logic;
+ d : in std_logic;
+ q : inout std_logic
+);
+end rreg1;
+
+architecture archrreg1 of rreg1 is
+begin
+ p1 : process (reset,clk) is
+ begin
+ if (reset = '1') then
+ q <= '0';
+ elsif (rising_edge(clk)) then
+ if (load = '1') then
+ q <= d;
+ else
+ q <= q;
+ end if;
+ end if;
+ end process p1;
+end archrreg1;
diff --git a/network_repeater_100bT4/rsynch.vhd b/network_repeater_100bT4/rsynch.vhd
new file mode 100755
index 0000000..389a396
--- /dev/null
+++ b/network_repeater_100bT4/rsynch.vhd
@@ -0,0 +1,52 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:57:56 06/12/2021
+-- Design Name:
+-- Module Name: rsynch - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity rsynch is
+port (
+ clk,reset : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+);
+end rsynch;
+
+architecture archrsynch of rsynch is
+ signal temp : std_logic;
+begin
+ p1 : process (reset,clk) is
+ begin
+ if (reset = '1') then
+ q <= '0';
+ elsif (rising_edge(clk)) then
+ temp <= d;
+ q <= temp;
+ end if;
+ end process p1;
+end archrsynch;
diff --git a/network_repeater_100bT4/symbolmux.vhd b/network_repeater_100bT4/symbolmux.vhd
new file mode 100755
index 0000000..f4aef03
--- /dev/null
+++ b/network_repeater_100bT4/symbolmux.vhd
@@ -0,0 +1,169 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:56:46 06/12/2021
+-- Design Name:
+-- Module Name: symbolmux - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity symbolmux is
+port (
+ txclk : in std_logic;
+ areset : in std_logic;
+ symbolclr : in std_logic;
+ symbolinc : in std_logic;
+ switch1 : in std_logic; -- line 1 d/s switch control
+ switch2 : in std_logic;
+ switch3 : in std_logic;
+ symbol1 : in std_logic_vector(1 downto 0); -- line 1 symbol mux ctrl
+ symbol2 : in std_logic_vector(1 downto 0);
+ symbol3 : in std_logic_vector(1 downto 0);
+ dmuxout : in std_logic_vector(5 downto 0); -- fifo data input
+ symbolend1 : buffer std_logic;
+ symbolend2 : out std_logic;
+ symbolend3 : out std_logic;
+ txd5 : out std_logic;
+ txd4 : out std_logic;
+ txd3 : out std_logic;
+ txd2 : out std_logic;
+ txd1 : out std_logic;
+ txd0 : out std_logic
+);
+end symbolmux;
+
+use work.portetop_pkg.all;
+
+architecture archsymbolmux of symbolmux is
+ signal clearcount : std_logic;
+ signal symbolcount : std_logic_vector(2 downto 0);
+ signal sosb1,sosb2,sosb3,bad1,bad2,bad3,jam : std_logic_vector(1 downto 0);
+ signal txd,muxout,smuxout : std_logic_vector(5 downto 0);
+ constant plus : std_logic_vector(1 downto 0) := "10";
+ constant zero: std_logic_vector(1 downto 0) := "00";
+ constant minus : std_logic_vector(1 downto 0) := "01";
+begin
+ u1 : ascount generic map (3) port map (txclk,areset,clearcount,symbolinc,symbolcount);
+ u2 : rdff generic map (6) port map (txclk,areset,muxout,txd);
+
+ txd5 <= txd(5);
+ txd4 <= txd(4);
+ txd3 <= txd(3);
+ txd2 <= txd(2);
+ txd1 <= txd(1);
+ txd0 <= txd(0);
+ symbolend1 <= symbolcount(0) and not symbolcount(1) and symbolcount(2);
+ symbolend2 <= symbolcount(0) and not symbolcount(1) and not symbolcount(2);
+ symbolend3 <= symbolcount(0) and symbolcount(1) and not symbolcount(2);
+ clearcount <= symbolend1 or symbolclr;
+
+ with symbol1 select smuxout(1 downto 0) <=
+ jam when "00",
+ sosb1 when "01",
+ bad1 when "10",
+ zero when others;
+
+ with switch1 select muxout(1 downto 0) <=
+ smuxout(1 downto 0) when '0',
+ dmuxout(1 downto 0) when others;
+
+ with symbol2 select smuxout(3 downto 2) <=
+ jam when "00",
+ sosb2 when "01",
+ bad2 when "10",
+ zero when others;
+
+ with switch2 select muxout(3 downto 2) <=
+ smuxout(3 downto 2) when '0',
+ dmuxout(3 downto 2) when others;
+
+ with symbol3 select smuxout(5 downto 4) <=
+ jam when "00",
+ sosb3 when "01",
+ bad3 when "10",
+ zero when others;
+
+ with switch3 select muxout(5 downto 4) <=
+ smuxout(5 downto 4) when '0',
+ dmuxout(5 downto 4) when others;
+
+ with symbolcount(0) select jam <=
+ plus when '0',
+ minus when others;
+
+ with symbolcount select sosb1 <=
+ plus when "000",
+ minus when "001",
+ plus when "010",
+ minus when "011",
+ minus when "100",
+ plus when "101",
+ zero when others;
+
+ with symbolcount select sosb2 <=
+ minus when "000",
+ plus when "001",
+ plus when "010",
+ minus when "011",
+ plus when "100",
+ minus when "101",
+ zero when others;
+
+ with symbolcount select sosb3 <=
+ plus when "000",
+ minus when "001",
+ minus when "010",
+ plus when "011",
+ plus when "100",
+ minus when "101",
+ zero when others;
+
+ with symbolcount select bad1 <=
+ minus when "000",
+ minus when "001",
+ minus when "010",
+ plus when "011",
+ plus when "100",
+ plus when "101",
+ zero when others;
+
+ with symbolcount select bad2 <=
+ plus when "000",
+ plus when "001",
+ minus when "010",
+ minus when "011",
+ minus when "100",
+ plus when "101",
+ zero when others;
+
+ with symbolcount select bad3 <=
+ minus when "000",
+ plus when "001",
+ plus when "010",
+ plus when "011",
+ minus when "100",
+ minus when "101",
+ zero when others;
+end archsymbolmux;
diff --git a/network_repeater_100bT4/tb_core.vhd b/network_repeater_100bT4/tb_core.vhd
new file mode 100755
index 0000000..ee24181
--- /dev/null
+++ b/network_repeater_100bT4/tb_core.vhd
@@ -0,0 +1,322 @@
+-- TestBench Template
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY testbench IS
+END testbench;
+
+ARCHITECTURE behavior OF testbench IS
+
+-- Component Declaration
+COMPONENT core
+PORT(
+reset : in std_logic;
+clk : in std_logic; -- cktpad for txclk
+rxd5 : in std_logic;
+rxd4 : in std_logic;
+rxd3 : in std_logic;
+rxd2 : in std_logic;
+rxd1 : in std_logic;
+rxd0 : in std_logic;
+rx_dv : in std_logic;
+rx_er : in std_logic;
+clk1 : in std_logic;
+crs1 : in std_logic;
+enable1_bar : in std_logic;
+link1_bar : in std_logic;
+clk2 : in std_logic;
+crs2 : in std_logic;
+enable2_bar : in std_logic;
+link2_bar : in std_logic;
+clk3 : in std_logic;
+crs3 : in std_logic;
+enable3_bar : in std_logic;
+link3_bar : in std_logic;
+clk4 : in std_logic;
+crs4 : in std_logic;
+enable4_bar : in std_logic;
+link4_bar : in std_logic;
+clk5 : in std_logic;
+crs5 : in std_logic;
+enable5_bar : in std_logic;
+link5_bar : in std_logic;
+clk6 : in std_logic;
+crs6 : in std_logic;
+enable6_bar : in std_logic;
+link6_bar : in std_logic;
+clk7 : in std_logic;
+crs7 : in std_logic;
+enable7_bar : in std_logic;
+link7_bar : in std_logic;
+clk8 : in std_logic;
+crs8 : in std_logic;
+enable8_bar : in std_logic;
+link8_bar : in std_logic;
+rx_en1 : out std_logic;
+tx_en1 : out std_logic;
+partition1_bar : inout std_logic;
+jabber1_bar : inout std_logic;
+rx_en2 : out std_logic;
+tx_en2 : out std_logic;
+partition2_bar : inout std_logic;
+jabber2_bar : inout std_logic;
+rx_en3 : out std_logic;
+tx_en3 : out std_logic;
+partition3_bar : inout std_logic;
+jabber3_bar : inout std_logic;
+rx_en4 : out std_logic;
+tx_en4 : out std_logic;
+partition4_bar : inout std_logic;
+jabber4_bar : inout std_logic;
+rx_en5 : out std_logic;
+tx_en5 : out std_logic;
+partition5_bar : inout std_logic;
+jabber5_bar : inout std_logic;
+rx_en6 : out std_logic;
+tx_en6 : out std_logic;
+partition6_bar : inout std_logic;
+jabber6_bar : inout std_logic;
+rx_en7 : out std_logic;
+tx_en7 : out std_logic;
+partition7_bar : inout std_logic;
+jabber7_bar : inout std_logic;
+rx_en8 : out std_logic;
+tx_en8 : out std_logic;
+partition8_bar : inout std_logic;
+jabber8_bar : inout std_logic;
+txd5 : out std_logic;
+txd4 : out std_logic;
+txd3 : out std_logic;
+txd2 : out std_logic;
+txd1 : out std_logic;
+txd0 : out std_logic;
+txdata : inout std_logic; -- tx_enall
+idle : out std_logic;
+preamble : out std_logic;
+data : out std_logic;
+jam : inout std_logic;
+collision : inout std_logic;
+wptr2 : out std_logic;
+wptr1 : out std_logic;
+wptr0 : out std_logic;
+rptr2 : out std_logic;
+rptr1 : out std_logic;
+rptr0 : out std_logic
+);
+END COMPONENT core;
+
+signal reset : std_logic;
+signal clk : std_logic;
+signal rxd5 : std_logic;
+signal rxd4 : std_logic;
+signal rxd3 : std_logic;
+signal rxd2 : std_logic;
+signal rxd1 : std_logic;
+signal rxd0 : std_logic;
+signal rx_dv : std_logic;
+signal rx_er : std_logic;
+signal clk1 : std_logic;
+signal crs1 : std_logic;
+signal enable1_bar : std_logic;
+signal link1_bar : std_logic;
+signal clk2 : std_logic;
+signal crs2 : std_logic;
+signal enable2_bar : std_logic;
+signal link2_bar : std_logic;
+signal clk3 : std_logic;
+signal crs3 : std_logic;
+signal enable3_bar : std_logic;
+signal link3_bar : std_logic;
+signal clk4 : std_logic;
+signal crs4 : std_logic;
+signal enable4_bar : std_logic;
+signal link4_bar : std_logic;
+signal clk5 : std_logic;
+signal crs5 : std_logic;
+signal enable5_bar : std_logic;
+signal link5_bar : std_logic;
+signal clk6 : std_logic;
+signal crs6 : std_logic;
+signal enable6_bar : std_logic;
+signal link6_bar : std_logic;
+signal clk7 : std_logic;
+signal crs7 : std_logic;
+signal enable7_bar : std_logic;
+signal link7_bar : std_logic;
+signal clk8 : std_logic;
+signal crs8 : std_logic;
+signal enable8_bar : std_logic;
+signal link8_bar : std_logic;
+signal rx_en1 : std_logic;
+signal tx_en1 : std_logic;
+signal partition1_bar : std_logic;
+signal jabber1_bar : std_logic;
+signal rx_en2 : std_logic;
+signal tx_en2 : std_logic;
+signal partition2_bar : std_logic;
+signal jabber2_bar : std_logic;
+signal rx_en3 : std_logic;
+signal tx_en3 : std_logic;
+signal partition3_bar : std_logic;
+signal jabber3_bar : std_logic;
+signal rx_en4 : std_logic;
+signal tx_en4 : std_logic;
+signal partition4_bar : std_logic;
+signal jabber4_bar : std_logic;
+signal rx_en5 : std_logic;
+signal tx_en5 : std_logic;
+signal partition5_bar : std_logic;
+signal jabber5_bar : std_logic;
+signal rx_en6 : std_logic;
+signal tx_en6 : std_logic;
+signal partition6_bar : std_logic;
+signal jabber6_bar : std_logic;
+signal rx_en7 : std_logic;
+signal tx_en7 : std_logic;
+signal partition7_bar : std_logic;
+signal jabber7_bar : std_logic;
+signal rx_en8 : std_logic;
+signal tx_en8 : std_logic;
+signal partition8_bar : std_logic;
+signal jabber8_bar : std_logic;
+signal txd5 : std_logic;
+signal txd4 : std_logic;
+signal txd3 : std_logic;
+signal txd2 : std_logic;
+signal txd1 : std_logic;
+signal txd0 : std_logic;
+signal txdata : std_logic;
+signal idle : std_logic;
+signal preamble : std_logic;
+signal data : std_logic;
+signal jam : std_logic;
+signal collision : std_logic;
+signal wptr2 : std_logic;
+signal wptr1 : std_logic;
+signal wptr0 : std_logic;
+signal rptr2 : std_logic;
+signal rptr1 : std_logic;
+signal rptr0 : std_logic;
+
+constant clock_period : time := 20 ns;
+
+BEGIN
+
+-- Component Instantiation
+uut: core PORT MAP (
+reset => reset,
+clk => clk,
+rxd5 => rxd5,
+rxd4 => rxd4,
+rxd3 => rxd3,
+rxd2 => rxd2,
+rxd1 => rxd1,
+rxd0 => rxd0,
+rx_dv => rx_dv,
+rx_er => rx_er,
+clk1 => clk1,
+crs1 => crs1,
+enable1_bar => enable1_bar,
+link1_bar => link1_bar,
+clk2 => clk2,
+crs2 => crs2,
+enable2_bar => enable2_bar,
+link2_bar => link2_bar,
+clk3 => clk3,
+crs3 => crs3,
+enable3_bar => enable3_bar,
+link3_bar => link3_bar,
+clk4 => clk4,
+crs4 => crs4,
+enable4_bar => enable4_bar,
+link4_bar => link4_bar,
+clk5 => clk5,
+crs5 => crs5,
+enable5_bar => enable5_bar,
+link5_bar => link5_bar,
+clk6 => clk6,
+crs6 => crs6,
+enable6_bar => enable6_bar,
+link6_bar => link6_bar,
+clk7 => clk7,
+crs7 => crs7,
+enable7_bar => enable7_bar,
+link7_bar => link7_bar,
+clk8 => clk8,
+crs8 => crs8,
+enable8_bar => enable8_bar,
+link8_bar => link8_bar,
+rx_en1 => rx_en1,
+tx_en1 => tx_en1,
+partition1_bar => partition1_bar,
+jabber1_bar => jabber1_bar,
+rx_en2 => rx_en2,
+tx_en2 => tx_en2,
+partition2_bar => partition2_bar,
+jabber2_bar => jabber2_bar,
+rx_en3 => rx_en3,
+tx_en3 => tx_en3,
+partition3_bar => partition3_bar,
+jabber3_bar => jabber3_bar,
+rx_en4 => rx_en4,
+tx_en4 => tx_en4,
+partition4_bar => partition4_bar,
+jabber4_bar => jabber4_bar,
+rx_en5 => rx_en5,
+tx_en5 => tx_en5,
+partition5_bar => partition5_bar,
+jabber5_bar => jabber5_bar,
+rx_en6 => rx_en6,
+tx_en6 => tx_en6,
+partition6_bar => partition6_bar,
+jabber6_bar => jabber6_bar,
+rx_en7 => rx_en7,
+tx_en7 => tx_en7,
+partition7_bar => partition7_bar,
+jabber7_bar => jabber7_bar,
+rx_en8 => rx_en8,
+tx_en8 => tx_en8,
+partition8_bar => partition8_bar,
+jabber8_bar => jabber8_bar,
+txd5 => txd5,
+txd4 => txd4,
+txd3 => txd3,
+txd2 => txd2,
+txd1 => txd1,
+txd0 => txd0,
+txdata => txdata,
+idle => idle,
+preamble => preamble,
+data => data,
+jam => jam,
+collision => collision,
+wptr2 => wptr2,
+wptr1 => wptr1,
+wptr0 => wptr0,
+rptr2 => rptr2,
+rptr1 => rptr1,
+rptr0 => rptr0
+);
+
+cp : process
+begin
+clk <= '1';
+wait for clock_period/2;
+clk <= '0';
+wait for clock_period/2;
+end process cp;
+
+-- Test Bench Statements
+tb : PROCESS
+BEGIN
+reset <= '1';
+wait for clock_period;
+reset <= '0';
+wait for clock_period;
+wait;
+END PROCESS tb;
+-- End Test Bench
+
+END;
diff --git a/pll/cl_u1_buf_1x.vhd b/pll/cl_u1_buf_1x.vhd
new file mode 100755
index 0000000..b5f6055
--- /dev/null
+++ b/pll/cl_u1_buf_1x.vhd
@@ -0,0 +1,19 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VComponents.all;
+entity cl_u1_buf_1x is
+port (
+i : in bit;
+o : out bit
+);
+end entity cl_u1_buf_1x;
+architecture arch of cl_u1_buf_1x is
+signal tti : std_logic_vector(0 downto 0);
+signal tto : std_logic;
+begin
+tti(0) <= to_stdulogic(i);
+b : BUF port map (O=>tto,I=>tti(0));
+o <= to_bit(tto);
+end architecture arch;
+
diff --git a/pll/cl_u1_inv_16x.vhd b/pll/cl_u1_inv_16x.vhd
new file mode 100755
index 0000000..9f364d8
--- /dev/null
+++ b/pll/cl_u1_inv_16x.vhd
@@ -0,0 +1,11 @@
+entity cl_u1_inv_16x is
+port (
+i : in bit;
+o : out bit
+);
+end entity cl_u1_inv_16x;
+architecture arch of cl_u1_inv_16x is
+begin
+o <= not i;
+end architecture arch;
+
diff --git a/pll/cl_u1_inv_1x.vhd b/pll/cl_u1_inv_1x.vhd
new file mode 100755
index 0000000..2826714
--- /dev/null
+++ b/pll/cl_u1_inv_1x.vhd
@@ -0,0 +1,11 @@
+entity cl_u1_inv_1x is
+port (
+i : in bit;
+o : out bit
+);
+end entity cl_u1_inv_1x;
+architecture arch of cl_u1_inv_1x is
+begin
+o <= not i;
+end architecture arch;
+
diff --git a/pll/cl_u1_inv_2x.vhd b/pll/cl_u1_inv_2x.vhd
new file mode 100755
index 0000000..6f0d5cb
--- /dev/null
+++ b/pll/cl_u1_inv_2x.vhd
@@ -0,0 +1,11 @@
+entity cl_u1_inv_2x is
+port (
+i : in bit;
+o : out bit
+);
+end entity cl_u1_inv_2x;
+architecture arch of cl_u1_inv_2x is
+begin
+o <= not i;
+end architecture arch;
+
diff --git a/pll/cl_u1_inv_4x.vhd b/pll/cl_u1_inv_4x.vhd
new file mode 100755
index 0000000..dac0d5e
--- /dev/null
+++ b/pll/cl_u1_inv_4x.vhd
@@ -0,0 +1,11 @@
+entity cl_u1_inv_4x is
+port (
+i : in bit;
+o : out bit
+);
+end entity cl_u1_inv_4x;
+architecture arch of cl_u1_inv_4x is
+begin
+o <= not i;
+end architecture arch;
+
diff --git a/pll/cl_u1_inv_8x.vhd b/pll/cl_u1_inv_8x.vhd
new file mode 100755
index 0000000..6936984
--- /dev/null
+++ b/pll/cl_u1_inv_8x.vhd
@@ -0,0 +1,11 @@
+entity cl_u1_inv_8x is
+port (
+i : in bit;
+o : out bit
+);
+end entity cl_u1_inv_8x;
+architecture arch of cl_u1_inv_8x is
+begin
+o <= not i;
+end architecture arch;
+
diff --git a/pll/cl_u1_nand2_1x.vhd b/pll/cl_u1_nand2_1x.vhd
new file mode 100755
index 0000000..99662d8
--- /dev/null
+++ b/pll/cl_u1_nand2_1x.vhd
@@ -0,0 +1,12 @@
+entity cl_u1_nand2_1x is
+port (
+in0 : in bit;
+in1 : in bit;
+o : out bit
+);
+end entity cl_u1_nand2_1x;
+architecture arch of cl_u1_nand2_1x is
+begin
+o <= not (in0 and in1);
+end architecture arch;
+
diff --git a/pll/cl_u1_nand2_2x.vhd b/pll/cl_u1_nand2_2x.vhd
new file mode 100755
index 0000000..0f92ec1
--- /dev/null
+++ b/pll/cl_u1_nand2_2x.vhd
@@ -0,0 +1,12 @@
+entity cl_u1_nand2_2x is
+port (
+in0 : in bit;
+in1 : in bit;
+o : out bit
+);
+end entity cl_u1_nand2_2x;
+architecture arch of cl_u1_nand2_2x is
+begin
+o <= not (in0 and in1);
+end architecture arch;
+
diff --git a/pll/cl_u1_nand2_4x.vhd b/pll/cl_u1_nand2_4x.vhd
new file mode 100755
index 0000000..eca4167
--- /dev/null
+++ b/pll/cl_u1_nand2_4x.vhd
@@ -0,0 +1,12 @@
+entity cl_u1_nand2_4x is
+port (
+in0 : in bit;
+in1 : in bit;
+o : out bit
+);
+end entity cl_u1_nand2_4x;
+architecture arch of cl_u1_nand2_4x is
+begin
+o <= not (in0 and in1);
+end architecture arch;
+
diff --git a/pll/cl_u1_nand2_8x.vhd b/pll/cl_u1_nand2_8x.vhd
new file mode 100755
index 0000000..e7b5ecf
--- /dev/null
+++ b/pll/cl_u1_nand2_8x.vhd
@@ -0,0 +1,12 @@
+entity cl_u1_nand2_8x is
+port (
+in0 : in bit;
+in1 : in bit;
+o : out bit
+);
+end entity cl_u1_nand2_8x;
+architecture arch of cl_u1_nand2_8x is
+begin
+o <= not (in0 and in1);
+end architecture arch;
+
diff --git a/pll/cl_u1_nor2_2x.vhd b/pll/cl_u1_nor2_2x.vhd
new file mode 100755
index 0000000..213172c
--- /dev/null
+++ b/pll/cl_u1_nor2_2x.vhd
@@ -0,0 +1,12 @@
+entity cl_u1_nor2_2x is
+port (
+in0 : in bit;
+in1 : in bit;
+o : out bit
+);
+end entity cl_u1_nor2_2x;
+architecture arch of cl_u1_nor2_2x is
+begin
+o <= not (in0 or in1);
+end architecture arch;
+
diff --git a/pll/cl_u1_nor2_4x.vhd b/pll/cl_u1_nor2_4x.vhd
new file mode 100755
index 0000000..c234fff
--- /dev/null
+++ b/pll/cl_u1_nor2_4x.vhd
@@ -0,0 +1,12 @@
+entity cl_u1_nor2_4x is
+port (
+in0 : in bit;
+in1 : in bit;
+o : out bit
+);
+end entity cl_u1_nor2_4x;
+architecture arch of cl_u1_nor2_4x is
+begin
+o <= not (in0 or in1);
+end architecture arch;
+
diff --git a/pll/cl_u1_nor3_2x.vhd b/pll/cl_u1_nor3_2x.vhd
new file mode 100755
index 0000000..8a21bd8
--- /dev/null
+++ b/pll/cl_u1_nor3_2x.vhd
@@ -0,0 +1,13 @@
+entity cl_u1_nor3_2x is
+port (
+in0 : in bit;
+in1 : in bit;
+in2 : in bit;
+o : out bit
+);
+end entity cl_u1_nor3_2x;
+architecture arch of cl_u1_nor3_2x is
+begin
+o <= not (in0 or in1 or in2);
+end architecture arch;
+
diff --git a/pll/cl_u1_xnor2_4x.vhd b/pll/cl_u1_xnor2_4x.vhd
new file mode 100755
index 0000000..5e5617a
--- /dev/null
+++ b/pll/cl_u1_xnor2_4x.vhd
@@ -0,0 +1,12 @@
+entity cl_u1_xnor2_4x is
+port (
+in0 : in bit;
+in1 : in bit;
+o : out bit
+);
+end entity cl_u1_xnor2_4x;
+architecture arch of cl_u1_xnor2_4x is
+begin
+o <= not (in0 xor in1);
+end architecture arch;
+
diff --git a/pll/decode.vhd b/pll/decode.vhd
new file mode 100755
index 0000000..ceed10a
--- /dev/null
+++ b/pll/decode.vhd
@@ -0,0 +1,19 @@
+entity decode is
+port (
+a : in bit_vector(1 downto 0);
+d : out bit_vector(3 downto 0)
+);
+end entity decode;
+architecture arch of decode is
+begin
+p0 : process (a) is
+begin
+ case (a) is
+ when "00" => d <= "0001";
+ when "01" => d <= "0010";
+ when "10" => d <= "0100";
+ when "11" => d <= "1000";
+ end case;
+end process p0;
+end architecture arch;
+
diff --git a/pll/entity n2_core_pll_inv_1x_cust is.vhd b/pll/entity n2_core_pll_inv_1x_cust is.vhd
new file mode 100755
index 0000000..9699905
--- /dev/null
+++ b/pll/entity n2_core_pll_inv_1x_cust is.vhd
@@ -0,0 +1,13 @@
+entity n2_core_pll_inv_1x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_inv_1x_cust;
+architecture arch of n2_core_pll_inv_1x_cust is
+--vss = '0';
+begin
+o <= not i;
+end architecture arch;
+
diff --git a/pll/fadd.vhd b/pll/fadd.vhd
new file mode 100755
index 0000000..e99ce25
--- /dev/null
+++ b/pll/fadd.vhd
@@ -0,0 +1,15 @@
+entity fadd is
+port (
+cin : in bit;
+a : in bit;
+b : in bit;
+s : out bit;
+cout : out bit
+);
+end entity fadd;
+architecture arch of fadd is
+begin
+s <= cin xor a xor b;
+cout <= (cin and a) or (cin and b) or (a and b);
+end architecture arch;
+
diff --git a/pll/imaginary_timed_rst.vhd b/pll/imaginary_timed_rst.vhd
new file mode 100755
index 0000000..1b3520e
--- /dev/null
+++ b/pll/imaginary_timed_rst.vhd
@@ -0,0 +1,63 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+entity imaginary_timed_rst is
+port (
+ref : in bit;
+vco_clk : in bit;
+pll_div2 : in bit_vector(5 downto 0);
+pll_arst_l : in bit;
+timed_pll_arst_l : out bit
+);
+end entity imaginary_timed_rst;
+architecture arch of imaginary_timed_rst is
+signal t0_pll_arst_l,t1_pll_arst_l,ref_q,ref_pulse : bit;
+signal cnt : unsigned(2 downto 0);
+begin
+p0 : process (ref,pll_arst_l) is
+begin
+if (pll_arst_l = '0') then
+cnt <= (others => '0');
+elsif (ref'event and ref = '1') then
+if (cnt = "101") then
+cnt <= "101";
+else
+cnt <= cnt + "1";
+end if;
+end if;
+end process p0;
+p1 : process (vco_clk,pll_arst_l) is
+begin
+if (pll_arst_l = '0') then
+ref_q <= '0';
+ref_pulse <= '0';
+elsif (vco_clk'event and vco_clk = '0') then
+ref_q <= ref;
+ref_pulse <= not ref_q and ref;
+end if;
+end process p1;
+p2 : process (vco_clk,pll_arst_l) is
+begin
+if (pll_arst_l = '0') then
+t0_pll_arst_l <= '0';
+elsif (vco_clk'event and vco_clk = '1') then
+if (cnt /= "101") then
+t0_pll_arst_l <= '0';
+elsif (ref_pulse = '1') then
+t0_pll_arst_l <= '1';
+else
+t0_pll_arst_l <= t0_pll_arst_l;
+end if;
+end if;
+end process p2;
+p3 : process (vco_clk,pll_arst_l) is
+begin
+if (pll_arst_l = '0') then
+t1_pll_arst_l <= '0';
+elsif (vco_clk'event and vco_clk = '1') then
+t1_pll_arst_l <= t0_pll_arst_l;
+end if;
+end process p3;
+timed_pll_arst_l <= t0_pll_arst_l when pll_div2(0) = '1' else t1_pll_arst_l;
+end architecture arch;
+
diff --git a/pll/imaginary_vco_gen.vhd b/pll/imaginary_vco_gen.vhd
new file mode 100755
index 0000000..1c31797
--- /dev/null
+++ b/pll/imaginary_vco_gen.vhd
@@ -0,0 +1,47 @@
+entity imaginary_vco_gen is
+port (
+pll_arst_l : in bit;
+sysclk : in bit;
+fdbkclk : in bit;
+div : in bit_vector(5 downto 0);
+vco_out : out bit
+);
+end entity imaginary_vco_gen;
+architecture arch of imaginary_vco_gen is
+signal div_lat : bit_vector(5 downto 0);
+signal rst_lat,sysclk_gated : bit;
+signal aaa : bit;
+component pll_core is
+port (
+pll_arst_l : in bit;
+sysclk : in bit;
+fdbkclk : in bit;
+div : in bit_vector(5 downto 0);
+vco_out : out bit
+);
+end component pll_core;
+begin
+aaa <= not pll_arst_l;
+p0 : process (pll_arst_l,div) is
+begin
+ if (aaa = '1') then -- XXX not
+ div_lat <= div;
+ end if;
+end process p0;
+--p1 : process (pll_arst_l,sysclk) is
+--begin
+-- if (not sysclk) then
+-- rst_lat <= pll_arst_l;
+-- end if;
+--end process p1;
+--sysclk_gated <= rst_lat and sysclk;
+sysclk_gated <= sysclk;
+pllc : pll_core port map (
+pll_arst_l => pll_arst_l,
+sysclk => sysclk_gated,
+fdbkclk => fdbkclk,
+div => div_lat,
+vco_out => vco_out
+);
+end architecture arch;
+
diff --git a/pll/mux2.vhd b/pll/mux2.vhd
new file mode 100755
index 0000000..33277db
--- /dev/null
+++ b/pll/mux2.vhd
@@ -0,0 +1,22 @@
+entity mux2 is
+port (
+in0,in1,sel0,sel1 : in bit;
+y : out bit
+);
+end entity mux2;
+architecture arch of mux2 is
+begin
+p0 : process (sel0,sel1,in0,in1) is
+variable t : bit_vector(1 downto 0);
+begin
+t := (sel1,sel0);
+case (t) is
+ when "01" =>
+ y <= in0;
+ when "10" =>
+ y <= in1;
+ when others => null;
+end case;
+end process p0;
+end architecture arch;
+
diff --git a/pll/mux2s.vhd b/pll/mux2s.vhd
new file mode 100755
index 0000000..15ff09c
--- /dev/null
+++ b/pll/mux2s.vhd
@@ -0,0 +1,18 @@
+entity mux2s is
+generic (SIZE : integer := 1);
+port (
+dout : out bit_vector(SIZE-1 downto 0);
+in0 : in bit_vector(SIZE-1 downto 0);
+in1 : in bit_vector(SIZE-1 downto 0);
+sel0 : in bit;
+sel1 : in bit
+);
+end entity mux2s;
+architecture arch of mux2s is
+signal tdout : bit_vector(SIZE-1 downto 0);
+begin
+dout <= tdout;
+tdout <= in0 when sel0 = '1' else in1 when sel1 = '1';
+--assign dout = ( ( in0 & { SIZE { sel0 } } ) | ( in1 & { SIZE { sel1 } } ) );
+end architecture arch;
+
diff --git a/pll/mux4.vhd b/pll/mux4.vhd
new file mode 100755
index 0000000..34f2557
--- /dev/null
+++ b/pll/mux4.vhd
@@ -0,0 +1,32 @@
+entity mux4 is
+generic (SIZE : integer := 1);
+port (
+dout : out bit_vector(SIZE-1 downto 0);
+in0 : in bit_vector(SIZE-1 downto 0);
+in1 : in bit_vector(SIZE-1 downto 0);
+in2 : in bit_vector(SIZE-1 downto 0);
+in3 : in bit_vector(SIZE-1 downto 0);
+sel0 : in bit;
+sel1 : in bit;
+sel2 : in bit;
+sel3 : in bit;
+muxtst : in bit
+);
+end entity mux4;
+architecture arch of mux4 is
+signal sel : bit_vector(4 downto 0);
+begin
+sel <= (muxtst,sel3,sel2,sel1,sel0);
+p0 : process (sel,in0,in1,in2,in3) is
+begin
+ case (sel) is --XXX 0st sel is '-'
+ when "00001" => dout <= in0;
+ when "00010" => dout <= in1;
+ when "00100" => dout <= in2;
+ when "01000" => dout <= in3;
+ when "00000" => dout <= (others => '1');
+ when others => dout <= (others => '0'); --XXX X
+ end case;
+end process p0;
+end architecture arch;
+
diff --git a/pll/mux4k.vhd b/pll/mux4k.vhd
new file mode 100755
index 0000000..3309888
--- /dev/null
+++ b/pll/mux4k.vhd
@@ -0,0 +1,32 @@
+entity mux4k is
+generic (SIZE : integer := 1);
+port (
+dout : out bit_vector(SIZE-1 downto 0);
+in0 : in bit_vector(SIZE-1 downto 0);
+in1 : in bit_vector(SIZE-1 downto 0);
+in2 : in bit_vector(SIZE-1 downto 0);
+in3 : in bit_vector(SIZE-1 downto 0);
+sel0 : in bit;
+sel1 : in bit;
+sel2 : in bit;
+sel3 : in bit;
+muxtst : in bit
+);
+end entity mux4k;
+architecture arch of mux4k is
+signal sel : bit_vector(4 downto 0);
+begin
+sel <= (muxtst,sel3,sel2,sel1,sel0);
+p0 : process (sel,in0,in1,in2,in3) is
+begin
+ case (sel) is --XXX 0st sel "-"
+ when "00001" => dout <= in0;
+ when "00010" => dout <= in1;
+ when "00100" => dout <= in2;
+ when "01000" => dout <= in3;
+ when "00000" => dout <= (others => '0');
+ when others => dout <= (others => '0');
+ end case;
+end process p0;
+end architecture arch;
+
diff --git a/pll/mux8.vhd b/pll/mux8.vhd
new file mode 100755
index 0000000..3e34eb6
--- /dev/null
+++ b/pll/mux8.vhd
@@ -0,0 +1,43 @@
+entity mux8 is
+generic (SIZE : integer := 1);
+port (
+dout : out bit_vector(SIZE-1 downto 0);
+in0 : in bit_vector(SIZE-1 downto 0);
+in1 : in bit_vector(SIZE-1 downto 0);
+in2 : in bit_vector(SIZE-1 downto 0);
+in3 : in bit_vector(SIZE-1 downto 0);
+in4 : in bit_vector(SIZE-1 downto 0);
+in5 : in bit_vector(SIZE-1 downto 0);
+in6 : in bit_vector(SIZE-1 downto 0);
+in7 : in bit_vector(SIZE-1 downto 0);
+sel0 : in bit;
+sel1 : in bit;
+sel2 : in bit;
+sel3 : in bit;
+sel4 : in bit;
+sel5 : in bit;
+sel6 : in bit;
+sel7 : in bit;
+muxtst : in bit
+);
+end entity mux8;
+architecture arch of mux8 is
+signal sel : bit_vector(8 downto 0);
+begin
+sel <= (muxtst,sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0);
+p0 : process (sel,in0,in1,in2,in3,in4,in5,in6,in7) is
+begin
+ case (sel) is --XXX sel 1st '-'
+ when "000000001" => dout <= in0;
+ when "000000010" => dout <= in1;
+ when "000000100" => dout <= in2;
+ when "000001000" => dout <= in3;
+ when "000010000" => dout <= in4;
+ when "000100000" => dout <= in5;
+ when "001000000" => dout <= in6;
+ when "010000000" => dout <= in7;
+ when "000000000" => dout <= (others => '1');
+ when others => dout <= (others => '0'); --XXX X
+ end case;
+end process p0;
+end architecture arch;
diff --git a/pll/n2_core_pll_4bit_counter_charc_cust.vhd b/pll/n2_core_pll_4bit_counter_charc_cust.vhd
new file mode 100755
index 0000000..976f6f6
--- /dev/null
+++ b/pll/n2_core_pll_4bit_counter_charc_cust.vhd
@@ -0,0 +1,206 @@
+entity n2_core_pll_4bit_counter_charc_cust is
+port (
+clk : in bit;
+reset : in bit;
+cnt3 : in bit;
+qout_0 : out bit;
+qout_1 : out bit;
+qout_2 : out bit;
+qout_3 : out bit;
+count_out : out bit;
+cnt1 : in bit;
+cnt2 : in bit;
+cnt0 : in bit
+);
+end entity n2_core_pll_4bit_counter_charc_cust;
+architecture arch of n2_core_pll_4bit_counter_charc_cust is
+--supply1 vdd;
+--vss = '0';
+signal vdd,vss : bit;
+signal net115,net88,net121,net127,sel,net133,nand_out,zero_0,zero_1,zero_2,zero_3,sel_b,din_0,din_1,din_2,din_3,next_0,next_1,next_2,next_3 : bit;
+component n2_core_pll_flop_reset_new_cust is
+port (
+vdd_reg : in bit;
+reset_val_l : in bit;
+d : in bit;
+reset : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end component n2_core_pll_flop_reset_new_cust;
+component n2_core_pll_tpm_muxa_cust is
+port (
+opb : out bit;
+op : out bit;
+d0 : in bit;
+d1 : in bit;
+sel : in bit;
+sel_b : in bit
+);
+end component n2_core_pll_tpm_muxa_cust;
+component n2_core_pll_inv_8x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_8x_cust;
+component n2_core_pll_buf_8x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_buf_8x_cust;
+component n2_core_pll_inv_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_4x_cust;
+component n2_core_pll_nand4_4x_cust is
+port (
+in3 : in bit;
+o : out bit;
+in2 : in bit;
+in1 : in bit;
+in0 : in bit
+);
+end component n2_core_pll_nand4_4x_cust;
+component n2_core_pll_4bit_counter_next_cust is
+port (
+q3 : in bit;
+q0b : in bit;
+q3b : in bit;
+d3 : out bit;
+q1b : in bit;
+q2b : in bit;
+d2 : out bit;
+d0 : out bit;
+q2 : in bit;
+q0 : in bit;
+q1 : in bit;
+d1 : out bit
+);
+end component n2_core_pll_4bit_counter_next_cust;
+signal tqout_0,tqout_1,tqout_2,tqout_3 : bit;
+begin
+vdd <= '1';
+vss <= '0';
+qout_0 <= tqout_0;
+qout_1 <= tqout_1;
+qout_2 <= tqout_2;
+qout_3 <= tqout_3;
+x2 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vss,
+d => din_1,
+reset => reset,
+clk => clk,
+q_l => tqout_1,
+q => zero_1
+);
+x3 : n2_core_pll_tpm_muxa_cust port map (
+opb => net127,
+op => din_0,
+d0 => next_0,
+d1 => cnt0,
+sel => sel,
+sel_b => sel_b
+);
+x4 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vss,
+d => din_2,
+reset => reset,
+clk => clk,
+q_l => tqout_2,
+q => zero_2
+);
+x5 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vss,
+d => din_3,
+reset => reset,
+clk => clk,
+q_l => tqout_3,
+q => zero_3
+);
+x6 : n2_core_pll_tpm_muxa_cust port map (
+opb => net133,
+op => din_1,
+d0 => next_1,
+d1 => cnt1,
+sel => sel,
+sel_b => sel_b
+);
+x7 : n2_core_pll_tpm_muxa_cust port map (
+opb => net121,
+op => din_2,
+d0 => next_2,
+d1 => cnt2,
+sel => sel,
+sel_b => sel_b
+);
+x8 : n2_core_pll_tpm_muxa_cust port map (
+opb => net115,
+op => din_3,
+d0 => next_3,
+d1 => cnt3,
+sel => sel,
+sel_b => sel_b
+);
+x13 : n2_core_pll_inv_8x_cust port map (
+vdd_reg => vdd,
+o => sel,
+i => nand_out
+);
+x14 : n2_core_pll_inv_8x_cust port map (
+vdd_reg => vdd,
+o => sel_b,
+i => net88
+);
+x15 : n2_core_pll_buf_8x_cust port map (
+vdd_reg => vdd,
+o => count_out,
+i => nand_out
+);
+x16 : n2_core_pll_inv_4x_cust port map (
+vdd_reg => vdd,
+o => net88,
+i => nand_out
+);
+x18 : n2_core_pll_nand4_4x_cust port map (
+in3 => tqout_3,
+o => nand_out,
+in2 => tqout_2,
+in1 => tqout_1,
+in0 => tqout_0
+);
+x0 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vss,
+d => din_0,
+reset => reset,
+clk => clk,
+q_l => tqout_0,
+q => zero_0
+);
+x1 : n2_core_pll_4bit_counter_next_cust port map (
+q3 => zero_3,
+q0b => tqout_0,
+q3b => tqout_3,
+d3 => next_3,
+q1b => tqout_1,
+q2b => tqout_2,
+d2 => next_2,
+d0 => next_0,
+q2 => zero_2,
+q0 => zero_0,
+q1 => zero_1,
+d1 => next_1
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_4bit_counter_next_cust.vhd b/pll/n2_core_pll_4bit_counter_next_cust.vhd
new file mode 100755
index 0000000..9a3ac9f
--- /dev/null
+++ b/pll/n2_core_pll_4bit_counter_next_cust.vhd
@@ -0,0 +1,82 @@
+entity n2_core_pll_4bit_counter_next_cust is
+port (
+q3 : in bit;
+q0b : in bit;
+q3b : in bit;
+d3 : out bit;
+q1b : in bit;
+q2b : in bit;
+d2 : out bit;
+d0 : out bit;
+q2 : in bit;
+q0 : in bit;
+q1 : in bit;
+d1 : out bit
+);
+end entity n2_core_pll_4bit_counter_next_cust;
+architecture arch of n2_core_pll_4bit_counter_next_cust is
+--supply1 vdd;
+signal vdd : bit;
+signal net31,net34,net53 : bit;
+component cl_u1_xnor2_4x is
+port (
+in0 : in bit;
+in1 : in bit;
+o : out bit
+);
+end component cl_u1_xnor2_4x;
+component cl_u1_nor2_2x is
+port (
+in0 : in bit;
+in1 : in bit;
+o : out bit
+);
+end component cl_u1_nor2_2x;
+component cl_u1_nor3_2x is
+port (
+in0 : in bit;
+in1 : in bit;
+in2 : in bit;
+o : out bit
+);
+end component cl_u1_nor3_2x;
+begin
+vdd <= '1';
+x2 : cl_u1_xnor2_4x port map (
+o => d2,
+in0 => q2b,
+in1 => net34
+);
+x3 : cl_u1_xnor2_4x port map (
+o => d3,
+in0 => q3b,
+in1 => net53
+);
+x4 : cl_u1_nor2_2x port map (
+o => net31,
+in1 => vdd,
+in0 => q3
+);
+xi45 : cl_u1_nor2_2x port map (
+o => net34,
+in1 => q0,
+in0 => q1
+);
+xi46 : cl_u1_nor3_2x port map (
+o => net53,
+in2 => q0,
+in1 => q1,
+in0 => q2
+);
+x0 : cl_u1_xnor2_4x port map (
+o => d0,
+in0 => q0b,
+in1 => vdd
+);
+x1 : cl_u1_xnor2_4x port map (
+o => d1,
+in0 => q1b,
+in1 => q0b
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_and2_16x_cust.vhd b/pll/n2_core_pll_and2_16x_cust.vhd
new file mode 100755
index 0000000..da6c6dc
--- /dev/null
+++ b/pll/n2_core_pll_and2_16x_cust.vhd
@@ -0,0 +1,13 @@
+entity n2_core_pll_and2_16x_cust is
+port (
+o : out bit;
+in1,in0 : in bit
+);
+end entity n2_core_pll_and2_16x_cust;
+architecture arch of n2_core_pll_and2_16x_cust is
+--supply1 vdd;
+--vss = '0';
+begin
+o <= in0 and in1;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_and3_16x_cust.vhd b/pll/n2_core_pll_and3_16x_cust.vhd
new file mode 100755
index 0000000..8d0d4f2
--- /dev/null
+++ b/pll/n2_core_pll_and3_16x_cust.vhd
@@ -0,0 +1,15 @@
+entity n2_core_pll_and3_16x_cust is
+port (
+o : out bit;
+in2 : in bit;
+in1 : in bit;
+in0 : in bit
+);
+end entity n2_core_pll_and3_16x_cust;
+architecture arch of n2_core_pll_and3_16x_cust is
+--supply1 vdd;
+--vss = '0';
+begin
+o <= (in0 and in1 and in2);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_buf_16x_cust.vhd b/pll/n2_core_pll_buf_16x_cust.vhd
new file mode 100755
index 0000000..e818e1b
--- /dev/null
+++ b/pll/n2_core_pll_buf_16x_cust.vhd
@@ -0,0 +1,13 @@
+entity n2_core_pll_buf_16x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_buf_16x_cust;
+architecture arch of n2_core_pll_buf_16x_cust is
+--vss = '0';
+begin
+o <= i;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_buf_2x_cust.vhd b/pll/n2_core_pll_buf_2x_cust.vhd
new file mode 100755
index 0000000..a3b9bd0
--- /dev/null
+++ b/pll/n2_core_pll_buf_2x_cust.vhd
@@ -0,0 +1,21 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VComponents.all;
+entity n2_core_pll_buf_2x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_buf_2x_cust;
+architecture arch of n2_core_pll_buf_2x_cust is
+--vss = '0';
+signal tti : std_logic_vector(0 downto 0);
+signal tto : std_logic;
+begin
+tti(0) <= to_stdulogic(i);
+b : BUF port map (O=>tto,I=>tti(0));
+o <= to_bit(tto);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_buf_4x_cust.vhd b/pll/n2_core_pll_buf_4x_cust.vhd
new file mode 100755
index 0000000..f09ad79
--- /dev/null
+++ b/pll/n2_core_pll_buf_4x_cust.vhd
@@ -0,0 +1,13 @@
+entity n2_core_pll_buf_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_buf_4x_cust;
+architecture arch of n2_core_pll_buf_4x_cust is
+--vss = '0';
+begin
+o <= i;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_buf_8x_cust.vhd b/pll/n2_core_pll_buf_8x_cust.vhd
new file mode 100755
index 0000000..ad6adf4
--- /dev/null
+++ b/pll/n2_core_pll_buf_8x_cust.vhd
@@ -0,0 +1,13 @@
+entity n2_core_pll_buf_8x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_buf_8x_cust;
+architecture arch of n2_core_pll_buf_8x_cust is
+--vss = '0';
+begin
+o <= i;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_bufi_4x_cust.vhd b/pll/n2_core_pll_bufi_4x_cust.vhd
new file mode 100755
index 0000000..e77ff21
--- /dev/null
+++ b/pll/n2_core_pll_bufi_4x_cust.vhd
@@ -0,0 +1,21 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VComponents.all;
+entity n2_core_pll_bufi_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_bufi_4x_cust;
+architecture arch of n2_core_pll_bufi_4x_cust is
+--vss = '0';
+signal tti : std_logic_vector(0 downto 0);
+signal tto : std_logic;
+begin
+tti(0) <= to_stdulogic(i);
+bufinst : BUF port map (O => tto,I => tti(0));
+o <= to_bit(tto);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_byp_enb_cust.vhd b/pll/n2_core_pll_byp_enb_cust.vhd
new file mode 100755
index 0000000..a0cb480
--- /dev/null
+++ b/pll/n2_core_pll_byp_enb_cust.vhd
@@ -0,0 +1,56 @@
+entity n2_core_pll_byp_enb_cust is
+port (
+sel1 : in bit;
+in1 : in bit;
+out1 : out bit;
+out0 : out bit;
+in0 : in bit;
+sel0 : in bit
+);
+end entity n2_core_pll_byp_enb_cust;
+architecture arch of n2_core_pll_byp_enb_cust is
+--supply1 vdd;
+signal vss,vdd : bit;
+signal net11,net8 : bit;
+component n2_core_pll_inv_8x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_8x_cust;
+component n2_core_pll_nand2_2x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in1 : in bit;
+in0 : in bit
+);
+end component n2_core_pll_nand2_2x_cust;
+begin
+vdd <= '1';
+vss <= '0';
+x4 : n2_core_pll_inv_8x_cust port map (
+vdd_reg => vdd,
+o => out1,
+i => net8
+);
+x8 : n2_core_pll_nand2_2x_cust port map (
+vdd_reg => vdd,
+o => net11,
+in1 => sel0,
+in0 => in0
+);
+x10 : n2_core_pll_nand2_2x_cust port map (
+vdd_reg => vdd,
+o => net8,
+in1 => sel1,
+in0 => in1
+);
+x11 : n2_core_pll_inv_8x_cust port map (
+vdd_reg => vdd,
+o => out0,
+i => net11
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_charc_cust.vhd b/pll/n2_core_pll_charc_cust.vhd
new file mode 100755
index 0000000..6cc7963
--- /dev/null
+++ b/pll/n2_core_pll_charc_cust.vhd
@@ -0,0 +1,467 @@
+entity n2_core_pll_charc_cust is
+port (
+arst_l : in bit;
+ccu_rst_ref_buf2_l : out bit;
+testmode : in bit;
+dr_clk_out : in bit;
+ccu_rst_sys_clk : out bit;
+lock : in bit;
+pll_charc_out : out bit_vector(1 downto 0);
+fb_clk_l : in bit;
+pll_charc_in : in bit;
+ref_clk_l : in bit;
+fast : in bit;
+slow : in bit;
+ref : in bit;
+fb : in bit;
+vco_clk : in bit;
+l1clk : in bit
+);
+end entity n2_core_pll_charc_cust;
+architecture arch of n2_core_pll_charc_cust is
+--supply1 vdd;
+signal vdd,vss : bit;
+signal aoa1a2 : bit_vector(7 downto 0);
+signal mxin : bit_vector(9 downto 0);
+signal a3a4 : bit_vector(3 downto 0);
+signal ta5 : bit_vector(1 downto 0);
+signal mxbuf : bit_vector(9 downto 0);
+signal out_bot,mux_out1,mux_out2,net76,net77,clk_fall1,clk_fall2,clk_fall3,clk_fall4,
+net224,out_top,net227,net238,reset,net0232,a5,a0,l1clk_vcoclk,a1,a2,a3,net251,a4,net252,
+a6_0,out_cnt1,a6,a6_1,a7,l1clk_vcoclk_l,net169,clk_rise1,clk_rise2,clk_rise3,clk_rise4,
+net174,l1clk_vco_clk,l1clk_vcoclk_div4 : bit;
+component n2_core_pll_div4_new_cust is
+port (
+clk : in bit;
+arst_l : in bit;
+clk_div_out : out bit
+);
+end component n2_core_pll_div4_new_cust;
+component n2_core_pll_charc_decoder_cust is
+port (
+a5_out : out bit_vector(1 downto 0);
+a6_out : out bit_vector(1 downto 0);
+a6 : in bit;
+a5 : in bit;
+a3a4 : out bit_vector(3 downto 0);
+a4 : in bit;
+a3 : in bit;
+aoa1a2 : out bit_vector(7 downto 0);
+a2 : in bit;
+a1 : in bit;
+a0 : in bit
+);
+end component n2_core_pll_charc_decoder_cust;
+component n2_core_pll_mux8_8x_cust is
+port (
+sel0 : in bit;
+in2 : in bit;
+sel2 : in bit;
+sel5 : in bit;
+in4 : in bit;
+sel7 : in bit;
+sel4 : in bit;
+in1 : in bit;
+dout : out bit;
+in0 : in bit;
+sel6 : in bit;
+in5 : in bit;
+in7 : in bit;
+sel3 : in bit;
+sel1 : in bit;
+in3 : in bit;
+in6 : in bit
+);
+end component n2_core_pll_mux8_8x_cust;
+component n2_core_pll_mux2_8x_cust is
+port (
+in0 : in bit;
+sel0 : in bit;
+dout : out bit;
+sel1 : in bit;
+in1 : in bit
+);
+end component n2_core_pll_mux2_8x_cust;
+component n2_core_pll_buf_16x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_buf_16x_cust;
+component n2_core_pll_4bit_counter_charc_cust is
+port (
+clk : in bit;
+reset : in bit;
+cnt3 : in bit;
+qout_0 : out bit;
+qout_1 : out bit;
+qout_2 : out bit;
+qout_3 : out bit;
+count_out : out bit;
+cnt1 : in bit;
+cnt2 : in bit;
+cnt0 : in bit
+);
+end component n2_core_pll_4bit_counter_charc_cust;
+component n2_core_pll_charc_flops_cust is
+port (
+data_in : in bit;
+clk : in bit;
+clk_l : in bit;
+clk_rise1 : out bit;
+clk_fall1 : out bit;
+clk_rise2 : out bit;
+clk_fall2 : out bit;
+reset : in bit;
+clk_rise4 : out bit;
+clk_rise3 : out bit;
+clk_fall3 : out bit;
+clk_fall4 : out bit
+);
+end component n2_core_pll_charc_flops_cust;
+component n2_core_pll_charc_mux_cust is
+port (
+clk_fall2 : in bit;
+clk_fall3 : in bit;
+clk_fall4 : in bit;
+clk_fall1 : in bit;
+clk_rise3 : in bit;
+clk_rise2 : in bit;
+clk_rise4 : in bit;
+clk_rise1 : in bit;
+mux_out1 : out bit;
+mux_out2 : out bit;
+a3a4 : in bit_vector(3 downto 0);
+aoa1a2 : in bit_vector(7 downto 0)
+);
+end component n2_core_pll_charc_mux_cust;
+component n2_core_pll_inv_16x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_16x_cust;
+component n2_core_pll_inv_32x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_32x_cust;
+component n2_core_pll_inv_2x_cust is
+port(
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_2x_cust;
+component n2_core_pll_flop_reset_new_cust is
+port (
+vdd_reg : in bit;
+reset_val_l : in bit;
+d : in bit;
+reset : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end component n2_core_pll_flop_reset_new_cust;
+
+signal ta6 : bit_vector(1 downto 0);
+begin
+vdd <= '1';
+vss <= '0';
+(a6_1,a6_0) <= ta6;
+x2 : n2_core_pll_div4_new_cust port map (
+clk => l1clk_vcoclk,
+arst_l => testmode,
+clk_div_out => l1clk_vcoclk_div4
+);
+x3 : n2_core_pll_charc_decoder_cust port map (
+a5_out => ta5,
+a6_out => ta6,
+a3a4 => a3a4,
+aoa1a2 => aoa1a2,
+a6 => a6,
+a5 => a5,
+a4 => a4,
+a3 => a3,
+a2 => a2,
+a1 => a1,
+a0 => a0
+);
+x4 : n2_core_pll_mux8_8x_cust port map (
+sel0 => aoa1a2(0),
+in2 => mxin(2),
+sel2 => aoa1a2(2),
+sel5 => aoa1a2(5),
+in4 => mxin(4),
+sel7 => aoa1a2(7),
+sel4 => aoa1a2(4),
+in1 => mxin(9),
+dout => out_bot,
+in0 => mxin(0),
+sel6 => aoa1a2(6),
+in5 => mxin(5),
+in7 => mxin(7),
+sel3 => aoa1a2(3),
+sel1 => aoa1a2(1),
+in3 => mxin(3),
+in6 => mxin(6)
+);
+x5 : n2_core_pll_mux2_8x_cust port map (
+in0 => mxin(8),
+sel0 => ta5(0),
+dout => l1clk_vcoclk,
+sel1 => ta5(1),
+in1 => mxin(1)
+);
+x6 : n2_core_pll_mux2_8x_cust port map (
+in0 => out_bot,
+sel0 => a6_0,
+dout => net169,
+sel1 => a6_1,
+in1 => mux_out2
+);
+x7 : n2_core_pll_mux2_8x_cust port map (
+in0 => out_top,
+sel0 => a6_0,
+dout => net174,
+sel1 => a6_1,
+in1 => mux_out1
+);
+x42_7 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => mxbuf(9),
+i => mxin(9)
+);
+x44_3 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => mxin(3),
+i => ref_clk_l
+);
+x42_0 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => mxbuf(0),
+i => mxin(0)
+);
+x44_4 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => mxin(4),
+i => fb
+);
+x12 : n2_core_pll_4bit_counter_charc_cust port map (
+clk => out_cnt1,
+reset => net77,
+cnt3 => vdd,
+qout_0 => a4,
+qout_1 => a5,
+qout_2 => a6,
+qout_3 => a7,
+count_out => net252,
+cnt1 => vdd,
+cnt2 => vdd,
+cnt0 => vdd
+);
+x15 : n2_core_pll_4bit_counter_charc_cust port map (
+clk => pll_charc_in,
+reset => net77,
+cnt3 => vdd,
+qout_0 => a0,
+qout_1 => a1,
+qout_2 => a2,
+qout_3 => a3,
+count_out => out_cnt1,
+cnt1 => vdd,
+cnt2 => vdd,
+cnt0 => vdd
+);
+x16 : n2_core_pll_charc_flops_cust port map (
+data_in => net238,
+clk => l1clk_vco_clk,
+clk_l => l1clk_vcoclk_l,
+clk_rise1 => clk_rise1,
+clk_fall1 => clk_fall1,
+clk_rise2 => clk_rise2,
+clk_fall2 => clk_fall2,
+reset => net77,
+clk_rise4 => clk_rise4,
+clk_rise3 => clk_rise3,
+clk_fall3 => clk_fall3,
+clk_fall4 => clk_fall4
+);
+x17 : n2_core_pll_charc_mux_cust port map (
+a3a4 => a3a4,
+aoa1a2 => aoa1a2,
+clk_fall2 => clk_fall2,
+clk_fall3 => clk_fall3,
+clk_fall4 => clk_fall4,
+clk_fall1 => clk_fall1,
+clk_rise3 => clk_rise3,
+clk_rise2 => clk_rise2,
+clk_rise4 => clk_rise4,
+clk_rise1 => clk_rise1,
+mux_out1 => mux_out1,
+mux_out2 => mux_out2
+);
+x42_1 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => mxbuf(1),
+i => mxin(1)
+);
+x44_5 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => mxin(5),
+i => ref
+);
+x42_2 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => mxbuf(2),
+i => mxin(2)
+);
+x44_6 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => mxin(6),
+i => slow
+);
+x34 : n2_core_pll_inv_16x_cust port map (
+vdd_reg => vdd,
+o => l1clk_vcoclk_l,
+i => l1clk_vcoclk
+);
+x35 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => l1clk_vco_clk,
+i => l1clk_vcoclk
+);
+x36 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => net238,
+i => net76
+);
+x37 : n2_core_pll_inv_16x_cust port map (
+vdd_reg => vdd,
+o => net224,
+i => net174
+);
+x38 : n2_core_pll_inv_16x_cust port map (
+vdd_reg => vdd,
+o => net227,
+i => net169
+);
+x39 : n2_core_pll_inv_32x_cust port map (
+vdd_reg => vdd,
+o => pll_charc_out(1),
+i => net224
+);
+x42_3 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => mxbuf(4),
+i => mxin(4)
+);
+x44_7 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => mxin(7),
+i => fast
+);
+x40 : n2_core_pll_inv_32x_cust port map (
+vdd_reg => vdd,
+o => pll_charc_out(0),
+i => net227
+);
+x41 : n2_core_pll_inv_2x_cust port map (
+vdd_reg => vdd,
+o => reset,
+i => arst_l
+);
+x43 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => net77,
+i => reset
+);
+x46 : n2_core_pll_inv_32x_cust port map (
+vdd_reg => vdd,
+o => ccu_rst_ref_buf2_l,
+i => mxin(5)
+);
+x47 : n2_core_pll_inv_32x_cust port map (
+vdd_reg => vdd,
+o => ccu_rst_sys_clk,
+i => net0232
+);
+x48 : n2_core_pll_inv_16x_cust port map (
+vdd_reg => vdd,
+o => net0232,
+i => mxin(3)
+);
+x42_4 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => mxbuf(6),
+i => mxin(6)
+);
+x44_0 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => mxin(0),
+i => lock
+);
+x44_8 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => mxin(8),
+i => l1clk
+);
+x42_5 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => mxbuf(7),
+i => mxin(7)
+);
+x44_1 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => mxin(1),
+i => vco_clk
+);
+x44_9 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => mxin(9),
+i => dr_clk_out
+);
+x42_6 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => mxbuf(8),
+i => mxin(8)
+);
+x44_2 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => mxin(2),
+i => fb_clk_l
+);
+x0 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => l1clk_vcoclk_div4,
+reset => net77,
+clk => l1clk_vcoclk_l,
+q_l => net251,
+q => net76
+);
+x1 : n2_core_pll_mux8_8x_cust port map (
+sel0 => aoa1a2(0),
+in2 => mxin(3),
+sel2 => aoa1a2(2),
+sel5 => aoa1a2(5),
+in4 => mxin(5),
+sel7 => aoa1a2(7),
+sel4 => aoa1a2(4),
+in1 => mxin(1),
+dout => out_top,
+in0 => mxin(1),
+sel6 => aoa1a2(6),
+in5 => mxin(4),
+in7 => mxin(6),
+sel3 => aoa1a2(3),
+sel1 => aoa1a2(1),
+in3 => mxin(2),
+in6 => mxin(7)
+);
+end architecture arch;
diff --git a/pll/n2_core_pll_charc_decoder_cust.vhd b/pll/n2_core_pll_charc_decoder_cust.vhd
new file mode 100755
index 0000000..e58ae6f
--- /dev/null
+++ b/pll/n2_core_pll_charc_decoder_cust.vhd
@@ -0,0 +1,225 @@
+entity n2_core_pll_charc_decoder_cust is
+port (
+a5_out : out bit_vector(1 downto 0);
+a6_out : out bit_vector(1 downto 0);
+a6 : in bit;
+a5 : in bit;
+a3a4 : out bit_vector(3 downto 0);
+a4 : in bit;
+a3 : in bit;
+aoa1a2 : out bit_vector(7 downto 0);
+a2 : in bit;
+a1 : in bit;
+a0 : in bit
+);
+end entity n2_core_pll_charc_decoder_cust;
+architecture arch of n2_core_pll_charc_decoder_cust is
+--supply1 vdd;
+signal vdd : bit;
+signal net188,net191,net194,net197,a0_buf,a1_buf,a2_buf,a3_buf,
+a4_buf,net144,net153,a0_inv,a1_inv,a2_inv,a3_inv,a4_inv,net179 : bit;
+component n2_core_pll_and3_16x_cust is
+port (
+o : out bit;
+in2 : in bit;
+in1 : in bit;
+in0 : in bit
+);
+end component n2_core_pll_and3_16x_cust;
+component n2_core_pll_inv_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_4x_cust;
+component n2_core_pll_buf_16x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_buf_16x_cust;
+component n2_core_pll_and2_16x_cust is
+port (
+o : out bit;
+in1,in0 : in bit
+);
+end component n2_core_pll_and2_16x_cust;
+begin
+vdd <= '1';
+x2 : n2_core_pll_and3_16x_cust port map (
+o => aoa1a2(2),
+in2 => a0_inv,
+in1 => a1_buf,
+in0 => a2_inv
+);
+x3 : n2_core_pll_and3_16x_cust port map (
+o => aoa1a2(3),
+in2 => a0_buf,
+in1 => a1_buf,
+in0 => a2_inv
+);
+x4 : n2_core_pll_inv_4x_cust port map (
+vdd_reg => vdd,
+o => net197,
+i => a0
+);
+x5 : n2_core_pll_inv_4x_cust port map (
+vdd_reg => vdd,
+o => net188,
+i => a3
+);
+x6 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => a2_buf,
+i => a2
+);
+x7 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => a3_buf,
+i => a3
+);
+x8 : n2_core_pll_and3_16x_cust port map (
+o => aoa1a2(4),
+in2 => a0_inv,
+in1 => a1_inv,
+in0 => a2_buf
+);
+x9 : n2_core_pll_and3_16x_cust port map (
+o => aoa1a2(5),
+in2 => a0_buf,
+in1 => a1_inv,
+in0 => a2_buf
+);
+x10 : n2_core_pll_and3_16x_cust port map (
+o => aoa1a2(6),
+in2 => a0_inv,
+in1 => a1_buf,
+in0 => a2_buf
+);
+x11 : n2_core_pll_and3_16x_cust port map (
+o => aoa1a2(7),
+in2 => a0_buf,
+in1 => a1_buf,
+in0 => a2_buf
+);
+x12 : n2_core_pll_and2_16x_cust port map (
+o => a3a4(0),
+in1 => a3_inv,
+in0 => a4_inv
+);
+x13 : n2_core_pll_and2_16x_cust port map (
+o => a3a4(1),
+in1 => a3_buf,
+in0 => a4_inv
+);
+x14 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => a1_buf,
+i => a1
+);
+x15 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => a0_buf,
+i => a0
+);
+x16 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => a2_inv,
+i => net191
+);
+x17 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => a1_inv,
+i => net194
+);
+x18 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => a0_inv,
+i => net197
+);
+x19 : n2_core_pll_inv_4x_cust port map (
+vdd_reg => vdd,
+o => net194,
+i => a1
+);
+x20 : n2_core_pll_inv_4x_cust port map (
+vdd_reg => vdd,
+o => net191,
+i => a2
+);
+x21 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => a4_buf,
+i => a4
+);
+x22 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => a4_inv,
+i => net153
+);
+x23 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => a3_inv,
+i => net188
+);
+x24 : n2_core_pll_inv_4x_cust port map (
+vdd_reg => vdd,
+o => net153,
+i => a4
+);
+x25 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => a5_out(0),
+i => net179
+);
+x26 : n2_core_pll_and2_16x_cust port map (
+o => a3a4(2),
+in1 => a3_inv,
+in0 => a4_buf
+);
+x27 : n2_core_pll_and2_16x_cust port map (
+o => a3a4(3),
+in1 => a3_buf,
+in0 => a4_buf
+);
+x28 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => a6_out(0),
+i => net144
+);
+x39 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => a6_out(1),
+i => a6
+);
+x40 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => a5_out(1),
+i => a5
+);
+x41 : n2_core_pll_inv_4x_cust port map (
+vdd_reg => vdd,
+o => net144,
+i => a6
+);
+x42 : n2_core_pll_inv_4x_cust port map (
+vdd_reg => vdd,
+o => net179,
+i => a5
+);
+x0 : n2_core_pll_and3_16x_cust port map (
+o => aoa1a2(0),
+in2 => a0_inv,
+in1 => a1_inv,
+in0 => a2_inv
+);
+x1 : n2_core_pll_and3_16x_cust port map (
+o => aoa1a2(1),
+in2 => a0_buf,
+in1 => a1_inv,
+in0 => a2_inv
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_charc_flops_cust.vhd b/pll/n2_core_pll_charc_flops_cust.vhd
new file mode 100755
index 0000000..4171c40
--- /dev/null
+++ b/pll/n2_core_pll_charc_flops_cust.vhd
@@ -0,0 +1,305 @@
+entity n2_core_pll_charc_flops_cust is
+port (
+data_in : in bit;
+clk : in bit;
+clk_l : in bit;
+clk_rise1 : out bit;
+clk_fall1 : out bit;
+clk_rise2 : out bit;
+clk_fall2 : out bit;
+reset : in bit;
+clk_rise4 : out bit;
+clk_rise3 : out bit;
+clk_fall3 : out bit;
+clk_fall4 : out bit
+);
+end entity n2_core_pll_charc_flops_cust;
+architecture arch of n2_core_pll_charc_flops_cust is
+--supply1 vdd;
+signal vdd : bit;
+signal net200,net107,net205,net092,net191,net094,net193,net0186,net213,net116,net214,net88,net221,net227,net229,net130,net231,net233,net137,net235,net237,net239,net142,net241,net243,net245,net247,net149,net249,net151,net255,net256,net158,net257,net0193,net165,net265,net267,net268,net170,net172,net270,net177,net179,net100 : bit;
+component n2_core_pll_flop_reset_new_1x_cust is
+port (
+vdd_reg : in bit;
+reset_val_l : in bit;
+d : in bit;
+reset : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end component n2_core_pll_flop_reset_new_1x_cust;
+component n2_core_pll_bufi_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_bufi_4x_cust;
+component n2_core_pll_buf_16x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_buf_16x_cust;
+component n2_core_pll_flop_reset_new_cust is
+port (
+vdd_reg : in bit;
+reset_val_l : in bit;
+d : in bit;
+reset : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end component n2_core_pll_flop_reset_new_cust;
+begin
+vdd <= '1';
+x2 : n2_core_pll_flop_reset_new_1x_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => data_in,
+reset => net213,
+clk => clk_l,
+q_l => net172,
+q => net170
+);
+x3 : n2_core_pll_flop_reset_new_1x_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => net233,
+reset => net213,
+clk => clk_l,
+q_l => net165,
+q => net0193
+);
+x4 : n2_core_pll_flop_reset_new_1x_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => net239,
+reset => net213,
+clk => clk_l,
+q_l => net257,
+q => net142
+);
+x5 : n2_core_pll_flop_reset_new_1x_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => net249,
+reset => net213,
+clk => clk,
+q_l => net151,
+q => net149
+);
+x6 : n2_core_pll_flop_reset_new_1x_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => net231,
+reset => net213,
+clk => clk,
+q_l => net158,
+q => net0186
+);
+x7 : n2_core_pll_flop_reset_new_1x_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => data_in,
+reset => net213,
+clk => clk,
+q_l => net179,
+q => net177
+);
+x8 : n2_core_pll_flop_reset_new_1x_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => data_in,
+reset => net213,
+clk => clk,
+q_l => net267,
+q => net100
+);
+x9 : n2_core_pll_flop_reset_new_1x_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => data_in,
+reset => net213,
+clk => clk_l,
+q_l => net268,
+q => net107
+);
+x10 : n2_core_pll_flop_reset_new_1x_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => net241,
+reset => net213,
+clk => clk_l,
+q_l => net116,
+q => net094
+);
+x11 : n2_core_pll_flop_reset_new_1x_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => net245,
+reset => net213,
+clk => clk,
+q_l => net265,
+q => net092
+);
+x12 : n2_core_pll_bufi_4x_cust port map (
+vdd_reg => vdd,
+o => net245,
+i => net267
+);
+x13 : n2_core_pll_bufi_4x_cust port map (
+vdd_reg => vdd,
+o => net247,
+i => net265
+);
+x14 : n2_core_pll_bufi_4x_cust port map (
+vdd_reg => vdd,
+o => net243,
+i => net116
+);
+x15 : n2_core_pll_bufi_4x_cust port map (
+vdd_reg => vdd,
+o => net241,
+i => net268
+);
+x17 : n2_core_pll_bufi_4x_cust port map (
+vdd_reg => vdd,
+o => net229,
+i => net255
+);
+x18 : n2_core_pll_bufi_4x_cust port map (
+vdd_reg => vdd,
+o => net227,
+i => net193
+);
+x19 : n2_core_pll_bufi_4x_cust port map (
+vdd_reg => vdd,
+o => net233,
+i => net172
+);
+x20 : n2_core_pll_bufi_4x_cust port map (
+vdd_reg => vdd,
+o => net231,
+i => net179
+);
+x21 : n2_core_pll_bufi_4x_cust port map (
+vdd_reg => vdd,
+o => net249,
+i => net158
+);
+x22 : n2_core_pll_bufi_4x_cust port map (
+vdd_reg => vdd,
+o => net239,
+i => net165
+);
+x23 : n2_core_pll_bufi_4x_cust port map (
+vdd_reg => vdd,
+o => net237,
+i => net257
+);
+x24 : n2_core_pll_bufi_4x_cust port map (
+vdd_reg => vdd,
+o => net235,
+i => net151
+);
+x33 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd,
+o => net213,
+i => reset
+);
+x34 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => net227,
+reset => net213,
+clk => clk_l,
+q_l => net256,
+q => clk_fall2
+);
+x35 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => net229,
+reset => net213,
+clk => clk,
+q_l => net200,
+q => clk_rise2
+);
+x37 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => data_in,
+reset => net213,
+clk => clk_l,
+q_l => net214,
+q => clk_fall1
+);
+x38 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => data_in,
+reset => net213,
+clk => clk,
+q_l => net221,
+q => clk_rise1
+);
+x41 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => net247,
+reset => net213,
+clk => clk,
+q_l => net88,
+q => clk_rise3
+);
+x42 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => net243,
+reset => net213,
+clk => clk_l,
+q_l => net270,
+q => clk_fall3
+);
+x49 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => net237,
+reset => net213,
+clk => clk_l,
+q_l => net130,
+q => clk_fall4
+);
+x50 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => net235,
+reset => net213,
+clk => clk,
+q_l => net137,
+q => clk_rise4
+);
+x0 : n2_core_pll_flop_reset_new_1x_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => data_in,
+reset => net213,
+clk => clk,
+q_l => net255,
+q => net205
+);
+x1 : n2_core_pll_flop_reset_new_1x_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => data_in,
+reset => net213,
+clk => clk_l,
+q_l => net193,
+q => net191
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_charc_mux_cust.vhd b/pll/n2_core_pll_charc_mux_cust.vhd
new file mode 100755
index 0000000..95ba4b6
--- /dev/null
+++ b/pll/n2_core_pll_charc_mux_cust.vhd
@@ -0,0 +1,270 @@
+entity n2_core_pll_charc_mux_cust is
+port (
+clk_fall2 : in bit;
+clk_fall3 : in bit;
+clk_fall4 : in bit;
+clk_fall1 : in bit;
+clk_rise3 : in bit;
+clk_rise2 : in bit;
+clk_rise4 : in bit;
+clk_rise1 : in bit;
+mux_out1 : out bit;
+mux_out2 : out bit;
+a3a4 : in bit_vector(3 downto 0);
+aoa1a2 : in bit_vector(7 downto 0)
+);
+end entity n2_core_pll_charc_mux_cust;
+architecture arch of n2_core_pll_charc_mux_cust is
+signal mux_in,mux_in1 : bit_vector(7 downto 0);
+component n2_core_pll_mux4_8x_cust is
+port (
+sel2 : in bit;
+sel3 : in bit;
+in2 : in bit;
+in3 : in bit;
+sel0 : in bit;
+sel1 : in bit;
+dout : out bit;
+in0 : in bit;
+in1 : in bit
+);
+end component n2_core_pll_mux4_8x_cust;
+component n2_core_pll_mux8_8x_cust is
+port (
+sel0 : in bit;
+in2 : in bit;
+sel2 : in bit;
+sel5 : in bit;
+in4 : in bit;
+sel7 : in bit;
+sel4 : in bit;
+in1 : in bit;
+dout : out bit;
+in0 : in bit;
+sel6 : in bit;
+in5 : in bit;
+in7 : in bit;
+sel3 : in bit;
+sel1 : in bit;
+in3 : in bit;
+in6 : in bit
+);
+end component n2_core_pll_mux8_8x_cust;
+begin
+x18 : n2_core_pll_mux4_8x_cust port map (
+sel2 => a3a4(2),
+sel3 => a3a4(3),
+in2 => clk_fall1,
+in3 => clk_rise2,
+sel0 => a3a4(0),
+sel1 => a3a4(1),
+dout => mux_in(0),
+in0 => clk_rise1,
+in1 => clk_rise1
+);
+x19 : n2_core_pll_mux4_8x_cust port map (
+sel2 => a3a4(2),
+sel3 => a3a4(3),
+in2 => clk_rise1,
+in3 => clk_rise1,
+sel0 => a3a4(0),
+sel1 => a3a4(1),
+dout => mux_in1(0),
+in0 => clk_fall1,
+in1 => clk_rise2
+);
+x20 : n2_core_pll_mux8_8x_cust port map (
+sel0 => aoa1a2(0),
+in2 => mux_in(2),
+sel2 => aoa1a2(2),
+sel5 => aoa1a2(5),
+in4 => mux_in(4),
+sel7 => aoa1a2(7),
+sel4 => aoa1a2(4),
+in1 => mux_in(1),
+dout => mux_out1,
+in0 => mux_in(0),
+sel6 => aoa1a2(6),
+in5 => mux_in(5),
+in7 => mux_in(7),
+sel3 => aoa1a2(3),
+sel1 => aoa1a2(1),
+in3 => mux_in(3),
+in6 => mux_in(6)
+);
+x21 : n2_core_pll_mux8_8x_cust port map (
+sel0 => aoa1a2(0),
+in2 => mux_in1(2),
+sel2 => aoa1a2(2),
+sel5 => aoa1a2(5),
+in4 => mux_in1(4),
+sel7 => aoa1a2(7),
+sel4 => aoa1a2(4),
+in1 => mux_in1(1),
+dout => mux_out2,
+in0 => mux_in1(0),
+sel6 => aoa1a2(6),
+in5 => mux_in1(5),
+in7 => mux_in1(7),
+sel3 => aoa1a2(3),
+sel1 => aoa1a2(1),
+in3 => mux_in1(3),
+in6 => mux_in1(6)
+);
+x22 : n2_core_pll_mux4_8x_cust port map (
+sel2 => a3a4(2),
+sel3 => a3a4(3),
+in2 => clk_rise2,
+in3 => clk_fall2,
+sel0 => a3a4(0),
+sel1 => a3a4(1),
+dout => mux_in(1),
+in0 => clk_fall1,
+in1 => clk_fall1
+);
+x23 : n2_core_pll_mux4_8x_cust port map (
+sel2 => a3a4(2),
+sel3 => a3a4(3),
+in2 => clk_fall2,
+in3 => clk_rise3,
+sel0 => a3a4(0),
+sel1 => a3a4(1),
+dout => mux_in(2),
+in0 => clk_rise2,
+in1 => clk_rise2
+);
+x24 : n2_core_pll_mux4_8x_cust port map (
+sel2 => a3a4(2),
+sel3 => a3a4(3),
+in2 => clk_rise3,
+in3 => clk_fall3,
+sel0 => a3a4(0),
+sel1 => a3a4(1),
+dout => mux_in(3),
+in0 => clk_fall2,
+in1 => clk_fall2
+);
+x25 : n2_core_pll_mux4_8x_cust port map (
+sel2 => a3a4(2),
+sel3 => a3a4(3),
+in2 => clk_fall3,
+in3 => clk_rise4,
+sel0 => a3a4(0),
+sel1 => a3a4(1),
+dout => mux_in(4),
+in0 => clk_rise3,
+in1 => clk_rise3
+);
+x26 : n2_core_pll_mux4_8x_cust port map (
+sel2 => a3a4(2),
+sel3 => a3a4(3),
+in2 => clk_rise4,
+in3 => clk_fall4,
+sel0 => a3a4(0),
+sel1 => a3a4(1),
+dout => mux_in(5),
+in0 => clk_fall3,
+in1 => clk_fall3
+);
+x27 : n2_core_pll_mux4_8x_cust port map (
+sel2 => a3a4(2),
+sel3 => a3a4(3),
+in2 => clk_fall4,
+in3 => clk_rise1,
+sel0 => a3a4(0),
+sel1 => a3a4(1),
+dout => mux_in(6),
+in0 => clk_rise4,
+in1 => clk_rise4
+);
+x28 : n2_core_pll_mux4_8x_cust port map (
+sel2 => a3a4(2),
+sel3 => a3a4(3),
+in2 => clk_rise1,
+in3 => clk_fall1,
+sel0 => a3a4(0),
+sel1 => a3a4(1),
+dout => mux_in(7),
+in0 => clk_fall4,
+in1 => clk_fall4
+);
+x29 : n2_core_pll_mux4_8x_cust port map (
+sel2 => a3a4(2),
+sel3 => a3a4(3),
+in2 => clk_fall1,
+in3 => clk_fall1,
+sel0 => a3a4(0),
+sel1 => a3a4(1),
+dout => mux_in1(1),
+in0 => clk_rise2,
+in1 => clk_fall2
+);
+x30 : n2_core_pll_mux4_8x_cust port map (
+sel2 => a3a4(2),
+sel3 => a3a4(3),
+in2 => clk_rise2,
+in3 => clk_rise2,
+sel0 => a3a4(0),
+sel1 => a3a4(1),
+dout => mux_in1(2),
+in0 => clk_fall2,
+in1 => clk_rise3
+);
+x31 : n2_core_pll_mux4_8x_cust port map (
+sel2 => a3a4(2),
+sel3 => a3a4(3),
+in2 => clk_fall2,
+in3 => clk_fall2,
+sel0 => a3a4(0),
+sel1 => a3a4(1),
+dout => mux_in1(3),
+in0 => clk_rise3,
+in1 => clk_fall3
+);
+x32 : n2_core_pll_mux4_8x_cust port map (
+sel2 => a3a4(2),
+sel3 => a3a4(3),
+in2 => clk_rise3,
+in3 => clk_rise3,
+sel0 => a3a4(0),
+sel1 => a3a4(1),
+dout => mux_in1(4),
+in0 => clk_fall3,
+in1 => clk_rise4
+);
+x33 : n2_core_pll_mux4_8x_cust port map (
+sel2 => a3a4(2),
+sel3 => a3a4(3),
+in2 => clk_fall3,
+in3 => clk_fall3,
+sel0 => a3a4(0),
+sel1 => a3a4(1),
+dout => mux_in1(5),
+in0 => clk_rise4,
+in1 => clk_fall4
+);
+x34 : n2_core_pll_mux4_8x_cust port map (
+sel2 => a3a4(2),
+sel3 => a3a4(3),
+in2 => clk_rise4,
+in3 => clk_rise4,
+sel0 => a3a4(0),
+sel1 => a3a4(1),
+dout => mux_in1(6),
+in0 => clk_fall4,
+in1 => clk_rise1
+);
+x35 : n2_core_pll_mux4_8x_cust port map (
+sel2 => a3a4(2),
+sel3 => a3a4(3),
+in2 => clk_fall4,
+in3 => clk_fall4,
+sel0 => a3a4(0),
+sel1 => a3a4(1),
+dout => mux_in1(7),
+in0 => clk_rise1,
+in1 => clk_fall1
+);
+end architecture arch;
+
+
diff --git a/pll/n2_core_pll_ckmux_cust.vhd b/pll/n2_core_pll_ckmux_cust.vhd
new file mode 100755
index 0000000..773b028
--- /dev/null
+++ b/pll/n2_core_pll_ckmux_cust.vhd
@@ -0,0 +1,259 @@
+entity n2_core_pll_ckmux_cust is
+port (
+pll_sdel : in bit_vector(1 downto 0);
+ckt_drv_int : out bit;
+cktree_drv_l : out bit;
+ext_clk : in bit;
+dft_rst_a_l : in bit;
+dft_rst_l : out bit;
+bypass_pll_clk : in bit;
+psel1 : out bit;
+psel0 : out bit;
+stretch_a : in bit;
+async_reset : in bit;
+cktree_drv : out bit;
+pll1_clk : in bit;
+pll_sel : in bit_vector(1 downto 0);
+bypass_clk : in bit
+);
+end entity n2_core_pll_ckmux_cust;
+architecture arch of n2_core_pll_ckmux_cust is
+--supply0 vss;
+signal vss,vdd : bit;
+signal sel_n0,byp_pll_clk_l,sel_n1,net93,pll_sel0_l,byp_pll_clk,s0_l,sel0,sel1,s1_l,sel2,sel3,net069,psel0_l,psel1_l,d1_clk,net070,net071,sel_n1_l,s0,s1,sel_n0_l,sel2_l,sel3_l,net64 : bit;
+signal net069_orig,net070_orig : bit;
+component cl_u1_nand2_4x is
+port (
+in0 : in bit;
+in1 : in bit;
+o : out bit
+);
+end component cl_u1_nand2_4x;
+component cl_u1_inv_16x is
+port (
+i : in bit;
+o : out bit
+);
+end component cl_u1_inv_16x;
+component cl_u1_inv_4x is
+port (
+i : in bit;
+o : out bit
+);
+end component cl_u1_inv_4x;
+component cl_u1_inv_8x is
+port (
+i : in bit;
+o : out bit
+);
+end component cl_u1_inv_8x;
+component cl_u1_inv_1x is
+port (
+i : in bit;
+o : out bit
+);
+end component cl_u1_inv_1x;
+component n2_core_pll_flopderst_16x_cust is
+port (
+q_l : out bit;
+reset_val : in bit;
+d : in bit;
+q : out bit;
+reset : in bit;
+clk : in bit;
+ena : in bit
+);
+end component n2_core_pll_flopderst_16x_cust;
+component cl_u1_inv_2x is
+port (
+i : in bit;
+o : out bit
+);
+end component cl_u1_inv_2x;
+component n2_core_pll_ckmux_mxdel_diffout_cust is
+port (
+ckt_drv_int : out bit;
+cktree_drv : out bit;
+cktree_drv_l : out bit;
+pll1_clk : in bit;
+sel1 : in bit;
+pll2_clk : in bit;
+bypass_clk : in bit;
+sel3 : in bit;
+d1_clk : out bit; --XXX in
+pll_sdel : in bit_vector(1 downto 0);
+sel0 : in bit;
+sel2 : in bit
+);
+end component n2_core_pll_ckmux_mxdel_diffout_cust;
+component n2_core_pll_clkmux_sync_cust is
+port (
+bypass_pll_clk : in bit;
+pll_clk : in bit;
+arst : in bit;
+d1 : in bit;
+d2 : in bit;
+d1_sync : out bit;
+d2_sync : out bit;
+d0_sync : out bit;
+d0 : in bit;
+d3_sync : out bit;
+d3 : in bit
+);
+end component n2_core_pll_clkmux_sync_cust;
+component cl_u1_nand2_1x is
+port (
+in0 : in bit;
+in1 : in bit;
+o : out bit
+);
+end component cl_u1_nand2_1x;
+component n2_core_pll_inv_8x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_8x_cust;
+component n2_core_pll_nand2_2x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in1 : in bit;
+in0 : in bit
+);
+end component n2_core_pll_nand2_2x_cust;
+begin
+vdd <= '1';
+vss <= '0';
+net069 <= net069_orig after 200 ps;
+net070 <= net070_orig after 200 ps;
+x2 : cl_u1_nand2_4x port map (
+o => s1_l,
+in1 => sel_n1_l,
+in0 => sel_n0
+);
+x4 : cl_u1_inv_16x port map (
+o => sel3,
+i => sel3_l
+);
+x5 : cl_u1_inv_4x port map (
+o => s1,
+i => s1_l
+);
+x6 : cl_u1_inv_8x port map (
+o => byp_pll_clk_l,
+i => bypass_pll_clk
+);
+x7 : cl_u1_inv_1x port map (
+o => pll_sel0_l,
+i => pll_sel(0)
+);
+x8 : cl_u1_nand2_4x port map (
+o => sel2_l,
+in1 => pll_sel(1),
+in0 => pll_sel0_l
+);
+xi72 : n2_core_pll_flopderst_16x_cust port map (
+q_l => net64,
+reset_val => byp_pll_clk_l,
+d => s0,
+q => sel0,
+reset => async_reset,
+clk => d1_clk,
+ena => net071
+);
+xi74 : n2_core_pll_flopderst_16x_cust port map (
+q_l => net93,
+reset_val => vss,
+d => s1,
+q => sel1,
+reset => async_reset,
+clk => d1_clk,
+ena => net071
+);
+xi75 : n2_core_pll_flopderst_16x_cust port map (
+q_l => sel_n1_l,
+reset_val => byp_pll_clk,
+d => net069,
+q => sel_n1,
+reset => async_reset,
+clk => d1_clk,
+ena => net071
+);
+xi76 : n2_core_pll_flopderst_16x_cust port map (
+q_l => sel_n0_l,
+reset_val => byp_pll_clk,
+d => net070,
+q => sel_n0,
+reset => async_reset,
+clk => d1_clk,
+ena => net071
+);
+x10 : cl_u1_nand2_4x port map (
+o => sel3_l,
+in1 => pll_sel(1),
+in0 => pll_sel(0)
+);
+x11 : cl_u1_inv_16x port map (
+o => sel2,
+i => sel2_l
+);
+x16 : cl_u1_inv_8x port map (
+o => psel1,
+i => psel1_l
+);
+x22 : cl_u1_inv_2x port map (
+o => psel1_l,
+i => sel1
+);
+x23 : cl_u1_inv_2x port map (
+o => psel0_l,
+i => sel0
+);
+x24 : cl_u1_inv_8x port map (
+o => psel0,
+i => psel0_l
+);
+x26 : cl_u1_inv_8x port map (
+o => byp_pll_clk,
+i => byp_pll_clk_l
+);
+x27 : cl_u1_inv_4x port map (
+o => s0,
+i => s0_l
+);
+xmxdel : n2_core_pll_ckmux_mxdel_diffout_cust port map (
+pll_sdel => pll_sdel,
+ckt_drv_int => ckt_drv_int,
+cktree_drv => cktree_drv,
+cktree_drv_l => cktree_drv_l,
+pll1_clk => pll1_clk,
+sel1 => sel1,
+pll2_clk => ext_clk,
+bypass_clk => bypass_clk,
+sel3 => sel3,
+d1_clk => d1_clk,
+sel0 => sel0,
+sel2 => sel2
+);
+x0 : n2_core_pll_clkmux_sync_cust port map (
+bypass_pll_clk => bypass_pll_clk,
+pll_clk => pll1_clk,
+arst => async_reset,
+d1 => pll_sel(0),
+d2 => pll_sel(1),
+d1_sync => net070_orig,
+d2_sync => net069_orig,
+d0_sync => net071,
+d0 => stretch_a,
+d3_sync => dft_rst_l,
+d3 => dft_rst_a_l
+);
+x1 : cl_u1_nand2_1x port map (
+o => s0_l,
+in1 => sel_n1_l,
+in0 => sel_n0_l
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_ckmux_mxdel_diffout_cust.vhd b/pll/n2_core_pll_ckmux_mxdel_diffout_cust.vhd
new file mode 100755
index 0000000..0a635c5
--- /dev/null
+++ b/pll/n2_core_pll_ckmux_mxdel_diffout_cust.vhd
@@ -0,0 +1,69 @@
+entity n2_core_pll_ckmux_mxdel_diffout_cust is
+port (
+ckt_drv_int : out bit;
+cktree_drv : out bit;
+cktree_drv_l : out bit;
+pll1_clk : in bit;
+sel1 : in bit;
+pll2_clk : in bit;
+bypass_clk : in bit;
+sel3 : in bit;
+d1_clk : out bit; --XXX in
+pll_sdel : in bit_vector(1 downto 0);
+sel0 : in bit;
+sel2 : in bit
+);
+end entity n2_core_pll_ckmux_mxdel_diffout_cust;
+architecture arch of n2_core_pll_ckmux_mxdel_diffout_cust is
+--supply1 vdd;
+--vss = '0';
+component mux4k is
+generic (SIZE : integer := 1);
+port (
+dout : out bit_vector(SIZE-1 downto 0);
+in0 : in bit_vector(SIZE-1 downto 0);
+in1 : in bit_vector(SIZE-1 downto 0);
+in2 : in bit_vector(SIZE-1 downto 0);
+in3 : in bit_vector(SIZE-1 downto 0);
+sel0 : in bit;
+sel1 : in bit;
+sel2 : in bit;
+sel3 : in bit;
+muxtst : in bit
+);
+end component mux4k;
+component n2_core_pll_clkmux_delay is
+port (
+pll_sdel : in bit_vector(1 downto 0);
+mux_out : out bit;
+d : in bit
+);
+end component n2_core_pll_clkmux_delay;
+signal tin0,tin1,tin2,tin3,tcktree_drv : bit_vector(0 downto 0);
+begin
+tin0(0) <= pll1_clk;
+d1_clk <= tin1(0);
+tin2(0) <= pll2_clk;
+tin3(0) <= bypass_clk;
+cktree_drv <= tcktree_drv(0);
+x1 : mux4k port map (
+muxtst => '0',
+in0 => tin0,
+in1 => tin1,
+in2 => tin2,
+in3 => tin3,
+sel0 => sel0,
+sel1 => sel1,
+sel2 => sel2,
+sel3 => sel3,
+dout => tcktree_drv
+);
+x0 : n2_core_pll_clkmux_delay port map (
+pll_sdel => pll_sdel,
+mux_out => tin1(0),
+d => pll1_clk
+);
+cktree_drv_l <= not tcktree_drv(0);
+ckt_drv_int <= tcktree_drv(0);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_clkmux_delay.vhd b/pll/n2_core_pll_clkmux_delay.vhd
new file mode 100755
index 0000000..cabc74f
--- /dev/null
+++ b/pll/n2_core_pll_clkmux_delay.vhd
@@ -0,0 +1,57 @@
+entity n2_core_pll_clkmux_delay is
+port (
+pll_sdel : in bit_vector(1 downto 0);
+mux_out : out bit;
+d : in bit
+);
+end entity n2_core_pll_clkmux_delay;
+architecture arch of n2_core_pll_clkmux_delay is
+component decode is
+port (
+a : in bit_vector(1 downto 0);
+d : out bit_vector(3 downto 0)
+);
+end component decode;
+component mux4
+generic (SIZE : integer := 1);
+port (
+dout : out bit_vector(SIZE-1 downto 0);
+in0 : in bit_vector(SIZE-1 downto 0);
+in1 : in bit_vector(SIZE-1 downto 0);
+in2 : in bit_vector(SIZE-1 downto 0);
+in3 : in bit_vector(SIZE-1 downto 0);
+sel0 : in bit;
+sel1 : in bit;
+sel2 : in bit;
+sel3 : in bit;
+muxtst : in bit
+);
+end component mux4;
+--supply1 vdd;
+--vss = '0';
+signal sel : bit_vector(3 downto 0);
+signal d0, d1, d2, d3, tmux_out : bit_vector(0 downto 0);
+begin
+mux_out <= tmux_out(0);
+d0(0) <= d after 40 ps;
+d1(0) <= d0(0) after 40 ps;
+d2(0) <= d1(0) after 40 ps;
+d3(0) <= d2(0) after 40 ps;
+x0 : decode port map (
+a => pll_sdel(1 downto 0),
+d => sel(3 downto 0)
+);
+x1 : mux4 port map (
+muxtst => '0',
+sel0 => sel(0),
+sel1 => sel(1),
+sel2 => sel(2),
+sel3 => sel(3),
+in0 => d0,
+in1 => d1,
+in2 => d2,
+in3 => d3,
+dout => tmux_out
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_clkmux_sync_cust.vhd b/pll/n2_core_pll_clkmux_sync_cust.vhd
new file mode 100755
index 0000000..5b4e055
--- /dev/null
+++ b/pll/n2_core_pll_clkmux_sync_cust.vhd
@@ -0,0 +1,234 @@
+entity n2_core_pll_clkmux_sync_cust is
+port (
+bypass_pll_clk : in bit;
+pll_clk : in bit;
+arst : in bit;
+d1 : in bit;
+d2 : in bit;
+d1_sync : out bit;
+d2_sync : out bit;
+d0_sync : out bit;
+d0 : in bit;
+d3_sync : out bit;
+d3 : in bit
+);
+end entity n2_core_pll_clkmux_sync_cust;
+architecture arch of n2_core_pll_clkmux_sync_cust is
+--supply1 vdd;
+signal net089,net111,net112,net113,net114,net0185,net0186,net0187,net0207,net0189,d0_1,d0_2,d1_1,d0_3,d1_2,d0_4,d1_3,d2_1, d1_4,d2_2,d3_1,d2_3,d3_2,d2_4,d3_3,d3_4,clk_dly1,clk_dly2,clk_dly3,clk_dly4,clk_dly5,net054,net057,net0110,net0191,net0192,net56,net0125,net0126,net078,net63 : bit;
+signal bypass_pll_clk_l : bit;
+signal vdd : bit;
+component n2_core_pll_flop_reset_new_cust is
+port (
+vdd_reg : in bit;
+reset_val_l : in bit;
+d : in bit;
+reset : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end component n2_core_pll_flop_reset_new_cust;
+component n2_core_pll_clkrep_cust is
+port (
+pll_clk : in bit;
+clk_dly3 : out bit;
+clk_dly5 : out bit;
+clk_dly4 : out bit;
+clk_dly2 : out bit;
+clk_dly1 : out bit
+);
+end component n2_core_pll_clkrep_cust;
+begin
+vdd <= '1';
+bypass_pll_clk_l <= not bypass_pll_clk;
+x2 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => bypass_pll_clk_l,
+d => d2_4,
+reset => arst,
+clk => clk_dly1,
+q_l => net0125,
+q => d2_sync
+);
+x3 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => d3_4,
+reset => arst,
+clk => clk_dly1,
+q_l => net057,
+q => d3_sync
+);
+x4 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => d1_4,
+reset => arst,
+clk => clk_dly1,
+q_l => net0110,
+q => d1_sync
+);
+x5 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => d0_4,
+reset => arst,
+clk => clk_dly1,
+q_l => net0192,
+q => d0_sync
+);
+x6 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => d0_3,
+reset => arst,
+clk => clk_dly2,
+q_l => net0191,
+q => d0_4
+);
+x7 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => d1_3,
+reset => arst,
+clk => clk_dly2,
+q_l => net089,
+q => d1_4
+);
+x8 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => d0_1,
+reset => arst,
+clk => clk_dly4,
+q_l => net0186,
+q => d0_2
+);
+x9 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => d1_1,
+reset => arst,
+clk => clk_dly4,
+q_l => net0187,
+q => d1_2
+);
+x10 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => d1_2,
+reset => arst,
+clk => clk_dly3,
+q_l => net0189,
+q => d1_3
+);
+x12 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => d1,
+reset => arst,
+clk => clk_dly5,
+q_l => net054,
+q => d1_1
+);
+x13 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => d0_2,
+reset => arst,
+clk => clk_dly3,
+q_l => net0185,
+q => d0_3
+);
+x14 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => d0,
+reset => arst,
+clk => clk_dly5,
+q_l => net0207,
+q => d0_1
+);
+x18 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => bypass_pll_clk_l,
+d => d2_2,
+reset => arst,
+clk => clk_dly3,
+q_l => net114,
+q => d2_3
+);
+x19 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => d3_2,
+reset => arst,
+clk => clk_dly3,
+q_l => net56,
+q => d3_3
+);
+x20 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => d3_1,
+reset => arst,
+clk => clk_dly4,
+q_l => net112,
+q => d3_2
+);
+x21 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => bypass_pll_clk_l,
+d => d2_1,
+reset => arst,
+clk => clk_dly4,
+q_l => net113,
+q => d2_2
+);
+x22 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => bypass_pll_clk_l,
+d => d2,
+reset => arst,
+clk => clk_dly5,
+q_l => net63,
+q => d2_1
+);
+x23 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => d3,
+reset => arst,
+clk => clk_dly5,
+q_l => net111,
+q => d3_1
+);
+x24 : n2_core_pll_clkrep_cust port map (
+pll_clk => pll_clk,
+clk_dly3 => clk_dly3,
+clk_dly5 => clk_dly5,
+clk_dly4 => clk_dly4,
+clk_dly2 => clk_dly2,
+clk_dly1 => clk_dly1
+);
+x0 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => d3_3,
+reset => arst,
+clk => clk_dly2,
+q_l => net078,
+q => d3_4
+);
+x1 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => bypass_pll_clk_l,
+d => d2_3,
+reset => arst,
+clk => clk_dly2,
+q_l => net0126,
+q => d2_4
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_clkrep_cust.vhd b/pll/n2_core_pll_clkrep_cust.vhd
new file mode 100755
index 0000000..00c42e1
--- /dev/null
+++ b/pll/n2_core_pll_clkrep_cust.vhd
@@ -0,0 +1,27 @@
+entity n2_core_pll_clkrep_cust is
+port (
+pll_clk : in bit;
+clk_dly3 : out bit;
+clk_dly5 : out bit;
+clk_dly4 : out bit;
+clk_dly2 : out bit;
+clk_dly1 : out bit
+);
+end entity n2_core_pll_clkrep_cust;
+architecture arch of n2_core_pll_clkrep_cust is
+--supply1 vdd;
+--vss = '0';
+signal tclk_dly3,tclk_dly5,tclk_dly4,tclk_dly2,tclk_dly1 : bit;
+begin
+tclk_dly1 <= pll_clk;
+tclk_dly2 <= tclk_dly1;
+tclk_dly3 <= tclk_dly2;
+tclk_dly4 <= tclk_dly3;
+tclk_dly5 <= tclk_dly4;
+clk_dly1 <= tclk_dly1;
+clk_dly2 <= tclk_dly2;
+clk_dly3 <= tclk_dly3;
+clk_dly4 <= tclk_dly4;
+clk_dly5 <= tclk_dly5;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_cp_cust.vhd b/pll/n2_core_pll_cp_cust.vhd
new file mode 100755
index 0000000..1fbeaf1
--- /dev/null
+++ b/pll/n2_core_pll_cp_cust.vhd
@@ -0,0 +1,30 @@
+entity n2_core_pll_cp_cust is
+port (
+slow_l : in bit;
+vdd_reg : in bit;
+slow : in bit;
+fast : in bit;
+fast_l : in bit;
+fltr : out bit
+);
+end entity n2_core_pll_cp_cust;
+architecture arch of n2_core_pll_cp_cust is
+begin
+end architecture arch;
+
+entity n2_core_pll_delay_cust is
+port (
+vdd_reg : in bit;
+out_delcr : out bit;
+i : in bit;
+out_del : out bit
+);
+end entity n2_core_pll_delay_cust;
+architecture arch of n2_core_pll_delay_cust is
+--supply1 vdd;
+--vss = '0';
+begin
+out_del <= i after 1 ns;
+out_delcr <= not i after 1 ns;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_csa32_cust.vhd b/pll/n2_core_pll_csa32_cust.vhd
new file mode 100755
index 0000000..f3f25c4
--- /dev/null
+++ b/pll/n2_core_pll_csa32_cust.vhd
@@ -0,0 +1,30 @@
+entity n2_core_pll_csa32_cust is
+port (
+in0 : in bit;
+sum : out bit;
+in0_l : in bit;
+carry : out bit;
+in2 : in bit;
+in1 : in bit
+);
+end entity n2_core_pll_csa32_cust;
+architecture arch of n2_core_pll_csa32_cust is
+component fadd is
+port (
+cin : in bit;
+a : in bit;
+b : in bit;
+s : out bit;
+cout : out bit
+);
+end component fadd;
+begin
+x1 : fadd port map (
+cin => in0,
+a => in1,
+b => in2,
+s => sum,
+cout => carry
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_d4_ctl_cust.vhd b/pll/n2_core_pll_d4_ctl_cust.vhd
new file mode 100755
index 0000000..10c5865
--- /dev/null
+++ b/pll/n2_core_pll_d4_ctl_cust.vhd
@@ -0,0 +1,210 @@
+entity n2_core_pll_d4_ctl_cust is
+port (
+cac_l : out bit;
+csel_l : out bit_vector(1 downto 1);
+pclk : out bit;
+out_clk : out bit;
+eq : in bit;
+in_clk : in bit;
+csel : out bit_vector(1 downto 1);
+rstps : in bit;
+a : in bit_vector(4 downto 0)
+);
+end entity n2_core_pll_d4_ctl_cust;
+architecture arch of n2_core_pll_d4_ctl_cust is
+--supply1 vdd;
+--vss = '0';
+signal vdd : bit;
+signal vss : bit;
+signal carry : bit_vector(3 downto 1);
+signal csel_a1,csel_a1_l : bit_vector(1 downto 0);
+signal sum : bit_vector(2 downto 0);
+signal net089,mux_clk_l,ca2_a1_l,net94,net034,net043,net045,rst1,ca2_a1,mux_clk,nreset : bit;
+component n2_core_pll_tpm1_cust is
+port (
+nreset : in bit;
+ca2_a1 : in bit;
+cac_l : out bit;
+reset : in bit;
+sel_l : out bit;
+sel : out bit;
+ip : in bit_vector(2 downto 0);
+vco_ck : in bit
+);
+end component n2_core_pll_tpm1_cust;
+component cl_u1_inv_8x is
+port (
+i : in bit;
+o : out bit
+);
+end component cl_u1_inv_8x;
+component n2_core_pll_inv1_32x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv1_32x_cust;
+component n2_core_pll_flop_reset1_cust is
+port(
+reset_val_l : in bit;
+d : in bit;
+reset : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end component n2_core_pll_flop_reset1_cust;
+component cl_u1_inv_4x is
+port (
+i : in bit;
+o : out bit
+);
+end component cl_u1_inv_4x;
+component n2_core_pll_inv1_16x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv1_16x_cust;
+component cl_u1_nand2_8x is
+port (
+in0 : in bit;
+in1 : in bit;
+o : out bit
+);
+end component cl_u1_nand2_8x;
+component n2_core_pll_flop_reset2_cust is
+port (
+d : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end component n2_core_pll_flop_reset2_cust;
+component n2_core_pll_csa32_cust is
+port (
+in0 : in bit;
+sum : out bit;
+in0_l : in bit;
+carry : out bit;
+in2 : in bit;
+in1 : in bit
+);
+end component n2_core_pll_csa32_cust;
+component cl_u1_buf_1x is
+port (
+i : in bit;
+o : out bit
+);
+end component cl_u1_buf_1x;
+begin
+vdd <= '1';
+vss <= '0';
+x2 : n2_core_pll_tpm1_cust port map (
+ip => a(4 downto 2),
+nreset => nreset,
+ca2_a1 => ca2_a1,
+cac_l => cac_l,
+reset => rst1,
+sel_l => mux_clk,
+sel => mux_clk_l,
+vco_ck => in_clk
+);
+x5 : cl_u1_inv_8x port map (
+o => net034,
+i => rstps
+);
+xa0 : n2_core_pll_flop_reset1_cust port map (
+reset_val_l => vdd,
+d => sum(0),
+reset => rst1,
+clk => mux_clk,
+q_l => csel_a1_l(0),
+q => csel_a1(0)
+);
+x6 : n2_core_pll_inv1_32x_cust port map (
+vdd_reg => vdd,
+o => rst1,
+i => net043
+);
+x7 : cl_u1_nand2_8x port map (
+o => nreset,
+in1 => a(4),
+in0 => net043
+);
+xa_1 : n2_core_pll_flop_reset1_cust port map (
+reset_val_l => vdd,
+d => sum(1),
+reset => rst1,
+clk => mux_clk,
+q_l => csel_a1_l(1),
+q => csel_a1(1)
+);
+x11 : cl_u1_nand2_8x port map (
+o => out_clk,
+in1 => eq,
+in0 => mux_clk_l
+);
+x13 : n2_core_pll_flop_reset2_cust port map (
+d => net034,
+clk => in_clk,
+q_l => net045,
+q => net043
+);
+xa_2 : n2_core_pll_flop_reset1_cust port map (
+reset_val_l => vdd,
+d => sum(2),
+reset => rst1,
+clk => mux_clk,
+q_l => ca2_a1_l,
+q => ca2_a1
+);
+xb_0 : n2_core_pll_csa32_cust port map (
+in0 => csel_a1(0),
+sum => sum(0),
+in0_l => csel_a1_l(0),
+carry => carry(1),
+in2 => vss,
+in1 => a(0)
+);
+x22 : n2_core_pll_inv1_16x_cust port map (
+vdd_reg => vdd,
+o => pclk,
+i => net94
+);
+xb_1 : n2_core_pll_csa32_cust port map (
+in0 => csel_a1(1),
+sum => sum(1),
+in0_l => csel_a1_l(1),
+carry => carry(2),
+in2 => carry(1),
+in1 => a(1)
+);
+x3_1 : cl_u1_buf_1x port map (
+o => net089,
+i => csel_a1(1)
+);
+xb_2 : n2_core_pll_csa32_cust port map (
+in0 => vss,
+sum => sum(2),
+in0_l => vdd,
+carry => carry(3),
+in2 => carry(2),
+in1 => vss
+);
+x0_1 : n2_core_pll_flop_reset1_cust port map (
+reset_val_l => vdd,
+d => net089,
+reset => rst1,
+clk => mux_clk,
+q_l => csel_l(1),
+q => csel(1)
+);
+x1 : cl_u1_inv_4x port map (
+o => net94,
+i => in_clk
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_d4_frac_cust.vhd b/pll/n2_core_pll_d4_frac_cust.vhd
new file mode 100755
index 0000000..1eb470f
--- /dev/null
+++ b/pll/n2_core_pll_d4_frac_cust.vhd
@@ -0,0 +1,99 @@
+entity n2_core_pll_d4_frac_cust is
+port (
+dft_rst_l : in bit;
+vco_clk : in bit;
+a : in bit_vector(4 downto 0);
+out_clk : out bit
+);
+end entity n2_core_pll_d4_frac_cust;
+architecture arch of n2_core_pll_d4_frac_cust is
+--supply1 vdd;
+signal vdd : bit;
+signal bs_pi_clk_4,bs_ph_clk_4,bs_csel_1,bs_csel_l_3,
+bs_csel_3,bs_csel_l_1 : bit_vector(1 downto 1); --XXX 0-0
+signal bs_rstps_0 : bit_vector(0 downto 0);
+signal bs_cac_l_4,bs_rstps_4,bs_pclk_0,bs_pclk_4,
+bs_cac_l_0,bs_pi_clk_0,bs_ph_clk_0 : bit;
+component n2_core_pll_d4_sync_cust is
+port (
+dft_rst_l : in bit;
+bs_rstps_4 : out bit;
+bs_rstps_0 : out bit;
+bs_pclk_4 : in bit;
+bs_pclk_0 : in bit
+);
+end component n2_core_pll_d4_sync_cust;
+component n2_core_pll_d4_mux_cust is
+port (
+out_clk : out bit;
+rstps : in bit_vector(0 downto 0);
+bs_pi_clk_4 : in bit;
+bs_pi_clk_0 : in bit
+);
+end component n2_core_pll_d4_mux_cust;
+component n2_core_pll_d4_ctl_cust is
+port (
+cac_l : out bit;
+csel_l : out bit_vector(1 downto 1);
+pclk : out bit;
+out_clk : out bit;
+eq : in bit;
+in_clk : in bit;
+csel : out bit_vector(1 downto 1);
+rstps : in bit;
+a : in bit_vector(4 downto 0)
+);
+end component n2_core_pll_d4_ctl_cust;
+component n2_core_pll_fse2diff_out_cust is
+port (
+vdd_reg : in bit;
+i : in bit;
+out_l : out bit;
+o : out bit
+);
+end component n2_core_pll_fse2diff_out_cust;
+begin
+vdd <= '1';
+x3 : n2_core_pll_d4_sync_cust port map (
+dft_rst_l => dft_rst_l,
+bs_rstps_4 => bs_rstps_4,
+bs_rstps_0 => bs_rstps_0(0),
+bs_pclk_4 => bs_pclk_4,
+bs_pclk_0 => bs_pclk_0
+);
+x2_0 : n2_core_pll_d4_ctl_cust port map (
+csel_l => bs_csel_l_1,
+csel => bs_csel_1,
+a => a,
+cac_l => bs_cac_l_0,
+pclk => bs_pclk_0,
+out_clk => bs_pi_clk_0,
+eq => bs_csel_l_1(1),
+in_clk => bs_ph_clk_0,
+rstps => bs_rstps_0(0)
+);
+x2_1 : n2_core_pll_d4_ctl_cust port map (
+csel_l => bs_csel_l_3,
+csel => bs_csel_3,
+a => a,
+cac_l => bs_cac_l_4,
+pclk => bs_pclk_4,
+out_clk => bs_pi_clk_4(1),
+eq => bs_csel_3(1),
+in_clk => bs_ph_clk_4(1),
+rstps => bs_rstps_4
+);
+x1_0 : n2_core_pll_fse2diff_out_cust port map (
+vdd_reg => vdd,
+i => vco_clk,
+out_l => bs_ph_clk_4(1),
+o => bs_ph_clk_0
+);
+x0 : n2_core_pll_d4_mux_cust port map (
+rstps => bs_rstps_0,
+out_clk => out_clk,
+bs_pi_clk_4 => bs_pi_clk_4(1),
+bs_pi_clk_0 => bs_pi_clk_0
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_d4_mux_cust.vhd b/pll/n2_core_pll_d4_mux_cust.vhd
new file mode 100755
index 0000000..e6156c7
--- /dev/null
+++ b/pll/n2_core_pll_d4_mux_cust.vhd
@@ -0,0 +1,82 @@
+entity n2_core_pll_d4_mux_cust is
+port (
+out_clk : out bit;
+rstps : in bit_vector(0 downto 0);
+bs_pi_clk_4 : in bit;
+bs_pi_clk_0 : in bit
+);
+end entity n2_core_pll_d4_mux_cust;
+architecture arch of n2_core_pll_d4_mux_cust is
+--supply1 vdd;
+--vss = '0';
+signal in8_clk_l,net032,mux_clk,in8_clk,net61 : bit;
+signal vss,vdd : bit;
+component cl_u1_nand2_4x is
+port (
+in0 : in bit;
+in1 : in bit;
+o : out bit
+);
+end component cl_u1_nand2_4x;
+component n2_core_pll_flop_reset1_cust is
+port(
+reset_val_l : in bit;
+d : in bit;
+reset : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end component n2_core_pll_flop_reset1_cust;
+component cl_u1_buf_1x is
+port (
+i : in bit;
+o : out bit
+);
+end component cl_u1_buf_1x;
+component n2_core_pll_inv_32x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_32x_cust;
+component n2_core_pll_inv_8x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_8x_cust;
+begin
+vdd <= '1';
+vss <= '0';
+x8 : cl_u1_nand2_4x port map (
+o => mux_clk,
+in1 => bs_pi_clk_0,
+in0 => bs_pi_clk_4
+);
+x9 : cl_u1_buf_1x port map (
+o => net61,
+i => in8_clk_l
+);
+x17 : n2_core_pll_flop_reset1_cust port map (
+reset_val_l => vss,
+d => net61,
+reset => rstps(0),
+clk => mux_clk,
+q_l => in8_clk_l,
+q => in8_clk
+);
+x0 : n2_core_pll_inv_32x_cust port map (
+vdd_reg => vdd,
+o => out_clk,
+i => net032
+);
+x1 : n2_core_pll_inv_8x_cust port map (
+vdd_reg => vdd,
+o => net032,
+i => in8_clk
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_d4_sync_cust.vhd b/pll/n2_core_pll_d4_sync_cust.vhd
new file mode 100755
index 0000000..a98382f
--- /dev/null
+++ b/pll/n2_core_pll_d4_sync_cust.vhd
@@ -0,0 +1,55 @@
+entity n2_core_pll_d4_sync_cust is
+port (
+dft_rst_l : in bit;
+bs_rstps_4 : out bit;
+bs_rstps_0 : out bit;
+bs_pclk_4 : in bit;
+bs_pclk_0 : in bit
+);
+end entity n2_core_pll_d4_sync_cust;
+architecture arch of n2_core_pll_d4_sync_cust is
+--supply1 vdd;
+signal net014,net031,net46 : bit;
+signal rstp_4 : bit; --bit_vector(4 downto 4);
+signal vdd : bit;
+component n2_core_pll_flop_reset2_cust is
+port (
+d : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end component n2_core_pll_flop_reset2_cust;
+component n2_core_pll_inv1_16x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv1_16x_cust;
+begin
+vdd <= '1';
+x2 : n2_core_pll_flop_reset2_cust port map (
+d => rstp_4,
+clk => bs_pclk_4,
+q_l => net46,
+q => net031
+);
+x7 : n2_core_pll_inv1_16x_cust port map (
+vdd_reg => vdd,
+o => bs_rstps_0,
+i => net014
+);
+x0 : n2_core_pll_flop_reset2_cust port map (
+d => dft_rst_l,
+clk => bs_pclk_0,
+q_l => rstp_4,
+q => net014
+);
+x1 : n2_core_pll_inv1_16x_cust port map (
+vdd_reg => vdd,
+o => bs_rstps_4,
+i => net46
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_delay_cust.vhd b/pll/n2_core_pll_delay_cust.vhd
new file mode 100755
index 0000000..a0ef15d
--- /dev/null
+++ b/pll/n2_core_pll_delay_cust.vhd
@@ -0,0 +1,16 @@
+entity n2_core_pll_delay_cust is
+port (
+vdd_reg : in bit;
+out_delcr : out bit;
+i : in bit;
+out_del : out bit
+);
+end entity n2_core_pll_delay_cust;
+architecture arch of n2_core_pll_delay_cust is
+--supply1 vdd;
+--vss = '0';
+begin
+out_del <= i after 1 ps;
+out_delcr <= not i after 1 ps;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_div4_cust.vhd b/pll/n2_core_pll_div4_cust.vhd
new file mode 100755
index 0000000..3b215b8
--- /dev/null
+++ b/pll/n2_core_pll_div4_cust.vhd
@@ -0,0 +1,115 @@
+entity n2_core_pll_div4_cust is
+port (
+clk : in bit;
+arst_l : in bit;
+clk_div_out : out bit
+);
+end entity n2_core_pll_div4_cust;
+architecture arch of n2_core_pll_div4_cust is
+--supply1 vdd;
+signal vss,vdd : bit;
+signal div4_l,clk_div,n1,n2,n3,n4,net19,net038,net26,net33,clk_div_l,div2_l : bit;
+component n2_core_pll_inv_8x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_8x_cust;
+component cl_u1_inv_4x is
+port (
+i : in bit;
+o : out bit
+);
+end component cl_u1_inv_4x;
+component n2_core_pll_flop_reset_new_cust is
+port (
+vdd_reg : in bit;
+reset_val_l : in bit;
+d : in bit;
+reset : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end component n2_core_pll_flop_reset_new_cust;
+component n2_core_pll_buf_2x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_buf_2x_cust;
+component n2_core_pll_inv_32x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_32x_cust;
+begin
+vdd <= '1';
+vss <= '0';
+x2 : n2_core_pll_inv_8x_cust port map (
+vdd_reg => vdd,
+o => clk_div_l,
+i => clk_div
+);
+x3 : cl_u1_inv_4x port map (
+o => net038,
+i => arst_l
+);
+x4 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => n2,
+reset => net038,
+clk => clk,
+q_l => div2_l,
+q => net33
+);
+x5 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => n4,
+reset => net038,
+clk => div2_l,
+q_l => div4_l,
+q => net26
+);
+x6 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => div4_l,
+reset => net038,
+clk => clk,
+q_l => clk_div,
+q => net19
+);
+x9 : n2_core_pll_buf_2x_cust port map (
+vdd_reg => vdd,
+o => n2,
+i => n1
+);
+x10 : n2_core_pll_buf_2x_cust port map (
+vdd_reg => vdd,
+o => n3,
+i => div4_l
+);
+x11 : n2_core_pll_buf_2x_cust port map (
+vdd_reg => vdd,
+o => n4,
+i => n3
+);
+x0 : n2_core_pll_buf_2x_cust port map (
+vdd_reg => vdd,
+o => n1,
+i => div2_l
+);
+x1 : n2_core_pll_inv_32x_cust port map (
+vdd_reg => vdd,
+o => clk_div_out,
+i => clk_div_l
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_div4_new_cust.vhd b/pll/n2_core_pll_div4_new_cust.vhd
new file mode 100755
index 0000000..5cafd55
--- /dev/null
+++ b/pll/n2_core_pll_div4_new_cust.vhd
@@ -0,0 +1,114 @@
+entity n2_core_pll_div4_new_cust is
+port (
+clk : in bit;
+arst_l : in bit;
+clk_div_out : out bit
+);
+end entity n2_core_pll_div4_new_cust;
+architecture arch of n2_core_pll_div4_new_cust is
+--supply1 vdd;
+signal vdd : bit;
+signal div4_l,clk_div,n1,n2,n3,n4,net19,net038,net26,net33,clk_div_l,div2_l : bit;
+component n2_core_pll_inv_8x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_8x_cust;
+component cl_u1_inv_4x is
+port (
+i : in bit;
+o : out bit
+);
+end component cl_u1_inv_4x;
+component n2_core_pll_flop_reset_new_cust is
+port (
+vdd_reg : in bit;
+reset_val_l : in bit;
+d : in bit;
+reset : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end component n2_core_pll_flop_reset_new_cust;
+component n2_core_pll_buf_2x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_buf_2x_cust;
+component n2_core_pll_inv_32x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_32x_cust;
+begin
+vdd <= '1';
+x2 : n2_core_pll_inv_8x_cust port map (
+vdd_reg => vdd,
+o => clk_div_l,
+i => clk_div
+);
+x3 : cl_u1_inv_4x port map (
+o => net038,
+i => arst_l
+);
+x4 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => n2,
+reset => net038,
+clk => clk,
+q_l => div2_l,
+q => net33
+);
+x5 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => n4,
+reset => net038,
+clk => div2_l,
+q_l => div4_l,
+q => net26
+);
+x6 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => div4_l,
+reset => net038,
+clk => clk,
+q_l => clk_div,
+q => net19
+);
+x9 : n2_core_pll_buf_2x_cust port map (
+vdd_reg => vdd,
+o => n2,
+i => n1
+);
+x10 : n2_core_pll_buf_2x_cust port map (
+vdd_reg => vdd,
+o => n3,
+i => div4_l
+);
+x11 : n2_core_pll_buf_2x_cust port map (
+vdd_reg => vdd,
+o => n4,
+i => n3
+);
+x0 : n2_core_pll_buf_2x_cust port map (
+vdd_reg => vdd,
+o => n1,
+i => div2_l
+);
+x1 : n2_core_pll_inv_32x_cust port map (
+vdd_reg => vdd,
+o => clk_div_out,
+i => clk_div_l
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_div4_new_cust_1.vhd b/pll/n2_core_pll_div4_new_cust_1.vhd
new file mode 100755
index 0000000..9c0189e
--- /dev/null
+++ b/pll/n2_core_pll_div4_new_cust_1.vhd
@@ -0,0 +1,74 @@
+entity n2_core_pll_div4_new_cust is
+port (
+clk : in bit;
+arst_l : in bit;
+clk_div_out : out bit
+);
+end entity n2_core_pll_div4_new_cust;
+architecture arch of n2_core_pll_div4_new_cust is
+--supply1 vdd;
+signal div4_l,clk_div,n1,n2,n3,n4,net19,net038,net26,net33,clk_div_l,div2_l : bit;
+begin
+x2 : n2_core_pll_inv_8x_cust port map (
+vdd_reg => vdd,
+o => clk_div_l,
+i => clk_div
+);
+x3 : cl_u1_inv_4x port map (
+o => net038,
+i => arst_l
+);
+x4 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => n2,
+reset => net038,
+clk => clk,
+q_l => div2_l,
+q => net33
+);
+x5 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => n4,
+reset => net038,
+clk => div2_l,
+q_l => div4_l,
+q => net26
+);
+x6 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd,
+reset_val_l => vdd,
+d => div4_l,
+reset => net038,
+clk => clk,
+q_l => clk_div,
+q => net19
+);
+x9 : n2_core_pll_buf_2x_cust port map (
+vdd_reg => vdd,
+o => n2,
+i => n1
+);
+x10 : n2_core_pll_buf_2x_cust port map (
+vdd_reg => vdd,
+o => n3,
+i => div4_l
+);
+x11 : n2_core_pll_buf_2x_cust port map (
+vdd_reg => vdd,
+o => n4,
+i => n3
+);
+x0 : n2_core_pll_buf_2x_cust port map (
+vdd_reg => vdd,
+o => n1,
+i => div2_l
+);
+x1 : n2_core_pll_inv_32x_cust port map (
+vdd_reg => vdd,
+o => clk_div_out,
+i => clk_div_l
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_flop_reset1_cust.vhd b/pll/n2_core_pll_flop_reset1_cust.vhd
new file mode 100755
index 0000000..2bb38d0
--- /dev/null
+++ b/pll/n2_core_pll_flop_reset1_cust.vhd
@@ -0,0 +1,42 @@
+entity n2_core_pll_flop_reset1_cust is
+port (
+reset_val_l : in bit;
+d : in bit;
+reset : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end entity n2_core_pll_flop_reset1_cust;
+architecture arch of n2_core_pll_flop_reset1_cust is
+--supply1 vdd;
+signal qq,qb : bit;
+begin
+--p0 : process (clk,d,reset) is
+--begin
+-- if (reset = '1') then
+-- qb <= not reset_val_l;
+-- elsif (clk = '0') then
+-- qb <= d;
+-- end if;
+--end process p0;
+--p1 : process (clk,reset) is
+--begin
+-- if (reset = '1') then
+-- q <= not reset_val_l;
+-- elsif (clk = '1') then
+-- q <= qb;
+-- end if;
+--end process p1;
+p0 : process (clk,reset) is
+begin
+ if (reset = '1') then
+ qq <= not reset_val_l;
+ elsif (clk'event and clk = '1') then
+ qq <= d;
+ end if;
+end process p0;
+q <= qq;
+q_l <= not qq;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_flop_reset1_cust_1.vhd b/pll/n2_core_pll_flop_reset1_cust_1.vhd
new file mode 100755
index 0000000..f927f41
--- /dev/null
+++ b/pll/n2_core_pll_flop_reset1_cust_1.vhd
@@ -0,0 +1,25 @@
+entity n2_core_pll_flop_reset1_cust is
+port(
+reset_val_l : in bit;
+d : in bit;
+reset : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end entity n2_core_pll_flop_reset1_cust;
+architecture arch of n2_core_pll_flop_reset1_cust is
+signal q : bit;
+signal qb : bit;
+begin
+p0 : process (clk,reset) is
+begin
+ if (reset = '1') then
+ q <= not reset_val_l;
+ elsif (rising_edge(clk)) then
+ q <= d;
+ end if;
+end process p0;
+q_l <= not q;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_flop_reset2_cust.vhd b/pll/n2_core_pll_flop_reset2_cust.vhd
new file mode 100755
index 0000000..f24bed4
--- /dev/null
+++ b/pll/n2_core_pll_flop_reset2_cust.vhd
@@ -0,0 +1,40 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+entity n2_core_pll_flop_reset2_cust is
+port (
+d : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end entity n2_core_pll_flop_reset2_cust;
+architecture arch of n2_core_pll_flop_reset2_cust is
+--supply1 vdd;
+signal qq,q_b : bit;
+begin
+p0 : process (clk,d) is
+begin
+if (clk = '0') then
+q_b <= d;
+else
+q_b <= q_b;
+end if;
+end process p0;
+p1 : process (clk) is
+begin
+if (clk = '1') then
+qq <= q_b;
+else
+qq <= qq;
+end if;
+end process p1;
+q <= qq;
+q_l <= not qq;
+--p0 : process (clk) is
+--begin
+--if (rising_edge(clk)) then
+--q <= d;
+--end if;
+--end process p0;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_flop_reset_new_1x_cust.vhd b/pll/n2_core_pll_flop_reset_new_1x_cust.vhd
new file mode 100755
index 0000000..bafc95b
--- /dev/null
+++ b/pll/n2_core_pll_flop_reset_new_1x_cust.vhd
@@ -0,0 +1,27 @@
+entity n2_core_pll_flop_reset_new_1x_cust is
+port (
+vdd_reg : in bit;
+reset_val_l : in bit;
+d : in bit;
+reset : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end entity n2_core_pll_flop_reset_new_1x_cust;
+architecture arch of n2_core_pll_flop_reset_new_1x_cust is
+--vss = '0';
+signal qq : bit;
+begin
+p0 : process(clk,reset) is
+begin
+if (reset = '1') then
+qq <= not reset_val_l;
+elsif (clk'event and clk = '1') then
+qq <= d;
+end if;
+end process p0;
+q <= qq;
+q_l <= not qq;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_flop_reset_new_cust.vhd b/pll/n2_core_pll_flop_reset_new_cust.vhd
new file mode 100755
index 0000000..97b23dc
--- /dev/null
+++ b/pll/n2_core_pll_flop_reset_new_cust.vhd
@@ -0,0 +1,47 @@
+entity n2_core_pll_flop_reset_new_cust is
+port (
+vdd_reg : in bit;
+reset_val_l : in bit;
+d : in bit;
+reset : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end entity n2_core_pll_flop_reset_new_cust;
+architecture arch of n2_core_pll_flop_reset_new_cust is
+signal qq,qb : bit;
+begin
+--p0 : process (clk,d,reset) is
+--begin
+-- if (reset = '1') then
+-- qb <= not reset_val_l;
+-- elsif (falling_edge(clk)) then
+-- qb <= d;
+-- else
+-- qb <= qb;
+-- end if;
+--end process p0;
+--p1 : process (clk,reset) is
+--begin
+-- if (reset = '1') then
+-- q <= not reset_val_l;
+-- elsif (rising_edge(clk)) then
+-- q <= qb;
+-- else
+-- q <= q;
+-- end if;
+--end process p1;
+--q_l <= not q;
+p0 : process (clk,reset) is
+begin
+ if (reset = '1') then
+ qq <= not reset_val_l;
+ elsif (clk'event and clk = '1') then
+ qq <= d;
+ end if;
+end process p0;
+q <= qq;
+q_l <= not qq;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_flopderst_16x_cust.vhd b/pll/n2_core_pll_flopderst_16x_cust.vhd
new file mode 100755
index 0000000..bc3635e
--- /dev/null
+++ b/pll/n2_core_pll_flopderst_16x_cust.vhd
@@ -0,0 +1,44 @@
+entity n2_core_pll_flopderst_16x_cust is
+port (
+q_l : out bit;
+reset_val : in bit;
+d : in bit;
+q : out bit;
+reset : in bit;
+clk : in bit;
+ena : in bit
+);
+end entity n2_core_pll_flopderst_16x_cust;
+architecture arch of n2_core_pll_flopderst_16x_cust is
+signal qb_p,qb_n,qq : bit;
+begin
+p0 : process (clk,d,reset,reset_val) is
+begin
+if (reset = '1') then
+qb_p <= reset_val;
+elsif (clk'event and clk = '1') then
+qb_p <= d;
+end if;
+end process p0;
+p1 : process (clk,d,reset,reset_val) is
+begin
+if (reset = '1') then
+qb_n <= reset_val;
+elsif (clk'event and clk = '0') then
+qb_n <= d;
+end if;
+end process p1;
+p2 : process (clk,reset,ena,reset_val) is
+begin
+if (reset = '1') then
+qq <= reset_val;
+elsif (clk = '1' and ena = '1') then -- XXX
+qq <= qb_n;
+elsif (clk = '0' and ena = '0') then -- XXX
+qq <= qb_p;
+end if;
+end process p2;
+q <= qq;
+q_l <= not qq;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_fse2diff_out_cust.vhd b/pll/n2_core_pll_fse2diff_out_cust.vhd
new file mode 100755
index 0000000..3e8ec4b
--- /dev/null
+++ b/pll/n2_core_pll_fse2diff_out_cust.vhd
@@ -0,0 +1,15 @@
+entity n2_core_pll_fse2diff_out_cust is
+port (
+vdd_reg : in bit;
+i : in bit;
+out_l : out bit;
+o : out bit
+);
+end entity n2_core_pll_fse2diff_out_cust;
+architecture arch of n2_core_pll_fse2diff_out_cust is
+--vss = '0';
+begin
+o <= i;
+out_l <= not i;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_inv1_16x_cust.vhd b/pll/n2_core_pll_inv1_16x_cust.vhd
new file mode 100755
index 0000000..7b5f676
--- /dev/null
+++ b/pll/n2_core_pll_inv1_16x_cust.vhd
@@ -0,0 +1,13 @@
+entity n2_core_pll_inv1_16x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_inv1_16x_cust;
+architecture arch of n2_core_pll_inv1_16x_cust is
+--vss = '0';
+begin
+o <= not i;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_inv1_32x_cust.vhd b/pll/n2_core_pll_inv1_32x_cust.vhd
new file mode 100755
index 0000000..d80d417
--- /dev/null
+++ b/pll/n2_core_pll_inv1_32x_cust.vhd
@@ -0,0 +1,13 @@
+entity n2_core_pll_inv1_32x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_inv1_32x_cust;
+architecture arch of n2_core_pll_inv1_32x_cust is
+--vss = '0';
+begin
+o <= not i;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_inv_100x_cust.vhd b/pll/n2_core_pll_inv_100x_cust.vhd
new file mode 100755
index 0000000..30cda71
--- /dev/null
+++ b/pll/n2_core_pll_inv_100x_cust.vhd
@@ -0,0 +1,13 @@
+entity n2_core_pll_inv_100x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_inv_100x_cust;
+architecture arch of n2_core_pll_inv_100x_cust is
+begin
+--wire vss = '0';
+o <= not i;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_inv_100x_cust_1.vhd b/pll/n2_core_pll_inv_100x_cust_1.vhd
new file mode 100755
index 0000000..d95b33b
--- /dev/null
+++ b/pll/n2_core_pll_inv_100x_cust_1.vhd
@@ -0,0 +1,12 @@
+entity n2_core_pll_inv_100x_cust is
+port(
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_inv_100x_cust;
+architecture arch of n2_core_pll_inv_100x_cust is
+begin
+o <= not i;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_inv_16x_a_cust.vhd b/pll/n2_core_pll_inv_16x_a_cust.vhd
new file mode 100755
index 0000000..869f4b4
--- /dev/null
+++ b/pll/n2_core_pll_inv_16x_a_cust.vhd
@@ -0,0 +1,13 @@
+entity n2_core_pll_inv_16x_a_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_inv_16x_a_cust;
+architecture arch of n2_core_pll_inv_16x_a_cust is
+--vss = '0';
+begin
+o <= not i;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_inv_16x_cust.vhd b/pll/n2_core_pll_inv_16x_cust.vhd
new file mode 100755
index 0000000..2411369
--- /dev/null
+++ b/pll/n2_core_pll_inv_16x_cust.vhd
@@ -0,0 +1,13 @@
+entity n2_core_pll_inv_16x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_inv_16x_cust;
+architecture arch of n2_core_pll_inv_16x_cust is
+--vss = '0';
+begin
+o <= not i;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_inv_1x_cust.vhd b/pll/n2_core_pll_inv_1x_cust.vhd
new file mode 100755
index 0000000..eb90a4f
--- /dev/null
+++ b/pll/n2_core_pll_inv_1x_cust.vhd
@@ -0,0 +1,12 @@
+entity n2_core_pll_inv_1x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_inv_1x_cust;
+architecture arch of n2_core_pll_inv_1x_cust is
+begin
+o <= not i;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_inv_2x_cust.vhd b/pll/n2_core_pll_inv_2x_cust.vhd
new file mode 100755
index 0000000..8100dca
--- /dev/null
+++ b/pll/n2_core_pll_inv_2x_cust.vhd
@@ -0,0 +1,13 @@
+entity n2_core_pll_inv_2x_cust is
+port(
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_inv_2x_cust;
+architecture arch of n2_core_pll_inv_2x_cust is
+--vss='0';
+begin
+o <= not i;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_inv_32x_cust.vhd b/pll/n2_core_pll_inv_32x_cust.vhd
new file mode 100755
index 0000000..7efa2db
--- /dev/null
+++ b/pll/n2_core_pll_inv_32x_cust.vhd
@@ -0,0 +1,13 @@
+entity n2_core_pll_inv_32x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_inv_32x_cust;
+architecture arch of n2_core_pll_inv_32x_cust is
+--vss = '0';
+begin
+o <= not i;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_inv_4x_cust.vhd b/pll/n2_core_pll_inv_4x_cust.vhd
new file mode 100755
index 0000000..24c8611
--- /dev/null
+++ b/pll/n2_core_pll_inv_4x_cust.vhd
@@ -0,0 +1,13 @@
+entity n2_core_pll_inv_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_inv_4x_cust;
+architecture arch of n2_core_pll_inv_4x_cust is
+--vss = '0';
+begin
+o <= not i;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_inv_8x_cust.vhd b/pll/n2_core_pll_inv_8x_cust.vhd
new file mode 100755
index 0000000..578d2b3
--- /dev/null
+++ b/pll/n2_core_pll_inv_8x_cust.vhd
@@ -0,0 +1,13 @@
+entity n2_core_pll_inv_8x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_inv_8x_cust;
+architecture arch of n2_core_pll_inv_8x_cust is
+--vss = '0';
+begin
+o <= not i;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_lockdet_cust.vhd b/pll/n2_core_pll_lockdet_cust.vhd
new file mode 100755
index 0000000..c70d968
--- /dev/null
+++ b/pll/n2_core_pll_lockdet_cust.vhd
@@ -0,0 +1,17 @@
+entity n2_core_pll_lockdet_cust is
+port (
+pll_jtag_lock_everlose : out bit;
+l1clk : in bit;
+pll_lock_dyn : out bit;
+reset_in : in bit;
+slow : in bit;
+fast : in bit;
+pll_lock_pulse : out bit;
+ref_ck : in bit
+);
+end entity n2_core_pll_lockdet_cust;
+architecture arch of n2_core_pll_lockdet_cust is
+--supply1 vdd;
+begin
+end architecture arch;
+
diff --git a/pll/n2_core_pll_m1_cust.vhd b/pll/n2_core_pll_m1_cust.vhd
new file mode 100755
index 0000000..b47850d
--- /dev/null
+++ b/pll/n2_core_pll_m1_cust.vhd
@@ -0,0 +1,11 @@
+entity n2_core_pll_m1_cust is
+port (
+vdd_reg : in bit
+);
+end entity n2_core_pll_m1_cust;
+architecture arch of n2_core_pll_m1_cust is
+--vss = '1';
+begin
+
+end architecture arch;
+
diff --git a/pll/n2_core_pll_mux2_8x_cust.vhd b/pll/n2_core_pll_mux2_8x_cust.vhd
new file mode 100755
index 0000000..a8cf29e
--- /dev/null
+++ b/pll/n2_core_pll_mux2_8x_cust.vhd
@@ -0,0 +1,27 @@
+entity n2_core_pll_mux2_8x_cust is
+port (
+in0 : in bit;
+sel0 : in bit;
+dout : out bit;
+sel1 : in bit;
+in1 : in bit
+);
+end entity n2_core_pll_mux2_8x_cust;
+architecture arch of n2_core_pll_mux2_8x_cust is
+component mux2 is
+port (
+in0,in1,sel0,sel1 : in bit;
+y : out bit
+);
+end component mux2;
+begin
+x1 : mux2
+port map (
+sel0 => sel0,
+sel1 => sel1,
+in0 => in0,
+in1 => in1,
+y => dout
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_mux4_8x_cust.vhd b/pll/n2_core_pll_mux4_8x_cust.vhd
new file mode 100755
index 0000000..e91fe17
--- /dev/null
+++ b/pll/n2_core_pll_mux4_8x_cust.vhd
@@ -0,0 +1,50 @@
+entity n2_core_pll_mux4_8x_cust is
+port (
+sel2 : in bit;
+sel3 : in bit;
+in2 : in bit;
+in3 : in bit;
+sel0 : in bit;
+sel1 : in bit;
+dout : out bit;
+in0 : in bit;
+in1 : in bit
+);
+end entity n2_core_pll_mux4_8x_cust;
+architecture arch of n2_core_pll_mux4_8x_cust is
+component mux4 is
+generic (SIZE : integer := 1);
+port (
+dout : out bit_vector(SIZE-1 downto 0);
+in0 : in bit_vector(SIZE-1 downto 0);
+in1 : in bit_vector(SIZE-1 downto 0);
+in2 : in bit_vector(SIZE-1 downto 0);
+in3 : in bit_vector(SIZE-1 downto 0);
+sel0 : in bit;
+sel1 : in bit;
+sel2 : in bit;
+sel3 : in bit;
+muxtst : in bit
+);
+end component mux4;
+signal tin0,tin1,tin2,tin3,tdout : bit_vector(0 downto 0);
+begin
+tin0(0) <= in0;
+tin1(0) <= in1;
+tin2(0) <= in2;
+tin3(0) <= in3;
+dout <= tdout(0);
+x1 : mux4 port map (
+in0 => tin0,
+in1 => tin1,
+in2 => tin2,
+in3 => tin3,
+sel0 => sel0,
+sel1 => sel1,
+sel2 => sel2,
+sel3 => sel3,
+muxtst => '0',
+dout => tdout
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_mux8_8x_cust.vhd b/pll/n2_core_pll_mux8_8x_cust.vhd
new file mode 100755
index 0000000..bb983a9
--- /dev/null
+++ b/pll/n2_core_pll_mux8_8x_cust.vhd
@@ -0,0 +1,78 @@
+entity n2_core_pll_mux8_8x_cust is
+port (
+sel0 : in bit;
+in2 : in bit;
+sel2 : in bit;
+sel5 : in bit;
+in4 : in bit;
+sel7 : in bit;
+sel4 : in bit;
+in1 : in bit;
+dout : out bit;
+in0 : in bit;
+sel6 : in bit;
+in5 : in bit;
+in7 : in bit;
+sel3 : in bit;
+sel1 : in bit;
+in3 : in bit;
+in6 : in bit
+);
+end entity n2_core_pll_mux8_8x_cust;
+architecture arch of n2_core_pll_mux8_8x_cust is
+component mux8 is
+generic (SIZE : integer := 1);
+port (
+dout : out bit_vector(SIZE-1 downto 0);
+in0 : in bit_vector(SIZE-1 downto 0);
+in1 : in bit_vector(SIZE-1 downto 0);
+in2 : in bit_vector(SIZE-1 downto 0);
+in3 : in bit_vector(SIZE-1 downto 0);
+in4 : in bit_vector(SIZE-1 downto 0);
+in5 : in bit_vector(SIZE-1 downto 0);
+in6 : in bit_vector(SIZE-1 downto 0);
+in7 : in bit_vector(SIZE-1 downto 0);
+sel0 : in bit;
+sel1 : in bit;
+sel2 : in bit;
+sel3 : in bit;
+sel4 : in bit;
+sel5 : in bit;
+sel6 : in bit;
+sel7 : in bit;
+muxtst : in bit
+);
+end component mux8;
+signal tin0,tin1,tin2,tin3,tin4,tin5,tin6,tin7,tdout : bit_vector(0 downto 0);
+begin
+dout <= tdout(0);
+tin0(0) <= in0;
+tin1(0) <= in1;
+tin2(0) <= in2;
+tin3(0) <= in3;
+tin4(0) <= in4;
+tin5(0) <= in5;
+tin6(0) <= in6;
+tin7(0) <= in7;
+x1 : mux8
+port map (
+sel0 => sel0,
+sel1 => sel1,
+sel2 => sel2,
+sel3 => sel3,
+sel4 => sel4,
+sel5 => sel5,
+sel6 => sel6,
+sel7 => sel7,
+in0 => tin0,
+in1 => tin1,
+in2 => tin2,
+in3 => tin3,
+in4 => tin4,
+in5 => tin5,
+in6 => tin6,
+in7 => tin7,
+muxtst => '0',
+dout => tdout
+);
+end architecture arch;
diff --git a/pll/n2_core_pll_nand2_2x_cust.vhd b/pll/n2_core_pll_nand2_2x_cust.vhd
new file mode 100755
index 0000000..2e4d4b3
--- /dev/null
+++ b/pll/n2_core_pll_nand2_2x_cust.vhd
@@ -0,0 +1,14 @@
+entity n2_core_pll_nand2_2x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in1 : in bit;
+in0 : in bit
+);
+end entity n2_core_pll_nand2_2x_cust;
+architecture arch of n2_core_pll_nand2_2x_cust is
+--vss = '0';
+begin
+o <= not (in0 and in1);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_nand2_4x_cust.vhd b/pll/n2_core_pll_nand2_4x_cust.vhd
new file mode 100755
index 0000000..298b3d3
--- /dev/null
+++ b/pll/n2_core_pll_nand2_4x_cust.vhd
@@ -0,0 +1,14 @@
+entity n2_core_pll_nand2_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in1 : in bit;
+in0 : in bit
+);
+end entity n2_core_pll_nand2_4x_cust;
+architecture arch of n2_core_pll_nand2_4x_cust is
+--vss = '0';
+begin
+o <= not (in0 and in1);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_nand2_8x_cust.vhd b/pll/n2_core_pll_nand2_8x_cust.vhd
new file mode 100755
index 0000000..403558e
--- /dev/null
+++ b/pll/n2_core_pll_nand2_8x_cust.vhd
@@ -0,0 +1,14 @@
+entity n2_core_pll_nand2_8x_cust is
+port (
+vsup : in bit;
+o : out bit;
+in1 : in bit;
+in0 : in bit
+);
+end entity n2_core_pll_nand2_8x_cust;
+architecture arch of n2_core_pll_nand2_8x_cust is
+--vss = '0';
+begin
+o <= not (in0 and in1);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_nand3_2x_cust.vhd b/pll/n2_core_pll_nand3_2x_cust.vhd
new file mode 100755
index 0000000..4c03d78
--- /dev/null
+++ b/pll/n2_core_pll_nand3_2x_cust.vhd
@@ -0,0 +1,15 @@
+entity n2_core_pll_nand3_2x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in2 : in bit;
+in1 : in bit;
+in0 : in bit
+);
+end entity n2_core_pll_nand3_2x_cust;
+architecture arch of n2_core_pll_nand3_2x_cust is
+--vss = '0';
+begin
+o <= not (in0 and in1 and in2);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_nand4_4x_cust.vhd b/pll/n2_core_pll_nand4_4x_cust.vhd
new file mode 100755
index 0000000..c5a56bd
--- /dev/null
+++ b/pll/n2_core_pll_nand4_4x_cust.vhd
@@ -0,0 +1,16 @@
+entity n2_core_pll_nand4_4x_cust is
+port (
+in3 : in bit;
+o : out bit;
+in2 : in bit;
+in1 : in bit;
+in0 : in bit
+);
+end entity n2_core_pll_nand4_4x_cust;
+architecture arch of n2_core_pll_nand4_4x_cust is
+--supply1 vdd;
+--vss = '0';
+begin
+o <= not (in0 and in1 and in2 and in3);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_nor2_2x_cust.vhd b/pll/n2_core_pll_nor2_2x_cust.vhd
new file mode 100755
index 0000000..a6754ae
--- /dev/null
+++ b/pll/n2_core_pll_nor2_2x_cust.vhd
@@ -0,0 +1,14 @@
+entity n2_core_pll_nor2_2x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in1 : in bit;
+in0 : in bit
+);
+end entity n2_core_pll_nor2_2x_cust;
+architecture arch of n2_core_pll_nor2_2x_cust is
+--vss = '0';
+begin
+o <= not (in0 or in1);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_nor2_4x_cust.vhd b/pll/n2_core_pll_nor2_4x_cust.vhd
new file mode 100755
index 0000000..009d59a
--- /dev/null
+++ b/pll/n2_core_pll_nor2_4x_cust.vhd
@@ -0,0 +1,14 @@
+entity n2_core_pll_nor2_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in1 : in bit;
+in0 : in bit
+);
+end entity n2_core_pll_nor2_4x_cust;
+architecture arch of n2_core_pll_nor2_4x_cust is
+--vss = '0';
+begin
+o <= not (in0 or in1);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_nor3_2x_cust.vhd b/pll/n2_core_pll_nor3_2x_cust.vhd
new file mode 100755
index 0000000..b921295
--- /dev/null
+++ b/pll/n2_core_pll_nor3_2x_cust.vhd
@@ -0,0 +1,15 @@
+entity n2_core_pll_nor3_2x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in2 : in bit;
+in1 : in bit;
+in0 : in bit
+);
+end entity n2_core_pll_nor3_2x_cust;
+architecture arch of n2_core_pll_nor3_2x_cust is
+--vss = '0';
+begin
+o <= not (in0 or in1 or in2);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_pad_cluster_cust.vhd b/pll/n2_core_pll_pad_cluster_cust.vhd
new file mode 100755
index 0000000..2301b89
--- /dev/null
+++ b/pll/n2_core_pll_pad_cluster_cust.vhd
@@ -0,0 +1,11 @@
+entity n2_core_pll_pad_cluster_cust is
+port(
+vdd_hv15 : in bit;
+pll_sys_clk : in bit_vector(1 downto 0)
+);
+end entity n2_core_pll_pad_cluster_cust;
+architecture arch of n2_core_pll_pad_cluster_cust is
+--supply1 vdd ;
+begin
+end architecture arch;
+
diff --git a/pll/n2_core_pll_pecl_all_cust.vhd b/pll/n2_core_pll_pecl_all_cust.vhd
new file mode 100755
index 0000000..c23d9e0
--- /dev/null
+++ b/pll/n2_core_pll_pecl_all_cust.vhd
@@ -0,0 +1,262 @@
+entity n2_core_pll_pecl_all_cust is
+port (
+regdivcr : out bit;
+ref_ck : out bit;
+slow_l : out bit;
+fast : out bit;
+fast_l : out bit;
+pll_clamp_fltr : in bit;
+pll_lock_pulse : out bit;
+vdd_reg : in bit;
+fb_ck : out bit;
+pll_bypass_clk_en : in bit;
+ccu_serdes_dtm : in bit;
+l2clk : in bit;
+slow : out bit;
+slow_buf : out bit;
+pll_jtag_lock_everlose : out bit;
+pll_lock_dyn : out bit;
+raw_clk_byp : out bit;
+fast_buf : out bit;
+l2clkc : in bit;
+testmode : in bit;
+pll_arst_l : in bit;
+pll_div1 : in bit_vector(5 downto 0);
+pll_div2 : in bit_vector(5 downto 0);
+ref : out bit;
+fb : out bit;
+pll_sys_clk : in bit_vector(1 downto 0);
+l1clk_buf : out bit;
+pfd_reset : out bit;
+fltr : out bit
+);
+end entity n2_core_pll_pecl_all_cust;
+architecture arch of n2_core_pll_pecl_all_cust is
+--supply1 vdd;
+signal vdd,vss : bit;
+signal net0142,net0111 : bit_vector(5 downto 0);
+signal net0164 : bit;
+signal arst : bit_vector(1 downto 0);
+signal net0178,l1clk_p,net0207,regdiv,fb_ckn,ref_ck_lock,wirenet0164,bypass_clk,net0234,net0139,net153,net155,ref_ckn,net0110,l1clk,l1clk_l,net0118,fb_ck_lock,l1clk_n,net0120,net0122,net0124 : bit;
+component n2_core_pll_pecl_bypass_clk_cust is
+port (
+phase_ck : out bit;
+pecl_p : in bit;
+pecl_n : in bit
+);
+end component n2_core_pll_pecl_bypass_clk_cust;
+component n2_core_pll_delay_cust is
+port (
+vdd_reg : in bit;
+out_delcr : out bit;
+i : in bit;
+out_del : out bit
+);
+end component n2_core_pll_delay_cust;
+component n2_core_pll_tpm_cust is
+port (
+reset : in bit;
+ip : in bit_vector(5 downto 0);
+vdd_reg : in bit;
+op : out bit_vector(5 downto 0);
+sel : out bit;
+div_ck_i : in bit;
+pwr_rst : in bit;
+div_ck : out bit;
+vco_ck : in bit
+);
+end component n2_core_pll_tpm_cust;
+component n2_core_pll_inv_16x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_16x_cust;
+component n2_core_pll_inv_8x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_8x_cust;
+component n2_core_pll_buf_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_buf_4x_cust;
+component n2_core_pll_vdd_xing_buf_32x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_vdd_xing_buf_32x_cust;
+component n2_core_pll_vdd_xing_buf_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_vdd_xing_buf_4x_cust;
+component n2_core_pll_pecl_cust is
+port (
+vdd_reg : in bit;
+fb_ck : out bit;
+pecl_p : in bit;
+pecl_n : in bit;
+hdr_p : in bit;
+ref_ck : out bit;
+hdr_n : in bit
+);
+end component n2_core_pll_pecl_cust;
+component n2_core_pll_se2diff_mux_cust is
+port (
+vdd_reg : in bit;
+in1 : in bit;
+sel : in bit;
+o : out bit;
+in0 : in bit;
+out_l : out bit
+);
+end component n2_core_pll_se2diff_mux_cust;
+component imaginary_vco_gen is
+port (
+pll_arst_l : in bit;
+sysclk : in bit;
+fdbkclk : in bit;
+div : in bit_vector(5 downto 0);
+vco_out : out bit
+);
+end component imaginary_vco_gen;
+component n2_core_pll_pecl_enb_cust is
+port (
+i : in bit;
+o : out bit;
+enb1 : in bit;
+enb0 : in bit
+);
+end component n2_core_pll_pecl_enb_cust;
+signal tnet0142,tnet0111 : bit_vector(5 downto 0);
+signal tdiv : bit_vector(5 downto 0);
+signal tref,tfast : bit;
+begin
+ref <= tref;
+fast <= tfast;
+tdiv <= (pll_div2(4 downto 0)&"1");
+(net0142(0),net0142(1),net0142(2),net0142(3),net0142(4),net0142(5)) <= tnet0142;
+(net0111(0),net0111(1),net0111(2),net0111(3),net0111(4),net0111(5)) <= tnet0111;
+vdd <= '1';
+vss <= '0';
+x2 : n2_core_pll_pecl_bypass_clk_cust port map (
+phase_ck => bypass_clk,
+pecl_p => pll_sys_clk(0),
+pecl_n => pll_sys_clk(1)
+);
+xdel1 : n2_core_pll_delay_cust port map (
+vdd_reg => vdd_reg,
+out_delcr => regdivcr,
+i => pll_arst_l,
+out_del => regdiv
+);
+x8 : n2_core_pll_tpm_cust port map (
+ip => pll_div2,
+op => tnet0142,
+reset => arst(0),
+vdd_reg => vdd_reg,
+sel => net0120,
+div_ck_i => regdiv,
+pwr_rst => arst(1),
+div_ck => fb,
+vco_ck => fb_ckn
+);
+x9 : n2_core_pll_inv_16x_cust port map (
+vdd_reg => vdd,
+o => l1clk_buf,
+i => net0139
+);
+x1_1 : n2_core_pll_inv_8x_cust port map (
+vdd_reg => vdd_reg,
+o => arst(1),
+i => net0164
+);
+x12 : n2_core_pll_pecl_enb_cust port map (
+i => bypass_clk,
+o => raw_clk_byp,
+enb1 => ccu_serdes_dtm,
+enb0 => pll_bypass_clk_en
+);
+x13 : n2_core_pll_inv_16x_cust port map (
+vdd_reg => vdd_reg,
+o => l1clk_n,
+i => l1clk
+);
+x15 : n2_core_pll_buf_4x_cust port map (
+vdd_reg => vdd,
+o => net0139,
+i => l1clk_l
+);
+x16 : n2_core_pll_vdd_xing_buf_32x_cust port map (
+vdd_reg => vdd,
+o => fb_ck,
+i => fb_ckn
+);
+x17 : n2_core_pll_vdd_xing_buf_32x_cust port map (
+vdd_reg => vdd,
+o => ref_ck,
+i => ref_ckn
+);
+x18 : n2_core_pll_vdd_xing_buf_4x_cust port map (
+vdd_reg => vdd_reg,
+o => net0164,
+i => pll_arst_l
+);
+x19 : n2_core_pll_inv_16x_cust port map (
+vdd_reg => vdd_reg,
+o => l1clk_p,
+i => l1clk_l
+);
+xpcl : n2_core_pll_pecl_cust port map (
+vdd_reg => vdd_reg,
+fb_ck => fb_ckn,
+pecl_p => pll_sys_clk(0),
+pecl_n => pll_sys_clk(1),
+hdr_p => l1clk_p,
+ref_ck => ref_ckn,
+hdr_n => l1clk_n
+);
+xd1 : n2_core_pll_tpm_cust port map (
+ip => pll_div1,
+op => tnet0111,
+reset => arst(1),
+vdd_reg => vdd_reg,
+sel => net0110,
+div_ck_i => regdiv,
+pwr_rst => arst(0),
+div_ck => tref,
+vco_ck => ref_ckn
+);
+xil1clk_hdr : n2_core_pll_se2diff_mux_cust port map (
+vdd_reg => vdd,
+in1 => l2clk,
+sel => testmode,
+o => l1clk,
+in0 => l2clkc,
+out_l => l1clk_l
+);
+x1_0 : n2_core_pll_inv_8x_cust port map (
+vdd_reg => vdd_reg,
+o => arst(0),
+i => net0164
+);
+ivg : imaginary_vco_gen port map (
+pll_arst_l => pll_arst_l,
+sysclk => tref,
+fdbkclk => tfast,
+div => tdiv,
+vco_out => tfast
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_pecl_bypass_clk_cust.vhd b/pll/n2_core_pll_pecl_bypass_clk_cust.vhd
new file mode 100755
index 0000000..d24dd2f
--- /dev/null
+++ b/pll/n2_core_pll_pecl_bypass_clk_cust.vhd
@@ -0,0 +1,13 @@
+entity n2_core_pll_pecl_bypass_clk_cust is
+port (
+phase_ck : out bit;
+pecl_p : in bit;
+pecl_n : in bit
+);
+end entity n2_core_pll_pecl_bypass_clk_cust;
+architecture arch of n2_core_pll_pecl_bypass_clk_cust is
+--supply1 vdd;
+begin
+phase_ck <= pecl_p;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_pecl_cust.vhd b/pll/n2_core_pll_pecl_cust.vhd
new file mode 100755
index 0000000..ad46a4d
--- /dev/null
+++ b/pll/n2_core_pll_pecl_cust.vhd
@@ -0,0 +1,18 @@
+entity n2_core_pll_pecl_cust is
+port (
+vdd_reg : in bit;
+fb_ck : out bit;
+pecl_p : in bit;
+pecl_n : in bit;
+hdr_p : in bit;
+ref_ck : out bit;
+hdr_n : in bit
+);
+end entity n2_core_pll_pecl_cust;
+architecture arch of n2_core_pll_pecl_cust is
+--vss = '0';
+begin
+ref_ck <= pecl_p;
+fb_ck <= hdr_p;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_pecl_enb_cust.vhd b/pll/n2_core_pll_pecl_enb_cust.vhd
new file mode 100755
index 0000000..2f4fcf5
--- /dev/null
+++ b/pll/n2_core_pll_pecl_enb_cust.vhd
@@ -0,0 +1,64 @@
+entity n2_core_pll_pecl_enb_cust is
+port (
+i : in bit;
+o : out bit;
+enb1 : in bit;
+enb0 : in bit
+);
+end entity n2_core_pll_pecl_enb_cust;
+architecture arch of n2_core_pll_pecl_enb_cust is
+--supply1 vdd;
+signal net10,net12,net8 : bit;
+signal vdd : bit;
+component n2_core_pll_nand2_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in1 : in bit;
+in0 : in bit
+);
+end component n2_core_pll_nand2_4x_cust;
+component n2_core_pll_inv_16x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_16x_cust;
+component cl_u1_nor2_2x is
+port (
+in0 : in bit;
+in1 : in bit;
+o : out bit
+);
+end component cl_u1_nor2_2x;
+component cl_u1_inv_2x is
+port (
+i : in bit;
+o : out bit
+);
+end component cl_u1_inv_2x;
+begin
+vdd <= '1';
+x12 : n2_core_pll_nand2_4x_cust port map (
+vdd_reg => vdd,
+o => net8,
+in1 => net10,
+in0 => i
+);
+x22 : n2_core_pll_inv_16x_cust port map (
+vdd_reg => vdd,
+o => o,
+i => net8
+);
+x0 : cl_u1_nor2_2x port map (
+o => net12,
+in1 => enb0,
+in0 => enb1
+);
+x1 : cl_u1_inv_2x port map (
+o => net10,
+i => net12
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_pfd_cust.vhd b/pll/n2_core_pll_pfd_cust.vhd
new file mode 100755
index 0000000..b588404
--- /dev/null
+++ b/pll/n2_core_pll_pfd_cust.vhd
@@ -0,0 +1,21 @@
+entity n2_core_pll_pfd_cust is
+port (
+vdd_reg : in bit;
+f_buf : out bit;
+f_buf_l : out bit;
+fast_l : out bit;
+clamp_fltr : in bit;
+s_buf : out bit;
+s_buf_l : out bit;
+slow_l : out bit;
+slow : out bit;
+fast : out bit;
+pfd_reset : out bit;
+fb : in bit;
+ref : in bit
+);
+end entity n2_core_pll_pfd_cust;
+architecture arch of n2_core_pll_pfd_cust is
+begin
+end architecture arch;
+
diff --git a/pll/n2_core_pll_se2diff_mux_cust.vhd b/pll/n2_core_pll_se2diff_mux_cust.vhd
new file mode 100755
index 0000000..bfac218
--- /dev/null
+++ b/pll/n2_core_pll_se2diff_mux_cust.vhd
@@ -0,0 +1,19 @@
+entity n2_core_pll_se2diff_mux_cust is
+port (
+vdd_reg : in bit;
+in1 : in bit;
+sel : in bit;
+o : out bit;
+in0 : in bit;
+out_l : out bit
+);
+end entity n2_core_pll_se2diff_mux_cust;
+architecture arch of n2_core_pll_se2diff_mux_cust is
+--vss = '0';
+signal ot : bit;
+begin
+ot <= in1 when sel = '1' else in0 when sel = '0';
+o <= ot;
+out_l <= not ot;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_tpm1_cust.vhd b/pll/n2_core_pll_tpm1_cust.vhd
new file mode 100755
index 0000000..3cbd9f7
--- /dev/null
+++ b/pll/n2_core_pll_tpm1_cust.vhd
@@ -0,0 +1,262 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+entity n2_core_pll_tpm1_cust is
+port (
+nreset : in bit;
+ca2_a1 : in bit;
+cac_l : out bit;
+reset : in bit;
+sel_l : out bit;
+sel : out bit;
+ip : in bit_vector(2 downto 0);
+vco_ck : in bit
+);
+end entity n2_core_pll_tpm1_cust;
+architecture arch of n2_core_pll_tpm1_cust is
+component n2_core_pll_flop_reset2_cust is
+port (
+d : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end component n2_core_pll_flop_reset2_cust;
+component cl_u1_inv_8x is
+port (
+i : in bit;
+o : out bit
+);
+end component cl_u1_inv_8x;
+component n2_core_pll_inv1_16x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv1_16x_cust;
+component n2_core_pll_tpm_mux1_cust is
+port (
+sel_l : in bit;
+vdd_reg : in bit;
+out_l : out bit;
+d0 : in bit;
+d1 : in bit;
+sel : in bit
+);
+end component n2_core_pll_tpm_mux1_cust;
+component n2_core_pll_inv_32x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_32x_cust;
+component n2_core_pll_flop_reset1_cust is
+port (
+reset_val_l : in bit;
+d : in bit;
+reset : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end component n2_core_pll_flop_reset1_cust;
+component cl_u1_nand2_8x
+port (
+in0 : in bit;
+in1 : in bit;
+o : out bit
+);
+end component cl_u1_nand2_8x;
+component n2_core_pll_inv1_32x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv1_32x_cust;
+component cl_u1_inv_1x
+port (
+i : in bit;
+o : out bit
+);
+end component cl_u1_inv_1x;
+component cl_u1_nand2_2x
+port (
+in0 : in bit;
+in1 : in bit;
+o : out bit
+);
+end component cl_u1_nand2_2x;
+component n2_core_pll_nand2_8x_cust is
+port (
+vsup : in bit;
+o : out bit;
+in1 : in bit;
+in0 : in bit
+);
+end component n2_core_pll_nand2_8x_cust;
+--supply1 vdd;
+--vss = '0';
+signal vdd : bit;
+signal vss : bit;
+signal tcac_l : bit;
+signal d3,q0_l,q1_l,q2_l,net75,q3_l,vco_ck_l,ca3,net121,d22,net128,d22_l,net130,net132,net0165,net137,net143,sel1,qa2_l,q0,q1,q2,q3,l1clk,net173,net174,sel1_q,d0,d1,d2 : bit;
+begin
+vdd <= '1';
+vss <= '0';
+cac_l <= tcac_l;
+x2 : n2_core_pll_flop_reset2_cust port map (
+d => ca2_a1,
+clk => vco_ck,
+q_l => net174,
+q => qa2_l
+);
+x3 : cl_u1_inv_8x port map (
+o => vco_ck_l,
+i => vco_ck
+);
+x4 : n2_core_pll_inv1_16x_cust port map (
+vdd_reg => vdd,
+o => d22,
+i => q0
+);
+x5 : n2_core_pll_tpm_mux1_cust port map (
+sel_l => d22_l,
+vdd_reg => vdd,
+out_l => d1,
+d0 => net132,
+d1 => q2_l,
+sel => d22
+);
+x6 : n2_core_pll_flop_reset2_cust port map (
+d => sel1,
+clk => vco_ck_l,
+q_l => net121,
+q => sel1_q
+);
+x7 : n2_core_pll_inv_32x_cust port map (
+vdd_reg => vdd,
+o => l1clk,
+i => net137
+);
+x8 : n2_core_pll_flop_reset1_cust port map (
+reset_val_l => vss,
+d => d1,
+reset => reset,
+clk => l1clk,
+q_l => q1_l,
+q => q1
+);
+x9 : n2_core_pll_flop_reset2_cust port map (
+d => ca3,
+clk => vco_ck_l,
+q_l => net173,
+q => tcac_l
+);
+x10 : cl_u1_nand2_8x port map (
+o => ca3 ,
+in1 => qa2_l,
+in0 => sel1
+);
+x11 : n2_core_pll_tpm_mux1_cust port map (
+sel_l => d22_l,
+vdd_reg => vdd,
+out_l => d2,
+d0 => vdd,
+d1 => q3_l,
+sel => d22
+);
+x12 : n2_core_pll_flop_reset1_cust port map (
+reset_val_l => vss,
+d => d3,
+reset => nreset,
+clk => l1clk,
+q_l => q3_l,
+q => q3
+);
+x13 : n2_core_pll_inv1_32x_cust port map (
+vdd_reg => vdd,
+o => sel_l,
+i => net143
+);
+x14 : cl_u1_nand2_8x port map (
+o => net143,
+in1 => sel1_q,
+in0 => vco_ck
+);
+x15 :cl_u1_inv_1x port map (
+o => net130,
+i => ip(2)
+);
+x16 : n2_core_pll_tpm_mux1_cust port map (
+sel_l => d22_l,
+vdd_reg => vdd,
+out_l => d3,
+d0 => ip(0),
+d1 => vss,
+sel => d22
+);
+x17 : n2_core_pll_inv1_16x_cust port map (
+vdd_reg => vdd,
+o => d22_l,
+i => q0_l
+);
+x18 : cl_u1_nand2_2x port map (
+o => net132,
+in1 => net130,
+in0 => net128
+);
+x19 : cl_u1_inv_1x port map (
+o => net128,
+i => ip(0)
+);
+x20 : cl_u1_inv_1x port map (
+o => net0165,
+i => ip(1)
+);
+x22 : n2_core_pll_flop_reset1_cust port map (
+reset_val_l => vss,
+d => d22,
+reset => reset,
+clk => vco_ck,
+q_l => sel1,
+q => net75
+);
+x36 : n2_core_pll_tpm_mux1_cust port map (
+sel_l => d22_l,
+vdd_reg => vdd,
+out_l => d0,
+d0 => vdd,
+d1 => q1_l,
+sel => d22
+);
+x45 : n2_core_pll_flop_reset1_cust port map (
+reset_val_l => vss,
+d => d0,
+reset => reset,
+clk => l1clk,
+q_l => q0_l,
+q => q0
+);
+x46 : n2_core_pll_flop_reset1_cust port map (
+reset_val_l => vss,
+d => d2,
+reset => nreset,
+clk => l1clk,
+q_l => q2_l,
+q => q2
+);
+x0 : n2_core_pll_nand2_8x_cust port map (
+vsup => vdd,
+o => net137,
+in1 => tcac_l,
+in0 => vco_ck
+);
+x1 : n2_core_pll_inv1_16x_cust port map (
+vdd_reg => vdd,
+o => sel,
+i => net75
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_tpm3_all_cust.vhd b/pll/n2_core_pll_tpm3_all_cust.vhd
new file mode 100755
index 0000000..d002543
--- /dev/null
+++ b/pll/n2_core_pll_tpm3_all_cust.vhd
@@ -0,0 +1,251 @@
+entity n2_core_pll_tpm3_all_cust is
+port (
+pll_stretch_a : in bit;
+ccu_serdes_dtm : in bit;
+dr_ext_clk : in bit;
+dc_clk : out bit;
+pll_clk_out_l : out bit;
+pll_div3 : in bit_vector(5 downto 0);
+pll_sdel : in bit_vector(1 downto 0);
+pll_sel_a : in bit_vector(1 downto 0);
+pll_bypass_clk_en : in bit;
+pll_arst_l : in bit;
+dr_clk_out : out bit;
+pll_bypass_clk : in bit;
+pll_clk_out : out bit;
+dr_clk_out_l : out bit;
+dr_stretch_a : in bit;
+pll_testmode : in bit;
+dr_sdel : in bit_vector(1 downto 0);
+vco8_clk : out bit;
+dr_sel_a : in bit_vector(1 downto 0);
+volb : in bit;
+vco2_clk : out bit;
+pll_ext_clk : in bit;
+pll_div4 : in bit_vector(6 downto 0);
+dft_rst_a_l : in bit
+);
+end entity n2_core_pll_tpm3_all_cust;
+architecture arch of n2_core_pll_tpm3_all_cust is
+--supply1 vdd ;
+--supply0 vss ;
+signal vdd,vss : bit;
+signal net077 : bit_vector(1 downto 0);
+signal net080,tnet080 : bit_vector(5 downto 0);
+signal rst : bit_vector(1 downto 1);
+signal rst_l : bit_vector(0 downto 0);
+signal net088,net0100,net0103,net0104,net095,arst_d_l,net096,net097,net098,pll1_clk,
+dr_byp_clk,net0153,net042,dr1_clk,d4int_out,net069,vco_clk,pll_byp_clk : bit;
+component n2_core_pll_ckmux_cust is
+port (
+pll_sdel : in bit_vector(1 downto 0);
+ckt_drv_int : out bit;
+cktree_drv_l : out bit;
+ext_clk : in bit;
+dft_rst_a_l : in bit;
+dft_rst_l : out bit;
+bypass_pll_clk : in bit;
+psel1 : out bit;
+psel0 : out bit;
+stretch_a : in bit;
+async_reset : in bit;
+cktree_drv : out bit;
+pll1_clk : in bit;
+pll_sel : in bit_vector(1 downto 0);
+bypass_clk : in bit
+);
+end component n2_core_pll_ckmux_cust;
+component n2_core_pll_byp_enb_cust is
+port (
+sel1 : in bit;
+in1 : in bit;
+out1 : out bit;
+out0 : out bit;
+in0 : in bit;
+sel0 : in bit
+);
+end component n2_core_pll_byp_enb_cust;
+component n2_core_pll_div4_cust is
+port (
+clk : in bit;
+arst_l : in bit;
+clk_div_out : out bit
+);
+end component n2_core_pll_div4_cust;
+component n2_core_pll_inv_32x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_32x_cust;
+component n2_core_pll_inv_16x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_16x_cust;
+component n2_core_pll_tpm3_cust is
+port (
+reset : in bit;
+ip : in bit_vector(5 downto 0);
+vdd_reg : in bit;
+op : out bit_vector(5 downto 0);
+sel : out bit;
+div_ck_i : in bit;
+pwr_rst : in bit;
+div_ck : out bit;
+vco_ck : in bit
+);
+end component n2_core_pll_tpm3_cust;
+component n2_core_pll_tpm3_sync_cust is
+port (
+dri1_clk : in bit;
+dft_rst_l : in bit;
+dc_clk : out bit;
+d4int_out : out bit;
+ccu_serdes_dtm : in bit;
+arst_l : in bit;
+arst : out bit;
+vco_clk : out bit;
+pll1_clk : in bit;
+arst_d_l : out bit;
+a : in bit_vector(2 downto 2);
+rst_l : out bit_vector(0 downto 0);
+rst : out bit_vector(1 downto 1);
+volb : in bit
+);
+end component n2_core_pll_tpm3_sync_cust;
+component n2_core_pll_inv_1x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_1x_cust;
+component n2_core_pll_d4_frac_cust is
+port (
+dft_rst_l : in bit;
+vco_clk : in bit;
+a : in bit_vector(4 downto 0);
+out_clk : out bit
+);
+end component n2_core_pll_d4_frac_cust;
+begin
+(net080(0),net080(1),net080(2),net080(3),net080(4),net080(5)) <= tnet080;
+vdd <= '1';
+vss <= '0';
+x2 : n2_core_pll_ckmux_cust
+port map (
+pll_sdel => pll_sdel,
+pll_sel => pll_sel_a,
+ckt_drv_int => net0104,
+cktree_drv_l => pll_clk_out_l,
+ext_clk => pll_ext_clk,
+dft_rst_a_l => vdd,
+dft_rst_l => net0153,
+bypass_pll_clk => pll_bypass_clk_en,
+psel1 => net0103,
+psel0 => net096,
+stretch_a => pll_stretch_a,
+async_reset => net095,
+cktree_drv => pll_clk_out,
+pll1_clk => pll1_clk,
+bypass_clk => pll_byp_clk
+);
+x3 : n2_core_pll_byp_enb_cust
+port map (
+sel1 => ccu_serdes_dtm,
+in1 => pll_bypass_clk,
+out1 => dr_byp_clk,
+out0 => pll_byp_clk,
+in0 => pll_bypass_clk,
+sel0 => pll_bypass_clk_en
+);
+x4 : n2_core_pll_ckmux_cust
+port map (
+pll_sdel => dr_sdel,
+pll_sel => dr_sel_a,
+ckt_drv_int => net098,
+cktree_drv_l => dr_clk_out_l,
+ext_clk => dr_ext_clk,
+dft_rst_a_l => vdd,
+dft_rst_l => net097,
+bypass_pll_clk => ccu_serdes_dtm,
+psel1 => net0100,
+psel0 => net042,
+stretch_a => dr_stretch_a,
+async_reset => net095,
+cktree_drv => dr_clk_out,
+pll1_clk => dr1_clk,
+bypass_clk => dr_byp_clk
+);
+x5 : n2_core_pll_div4_cust
+port map (
+clk => pll1_clk,
+arst_l => pll_testmode,
+clk_div_out => vco8_clk
+);
+x6 : n2_core_pll_inv_32x_cust
+port map (
+vdd_reg => vdd,
+o => vco2_clk,
+i => net069
+);
+x7 : n2_core_pll_inv_16x_cust
+port map (
+vdd_reg => vdd,
+o => net069,
+i => pll1_clk
+);
+xd3 : n2_core_pll_tpm3_cust
+port map (
+ip => pll_div3,
+op => tnet080,
+reset => net095,
+vdd_reg => vdd,
+sel => net088,
+div_ck_i => vdd,
+pwr_rst => vdd,
+div_ck => pll1_clk,
+vco_ck => vco_clk
+);
+x11_0 : n2_core_pll_inv_1x_cust
+port map (
+vdd_reg => vdd,
+o => net077(1),
+i => pll_div4(5)
+);
+x11_1 : n2_core_pll_inv_1x_cust
+port map (
+vdd_reg => vdd,
+o => net077(0),
+i => pll_div4(6)
+);
+x0 : n2_core_pll_tpm3_sync_cust
+port map (
+a => pll_div4(2 downto 2),
+rst_l => rst_l(0 downto 0),
+rst => rst(1 downto 1),
+dri1_clk => vss,
+dft_rst_l => dft_rst_a_l,
+dc_clk => dc_clk,
+d4int_out => d4int_out,
+ccu_serdes_dtm => vss,
+arst_l => pll_arst_l,
+arst => net095,
+vco_clk => vco_clk,
+pll1_clk => pll1_clk,
+arst_d_l => arst_d_l,
+volb => volb
+);
+x1 : n2_core_pll_d4_frac_cust
+port map (
+a => pll_div4(4 downto 0),
+dft_rst_l => rst_l(0),
+vco_clk => vco_clk,
+out_clk => dr1_clk
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_tpm3_cust.vhd b/pll/n2_core_pll_tpm3_cust.vhd
new file mode 100755
index 0000000..4bf65ec
--- /dev/null
+++ b/pll/n2_core_pll_tpm3_cust.vhd
@@ -0,0 +1,503 @@
+entity n2_core_pll_tpm3_cust is
+port (
+reset : in bit;
+ip : in bit_vector(5 downto 0);
+vdd_reg : in bit;
+op : out bit_vector(5 downto 0);
+sel : out bit;
+div_ck_i : in bit;
+pwr_rst : in bit;
+div_ck : out bit;
+vco_ck : in bit
+);
+end entity n2_core_pll_tpm3_cust;
+architecture arch of n2_core_pll_tpm3_cust is
+--vss = '0';
+signal vss,vdd : bit;
+signal tsel : bit;
+signal net183,nz_2,net201,net282,nz_3,nz_4,nz_5,net186,net205,f4q,f5d,net195,vco_ckb,vco_ckd,net198,f5q,r_gate,reset_d,net0362,net235,zero_0,net236,zero_1,zero_2,f0d,zero_3,zero_4,zero_5,sel_b,f0q,net147,f1d,net252,net256,net0248,net159,f1q,f2d,nzero_0,nzero_1,net162,nzero_2,nzero_3,nzero_4,nzero_5,f2q,next0,next1,next2,next3,f3d,next4,next5,net171,nip0,nip1,nip2,nip3,nip4,nip5,net0501,f3q,net0502,net0503,net0504,f4d,net0505,net0506,nz_0,nz_1 : bit;
+component n2_core_pll_buf_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_buf_4x_cust;
+component n2_core_pll_buf_16x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_buf_16x_cust;
+component n2_core_pll_tpm_mux_cust is
+port (
+opb : out bit;
+vdd_reg : in bit;
+op : out bit;
+d0 : in bit;
+d1 : in bit;
+sel : in bit;
+sel_b : in bit
+);
+end component n2_core_pll_tpm_mux_cust;
+component n2_core_pll_buf_8x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_buf_8x_cust;
+component n2_core_pll_inv_8x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_8x_cust;
+component n2_core_pll_tpm_next_new_cust is
+port (
+vdd_reg : in bit;
+d5 : out bit;
+q0b : in bit;
+q3b : in bit;
+d3 : out bit;
+q5b : in bit;
+q1b : in bit;
+q2b : in bit;
+d2 : out bit;
+d0 : out bit;
+d4 : out bit;
+q2 : in bit;
+q0 : in bit;
+q1 : in bit;
+d1 : out bit;
+q4b : in bit
+);
+end component n2_core_pll_tpm_next_new_cust;
+component n2_core_pll_tpm_gate2_cust is
+port (
+vdd_reg : in bit;
+div_ck : out bit;
+r : in bit;
+ck : in bit
+);
+end component n2_core_pll_tpm_gate2_cust;
+component n2_core_pll_flop_reset_new_cust is
+port (
+vdd_reg : in bit;
+reset_val_l : in bit;
+d : in bit;
+reset : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end component n2_core_pll_flop_reset_new_cust;
+component n2_core_pll_inv_32x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_32x_cust;
+component n2_core_pll_tpm_zd1_cust is
+port (
+vdd_reg : in bit;
+zero1 : out bit;
+zero1_b : out bit;
+q4b : in bit;
+q0b : in bit;
+q1b : in bit;
+q2b : in bit;
+q3b : in bit;
+q5b : in bit
+);
+end component n2_core_pll_tpm_zd1_cust;
+component n2_core_pll_tpm_nzd_cust is
+port (
+vdd_reg : in bit;
+q2b : in bit;
+q4b : in bit;
+q3b : in bit;
+zero : out bit;
+q1b : in bit;
+q0b : in bit;
+q5b : in bit
+);
+end component n2_core_pll_tpm_nzd_cust;
+component n2_core_pll_inv_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_4x_cust;
+signal top : bit_vector(5 downto 0);
+begin
+vdd <= '1';
+vss <= '0';
+op <= top;
+sel <= tsel;
+x2 : n2_core_pll_buf_4x_cust port map (
+vdd_reg => vdd_reg,
+o => net205,
+i => ip(0)
+);
+x4 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd_reg,
+o => reset_d,
+i => reset
+);
+x5 : n2_core_pll_tpm_mux_cust port map (
+opb => nzero_0,
+vdd_reg => vdd_reg,
+op => nz_0,
+d0 => ip(0),
+d1 => nip0,
+sel => net256,
+sel_b => net282
+);
+x6 : n2_core_pll_buf_8x_cust port map (
+vdd_reg => vdd_reg,
+o => net282,
+i => pwr_rst
+);
+x7 : n2_core_pll_inv_8x_cust port map (
+vdd_reg => vdd_reg,
+o => net256,
+i => pwr_rst
+);
+x8 : n2_core_pll_buf_4x_cust port map (
+vdd_reg => vdd_reg,
+o => net183,
+i => ip(1)
+);
+x9 : n2_core_pll_buf_4x_cust port map (
+vdd_reg => vdd_reg,
+o => net195,
+i => ip(2)
+);
+x10 : n2_core_pll_buf_4x_cust port map (
+vdd_reg => vdd_reg,
+o => net159,
+i => ip(3)
+);
+x11 : n2_core_pll_buf_4x_cust port map (
+vdd_reg => vdd_reg,
+o => net147,
+i => ip(4)
+);
+x12 : n2_core_pll_buf_4x_cust port map (
+vdd_reg => vdd_reg,
+o => net171,
+i => ip(5)
+);
+x13 : n2_core_pll_buf_8x_cust port map (
+vdd_reg => vdd_reg,
+o => top(0),
+i => nip0
+);
+x14 : n2_core_pll_buf_8x_cust port map (
+vdd_reg => vdd_reg,
+o => top(1),
+i => nip1
+);
+x15 : n2_core_pll_buf_8x_cust port map (
+vdd_reg => vdd_reg,
+o => top(2),
+i => nip2
+);
+x16 : n2_core_pll_tpm_next_new_cust port map (
+vdd_reg => vdd_reg,
+d5 => next5,
+q0b => zero_0,
+q3b => zero_3,
+d3 => next3,
+q5b => zero_5,
+q1b => zero_1,
+q2b => zero_2,
+d2 => next2,
+d0 => next0,
+d4 => next4,
+q2 => f2q,
+q0 => f0q,
+q1 => f1q,
+d1 => next1,
+q4b => zero_4
+);
+x17 : n2_core_pll_tpm_mux_cust port map (
+opb => nzero_1,
+vdd_reg => vdd_reg,
+op => nz_1,
+d0 => ip(1),
+d1 => nip1,
+sel => net256,
+sel_b => net282
+);
+x18 : n2_core_pll_buf_8x_cust port map (
+vdd_reg => vdd_reg,
+o => top(3),
+i => nip3
+);
+x19 : n2_core_pll_buf_8x_cust port map (
+vdd_reg => vdd_reg,
+o => top(4),
+i => nip4
+);
+x20 : n2_core_pll_buf_8x_cust port map (
+vdd_reg => vdd_reg,
+o => top(5),
+i => nip5
+);
+x23 : n2_core_pll_tpm_mux_cust port map (
+opb => nzero_2,
+vdd_reg => vdd_reg,
+op => nz_2,
+d0 => ip(2),
+d1 => nip2,
+sel => net256,
+sel_b => net282
+);
+x24 : n2_core_pll_tpm_gate2_cust port map (
+vdd_reg => vdd_reg,
+div_ck => div_ck,
+r => r_gate,
+ck => vco_ck
+);
+x25 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => net205,
+reset => reset_d,
+clk => div_ck_i,
+q_l => net201,
+q => nip0
+);
+x26 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => net183,
+reset => reset_d,
+clk => div_ck_i,
+q_l => net186,
+q => nip1
+);
+x27 : n2_core_pll_tpm_mux_cust port map (
+opb => nzero_3,
+vdd_reg => vdd_reg,
+op => nz_3,
+d0 => ip(3),
+d1 => nip3,
+sel => net256,
+sel_b => net282
+);
+x28 : n2_core_pll_tpm_mux_cust port map (
+opb => nzero_4,
+vdd_reg => vdd_reg,
+op => nz_4,
+d0 => ip(4),
+d1 => nip4,
+sel => net256,
+sel_b => net282
+);
+x29 : n2_core_pll_tpm_mux_cust port map (
+opb => nzero_5,
+vdd_reg => vdd_reg,
+op => nz_5,
+d0 => ip(5),
+d1 => nip5,
+sel => net256,
+sel_b => net282
+);
+x30 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => net195,
+reset => reset_d,
+clk => div_ck_i,
+q_l => net198,
+q => nip2
+);
+x31 : n2_core_pll_inv_32x_cust port map (
+vdd_reg => vdd_reg,
+o => vco_ckd,
+i => net252
+);
+x32 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => net159,
+reset => reset_d,
+clk => div_ck_i,
+q_l => net162,
+q => nip3
+);
+x33 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => net147,
+reset => reset_d,
+clk => div_ck_i,
+q_l => net235,
+q => nip4
+);
+x34 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => net171,
+reset => reset_d,
+clk => div_ck_i,
+q_l => net236,
+q => nip5
+);
+x36 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => f1d,
+reset => reset_d,
+clk => vco_ckd,
+q_l => zero_1,
+q => f1q
+);
+x37 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => f2d,
+reset => reset_d,
+clk => vco_ckd,
+q_l => zero_2,
+q => f2q
+);
+x38 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => f3d,
+reset => reset_d,
+clk => vco_ckd,
+q_l => zero_3,
+q => f3q
+);
+x39 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => f4d,
+reset => reset_d,
+clk => vco_ckd,
+q_l => zero_4,
+q => f4q
+);
+x40 : n2_core_pll_tpm_zd1_cust port map (
+vdd_reg => vdd_reg,
+zero1 => tsel,
+zero1_b => sel_b,
+q4b => zero_4,
+q0b => zero_0,
+q1b => zero_1,
+q2b => zero_2,
+q3b => zero_3,
+q5b => zero_5
+);
+x41 : n2_core_pll_inv_8x_cust port map (
+vdd_reg => vdd_reg,
+o => net252,
+i => vco_ck
+);
+x42 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => f5d,
+reset => reset_d,
+clk => vco_ckd,
+q_l => zero_5,
+q => f5q
+);
+x43 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vss,
+d => tsel,
+reset => reset_d,
+clk => vco_ckb,
+q_l => r_gate,
+q => net0248
+);
+x44 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => f0d,
+reset => reset_d,
+clk => vco_ckd,
+q_l => zero_0,
+q => f0q
+);
+x47 : n2_core_pll_tpm_mux_cust port map (
+opb => net0506,
+vdd_reg => vdd_reg,
+op => f0d,
+d0 => next0,
+d1 => nz_0,
+sel => tsel,
+sel_b => sel_b
+);
+x48 : n2_core_pll_tpm_mux_cust port map (
+opb => net0505,
+vdd_reg => vdd_reg,
+op => f1d,
+d0 => next1,
+d1 => nz_1,
+sel => tsel,
+sel_b => sel_b
+);
+x49 : n2_core_pll_tpm_nzd_cust port map (
+vdd_reg => vdd_reg,
+q2b => nzero_2,
+q4b => nzero_4,
+q3b => nzero_3,
+zero => net0362,
+q1b => nzero_1,
+q0b => nzero_0,
+q5b => nzero_5
+);
+x50 : n2_core_pll_tpm_mux_cust port map (
+opb => net0504,
+vdd_reg => vdd_reg,
+op => f2d,
+d0 => next2,
+d1 => nz_2,
+sel => tsel,
+sel_b => sel_b
+);
+x51 : n2_core_pll_tpm_mux_cust port map (
+opb => net0503,
+vdd_reg => vdd_reg,
+op => f3d,
+d0 => next3,
+d1 => nz_3,
+sel => tsel,
+sel_b => sel_b
+);
+x52 : n2_core_pll_tpm_mux_cust port map (
+opb => net0502,
+vdd_reg => vdd_reg,
+op => f4d,
+d0 => next4,
+d1 => nz_4,
+sel => tsel,
+sel_b => sel_b
+);
+x53 : n2_core_pll_tpm_mux_cust port map (
+opb => net0501,
+vdd_reg => vdd_reg,
+op => f5d,
+d0 => next5,
+d1 => nz_5,
+sel => tsel,
+sel_b => sel_b
+);
+x1 : n2_core_pll_inv_4x_cust port map (
+vdd_reg => vdd_reg,
+o => vco_ckb,
+i => vco_ckd
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_tpm3_sync_cust.vhd b/pll/n2_core_pll_tpm3_sync_cust.vhd
new file mode 100755
index 0000000..b5efda2
--- /dev/null
+++ b/pll/n2_core_pll_tpm3_sync_cust.vhd
@@ -0,0 +1,212 @@
+entity n2_core_pll_tpm3_sync_cust is
+port (
+dri1_clk : in bit;
+dft_rst_l : in bit;
+dc_clk : out bit;
+d4int_out : out bit;
+ccu_serdes_dtm : in bit;
+arst_l : in bit;
+arst : out bit;
+vco_clk : out bit;
+pll1_clk : in bit;
+arst_d_l : out bit;
+a : in bit_vector(2 downto 2);
+rst_l : out bit_vector(0 downto 0);
+rst : out bit_vector(1 downto 1);
+volb : in bit
+);
+end entity n2_core_pll_tpm3_sync_cust;
+architecture arch of n2_core_pll_tpm3_sync_cust is
+--supply1 vdd;
+--supply0 vss;
+signal vdd,vss : bit;
+signal rstpa,rstpb : bit_vector(1 downto 1);
+signal rstp_l,rstp,rstp1,net127 : bit_vector(1 downto 0);
+signal net77,net110,net79,net112,net115,net116,net81,net120,vco_clk_d,net63,vco_out,net69 : bit;
+signal tdc_clk : bit;
+component n2_core_pll_inv1_16x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv1_16x_cust;
+component cl_u1_nand2_8x is
+port (
+in0 : in bit;
+in1 : in bit;
+o : out bit
+);
+end component cl_u1_nand2_8x;
+component n2_core_pll_fse2diff_out_cust is
+port (
+vdd_reg : in bit;
+i : in bit;
+out_l : out bit;
+o : out bit
+);
+end component n2_core_pll_fse2diff_out_cust;
+component cl_u1_inv_4x is
+port (
+i : in bit;
+o : out bit
+);
+end component cl_u1_inv_4x;
+component cl_u1_inv_2x is
+port (
+i : in bit;
+o : out bit
+);
+end component cl_u1_inv_2x;
+component n2_core_pll_flop_reset1_cust is
+port(
+reset_val_l : in bit;
+d : in bit;
+reset : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end component n2_core_pll_flop_reset1_cust;
+component n2_core_pll_tpm_mux_cust is
+port (
+opb : out bit;
+vdd_reg : in bit;
+op : out bit;
+d0 : in bit;
+d1 : in bit;
+sel : in bit;
+sel_b : in bit
+);
+end component n2_core_pll_tpm_mux_cust;
+component cl_u1_inv_8x is
+port (
+i : in bit;
+o : out bit
+);
+end component cl_u1_inv_8x;
+component cl_u1_buf_1x is
+port (
+i : in bit;
+o : out bit
+);
+end component cl_u1_buf_1x;
+component n2_core_pll_flop_reset2_cust is
+port (
+d : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end component n2_core_pll_flop_reset2_cust;
+signal tvco_clk,tarst : bit;
+signal trst : bit_vector(1 downto 1);
+begin
+vdd <= '1';
+vss <= '0';
+rst <= trst;
+arst <= tarst;
+dc_clk <= tdc_clk;
+vco_out <= not volb;
+tdc_clk <= not vco_out;
+tvco_clk <= not tdc_clk;
+x2 : n2_core_pll_inv1_16x_cust port map (
+vdd_reg => vdd,
+o => rstpa(1),
+i => rstp_l(1)
+);
+x5_1 : n2_core_pll_flop_reset2_cust port map (
+d => rstp1(0),
+clk => vco_clk_d,
+q_l => net127(0),
+q => rstp1(1)
+);
+x8 : n2_core_pll_inv1_16x_cust port map (
+vdd_reg => vdd,
+o => tarst,
+i => arst_l
+);
+x9 : cl_u1_nand2_8x port map (
+o => trst(1),
+in1 => ccu_serdes_dtm,
+in0 => net63
+);
+x10 : n2_core_pll_fse2diff_out_cust port map (
+vdd_reg => vdd,
+i => tvco_clk,
+out_l => net81,
+o => vco_clk_d
+);
+x11 : cl_u1_inv_4x port map (
+o => net77,
+i => net69
+);
+x12 : n2_core_pll_fse2diff_out_cust port map (
+vdd_reg => vdd,
+i => rstpa(1),
+out_l => net112,
+o => rstpb(1)
+);
+x14 : n2_core_pll_inv1_16x_cust port map (
+vdd_reg => vdd,
+o => arst_d_l,
+i => tarst
+);
+x15 : cl_u1_inv_4x port map (
+o => net79,
+i => a(2)
+);
+x16 : cl_u1_inv_2x port map (
+o => net63,
+i => rstp(1)
+);
+x17 : n2_core_pll_flop_reset1_cust port map (
+reset_val_l => vdd,
+d => net116,
+reset => trst(1),
+clk => dri1_clk,
+q_l => net120,
+q => net110
+);
+xb_0 : n2_core_pll_flop_reset2_cust port map (
+d => dft_rst_l,
+clk => pll1_clk,
+q_l => rstp(0),
+q => rstp_l(0)
+);
+x22 : n2_core_pll_inv1_16x_cust port map (
+vdd_reg => vdd,
+o => rst_l(0),
+i => net77
+);
+xb_1 : n2_core_pll_flop_reset2_cust port map (
+d => rstp_l(0),
+clk => tvco_clk,
+q_l => rstp(1),
+q => rstp_l(1)
+);
+x37 : n2_core_pll_tpm_mux_cust port map (
+opb => net69,
+vdd_reg => vdd,
+op => net115,
+d0 => rstp1(1),
+d1 => rstp1(0),
+sel => a(2),
+sel_b => net79
+);
+x5_0 : n2_core_pll_flop_reset2_cust port map (
+d => rstpb(1),
+clk => vco_clk_d,
+q_l => net127(1),
+q => rstp1(0)
+);
+x0 : cl_u1_inv_8x port map (
+o => d4int_out,
+i => net110
+);
+x1 : cl_u1_buf_1x port map (
+o => net116,
+i => net120
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_tpm_cust.vhd b/pll/n2_core_pll_tpm_cust.vhd
new file mode 100755
index 0000000..a9e6267
--- /dev/null
+++ b/pll/n2_core_pll_tpm_cust.vhd
@@ -0,0 +1,513 @@
+entity n2_core_pll_tpm_cust is
+port (
+reset : in bit;
+ip : in bit_vector(5 downto 0);
+vdd_reg : in bit;
+op : out bit_vector(5 downto 0);
+sel : out bit;
+div_ck_i : in bit;
+pwr_rst : in bit;
+div_ck : out bit;
+vco_ck : in bit
+);
+end entity n2_core_pll_tpm_cust;
+architecture arch of n2_core_pll_tpm_cust is
+--vss = '0';
+signal vdd,vss : bit;
+signal net183,nz_2,net201,net282,nz_3,nz_4,nz_5,net186,net205,net189,f4q,f5d,net195,vco_ckb,vco_ckd,net198,f5q,net219,f_gate,r_gate,reset_d,net235,zero_0,net236,zero_1,zero_2,f0d,zero_3,zero_4,zero_5,sel_b,f0q,net147,f1d,not_zero,net252,net256,net159,f1q,f2d,nzero_0,nzero_1,net162,nzero_2,nzero_3,nzero_4,nzero_5,f2q,next0,next1,next2,next3,f3d,next4,next5,net171,nip0,nip1,nip2,nip3,nip4,nip5,net0501,f3q,net0502,net0503,net0504,f4d,net0505,net0506,nz_0,nz_1 : bit;
+signal tsel : bit;
+component n2_core_pll_buf_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_buf_4x_cust;
+component n2_core_pll_buf_16x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_buf_16x_cust;
+component n2_core_pll_tpm_mux_cust is
+port (
+opb : out bit;
+vdd_reg : in bit;
+op : out bit;
+d0 : in bit;
+d1 : in bit;
+sel : in bit;
+sel_b : in bit
+);
+end component n2_core_pll_tpm_mux_cust;
+component n2_core_pll_buf_8x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_buf_8x_cust;
+component n2_core_pll_inv_8x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_8x_cust;
+component n2_core_pll_tpm_next_new_cust is
+port (
+vdd_reg : in bit;
+d5 : out bit;
+q0b : in bit;
+q3b : in bit;
+d3 : out bit;
+q5b : in bit;
+q1b : in bit;
+q2b : in bit;
+d2 : out bit;
+d0 : out bit;
+d4 : out bit;
+q2 : in bit;
+q0 : in bit;
+q1 : in bit;
+d1 : out bit;
+q4b : in bit
+);
+end component n2_core_pll_tpm_next_new_cust;
+component n2_core_pll_flop_reset_new_cust is
+port (
+vdd_reg : in bit;
+reset_val_l : in bit;
+d : in bit;
+reset : in bit;
+clk : in bit;
+q_l : out bit;
+q : out bit
+);
+end component n2_core_pll_flop_reset_new_cust;
+component n2_core_pll_inv_32x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_32x_cust;
+component n2_core_pll_tpm_zd1_cust is
+port (
+vdd_reg : in bit;
+zero1 : out bit;
+zero1_b : out bit;
+q4b : in bit;
+q0b : in bit;
+q1b : in bit;
+q2b : in bit;
+q3b : in bit;
+q5b : in bit
+);
+end component n2_core_pll_tpm_zd1_cust;
+component n2_core_pll_tpm_nzd_cust is
+port (
+vdd_reg : in bit;
+q2b : in bit;
+q4b : in bit;
+q3b : in bit;
+zero : out bit;
+q1b : in bit;
+q0b : in bit;
+q5b : in bit
+);
+end component n2_core_pll_tpm_nzd_cust;
+component n2_core_pll_tpm_gate_new_cust is
+port (
+r_b : in bit;
+vdd_reg : in bit;
+div_ck : out bit;
+r : in bit;
+ck : in bit;
+f : in bit
+);
+end component n2_core_pll_tpm_gate_new_cust;
+component n2_core_pll_inv_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_4x_cust;
+begin
+vss <= '0';
+sel <= tsel;
+x2 : n2_core_pll_buf_4x_cust port map (
+vdd_reg => vdd_reg,
+o => net205,
+i => ip(0)
+);
+x4 : n2_core_pll_buf_16x_cust port map (
+vdd_reg => vdd_reg,
+o => reset_d,
+i => reset
+);
+x5 : n2_core_pll_tpm_mux_cust port map (
+opb => nzero_0,
+vdd_reg => vdd_reg,
+op => nz_0,
+d0 => ip(0),
+d1 => nip0,
+sel => net256,
+sel_b => net282
+);
+x6 : n2_core_pll_buf_8x_cust port map (
+vdd_reg => vdd_reg,
+o => net282,
+i => pwr_rst
+);
+x7 : n2_core_pll_inv_8x_cust port map (
+vdd_reg => vdd_reg,
+o => net256,
+i => pwr_rst
+);
+x8 : n2_core_pll_buf_4x_cust port map (
+vdd_reg => vdd_reg,
+o => net183,
+i => ip(1)
+);
+x9 : n2_core_pll_buf_4x_cust port map (
+vdd_reg => vdd_reg,
+o => net195,
+i => ip(2)
+);
+x10 : n2_core_pll_buf_4x_cust port map (
+vdd_reg => vdd_reg,
+o => net159,
+i => ip(3)
+);
+x11 : n2_core_pll_buf_4x_cust port map (
+vdd_reg => vdd_reg,
+o => net147,
+i => ip(4)
+);
+x12 : n2_core_pll_buf_4x_cust port map (
+vdd_reg => vdd_reg,
+o => net171,
+i => ip(5)
+);
+x13 : n2_core_pll_buf_8x_cust port map (
+vdd_reg => vdd_reg,
+o => op(0),
+i => nip0
+);
+x14 : n2_core_pll_buf_8x_cust port map (
+vdd_reg => vdd_reg,
+o => op(1),
+i => nip1
+);
+x15 : n2_core_pll_buf_8x_cust port map (
+vdd_reg => vdd_reg,
+o => op(2),
+i => nip2
+);
+x16 : n2_core_pll_tpm_next_new_cust port map (
+vdd_reg => vdd_reg,
+d5 => next5,
+q0b => zero_0,
+q3b => zero_3,
+d3 => next3,
+q5b => zero_5,
+q1b => zero_1,
+q2b => zero_2,
+d2 => next2,
+d0 => next0,
+d4 => next4,
+q2 => f2q,
+q0 => f0q,
+q1 => f1q,
+d1 => next1,
+q4b => zero_4
+);
+x17 : n2_core_pll_tpm_mux_cust port map (
+opb => nzero_1,
+vdd_reg => vdd_reg,
+op => nz_1,
+d0 => ip(1),
+d1 => nip1,
+sel => net256,
+sel_b => net282
+);
+x18 : n2_core_pll_buf_8x_cust port map (
+vdd_reg => vdd_reg,
+o => op(3),
+i => nip3
+);
+x19 : n2_core_pll_buf_8x_cust port map (
+vdd_reg => vdd_reg,
+o => op(4),
+i => nip4
+);
+x20 : n2_core_pll_buf_8x_cust port map (
+vdd_reg => vdd_reg,
+o => op(5),
+i => nip5
+);
+x23 : n2_core_pll_tpm_mux_cust port map (
+opb => nzero_2,
+vdd_reg => vdd_reg,
+op => nz_2,
+d0 => ip(2),
+d1 => nip2,
+sel => net256,
+sel_b => net282
+);
+x24 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => net205,
+reset => reset_d,
+clk => div_ck_i,
+q_l => net201,
+q => nip0
+);
+x25 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => net183,
+reset => reset_d,
+clk => div_ck_i,
+q_l => net186,
+q => nip1
+);
+x27 : n2_core_pll_tpm_mux_cust port map (
+opb => nzero_3,
+vdd_reg => vdd_reg,
+op => nz_3,
+d0 => ip(3),
+d1 => nip3,
+sel => net256,
+sel_b => net282
+);
+x28 : n2_core_pll_tpm_mux_cust port map (
+opb => nzero_4,
+vdd_reg => vdd_reg,
+op => nz_4,
+d0 => ip(4),
+d1 => nip4,
+sel => net256,
+sel_b => net282
+);
+x29 : n2_core_pll_tpm_mux_cust port map (
+opb => nzero_5,
+vdd_reg => vdd_reg,
+op => nz_5,
+d0 => ip(5),
+d1 => nip5,
+sel => net256,
+sel_b => net282
+);
+x30 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => net195,
+reset => reset_d,
+clk => div_ck_i,
+q_l => net198,
+q => nip2
+);
+x31 : n2_core_pll_inv_32x_cust port map (
+vdd_reg => vdd_reg,
+o => vco_ckd,
+i => net252
+);
+x32 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => net159,
+reset => reset_d,
+clk => div_ck_i,
+q_l => net162,
+q => nip3
+);
+x33 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => net147,
+reset => reset_d,
+clk => div_ck_i,
+q_l => net235,
+q => nip4
+);
+x34 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => net171,
+reset => reset_d,
+clk => div_ck_i,
+q_l => net236,
+q => nip5
+);
+x35 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => f0d,
+reset => reset_d,
+clk => vco_ckd,
+q_l => zero_0,
+q => f0q
+);
+x36 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => f1d,
+reset => reset_d,
+clk => vco_ckd,
+q_l => zero_1,
+q => f1q
+);
+x37 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => f2d,
+reset => reset_d,
+clk => vco_ckd,
+q_l => zero_2,
+q => f2q
+);
+x38 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => f3d,
+reset => reset_d,
+clk => vco_ckd,
+q_l => zero_3,
+q => f3q
+);
+x39 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => f4d,
+reset => reset_d,
+clk => vco_ckd,
+q_l => zero_4,
+q => f4q
+);
+x40 : n2_core_pll_tpm_zd1_cust port map (
+vdd_reg => vdd_reg,
+zero1 => tsel,
+zero1_b => sel_b,
+q4b => zero_4,
+q0b => zero_0,
+q1b => zero_1,
+q2b => zero_2,
+q3b => zero_3,
+q5b => zero_5
+);
+x41 : n2_core_pll_inv_8x_cust port map (
+vdd_reg => vdd_reg,
+o => net252,
+i => vco_ck
+);
+x42 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => f5d,
+reset => reset_d,
+clk => vco_ckd,
+q_l => zero_5,
+q => f5q
+);
+x43 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vss,
+d => tsel,
+reset => reset_d,
+clk => vco_ckb,
+q_l => net219,
+q => r_gate
+);
+x44 : n2_core_pll_flop_reset_new_cust port map (
+vdd_reg => vdd_reg,
+reset_val_l => vdd_reg,
+d => not_zero,
+reset => reset_d,
+clk => vco_ckd,
+q_l => net189,
+q => f_gate
+);
+x47 : n2_core_pll_tpm_mux_cust port map (
+opb => net0506,
+vdd_reg => vdd_reg,
+op => f0d,
+d0 => next0,
+d1 => nz_0,
+sel => tsel,
+sel_b => sel_b
+);
+x48 : n2_core_pll_tpm_mux_cust port map (
+opb => net0505,
+vdd_reg => vdd_reg,
+op => f1d,
+d0 => next1,
+d1 => nz_1,
+sel => tsel,
+sel_b => sel_b
+);
+x49 : n2_core_pll_tpm_nzd_cust port map (
+vdd_reg => vdd_reg,
+q2b => nzero_2,
+q4b => nzero_4,
+q3b => nzero_3,
+zero => not_zero,
+q1b => nzero_1,
+q0b => nzero_0,
+q5b => nzero_5
+);
+x50 : n2_core_pll_tpm_mux_cust port map (
+opb => net0504,
+vdd_reg => vdd_reg,
+op => f2d,
+d0 => next2,
+d1 => nz_2,
+sel => tsel,
+sel_b => sel_b
+);
+x51 : n2_core_pll_tpm_mux_cust port map (
+opb => net0503,
+vdd_reg => vdd_reg,
+op => f3d,
+d0 => next3,
+d1 => nz_3,
+sel => tsel,
+sel_b => sel_b
+);
+x52 : n2_core_pll_tpm_mux_cust port map (
+opb => net0502,
+vdd_reg => vdd_reg,
+op => f4d,
+d0 => next4,
+d1 => nz_4,
+sel => tsel,
+sel_b => sel_b
+);
+x53 : n2_core_pll_tpm_mux_cust port map (
+opb => net0501,
+vdd_reg => vdd_reg,
+op => f5d,
+d0 => next5,
+d1 => nz_5,
+sel => tsel,
+sel_b => sel_b
+);
+x0 : n2_core_pll_tpm_gate_new_cust port map (
+r_b => net219,
+vdd_reg => vdd_reg,
+div_ck => div_ck,
+r => r_gate,
+ck => vco_ck,
+f => f_gate
+);
+x1 : n2_core_pll_inv_4x_cust port map (
+vdd_reg => vdd_reg,
+o => vco_ckb,
+i => vco_ckd
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_tpm_gate2_cust.vhd b/pll/n2_core_pll_tpm_gate2_cust.vhd
new file mode 100755
index 0000000..5f09c03
--- /dev/null
+++ b/pll/n2_core_pll_tpm_gate2_cust.vhd
@@ -0,0 +1,19 @@
+entity n2_core_pll_tpm_gate2_cust is
+port (
+vdd_reg : in bit;
+div_ck : out bit;
+r : in bit;
+ck : in bit
+);
+end entity n2_core_pll_tpm_gate2_cust;
+architecture arch of n2_core_pll_tpm_gate2_cust is
+--vss = '0';
+begin
+p0 : process (ck,r) is
+begin
+ if (ck = '1') then
+ div_ck <= not r;
+ end if;
+end process p0;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_tpm_gate_new_cust.vhd b/pll/n2_core_pll_tpm_gate_new_cust.vhd
new file mode 100755
index 0000000..fbbe10c
--- /dev/null
+++ b/pll/n2_core_pll_tpm_gate_new_cust.vhd
@@ -0,0 +1,29 @@
+entity n2_core_pll_tpm_gate_new_cust is
+port (
+r_b : in bit;
+vdd_reg : in bit;
+div_ck : out bit;
+r : in bit;
+ck : in bit;
+f : in bit
+);
+end entity n2_core_pll_tpm_gate_new_cust;
+architecture arch of n2_core_pll_tpm_gate_new_cust is
+--vss = '0';
+signal tdiv_ck : bit;
+begin
+div_ck <= tdiv_ck;
+p0 : process (ck,r,f,tdiv_ck) is
+begin
+if ((ck = '1') and (r = '1')) then
+tdiv_ck <= '1';
+elsif ((ck = '1') and (f = '0')) then
+tdiv_ck <= '0';
+elsif ((ck = '1') and (r = '0') and (tdiv_ck = '1')) then
+tdiv_ck <= '0';
+else
+tdiv_ck <= tdiv_ck;
+end if;
+end process p0;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_tpm_mux1_cust.vhd b/pll/n2_core_pll_tpm_mux1_cust.vhd
new file mode 100755
index 0000000..9703df4
--- /dev/null
+++ b/pll/n2_core_pll_tpm_mux1_cust.vhd
@@ -0,0 +1,36 @@
+entity n2_core_pll_tpm_mux1_cust is
+port (
+sel_l : in bit;
+vdd_reg : in bit;
+out_l : out bit;
+d0 : in bit;
+d1 : in bit;
+sel : in bit
+);
+end entity n2_core_pll_tpm_mux1_cust;
+architecture arch of n2_core_pll_tpm_mux1_cust is
+--vss = '0';
+component mux2s
+generic (SIZE : integer := 1);
+port (
+dout : out bit_vector(SIZE-1 downto 0);
+in0 : in bit_vector(SIZE-1 downto 0);
+in1 : in bit_vector(SIZE-1 downto 0);
+sel0 : in bit;
+sel1 : in bit
+);
+end component mux2s;
+signal td0,td1,tdout : bit_vector(0 downto 0);
+begin
+td0(0) <= d0;
+td1(0) <= d1;
+x1 : mux2s port map (
+sel0 => sel_l,
+sel1 => sel,
+in0 => td0,
+in1 => td1,
+dout => tdout
+);
+out_l <= not tdout(0);
+end architecture arch;
+--XXX check
diff --git a/pll/n2_core_pll_tpm_mux_cust.vhd b/pll/n2_core_pll_tpm_mux_cust.vhd
new file mode 100755
index 0000000..d80cac8
--- /dev/null
+++ b/pll/n2_core_pll_tpm_mux_cust.vhd
@@ -0,0 +1,20 @@
+entity n2_core_pll_tpm_mux_cust is
+port (
+opb : out bit;
+vdd_reg : in bit;
+op : out bit;
+d0 : in bit;
+d1 : in bit;
+sel : in bit;
+sel_b : in bit
+);
+end entity n2_core_pll_tpm_mux_cust;
+architecture arch of n2_core_pll_tpm_mux_cust is
+--vss = '0';
+signal topb : bit;
+begin
+topb <= (not (sel and d1)) and (not (sel_b and d0));
+opb <= topb;
+op <= not topb;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_tpm_muxa_cust.vhd b/pll/n2_core_pll_tpm_muxa_cust.vhd
new file mode 100755
index 0000000..df583b2
--- /dev/null
+++ b/pll/n2_core_pll_tpm_muxa_cust.vhd
@@ -0,0 +1,32 @@
+entity n2_core_pll_tpm_muxa_cust is
+port (
+opb : out bit;
+op : out bit;
+d0 : in bit;
+d1 : in bit;
+sel : in bit;
+sel_b : in bit
+);
+end entity n2_core_pll_tpm_muxa_cust;
+architecture arch of n2_core_pll_tpm_muxa_cust is
+--supply1 vdd;
+--vss = '0';
+component mux2 is
+port (
+in0,in1,sel0,sel1 : in bit;
+y : out bit
+);
+end component mux2;
+signal top : bit;
+begin
+x1 : mux2 port map (
+sel0 => sel_b,
+sel1 => sel,
+in0 => d0,
+in1 => d1,
+y => top
+);
+op <= top;
+opb <= not top;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_tpm_next_new_cust.vhd b/pll/n2_core_pll_tpm_next_new_cust.vhd
new file mode 100755
index 0000000..32ca879
--- /dev/null
+++ b/pll/n2_core_pll_tpm_next_new_cust.vhd
@@ -0,0 +1,153 @@
+entity n2_core_pll_tpm_next_new_cust is
+port (
+vdd_reg : in bit;
+d5 : out bit;
+q0b : in bit;
+q3b : in bit;
+d3 : out bit;
+q5b : in bit;
+q1b : in bit;
+q2b : in bit;
+d2 : out bit;
+d0 : out bit;
+d4 : out bit;
+q2 : in bit;
+q0 : in bit;
+q1 : in bit;
+d1 : out bit;
+q4b : in bit
+);
+end entity n2_core_pll_tpm_next_new_cust;
+architecture arch of n2_core_pll_tpm_next_new_cust is
+component n2_core_pll_xnor2_4x_new_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in0 : in bit;
+in1 : in bit
+);
+end component n2_core_pll_xnor2_4x_new_cust;
+component n2_core_pll_nand2_2x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in1 : in bit;
+in0 : in bit
+);
+end component n2_core_pll_nand2_2x_cust;
+component n2_core_pll_nor2_2x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in1 : in bit;
+in0 : in bit
+);
+end component n2_core_pll_nor2_2x_cust;
+component n2_core_pll_nand3_2x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in2 : in bit;
+in1 : in bit;
+in0 : in bit
+);
+end component n2_core_pll_nand3_2x_cust;
+component n2_core_pll_nor3_2x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in2 : in bit;
+in1 : in bit;
+in0 : in bit
+);
+end component n2_core_pll_nor3_2x_cust;
+signal net73,net76,net091,net0115,net53,net55,net64,net69 : bit;
+begin
+x2 : n2_core_pll_xnor2_4x_new_cust port map (
+vdd_reg => vdd_reg,
+o => d1,
+in0 => q1b,
+in1 => q0b
+);
+x3 : n2_core_pll_xnor2_4x_new_cust port map (
+vdd_reg => vdd_reg,
+o => d2,
+in0 => q2b,
+in1 => net76
+);
+x4 : n2_core_pll_xnor2_4x_new_cust port map (
+vdd_reg => vdd_reg,
+o => d3,
+in0 => q3b,
+in1 => net73
+);
+x5 : n2_core_pll_nand2_2x_cust port map (
+vdd_reg => vdd_reg,
+o => net53,
+in1 => q1b,
+in0 => q0b
+);
+x6 : n2_core_pll_nor2_2x_cust port map (
+vdd_reg => vdd_reg,
+o => net76,
+in1 => q1,
+in0 => q0
+);
+x7 : n2_core_pll_nor2_2x_cust port map (
+vdd_reg => vdd_reg,
+o => net55,
+in1 => net64,
+in0 => net53
+);
+x8 : n2_core_pll_xnor2_4x_new_cust port map (
+vdd_reg => vdd_reg,
+o => d4,
+in0 => q4b,
+in1 => net69
+);
+x9 : n2_core_pll_xnor2_4x_new_cust port map (
+vdd_reg => vdd_reg,
+o => d5,
+in0 => q5b,
+in1 => net55
+);
+x13 : n2_core_pll_nand3_2x_cust port map (
+vdd_reg => vdd_reg,
+o => net64,
+in2 => q4b,
+in1 => q3b,
+in0 => q2b
+);
+x14 : n2_core_pll_nand2_2x_cust port map (
+vdd_reg => vdd_reg,
+o => net0115,
+in1 => q1b,
+in0 => q0b
+);
+x15 : n2_core_pll_nand2_2x_cust port map (
+vdd_reg => vdd_reg,
+o => net091,
+in1 => q3b,
+in0 => q2b
+);
+x16 : n2_core_pll_nor2_2x_cust port map (
+vdd_reg => vdd_reg,
+o => net69,
+in1 => net091,
+in0 => net0115
+);
+x0 : n2_core_pll_nor3_2x_cust port map (
+vdd_reg => vdd_reg,
+o => net73,
+in2 => q2,
+in1 => q1,
+in0 => q0
+);
+x1 : n2_core_pll_xnor2_4x_new_cust port map (
+vdd_reg => vdd_reg,
+o => d0,
+in0 => q0b,
+in1 => vdd_reg
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_tpm_nzd_cust.vhd b/pll/n2_core_pll_tpm_nzd_cust.vhd
new file mode 100755
index 0000000..d81b4a1
--- /dev/null
+++ b/pll/n2_core_pll_tpm_nzd_cust.vhd
@@ -0,0 +1,66 @@
+entity n2_core_pll_tpm_nzd_cust is
+port (
+vdd_reg : in bit;
+q2b : in bit;
+q4b : in bit;
+q3b : in bit;
+zero : out bit;
+q1b : in bit;
+q0b : in bit;
+q5b : in bit
+);
+end entity n2_core_pll_tpm_nzd_cust;
+architecture arch of n2_core_pll_tpm_nzd_cust is
+component n2_core_pll_nand3_2x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in2 : in bit;
+in1 : in bit;
+in0 : in bit
+);
+end component n2_core_pll_nand3_2x_cust;
+component n2_core_pll_inv_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_4x_cust;
+component n2_core_pll_nor2_2x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in1 : in bit;
+in0 : in bit
+);
+end component n2_core_pll_nor2_2x_cust;
+signal net22,net28,net33 : bit;
+begin
+x2 : n2_core_pll_nand3_2x_cust port map (
+vdd_reg => vdd_reg,
+o => net28,
+in2 => q2b,
+in1 => q1b,
+in0 => q0b
+);
+x3 : n2_core_pll_nand3_2x_cust port map (
+vdd_reg => vdd_reg,
+o => net33,
+in2 => q5b,
+in1 => q4b,
+in0 => q3b
+);
+x0 : n2_core_pll_inv_4x_cust port map (
+vdd_reg => vdd_reg,
+o => zero,
+i => net22
+);
+x1 : n2_core_pll_nor2_2x_cust port map (
+vdd_reg => vdd_reg,
+o => net22,
+in1 => net33,
+in0 => net28
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_tpm_zd1_cust.vhd b/pll/n2_core_pll_tpm_zd1_cust.vhd
new file mode 100755
index 0000000..bd4479c
--- /dev/null
+++ b/pll/n2_core_pll_tpm_zd1_cust.vhd
@@ -0,0 +1,90 @@
+entity n2_core_pll_tpm_zd1_cust is
+port (
+vdd_reg : in bit;
+zero1 : out bit;
+zero1_b : out bit;
+q4b : in bit;
+q0b : in bit;
+q1b : in bit;
+q2b : in bit;
+q3b : in bit;
+q5b : in bit
+);
+end entity n2_core_pll_tpm_zd1_cust;
+architecture arch of n2_core_pll_tpm_zd1_cust is
+component n2_core_pll_nand2_2x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in1 : in bit;
+in0 : in bit
+);
+end component n2_core_pll_nand2_2x_cust;
+component n2_core_pll_nor2_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in1 : in bit;
+in0 : in bit
+);
+end component n2_core_pll_nor2_4x_cust;
+component n2_core_plllvt_nand2_16x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in1 : in bit;
+in0 : in bit
+);
+end component n2_core_plllvt_nand2_16x_cust;
+component n2_core_pll_nand3_2x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in2 : in bit;
+in1 : in bit;
+in0 : in bit
+);
+end component n2_core_pll_nand3_2x_cust;
+component n2_core_pll_inv_16x_a_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_16x_a_cust;
+signal net28,net33,net38 : bit;
+signal tzero1_b : bit;
+begin
+zero1_b <= tzero1_b;
+x2 : n2_core_pll_nand2_2x_cust port map (
+vdd_reg => vdd_reg,
+o => net33,
+in1 => q1b,
+in0 => q2b
+);
+x3 : n2_core_pll_nor2_4x_cust port map (
+vdd_reg => vdd_reg,
+o => net28,
+in1 => net33,
+in0 => net38
+);
+x4 : n2_core_plllvt_nand2_16x_cust port map (
+vdd_reg => vdd_reg,
+o => tzero1_b,
+in1 => q0b,
+in0 => net28
+);
+x0 : n2_core_pll_nand3_2x_cust port map (
+vdd_reg => vdd_reg,
+o => net38,
+in2 => q3b,
+in1 => q4b,
+in0 => q5b
+);
+x1 : n2_core_pll_inv_16x_a_cust port map (
+vdd_reg => vdd_reg,
+o => zero1,
+i => tzero1_b
+);
+end architecture arch;
+
diff --git a/pll/n2_core_pll_vco_sum_cust.vhd b/pll/n2_core_pll_vco_sum_cust.vhd
new file mode 100755
index 0000000..d46eecd
--- /dev/null
+++ b/pll/n2_core_pll_vco_sum_cust.vhd
@@ -0,0 +1,17 @@
+entity n2_core_pll_vco_sum_cust is
+port (
+dc_clk : in bit;
+volb : out bit;
+vdd_reg : in bit;
+slow : in bit;
+slow_l : in bit;
+fast : in bit;
+fltr : in bit;
+fast_l : in bit
+);
+end entity n2_core_pll_vco_sum_cust;
+architecture arch of n2_core_pll_vco_sum_cust is
+begin
+volb <= fast;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_vco_sum_cust_1.vhd b/pll/n2_core_pll_vco_sum_cust_1.vhd
new file mode 100755
index 0000000..d46eecd
--- /dev/null
+++ b/pll/n2_core_pll_vco_sum_cust_1.vhd
@@ -0,0 +1,17 @@
+entity n2_core_pll_vco_sum_cust is
+port (
+dc_clk : in bit;
+volb : out bit;
+vdd_reg : in bit;
+slow : in bit;
+slow_l : in bit;
+fast : in bit;
+fltr : in bit;
+fast_l : in bit
+);
+end entity n2_core_pll_vco_sum_cust;
+architecture arch of n2_core_pll_vco_sum_cust is
+begin
+volb <= fast;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_vdd_xing_buf_32x_cust.vhd b/pll/n2_core_pll_vdd_xing_buf_32x_cust.vhd
new file mode 100755
index 0000000..a352be8
--- /dev/null
+++ b/pll/n2_core_pll_vdd_xing_buf_32x_cust.vhd
@@ -0,0 +1,13 @@
+entity n2_core_pll_vdd_xing_buf_32x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_vdd_xing_buf_32x_cust;
+architecture arch of n2_core_pll_vdd_xing_buf_32x_cust is
+--vss = '0';
+begin
+o <= i;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_vdd_xing_buf_4x_cust.vhd b/pll/n2_core_pll_vdd_xing_buf_4x_cust.vhd
new file mode 100755
index 0000000..32d8403
--- /dev/null
+++ b/pll/n2_core_pll_vdd_xing_buf_4x_cust.vhd
@@ -0,0 +1,12 @@
+entity n2_core_pll_vdd_xing_buf_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end entity n2_core_pll_vdd_xing_buf_4x_cust;
+architecture arch of n2_core_pll_vdd_xing_buf_4x_cust is
+begin
+o <= i;
+end architecture arch;
+
diff --git a/pll/n2_core_pll_vrr_cust.vhd b/pll/n2_core_pll_vrr_cust.vhd
new file mode 100755
index 0000000..d16fbcd
--- /dev/null
+++ b/pll/n2_core_pll_vrr_cust.vhd
@@ -0,0 +1,19 @@
+entity n2_core_pll_vrr_cust is
+port(
+vdd_reg : in bit;
+fltr_nw : inout bit;
+reset : in bit;
+fb : in bit;
+div8 : in bit;
+div4 : in bit;
+div_ck : in bit;
+vrr_disbl : in bit;
+clamp_fltr : in bit;
+pfd_reset : in bit
+);
+end entity n2_core_pll_vrr_cust;
+architecture arch of n2_core_pll_vrr_cust is
+--vss = '0';
+begin
+end architecture arch;
+
diff --git a/pll/n2_core_pll_xnor2_4x_new_cust.vhd b/pll/n2_core_pll_xnor2_4x_new_cust.vhd
new file mode 100755
index 0000000..47bd10c
--- /dev/null
+++ b/pll/n2_core_pll_xnor2_4x_new_cust.vhd
@@ -0,0 +1,14 @@
+entity n2_core_pll_xnor2_4x_new_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in0 : in bit;
+in1 : in bit
+);
+end entity n2_core_pll_xnor2_4x_new_cust;
+architecture arch of n2_core_pll_xnor2_4x_new_cust is
+--vss = '0';
+begin
+o <= not (in0 xor in1);
+end architecture arch;
+
diff --git a/pll/n2_core_plllvt_nand2_16x_cust.vhd b/pll/n2_core_plllvt_nand2_16x_cust.vhd
new file mode 100755
index 0000000..cc36044
--- /dev/null
+++ b/pll/n2_core_plllvt_nand2_16x_cust.vhd
@@ -0,0 +1,14 @@
+entity n2_core_plllvt_nand2_16x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+in1 : in bit;
+in0 : in bit
+);
+end entity n2_core_plllvt_nand2_16x_cust;
+architecture arch of n2_core_plllvt_nand2_16x_cust is
+--vss = '0';
+begin
+o <= not (in0 and in1);
+end architecture arch;
+
diff --git a/pll/n2_vreg_cust.vhd b/pll/n2_vreg_cust.vhd
new file mode 100755
index 0000000..74201ed
--- /dev/null
+++ b/pll/n2_vreg_cust.vhd
@@ -0,0 +1,19 @@
+entity n2_vreg_cust is
+port (
+v1p1reg_lowv : out bit;
+vdd_hv15 : in bit;
+vref : out bit;
+vrefb : out bit;
+i50n : out bit_vector(9 downto 0);
+selbg_l : in bit
+);
+end entity n2_vreg_cust;
+architecture arch of n2_vreg_cust is
+begin
+--vss = '0';
+v1p1reg_lowv <= '1';
+i50n <= (others => '0');
+vref <= '1';
+vrefb <= '1';
+end architecture arch;
+
diff --git a/pll/pll.xise b/pll/pll.xise
new file mode 100755
index 0000000..6240c90
--- /dev/null
+++ b/pll/pll.xise
@@ -0,0 +1,798 @@
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diff --git a/pll/pll_core.vhd b/pll/pll_core.vhd
new file mode 100755
index 0000000..48ce600
--- /dev/null
+++ b/pll/pll_core.vhd
@@ -0,0 +1,176 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+entity pll_core is
+port (
+pll_arst_l : in bit;
+sysclk : in bit;
+fdbkclk : in bit;
+div : in bit_vector(5 downto 0);
+vco_out : out bit
+);
+end entity pll_core;
+architecture arch of pll_core is
+signal vco_tmp,locked : bit;
+signal neg_delay,ref_per,vco_per,vco_hi_ph,vco_lo_ph : time := 0 ps;
+signal t0,t1,posedge_vco_tmp,posedge_fdbkclk,insdelay,adj_delay : time := 0 ps;
+signal j,ph_offset_past,ph_offset : integer;
+signal pulse_cnt : integer := 2;
+signal mult,mult2x : integer := 0;
+signal vco_shift : bit;
+signal tmp_clk1,tmp_clk2,tmp_clk3,tmp_clk4 : bit;
+signal lock_cnt : bit_vector(2 downto 0);
+signal qnt_err : time;
+--synthesis translate_off
+--https://groups.google.com/g/comp.lang.vhdl/c/OxgjdpZDOxU/m/SOB3tlzxQwgJ
+---------------------------------------------------------- to_sl ---
+---- convert 'bit' to 'std_logic' ---
+---------------------------------------------------------- to_sl ---
+function to_sl(b: bit) return std_logic is
+begin
+if b='1' then
+return '1';
+else
+return '0';
+end if;
+end;
+--------------------------------------------------------- to_slv ---
+---- convert 'bit_vector' to 'std_logic_vector' ---
+--------------------------------------------------------- to_slv ---
+function to_slv(bv:bit_vector) return std_logic_vector is
+variable sv: std_logic_vector(bv'RANGE);
+begin
+for i in bv'RANGE loop
+sv(i) := to_sl(bv(i));
+end loop;
+return sv;
+end;
+
+begin
+mult <= to_integer(unsigned(to_slv(div))) + 1;
+mult2x <= mult*2;
+p0 : process (sysclk) is
+begin
+ t0 <= NOW;
+ if (sysclk'event and sysclk = '1') then
+ t1 <= NOW;
+ ref_per <= t1 - t0;
+ vco_per <= time(ref_per / (to_integer(unsigned(to_slv(div)))+1));
+ vco_hi_ph <= ref_per / mult2x;
+ vco_lo_ph <= vco_per - vco_hi_ph;
+ qnt_err <= ref_per - (vco_hi_ph + vco_lo_ph) * mult;
+ end if;
+end process p0;
+p1 : process (sysclk) is
+variable jj : integer := 0;
+begin
+ vco_tmp <= '1';
+ l0 : for j in 1 to mult loop
+ jj := j;
+ vco_tmp <= '0' after vco_hi_ph;
+ if (jj = mult/2 and (qnt_err /= 0 ns)) then
+ jj := jj / 2;
+ end if;
+ if (jj = 1) then
+ exit;
+ end if;
+ vco_tmp <= '1';
+ end loop l0;
+ vco_tmp <= '0' after vco_hi_ph;
+end process p1;
+--always @ ( posedge sysclk ) begin
+-- vco_tmp = 1'b1;
+-- for ( j = 1; j < mult; j = j+1 ) begin
+-- #(vco_hi_ph) vco_tmp = 1'b0;
+-- if ((j == (mult >> 1)) && (qnt_err != 0)) // internal multiplier for N2 is always even
+-- #(j/2);
+-- #(vco_lo_ph) vco_tmp = 1'b1;
+-- end
+-- #(vco_hi_ph) vco_tmp = 1'b0; // for remaining part of cycle
+--end
+p2 : process (vco_tmp,pll_arst_l) is
+begin
+ if (pll_arst_l = '0') then
+ posedge_vco_tmp <= 0 ps;
+ posedge_fdbkclk <= 0 ps;
+ adj_delay <= 0 ps;
+ insdelay <= 0 ps;
+ ph_offset_past <= 360;
+ elsif (vco_tmp'event and vco_tmp = '1') then
+ if (locked = '1') then
+ insdelay <= insdelay;
+ else
+ posedge_vco_tmp <= NOW;
+-- wait until (fdbkclk'event and fdbkclk = '1');
+ posedge_fdbkclk <= NOW;
+ insdelay <= posedge_fdbkclk - posedge_vco_tmp;
+ end if;
+ l1 : while (vco_per <= insdelay) loop
+ insdelay <= insdelay - vco_per;
+ end loop l1;
+ adj_delay <= vco_per - insdelay;
+ end if;
+end process p2;
+--XXX finish
+--always @ ( posedge vco_tmp or negedge pll_arst_l ) begin
+-- if (!pll_arst_l) begin
+-- posedge_vco_tmp = 0;
+-- posedge_fdbkclk = 0;
+-- adj_delay = 0;
+-- insdelay = 0;
+-- ph_offset_past = 360;
+-- end else begin
+-- if (locked)
+-- insdelay = insdelay;
+-- else begin
+-- posedge_vco_tmp = $realtime;
+-- @(posedge fdbkclk );
+-- posedge_fdbkclk = $realtime;
+-- insdelay = posedge_fdbkclk - posedge_vco_tmp;
+-- end
+-- `ifdef PLL_PH_DEBUG
+-- // DEBUG BEGIN
+-- ph_offset = (360 * insdelay)/vco_per;
+-- if (ph_offset != ph_offset_past)
+-- $display ("phase offset changed changed from %d to %d degrees",
+-- ph_offset_past, ph_offset );
+-- ph_offset_past = ph_offset;
+-- // DEBUG END
+-- `endif
+-- while (vco_per <= insdelay)
+-- insdelay = insdelay - vco_per ;
+-- adj_delay = vco_per - insdelay;
+-- end
+--end
+
+--assign vco_out = locked? vco_shift : vco_tmp;
+--always @ (negedge sysclk or negedge pll_arst_l ) begin
+-- if (!pll_arst_l) begin
+-- locked <= 1'b0;
+-- lock_cnt <= 3'b0;
+-- end else begin
+-- if (lock_cnt == `PLL_LOCK_CNT ) begin
+-- locked <= 1'b1;
+-- lock_cnt <= `PLL_LOCK_CNT;
+-- end else begin
+-- locked <= 1'b0;
+-- lock_cnt <= lock_cnt + 1'b1;
+-- end
+-- end
+--end
+--`ifdef FDBK_TRACKING
+-- always @ (vco_tmp) tmp_clk1 = #(adj_delay/4) vco_tmp;
+-- always @ (tmp_clk1) tmp_clk2 = #(adj_delay/4) tmp_clk1;
+-- always @ (tmp_clk2) tmp_clk3 = #(adj_delay/4) tmp_clk2;
+-- always @ (tmp_clk3) tmp_clk4 = #(adj_delay/4) tmp_clk3;
+--`else
+-- always @ (vco_tmp) tmp_clk1 = vco_tmp;
+-- always @ (tmp_clk1) tmp_clk2 = tmp_clk1;
+-- always @ (tmp_clk2) tmp_clk3 = tmp_clk2;
+-- always @ (tmp_clk3) tmp_clk4 = tmp_clk3;
+--`endif
+--assign vco_shift = tmp_clk4;
+--synthesis translate_on
+end architecture arch;
+
diff --git a/pll/tb_top.vhd b/pll/tb_top.vhd
new file mode 100755
index 0000000..d6e9367
--- /dev/null
+++ b/pll/tb_top.vhd
@@ -0,0 +1,210 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:34:46 08/08/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/pll/tb_top.vhd
+-- Project Name: pll
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: n2_core_pll_cust
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_top IS
+END tb_top;
+
+ARCHITECTURE behavior OF tb_top IS
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT n2_core_pll_cust
+port (
+pll_char_out : out bit_vector(1 downto 0);
+pll_sys_clk : in bit_vector(1 downto 0);
+dr_sel_a : in bit_vector(1 downto 0);
+dr_sdel : in bit_vector(1 downto 0);
+pll_sdel : in bit_vector(1 downto 0);
+pll_sel_a : in bit_vector(1 downto 0);
+pll_div4 : in bit_vector(6 downto 0);
+pll_div3 : in bit_vector(5 downto 0);
+pll_div2 : in bit_vector(5 downto 0);
+pll_div1 : in bit_vector(5 downto 0);
+pll_clk_out_l : out bit;
+dr_clk_out_l : out bit;
+pll_clk_out : out bit;
+dr_clk_out : out bit;
+ccu_rst_ref_buf2 : out bit;
+ccu_rst_sys_clk : out bit;
+sel_l2clk_fbk : in bit;
+dr_stretch_a : in bit;
+pll_clamp_fltr : in bit;
+dr_ext_clk : in bit;
+ccu_serdes_dtm : in bit;
+pll_ext_clk : in bit;
+vreg_selbg_l : in bit;
+l2clk : in bit;
+dft_rst_a_l : in bit;
+pll_char_in : in bit;
+pll_arst_l : in bit;
+vdd_hv15 : in bit;
+pll_stretch_a : in bit;
+pll_bypass : in bit;
+pll_testmode : in bit
+);
+END COMPONENT;
+
+--Inputs
+signal pll_sys_clk : bit_vector(1 downto 0) := (others => '0');
+signal dr_sel_a : bit_vector(1 downto 0) := (others => '0');
+signal dr_sdel : bit_vector(1 downto 0) := (others => '0');
+signal pll_sdel : bit_vector(1 downto 0) := (others => '0');
+signal pll_sel_a : bit_vector(1 downto 0) := (others => '0');
+signal pll_div4 : bit_vector(6 downto 0) := (others => '0');
+signal pll_div3 : bit_vector(5 downto 0) := (others => '0');
+signal pll_div2 : bit_vector(5 downto 0) := (others => '0');
+signal pll_div1 : bit_vector(5 downto 0) := (others => '0');
+signal sel_l2clk_fbk : bit := '0';
+signal dr_stretch_a : bit := '0';
+signal pll_clamp_fltr : bit := '0';
+signal dr_ext_clk : bit := '0';
+signal ccu_serdes_dtm : bit := '0';
+signal pll_ext_clk : bit := '0';
+signal vreg_selbg_l : bit := '0';
+signal l2clk : bit := '0';
+signal dft_rst_a_l : bit := '0';
+signal pll_char_in : bit := '0';
+signal pll_arst_l : bit := '0';
+signal vdd_hv15 : bit := '0';
+signal pll_stretch_a : bit := '0';
+signal pll_bypass : bit := '0';
+signal pll_testmode : bit := '0';
+
+--Outputs
+signal pll_char_out : bit_vector(1 downto 0);
+signal pll_clk_out_l : bit;
+signal dr_clk_out_l : bit;
+signal pll_clk_out : bit;
+signal dr_clk_out : bit;
+signal ccu_rst_ref_buf2 : bit;
+signal ccu_rst_sys_clk : bit;
+
+-- Clock period definitions
+constant pll_sys_clk_period : time := 10 ns;
+constant ccu_rst_sys_clk_period : time := 10 ns;
+constant dr_ext_clk_period : time := 10 ns;
+constant pll_ext_clk_period : time := 10 ns;
+constant l2clk_period : time := 10 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: n2_core_pll_cust PORT MAP (
+pll_char_out => pll_char_out,
+pll_sys_clk => pll_sys_clk,
+dr_sel_a => dr_sel_a,
+dr_sdel => dr_sdel,
+pll_sdel => pll_sdel,
+pll_sel_a => pll_sel_a,
+pll_div4 => pll_div4,
+pll_div3 => pll_div3,
+pll_div2 => pll_div2,
+pll_div1 => pll_div1,
+pll_clk_out_l => pll_clk_out_l,
+dr_clk_out_l => dr_clk_out_l,
+pll_clk_out => pll_clk_out,
+dr_clk_out => dr_clk_out,
+ccu_rst_ref_buf2 => ccu_rst_ref_buf2,
+ccu_rst_sys_clk => ccu_rst_sys_clk,
+sel_l2clk_fbk => sel_l2clk_fbk,
+dr_stretch_a => dr_stretch_a,
+pll_clamp_fltr => pll_clamp_fltr,
+dr_ext_clk => dr_ext_clk,
+ccu_serdes_dtm => ccu_serdes_dtm,
+pll_ext_clk => pll_ext_clk,
+vreg_selbg_l => vreg_selbg_l,
+l2clk => l2clk,
+dft_rst_a_l => dft_rst_a_l,
+pll_char_in => pll_char_in,
+pll_arst_l => pll_arst_l,
+vdd_hv15 => vdd_hv15,
+pll_stretch_a => pll_stretch_a,
+pll_bypass => pll_bypass,
+pll_testmode => pll_testmode
+);
+
+-- Clock process definitions
+pll_sys_clk_process :process
+begin
+pll_sys_clk <= "00";
+wait for pll_sys_clk_period/4;
+pll_sys_clk <= "01";
+wait for pll_sys_clk_period/4;
+pll_sys_clk <= "10";
+wait for pll_sys_clk_period/4;
+pll_sys_clk <= "11";
+wait for pll_sys_clk_period/4;
+end process;
+
+--ccu_rst_sys_clk_process :process
+--begin
+--ccu_rst_sys_clk <= '0';
+--wait for ccu_rst_sys_clk_period/2;
+--ccu_rst_sys_clk <= '1';
+--wait for ccu_rst_sys_clk_period/2;
+--end process;
+
+dr_ext_clk_process :process
+begin
+dr_ext_clk <= '0';
+wait for dr_ext_clk_period/2;
+dr_ext_clk <= '1';
+wait for dr_ext_clk_period/2;
+end process;
+
+pll_ext_clk_process :process
+begin
+pll_ext_clk <= '0';
+wait for pll_ext_clk_period/2;
+pll_ext_clk <= '1';
+wait for pll_ext_clk_period/2;
+end process;
+
+l2clk_process :process
+begin
+l2clk <= '0';
+wait for l2clk_period/2;
+l2clk <= '1';
+wait for l2clk_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+wait for 100 ns;
+wait for pll_sys_clk_period*10;
+-- insert stimulus here
+wait;
+end process;
+
+END;
diff --git a/pll/top.vhd b/pll/top.vhd
new file mode 100755
index 0000000..5a50a6e
--- /dev/null
+++ b/pll/top.vhd
@@ -0,0 +1,364 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 10:02:21 08/06/2021
+-- Design Name:
+-- Module Name: pll - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+--
+-- WIP BASED ON PLL FROM OpenSPARCT2.1.3 PROJECT
+--
+
+entity n2_core_pll_cust is
+port (
+pll_char_out : out bit_vector(1 downto 0);
+pll_sys_clk : in bit_vector(1 downto 0);
+dr_sel_a : in bit_vector(1 downto 0);
+dr_sdel : in bit_vector(1 downto 0);
+pll_sdel : in bit_vector(1 downto 0);
+pll_sel_a : in bit_vector(1 downto 0);
+pll_div4 : in bit_vector(6 downto 0);
+pll_div3 : in bit_vector(5 downto 0);
+pll_div2 : in bit_vector(5 downto 0);
+pll_div1 : in bit_vector(5 downto 0);
+pll_clk_out_l : out bit;
+dr_clk_out_l : out bit;
+pll_clk_out : out bit;
+dr_clk_out : out bit;
+ccu_rst_ref_buf2 : out bit;
+ccu_rst_sys_clk : out bit;
+sel_l2clk_fbk : in bit;
+dr_stretch_a : in bit;
+pll_clamp_fltr : in bit;
+dr_ext_clk : in bit;
+ccu_serdes_dtm : in bit;
+pll_ext_clk : in bit;
+vreg_selbg_l : in bit;
+l2clk : in bit;
+dft_rst_a_l : in bit;
+pll_char_in : in bit;
+pll_arst_l : in bit;
+vdd_hv15 : in bit;
+pll_stretch_a : in bit;
+pll_bypass : in bit;
+pll_testmode : in bit
+);
+end entity n2_core_pll_cust;
+architecture Behavioral of n2_core_pll_cust is
+signal vdd : bit := '1';
+signal vss : bit := '0';
+signal vdd_reg : bit := '1';
+signal net0210 : bit_vector(9 downto 0);
+signal pll_jtag_lock_everlose,fast_l,ref_ck,l1clk_buf,net0189,fast_buf,vco2_clk,slow_buf,
+ref,pll_lock_pulse,dc_clk,pfd_reset,pll_lock_dyn,vco8_clk,net0131,net0132,bypass_clk,
+net0135,net0136,net0139,slow,fb,net0144,fast,net159,fb_ck,net0114,net163,div_ck3,
+net0117,dr_clk,fltr,net080,slow_l,vco_out,net0172,timed_pll_arst_l : bit;
+component n2_core_pll_vco_sum_cust is
+port (
+dc_clk : in bit;
+volb : out bit;
+vdd_reg : in bit;
+slow : in bit;
+slow_l : in bit;
+fast : in bit;
+fltr : in bit;
+fast_l : in bit
+);
+end component n2_core_pll_vco_sum_cust;
+component n2_core_pll_tpm3_all_cust is
+port (
+pll_stretch_a : in bit;
+ccu_serdes_dtm : in bit;
+dr_ext_clk : in bit;
+dc_clk : out bit;
+pll_clk_out_l : out bit;
+pll_div3 : in bit_vector(5 downto 0);
+pll_sdel : in bit_vector(1 downto 0);
+pll_sel_a : in bit_vector(1 downto 0);
+pll_bypass_clk_en : in bit;
+pll_arst_l : in bit;
+dr_clk_out : out bit;
+pll_bypass_clk : in bit;
+pll_clk_out : out bit;
+dr_clk_out_l : out bit;
+dr_stretch_a : in bit;
+pll_testmode : in bit;
+dr_sdel : in bit_vector(1 downto 0);
+vco8_clk : out bit;
+dr_sel_a : in bit_vector(1 downto 0);
+volb : in bit;
+vco2_clk : out bit;
+pll_ext_clk : in bit;
+pll_div4 : in bit_vector(6 downto 0);
+dft_rst_a_l : in bit
+);
+end component n2_core_pll_tpm3_all_cust;
+component n2_core_pll_inv_1x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_1x_cust;
+component n2_core_pll_vdd_xing_buf_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_vdd_xing_buf_4x_cust;
+component n2_core_pll_charc_cust is
+port (
+arst_l : in bit;
+ccu_rst_ref_buf2_l : out bit;
+testmode : in bit;
+dr_clk_out : in bit;
+ccu_rst_sys_clk : out bit;
+lock : in bit;
+pll_charc_out : out bit_vector(1 downto 0);
+fb_clk_l : in bit;
+pll_charc_in : in bit;
+ref_clk_l : in bit;
+fast : in bit;
+slow : in bit;
+ref : in bit;
+fb : in bit;
+vco_clk : in bit;
+l1clk : in bit
+);
+end component n2_core_pll_charc_cust;
+component n2_core_pll_inv_32x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_32x_cust;
+component n2_core_pll_inv_4x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_4x_cust;
+component n2_core_pll_inv_8x_cust is
+port (
+vdd_reg : in bit;
+o : out bit;
+i : in bit
+);
+end component n2_core_pll_inv_8x_cust;
+component n2_core_pll_pecl_all_cust is
+port (
+regdivcr : out bit;
+ref_ck : out bit;
+slow_l : out bit;
+fast : out bit;
+fast_l : out bit;
+pll_clamp_fltr : in bit;
+pll_lock_pulse : out bit;
+vdd_reg : in bit;
+fb_ck : out bit;
+pll_bypass_clk_en : in bit;
+ccu_serdes_dtm : in bit;
+l2clk : in bit;
+slow : out bit;
+slow_buf : out bit;
+pll_jtag_lock_everlose : out bit;
+pll_lock_dyn : out bit;
+raw_clk_byp : out bit;
+fast_buf : out bit;
+l2clkc : in bit;
+testmode : in bit;
+pll_arst_l : in bit;
+pll_div1 : in bit_vector(5 downto 0);
+pll_div2 : in bit_vector(5 downto 0);
+ref : out bit;
+fb : out bit;
+pll_sys_clk : in bit_vector(1 downto 0);
+l1clk_buf : out bit;
+pfd_reset : out bit;
+fltr : out bit
+);
+end component n2_core_pll_pecl_all_cust;
+component imaginary_timed_rst is
+port (
+ref : in bit;
+vco_clk : in bit;
+pll_div2 : in bit_vector(5 downto 0);
+pll_arst_l : in bit;
+timed_pll_arst_l : out bit
+);
+end component imaginary_timed_rst;
+begin
+x2 : n2_core_pll_vco_sum_cust port map (
+dc_clk => dc_clk,
+vdd_reg => vdd_reg,
+volb => vco_out,
+slow => slow,
+slow_l => slow_l,
+fast => fast,
+fltr => fltr,
+fast_l => fast_l
+);
+x6 : n2_core_pll_tpm3_all_cust port map (
+pll_div3 => pll_div3,
+pll_sdel => pll_sdel,
+pll_sel_a => pll_sel_a,
+dr_sdel => dr_sdel,
+dr_sel_a => dr_sel_a,
+pll_div4 => pll_div4,
+pll_stretch_a => pll_stretch_a,
+ccu_serdes_dtm => ccu_serdes_dtm,
+dr_ext_clk => dr_ext_clk,
+dc_clk => dc_clk,
+pll_clk_out_l => net0132,
+pll_bypass_clk_en => pll_bypass,
+--pll_arst_l => pll_arst_l,
+pll_arst_l => timed_pll_arst_l, -- worked around non-deterministic reset - mh157021
+dr_clk_out => dr_clk,
+pll_bypass_clk => bypass_clk,
+pll_clk_out => net0144,
+dr_clk_out_l => net0131,
+dr_stretch_a => dr_stretch_a,
+pll_testmode => pll_testmode,
+vco8_clk => vco8_clk,
+volb => not vco_out,
+vco2_clk => vco2_clk,
+pll_ext_clk => pll_ext_clk,
+dft_rst_a_l => dft_rst_a_l
+);
+x8 : n2_core_pll_inv_1x_cust port map (
+vdd_reg => vdd,
+o => net163,
+i => pll_arst_l
+);
+x9 : n2_core_pll_vdd_xing_buf_4x_cust port map (
+vdd_reg => vdd_reg,
+o => net159,
+i => net163
+);
+xcharc : n2_core_pll_charc_cust port map (
+pll_charc_out => pll_char_out,
+arst_l => pll_arst_l,
+ccu_rst_ref_buf2_l => net0139,
+testmode => pll_testmode,
+dr_clk_out => dr_clk,
+ccu_rst_sys_clk => ccu_rst_sys_clk,
+lock => pll_lock_dyn,
+fb_clk_l => fb_ck,
+pll_charc_in => pll_char_in,
+ref_clk_l => ref_ck,
+fast => fast_buf,
+slow => slow_buf,
+ref => ref,
+fb => fb,
+vco_clk => vco8_clk,
+l1clk => l1clk_buf
+);
+x14 : n2_core_pll_inv_32x_cust port map (
+vdd_reg => vdd,
+o => pll_clk_out_l,
+i => net0144
+);
+x15 : n2_core_pll_inv_32x_cust port map (
+vdd_reg => vdd,
+o => dr_clk_out_l,
+i => dr_clk
+);
+x16 : n2_core_pll_inv_4x_cust port map (
+vdd_reg => vdd_reg,
+o => net0117,
+i => net0172
+);
+x17 : n2_core_pll_inv_8x_cust port map (
+vdd_reg => vdd_reg,
+o => net0114,
+i => net0117
+);
+x18 : n2_core_pll_inv_32x_cust port map (
+vdd_reg => vdd,
+o => ccu_rst_ref_buf2,
+i => net0139
+);
+x1 : n2_core_pll_pecl_all_cust port map (
+pll_div1 => pll_div1,
+pll_div2 => pll_div2,
+pll_sys_clk => pll_sys_clk,
+regdivcr => div_ck3,
+ref_ck => ref_ck,
+slow_l => slow_l,
+fast => fast,
+fast_l => fast_l,
+pll_clamp_fltr => net0114,
+pll_lock_pulse => pll_lock_pulse,
+vdd_reg => vdd_reg,
+fb_ck => fb_ck,
+pll_bypass_clk_en => pll_bypass,
+ccu_serdes_dtm => ccu_serdes_dtm,
+l2clk => l2clk,
+slow => slow,
+slow_buf => slow_buf,
+pll_jtag_lock_everlose => pll_jtag_lock_everlose,
+pll_lock_dyn => pll_lock_dyn,
+raw_clk_byp => bypass_clk,
+fast_buf => fast_buf,
+l2clkc => vco2_clk,
+testmode => sel_l2clk_fbk,
+pll_arst_l => pll_arst_l,
+ref => ref,
+fb => fb,
+l1clk_buf => l1clk_buf,
+pfd_reset => pfd_reset,
+fltr => fltr
+);
+itr: imaginary_timed_rst port map (
+ref => ref,
+vco_clk => vco_out,
+pll_arst_l => pll_arst_l,
+pll_div2 => pll_div2,
+timed_pll_arst_l => timed_pll_arst_l
+);
+end architecture Behavioral;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/pwm_led.gif b/pwm_led.gif
new file mode 100755
index 0000000..a4dc844
Binary files /dev/null and b/pwm_led.gif differ
diff --git a/pwm_led/Nexys2_1200General.ucf b/pwm_led/Nexys2_1200General.ucf
new file mode 100755
index 0000000..3c6434d
--- /dev/null
+++ b/pwm_led/Nexys2_1200General.ucf
@@ -0,0 +1,252 @@
+## This file is a general .ucf for Nexys2 rev A board
+## To use it in a project:
+## - remove or comment the lines corresponding to unused pins
+## - rename the used signals according to the project
+
+## Signals Led<7>Led<4> are assigned to pins which change type from s3e500 to other dies using the same package
+## Both versions are provided in this file.
+## Keep only the appropriate one, and remove or comment the other one.
+
+#NET "SDA" LOC = "L15";
+#NET "SCL" LOC = "K12";
+
+## Clock pin for Nexys 2 Board
+NET "clk" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
+#NET "clk1" LOC = "U9"; # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK, Sch name = GCLK1
+
+## onBoard USB controller
+## NOTE: DEPP and DSTM net names use some of the same pins, if trying to use both DEPP and DSTM use a signle net name for each shared pin.
+
+## Data bus for both the DEPP and DSTM interfaces uncomment lines 19-26 if using either one
+#NET "DB<0>" LOC = "R14"; # Bank = 2, Pin name = IO_L24N_2/A20, Type = DUAL, Sch name = U-FD0
+#NET "DB<1>" LOC = "R13"; # Bank = 2, Pin name = IO_L22N_2/A22, Type = DUAL, Sch name = U-FD1
+#NET "DB<2>" LOC = "P13"; # Bank = 2, Pin name = IO_L22P_2/A23, Type = DUAL, Sch name = U-FD2
+#NET "DB<3>" LOC = "T12"; # Bank = 2, Pin name = IO_L20P_2, Type = I/O, Sch name = U-FD3
+#NET "DB<4>" LOC = "N11"; # Bank = 2, Pin name = IO_L18N_2, Type = I/O, Sch name = U-FD4
+#NET "DB<5>" LOC = "R11"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = U-FD5
+#NET "DB<6>" LOC = "P10"; # Bank = 2, Pin name = IO_L15N_2/D1/GCLK3, Type = DUAL/GCLK, Sch name = U-FD6
+#NET "DB<7>" LOC = "R10"; # Bank = 2, Pin name = IO_L15P_2/D2/GCLK2, Type = DUAL/GCLK, Sch name = U-FD7
+
+## If using the DEPP interface uncomment lines 29-32
+#NET "EppWRITE" LOC = "V16"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-FLAGC
+#NET "EppASTB" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
+#NET "EppDSTB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
+#NET "EppWAIT" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
+
+## If using the DSTM interface uncomment lines 35-44
+#NET "DstmIFCLK" LOC = "T15"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = U-IFCLK
+#NET "DstmSLCS" LOC = "T16"; # Bank = 2, Pin name = IO_L26P_2/VS0/A17, Type = DUAL, Sch name = U-SLCS
+#NET "DstmFLAGA" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
+#NET "DstmFLAGB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
+#NET "DstmADR<0>" LOC = "T14"; # Bank = 2, Pin name = IO_L24P_2/A21, Type = DUAL, Sch name = U-FIFOAD0
+#NET "DstmADR<1>" LOC = "V13"; # Bank = 2, Pin name = IO_L19N_2/VREF_2, Type = VREF, Sch name = U-FIFOAD1
+#NET "DstmSLRD" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
+#NET "DstmSLWR" LOC = "V9"; # Bank = 2, Pin name = IO_L13N_2/D3/GCLK15, Type = DUAL/GCLK, Sch name = U-SLWR
+#NET "DstmSLOE" LOC = "V15"; # Bank = 2, Pin name = IO_L25P_2/VS2/A19, Type = DUAL, Sch name = U-SLOE
+#NET "DstmPKTEND" LOC = "V12"; # Bank = 2, Pin name = IO_L19P_2, Type = I/O, Sch name = U-PKTEND
+
+#NET "UsbMode" LOC = "U15"; # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type = DUAL, Sch name = U-INT0#
+#NET "UsbRdy" LOC = "U13"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-RDY
+
+## onBoard Cellular RAM and StrataFlash
+#NET "io_MemOE" LOC = "T2"; # Bank = 3, Pin name = IO_L24P_3, Type = I/O, Sch name = OE
+#NET "io_MemWR" LOC = "N7"; # Bank = 2, Pin name = IO_L07P_2, Type = I/O, Sch name = WE
+
+#NET "io_RamAdv" LOC = "J4"; # Bank = 3, Pin name = IO_L11N_3/LHCLK1, Type = LHCLK, Sch name = MT-ADV
+#NET "io_RamCS" LOC = "R6"; # Bank = 2, Pin name = IO_L05P_2, Type = I/O, Sch name = MT-CE
+#NET "io_RamClk" LOC = "H5"; # Bank = 3, Pin name = IO_L08N_3, Type = I/O, Sch name = MT-CLK
+#NET "io_RamCRE" LOC = "P7"; # Bank = 2, Pin name = IO_L07N_2, Type = I/O, Sch name = MT-CRE
+#NET "io_RamLB" LOC = "K5"; # Bank = 3, Pin name = IO_L14N_3/LHCLK7, Type = LHCLK, Sch name = MT-LB
+#NET "io_RamUB" LOC = "K4"; # Bank = 3, Pin name = IO_L13N_3/LHCLK5, Type = LHCLK, Sch name = MT-UB
+#NET "RamWait" LOC = "F5"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = MT-WAIT
+
+#NET "FlashRp" LOC = "T5"; # Bank = 2, Pin name = IO_L04N_2, Type = I/O, Sch name = RP#
+#NET "io_FlashCS" LOC = "R5"; # Bank = 2, Pin name = IO_L04P_2, Type = I/O, Sch name = ST-CE
+#NET "FlashStSts" LOC = "D3"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = ST-STS
+
+#NET "io_MemAdr<1>" LOC = "J1"; # Bank = 3, Pin name = IO_L12P_3/LHCLK2, Type = LHCLK, Sch name = ADR1
+#NET "io_MemAdr<2>" LOC = "J2"; # Bank = 3, Pin name = IO_L12N_3/LHCLK3/IRDY2, Type = LHCLK, Sch name = ADR2
+#NET "io_MemAdr<3>" LOC = "H4"; # Bank = 3, Pin name = IO_L09P_3, Type = I/O, Sch name = ADR3
+#NET "io_MemAdr<4>" LOC = "H1"; # Bank = 3, Pin name = IO_L10N_3, Type = I/O, Sch name = ADR4
+#NET "io_MemAdr<5>" LOC = "H2"; # Bank = 3, Pin name = IO_L10P_3, Type = I/O, Sch name = ADR5
+#NET "io_MemAdr<6>" LOC = "J5"; # Bank = 3, Pin name = IO_L11P_3/LHCLK0, Type = LHCLK, Sch name = ADR6
+#NET "io_MemAdr<7>" LOC = "H3"; # Bank = 3, Pin name = IO_L09N_3, Type = I/O, Sch name = ADR7
+#NET "io_MemAdr<8>" LOC = "H6"; # Bank = 3, Pin name = IO_L08P_3, Type = I/O, Sch name = ADR8
+#NET "io_MemAdr<9>" LOC = "F1"; # Bank = 3, Pin name = IO_L05P_3, Type = I/O, Sch name = ADR9
+#NET "io_MemAdr<10>" LOC = "G3"; # Bank = 3, Pin name = IO_L06P_3, Type = I/O, Sch name = ADR10
+#NET "io_MemAdr<11>" LOC = "G6"; # Bank = 3, Pin name = IO_L07P_3, Type = I/O, Sch name = ADR11
+#NET "io_MemAdr<12>" LOC = "G5"; # Bank = 3, Pin name = IO_L07N_3, Type = I/O, Sch name = ADR12
+#NET "io_MemAdr<13>" LOC = "G4"; # Bank = 3, Pin name = IO_L06N_3/VREF_3, Type = VREF, Sch name = ADR13
+#NET "io_MemAdr<14>" LOC = "F2"; # Bank = 3, Pin name = IO_L05N_3, Type = I/O, Sch name = ADR14
+#NET "io_MemAdr<15>" LOC = "E1"; # Bank = 3, Pin name = IO_L03N_3, Type = I/O, Sch name = ADR15
+#NET "io_MemAdr<16>" LOC = "M5"; # Bank = 3, Pin name = IO_L19P_3, Type = I/O, Sch name = ADR16
+#NET "io_MemAdr<17>" LOC = "E2"; # Bank = 3, Pin name = IO_L03P_3, Type = I/O, Sch name = ADR17
+#NET "io_MemAdr<18>" LOC = "C2"; # Bank = 3, Pin name = IO_L01N_3, Type = I/O, Sch name = ADR18
+#NET "io_MemAdr<19>" LOC = "C1"; # Bank = 3, Pin name = IO_L01P_3, Type = I/O, Sch name = ADR19
+#NET "io_MemAdr<20>" LOC = "D2"; # Bank = 3, Pin name = IO_L02N_3/VREF_3, Type = VREF, Sch name = ADR20
+#NET "io_MemAdr<21>" LOC = "K3"; # Bank = 3, Pin name = IO_L13P_3/LHCLK4/TRDY2, Type = LHCLK, Sch name = ADR21
+#NET "io_MemAdr<22>" LOC = "D1"; # Bank = 3, Pin name = IO_L02P_3, Type = I/O, Sch name = ADR22
+#NET "io_MemAdr<23>" LOC = "K6"; # Bank = 3, Pin name = IO_L14P_3/LHCLK6, Type = LHCLK, Sch name = ADR23
+
+#NET "io_MemDB<0>" LOC = "L1"; # Bank = 3, Pin name = IO_L15P_3, Type = I/O, Sch name = DB0
+#NET "io_MemDB<1>" LOC = "L4"; # Bank = 3, Pin name = IO_L16N_3, Type = I/O, Sch name = DB1
+#NET "io_MemDB<2>" LOC = "L6"; # Bank = 3, Pin name = IO_L17P_3, Type = I/O, Sch name = DB2
+#NET "io_MemDB<3>" LOC = "M4"; # Bank = 3, Pin name = IO_L18P_3, Type = I/O, Sch name = DB3
+#NET "io_MemDB<4>" LOC = "N5"; # Bank = 3, Pin name = IO_L20N_3, Type = I/O, Sch name = DB4
+#NET "io_MemDB<5>" LOC = "P1"; # Bank = 3, Pin name = IO_L21N_3, Type = I/O, Sch name = DB5
+#NET "io_MemDB<6>" LOC = "P2"; # Bank = 3, Pin name = IO_L21P_3, Type = I/O, Sch name = DB6
+#NET "io_MemDB<7>" LOC = "R2"; # Bank = 3, Pin name = IO_L23N_3, Type = I/O, Sch name = DB7
+#NET "io_MemDB<8>" LOC = "L3"; # Bank = 3, Pin name = IO_L16P_3, Type = I/O, Sch name = DB8
+#NET "io_MemDB<9>" LOC = "L5"; # Bank = 3, Pin name = IO_L17N_3/VREF_3, Type = VREF, Sch name = DB9
+#NET "io_MemDB<10>" LOC = "M3"; # Bank = 3, Pin name = IO_L18N_3, Type = I/O, Sch name = DB10
+#NET "io_MemDB<11>" LOC = "M6"; # Bank = 3, Pin name = IO_L19N_3, Type = I/O, Sch name = DB11
+#NET "io_MemDB<12>" LOC = "L2"; # Bank = 3, Pin name = IO_L15N_3, Type = I/O, Sch name = DB12
+#NET "io_MemDB<13>" LOC = "N4"; # Bank = 3, Pin name = IO_L20P_3, Type = I/O, Sch name = DB13
+#NET "io_MemDB<14>" LOC = "R3"; # Bank = 3, Pin name = IO_L23P_3, Type = I/O, Sch name = DB14
+#NET "io_MemDB<15>" LOC = "T1"; # Bank = 3, Pin name = IO_L24N_3, Type = I/O, Sch name = DB15
+
+## 7 segment display
+#NET "seg<0>" LOC = "L18"; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA
+#NET "seg<1>" LOC = "F18"; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB
+#NET "seg<2>" LOC = "D17"; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC
+#NET "seg<3>" LOC = "D16"; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD
+#NET "seg<4>" LOC = "G14"; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE
+#NET "seg<5>" LOC = "J17"; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
+#NET "seg<6>" LOC = "H14"; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG
+#NET "dp" LOC = "C17"; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP
+
+#NET "an<0>" LOC = "F17"; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0
+#NET "an<1>" LOC = "H17"; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1
+#NET "an<2>" LOC = "C18"; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2
+#NET "an<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3
+
+## Leds
+NET "Led<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
+NET "Led<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
+NET "Led<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
+NET "Led<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
+NET "Led<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4? s3e500 only
+NET "Led<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5? s3e500 only
+NET "Led<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6? s3e500 only
+NET "Led<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7? s3e500 only
+NET "Led<4>" LOC = "E16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD4? other than s3e500
+NET "Led<5>" LOC = "P16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD5? other than s3e500
+NET "Led<6>" LOC = "E4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD6? other than s3e500
+NET "Led<7>" LOC = "P4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD7? other than s3e500
+
+## Switches
+NET "sw<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
+NET "sw<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
+NET "sw<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
+NET "sw<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
+NET "sw<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
+NET "sw<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
+NET "sw<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
+NET "sw<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7
+
+## Buttons
+NET "btn<0>" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
+NET "btn<1>" LOC = "D18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = BTN1
+NET "btn<2>" LOC = "E18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN2
+NET "btn<3>" LOC = "H13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN3
+
+## VGA Connector
+#NET "vgaRed<1>" LOC = "R9"; # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0
+#NET "vgaRed<2>" LOC = "T8"; # Bank = 2, Pin name = IO_L10N_2, Type = I/O, Sch name = RED1
+#NET "vgaRed<3>" LOC = "R8"; # Bank = 2, Pin name = IO_L10P_2, Type = I/O, Sch name = RED2
+#NET "vgaGreen<1>" LOC = "N8"; # Bank = 2, Pin name = IO_L09N_2, Type = I/O, Sch name = GRN0
+#NET "vgaGreen<2>" LOC = "P8"; # Bank = 2, Pin name = IO_L09P_2, Type = I/O, Sch name = GRN1
+#NET "vgaGreen<3>" LOC = "P6"; # Bank = 2, Pin name = IO_L05N_2, Type = I/O, Sch name = GRN2
+#NET "vgaBlue<2>" LOC = "U5"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = BLU1
+#NET "vgaBlue<3>" LOC = "U4"; # Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DUAL, Sch name = BLU2
+
+#NET "Hsync" LOC = "T4"; # Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type = DUAL, Sch name = HSYNC
+#NET "Vsync" LOC = "U3"; # Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUAL, Sch name = VSYNC
+
+## PS/2 connector
+#NET "PS2C" LOC = "R12"; # Bank = 2, Pin name = IO_L20N_2, Type = I/O, Sch name = PS2C
+#NET "PS2D" LOC = "P11"; # Bank = 2, Pin name = IO_L18P_2, Type = I/O, Sch name = PS2D
+
+## FX2 connector
+#NET "PIO<0>" LOC = "B4"; # Bank = 0, Pin name = IO_L24N_0, Type = I/O, Sch name = R-IO1
+#NET "PIO<1>" LOC = "A4"; # Bank = 0, Pin name = IO_L24P_0, Type = I/O, Sch name = R-IO2
+#NET "PIO<2>" LOC = "C3"; # Bank = 0, Pin name = IO_L25P_0, Type = I/O, Sch name = R-IO3
+#NET "PIO<3>" LOC = "C4"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO4
+#NET "PIO<4>" LOC = "B6"; # Bank = 0, Pin name = IO_L20P_0, Type = I/O, Sch name = R-IO5
+#NET "PIO<5>" LOC = "D5"; # Bank = 0, Pin name = IO_L23N_0/VREF_0, Type = VREF, Sch name = R-IO6
+#NET "PIO<6>" LOC = "C5"; # Bank = 0, Pin name = IO_L23P_0, Type = I/O, Sch name = R-IO7
+#NET "PIO<7>" LOC = "F7"; # Bank = 0, Pin name = IO_L19P_0, Type = I/O, Sch name = R-IO8
+#NET "PIO<8>" LOC = "E7"; # Bank = 0, Pin name = IO_L19N_0/VREF_0, Type = VREF, Sch name = R-IO9
+#NET "PIO<9>" LOC = "A6"; # Bank = 0, Pin name = IO_L20N_0, Type = I/O, Sch name = R-IO10
+#NET "PIO<10>" LOC = "C7"; # Bank = 0, Pin name = IO_L18P_0, Type = I/O, Sch name = R-IO11
+#NET "PIO<11>" LOC = "F8"; # Bank = 0, Pin name = IO_L17N_0, Type = I/O, Sch name = R-IO12
+#NET "PIO<12>" LOC = "D7"; # Bank = 0, Pin name = IO_L18N_0/VREF_0, Type = VREF, Sch name = R-IO13
+#NET "PIO<13>" LOC = "E8"; # Bank = 0, Pin name = IO_L17P_0, Type = I/O, Sch name = R-IO14
+#NET "PIO<14>" LOC = "E9"; # Bank = 0, Pin name = IO_L15P_0, Type = I/O, Sch name = R-IO15
+#NET "PIO<15>" LOC = "C9"; # Bank = 0, Pin name = IO_L14P_0/GCLK10, Type = GCLK, Sch name = R-IO16
+#NET "PIO<16>" LOC = "A8"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO17
+#NET "PIO<17>" LOC = "G9"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO18
+#NET "PIO<18>" LOC = "F9"; # Bank = 0, Pin name = IO_L15N_0, Type = I/O, Sch name = R-IO19
+#NET "PIO<19>" LOC = "D10"; # Bank = 0, Pin name = IO_L11P_0/GCLK4, Type = GCLK, Sch name = R-IO20
+#NET "PIO<20>" LOC = "A10"; # Bank = 0, Pin name = IO_L12N_0/GCLK7, Type = GCLK, Sch name = R-IO21
+#NET "PIO<21>" LOC = "B10"; # Bank = 0, Pin name = IO_L12P_0/GCLK6, Type = GCLK, Sch name = R-IO22
+#NET "PIO<22>" LOC = "A11"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO23
+#NET "PIO<23>" LOC = "D11"; # Bank = 0, Pin name = IO_L09N_0, Type = I/O, Sch name = R-IO24
+#NET "PIO<24>" LOC = "E10"; # Bank = 0, Pin name = IO_L11N_0/GCLK5, Type = GCLK, Sch name = R-IO25
+#NET "PIO<25>" LOC = "B11"; # Bank = 0, Pin name = IO/VREF_0, Type = VREF, Sch name = R-IO26
+#NET "PIO<26>" LOC = "C11"; # Bank = 0, Pin name = IO_L09P_0, Type = I/O, Sch name = R-IO27
+#NET "PIO<27>" LOC = "E11"; # Bank = 0, Pin name = IO_L08P_0, Type = I/O, Sch name = R-IO28
+#NET "PIO<28>" LOC = "F11"; # Bank = 0, Pin name = IO_L08N_0, Type = I/O, Sch name = R-IO29
+#NET "PIO<29>" LOC = "E12"; # Bank = 0, Pin name = IO_L06N_0, Type = I/O, Sch name = R-IO30
+#NET "PIO<30>" LOC = "F12"; # Bank = 0, Pin name = IO_L06P_0, Type = I/O, Sch name = R-IO31
+#NET "PIO<31>" LOC = "A13"; # Bank = 0, Pin name = IO_L05P_0, Type = I/O, Sch name = R-IO32
+#NET "PIO<32>" LOC = "B13"; # Bank = 0, Pin name = IO_L05N_0/VREF_0, Type = VREF, Sch name = R-IO33
+#NET "PIO<33>" LOC = "E13"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO34
+#NET "PIO<34>" LOC = "A14"; # Bank = 0, Pin name = IO_L04N_0, Type = I/O, Sch name = R-IO35
+#NET "PIO<35>" LOC = "C14"; # Bank = 0, Pin name = IO_L03N_0/VREF_0, Type = VREF, Sch name = R-IO36
+#NET "PIO<36>" LOC = "D14"; # Bank = 0, Pin name = IO_L03P_0, Type = I/O, Sch name = R-IO37
+#NET "PIO<37>" LOC = "B14"; # Bank = 0, Pin name = IO_L04P_0, Type = I/O, Sch name = R-IO38
+#NET "PIO<38>" LOC = "A16"; # Bank = 0, Pin name = IO_L01N_0, Type = I/O, Sch name = R-IO39
+#NET "PIO<39>" LOC = "B16"; # Bank = 0, Pin name = IO_L01P_0, Type = I/O, Sch name = R-IO40
+
+## 12 pin connectors
+
+##JA
+#NET "JA<0>" LOC = "L15"; # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1
+#NET "JA<1>" LOC = "K12"; # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2
+#NET "JA<2>" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
+#NET "JA<3>" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
+#NET "JA<4>" LOC = "K13"; # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL, Sch name = JA7
+#NET "JA<5>" LOC = "L16"; # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL, Sch name = JA8
+#NET "JA<6>" LOC = "M14"; # Bank = 1, Pin name = IO_L05P_1, Type = I/O, Sch name = JA9
+#NET "JA<7>" LOC = "M16"; # Bank = 1, Pin name = IO_L07N_1, Type = I/O, Sch name = JA10
+
+##JB
+#NET "JB<0>" LOC = "M13"; # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF, Sch name = JB1
+#NET "JB<1>" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
+#NET "JB<2>" LOC = "R15"; # Bank = 1, Pin name = IO_L03P_1, Type = I/O, Sch name = JB3
+#NET "JB<3>" LOC = "T17"; # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL, Sch name = JB4
+#NET "JB<4>" LOC = "P17"; # Bank = 1, Pin name = IO_L06P_1, Type = I/O, Sch name = JB7
+#NET "JB<5>" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
+#NET "JB<6>" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
+#NET "JB<7>" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
+
+##JC
+#NET "JC<0>" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
+#NET "JC<1>" LOC = "J16"; # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL, Sch name = JC2
+#NET "JC<2>" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
+#NET "JC<3>" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
+#NET "JC<4>" LOC = "H15"; # Bank = 1, Pin name = IO_L17N_1, Type = I/O, Sch name = JC7
+#NET "JC<5>" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
+#NET "JC<6>" LOC = "G16"; # Bank = 1, Pin name = IO_L18N_1, Type = I/O, Sch name = JC9
+#NET "JC<7>" LOC = "J12"; # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL, Sch name = JC10
+
+##JD - NOTE: For other JD pins see LD(3:0) above under "Leds"
+#NET "JD<0>" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
+#NET "JD<1>" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
+#NET "JD<2>" LOC = "N18"; # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3
+#NET "JD<3>" LOC = "P18"; # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4
+
+## RS232 connector
+#NET "RsRx" LOC = "U6"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = RS-RX
+#NET "RsTx" LOC = "P9"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = RS-TX
diff --git a/pwm_led/clock_divider_cnt.vhd b/pwm_led/clock_divider_cnt.vhd
new file mode 100755
index 0000000..d5f6890
--- /dev/null
+++ b/pwm_led/clock_divider_cnt.vhd
@@ -0,0 +1,66 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:42:10 09/18/2020
+-- Design Name:
+-- Module Name: clock_divider - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_divider_cnt is
+Generic (
+ g_board_clock : integer;
+ g_divider : integer
+);
+Port (
+ i_reset : in STD_LOGIC;
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+);
+end clock_divider_cnt;
+
+architecture Behavioral of clock_divider_cnt is
+begin
+
+p0 : process (i_clock,i_reset) is
+ variable clock_out : std_logic;
+ variable counter : integer := 0;
+begin
+ if (i_reset = '1') then
+ counter := 0;
+ clock_out := '0';
+ elsif (rising_edge(i_clock)) then
+ if (counter = (g_board_clock / g_divider) - 1) then
+ clock_out := '1';
+ counter := 0;
+ else
+ clock_out := '0';
+ counter := counter + 1;
+ end if;
+ end if;
+ o_clock <= clock_out;
+end process p0;
+
+end Behavioral;
diff --git a/pwm_led/clock_divider_sub.vhd b/pwm_led/clock_divider_sub.vhd
new file mode 100755
index 0000000..667d4fe
--- /dev/null
+++ b/pwm_led/clock_divider_sub.vhd
@@ -0,0 +1,63 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:42:10 09/18/2020
+-- Design Name:
+-- Module Name: clock_divider - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_divider_sub is
+Port(
+i_clk : in STD_LOGIC;
+i_board_clock : in INTEGER;
+i_divider : in INTEGER;
+o_clk : out STD_LOGIC
+);
+end clock_divider_sub;
+
+architecture Behavioral of clock_divider_sub is
+begin
+
+p0 : process (i_clk) is
+ variable clk_out : std_logic;
+ variable a : integer := i_board_clock;
+ variable b : integer := i_divider;
+begin
+ if (rising_edge(i_clk)) then
+ if (a <= 0) then
+ clk_out := '1';
+ a := i_board_clock;
+ b := i_divider;
+ else
+ clk_out := '0';
+ a := a - b;
+ end if;
+ end if;
+ o_clk <= clk_out;
+end process p0;
+
+end Behavioral;
+
diff --git a/pwm_led/debounce.vhd b/pwm_led/debounce.vhd
new file mode 100755
index 0000000..bd8cf95
--- /dev/null
+++ b/pwm_led/debounce.vhd
@@ -0,0 +1,93 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:44:39 03/09/2021
+-- Design Name:
+-- Module Name: debounce - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity debounce is
+Generic (
+ G_BOARD_CLOCK : integer := 50_000_000;
+ G_SIZE : integer := 8
+);
+Port (
+ i_clk : in STD_LOGIC;
+ i_reset : in STD_LOGIC;
+ i_btn : in STD_LOGIC;
+ o_db_btn : out STD_LOGIC
+);
+end debounce;
+
+architecture Behavioral of debounce is
+
+ COMPONENT clock_divider_cnt IS
+ Generic (
+ g_board_clock : integer;
+ g_divider : integer
+ );
+ Port (
+ i_reset : in STD_LOGIC;
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+ );
+ END COMPONENT clock_divider_cnt;
+
+ signal d_clk : std_logic;
+ signal q : std_logic_vector(G_SIZE-1 downto 0);
+ signal qn : std_logic_vector(G_SIZE-1 downto 0);
+
+begin
+
+ clk_div_cnt : clock_divider_cnt
+ GENERIC MAP (
+ g_board_clock => G_BOARD_CLOCK,
+ g_divider => G_BOARD_CLOCK/2/1250
+ )
+ PORT MAP (
+ i_reset => i_reset,
+ i_clock => i_clk,
+ o_clock => d_clk
+ );
+
+ p0 : process (i_clk,i_reset) is
+ begin
+ if (i_reset = '1') then
+ q <= (others => '0');
+ qn <= (others => '1');
+ o_db_btn <= '0';
+ elsif (rising_edge(i_clk)) then
+ q(G_SIZE-1 downto 0) <= q(G_SIZE-2 downto 0) & i_btn;
+ if (q(G_SIZE-1 downto 0) = qn(G_SIZE-1 downto 0)) then
+ o_db_btn <= '1';
+ q <= (others => '0');
+ else
+ o_db_btn <= '0';
+ end if;
+ end if;
+ end process p0;
+
+end Behavioral;
diff --git a/pwm_led/gamma_correction_green.sh b/pwm_led/gamma_correction_green.sh
new file mode 100755
index 0000000..7a47179
--- /dev/null
+++ b/pwm_led/gamma_correction_green.sh
@@ -0,0 +1,49 @@
+#!/bin/sh
+
+LD_LIBRARY_PATH=""
+
+echo "" | awk '
+BEGIN {
+ a = 256; # PWM for 8 bit
+ b = 1; # step
+ c=0; # start counter
+ gamma=1; # use GAMMA
+ table[0]=""; # array for hex variables
+ s="GAMMA_CORRECTION"; # script name
+ n="GREEN"; # color name
+}
+{
+ for (c=0;c '0');
+ elsif (rising_edge(clk)) then
+ if (enable = '1') then
+ count_i(G_SIZE-1 downto 0) <= input(G_SIZE-1 downto 0) xor ('0' & input(G_SIZE-1 downto 1));
+ else
+ count_i <= count_i;
+ end if;
+ end if;
+ end process;
+
+ output <= count_i;
+
+end architecture;
+
diff --git a/pwm_led/lfsr.vhd b/pwm_led/lfsr.vhd
new file mode 100755
index 0000000..008183c
--- /dev/null
+++ b/pwm_led/lfsr.vhd
@@ -0,0 +1,40 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+-- https://semiwiki.com/fpga/6129-pseudo-random-generator-tutorial-in-vhdl-part-1-3/
+
+entity lfsr1 is
+generic (G_SIZE : integer);
+port (
+ reset : in std_logic;
+ clk : in std_logic;
+ enable : in std_logic;
+ count : out std_logic_vector (G_SIZE-1 downto 0) -- lfsr output
+);
+end entity;
+
+architecture rtl of lfsr1 is
+
+ signal count_i : std_logic_vector (G_SIZE-1 downto 0);
+ signal feedback : std_logic;
+
+begin
+
+ feedback <= not(count_i(G_SIZE-1) xor count_i(G_SIZE-2)); -- LFSR size 4
+
+ process (reset, clk)
+ begin
+ if (reset = '1') then
+ count_i <= (others => '0');
+ elsif (rising_edge(clk)) then
+ if (enable = '1') then
+ count_i <= count_i(G_SIZE-2 downto 0) & feedback;
+ else
+ count_i <= count_i;
+ end if;
+ end if;
+ end process;
+
+ count <= count_i;
+
+end architecture;
diff --git a/pwm_led/pwm.vhd b/pwm_led/pwm.vhd
new file mode 100755
index 0000000..88c2a1a
--- /dev/null
+++ b/pwm_led/pwm.vhd
@@ -0,0 +1,107 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:06:53 02/26/2021
+-- Design Name:
+-- Module Name: pwm - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments: Majewski,Zbysiński "Układy FPGA w przykładach" list.4.24 p.97
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity PWM is
+Generic (PWM_RES : integer := 4);
+Port (
+ clk : in STD_LOGIC;
+ res : in STD_LOGIC;
+ ld : in STD_LOGIC;
+ data : in STD_LOGIC_VECTOR (PWM_RES-1 downto 0);
+ pwm : out STD_LOGIC
+);
+end PWM;
+
+architecture Behavioral of pwm is
+ signal data_int_cmp,data_int,cnt_out : std_logic_vector(PWM_RES-1 downto 0);
+ signal res_pwm_o,q,co : std_logic;
+ constant ZERO : std_logic_vector(PWM_RES-1 downto 0) := (others=>'0');
+ constant FF : std_logic_vector(PWM_RES-1 downto 0) := (others=>'1');
+begin
+ p0 : process (ld,res,data) is -- reg in 1st
+ begin
+ if (res = '1') then
+ data_int <= (others => '0');
+ elsif (ld = '1') then
+ data_int <= data;
+ end if;
+ end process p0;
+
+ p1 : process (co,res) is -- reg in 2st
+ begin
+ if (res = '1') then
+ data_int_cmp <= (others => '0');
+ elsif (rising_edge(co)) then
+ data_int_cmp <= data_int;
+ end if;
+ end process p1;
+
+ p2 : process (clk,res) is -- PWM counter
+ begin
+ if (res = '1') then
+ cnt_out <= (others => '0');
+ elsif (rising_edge(clk)) then
+ cnt_out <= std_logic_vector(to_unsigned(to_integer(unsigned(cnt_out))+1,PWM_RES));
+ end if;
+ end process p2;
+
+ p3 : process (clk,res,cnt_out) is -- signal gen carry from counter
+ begin
+ if (res = '1' or cnt_out < FF) then
+ co <= '0';
+ elsif (rising_edge(clk) and cnt_out = FF) then
+ co <= '1';
+ end if;
+ end process p3;
+
+ p4 : process (data_int_cmp,cnt_out) is -- PWM comparator
+ begin
+ if (cnt_out = ZERO) then
+ res_pwm_o <= '0';
+ elsif (data_int_cmp >= cnt_out) then
+ res_pwm_o <= '1';
+ else
+ res_pwm_o <= '0';
+ end if;
+ end process p4;
+
+ p5 : process (clk,res,res_pwm_o) is
+ begin
+ if (res = '1') then
+ q <= '0';
+ elsif (rising_edge(clk)) then
+ q <= res_pwm_o;
+ end if;
+ end process p5;
+
+ pwm <= q;
+end Behavioral;
+
diff --git a/pwm_led/pwm_led.xise b/pwm_led/pwm_led.xise
new file mode 100755
index 0000000..467eff8
--- /dev/null
+++ b/pwm_led/pwm_led.xise
@@ -0,0 +1,397 @@
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diff --git a/pwm_led/pwm_new.vhd b/pwm_led/pwm_new.vhd
new file mode 100755
index 0000000..be518a8
--- /dev/null
+++ b/pwm_led/pwm_new.vhd
@@ -0,0 +1,105 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:39:35 02/26/2021
+-- Design Name:
+-- Module Name: pwm - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity PWM_NEW is
+Generic (
+ PWM_WIDTH : integer := 8
+);
+Port (
+ i_clock : in STD_LOGIC;
+ i_reset : in STD_LOGIC;
+ i_load : in STD_LOGIC;
+ i_data : in INTEGER RANGE 0 TO 2**PWM_WIDTH-1;
+ o_pwm : out STD_LOGIC
+);
+end entity PWM_NEW;
+
+architecture Behavioral of PWM_NEW is
+
+ signal data : integer range 0 to 2**PWM_WIDTH-1;
+ signal pwm : std_logic;
+
+ type state_type is (idle,pwm_1,pwm_0);
+ signal state : state_type;
+
+begin
+
+ pa : process (i_clock) is
+ begin
+ if (rising_edge(i_clock)) then
+ if (i_load = '1') then
+ data <= i_data;
+ end if;
+ o_pwm <= pwm;
+ end if;
+ end process pa;
+
+ p0 : process (i_clock,i_reset) is
+ constant v_pwm_count : integer range 0 to 2**PWM_WIDTH-1 := 2**PWM_WIDTH-1;
+ variable v_pwm_index : integer range 0 to 2**PWM_WIDTH-1;
+ variable v_pwm : std_logic;
+ begin
+ if (i_reset = '1') then
+ state <= idle;
+ elsif (rising_edge(i_clock)) then
+ case (state) is
+ when idle =>
+ state <= pwm_1;
+ v_pwm_index := 0;
+ pwm <= '0';
+ when pwm_1 =>
+ if (v_pwm_index < data) then
+ v_pwm_index := v_pwm_index + 1;
+ if (v_pwm_index = 0 or data = 0) then
+ pwm <= '0';
+ else
+ pwm <= '1';
+ end if;
+ else
+ state <= pwm_0;
+ v_pwm_index := 0;
+ end if;
+ when pwm_0 =>
+ if (v_pwm_index < v_pwm_count - data) then
+ v_pwm_index := v_pwm_index + 1;
+ pwm <= '0';
+ else
+ state <= pwm_1;
+ v_pwm_index := 0;
+ end if;
+ when others =>
+ pwm <= '0';
+ end case;
+ end if;
+ end process p0;
+
+end Behavioral;
+
diff --git a/pwm_led/tb_debounce.vhd b/pwm_led/tb_debounce.vhd
new file mode 100755
index 0000000..afe7c49
--- /dev/null
+++ b/pwm_led/tb_debounce.vhd
@@ -0,0 +1,265 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:03:02 03/09/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/pwm_led/tb_debounce.vhd
+-- Project Name: pwm_led
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: debounce
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_debounce IS
+END tb_debounce;
+
+ARCHITECTURE behavior OF tb_debounce IS
+
+ -- Constant
+ constant SIZE : integer := 8;
+ constant DEBOUNCE_REGISTER : integer := 5;
+ constant G_BOARD_CLOCK : integer := 50_000_000;
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT debounce
+ GENERIC (
+ G_BOARD_CLOCK : integer;
+ G_SIZE : integer
+ );
+ PORT(
+ i_clk : IN std_logic;
+ i_reset : in STD_LOGIC;
+ i_btn : IN std_logic;
+ o_db_btn : OUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT lfsr1 IS
+ GENERIC (G_SIZE : integer);
+ PORT (
+ reset : in std_logic;
+ clk : in std_logic;
+ enable : in std_logic;
+ count : out std_logic_vector (G_SIZE-1 downto 0) -- lfsr output
+ );
+ END COMPONENT lfsr1;
+
+ COMPONENT graycode IS
+ GENERIC (G_SIZE : integer);
+ PORT (
+ reset : in std_logic;
+ clk : in std_logic;
+ enable : in std_logic;
+ input : in std_logic_vector (G_SIZE-1 downto 0);
+ output : out std_logic_vector (G_SIZE-1 downto 0)
+ );
+ END COMPONENT graycode;
+
+ COMPONENT clock_divider_cnt IS
+ Generic (
+ g_board_clock : integer;
+ g_divider : integer
+ );
+ Port (
+ i_reset : in STD_LOGIC;
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+ );
+ END COMPONENT clock_divider_cnt;
+
+ --Inputs
+ signal i_clk : std_logic := '0';
+ signal i_btn : std_logic := '0';
+ signal reset : std_logic := '0';
+ signal enable_gc : std_logic := '0';
+ signal enable_lfsr : std_logic := '0';
+ signal i_int : std_logic_vector (SIZE-1 downto 0) := (others => '0');
+
+ --Outputs
+ signal o_db_btn : std_logic;
+ signal o_gc : std_logic_vector (SIZE-1 downto 0);
+ signal o_lfsr : std_logic_vector (SIZE-1 downto 0);
+ signal o_clk_div : std_logic;
+
+ -- Clock period definitions
+ constant i_clk_period : time := (1_000_000_000/G_BOARD_CLOCK) * 1 ns; -- XXX 50Mhz
+
+ -- States
+ type state_type is (idle,start,lfsr_enable,lfsr_disable,lfsr_send,lfsr_increment,lfsr_wait0,gc_send,gc_increment,gc_wait0,stop);
+ signal state : state_type := idle;
+ signal simulation_finish : std_logic := '0';
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: debounce
+ GENERIC MAP (
+ G_BOARD_CLOCK => G_BOARD_CLOCK,
+ G_SIZE => DEBOUNCE_REGISTER
+ )
+ PORT MAP (
+ i_clk => i_clk,
+ i_reset => reset,
+ i_btn => i_btn,
+ o_db_btn => o_db_btn
+ );
+
+ uut_lfsr: lfsr1
+ GENERIC MAP (G_SIZE => SIZE)
+ PORT MAP (
+ reset => reset,
+ clk => i_clk,
+ enable => enable_lfsr,
+ count => o_lfsr
+ );
+
+ uut_graycode: graycode
+ GENERIC MAP (G_SIZE => SIZE)
+ PORT MAP (
+ reset => reset,
+ clk => i_clk,
+ enable => enable_gc,
+ input => i_int,
+ output => o_gc
+ );
+
+ uut_clkdiv: clock_divider_cnt
+ GENERIC MAP (
+ g_board_clock => G_BOARD_CLOCK,
+ g_divider => G_BOARD_CLOCK / SIZE -- out clk cnt
+ )
+ PORT MAP (
+ i_reset => reset,
+ i_clock => i_clk,
+ o_clock => o_clk_div
+ );
+
+ -- Clock process definitions
+ i_clk_process :process
+ begin
+ while simulation_finish = '0' loop
+ i_clk <= '0';
+ wait for i_clk_period/2;
+ i_clk <= '1';
+ wait for i_clk_period/2;
+ end loop;
+ wait;
+ end process;
+
+ -- Stimulus process
+ stim_proc: process (i_clk) is
+
+ constant WAIT0_COUNT : integer := SIZE;
+ variable wait0 : integer range 0 to WAIT0_COUNT-1 := 0;
+-- LFSR
+ variable index : integer range 0 to SIZE-1 := 0;
+ constant send_the_same : integer := 1;
+ variable send_the_same_index : integer range 0 to send_the_same-1 := 0;
+-- GRAYCODE
+ constant o_gc_max : integer := SIZE;
+ variable o_gc_index : integer range 0 to o_gc_max-1 := 0;
+ constant gc_max : std_logic_vector(SIZE-1 downto 0) := (others => '1');
+ variable gc_index : std_logic_vector(SIZE-1 downto 0) := (others => '0');
+
+ begin
+ -- insert stimulus here
+-- GRAYCODE
+ if (rising_edge(i_clk)) then
+ case (state) is
+ when idle =>
+ state <= start;
+ reset <= '1', '0' after 10*i_clk_period;
+ when start =>
+ state <= gc_send;
+ REPORT "GRAYCODE" SEVERITY NOTE;
+ when gc_send => -- start from gc mode
+ if (o_gc_index = o_gc_max-1) then
+ state <= gc_increment;
+ o_gc_index := 0;
+ enable_gc <= '1';
+ else
+ state <= gc_send;
+ i_btn <= o_gc(o_gc_index);
+ o_gc_index := o_gc_index + 1;
+ end if;
+ when gc_increment =>
+ enable_gc <= '0';
+ if (to_integer(unsigned(gc_index)) = to_integer(unsigned(gc_max))-1) then
+ state <= lfsr_enable; -- jump to lfsr mode
+ REPORT "LFSR" SEVERITY NOTE;
+ gc_index := std_logic_vector(to_unsigned(0,SIZE));
+ else
+ state <= gc_wait0;
+ gc_index := std_logic_vector(to_unsigned(to_integer(unsigned(gc_index) + 1),SIZE));
+ i_int <= gc_index;
+ end if;
+ when gc_wait0 =>
+ if (wait0 < WAIT0_COUNT) then
+ state <= gc_wait0;
+ wait0 := wait0 + 1;
+ i_btn <= '0';
+ else
+ state <= gc_send;
+ wait0 := 0;
+ end if;
+ when lfsr_enable =>
+ state <= lfsr_disable;
+ enable_lfsr <= '1';
+ when lfsr_disable =>
+ state <= lfsr_send;
+ enable_lfsr <= '0';
+ when lfsr_send =>
+ if (index = SIZE-1) then
+ state <= lfsr_increment;
+ index := 0;
+ else
+ state <= lfsr_send;
+ i_btn <= o_lfsr(index);
+ index := index + 1;
+ end if;
+ when lfsr_increment =>
+ if (o_lfsr = std_logic_vector(to_unsigned(0,SIZE))) then
+ state <= stop;
+ else
+ state <= lfsr_wait0;
+ end if;
+ when lfsr_wait0 =>
+ if (wait0 = WAIT0_COUNT-1) then
+ state <= lfsr_enable;
+ wait0 := 0;
+ else
+ state <= lfsr_wait0;
+ wait0 := wait0 + 1;
+ i_btn <= '0';
+ end if;
+ when stop =>
+ REPORT "END" SEVERITY NOTE;
+ simulation_finish <= '1';
+ state <= stop;
+ end case;
+ end if;
+ end process;
+
+END;
diff --git a/pwm_led/tb_debounce.wcfg b/pwm_led/tb_debounce.wcfg
new file mode 100755
index 0000000..1d2e160
--- /dev/null
+++ b/pwm_led/tb_debounce.wcfg
@@ -0,0 +1,210 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ tb_debounce
+ label
+
+ i_clk
+ i_clk
+
+
+ i_btn
+ i_btn
+
+
+ reset
+ reset
+
+
+ enable_gc
+ enable_gc
+
+
+ enable_lfsr
+ enable_lfsr
+
+
+ i_int[7:0]
+ i_int[7:0]
+
+
+ o_db_btn
+ o_db_btn
+
+
+ o_gc[7:0]
+ o_gc[7:0]
+
+
+ o_lfsr[7:0]
+ o_lfsr[7:0]
+
+
+ o_clk_div
+ o_clk_div
+
+
+ state
+ state
+
+
+ size
+ size
+
+
+ debounce_register
+ debounce_register
+
+
+ g_board_clock
+ g_board_clock
+
+
+ i_clk_period
+ i_clk_period
+
+
+
+ uut
+ label
+
+ i_clk
+ i_clk
+
+
+ i_reset
+ i_reset
+
+
+ i_btn
+ i_btn
+
+
+ o_db_btn
+ o_db_btn
+
+
+ d_clk
+ d_clk
+
+
+ q[4:0]
+ q[4:0]
+
+
+ qn[4:0]
+ qn[4:0]
+
+
+ g_board_clock
+ g_board_clock
+
+
+ g_size
+ g_size
+
+
+
+ uut_lfsr
+ label
+
+ reset
+ reset
+
+
+ clk
+ clk
+
+
+ enable
+ enable
+
+
+ count[7:0]
+ count[7:0]
+
+
+ count_i[7:0]
+ count_i[7:0]
+
+
+ feedback
+ feedback
+
+
+ g_size
+ g_size
+
+
+
+ uut_graycode
+ label
+
+ reset
+ reset
+
+
+ clk
+ clk
+
+
+ enable
+ enable
+
+
+ input[7:0]
+ input[7:0]
+
+
+ output[7:0]
+ output[7:0]
+
+
+ count_i[7:0]
+ count_i[7:0]
+
+
+ g_size
+ g_size
+
+
+
+ uut_clkdiv
+ label
+
+ i_reset
+ i_reset
+
+
+ i_clock
+ i_clock
+
+
+ o_clock
+ o_clock
+
+
+ g_board_clock
+ g_board_clock
+
+
+ g_divider
+ g_divider
+
+
+
diff --git a/pwm_led/tb_pwm.vhd b/pwm_led/tb_pwm.vhd
new file mode 100755
index 0000000..3cb0c54
--- /dev/null
+++ b/pwm_led/tb_pwm.vhd
@@ -0,0 +1,196 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:22:35 02/26/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/pwm_led/tb_pwm.vhd
+-- Project Name: pwm_led
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: PWM
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_pwm IS
+END tb_pwm;
+
+ARCHITECTURE behavior OF tb_pwm IS
+ constant PWM_RES : integer := 4;
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT PWM
+ GENERIC (PWM_RES : integer);
+ PORT(
+ clk : IN std_logic;
+ res : IN std_logic;
+ ld : IN std_logic;
+ data : IN std_logic_vector(PWM_RES-1 downto 0);
+ pwm : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal clk : std_logic := '0';
+ signal res : std_logic := '0';
+ signal ld : std_logic := '0';
+ signal data : std_logic_vector(PWM_RES-1 downto 0) := (others => '0');
+
+ --Outputs
+ signal o_pwm : std_logic;
+
+ -- Clock period definitions
+ constant clk_period : time := 20 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: PWM GENERIC MAP (PWM_RES => PWM_RES)
+ PORT MAP (
+ clk => clk,
+ res => res,
+ ld => ld,
+ data => data,
+ pwm => o_pwm
+ );
+
+ -- Clock process definitions
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ variable period : integer := 8*2;
+ begin
+ -- hold reset state for 100 ns.
+ res <= '1';
+ wait for 100 ns;
+ res <= '0';
+
+ ld <= '1';
+ data <= x"F";
+ wait for clk_period;
+ ld <= '0';
+ wait for period*clk_period;
+
+ ld <= '1';
+ data <= x"E";
+ wait for clk_period;
+ ld <= '0';
+ wait for period*clk_period;
+
+ ld <= '1';
+ data <= x"D";
+ wait for clk_period;
+ ld <= '0';
+ wait for period*clk_period;
+
+ ld <= '1';
+ data <= x"C";
+ wait for clk_period;
+ ld <= '0';
+ wait for period*clk_period;
+
+ ld <= '1';
+ data <= x"B";
+ wait for clk_period;
+ ld <= '0';
+ wait for period*clk_period;
+
+ ld <= '1';
+ data <= x"A";
+ wait for clk_period;
+ ld <= '0';
+ wait for period*clk_period;
+
+ ld <= '1';
+ data <= x"9";
+ wait for clk_period;
+ ld <= '0';
+ wait for period*clk_period;
+
+ ld <= '1';
+ data <= x"8";
+ wait for clk_period;
+ ld <= '0';
+ wait for period*clk_period;
+
+ ld <= '1';
+ data <= x"7";
+ wait for clk_period;
+ ld <= '0';
+ wait for period*clk_period;
+
+ ld <= '1';
+ data <= x"6";
+ wait for clk_period;
+ ld <= '0';
+ wait for period*clk_period;
+
+ ld <= '1';
+ data <= x"5";
+ wait for clk_period;
+ ld <= '0';
+ wait for period*clk_period;
+
+ ld <= '1';
+ data <= x"4";
+ wait for clk_period;
+ ld <= '0';
+ wait for period*clk_period;
+
+ ld <= '1';
+ data <= x"3";
+ wait for clk_period;
+ ld <= '0';
+ wait for period*clk_period;
+
+ ld <= '1';
+ data <= x"2";
+ wait for clk_period;
+ ld <= '0';
+ wait for period*clk_period;
+
+ ld <= '1';
+ data <= x"1";
+ wait for clk_period;
+ ld <= '0';
+ wait for period*clk_period;
+
+ ld <= '1';
+ data <= x"0";
+ wait for clk_period;
+ ld <= '0';
+ wait for period*clk_period;
+
+ end process;
+
+END;
diff --git a/pwm_led/tb_pwm.wcfg b/pwm_led/tb_pwm.wcfg
new file mode 100755
index 0000000..bece3d8
--- /dev/null
+++ b/pwm_led/tb_pwm.wcfg
@@ -0,0 +1,105 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ tb
+ label
+
+ clk
+ clk
+
+
+ res
+ res
+
+
+ ld
+ ld
+
+
+ data[3:0]
+ data[3:0]
+ HEXRADIX
+
+
+ o_pwm
+ o_pwm
+
+
+ clk_period
+ clk_period
+
+
+
+ pwm
+ label
+
+ clk
+ clk
+
+
+ res
+ res
+
+
+ ld
+ ld
+
+
+ data[3:0]
+ data[3:0]
+
+
+ pwm
+ pwm
+
+
+ data_int_cmp[3:0]
+ data_int_cmp[3:0]
+
+
+ data_int[3:0]
+ data_int[3:0]
+
+
+ cnt_out[3:0]
+ cnt_out[3:0]
+ UNSIGNEDDECRADIX
+
+
+ res_pwm_o
+ res_pwm_o
+
+
+ q
+ q
+
+
+ co
+ co
+
+
+ pwm_res
+ pwm_res
+
+
+ zero[3:0]
+ zero[3:0]
+
+
+ ff[3:0]
+ ff[3:0]
+
+
+
diff --git a/pwm_led/tb_pwm_new.vhd b/pwm_led/tb_pwm_new.vhd
new file mode 100755
index 0000000..0a09aa0
--- /dev/null
+++ b/pwm_led/tb_pwm_new.vhd
@@ -0,0 +1,121 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:54:47 02/26/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/pwm_led/tb_pwm_new.vhd
+-- Project Name: pwm_led
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: pwm_new
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_pwm_new IS
+END tb_pwm_new;
+
+ARCHITECTURE behavior OF tb_pwm_new IS
+
+ constant PWM_WIDTH : integer := 4;
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT pwm_new
+ GENERIC (PWM_WIDTH : integer);
+ PORT(
+ i_clock : IN std_logic;
+ i_reset : IN std_logic;
+ i_load : in STD_LOGIC;
+ i_data : IN INTEGER RANGE 0 TO 2**PWM_WIDTH;
+ o_pwm : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal i_clock : std_logic := '0';
+ signal i_reset : std_logic := '0';
+ signal i_load : std_logic := '0';
+ signal i_data : INTEGER RANGE 0 TO 2**PWM_WIDTH := 0;
+
+ --Outputs
+ signal o_pwm : std_logic;
+
+ -- Clock period definitions
+ constant i_clock_period : time := 20 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: pwm_new GENERIC MAP (PWM_WIDTH => PWM_WIDTH) PORT MAP (
+ i_clock => i_clock,
+ i_reset => i_reset,
+ i_load => i_load,
+ i_data => i_data,
+ o_pwm => o_pwm
+ );
+
+ -- Clock process definitions
+ i_clock_process :process
+ begin
+ i_clock <= '0';
+ wait for i_clock_period/2;
+ i_clock <= '1';
+ wait for i_clock_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ variable wait_pwm : integer := 2**PWM_WIDTH-1;
+ variable i_clock_period : time := i_clock_period;
+ begin
+ -- hold reset state for 100 ns.
+ i_reset <= '1';
+ wait for i_clock_period;
+ i_reset <= '0';
+
+ for i in 0 to 2**PWM_WIDTH-1 loop
+ i_load <= '1';
+ i_data <= i;
+ wait for i_clock_period;
+ i_load <= '0';
+ wait for i_clock_period*wait_pwm;
+ end loop;
+
+ i_reset <= '1';
+ wait for i_clock_period;
+ i_reset <= '0';
+
+ for i in 0 to 2**PWM_WIDTH-1 loop
+ i_load <= '1';
+ i_data <= ((2**PWM_WIDTH-1) - i);
+ wait for i_clock_period;
+ i_load <= '0';
+ wait for i_clock_period*wait_pwm;
+ end loop;
+
+ wait;
+ end process;
+
+END;
diff --git a/pwm_led/tb_pwm_new.wcfg b/pwm_led/tb_pwm_new.wcfg
new file mode 100755
index 0000000..a6c0926
--- /dev/null
+++ b/pwm_led/tb_pwm_new.wcfg
@@ -0,0 +1,99 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ tb_pwm_new
+ label
+
+ i_clock
+ i_clock
+
+
+ i_reset
+ i_reset
+
+
+ i_data
+ i_data
+
+
+ o_pwm
+ o_pwm
+
+
+ i_clock_period
+ i_clock_period
+
+
+
+ pwm_new
+ label
+
+ state
+ state
+
+
+ data
+ data
+
+
+ i_clock
+ i_clock
+
+
+ i_reset
+ i_reset
+
+
+ i_data
+ i_data
+
+
+ i_load
+ i_load
+
+
+ o_pwm
+ o_pwm
+
+
+ pwm_count[3:0]
+ pwm_count[3:0]
+ HEXRADIX
+
+
+ pwm_index[3:0]
+ pwm_index[3:0]
+ HEXRADIX
+
+
+ pwm_logic_1[3:0]
+ pwm_logic_1[3:0]
+ HEXRADIX
+
+
+ pwm_logic_0[3:0]
+ pwm_logic_0[3:0]
+ HEXRADIX
+
+
+ pwm
+ pwm
+
+
+ pwm_width
+ pwm_width
+
+
+
diff --git a/pwm_led/tb_top.vhd b/pwm_led/tb_top.vhd
new file mode 100755
index 0000000..7d86271
--- /dev/null
+++ b/pwm_led/tb_top.vhd
@@ -0,0 +1,232 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:27:16 02/26/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/pwm_led/tb_top.vhd
+-- Project Name: pwm_led
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_top IS
+END tb_top;
+
+ARCHITECTURE behavior OF tb_top IS
+ constant G_BOARD_CLOCK : integer := 1_000_000;
+ constant G_PWM_WIDTH : integer := 8;
+ constant G_LEDS : integer := 8;
+ constant G_SWITCHS : integer := 8;
+ constant G_BUTTONS : integer := 4;
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT top IS
+ Generic (
+ BOARD_CLOCK : integer;
+ PWM_WIDTH : integer;
+ LEDS : integer;
+ SWITCHS : integer;
+ BUTTONS : integer
+ );
+ Port (
+ clk : in STD_LOGIC;
+ btn : in STD_LOGIC_VECTOR(BUTTONS-1 downto 0);
+ sw : in STD_LOGIC_VECTOR (SWITCHS-1 downto 0);
+ led : out STD_LOGIC_VECTOR (LEDS-1 downto 0)
+ );
+ END COMPONENT top;
+
+ --Inputs
+ signal clk : std_logic := '0';
+ signal btn : std_logic_vector(G_BUTTONS-1 downto 0) := (others => '0');
+ signal sw : std_logic_vector(G_SWITCHS-1 downto 0) := (others => '0');
+
+ --Outputs
+ signal led : std_logic_vector(G_LEDS-1 downto 0);
+
+ -- Clock period definitions
+ constant clk_period : time := (1_000_000_000/G_BOARD_CLOCK) * 1 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: top
+ GENERIC MAP (
+ BOARD_CLOCK => G_BOARD_CLOCK,
+ PWM_WIDTH => G_PWM_WIDTH,
+ LEDS => G_LEDS,
+ SWITCHS => G_SWITCHS,
+ BUTTONS => G_BUTTONS
+ )
+ PORT MAP (
+ clk => clk,
+ btn => btn,
+ sw => sw,
+ led => led
+ );
+
+ -- Clock process definitions
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+ btn(0) <= '1', '0' after clk_period*100;
+
+ -- Stimulus process
+ stim_proc: process
+ variable delay : time := G_BOARD_CLOCK * clk_period;
+ constant WAIT_BUTTON : time := 40 ms;
+ begin
+
+ sw <= "00000001";
+ wait for delay;
+
+ btn(1) <= '1'; wait for WAIT_BUTTON;
+ btn(1) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ btn(1) <= '1'; wait for WAIT_BUTTON;
+ btn(1) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ btn(1) <= '1'; wait for WAIT_BUTTON;
+ btn(1) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ btn(1) <= '1'; wait for WAIT_BUTTON;
+ btn(1) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ btn(1) <= '1'; wait for WAIT_BUTTON;
+ btn(1) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ btn(1) <= '1'; wait for WAIT_BUTTON;
+ btn(1) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ btn(1) <= '1'; wait for WAIT_BUTTON;
+ btn(1) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ btn(1) <= '1'; wait for WAIT_BUTTON;
+ btn(1) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ btn(1) <= '1'; wait for WAIT_BUTTON;
+ btn(1) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ btn(1) <= '1'; wait for WAIT_BUTTON;
+ btn(1) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+
+ btn(2) <= '1'; wait for WAIT_BUTTON;
+ btn(2) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ btn(2) <= '1'; wait for WAIT_BUTTON;
+ btn(2) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ btn(2) <= '1'; wait for WAIT_BUTTON;
+ btn(2) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ btn(2) <= '1'; wait for WAIT_BUTTON;
+ btn(2) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ btn(2) <= '1'; wait for WAIT_BUTTON;
+ btn(2) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ btn(2) <= '1'; wait for WAIT_BUTTON;
+ btn(2) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ btn(2) <= '1'; wait for WAIT_BUTTON;
+ btn(2) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ btn(2) <= '1'; wait for WAIT_BUTTON;
+ btn(2) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ btn(2) <= '1'; wait for WAIT_BUTTON;
+ btn(2) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ btn(2) <= '1'; wait for WAIT_BUTTON;
+ btn(2) <= '0'; wait for WAIT_BUTTON;
+ wait for delay;
+ sw <= "00000000";
+ wait for delay;
+
+-- sw <= "00000000";
+-- wait for delay;
+--
+-- sw <= "00000001";
+-- wait for delay;
+-- sw <= "00000010";
+-- wait for delay;
+-- sw <= "00000100";
+-- wait for delay;
+-- sw <= "00001000";
+-- wait for delay;
+-- sw <= "00010000";
+-- wait for delay;
+-- sw <= "00100000";
+-- wait for delay;
+-- sw <= "01000000";
+-- wait for delay;
+-- sw <= "10000000";
+-- wait for delay;
+--
+-- sw <= "00000000";
+-- wait for delay;
+-- sw <= "00000001";
+-- wait for delay;
+-- sw <= "00000011";
+-- wait for delay;
+-- sw <= "00000111";
+-- wait for delay;
+-- sw <= "00001111";
+-- wait for delay;
+-- sw <= "00011111";
+-- wait for delay;
+-- sw <= "00111111";
+-- wait for delay;
+-- sw <= "01111111";
+-- wait for delay;
+-- sw <= "11111111";
+-- wait for delay;
+-- sw <= "01111111";
+-- wait for delay;
+-- sw <= "00111111";
+-- wait for delay;
+-- sw <= "00011111";
+-- wait for delay;
+-- sw <= "00001111";
+-- wait for delay;
+-- sw <= "00000111";
+-- wait for delay;
+-- sw <= "00000011";
+-- wait for delay;
+-- sw <= "00000001";
+-- wait for delay;
+-- sw <= "00000000";
+-- wait for delay;
+ end process;
+
+END;
diff --git a/pwm_led/tb_top.wcfg b/pwm_led/tb_top.wcfg
new file mode 100755
index 0000000..f7ff547
--- /dev/null
+++ b/pwm_led/tb_top.wcfg
@@ -0,0 +1,219 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ [0]
+ led[0]
+
+
+ s_wait0_index
+ s_wait0_index
+
+
+ tb_top
+ label
+
+ clk
+ clk
+
+
+ btn[3:0]
+ btn[3:0]
+
+
+ sw[7:0]
+ sw[7:0]
+
+
+ led[7:0]
+ led[7:0]
+
+
+ g_board_clock
+ g_board_clock
+
+
+ g_pwm_width
+ g_pwm_width
+
+
+ g_leds
+ g_leds
+
+
+ g_switchs
+ g_switchs
+
+
+ g_buttons
+ g_buttons
+
+
+ clk_period
+ clk_period
+
+
+
+ top
+ label
+
+ clk
+ clk
+
+
+ btn[3:0]
+ btn[3:0]
+
+
+ db_btn[3:0]
+ db_btn[3:0]
+
+
+ sw[7:0]
+ sw[7:0]
+
+
+ led[7:0]
+ led[7:0]
+
+
+ state
+ state
+
+
+ data[0:7]
+ data[0:7]
+
+
+ o_pwm[7:0]
+ o_pwm[7:0]
+
+
+ ld[7:0]
+ ld[7:0]
+
+
+ s_wait0
+ s_wait0
+
+
+ v_index[0:7]
+ v_index[0:7]
+
+
+ v_wait0
+ v_wait0
+
+
+ v_direction[7:0]
+ v_direction[7:0]
+
+
+ board_clock
+ board_clock
+
+
+ pwm_width
+ pwm_width
+
+
+ leds
+ leds
+
+
+ switchs
+ switchs
+
+
+ buttons
+ buttons
+
+
+ pwm_res
+ pwm_res
+
+
+ l_data
+ l_data
+
+
+ s_wait0_1
+ s_wait0_1
+
+
+ s_wait0_2
+ s_wait0_2
+
+
+ s_wait0_3
+ s_wait0_3
+
+
+ s_wait0_4
+ s_wait0_4
+
+
+ s_wait0_5
+ s_wait0_5
+
+
+ s_wait0_6
+ s_wait0_6
+
+
+ s_wait0_7
+ s_wait0_7
+
+
+ s_wait0_8
+ s_wait0_8
+
+
+ s_wait0_9
+ s_wait0_9
+
+
+ s_wait0_10
+ s_wait0_10
+
+
+ s_wait0_min
+ s_wait0_min
+
+
+ s_wait0_max
+ s_wait0_max
+
+
+ s_wait0_default
+ s_wait0_default
+
+ o_pwm[7:0]
+ o_pwm[7:0]
+
+
+ label
+ i_data
+ i_data
+ i_data1
+
+
+ label
+ i_data
+ i_data
+ i_data0
+
+
+
diff --git a/pwm_led/top.vhd b/pwm_led/top.vhd
new file mode 100755
index 0000000..433224f
--- /dev/null
+++ b/pwm_led/top.vhd
@@ -0,0 +1,420 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:46:04 02/26/2021
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_GAMMA_CORRECTION_GREEN.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top is
+Generic (
+ BOARD_CLOCK : integer := 50_000_000;
+ PWM_WIDTH : integer := 8;
+ LEDS : integer := 8;
+ SWITCHS : integer := 8;
+ BUTTONS : integer :=4
+);
+Port (
+ clk : in STD_LOGIC;
+ btn : in STD_LOGIC_VECTOR(BUTTONS-1 downto 0);
+ sw : in STD_LOGIC_VECTOR (SWITCHS-1 downto 0);
+ led : out STD_LOGIC_VECTOR (LEDS-1 downto 0)
+);
+end entity top;
+
+architecture Behavioral of top is
+ type state_type is (start,wait0,stop);
+ signal state : state_type;
+
+ COMPONENT PWM_NEW is
+ Generic (PWM_WIDTH : integer);
+ Port (
+ i_clock : in STD_LOGIC;
+ i_reset : in STD_LOGIC;
+ i_load : in STD_LOGIC;
+ i_data : in INTEGER RANGE 0 TO 2**PWM_WIDTH-1;
+ o_pwm : out STD_LOGIC
+ );
+ END COMPONENT PWM_NEW;
+
+ COMPONENT debounce IS
+ Generic (
+ G_BOARD_CLOCK : integer
+ );
+ Port (
+ i_clk : in STD_LOGIC;
+ i_reset : in STD_LOGIC;
+ i_btn : in STD_LOGIC;
+ o_db_btn : out STD_LOGIC
+ );
+ END COMPONENT debounce;
+
+ constant PWM_RES : integer := PWM_WIDTH;
+ constant L_DATA : integer range 0 to LEDS-1 := LEDS-1;
+ type A_DATA is array(0 to L_DATA) of INTEGER RANGE 0 TO 2**PWM_RES-1;
+ signal data : A_DATA;
+ signal o_pwm : std_logic_vector(PWM_RES-1 downto 0);
+ signal ld : std_logic_vector(LEDS-1 downto 0);
+
+ constant S_WAIT0_1 : integer := 1;
+ constant S_WAIT0_2 : integer := 2;
+ constant S_WAIT0_3 : integer := 3;
+ constant S_WAIT0_4 : integer := 4;
+ constant S_WAIT0_5 : integer := 5;
+ constant S_WAIT0_6 : integer := 6;
+ constant S_WAIT0_7 : integer := 7;
+ constant S_WAIT0_8 : integer := 8;
+ constant S_WAIT0_9 : integer := 9;
+ constant S_WAIT0_10 : integer := 10;
+ constant S_WAIT0_MIN : integer := 1;
+ constant S_WAIT0_MAX : integer := 10;
+ constant S_WAIT0_DEFAULT : integer := (BOARD_CLOCK/((2**PWM_RES)*S_WAIT0_MIN))-1;
+ signal S_WAIT0_INDEX : integer := 1;
+ signal S_WAIT0 : integer;
+
+ type A_NUM_GAMMA is array(0 to LEDS-1) of integer range 0 to NUMBER_GAMMA_CORRECTION_GREEN;
+ signal v_index : A_NUM_GAMMA;
+ signal v_wait0 : integer range 0 to S_WAIT0_DEFAULT;
+ signal v_direction : std_logic_vector(LEDS-1 downto 0);
+
+ signal db_btn : std_logic_vector(BUTTONS-1 downto 0);
+
+ COMPONENT PWM is
+ Generic (PWM_RES : integer);
+ Port (
+ i_clock : in STD_LOGIC;
+ i_reset : in STD_LOGIC;
+ i_load : in STD_LOGIC;
+ i_data : in INTEGER RANGE 0 TO 2**PWM_WIDTH-1;
+ o_pwm : out STD_LOGIC
+ );
+ END COMPONENT PWM_NEW;
+
+ constant PWM_RES : integer := 8;
+ constant L_DATA : integer range 0 to LEDS-1 := LEDS-1;
+ type A_DATA is array(0 to L_DATA) of INTEGER RANGE 0 TO 2**PWM_RES-1;
+ signal data : A_DATA;
+ signal o_pwm : std_logic_vector(PWM_RES-1 downto 0);
+ signal ld : std_logic_vector(LEDS-1 downto 0);
+ constant T_WAIT0 : integer range 0 to (BOARD_CLOCK/((2**PWM_RES)*2))-1 := (BOARD_CLOCK/((2**PWM_RES)*2))-1; -- XXX sim
+
+ type A_NUM_GAMMA is array(0 to LEDS-1) of integer range 0 to NUMBER_GAMMA_CORRECTION_GREEN;
+ signal v_index : A_NUM_GAMMA;
+ signal v_wait0 : integer range 0 to S_WAIT0_DEFAULT;
+ signal v_direction : std_logic_vector(LEDS-1 downto 0);
+
+ signal db_btn : std_logic_vector(BUTTONS-1 downto 0);
+
+begin
+
+ c0to4 : FOR i in 0 to BUTTONS-1 GENERATE
+ btn0to4 : debounce
+ GENERIC MAP (G_BOARD_CLOCK => BOARD_CLOCK)
+ PORT MAP (
+ i_clk => clk,
+ i_reset => btn(0),
+ i_btn => btn(i),
+ o_db_btn => db_btn(i)
+ );
+ END GENERATE c0to4;
+
+ c0to7 : FOR i IN 0 to LEDS-1 GENERATE
+ pwm0to7 : PWM_NEW
+ GENERIC MAP (PWM_WIDTH => PWM_RES) -- 0 to 255
+ PORT MAP (
+ i_clock => clk,
+ i_reset => btn(0),
+ i_load => ld(i),
+ i_data => data(i),
+ o_pwm => o_pwm(i)
+ );
+ END GENERATE c0to7;
+
+ p_a : process (db_btn) is
+ begin
+ if (db_btn(1)='1') then
+ if (S_WAIT0_INDEX < S_WAIT0_10) then
+ S_WAIT0_INDEX <= S_WAIT0_INDEX + 1;
+ else
+ S_WAIT0_INDEX <= S_WAIT0_10;
+ end if;
+ end if;
+ if (db_btn(2)='1') then
+ if (S_WAIT0_INDEX > S_WAIT0_1) then
+ S_WAIT0_INDEX <= S_WAIT0_INDEX - 1;
+ else
+ S_WAIT0_INDEX <= S_WAIT0_1;
+ end if;
+ end if;
+ end process p_a;
+
+ S_WAIT0 <= (BOARD_CLOCK/((2**PWM_RES)*S_WAIT0_1))-1 when S_WAIT0_INDEX=1 else
+ (BOARD_CLOCK/((2**PWM_RES)*S_WAIT0_2))-1 when S_WAIT0_INDEX=2 else
+ (BOARD_CLOCK/((2**PWM_RES)*S_WAIT0_3))-1 when S_WAIT0_INDEX=3 else
+ (BOARD_CLOCK/((2**PWM_RES)*S_WAIT0_4))-1 when S_WAIT0_INDEX=4 else
+ (BOARD_CLOCK/((2**PWM_RES)*S_WAIT0_5))-1 when S_WAIT0_INDEX=5 else
+ (BOARD_CLOCK/((2**PWM_RES)*S_WAIT0_6))-1 when S_WAIT0_INDEX=6 else
+ (BOARD_CLOCK/((2**PWM_RES)*S_WAIT0_7))-1 when S_WAIT0_INDEX=7 else
+ (BOARD_CLOCK/((2**PWM_RES)*S_WAIT0_8))-1 when S_WAIT0_INDEX=8 else
+ (BOARD_CLOCK/((2**PWM_RES)*S_WAIT0_9))-1 when S_WAIT0_INDEX=9 else
+ (BOARD_CLOCK/((2**PWM_RES)*S_WAIT0_10))-1 when S_WAIT0_INDEX=10 else
+ (BOARD_CLOCK/((2**PWM_RES)*S_WAIT0_1))-1;
+
+ p0 : process (clk,btn(0)) is
+ begin
+ if (btn(0) = '1') then
+ state <= start;
+ v_direction <= (others => '0');
+ v_wait0 <= 0;
+ v_index(0) <= 0;
+ v_index(1) <= 0;
+ v_index(2) <= 0;
+ v_index(3) <= 0;
+ v_index(4) <= 0;
+ v_index(5) <= 0;
+ v_index(6) <= 0;
+ v_index(7) <= 0;
+ ld(0) <= '1';
+ data(0) <= 0;
+ ld(1) <= '1';
+ data(1) <= 0;
+ ld(2) <= '1';
+ data(2) <= 0;
+ ld(3) <= '1';
+ data(3) <= 0;
+ ld(4) <= '1';
+ data(4) <= 0;
+ ld(5) <= '1';
+ data(5) <= 0;
+ ld(6) <= '1';
+ data(6) <= 0;
+ ld(7) <= '1';
+ data(7) <= 0;
+ elsif (rising_edge(clk)) then
+ case (state) is
+ when start =>
+ state <= wait0;
+ if (std_match(sw,"-------1")) then
+ ld(0) <= '1';
+ data(0) <= to_integer(unsigned(C_GAMMA_CORRECTION_GREEN(v_index(0))));
+ end if;
+ if (std_match(sw,"------1-")) then
+ ld(1) <= '1';
+ data(1) <= to_integer(unsigned(C_GAMMA_CORRECTION_GREEN(v_index(1))));
+ end if;
+ if (std_match(sw,"-----1--")) then
+ ld(2) <= '1';
+ data(2) <= to_integer(unsigned(C_GAMMA_CORRECTION_GREEN(v_index(2))));
+ end if;
+ if (std_match(sw,"----1---")) then
+ ld(3) <= '1';
+ data(3) <= to_integer(unsigned(C_GAMMA_CORRECTION_GREEN(v_index(3))));
+ end if;
+ if (std_match(sw,"---1----")) then
+ ld(4) <= '1';
+ data(4) <= to_integer(unsigned(C_GAMMA_CORRECTION_GREEN(v_index(4))));
+ end if;
+ if (std_match(sw,"--1-----")) then
+ ld(5) <= '1';
+ data(5) <= to_integer(unsigned(C_GAMMA_CORRECTION_GREEN(v_index(5))));
+ end if;
+ if (std_match(sw,"-1------")) then
+ ld(6) <= '1';
+ data(6) <= to_integer(unsigned(C_GAMMA_CORRECTION_GREEN(v_index(6))));
+ end if;
+ if (std_match(sw,"1-------")) then
+ ld(7) <= '1';
+ data(7) <= to_integer(unsigned(C_GAMMA_CORRECTION_GREEN(v_index(7))));
+ end if;
+ when wait0 =>
+ if (v_wait0 < S_WAIT0) then
+ state <= wait0;
+ v_wait0 <= v_wait0 + 1;
+ ld(0) <= '0';
+ ld(1) <= '0';
+ ld(2) <= '0';
+ ld(3) <= '0';
+ ld(4) <= '0';
+ ld(5) <= '0';
+ ld(6) <= '0';
+ ld(7) <= '0';
+ else
+ state <= stop;
+ v_wait0 <= 0;
+ end if;
+ when stop =>
+ state <= start;
+ if (std_match(sw,"-------1")) then
+ if (v_direction(0) = '0') then
+ if (v_index(0) < NUMBER_GAMMA_CORRECTION_GREEN-1) then
+ v_index(0) <= v_index(0) + 1;
+ else
+ v_index(0) <= NUMBER_GAMMA_CORRECTION_GREEN-1;
+ v_direction(0) <= '1';
+ end if;
+ end if;
+ if (v_direction(0) = '1') then
+ if (v_index(0) > 0) then
+ v_index(0) <= v_index(0) - 1;
+ else
+ v_index(0) <= 0;
+ v_direction(0) <= '0';
+ end if;
+ end if;
+ end if;
+ if (std_match(sw,"------1-")) then
+ if (v_direction(1) = '0') then
+ if (v_index(1) < NUMBER_GAMMA_CORRECTION_GREEN-1) then
+ v_index(1) <= v_index(1) + 1;
+ else
+ v_index(1) <= NUMBER_GAMMA_CORRECTION_GREEN-1;
+ v_direction(1) <= '1';
+ end if;
+ end if;
+ if (v_direction(1) = '1') then
+ if (v_index(1) > 0) then
+ v_index(1) <= v_index(1) - 1;
+ else
+ v_index(1) <= 0;
+ v_direction(1) <= '0';
+ end if;
+ end if;
+ end if;
+ if (std_match(sw,"-----1--")) then
+ if (v_direction(2) = '0') then
+ if (v_index(2) < NUMBER_GAMMA_CORRECTION_GREEN-1) then
+ v_index(2) <= v_index(2) + 1;
+ else
+ v_index(2) <= NUMBER_GAMMA_CORRECTION_GREEN-1;
+ v_direction(2) <= '1';
+ end if;
+ end if;
+ if (v_direction(2) = '1') then
+ if (v_index(2) > 0) then
+ v_index(2) <= v_index(2) - 1;
+ else
+ v_index(2) <= 0;
+ v_direction(2) <= '0';
+ end if;
+ end if;
+ end if;
+ if (std_match(sw,"----1---")) then
+ if (v_direction(3) = '0') then
+ if (v_index(3) < NUMBER_GAMMA_CORRECTION_GREEN-1) then
+ v_index(3) <= v_index(3) + 1;
+ else
+ v_index(3) <= NUMBER_GAMMA_CORRECTION_GREEN-1;
+ v_direction(3) <= '1';
+ end if;
+ end if;
+ if (v_direction(3) = '1') then
+ if (v_index(3) > 0) then
+ v_index(3) <= v_index(3) - 1;
+ else
+ v_index(3) <= 0;
+ v_direction(3) <= '0';
+ end if;
+ end if;
+ end if;
+ if (std_match(sw,"---1----")) then
+ if (v_direction(4) = '0') then
+ if (v_index(4) < NUMBER_GAMMA_CORRECTION_GREEN-1) then
+ v_index(4) <= v_index(4) + 1;
+ else
+ v_index(4) <= NUMBER_GAMMA_CORRECTION_GREEN-1;
+ v_direction(4) <= '1';
+ end if;
+ end if;
+ if (v_direction(4) = '1') then
+ if (v_index(4) > 0) then
+ v_index(4) <= v_index(4) - 1;
+ else
+ v_index(4) <= 0;
+ v_direction(4) <= '0';
+ end if;
+ end if;
+ end if;
+ if (std_match(sw,"--1-----")) then
+ if (v_direction(5) = '0') then
+ if (v_index(5) < NUMBER_GAMMA_CORRECTION_GREEN-1) then
+ v_index(5) <= v_index(5) + 1;
+ else
+ v_index(5) <= NUMBER_GAMMA_CORRECTION_GREEN-1;
+ v_direction(5) <= '1';
+ end if;
+ end if;
+ if (v_direction(5) = '1') then
+ if (v_index(5) > 0) then
+ v_index(5) <= v_index(5) - 1;
+ else
+ v_index(5) <= 0;
+ v_direction(5) <= '0';
+ end if;
+ end if;
+ end if;
+ if (std_match(sw,"-1------")) then
+ if (v_direction(6) = '0') then
+ if (v_index(6) < NUMBER_GAMMA_CORRECTION_GREEN-1) then
+ v_index(6) <= v_index(6) + 1;
+ else
+ v_index(6) <= NUMBER_GAMMA_CORRECTION_GREEN-1;
+ v_direction(6) <= '1';
+ end if;
+ end if;
+ if (v_direction(6) = '1') then
+ if (v_index(6) > 0) then
+ v_index(6) <= v_index(6) - 1;
+ else
+ v_index(6) <= 0;
+ v_direction(6) <= '0';
+ end if;
+ end if;
+ end if;
+ if (std_match(sw,"1-------")) then
+ if (v_direction(7) = '0') then
+ if (v_index(7) < NUMBER_GAMMA_CORRECTION_GREEN-1) then
+ v_index(7) <= v_index(7) + 1;
+ else
+ v_index(7) <= NUMBER_GAMMA_CORRECTION_GREEN-1;
+ v_direction(7) <= '1';
+ end if;
+ end if;
+ if (v_direction(7) = '1') then
+ if (v_index(7) > 0) then
+ v_index(7) <= v_index(7) - 1;
+ else
+ v_index(7) <= 0;
+ v_direction(7) <= '0';
+ end if;
+ end if;
+ end if;
+ when others => null;
+ end case;
+ end if;
+ end process p0;
+ led(led'range) <= o_pwm(o_pwm'range);
+end Behavioral;
diff --git a/rloc_rc/FF_JK.ucf b/rloc_rc/FF_JK.ucf
new file mode 100755
index 0000000..73b4160
--- /dev/null
+++ b/rloc_rc/FF_JK.ucf
@@ -0,0 +1,5 @@
+NET "i_r" LOC = "T1";
+NET "C" LOC = "T2";
+NET "J" LOC = "U1";
+NET "K" LOC = "V2";
+NET "Q1" LOC = "U3";
diff --git a/rloc_rc/FF_JK.vhd b/rloc_rc/FF_JK.vhd
new file mode 100755
index 0000000..6738044
--- /dev/null
+++ b/rloc_rc/FF_JK.vhd
@@ -0,0 +1,398 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity FF_JK is
+port (
+ i_r : in STD_LOGIC;
+ J,K,C : in STD_LOGIC;
+ Q1 : inout STD_LOGIC;
+ Q2 : inout STD_LOGIC
+);
+end entity FF_JK;
+
+architecture LUT of FF_JK is
+
+ constant W_NOT : time := 0 ns;
+ constant W_NAND2 : time := 0 ns;
+ constant W_NAND3 : time := 0 ns;
+ constant W_NAND4 : time := 0 ns;
+ constant W_Q1MS : time := 0 ns;
+ constant W_Q2MS : time := 0 ns;
+ constant W_C : time := 0 ns;
+ constant W_NOTC : time := 0 ns;
+ constant W_J : time := 0 ns;
+ constant W_K : time := 0 ns;
+
+ signal sa,sb,sc,sd : std_logic := '0';
+ signal se,sg : std_logic := '0';
+ signal sh,sj : std_logic := '0';
+ signal sk,sn : std_logic := '0';
+ signal so,sp : std_logic := '0';
+ signal sr,ss : std_logic := '0';
+ signal st,su : std_logic := '0';
+ signal sw,sx : std_logic := '0';
+ signal sy,sz : std_logic := '0';
+ signal i_rb : std_logic := '0';
+
+-- component GATE_NAND3 is
+-- Generic (
+-- DELAY_NAND3 : time := 1 ps
+-- );
+-- Port (
+-- A,B,C : in STD_LOGIC;
+-- D : out STD_LOGIC
+-- );
+-- end component GATE_NAND3;
+-- for all : GATE_NAND3 use entity WORK.GATE_NAND3(GATE_NAND3_LUT);
+
+ component GATE_AND is
+ generic (
+ delay_and : TIME := 1 ps
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_AND;
+ for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_LUT);
+
+ component GATE_NAND is
+ Generic (
+ DELAY_NAND : time := 1 ps
+ );
+ Port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_NAND;
+ for all : GATE_NAND use entity WORK.GATE_NAND(GATE_NAND_LUT);
+
+ component GATE_NAND3 is
+ Generic (
+ DELAY_NAND3 : time := 1 ps
+ );
+ Port (
+ A,B,C : in STD_LOGIC;
+ D : out STD_LOGIC
+ );
+ end component GATE_NAND3;
+ for all : GATE_NAND3 use entity WORK.GATE_NAND3(GATE_NAND3_LUT);
+
+ component GATE_NAND4 is
+ Generic (
+ DELAY_NAND4 : time := 1 ps
+ );
+ Port (
+ A,B,C,D : in STD_LOGIC;
+ E : out STD_LOGIC
+ );
+ end component GATE_NAND4;
+ for all : GATE_NAND4 use entity WORK.GATE_NAND4(GATE_NAND4_LUT);
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 1 ps
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ attribute rloc : string;
+ attribute rloc of clock_b : label is "X0Y0";
+ attribute rloc of i_rbar : label is "X0Y0";
+ attribute rloc of nand3_1u : label is "X1Y0";
+ attribute rloc of nand3_1d : label is "X1Y0";
+ attribute rloc of nand2_1u_1 : label is "X1Y1";
+ attribute rloc of nand2_1d_1 : label is "X1Y1";
+ attribute rloc of nand2_1u_2 : label is "X2Y0";
+ attribute rloc of nand2_1d_2 : label is "X2Y0";
+ attribute rloc of nand2_q1 : label is "X2Y1";
+ attribute rloc of nand2_q2 : label is "X2Y1";
+ attribute rloc of q1_out : label is "X3Y0";
+-- attribute rloc of q2_out : label is "X3Y1";
+ attribute h_set : string;
+ attribute h_set of clock_b : label is "rc/ffjk";
+ attribute h_set of i_rbar : label is "rc/ffjk";
+ attribute h_set of nand3_1u : label is "rc/ffjk";
+ attribute h_set of nand3_1d : label is "rc/ffjk";
+ attribute h_set of nand2_1u_1 : label is "rc/ffjk";
+ attribute h_set of nand2_1d_1 : label is "rc/ffjk";
+ attribute h_set of nand2_1u_2 : label is "rc/ffjk";
+ attribute h_set of nand2_1d_2 : label is "rc/ffjk";
+ attribute h_set of nand2_q1 : label is "rc/ffjk";
+ attribute h_set of nand2_q2 : label is "rc/ffjk";
+ attribute h_set of q1_out : label is "rc/ffjk";
+-- attribute h_set of q2_out" : label is "rc/ffjk";
+
+begin
+
+-- sa <= C after W_C;
+ -- clock bar
+ clock_b : GATE_NOT GENERIC MAP (W_NOTC)
+ PORT MAP (A=>C,B=>sb);
+-- sb <= not C after W_NOTC;
+-- sc <= j after W_J;
+-- sd <= k after W_K;
+
+ -- reset bar
+ i_rbar : GATE_NOT GENERIC MAP (W_NOT)
+ PORT MAP (A=>i_r,B=>i_rb);
+
+ -- nand3 1u plus i_r bar
+ nand3_1u : GATE_NAND4 GENERIC MAP (W_NAND3)
+ PORT MAP (A=>C,B=>j,C=>q2,D=>i_rb,E=>sg);
+-- se <= not (sa and sc and q2 and not i_r);
+-- sg <= se after W_NAND3;
+
+ -- nand3 1d
+ nand3_1d : GATE_NAND3 GENERIC MAP (W_NAND3)
+ PORT MAP (A=>C,B=>k,C=>q1,D=>sj);
+-- sh <= not (sa and sd and q1);
+-- sj <= sh after W_NAND3;
+
+ -- nand2 1u
+ nand2_1u_1 : GATE_NAND GENERIC MAP (W_NAND2)
+ PORT MAP (A=>sg,B=>sp,C=>sn);
+-- sk <= sg nand sp;
+-- sn <= sk after W_NAND2;
+
+ -- nand2 1d plus i_r bar
+ nand2_1d_1 : GATE_NAND3 GENERIC MAP (1 ns)
+ PORT MAP (A=>sj,B=>sn,C=>i_rb,D=>sp);
+-- so <= not (sj and sn and not i_r);
+-- sp <= so after 1 ns;
+
+ -- nand2 1u
+ nand2_1u_2 : GATE_NAND GENERIC MAP (W_NAND2)
+ PORT MAP (A=>sn,B=>sb,C=>ss);
+-- sr <= sn nand sb;
+-- ss <= sr after W_NAND2;
+
+ -- nand2 1d
+ nand2_1d_2 : GATE_NAND GENERIC MAP (W_NAND2)
+ PORT MAP (A=>sp,B=>sb,C=>su);
+-- st <= sp nand sb;
+-- su <= st after W_NAND2;
+
+ -- nand2 q1
+ nand2_q1 : GATE_NAND GENERIC MAP (1 ns)
+ PORT MAP (A=>ss,B=>q2,C=>sx);
+-- sw <= ss nand q2;
+-- sx <= sw after 1 ns;
+
+ -- nand2 q2
+ nand2_q2 : GATE_NAND GENERIC MAP (W_NAND2)
+ PORT MAP (A=>su,B=>q1,C=>sz);
+-- sy <= su nand q1;
+-- sz <= sy after W_NAND2;
+
+ q1_out : GATE_AND GENERIC MAP (1 ns)
+ PORT MAP (A=>sx,B=>i_rb,C=>q1);
+-- q1 <= sx and not i_r after 1 ns; -- XXX metastable
+ q2_out : BUF PORT MAP (I=>sz,O=>q2);
+-- q2 <= sz after W_Q2MS;
+
+end architecture LUT;
+
+--architecture structural of FF_JK is
+-- constant W_NAND2 : time := 0 ns;
+-- constant W_NAND3 : time := 0 ns;
+-- constant W_Q1MS : time := 0 ns;
+-- constant W_Q2MS : time := 0 ns;
+-- constant W_C : time := 0 ns;
+-- constant W_NOTC : time := 0 ns;
+-- constant W_J : time := 0 ns;
+-- constant W_K : time := 0 ns;
+--
+-- signal sa,sb,sc,sd : std_logic := '0';
+-- signal se,sg : std_logic := '0';
+-- signal sh,sj : std_logic := '0';
+-- signal sk,sn : std_logic := '0';
+-- signal so,sp : std_logic := '0';
+-- signal sr,ss : std_logic := '0';
+-- signal st,su : std_logic := '0';
+-- signal sw,sx : std_logic := '0';
+-- signal sy,sz : std_logic := '0';
+--begin
+--
+-- sa <= C after W_C;
+-- sb <= not C after W_NOTC;
+-- sc <= j after W_J;
+-- sd <= k after W_K;
+--
+-- -- nand3 1u
+-- se <= not (sa and sc and q2 and not i_r);
+-- sg <= se after W_NAND3;
+--
+-- -- nand3 1d
+-- sh <= not (sa and sd and q1);
+-- sj <= sh after W_NAND3;
+--
+-- -- nand2 1u
+-- sk <= sg nand sp;
+-- sn <= sk after W_NAND2;
+--
+-- -- nand2 1d
+-- so <= not (sj and sn and not i_r);
+-- sp <= so after 1 ns;
+--
+-- -- nand2 1u
+-- sr <= sn nand sb;
+-- ss <= sr after W_NAND2;
+--
+-- -- nand2 1d
+-- st <= sp nand sb;
+-- su <= st after W_NAND2;
+--
+-- -- nand2 q1
+-- sw <= ss nand q2;
+-- sx <= sw after 1 ns;
+--
+-- -- nand2 q2
+-- sy <= su nand q1;
+-- sz <= sy after W_NAND2;
+--
+-- q1 <= sx and not i_r after 1 ns; -- XXX metastable
+-- q2 <= sz after W_Q2MS;
+--
+--end architecture Structural;
+
+---- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#JK_flip-flop
+---- XXX strange operation
+--architecture Behavioral_FF_JK of FF_JK is
+--component GAND is
+--port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+--end component GAND;
+--component FF_SR_NOR is
+--port (S,R:in STD_LOGIC;Q1,Q2:inout STD_LOGIC);
+--end component FF_SR_NOR;
+----component GNOT is
+----generic (delay_not : TIME := 0 ns);
+----port (A:in STD_LOGIC;B:out STD_LOGIC);
+----end component GNOT;
+----for all : GNOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+--for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+--for all : FF_SR_NOR use entity WORK.FF_SR(Behavioral_NOR);
+----for all : FF_SR_NOR use entity WORK.FF_SR(Behavioral_NAND);
+----for all : FF_SR_NOR use entity WORK.FF_SR(Behavioral_ANDOR);
+----for all : FF_SR_NOR use entity WORK.FF_SR(Behavioral_NOT_S_NOT_R);
+--signal sa,sb,sc,sd: STD_LOGIC;
+----signal n1,n2 : STD_LOGIC;
+--begin
+--g1: GAND port map (K,C,sa);
+--g2: GAND port map (sa,Q1,sb);
+----gn1 : GNOT port map (sb,n1);
+--g3: GAND port map (C,J,sc);
+--g4: GAND port map (sc,Q2,sd);
+----gn2 : GNOT port map (sd,n2);
+--g5: FF_SR_NOR port map (sb,sd,Q1,Q2);
+--end architecture Behavioral_FF_JK;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#JK_flip-flop
+--architecture Structural of FF_JK is
+--component GAND is port (A,B:in STD_LOGIC;C:out STD_LOGIC); end component GAND;
+--component GOR is port (A,B:in STD_LOGIC;C:out STD_LOGIC); end component GOR;
+--component GNOT is port (A:in STD_LOGIC;B:out STD_LOGIC); end component GNOT;
+--for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+--for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+--for all : GNOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+--signal sa,sb,sc,sd,se,sf,sg,sh,si,sj : std_logic;
+--begin
+--g1 : GAND port map (J,C,sa);
+--g2 : GAND port map (K,C,sb);
+--
+--g3 : GAND port map (sa,Q2,sc);
+--
+--g4 : GNOT port map (sb,sd);
+--g5 : GAND port map (sd,Q1,se);
+--
+--g6 : GOR port map (sc,se,sf);
+--g7 : GNOT port map (sf,sg);
+--Q1 <= sf;
+--Q2 <= sg;
+--end architecture Structural;
+
+--architecture Structural of FF_JK is
+----component GAND is port (A,B:in STD_LOGIC;C:out STD_LOGIC); end component GAND;
+----component GOR is port (A,B:in STD_LOGIC;C:out STD_LOGIC); end component GOR;
+----component GNOT is port (A:in STD_LOGIC;B:out STD_LOGIC); end component GNOT;
+----for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+----for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+----for all : GNOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+--signal sa,sb,sc,sd,se,sf,sg,sh,si,sj : std_logic := '0';
+--constant clock_period : time := 1 ns;
+--begin
+--g1 : sa <= J and C;
+--sb <= sa and Q2 after clock_period;
+--
+--g2 : sc <= K and C;
+--sd <= sc and Q1 after clock_period;
+--
+--g3 : se <= sb nor Q2 after clock_period;
+--
+--g4 : sf <= sd nor Q1 after clock_period;
+--
+--Q1 <= se;
+--Q2 <= sf;
+--end architecture Structural;
+
+
+
+-- p0 : process (C,j,k,q1,q2) is
+-- variable sa,sb,sc,sd : std_logic;
+-- variable se,sf,sg : std_logic;
+-- variable sh,si,sj : std_logic;
+-- variable sk,sn : std_logic;
+-- variable so,sp : std_logic := '0';
+-- variable sr,ss : std_logic := '0';
+-- variable st,su : std_logic;
+-- variable sw,sx : std_logic;
+-- variable sy,sz : std_logic;
+-- begin
+-- sa := C;
+-- sb := not C;
+-- sc := j;
+-- sd := k;
+--
+-- -- nand3 1u
+-- se := sa and sc;
+-- sf := se and q2;
+-- sg := not sf;
+--
+-- -- nand3 1d
+-- sh := sa and sd;
+-- si := sh and q1;
+-- sj := not si;
+--
+-- -- nand2 1u
+-- sk := sg and sp;
+-- sn := not sk;
+--
+-- -- nand2 1d
+-- so := sj and sn;
+-- sp := not so;
+--
+-- -- nand2 1u
+-- sr := sn and sb;
+-- ss := not sr;
+--
+-- -- nand2 1d
+-- st := sp and sb;
+-- su := not st;
+--
+-- -- nand2 q1
+-- sw := ss and q2;
+-- sx := not sw;
+--
+-- -- nand2 q2
+-- sy := su and q1;
+-- sz := not sy;
+--
+-- q1 <= sx;
+-- q2 <= sy;
+-- end process p0;
diff --git a/rloc_rc/LUT2.vhd b/rloc_rc/LUT2.vhd
new file mode 100755
index 0000000..380b8f3
--- /dev/null
+++ b/rloc_rc/LUT2.vhd
@@ -0,0 +1,75 @@
+-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/LUT2.vhd,v 1.2 2009/12/01 02:57:17 yanx Exp $
+-------------------------------------------------------------------------------
+-- Copyright (c) 1995/2004 Xilinx, Inc.
+-- All Right Reserved.
+-------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor : Xilinx
+-- \ \ \/ Version : 11.1
+-- \ \ Description : Xilinx Functional Simulation Library Component
+-- / / 2-input Look-Up-Table with General Output
+-- /___/ /\ Filename : LUT2.vhd
+-- \ \ / \ Timestamp : Thu Apr 8 10:56:01 PDT 2004
+-- \___\/\___\
+--
+-- Revision:
+-- 03/23/04 - Initial version.
+-- 03/15/05 - Modified to handle the address unknown case.
+-- 03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842)
+-- 04/13/06 - Add address declaration. (CR229735)
+-- 11/30/09 - Remove extra line of O<=INIT_REG(0) (CR537043)
+-- End Revision
+
+----- CELL LUT2 -----
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+library unisim;
+use unisim.VPKG.all;
+use unisim.VCOMPONENTS.all;
+
+entity LUT2 is
+ generic(
+ INIT : bit_vector := X"0"
+ );
+
+ port(
+ O : out std_ulogic;
+
+ I0 : in std_ulogic;
+ I1 : in std_ulogic
+ );
+end LUT2;
+
+architecture LUT2_V of LUT2 is
+begin
+ VITALBehavior : process (I0, I1)
+ variable INIT_reg : std_logic_vector((INIT'length - 1) downto 0) := To_StdLogicVector(INIT);
+ variable address : std_logic_vector(1 downto 0);
+ variable address_int : integer := 0;
+ begin
+ address := I1 & I0;
+ address_int := SLV_TO_INT(address(1 downto 0));
+
+ if ((I1 xor I0) = '1' or (I1 xor I0) = '0') then
+ O <= INIT_reg(address_int);
+ else
+ if ((INIT_reg(0) = INIT_reg(1)) and (INIT_reg(2) = INIT_reg(3)) and
+ (INIT_reg(0) = INIT_reg(2))) then
+ O <= INIT_reg(0);
+ elsif ((I1 = '0') and (INIT_reg(0) = INIT_reg(1))) then
+ O <= INIT_reg(0);
+ elsif ((I1 = '1') and (INIT_reg(2) = INIT_reg(3))) then
+ O <= INIT_reg(2);
+ elsif ((I0 = '0') and (INIT_reg(0) = INIT_reg(2))) then
+ O <= INIT_reg(0);
+ elsif ((I0 = '1') and (INIT_reg(1) = INIT_reg(3))) then
+ O <= INIT_reg(1);
+ else
+ O <= 'X';
+ end if;
+ end if;
+ end process;
+end LUT2_V;
diff --git a/rloc_rc/LUT4.vhd b/rloc_rc/LUT4.vhd
new file mode 100755
index 0000000..e01566c
--- /dev/null
+++ b/rloc_rc/LUT4.vhd
@@ -0,0 +1,97 @@
+-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/LUT4.vhd,v 1.1 2008/06/19 16:59:24 vandanad Exp $
+-------------------------------------------------------------------------------
+-- Copyright (c) 1995/2004 Xilinx, Inc.
+-- All Right Reserved.
+-------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor : Xilinx
+-- \ \ \/ Version : 11.1
+-- \ \ Description : Xilinx Functional Simulation Library Component
+-- / / 4-input Look-Up-Table with General Output
+-- /___/ /\ Filename : LUT4.vhd
+-- \ \ / \ Timestamp : Thu Apr 8 10:56:02 PDT 2004
+-- \___\/\___\
+--
+-- Revision:
+-- 03/23/04 - Initial version.
+-- 03/15/05 - Modified to handle the address unknown case.
+-- 03/10/06 - replace TO_INTEGER to SLV_TO_INT. (CR 226842)
+-- End Revision
+
+----- CELL LUT4 -----
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+library unisim;
+use unisim.VPKG.all;
+use unisim.VCOMPONENTS.all;
+
+entity LUT4 is
+ generic(
+ INIT : bit_vector := X"0000"
+ );
+
+ port(
+ O : out std_ulogic;
+
+ I0 : in std_ulogic;
+ I1 : in std_ulogic;
+ I2 : in std_ulogic;
+ I3 : in std_ulogic
+ );
+end LUT4;
+
+architecture LUT4_V of LUT4 is
+
+function lut4_mux4 (d : std_logic_vector(3 downto 0); s : std_logic_vector(1 downto 0) )
+ return std_logic is
+
+ variable lut4_mux4_o : std_logic;
+ begin
+
+ if (((s(1) xor s(0)) = '1') or ((s(1) xor s(0)) = '0')) then
+ lut4_mux4_o := d(SLV_TO_INT(s));
+ elsif ((d(0) xor d(1)) = '0' and (d(2) xor d(3)) = '0'
+ and (d(0) xor d(2)) = '0') then
+ lut4_mux4_o := d(0);
+ elsif ((s(1) = '0') and (d(0) = d(1))) then
+ lut4_mux4_o := d(0);
+ elsif ((s(1) = '1') and (d(2) = d(3))) then
+ lut4_mux4_o := d(2);
+ elsif ((s(0) = '0') and (d(0) = d(2))) then
+ lut4_mux4_o := d(0);
+ elsif ((s(0) = '1') and (d(1) = d(3))) then
+ lut4_mux4_o := d(1);
+ else
+ lut4_mux4_o := 'X';
+ end if;
+
+ return (lut4_mux4_o);
+
+ end function lut4_mux4;
+
+ constant INIT_reg : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT);
+begin
+
+ lut_p : process (I0, I1, I2, I3)
+-- variable INIT_reg : std_logic_vector(15 downto 0) := To_StdLogicVector(INIT);
+ variable I_reg : std_logic_vector(3 downto 0);
+ begin
+
+ I_reg := TO_STDLOGICVECTOR(I3 & I2 & I1 & I0);
+
+ if ((I3 xor I2 xor I1 xor I0) = '1' or (I3 xor I2 xor I1 xor I0) = '0') then
+ O <= INIT_reg(SLV_TO_INT(I_reg));
+ else
+
+ O <= lut4_mux4 (
+ (lut4_mux4 ( INIT_reg(15 downto 12), I_reg(1 downto 0)) &
+ lut4_mux4 ( INIT_reg(11 downto 8), I_reg(1 downto 0)) &
+ lut4_mux4 ( INIT_reg(7 downto 4), I_reg(1 downto 0)) &
+ lut4_mux4 ( INIT_reg(3 downto 0), I_reg(1 downto 0))), I_reg(3 downto 2));
+
+ end if;
+ end process;
+end LUT4_V;
diff --git a/rloc_rc/gate_and.vhd b/rloc_rc/gate_and.vhd
new file mode 100755
index 0000000..be40aba
--- /dev/null
+++ b/rloc_rc/gate_and.vhd
@@ -0,0 +1,41 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_AND is
+generic (
+delay_and : TIME := 1 ps
+);
+port (
+A,B : in STD_LOGIC;
+C : out STD_LOGIC
+);
+end entity GATE_AND;
+
+architecture GATE_AND_BEHAVIORAL_1 of GATE_AND is
+begin
+C <= A and B after delay_and;
+end architecture GATE_AND_BEHAVIORAL_1;
+
+architecture GATE_AND_LUT of GATE_AND is
+-- signal T : std_logic;
+begin
+ b0 : block
+ attribute rloc : string;
+ attribute rloc of gate_and_LUT2_D : label is "X0Y0";
+ attribute h_set : string;
+ attribute h_set of gate_and_LUT2_D : label is "rc/ffjk/gate_and_LUT2_D";
+ begin
+ gate_and_LUT2_D : LUT2_D
+ generic map (
+ INIT => "1000")
+ port map (
+ LO => C,
+ O => open,
+ I0 => A,
+ I1 => B
+ );
+ end block b0;
+-- C <= T after delay_and;
+end architecture GATE_AND_LUT;
diff --git a/rloc_rc/gate_nand.vhd b/rloc_rc/gate_nand.vhd
new file mode 100755
index 0000000..73a27a9
--- /dev/null
+++ b/rloc_rc/gate_nand.vhd
@@ -0,0 +1,69 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 09:50:05 09/12/2021
+-- Design Name:
+-- Module Name: gate_and3 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity GATE_NAND is
+Generic (
+DELAY_NAND : time := 1 ps
+);
+Port (
+A,B : in STD_LOGIC;
+C : out STD_LOGIC
+);
+end GATE_NAND;
+
+architecture GATE_NAND_BEHAVIORAL_1 of GATE_NAND is
+ signal T : std_logic;
+begin
+T <= A nand B;
+C <= T after DELAY_NAND;
+end GATE_NAND_BEHAVIORAL_1;
+
+architecture GATE_NAND_LUT of GATE_NAND is
+-- signal T : std_logic;
+begin
+ b0 : block
+ attribute rloc : string;
+ attribute rloc of gate_nand_LUT2_D : label is "X0Y0";
+ attribute h_set : string;
+ attribute h_set of gate_nand_LUT2_D : label is "rc/ffjk/gate_nand_LUT2_D";
+ begin
+ gate_nand_LUT2_D : LUT2_D
+ generic map (
+ INIT => "0111")
+ port map (
+ LO => C,
+ O => open,
+ I0 => A,
+ I1 => B
+ );
+ end block b0;
+-- C <= T after DELAY_NAND;
+end architecture GATE_NAND_LUT;
\ No newline at end of file
diff --git a/rloc_rc/gate_nand3.vhd b/rloc_rc/gate_nand3.vhd
new file mode 100755
index 0000000..b34f27d
--- /dev/null
+++ b/rloc_rc/gate_nand3.vhd
@@ -0,0 +1,70 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 09:50:05 09/12/2021
+-- Design Name:
+-- Module Name: gate_and3 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity GATE_NAND3 is
+Generic (
+DELAY_NAND3 : time := 1 ps
+);
+Port (
+A,B,C : in STD_LOGIC;
+D : out STD_LOGIC
+);
+end GATE_NAND3;
+
+architecture GATE_NAND3_BEHAVIORAL_1 of GATE_NAND3 is
+ signal T : std_logic;
+begin
+T <= not (A and B and C);
+D <= T after DELAY_NAND3;
+end GATE_NAND3_BEHAVIORAL_1;
+
+architecture GATE_NAND3_LUT of GATE_NAND3 is
+-- signal T : std_logic;
+begin
+ b0 : block
+ attribute rloc : string;
+ attribute rloc of gate_nand3_LUT3_D : label is "X0Y0";
+ attribute h_set : string;
+ attribute h_set of gate_nand3_LUT3_D : label is "rc/ffjk/gate_nand3_LUT3_D";
+ begin
+ gate_nand3_LUT3_D : LUT3_D
+ generic map (
+ INIT => "01111111")
+ port map (
+ LO => D,
+ O => open,
+ I0 => A,
+ I1 => B,
+ I2 => C
+ );
+ end block b0;
+-- D <= T after DELAY_NAND3;
+end architecture GATE_NAND3_LUT;
\ No newline at end of file
diff --git a/rloc_rc/gate_nand4.vhd b/rloc_rc/gate_nand4.vhd
new file mode 100755
index 0000000..3c062b4
--- /dev/null
+++ b/rloc_rc/gate_nand4.vhd
@@ -0,0 +1,71 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 09:50:05 09/12/2021
+-- Design Name:
+-- Module Name: gate_and3 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity GATE_NAND4 is
+Generic (
+DELAY_NAND4 : time := 1 ps
+);
+Port (
+A,B,C,D : in STD_LOGIC;
+E : out STD_LOGIC
+);
+end GATE_NAND4;
+
+architecture GATE_NAND4_BEHAVIORAL_1 of GATE_NAND4 is
+ signal T : std_logic;
+begin
+T <= not (A and B and C and D);
+E <= T after DELAY_NAND4;
+end GATE_NAND4_BEHAVIORAL_1;
+
+architecture GATE_NAND4_LUT of GATE_NAND4 is
+-- signal T : std_logic;
+begin
+ b0 : block
+ attribute rloc : string;
+ attribute rloc of gate_nand4_LUT4_D : label is "X0Y0";
+ attribute h_set : string;
+ attribute h_set of gate_nand4_LUT4_D : label is "rc/ffjk/gate_nand4_LUT4_D";
+ begin
+ gate_nand4_LUT4_D : LUT4_D
+ generic map (
+ INIT => X"7FFF")
+ port map (
+ LO => E,
+ O => open,
+ I0 => A,
+ I1 => B,
+ I2 => C,
+ I3 => D
+ );
+ end block b0;
+-- E <= T after DELAY_NAND4;
+end architecture GATE_NAND4_LUT;
\ No newline at end of file
diff --git a/rloc_rc/gate_not.vhd b/rloc_rc/gate_not.vhd
new file mode 100755
index 0000000..e806423
--- /dev/null
+++ b/rloc_rc/gate_not.vhd
@@ -0,0 +1,40 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_NOT is
+generic (
+delay_not : TIME := 1 ps
+);
+port (
+A : in STD_LOGIC;
+B : out STD_LOGIC
+);
+end entity GATE_NOT;
+
+architecture GATE_NOT_BEHAVIORAL_1 of GATE_NOT is
+begin
+B <= not A after delay_not;
+end architecture GATE_NOT_BEHAVIORAL_1;
+
+architecture GATE_NOT_LUT of GATE_NOT is
+-- signal T : std_logic;
+begin
+ b0 : block
+ attribute rloc : string;
+ attribute rloc of gate_not_LUT1_D : label is "X0Y0";
+ attribute h_set : string;
+ attribute h_set of gate_not_LUT1_D : label is "rc/ffjk/gate_not_LUT1_D";
+ begin
+ gate_not_LUT1_D : LUT1_D
+ generic map (
+ INIT => "01")
+ port map (
+ LO => B,
+ O => open,
+ I0 => A
+ );
+ end block b0;
+-- B <= T after delay_not;
+end architecture GATE_NOT_LUT;
diff --git a/rloc_rc/gate_or.vhd b/rloc_rc/gate_or.vhd
new file mode 100755
index 0000000..dd262a6
--- /dev/null
+++ b/rloc_rc/gate_or.vhd
@@ -0,0 +1,41 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_OR is
+generic (
+delay_or : TIME := 1 ps
+);
+port (
+A,B : in STD_LOGIC;
+C : out STD_LOGIC
+);
+end entity GATE_OR;
+
+architecture GATE_OR_BEHAVIORAL_1 of GATE_OR is
+begin
+C <= A or B after delay_or;
+end architecture GATE_OR_BEHAVIORAL_1;
+
+architecture GATE_OR_LUT of GATE_OR is
+-- signal T : std_logic;
+begin
+ b0 : block
+ attribute rloc : string;
+ attribute rloc of gate_or_LUT2_D : label is "X0Y0";
+ attribute h_set : string;
+ attribute h_set of gate_or_LUT2_D : label is "rc/ffjk/gate_or_LUT2_D";
+ begin
+ gate_or_LUT2_D : LUT2_D
+ generic map (
+ INIT => "1110")
+ port map (
+ O => open,
+ LO => C,
+ I0 => A,
+ I1 => B
+ );
+ end block b0;
+-- C <= T after delay_or;
+end architecture GATE_OR_LUT;
diff --git a/rloc_rc/ripple_counter.ucf b/rloc_rc/ripple_counter.ucf
new file mode 100755
index 0000000..29d861e
--- /dev/null
+++ b/rloc_rc/ripple_counter.ucf
@@ -0,0 +1,5 @@
+NET "i_clock" LOC = "T1";
+NET "i_cpb" LOC = "T2";
+NET "i_mrb" LOC = "U1";
+NET "i_ud" LOC = "V2";
+NET "o_q<0>" LOC = "U3";
diff --git a/rloc_rc/ripple_counter.vhd b/rloc_rc/ripple_counter.vhd
new file mode 100755
index 0000000..d3adb74
--- /dev/null
+++ b/rloc_rc/ripple_counter.vhd
@@ -0,0 +1,162 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:32:30 05/04/2021
+-- Design Name:
+-- Module Name: ripple_counter - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity ripple_counter is
+Generic (
+N : integer := 4;
+MAX : integer := 16
+);
+Port (
+i_clock : in std_logic;
+i_cpb : in std_logic;
+i_mrb : in std_logic;
+i_ud : in std_logic;
+o_q : inout std_logic_vector(N-1 downto 0)
+);
+end ripple_counter;
+
+architecture Behavioral of ripple_counter is
+
+ component FF_JK is
+ port (
+ i_r:in STD_LOGIC;
+ J,K,C:in STD_LOGIC;
+ Q1:inout STD_LOGIC;
+ Q2:inout STD_LOGIC
+ );
+ end component FF_JK;
+ for all : FF_JK use entity WORK.FF_JK(LUT);
+
+ component GATE_AND is
+ generic (
+ delay_and : TIME := 1 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_AND;
+ for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_LUT);
+
+ component GATE_OR is
+ generic (
+ delay_or : TIME := 1 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_OR;
+ for all : GATE_OR use entity WORK.GATE_OR(GATE_OR_LUT);
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 1 ns
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ signal cp,mr : std_logic;
+ signal q1,q2 : std_logic_vector(N-1 downto 0);
+ signal ping,ping1,ping2 : std_logic;
+ signal ffjk_and_u,ffjk_and_d,ffjk_or : std_logic_vector(N-1 downto 0); -- XXX omit last FF JK
+ signal ud,udb : std_logic;
+ signal gated_clock : std_logic := '0';
+ constant a : std_logic_vector(N-1 downto 0) := std_logic_vector(to_unsigned(MAX,N));
+ constant b : std_logic_vector(N-1 downto 0) := std_logic_vector(to_unsigned(0,N));
+
+ constant WAIT_AND : time := 0 ps;
+ constant WAIT_OR : time := 0 ps;
+ constant WAIT_NOT : time := 0 ps;
+
+begin
+
+ ffjk_or(N-1) <= '0';
+ gated_clock_gand_lut2 : GATE_AND generic map (WAIT_AND) port map (A=>i_clock,B=>i_cpb,C=>gated_clock); -- XXX ~20mhz
+ o_q <= q1;
+ mr_block : mr <= '1' when q1 = a or i_mrb = '1' else '0';
+
+ g0_not_clock : GATE_NOT generic map (WAIT_NOT) port map (A=>i_ud,B=>udb);
+
+ g0_and_u : for i in 0 to N-1 generate -- XXX omit last FF JK
+ g0_and_u_first : if (i=0) generate
+ g0_and_u_first : GATE_AND generic map (WAIT_AND) port map (A=>q1(i),B=>i_ud,C=>ffjk_and_u(i));
+ end generate g0_and_u_first;
+ g0_and_u_chain : if (i>0) generate
+ g0_and_u_chain : GATE_AND generic map (WAIT_AND) port map (A=>q1(i),B=>ffjk_and_u(i-1),C=>ffjk_and_u(i));
+ end generate g0_and_u_chain;
+ end generate g0_and_u;
+
+ g0_and_d : for i in 0 to N-1 generate -- XXX omit last FF JK
+ g0_and_d_first : if (i=0) generate
+ g0_and_d_first : GATE_AND generic map (WAIT_AND) port map (A=>q2(i),B=>udb,C=>ffjk_and_d(i)); -- XXX udb make unconnected
+ end generate g0_and_d_first;
+ g0_and_d_chain : if (i>0) generate
+ g0_and_d_chain : GATE_AND generic map (WAIT_AND) port map (A=>q2(i),B=>ffjk_and_d(i-1),C=>ffjk_and_d(i));
+ end generate g0_and_d_chain;
+ end generate g0_and_d;
+
+ g0_or : for i in 0 to N-1 generate -- XXX omit last FF JK
+ g0_or_chain : GATE_OR generic map (WAIT_OR) port map (A=>ffjk_and_u(i),B=>ffjk_and_d(i),C=>ffjk_or(i));
+ end generate g0_or;
+
+ g0 : for i in 0 to N-1 generate
+ ffjk_first : if (i=0) generate
+ b0 : block
+ attribute rloc : string;
+ attribute rloc of ffjk_first_1 : label is "X0Y8";
+ attribute h_set : string;
+ attribute h_set of ffjk_first_1 : label is "rc";
+ begin
+ ffjk_first_1 : FF_JK port map (i_r=>mr,J=>i_cpb,K=>i_cpb,C=>gated_clock,Q1=>q1(i),Q2=>q2(i));
+ end block b0;
+ end generate ffjk_first;
+ ffjk_chain : if (i>0) generate
+ b1 : block
+ -- XXX UG625 p231
+ constant row1 : natural := i * 20;
+ constant rloc_str : string := ""
+ & "" & "X" & natural'image(row1) & "Y" & "8";
+ attribute rloc : string;
+ attribute rloc of ffjk_chain_1 : label is rloc_str;
+ attribute h_set : string;
+ attribute h_set of ffjk_chain_1 : label is "rc";
+ begin
+ ffjk_chain_1 : FF_JK port map (i_r=>mr,J=>ffjk_or(i-1),K=>ffjk_or(i-1),C=>gated_clock,Q1=>q1(i),Q2=>q2(i));
+ end block b1;
+ end generate ffjk_chain;
+ end generate g0;
+
+end Behavioral;
diff --git a/rloc_rc/rloc_rc.xise b/rloc_rc/rloc_rc.xise
new file mode 100755
index 0000000..caf5306
--- /dev/null
+++ b/rloc_rc/rloc_rc.xise
@@ -0,0 +1,385 @@
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diff --git a/rloc_rc/tb_ripple_counter.vhd b/rloc_rc/tb_ripple_counter.vhd
new file mode 100755
index 0000000..0c7b6df
--- /dev/null
+++ b/rloc_rc/tb_ripple_counter.vhd
@@ -0,0 +1,172 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:55:32 05/04/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_ripple_counter.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: ripple_counter
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ripple_counter IS
+END tb_ripple_counter;
+
+ARCHITECTURE behavior OF tb_ripple_counter IS
+
+constant N : integer := 8;
+constant MAX : integer := 130;
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT ripple_counter
+GENERIC(
+N : integer;
+MAX : integer
+);
+PORT(
+i_clock : IN std_logic;
+i_cpb : IN std_logic;
+i_mrb : IN std_logic;
+i_ud : IN std_logic;
+o_q : INOUT std_logic_vector(N-1 downto 0)
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_cpb : std_logic := '0';
+signal i_mrb : std_logic := '0';
+signal i_ud : std_logic := '0';
+
+--BiDirs
+signal o_q : std_logic_vector(N-1 downto 0);
+
+signal clock : std_logic := '0';
+constant clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: ripple_counter
+GENERIC MAP (
+N => N,
+MAX => MAX
+)
+PORT MAP (
+i_clock => clock,
+i_cpb => i_cpb,
+i_mrb => i_mrb,
+i_ud => i_ud,
+o_q => o_q
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+
+---- insert stimulus here
+
+-- reset, ok 0 when reset=1
+wait for clock_period;
+i_mrb <= '1';
+wait for 25*clock_period;
+i_mrb <= '0';
+
+-- wait some time, count down when ud=0
+wait for 100*clock_period;
+
+-- mrb,cpb must be 1 to reset and start count
+i_mrb <= '1';
+i_cpb <= '1';
+i_ud <= '1'; -- count up
+wait for 1*clock_period;
+i_mrb <= '0'; -- start counting
+wait for 4*MAX*clock_period; -- wait MAX ticks
+i_cpb <= '0'; -- ok, count from 0 to MAX-2, MAX-1=0 then ping
+i_ud <= '0';
+
+-- wait some time
+wait for 100*clock_period;
+
+-- dont want reset, reset in middle cpb
+wait for clock_period;
+i_cpb <= '1';
+i_ud <= '0'; -- count down
+wait for (MAX*clock_period)/2 - 241 ns;
+i_mrb <= '1';
+wait for clock_period;
+i_mrb <= '0';
+wait for (MAX*clock_period)/2 + 241 ns;
+wait for (MAX*clock_period)/2 - 123 ns;
+i_mrb <= '1';
+wait for clock_period;
+i_mrb <= '0';
+wait for (MAX*clock_period)/2 + 123 ns;
+wait for (MAX*clock_period)/2 - 177 ns;
+i_mrb <= '1';
+wait for clock_period;
+i_mrb <= '0';
+wait for (MAX*clock_period)/2 + 177 ns;
+wait for (MAX*clock_period)/2 - 89 ns;
+i_mrb <= '1';
+wait for clock_period;
+i_mrb <= '0';
+wait for (MAX*clock_period)/2 + 89 ns;
+i_cpb <= '0'; -- strange
+i_ud <= '0';
+
+-- wait some time, not count, stay on 1
+wait for 100*clock_period;
+
+-- mrb,cpb must be 1 to reset and start count
+wait for clock_period;
+i_mrb <= '1';
+i_cpb <= '1';
+i_ud <= '0'; -- count down
+wait for 1*clock_period; -- wait for reset
+i_mrb <= '0'; -- start counting
+wait for 4*MAX*clock_period;
+i_cpb <= '0'; -- strange
+i_ud <= '0';
+
+wait for 10*clock_period; -- XXX reset
+i_mrb <= '1';
+wait for 100*clock_period;
+i_mrb <= '0';
+
+wait;
+end process;
+
+END;
diff --git a/rs232_1/Nexys2_1200General.ucf b/rs232_1/Nexys2_1200General.ucf
new file mode 100755
index 0000000..7322e57
--- /dev/null
+++ b/rs232_1/Nexys2_1200General.ucf
@@ -0,0 +1,251 @@
+## This file is a general .ucf for Nexys2 rev A board
+## To use it in a project:
+## - remove or comment the lines corresponding to unused pins
+## - rename the used signals according to the project
+
+## Signals Led<7>Led<4> are assigned to pins which change type from s3e500 to other dies using the same package
+## Both versions are provided in this file.
+## Keep only the appropriate one, and remove or comment the other one.
+
+NET "i_clock" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
+## Clock pin for Nexys 2 Board
+#NET "clk" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
+#NET "clk1" LOC = "U9"; # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK, Sch name = GCLK1
+
+## onBoard USB controller
+## NOTE: DEPP and DSTM net names use some of the same pins, if trying to use both DEPP and DSTM use a signle net name for each shared pin.
+
+## Data bus for both the DEPP and DSTM interfaces uncomment lines 19-26 if using either one
+#NET "DB<0>" LOC = "R14"; # Bank = 2, Pin name = IO_L24N_2/A20, Type = DUAL, Sch name = U-FD0
+#NET "DB<1>" LOC = "R13"; # Bank = 2, Pin name = IO_L22N_2/A22, Type = DUAL, Sch name = U-FD1
+#NET "DB<2>" LOC = "P13"; # Bank = 2, Pin name = IO_L22P_2/A23, Type = DUAL, Sch name = U-FD2
+#NET "DB<3>" LOC = "T12"; # Bank = 2, Pin name = IO_L20P_2, Type = I/O, Sch name = U-FD3
+#NET "DB<4>" LOC = "N11"; # Bank = 2, Pin name = IO_L18N_2, Type = I/O, Sch name = U-FD4
+#NET "DB<5>" LOC = "R11"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = U-FD5
+#NET "DB<6>" LOC = "P10"; # Bank = 2, Pin name = IO_L15N_2/D1/GCLK3, Type = DUAL/GCLK, Sch name = U-FD6
+#NET "DB<7>" LOC = "R10"; # Bank = 2, Pin name = IO_L15P_2/D2/GCLK2, Type = DUAL/GCLK, Sch name = U-FD7
+
+## If using the DEPP interface uncomment lines 29-32
+#NET "EppWRITE" LOC = "V16"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-FLAGC
+#NET "EppASTB" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
+#NET "EppDSTB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
+#NET "EppWAIT" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
+
+## If using the DSTM interface uncomment lines 35-44
+#NET "DstmIFCLK" LOC = "T15"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = U-IFCLK
+#NET "DstmSLCS" LOC = "T16"; # Bank = 2, Pin name = IO_L26P_2/VS0/A17, Type = DUAL, Sch name = U-SLCS
+#NET "DstmFLAGA" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
+#NET "DstmFLAGB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
+#NET "DstmADR<0>" LOC = "T14"; # Bank = 2, Pin name = IO_L24P_2/A21, Type = DUAL, Sch name = U-FIFOAD0
+#NET "DstmADR<1>" LOC = "V13"; # Bank = 2, Pin name = IO_L19N_2/VREF_2, Type = VREF, Sch name = U-FIFOAD1
+#NET "DstmSLRD" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
+#NET "DstmSLWR" LOC = "V9"; # Bank = 2, Pin name = IO_L13N_2/D3/GCLK15, Type = DUAL/GCLK, Sch name = U-SLWR
+#NET "DstmSLOE" LOC = "V15"; # Bank = 2, Pin name = IO_L25P_2/VS2/A19, Type = DUAL, Sch name = U-SLOE
+#NET "DstmPKTEND" LOC = "V12"; # Bank = 2, Pin name = IO_L19P_2, Type = I/O, Sch name = U-PKTEND
+
+#NET "UsbMode" LOC = "U15"; # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type = DUAL, Sch name = U-INT0#
+#NET "UsbRdy" LOC = "U13"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-RDY
+
+## onBoard Cellular RAM and StrataFlash
+#NET "io_MemOE" LOC = "T2"; # Bank = 3, Pin name = IO_L24P_3, Type = I/O, Sch name = OE
+#NET "io_MemWR" LOC = "N7"; # Bank = 2, Pin name = IO_L07P_2, Type = I/O, Sch name = WE
+#
+#NET "io_RamAdv" LOC = "J4"; # Bank = 3, Pin name = IO_L11N_3/LHCLK1, Type = LHCLK, Sch name = MT-ADV
+#NET "io_RamCS" LOC = "R6"; # Bank = 2, Pin name = IO_L05P_2, Type = I/O, Sch name = MT-CE
+#NET "io_RamClk" LOC = "H5"; # Bank = 3, Pin name = IO_L08N_3, Type = I/O, Sch name = MT-CLK
+#NET "io_RamCRE" LOC = "P7"; # Bank = 2, Pin name = IO_L07N_2, Type = I/O, Sch name = MT-CRE
+#NET "io_RamLB" LOC = "K5"; # Bank = 3, Pin name = IO_L14N_3/LHCLK7, Type = LHCLK, Sch name = MT-LB
+#NET "io_RamUB" LOC = "K4"; # Bank = 3, Pin name = IO_L13N_3/LHCLK5, Type = LHCLK, Sch name = MT-UB
+#NET "RamWait" LOC = "F5"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = MT-WAIT
+
+#NET "FlashRp" LOC = "T5"; # Bank = 2, Pin name = IO_L04N_2, Type = I/O, Sch name = RP#
+#NET "io_FlashCS" LOC = "R5"; # Bank = 2, Pin name = IO_L04P_2, Type = I/O, Sch name = ST-CE
+#NET "FlashStSts" LOC = "D3"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = ST-STS
+
+#NET "io_MemAdr<1>" LOC = "J1"; # Bank = 3, Pin name = IO_L12P_3/LHCLK2, Type = LHCLK, Sch name = ADR1
+#NET "io_MemAdr<2>" LOC = "J2"; # Bank = 3, Pin name = IO_L12N_3/LHCLK3/IRDY2, Type = LHCLK, Sch name = ADR2
+#NET "io_MemAdr<3>" LOC = "H4"; # Bank = 3, Pin name = IO_L09P_3, Type = I/O, Sch name = ADR3
+#NET "io_MemAdr<4>" LOC = "H1"; # Bank = 3, Pin name = IO_L10N_3, Type = I/O, Sch name = ADR4
+#NET "io_MemAdr<5>" LOC = "H2"; # Bank = 3, Pin name = IO_L10P_3, Type = I/O, Sch name = ADR5
+#NET "io_MemAdr<6>" LOC = "J5"; # Bank = 3, Pin name = IO_L11P_3/LHCLK0, Type = LHCLK, Sch name = ADR6
+#NET "io_MemAdr<7>" LOC = "H3"; # Bank = 3, Pin name = IO_L09N_3, Type = I/O, Sch name = ADR7
+#NET "io_MemAdr<8>" LOC = "H6"; # Bank = 3, Pin name = IO_L08P_3, Type = I/O, Sch name = ADR8
+#NET "io_MemAdr<9>" LOC = "F1"; # Bank = 3, Pin name = IO_L05P_3, Type = I/O, Sch name = ADR9
+#NET "io_MemAdr<10>" LOC = "G3"; # Bank = 3, Pin name = IO_L06P_3, Type = I/O, Sch name = ADR10
+#NET "io_MemAdr<11>" LOC = "G6"; # Bank = 3, Pin name = IO_L07P_3, Type = I/O, Sch name = ADR11
+#NET "io_MemAdr<12>" LOC = "G5"; # Bank = 3, Pin name = IO_L07N_3, Type = I/O, Sch name = ADR12
+#NET "io_MemAdr<13>" LOC = "G4"; # Bank = 3, Pin name = IO_L06N_3/VREF_3, Type = VREF, Sch name = ADR13
+#NET "io_MemAdr<14>" LOC = "F2"; # Bank = 3, Pin name = IO_L05N_3, Type = I/O, Sch name = ADR14
+#NET "io_MemAdr<15>" LOC = "E1"; # Bank = 3, Pin name = IO_L03N_3, Type = I/O, Sch name = ADR15
+#NET "io_MemAdr<16>" LOC = "M5"; # Bank = 3, Pin name = IO_L19P_3, Type = I/O, Sch name = ADR16
+#NET "io_MemAdr<17>" LOC = "E2"; # Bank = 3, Pin name = IO_L03P_3, Type = I/O, Sch name = ADR17
+#NET "io_MemAdr<18>" LOC = "C2"; # Bank = 3, Pin name = IO_L01N_3, Type = I/O, Sch name = ADR18
+#NET "io_MemAdr<19>" LOC = "C1"; # Bank = 3, Pin name = IO_L01P_3, Type = I/O, Sch name = ADR19
+#NET "io_MemAdr<20>" LOC = "D2"; # Bank = 3, Pin name = IO_L02N_3/VREF_3, Type = VREF, Sch name = ADR20
+#NET "io_MemAdr<21>" LOC = "K3"; # Bank = 3, Pin name = IO_L13P_3/LHCLK4/TRDY2, Type = LHCLK, Sch name = ADR21
+#NET "io_MemAdr<22>" LOC = "D1"; # Bank = 3, Pin name = IO_L02P_3, Type = I/O, Sch name = ADR22
+#NET "io_MemAdr<23>" LOC = "K6"; # Bank = 3, Pin name = IO_L14P_3/LHCLK6, Type = LHCLK, Sch name = ADR23
+#
+#NET "io_MemDB<0>" LOC = "L1"; # Bank = 3, Pin name = IO_L15P_3, Type = I/O, Sch name = DB0
+#NET "io_MemDB<1>" LOC = "L4"; # Bank = 3, Pin name = IO_L16N_3, Type = I/O, Sch name = DB1
+#NET "io_MemDB<2>" LOC = "L6"; # Bank = 3, Pin name = IO_L17P_3, Type = I/O, Sch name = DB2
+#NET "io_MemDB<3>" LOC = "M4"; # Bank = 3, Pin name = IO_L18P_3, Type = I/O, Sch name = DB3
+#NET "io_MemDB<4>" LOC = "N5"; # Bank = 3, Pin name = IO_L20N_3, Type = I/O, Sch name = DB4
+#NET "io_MemDB<5>" LOC = "P1"; # Bank = 3, Pin name = IO_L21N_3, Type = I/O, Sch name = DB5
+#NET "io_MemDB<6>" LOC = "P2"; # Bank = 3, Pin name = IO_L21P_3, Type = I/O, Sch name = DB6
+#NET "io_MemDB<7>" LOC = "R2"; # Bank = 3, Pin name = IO_L23N_3, Type = I/O, Sch name = DB7
+#NET "io_MemDB<8>" LOC = "L3"; # Bank = 3, Pin name = IO_L16P_3, Type = I/O, Sch name = DB8
+#NET "io_MemDB<9>" LOC = "L5"; # Bank = 3, Pin name = IO_L17N_3/VREF_3, Type = VREF, Sch name = DB9
+#NET "io_MemDB<10>" LOC = "M3"; # Bank = 3, Pin name = IO_L18N_3, Type = I/O, Sch name = DB10
+#NET "io_MemDB<11>" LOC = "M6"; # Bank = 3, Pin name = IO_L19N_3, Type = I/O, Sch name = DB11
+#NET "io_MemDB<12>" LOC = "L2"; # Bank = 3, Pin name = IO_L15N_3, Type = I/O, Sch name = DB12
+#NET "io_MemDB<13>" LOC = "N4"; # Bank = 3, Pin name = IO_L20P_3, Type = I/O, Sch name = DB13
+#NET "io_MemDB<14>" LOC = "R3"; # Bank = 3, Pin name = IO_L23P_3, Type = I/O, Sch name = DB14
+#NET "io_MemDB<15>" LOC = "T1"; # Bank = 3, Pin name = IO_L24N_3, Type = I/O, Sch name = DB15
+
+## 7 segment display
+#NET "seg<0>" LOC = "L18"; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA
+#NET "seg<1>" LOC = "F18"; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB
+#NET "seg<2>" LOC = "D17"; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC
+#NET "seg<3>" LOC = "D16"; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD
+#NET "seg<4>" LOC = "G14"; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE
+#NET "seg<5>" LOC = "J17"; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
+#NET "seg<6>" LOC = "H14"; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG
+#NET "dp" LOC = "C17"; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP
+
+#NET "an<0>" LOC = "F17"; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0
+#NET "an<1>" LOC = "H17"; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1
+#NET "an<2>" LOC = "C18"; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2
+#NET "an<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3
+
+## Leds
+#NET "Led<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
+#NET "Led<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
+#NET "Led<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
+#NET "Led<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
+#NET "Led<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4? s3e500 only
+#NET "Led<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5? s3e500 only
+#NET "Led<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6? s3e500 only
+#NET "Led<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7? s3e500 only
+#NET "Led<4>" LOC = "E16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD4? other than s3e500
+#NET "Led<5>" LOC = "P16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD5? other than s3e500
+#NET "Led<6>" LOC = "E4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD6? other than s3e500
+#NET "Led<7>" LOC = "P4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD7? other than s3e500
+
+## Switches
+#NET "sw<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
+#NET "sw<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
+#NET "sw<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
+#NET "sw<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
+#NET "sw<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
+#NET "sw<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
+#NET "sw<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
+#NET "sw<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7
+
+NET "i_reset" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
+## Buttons
+#NET "btn<0>" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
+#NET "btn<1>" LOC = "D18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = BTN1
+#NET "btn<2>" LOC = "E18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN2
+#NET "btn<3>" LOC = "H13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN3
+
+## VGA Connector
+#NET "vgaRed<1>" LOC = "R9"; # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0
+#NET "vgaRed<2>" LOC = "T8"; # Bank = 2, Pin name = IO_L10N_2, Type = I/O, Sch name = RED1
+#NET "vgaRed<3>" LOC = "R8"; # Bank = 2, Pin name = IO_L10P_2, Type = I/O, Sch name = RED2
+#NET "vgaGreen<1>" LOC = "N8"; # Bank = 2, Pin name = IO_L09N_2, Type = I/O, Sch name = GRN0
+#NET "vgaGreen<2>" LOC = "P8"; # Bank = 2, Pin name = IO_L09P_2, Type = I/O, Sch name = GRN1
+#NET "vgaGreen<3>" LOC = "P6"; # Bank = 2, Pin name = IO_L05N_2, Type = I/O, Sch name = GRN2
+#NET "vgaBlue<2>" LOC = "U5"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = BLU1
+#NET "vgaBlue<3>" LOC = "U4"; # Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DUAL, Sch name = BLU2
+
+#NET "Hsync" LOC = "T4"; # Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type = DUAL, Sch name = HSYNC
+#NET "Vsync" LOC = "U3"; # Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUAL, Sch name = VSYNC
+
+## PS/2 connector
+#NET "PS2C" LOC = "R12"; # Bank = 2, Pin name = IO_L20N_2, Type = I/O, Sch name = PS2C
+#NET "PS2D" LOC = "P11"; # Bank = 2, Pin name = IO_L18P_2, Type = I/O, Sch name = PS2D
+
+## FX2 connector
+#NET "PIO<0>" LOC = "B4"; # Bank = 0, Pin name = IO_L24N_0, Type = I/O, Sch name = R-IO1
+#NET "PIO<1>" LOC = "A4"; # Bank = 0, Pin name = IO_L24P_0, Type = I/O, Sch name = R-IO2
+#NET "PIO<2>" LOC = "C3"; # Bank = 0, Pin name = IO_L25P_0, Type = I/O, Sch name = R-IO3
+#NET "PIO<3>" LOC = "C4"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO4
+#NET "PIO<4>" LOC = "B6"; # Bank = 0, Pin name = IO_L20P_0, Type = I/O, Sch name = R-IO5
+#NET "PIO<5>" LOC = "D5"; # Bank = 0, Pin name = IO_L23N_0/VREF_0, Type = VREF, Sch name = R-IO6
+#NET "PIO<6>" LOC = "C5"; # Bank = 0, Pin name = IO_L23P_0, Type = I/O, Sch name = R-IO7
+#NET "PIO<7>" LOC = "F7"; # Bank = 0, Pin name = IO_L19P_0, Type = I/O, Sch name = R-IO8
+#NET "PIO<8>" LOC = "E7"; # Bank = 0, Pin name = IO_L19N_0/VREF_0, Type = VREF, Sch name = R-IO9
+#NET "PIO<9>" LOC = "A6"; # Bank = 0, Pin name = IO_L20N_0, Type = I/O, Sch name = R-IO10
+#NET "PIO<10>" LOC = "C7"; # Bank = 0, Pin name = IO_L18P_0, Type = I/O, Sch name = R-IO11
+#NET "PIO<11>" LOC = "F8"; # Bank = 0, Pin name = IO_L17N_0, Type = I/O, Sch name = R-IO12
+#NET "PIO<12>" LOC = "D7"; # Bank = 0, Pin name = IO_L18N_0/VREF_0, Type = VREF, Sch name = R-IO13
+#NET "PIO<13>" LOC = "E8"; # Bank = 0, Pin name = IO_L17P_0, Type = I/O, Sch name = R-IO14
+#NET "PIO<14>" LOC = "E9"; # Bank = 0, Pin name = IO_L15P_0, Type = I/O, Sch name = R-IO15
+#NET "PIO<15>" LOC = "C9"; # Bank = 0, Pin name = IO_L14P_0/GCLK10, Type = GCLK, Sch name = R-IO16
+#NET "PIO<16>" LOC = "A8"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO17
+#NET "PIO<17>" LOC = "G9"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO18
+#NET "PIO<18>" LOC = "F9"; # Bank = 0, Pin name = IO_L15N_0, Type = I/O, Sch name = R-IO19
+#NET "PIO<19>" LOC = "D10"; # Bank = 0, Pin name = IO_L11P_0/GCLK4, Type = GCLK, Sch name = R-IO20
+#NET "PIO<20>" LOC = "A10"; # Bank = 0, Pin name = IO_L12N_0/GCLK7, Type = GCLK, Sch name = R-IO21
+#NET "PIO<21>" LOC = "B10"; # Bank = 0, Pin name = IO_L12P_0/GCLK6, Type = GCLK, Sch name = R-IO22
+#NET "PIO<22>" LOC = "A11"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO23
+#NET "PIO<23>" LOC = "D11"; # Bank = 0, Pin name = IO_L09N_0, Type = I/O, Sch name = R-IO24
+#NET "PIO<24>" LOC = "E10"; # Bank = 0, Pin name = IO_L11N_0/GCLK5, Type = GCLK, Sch name = R-IO25
+#NET "PIO<25>" LOC = "B11"; # Bank = 0, Pin name = IO/VREF_0, Type = VREF, Sch name = R-IO26
+#NET "PIO<26>" LOC = "C11"; # Bank = 0, Pin name = IO_L09P_0, Type = I/O, Sch name = R-IO27
+#NET "PIO<27>" LOC = "E11"; # Bank = 0, Pin name = IO_L08P_0, Type = I/O, Sch name = R-IO28
+#NET "PIO<28>" LOC = "F11"; # Bank = 0, Pin name = IO_L08N_0, Type = I/O, Sch name = R-IO29
+#NET "PIO<29>" LOC = "E12"; # Bank = 0, Pin name = IO_L06N_0, Type = I/O, Sch name = R-IO30
+#NET "PIO<30>" LOC = "F12"; # Bank = 0, Pin name = IO_L06P_0, Type = I/O, Sch name = R-IO31
+#NET "PIO<31>" LOC = "A13"; # Bank = 0, Pin name = IO_L05P_0, Type = I/O, Sch name = R-IO32
+#NET "PIO<32>" LOC = "B13"; # Bank = 0, Pin name = IO_L05N_0/VREF_0, Type = VREF, Sch name = R-IO33
+#NET "PIO<33>" LOC = "E13"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO34
+#NET "PIO<34>" LOC = "A14"; # Bank = 0, Pin name = IO_L04N_0, Type = I/O, Sch name = R-IO35
+#NET "PIO<35>" LOC = "C14"; # Bank = 0, Pin name = IO_L03N_0/VREF_0, Type = VREF, Sch name = R-IO36
+#NET "PIO<36>" LOC = "D14"; # Bank = 0, Pin name = IO_L03P_0, Type = I/O, Sch name = R-IO37
+#NET "PIO<37>" LOC = "B14"; # Bank = 0, Pin name = IO_L04P_0, Type = I/O, Sch name = R-IO38
+#NET "PIO<38>" LOC = "A16"; # Bank = 0, Pin name = IO_L01N_0, Type = I/O, Sch name = R-IO39
+#NET "PIO<39>" LOC = "B16"; # Bank = 0, Pin name = IO_L01P_0, Type = I/O, Sch name = R-IO40
+
+## 12 pin connectors
+
+##JA
+#NET "JA<0>" LOC = "L15"; # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1
+#NET "JA<1>" LOC = "K12"; # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2
+#NET "JA<2>" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
+#NET "JA<3>" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
+#NET "JA<4>" LOC = "K13"; # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL, Sch name = JA7
+#NET "JA<5>" LOC = "L16"; # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL, Sch name = JA8
+#NET "JA<6>" LOC = "M14"; # Bank = 1, Pin name = IO_L05P_1, Type = I/O, Sch name = JA9
+#NET "JA<7>" LOC = "M16"; # Bank = 1, Pin name = IO_L07N_1, Type = I/O, Sch name = JA10
+
+##JB
+#NET "JB<0>" LOC = "M13"; # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF, Sch name = JB1
+#NET "JB<1>" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
+#NET "JB<2>" LOC = "R15"; # Bank = 1, Pin name = IO_L03P_1, Type = I/O, Sch name = JB3
+#NET "JB<3>" LOC = "T17"; # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL, Sch name = JB4
+#NET "JB<4>" LOC = "P17"; # Bank = 1, Pin name = IO_L06P_1, Type = I/O, Sch name = JB7
+#NET "JB<5>" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
+#NET "JB<6>" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
+#NET "JB<7>" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
+
+##JC
+#NET "JC<0>" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
+#NET "JC<1>" LOC = "J16"; # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL, Sch name = JC2
+#NET "JC<2>" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
+#NET "JC<3>" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
+#NET "JC<4>" LOC = "H15"; # Bank = 1, Pin name = IO_L17N_1, Type = I/O, Sch name = JC7
+#NET "JC<5>" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
+#NET "JC<6>" LOC = "G16"; # Bank = 1, Pin name = IO_L18N_1, Type = I/O, Sch name = JC9
+#NET "JC<7>" LOC = "J12"; # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL, Sch name = JC10
+
+##JD - NOTE: For other JD pins see LD(3:0) above under "Leds"
+#NET "JD<0>" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
+#NET "JD<1>" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
+#NET "JD<2>" LOC = "N18"; # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3
+#NET "JD<3>" LOC = "P18"; # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4
+
+## RS232 connector
+NET "i_RsRX" LOC = "U6"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = RS-RX
+NET "o_RsTX" LOC = "P9"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = RS-TX
diff --git a/rs232_1/p_constants.vhd b/rs232_1/p_constants.vhd
new file mode 100755
index 0000000..16ef1fc
--- /dev/null
+++ b/rs232_1/p_constants.vhd
@@ -0,0 +1,20 @@
+--
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+--
+-- To use any of the example code shown below, uncomment the lines and modify as necessary
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package p_constants is
+ constant G_BOARD_CLOCK : integer := 50_000_000;
+ constant G_BAUD_RATE : integer := 300;
+-- constant G_BAUD_RATE : integer := 115200;
+end p_constants;
+
+package body p_constants is
+end p_constants;
diff --git a/rs232_1/rs232.vhd b/rs232_1/rs232.vhd
new file mode 100755
index 0000000..add9fb2
--- /dev/null
+++ b/rs232_1/rs232.vhd
@@ -0,0 +1,361 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:54:25 09/08/2020
+-- Design Name:
+-- Module Name: module_1 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity rs232 is
+Generic (
+ G_BOARD_CLOCK : integer := 50_000_000;
+ G_BAUD_RATE : integer := 9_600
+);
+Port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ enable_tx : in STD_LOGIC;
+ enable_rx : in STD_LOGIC;
+ byte_to_send : in STD_LOGIC_VECTOR (7 downto 0);
+ byte_received : out STD_LOGIC_VECTOR (7 downto 0);
+ parity_tx : out STD_LOGIC;
+ parity_tx_error : out STD_LOGIC;
+ parity_rx : out STD_LOGIC;
+ parity_rx_error : out STD_LOGIC;
+ busy : out STD_LOGIC;
+ ready : out STD_LOGIC;
+ is_byte_received : out STD_LOGIC;
+ start_rx : out STD_LOGIC;
+ RsTx : out STD_LOGIC;
+ RsRx : in STD_LOGIC
+);
+end rs232;
+
+architecture Behavioral of rs232 is
+
+ constant recv_bits : integer := 11; -- XXX 0/8bit/P/1
+ constant a : integer := (G_BOARD_CLOCK/G_BAUD_RATE);
+
+ signal v_i : std_logic_vector(31 downto 0);
+ signal v_w : std_logic_vector(31 downto 0);
+ signal t_w : std_logic_vector(31 downto 0);
+ signal temp : std_logic_vector(recv_bits - 1 downto 0);
+ signal p_tx,p_rx : std_logic;
+
+ type t_state is (
+ idle,
+ start,wstart,
+ b1,wb1,b2,wb2,b3,wb3,b4,wb4,b5,wb5,b6,wb6,b7,wb7,b8,wb8,
+ parity,wparity,
+ stop,wstop
+ );
+ signal tx_state : t_state;
+
+ type r_state is (
+ idle,
+ start,
+ get_first_bit,
+ get_first_bit_wait,
+ recv,
+ wait0,
+ increment,
+ parity,
+ wparity,
+ check_parity,
+ stop
+ );
+ signal rx_state : r_state;
+
+begin
+
+ p0 : process (clk,rst) is -- rx mode
+ begin
+ if (rst = '1') then
+ rx_state <= idle;
+ v_i <= (others => '0');
+ v_w <= (others => '0');
+ temp <= (others => '0');
+ elsif (rising_edge(clk)) then
+ case (rx_state) is
+ when idle =>
+ --byte_received <= (others => 'X');
+ start_rx <= '0';
+ if (enable_rx = '1') then
+ rx_state <= start;
+ v_i <= (others => '0');
+ v_w <= (others => '0');
+ is_byte_received <= '0';
+ elsif (enable_rx = '0') then
+ rx_state <= idle;
+ end if;
+ when start =>
+ if (RsRx = '1') then
+ rx_state <= start;
+ v_w <= (others => '0');
+ elsif (RsRx = '0') then
+ if (to_integer(unsigned(v_w)) = a-1) then
+ rx_state <= get_first_bit;
+ start_rx <= '1';
+ else
+ rx_state <= start;
+ v_w <= std_logic_vector(to_unsigned(to_integer(unsigned(v_w)) + 1,32));
+ end if;
+ end if;
+ when get_first_bit =>
+ start_rx <= '0';
+ rx_state <= get_first_bit_wait;
+ v_i <= x"00000001"; -- we receive first bit
+ temp(0) <= RsRx;
+ v_w <= (others => '0');
+ --temp(0) <= '0';
+ when get_first_bit_wait =>
+ rx_state <= recv;
+ if (to_integer(unsigned(v_w)) = a-1) then
+ rx_state <= recv;
+ v_w <= (others => '0');
+ else
+ rx_state <= get_first_bit_wait;
+ v_w <= std_logic_vector(to_unsigned(to_integer(unsigned(v_w)) + 1,32));
+ end if;
+ when recv =>
+ rx_state <= wait0;
+ temp(to_integer(unsigned(v_i))) <= RsRx;
+ when wait0 =>
+ if (to_integer(unsigned(v_w)) = a-1) then
+ rx_state <= increment;
+ v_w <= (others => '0');
+ else
+ rx_state <= wait0;
+ v_w <= std_logic_vector(to_unsigned(to_integer(unsigned(v_w)) + 1,32));
+ end if;
+ when increment =>
+ if (to_integer(unsigned(v_i)) = recv_bits-4) then
+ rx_state <= parity;
+ v_i <= (others => '0');
+ else
+ rx_state <= recv;
+ v_i <= std_logic_vector(to_unsigned(to_integer(unsigned(v_i)) + 1,32));
+ end if;
+ when parity =>
+ rx_state <= wparity;
+ --p_rx <= temp(1) xor temp(2) xor temp(3) xor temp(4) xor temp(5) xor temp(6) xor temp(7) xor temp(8); -- XXX 2x/E=0,2x+1/O=1
+ p_rx <= temp(0) xor temp(1) xor temp(2) xor temp(3) xor temp(4) xor temp(5) xor temp(6) xor temp(7); -- XXX 2x/E=0,2x+1/O=1
+ when wparity =>
+ if (to_integer(unsigned(v_w)) = a-1) then
+ rx_state <= check_parity;
+ v_w <= (others => '0');
+ else
+ rx_state <= wparity;
+ v_w <= std_logic_vector(to_unsigned(to_integer(unsigned(v_w)) + 1,32));
+ end if;
+ when check_parity =>
+ rx_state <= stop;
+ if (p_rx = '1') then -- XXX 2x/E=0,2x+1/O=1
+ parity_rx_error <= '1';
+ else
+ parity_rx_error <= '0';
+ end if;
+ when stop =>
+ rx_state <= idle;
+ is_byte_received <= '1';
+ byte_received <= temp(recv_bits-4 downto 0);
+ parity_rx <= p_rx; -- recv_bits-1
+ end case;
+ end if;
+ end process p0;
+
+ p1 : process (clk,rst) is -- tx mode
+ begin
+ if (rst = '1') then
+ tx_state <= idle;
+ busy <= '0';
+ ready <= '1';
+ RsTx <= '0';
+ t_w <= (others => '0');
+ elsif (rising_edge(clk)) then
+ case tx_state is
+ when idle =>
+ RsTx <= '1';
+ if (enable_tx = '1') then
+ tx_state <= start;
+ busy <= '1';
+ ready <= '0';
+ else
+ tx_state <= idle;
+ busy <= '0';
+ ready <= '1';
+ end if;
+ when start =>
+ tx_state <= wstart;
+ RsTx <= '0';
+ when wstart =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= b1;
+ t_w <= (others => '0');
+ else
+ tx_state <= wstart;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b1 =>
+ tx_state <= wb1;
+-- RsTx <= byte_to_send(1);
+ RsTx <= byte_to_send(0);
+-- RsTx <= byte_to_send(7);
+ when wb1 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= b2;
+ t_w <= (others => '0');
+ else
+ tx_state <= wb1;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b2 =>
+ tx_state <= wb2;
+-- RsTx <= byte_to_send(2);
+ RsTx <= byte_to_send(1);
+-- RsTx <= byte_to_send(6);
+ when wb2 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= b3;
+ t_w <= (others => '0');
+ else
+ tx_state <= wb2;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b3 =>
+ tx_state <= wb3;
+-- RsTx <= byte_to_send(3);
+ RsTx <= byte_to_send(2);
+-- RsTx <= byte_to_send(5);
+ when wb3 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= b4;
+ t_w <= (others => '0');
+ else
+ tx_state <= wb3;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b4 =>
+ tx_state <= wb4;
+-- RsTx <= byte_to_send(4);
+ RsTx <= byte_to_send(3);
+-- RsTx <= byte_to_send(4);
+ when wb4 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= b5;
+ t_w <= (others => '0');
+ else
+ tx_state <= wb4;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b5 =>
+ tx_state <= wb5;
+-- RsTx <= byte_to_send(5);
+ RsTx <= byte_to_send(4);
+-- RsTx <= byte_to_send(3);
+ when wb5 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= b6;
+ t_w <= (others => '0');
+ else
+ tx_state <= wb5;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b6 =>
+ tx_state <= wb6;
+-- RsTx <= byte_to_send(6);
+ RsTx <= byte_to_send(5);
+-- RsTx <= byte_to_send(2);
+ when wb6 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= b7;
+ t_w <= (others => '0');
+ else
+ tx_state <= wb6;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b7 =>
+ tx_state <= wb7;
+-- RsTx <= byte_to_send(7);
+ RsTx <= byte_to_send(6);
+-- RsTx <= byte_to_send(1);
+ when wb7 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= b8;
+ t_w <= (others => '0');
+ else
+ tx_state <= wb7;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b8 =>
+ tx_state <= wb8;
+-- RsTx <= byte_to_send(8);
+ RsTx <= byte_to_send(7);
+-- RsTx <= byte_to_send(0);
+ when wb8 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= parity;
+ t_w <= (others => '0');
+ else
+ tx_state <= wb8;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when parity =>
+ tx_state <= wparity;
+-- p_tx <= not (byte_to_send(0) xor byte_to_send(1) xor byte_to_send(2) xor byte_to_send(3) xor byte_to_send(4) xor byte_to_send(5) xor byte_to_send(6) xor byte_to_send(7));
+ p_tx <= byte_to_send(0) xor byte_to_send(1) xor byte_to_send(2) xor byte_to_send(3) xor byte_to_send(4) xor byte_to_send(5) xor byte_to_send(6) xor byte_to_send(7);
+ --p_tx <= byte_to_send(1) xor byte_to_send(2) xor byte_to_send(3) xor byte_to_send(4) xor byte_to_send(5) xor byte_to_send(6) xor byte_to_send(7) xor byte_to_send(8);
+ when wparity =>
+ RsTx <= p_tx;
+ --RsTx <= '0';
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= stop;
+ t_w <= (others => '0');
+ else
+ tx_state <= wparity;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when stop =>
+ tx_state <= wstop;
+ RsTx <= '1';
+ --RsTx <= p_tx;
+ busy <= '0';
+ ready <= '1';
+ when wstop =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= idle;
+ parity_tx <= p_tx;
+ t_w <= (others => '0');
+ else
+ tx_state <= wstop;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when others => null;
+ end case;
+ end if;
+ end process p1;
+
+end Behavioral;
diff --git a/rs232_1/rs232_1.vhd b/rs232_1/rs232_1.vhd
new file mode 100755
index 0000000..73196f0
--- /dev/null
+++ b/rs232_1/rs232_1.vhd
@@ -0,0 +1,111 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:54:25 09/08/2020
+-- Design Name:
+-- Module Name: module_1 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity rs232_1 is
+Port(
+ clk : in STD_LOGIC_VECTOR (0 downto 0);
+ rst : in STD_LOGIC_VECTOR (0 downto 0);
+ RsTx : out STD_LOGIC_VECTOR (0 downto 0);
+ RsRx : in STD_LOGIC_VECTOR (0 downto 0)
+);
+end rs232_1;
+
+architecture Behavioral of rs232_1 is
+ constant CLK_BOARD : integer := 50_000_000;
+ constant BAUD_RATE : integer := 9_600;
+
+ signal clk_div1 : std_logic_vector (0 downto 0);
+
+ constant NUMBER_BITS : integer := 8;
+ signal send_byte_index : std_logic_vector(NUMBER_BITS-1 downto 0) := x"00";
+
+-- signal byte_to_send : std_logic_vector (NUMBER_BITS-1 downto 0) := "01000001";
+ signal byte_to_send : std_logic_vector (NUMBER_BITS-1 downto 0) := "10101010";
+-- signal byte_to_send : std_logic_vector (NUMBER_BITS-1 downto 0) := "01010101";
+-- signal byte_to_send : std_logic_vector (NUMBER_BITS-1 downto 0) := "11111111";
+-- signal byte_to_send : std_logic_vector (NUMBER_BITS-1 downto 0) := "00000000";
+
+ type state is (start,increment_index,send_byte,send_byte_last,stop);
+ signal c_state,n_state : state := start;
+begin
+
+ p_dv : process (clk(0),c_state,rst) is
+ variable COUNTER_BAUD_RATE_MAX : integer := (CLK_BOARD/BAUD_RATE);
+ variable counter_baud_rate : integer := 0;
+ begin
+ if (rst(0) = '1') then
+ send_byte_index <= x"00";
+ elsif (rising_edge(clk(0))) then
+ if (counter_baud_rate < COUNTER_BAUD_RATE_MAX-1) then
+ clk_div1 <= std_logic_vector(to_unsigned(0,1));
+ counter_baud_rate := counter_baud_rate + 1;
+ else
+ clk_div1 <= std_logic_vector(to_unsigned(1,1));
+ counter_baud_rate := 0;
+ if (c_state = send_byte) then
+ if (to_integer(unsigned(send_byte_index)) < NUMBER_BITS-1) then
+ send_byte_index <= std_logic_vector(unsigned(send_byte_index)+1);
+ else
+ send_byte_index <= x"00";
+ end if;
+ end if;
+ end if;
+ end if;
+ end process p_dv;
+
+ p0 : process (clk_div1(0),c_state) is
+ begin
+ if (rising_edge(clk_div1(0))) then
+ c_state <= n_state;
+ end if;
+ case c_state is
+ when start =>
+ RsTx <= std_logic_vector(to_unsigned(0,1));
+ n_state <= send_byte;
+ when send_byte =>
+ if (to_integer(unsigned(send_byte_index)) < NUMBER_BITS-1) then
+ n_state <= send_byte;
+ else
+ n_state <= stop;
+ end if;
+ if (byte_to_send(to_integer(NUMBER_BITS-1-unsigned(send_byte_index))) = '0') then
+ RsTx <= std_logic_vector(to_unsigned(0,1));
+ elsif (byte_to_send(to_integer(NUMBER_BITS-1-unsigned(send_byte_index))) = '1') then
+ RsTx <= std_logic_vector(to_unsigned(1,1));
+ end if;
+ when stop =>
+ RsTx <= std_logic_vector(to_unsigned(1,1));
+ n_state <= start;
+ when others => null;
+ end case;
+ end process p0;
+
+end Behavioral;
diff --git a/rs232_1/rs232_1.xise b/rs232_1/rs232_1.xise
new file mode 100755
index 0000000..7bbba11
--- /dev/null
+++ b/rs232_1/rs232_1.xise
@@ -0,0 +1,361 @@
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diff --git a/rs232_1/rs232_squarewave_U.vhd b/rs232_1/rs232_squarewave_U.vhd
new file mode 100755
index 0000000..73196f0
--- /dev/null
+++ b/rs232_1/rs232_squarewave_U.vhd
@@ -0,0 +1,111 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:54:25 09/08/2020
+-- Design Name:
+-- Module Name: module_1 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity rs232_1 is
+Port(
+ clk : in STD_LOGIC_VECTOR (0 downto 0);
+ rst : in STD_LOGIC_VECTOR (0 downto 0);
+ RsTx : out STD_LOGIC_VECTOR (0 downto 0);
+ RsRx : in STD_LOGIC_VECTOR (0 downto 0)
+);
+end rs232_1;
+
+architecture Behavioral of rs232_1 is
+ constant CLK_BOARD : integer := 50_000_000;
+ constant BAUD_RATE : integer := 9_600;
+
+ signal clk_div1 : std_logic_vector (0 downto 0);
+
+ constant NUMBER_BITS : integer := 8;
+ signal send_byte_index : std_logic_vector(NUMBER_BITS-1 downto 0) := x"00";
+
+-- signal byte_to_send : std_logic_vector (NUMBER_BITS-1 downto 0) := "01000001";
+ signal byte_to_send : std_logic_vector (NUMBER_BITS-1 downto 0) := "10101010";
+-- signal byte_to_send : std_logic_vector (NUMBER_BITS-1 downto 0) := "01010101";
+-- signal byte_to_send : std_logic_vector (NUMBER_BITS-1 downto 0) := "11111111";
+-- signal byte_to_send : std_logic_vector (NUMBER_BITS-1 downto 0) := "00000000";
+
+ type state is (start,increment_index,send_byte,send_byte_last,stop);
+ signal c_state,n_state : state := start;
+begin
+
+ p_dv : process (clk(0),c_state,rst) is
+ variable COUNTER_BAUD_RATE_MAX : integer := (CLK_BOARD/BAUD_RATE);
+ variable counter_baud_rate : integer := 0;
+ begin
+ if (rst(0) = '1') then
+ send_byte_index <= x"00";
+ elsif (rising_edge(clk(0))) then
+ if (counter_baud_rate < COUNTER_BAUD_RATE_MAX-1) then
+ clk_div1 <= std_logic_vector(to_unsigned(0,1));
+ counter_baud_rate := counter_baud_rate + 1;
+ else
+ clk_div1 <= std_logic_vector(to_unsigned(1,1));
+ counter_baud_rate := 0;
+ if (c_state = send_byte) then
+ if (to_integer(unsigned(send_byte_index)) < NUMBER_BITS-1) then
+ send_byte_index <= std_logic_vector(unsigned(send_byte_index)+1);
+ else
+ send_byte_index <= x"00";
+ end if;
+ end if;
+ end if;
+ end if;
+ end process p_dv;
+
+ p0 : process (clk_div1(0),c_state) is
+ begin
+ if (rising_edge(clk_div1(0))) then
+ c_state <= n_state;
+ end if;
+ case c_state is
+ when start =>
+ RsTx <= std_logic_vector(to_unsigned(0,1));
+ n_state <= send_byte;
+ when send_byte =>
+ if (to_integer(unsigned(send_byte_index)) < NUMBER_BITS-1) then
+ n_state <= send_byte;
+ else
+ n_state <= stop;
+ end if;
+ if (byte_to_send(to_integer(NUMBER_BITS-1-unsigned(send_byte_index))) = '0') then
+ RsTx <= std_logic_vector(to_unsigned(0,1));
+ elsif (byte_to_send(to_integer(NUMBER_BITS-1-unsigned(send_byte_index))) = '1') then
+ RsTx <= std_logic_vector(to_unsigned(1,1));
+ end if;
+ when stop =>
+ RsTx <= std_logic_vector(to_unsigned(1,1));
+ n_state <= start;
+ when others => null;
+ end case;
+ end process p0;
+
+end Behavioral;
diff --git a/rs232_1/tb_rs232_1.vhd b/rs232_1/tb_rs232_1.vhd
new file mode 100755
index 0000000..072671d
--- /dev/null
+++ b/rs232_1/tb_rs232_1.vhd
@@ -0,0 +1,198 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:24:06 04/21/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/rs232_1/tb_rs232_1.vhd
+-- Project Name: rs232_1
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: rs232
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_rs232_1 IS
+END tb_rs232_1;
+
+ARCHITECTURE behavior OF tb_rs232_1 IS
+
+constant G_BOARD_CLOCK : integer := 1_000_000;
+constant G_BAUD_RATE : integer := 300;
+-- Clock period definitions
+constant clk_period : time := (1_000_000_000/G_BOARD_CLOCK) * 1 ns;
+constant one_uart_bit : time := (G_BOARD_CLOCK/G_BAUD_RATE) * clk_period;
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT rs232
+GENERIC(
+G_BOARD_CLOCK : integer := G_BOARD_CLOCK;
+G_BAUD_RATE : integer := G_BAUD_RATE
+);
+PORT(
+clk : IN std_logic;
+rst : IN std_logic;
+enable_tx : IN std_logic;
+enable_rx : IN std_logic;
+byte_to_send : IN std_logic_vector(7 downto 0);
+byte_received : OUT std_logic_vector(7 downto 0);
+parity_tx : OUT std_logic;
+parity_tx_error : OUT std_logic;
+parity_rx : OUT std_logic;
+parity_rx_error : OUT std_logic;
+busy : OUT std_logic;
+ready : OUT std_logic;
+is_byte_received : OUT std_logic;
+RsTx : OUT std_logic;
+RsRx : IN std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal clk : std_logic := '0';
+signal rst : std_logic := '0';
+signal enable_tx : std_logic := '0';
+signal enable_rx : std_logic := '0';
+signal byte_to_send : std_logic_vector(7 downto 0) := (others => '0');
+signal RsRx : std_logic := '0';
+
+--Outputs
+signal byte_received : std_logic_vector(7 downto 0);
+signal parity_tx : std_logic;
+signal parity_tx_error : std_logic;
+signal parity_rx : std_logic;
+signal parity_rx_error : std_logic;
+signal busy : std_logic;
+signal ready : std_logic;
+signal is_byte_received : std_logic;
+signal RsTx : std_logic;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: rs232 PORT MAP (
+clk => clk,
+rst => rst,
+enable_tx => enable_tx,
+enable_rx => enable_rx,
+byte_to_send => byte_to_send,
+byte_received => byte_received,
+parity_tx => parity_tx,
+parity_tx_error => parity_tx_error,
+parity_rx => parity_rx,
+parity_rx_error => parity_rx_error,
+busy => busy,
+ready => ready,
+is_byte_received => is_byte_received,
+RsTx => RsTx,
+RsRx => RsRx
+);
+
+-- Clock process definitions
+clk_process :process
+begin
+clk <= '0';
+wait for clk_period/2;
+clk <= '1';
+wait for clk_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+type test_array is array(0 to 10) of std_logic_vector(7 downto 0);
+variable test : test_array := (x"AA",x"55",x"FF",x"00",x"41",x"42",x"43",x"44",x"45",x"46",x"47");
+variable test_ff : std_logic_vector(7 downto 0) := X"FF";
+begin
+rst <= '1';
+wait for clk_period;
+rst <= '0';
+wait for clk_period;
+
+enable_tx <= '1';
+byte_to_send <= x"DD";
+wait for clk_period;
+enable_tx <= '0';
+wait until busy = '0';
+
+
+byte_to_send <= (others => 'X');
+
+-- receive raw bits
+enable_rx <= '1';
+l0 : for i in 0 to 10 loop
+RsRx <= '0';
+wait for one_uart_bit;
+l1 : for j in 0 to 7 loop
+RsRx <= test(i)(j);
+wait for one_uart_bit;
+end loop l1;
+--RsRX <= test(i)(0) xor test(i)(1) xor test(i)(2) xor test(i)(3) xor test(i)(4) xor test(i)(5) xor test(i)(6) xor test(i)(7); -- XXX Even
+RsRX <= not (test(i)(0) xor test(i)(1) xor test(i)(2) xor test(i)(3) xor test(i)(4) xor test(i)(5) xor test(i)(6) xor test(i)(7)); -- XXX Odd
+wait for one_uart_bit;
+RsRx <= '1';
+wait for one_uart_bit;
+end loop l0;
+enable_rx <= '0';
+
+-- send bytes
+enable_tx <= '1';
+l10 : for i in 0 to 10 loop
+byte_to_send <= test(i);
+wait until busy = '0';
+end loop l10;
+enable_tx <= '0';
+
+byte_to_send <= (others => 'X');
+
+-- receive FF's
+enable_rx <= '1';
+l00 : for i in 0 to 20 loop
+RsRx <= '0';
+wait for one_uart_bit;
+l20 : for j in 0 to 7 loop
+RsRx <= test_ff(j);
+wait for one_uart_bit;
+end loop l20;
+--RsRX <= test_ff(0) xor test_ff(1) xor test_ff(2) xor test_ff(3) xor test_ff(4) xor test_ff(5) xor test_ff(6) xor test_ff(7); -- XXX Even
+RsRX <= not (test_ff(0) xor test_ff(1) xor test_ff(2) xor test_ff(3) xor test_ff(4) xor test_ff(5) xor test_ff(6) xor test_ff(7)); -- XXX Odd
+wait for one_uart_bit;
+RsRx <= '1';
+wait for one_uart_bit;
+end loop l00;
+enable_rx <= '0';
+
+-- send ff's
+enable_tx <= '1';
+l1000 : for i in 0 to 20 loop
+byte_to_send <= x"FF";
+wait for clk_period;
+wait until busy = '1';
+end loop l1000;
+enable_tx <= '0';
+
+byte_to_send <= (others => 'X');
+
+wait;
+end process;
+
+END;
diff --git a/rs232_1/tb_rs232_1.wcfg b/rs232_1/tb_rs232_1.wcfg
new file mode 100755
index 0000000..97145b2
--- /dev/null
+++ b/rs232_1/tb_rs232_1.wcfg
@@ -0,0 +1,209 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ tb
+ label
+
+ clk
+ clk
+
+
+ rst
+ rst
+
+
+ enable_tx
+ enable_tx
+
+
+ byte_to_send[7:0]
+ byte_to_send[7:0]
+ HEXRADIX
+
+
+ rstx
+ rstx
+
+
+ enable_rx
+ enable_rx
+
+
+ byte_received[7:0]
+ byte_received[7:0]
+ HEXRADIX
+
+
+ rsrx
+ rsrx
+
+
+ parity_tx
+ parity_tx
+
+
+ parity_tx_error
+ parity_tx_error
+
+
+ parity_rx
+ parity_rx
+
+
+ parity_rx_error
+ parity_rx_error
+
+
+ busy
+ busy
+
+
+ ready
+ ready
+
+
+ is_byte_received
+ is_byte_received
+
+
+ g_board_clock
+ g_board_clock
+
+
+ g_baud_rate
+ g_baud_rate
+
+
+ clk_period
+ clk_period
+
+
+ one_uart_bit
+ one_uart_bit
+
+
+
+ uut
+ label
+
+ clk
+ clk
+
+
+ rst
+ rst
+
+
+ enable_tx
+ enable_tx
+
+
+ enable_rx
+ enable_rx
+
+
+ byte_to_send[7:0]
+ byte_to_send[7:0]
+
+
+ byte_received[7:0]
+ byte_received[7:0]
+
+
+ parity_tx
+ parity_tx
+
+
+ parity_tx_error
+ parity_tx_error
+
+
+ parity_rx
+ parity_rx
+
+
+ parity_rx_error
+ parity_rx_error
+
+
+ busy
+ busy
+
+
+ ready
+ ready
+
+
+ is_byte_received
+ is_byte_received
+
+
+ rstx
+ rstx
+
+
+ rsrx
+ rsrx
+
+
+ v_i[31:0]
+ v_i[31:0]
+
+
+ v_w[31:0]
+ v_w[31:0]
+
+
+ t_w[31:0]
+ t_w[31:0]
+
+
+ temp[10:0]
+ temp[10:0]
+
+
+ p_tx
+ p_tx
+
+
+ p_rx
+ p_rx
+
+
+ tx_state
+ tx_state
+
+
+ rx_state
+ rx_state
+
+
+ g_board_clock
+ g_board_clock
+
+
+ g_baud_rate
+ g_baud_rate
+
+
+ recv_bits
+ recv_bits
+
+
+ a
+ a
+
+
+
diff --git a/rs232_1/tb_top.vhd b/rs232_1/tb_top.vhd
new file mode 100755
index 0000000..fd7e79b
--- /dev/null
+++ b/rs232_1/tb_top.vhd
@@ -0,0 +1,151 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:48:53 03/19/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/rs232_1/tb_top.vhd
+-- Project Name: rs232_1
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE WORK.p_constants.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_top IS
+END tb_top;
+
+ARCHITECTURE behavior OF tb_top IS
+
+ constant G_BOARD_CLOCK : integer := 1_000_000;
+
+ -- Clock period definitions
+ constant i_clock_period : time := (1_000_000_000/G_BOARD_CLOCK) * 1 ns;
+ constant one_uart_bit : time := (G_BOARD_CLOCK/G_BAUD_RATE) * i_clock_period;
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT top
+ GENERIC(
+ G_BOARD_CLOCK : integer := G_BOARD_CLOCK;
+ G_BAUD_RATE : integer := G_BAUD_RATE
+ );
+ PORT(
+ i_clock : IN std_logic;
+ i_reset : IN std_logic;
+ o_RsTX : OUT std_logic;
+ i_RsRX : IN std_logic
+ );
+ END COMPONENT;
+
+ --Inputs
+ signal i_clock : std_logic := '0';
+ signal i_reset : std_logic := '0';
+ signal i_RsRX : std_logic := '1';
+
+ --Outputs
+ signal o_RsTX : std_logic;
+
+ --Clock
+ signal rs_clock : std_logic := '0';
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: top
+ GENERIC MAP (
+ G_BOARD_CLOCK => G_BOARD_CLOCK,
+ G_BAUD_RATE => G_BAUD_RATE
+ )
+ PORT MAP (
+ i_clock => i_clock,
+ i_reset => i_reset,
+ o_RsTX => o_RsTX,
+ i_RsRX => i_RsRX
+ );
+
+ -- Clock process definitions
+ i_clock_process :process
+ begin
+ i_clock <= '0';
+ wait for i_clock_period/2;
+ i_clock <= '1';
+ wait for i_clock_period/2;
+ end process;
+
+ rs_clock_process :process
+ begin
+ rs_clock <= '0';
+ wait for one_uart_bit/2;
+ rs_clock <= '1';
+ wait for one_uart_bit/2;
+ end process;
+
+ -- Stimulus process
+ stim_proc: process
+ type test_array is array(0 to 9+2) of std_logic_vector(7 downto 0);
+-- type test_array is array(0 to 10) of std_logic_vector(7 downto 0);
+ variable test : test_array := (x"31",x"32",x"33",x"34",x"35",x"36",x"37",x"38",x"39",x"30",x"00",x"FF");
+-- variable test : test_array := (x"AA",x"55",x"FF",x"00",x"41",x"42",x"43",x"44",x"45",x"46",x"47");
+ --variable test : test_array := (x"6F",x"70",x"4F",x"50",x"6F",x"70",x"4F",x"50",x"00",x"FF",x"00");
+ begin
+ i_reset <= '1';
+ wait for i_clock_period;
+ i_reset <= '0';
+ wait for 40 ms; -- must wait for user key
+ -- insert stimulus here
+
+ l0 : for i in 0 to 9 loop -- data for cp1202
+ i_RsRX <= '0';
+ wait for one_uart_bit;
+ l1 : for j in 0 to 7 loop
+ i_RsRX <= test(i)(j);
+ wait for one_uart_bit;
+ end loop l1;
+ i_RsRX <= test(i)(0) xor test(i)(1) xor test(i)(2) xor test(i)(3) xor test(i)(4) xor test(i)(5) xor test(i)(6) xor test(i)(7); -- XXX Even
+ --i_RsRX <= not (test(i)(0) xor test(i)(1) xor test(i)(2) xor test(i)(3) xor test(i)(4) xor test(i)(5) xor test(i)(6) xor test(i)(7)); -- XXX Odd
+ wait for one_uart_bit;
+ i_RsRX <= '1';
+ wait for one_uart_bit;
+ wait for 50 ms;
+ end loop l0;
+
+ l3 : for i in 9 to 11 loop -- data for cp1202 FF and 00
+ i_RsRX <= '0';
+ wait for one_uart_bit;
+ l4 : for j in 0 to 7 loop
+ i_RsRX <= test(i)(j);
+ wait for one_uart_bit;
+ end loop l4;
+ --i_RsRX <= test(i)(0) xor test(i)(1) xor test(i)(2) xor test(i)(3) xor test(i)(4) xor test(i)(5) xor test(i)(6) xor test(i)(7); -- XXX Even
+ i_RsRX <= not (test(i)(0) xor test(i)(1) xor test(i)(2) xor test(i)(3) xor test(i)(4) xor test(i)(5) xor test(i)(6) xor test(i)(7)); -- XXX Odd
+ wait for one_uart_bit;
+ i_RsRX <= '1';
+ wait for one_uart_bit;
+ wait for 100 ms;
+ end loop l3;
+
+ wait;
+ end process;
+
+END;
diff --git a/rs232_1/tb_top.wcfg b/rs232_1/tb_top.wcfg
new file mode 100755
index 0000000..ee75181
--- /dev/null
+++ b/rs232_1/tb_top.wcfg
@@ -0,0 +1,254 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ rsrx
+ rsrx
+
+
+ rstx
+ rstx
+
+
+ rs_clock
+ rs_clock
+
+
+ rx_state
+ rx_state
+
+
+ byte_received[7:0]
+ byte_received[7:0]
+ HEXRADIX
+
+
+ tx_state
+ tx_state
+
+
+ byte_to_send[7:0]
+ byte_to_send[7:0]
+ HEXRADIX
+
+
+ tb
+ label
+
+ i_clock
+ i_clock
+
+
+ i_reset
+ i_reset
+
+
+ i_rsrx
+ i_rsrx
+
+
+ o_rstx
+ o_rstx
+
+
+ i_clock_period
+ i_clock_period
+
+
+ one_uart_bit
+ one_uart_bit
+
+
+
+ uut
+ label
+
+ i_clock
+ i_clock
+
+
+ i_reset
+ i_reset
+
+
+ i_rsrx
+ i_rsrx
+
+
+ o_rstx
+ o_rstx
+
+
+ enable_tx
+ enable_tx
+
+
+ enable_rx
+ enable_rx
+
+
+ busy
+ busy
+
+
+ ready
+ ready
+
+
+ is_byte_received
+ is_byte_received
+
+
+ parity_tx
+ parity_tx
+
+
+ parity_rx
+ parity_rx
+
+
+ byte_to_send[7:0]
+ byte_to_send[7:0]
+ HEXRADIX
+
+
+ byte_received[7:0]
+ byte_received[7:0]
+ HEXRADIX
+
+
+ byte_to_send[7:0]
+ byte_to_send[7:0]
+
+
+ byte_received[7:0]
+ byte_received[7:0]
+
+
+ state
+ state
+
+
+ g_board_clock
+ g_board_clock
+
+
+ g_baud_rate
+ g_baud_rate
+
+
+
+ rs232
+ label
+
+ clk
+ clk
+
+
+ rst
+ rst
+
+
+ enable_rx
+ enable_rx
+
+
+ byte_received[7:0]
+ byte_received[7:0]
+ HEXRADIX
+
+
+ enable_tx
+ enable_tx
+
+
+ byte_to_send[7:0]
+ byte_to_send[7:0]
+ HEXRADIX
+
+
+ busy
+ busy
+
+
+ ready
+ ready
+
+
+ start_rx
+ start_rx
+
+
+ rsrx
+ rsrx
+
+
+ is_byte_received
+ is_byte_received
+
+
+ rstx
+ rstx
+
+
+ tx_state
+ tx_state
+
+
+ rx_state
+ rx_state
+
+
+ v_i[31:0]
+ v_i[31:0]
+
+
+ v_w[31:0]
+ v_w[31:0]
+
+
+ t_w[31:0]
+ t_w[31:0]
+
+
+ temp[10:0]
+ temp[10:0]
+
+
+ p_tx
+ p_tx
+
+
+ p_rx
+ p_rx
+
+
+ parity_tx
+ parity_tx
+
+
+ parity_tx_error
+ parity_tx_error
+
+
+ parity_rx
+ parity_rx
+
+
+ parity_rx_error
+ parity_rx_error
+
+
+
diff --git a/rs232_1/top.vhd b/rs232_1/top.vhd
new file mode 100755
index 0000000..752339c
--- /dev/null
+++ b/rs232_1/top.vhd
@@ -0,0 +1,171 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:31:58 03/19/2021
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_constants.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top is
+Generic (
+ G_BOARD_CLOCK : integer := G_BOARD_CLOCK;
+ G_BAUD_RATE : integer := G_BAUD_RATE
+);
+Port (
+ i_clock : in STD_LOGIC;
+ i_reset : in STD_LOGIC;
+ o_RsTX : out STD_LOGIC;
+ i_RsRX : in STD_LOGIC
+);
+end top;
+
+architecture Behavioral of top is
+
+ COMPONENT rs232 IS
+ Generic (
+ G_BOARD_CLOCK : integer := G_BOARD_CLOCK;
+ G_BAUD_RATE : integer := G_BAUD_RATE
+ );
+ Port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ enable_tx : in STD_LOGIC;
+ enable_rx : in STD_LOGIC;
+ byte_to_send : in STD_LOGIC_VECTOR (7 downto 0);
+ byte_received : out STD_LOGIC_VECTOR (7 downto 0);
+ parity_tx : out STD_LOGIC;
+ parity_rx : out STD_LOGIC;
+ busy : out STD_LOGIC;
+ ready : out STD_LOGIC;
+ is_byte_received : out STD_LOGIC;
+ start_rx : out STD_LOGIC;
+ RsTx : out STD_LOGIC;
+ RsRx : in STD_LOGIC
+ );
+ END COMPONENT rs232;
+
+ signal enable_tx,enable_rx,busy,ready,is_byte_received,parity_tx,parity_rx,start_rx : std_logic;
+ signal byte_to_send : std_logic_vector(7 downto 0);
+ signal byte_received : std_logic_vector(7 downto 0);
+
+ type state_type is (
+ idle,
+ st_enable_rx,
+ st_rs_rx,
+ st_disable_rx,
+ st_enable_tx,
+ st_rs232_ready,
+ st_rs232_send,
+ st_rs232_waiting,
+ st_disable_tx
+ );
+ signal state : state_type;
+
+begin
+
+ c_rs232 : rs232
+ GENERIC MAP (
+ G_BOARD_CLOCK => G_BOARD_CLOCK,
+ G_BAUD_RATE => G_BAUD_RATE
+ )
+ PORT MAP (
+ clk => i_clock,
+ rst => i_reset,
+ enable_tx => enable_tx,
+ enable_rx => enable_rx,
+ byte_to_send => byte_to_send,
+ byte_received => byte_received,
+ parity_tx => parity_tx,
+ parity_rx => parity_rx,
+ busy => busy,
+ ready => ready,
+ is_byte_received => is_byte_received,
+ start_rx => start_rx,
+ RsTx => o_RsTX,
+ RsRx => i_RsRX
+ );
+
+ p0 : process (i_clock,i_reset) is
+ begin
+ if (i_reset = '1') then
+ state <= idle;
+ enable_tx <= '0';
+ enable_rx <= '0';
+ elsif (rising_edge(i_clock)) then
+ case (state) is
+ when idle =>
+ if (ready = '1') then
+ state <= st_enable_rx;
+ else
+ state <= idle;
+ end if;
+ when st_enable_rx =>
+ state <= st_rs_rx;
+ enable_rx <= '1';
+ when st_rs_rx =>
+ if (start_rx = '1') then
+ state <= st_disable_rx;
+ else
+ state <= st_rs_rx;
+ end if;
+ when st_disable_rx =>
+ if (is_byte_received = '1') then
+ state <= st_enable_tx;
+ enable_rx <= '0';
+ else
+ state <= st_disable_rx;
+ end if;
+ when st_enable_tx =>
+ state <= st_rs232_ready;
+ enable_tx <= '1';
+ byte_to_send <= byte_received;
+ when st_rs232_ready =>
+ if (ready = '1') then
+ state <= st_rs232_send;
+ else
+ state <= st_rs232_ready;
+ end if;
+ when st_rs232_send =>
+ if (ready = '0') then
+ state <= st_rs232_waiting;
+ else
+ state <= st_rs232_send;
+ end if;
+ when st_rs232_waiting =>
+ if (busy = '1') then
+ state <= st_rs232_waiting;
+ else
+ state <= st_disable_tx;
+ end if;
+ when st_disable_tx =>
+ state <= idle;
+ enable_tx <= '0';
+ end case;
+ end if;
+ end process p0;
+
+end Behavioral;
diff --git a/simple_logicanalyser.gif b/simple_logicanalyser.gif
new file mode 100755
index 0000000..7483424
Binary files /dev/null and b/simple_logicanalyser.gif differ
diff --git a/simple_monitoring_4x_camera.gif b/simple_monitoring_4x_camera.gif
new file mode 100755
index 0000000..647b0df
Binary files /dev/null and b/simple_monitoring_4x_camera.gif differ
diff --git a/sr/binary_to_bcd.vhd b/sr/binary_to_bcd.vhd
new file mode 100755
index 0000000..8ea6821
--- /dev/null
+++ b/sr/binary_to_bcd.vhd
@@ -0,0 +1,113 @@
+--------------------------------------------------------------------------------
+--
+-- FileName: binary_to_bcd.vhd
+-- Dependencies: binary_to_bcd_digit.vhd
+-- Design Software: Quartus II 64-bit Version 13.1.0 Build 162 SJ Web Edition
+--
+-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
+-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
+-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
+-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
+-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
+-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
+-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
+-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
+--
+-- Version History
+-- Version 1.0 6/15/2017 Scott Larson
+-- Initial Public Release
+-- Version 1.1 6/23/2017 Scott Larson
+-- Fixed small corner-case bug
+-- Version 1.2 1/16/2018 Scott Larson
+-- Fixed reset logic to include resetting the state machine
+--
+--------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY binary_to_bcd IS
+ GENERIC(
+ bits : INTEGER := 10; --size of the binary input numbers in bits
+ digits : INTEGER := 3); --number of BCD digits to convert to
+ PORT(
+ clk : IN STD_LOGIC; --system clock
+ reset_n : IN STD_LOGIC; --active low asynchronus reset
+ ena : IN STD_LOGIC; --latches in new binary number and starts conversion
+ binary : IN STD_LOGIC_VECTOR(bits-1 DOWNTO 0); --binary number to convert
+ busy : OUT STD_LOGIC; --indicates conversion in progress
+ bcd : OUT STD_LOGIC_VECTOR(digits*4-1 DOWNTO 0)); --resulting BCD number
+END binary_to_bcd;
+
+ARCHITECTURE logic OF binary_to_bcd IS
+ TYPE machine IS(idle, convert); --needed states
+ SIGNAL state : machine; --state machine
+ SIGNAL binary_reg : STD_LOGIC_VECTOR(bits-1 DOWNTO 0); --latched in binary number
+ SIGNAL bcd_reg : STD_LOGIC_VECTOR(digits*4-1 DOWNTO 0); --bcd result register
+ SIGNAL converter_ena : STD_LOGIC; --enable into each BCD single digit converter
+ SIGNAL converter_inputs : STD_LOGIC_VECTOR(digits DOWNTO 0); --inputs into each BCD single digit converter
+
+ --binary to BCD single digit converter component
+ COMPONENT binary_to_bcd_digit IS
+ PORT(
+ clk : IN STD_LOGIC;
+ reset_n : IN STD_LOGIC;
+ ena : IN STD_LOGIC;
+ binary : IN STD_LOGIC;
+ c_out : BUFFER STD_LOGIC;
+ bcd : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));
+ END COMPONENT binary_to_bcd_digit;
+
+BEGIN
+
+ PROCESS(reset_n, clk)
+ VARIABLE bit_count : INTEGER RANGE 0 TO bits+1 := 0; --counts the binary bits shifted into the converters
+ BEGIN
+ IF(reset_n = '0') THEN --asynchronous reset asserted
+ bit_count := 0; --reset bit counter
+ busy <= '1'; --indicate not available
+ converter_ena <= '0'; --disable the converter
+ bcd <= (OTHERS => '0'); --clear BCD result port
+ state <= idle; --reset state machine
+ ELSIF(clk'EVENT AND clk = '1') THEN --system clock rising edge
+ CASE state IS
+
+ WHEN idle => --idle state
+ IF(ena = '1') THEN --converter is enabled
+ busy <= '1'; --indicate conversion in progress
+ converter_ena <= '1'; --enable the converter
+ binary_reg <= binary; --latch in binary number for conversion
+ bit_count := 0; --reset bit counter
+ state <= convert; --go to convert state
+ ELSE --converter is not enabled
+ busy <= '0'; --indicate available
+ converter_ena <= '0'; --disable the converter
+ state <= idle; --remain in idle state
+ END IF;
+
+ WHEN convert => --convert state
+ IF(bit_count < bits+1) THEN --not all bits shifted in
+ bit_count := bit_count + 1; --increment bit counter
+ converter_inputs(0) <= binary_reg(bits-1); --shift next bit into converter
+ binary_reg <= binary_reg(bits-2 DOWNTO 0) & '0'; --shift binary number register
+ state <= convert; --remain in convert state
+ ELSE --all bits shifted in
+ busy <= '0'; --indicate conversion is complete
+ converter_ena <= '0'; --disable the converter
+ bcd <= bcd_reg; --output result
+ state <= idle; --return to idle state
+ END IF;
+
+ END CASE;
+ END IF;
+ END PROCESS;
+
+ --instantiate the converter logic for the specified number of digits
+ bcd_digits: FOR i IN 1 to digits GENERATE
+ digit_0: binary_to_bcd_digit
+ PORT MAP (clk, reset_n, converter_ena, converter_inputs(i-1), converter_inputs(i), bcd_reg(i*4-1 DOWNTO i*4-4));
+ END GENERATE;
+
+END logic;
+
diff --git a/sr/binary_to_bcd_digit.vhd b/sr/binary_to_bcd_digit.vhd
new file mode 100755
index 0000000..1993ebe
--- /dev/null
+++ b/sr/binary_to_bcd_digit.vhd
@@ -0,0 +1,64 @@
+--------------------------------------------------------------------------------
+--
+-- FileName: binary_to_bcd_digit.vhd
+-- Dependencies: none
+-- Design Software: Quartus II 64-bit Version 13.1.0 Build 162 SJ Web Edition
+--
+-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
+-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
+-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
+-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
+-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
+-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
+-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
+-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
+--
+-- Version History
+-- Version 1.0 6/15/2017 Scott Larson
+-- Initial Public Release
+--
+--------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY binary_to_bcd_digit IS
+ PORT(
+ clk : IN STD_LOGIC; --system clock
+ reset_n : IN STD_LOGIC; --active low asynchronous reset
+ ena : IN STD_LOGIC; --activate operation
+ binary : IN STD_LOGIC; --bit shifted into digit
+ c_out : BUFFER STD_LOGIC; --carry out shifted to next larger digit
+ bcd : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)); --resulting BCD output
+END binary_to_bcd_digit;
+
+ARCHITECTURE logic OF binary_to_bcd_digit IS
+ SIGNAL prev_ena : STD_LOGIC; --keeps track of the previous enable to identify when enable is first asserted
+BEGIN
+
+ c_out <= bcd(3) OR (bcd(2) AND bcd(1)) OR (bcd(2) AND bcd(0)); --assert carry out when register value exceeds 4
+
+ PROCESS(reset_n, clk)
+ BEGIN
+ IF(reset_n = '0') THEN --asynchronous reset asserted
+ prev_ena <= '0'; --clear ena history
+ bcd <= "0000"; --clear output
+ ELSIF(clk'EVENT AND clk = '1') THEN --rising edge of system clock
+ prev_ena <= ena; --keep track of last enable
+ IF(ena = '1') THEN --operation activated
+ IF(prev_ena = '0') THEN --first cycle of activation
+ bcd <= "0000"; --initialize the register
+ ELSIF(c_out = '1') THEN --register value exceeds 4
+ bcd(0) <= binary; --shift new bit into first register
+ bcd(1) <= NOT bcd(0); --set second register to adjusted value
+ bcd(2) <= NOT (bcd(1) XOR bcd(0)); --set third register to adjusted value
+ bcd(3) <= bcd(3) AND bcd(0); --set fourth register to adjusted value
+ ELSE --register value does not exceed 4
+ bcd <= bcd(2 DOWNTO 0) & binary; --shift register values up and shift in new bit
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+
+END logic;
diff --git a/sr/p_constants.vhd b/sr/p_constants.vhd
new file mode 100755
index 0000000..b42e66d
--- /dev/null
+++ b/sr/p_constants.vhd
@@ -0,0 +1,14 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package p_constants is
+ constant G_BOARD_CLOCK : integer := 1_000_000_000; -- 1 GHZ , 1 ns
+-- constant G_BOARD_CLOCK : integer := 50_000_000; -- nexys 2
+-- constant G_BOARD_CLOCK : integer := 8_000_000; -- basys 2
+ constant G_LCD_CLOCK_DIVIDER : integer := 200;
+ constant G_BCD_BITS : integer := 16;
+ constant G_BCD_DIGITS : integer := 4;
+end p_constants;
+
+package body p_constants is
+end p_constants;
diff --git a/sr/sr.xise b/sr/sr.xise
new file mode 100755
index 0000000..3124b90
--- /dev/null
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@@ -0,0 +1,374 @@
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diff --git a/sr/tb_top.vhd b/sr/tb_top.vhd
new file mode 100755
index 0000000..c664c3c
--- /dev/null
+++ b/sr/tb_top.vhd
@@ -0,0 +1,150 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+USE ieee.numeric_std.ALL;
+
+USE WORK.p_constants.ALL;
+
+ENTITY tb_top IS
+END tb_top;
+
+ARCHITECTURE behavior OF tb_top IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT top
+GENERIC (
+constant G_BOARD_CLOCK : integer := G_BOARD_CLOCK;
+constant G_LCD_CLOCK_DIVIDER : integer := G_LCD_CLOCK_DIVIDER
+);
+PORT (
+signal i_clock : in std_logic;
+signal i_reset : in std_logic;
+signal i_push : in std_logic;
+signal i_phase1 : in std_logic;
+signal i_phase2 : in std_logic;
+signal o_anode : out std_logic_vector(3 downto 0);
+signal o_segment : out std_logic_vector(6 downto 0)
+);
+END COMPONENT;
+
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+signal i_push : std_logic := '0';
+signal i_phase1 : std_logic := '0';
+signal i_phase2 : std_logic := '0';
+
+--Outputs
+signal o_anode : std_logic_vector(3 downto 0);
+signal o_segment : std_logic_vector(6 downto 0);
+
+-- Clock period definitions
+constant i_clock_period : time := (1_000_000_000 / G_BOARD_CLOCK) * 1 ns;
+--constant i_clock_period : time := 1 ns;
+
+constant C_WAIT : time := 1 us; -- wait for LCD initialize
+constant N : integer := 28; -- number of tests, apart from 0 and MAX-1
+type vsubarray is array(0 to 2) of integer range 0 to 2**16-1;
+type subarray is array(integer range <>) of vsubarray;
+signal v : subarray(0 to N-1) := (
+ -- 0 => offset, 1 => length, 2 => differ
+ (0,0,0), -- MAX start, not using
+ (60,30,7), -- first tested values
+ (120,30,9),
+ (180,30,11),
+ (240,30,13),
+ -- XXX in cycles , a(i)=a(i-1)+2*b+10,b=x,c=value>=b => false
+ (1010,1000,112),
+ (3020,1000,152),
+ (5030,1000,274),
+ (7040,1000,275),
+ (9050,1000,491),
+ (11060,1000,619),
+ (13070,1000,632),
+ (15080,1000,835),
+ (17090,1000,874),
+ (19100,1000,999),
+ (21110,1000,1000),
+ (23120,2000,1999),
+ (27130,2000,1890),
+ (31140,2000,1999),
+ (35150,2000,1999),
+ (39160,2000,1999),
+ (43170,2000,1999),
+ (47180,2000,1999),
+ (51190,2000,1999),
+ (55200,2000,2000),
+ (59210,2000,4003), -- 4004 dont work, because on this ts we have reset
+ (63220,2000,0000), --last tested values
+ (2**16-1,2**16-1,2**16-1) -- XXX max end, not using
+);
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: top PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+i_push => i_push,
+i_phase1 => i_phase1,
+i_phase2 => i_phase2,
+o_anode => o_anode,
+o_segment => o_segment
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+process (i_clock,i_reset)
+ variable i : integer range 0 to N-1 := 0;
+ variable a,b,c : integer range 0 to 2**16-1 := 0;
+ variable diff : time := 0 ns;
+begin
+ if (rising_edge(i_clock)) then
+ if (i = N-1) then
+ i := N-1;
+ else
+ i := i + 1;
+ a := v(i)(0);
+ b := v(i)(1);
+ c := v(i)(2);
+ diff := (i * i_clock_period) - i_clock_period/2;
+-- report " a = " & integer'image(a) & " b=" & integer'image(b) & " c=" & integer'image(c);
+-- report " diff = " & time'image(diff);
+ end if;
+ -- all signals below have calulated waitings
+ i_phase1 <= transport '1'
+ after C_WAIT + (a * i_clock_period) - time(diff);
+ i_phase1 <= transport '0'
+ after C_WAIT + (a * i_clock_period) + (b * i_clock_period) - time(diff);
+ i_phase2 <= transport '1'
+ after C_WAIT + (a * i_clock_period) + (c * i_clock_period) - time(diff);
+ i_phase2 <= transport '0'
+ after C_WAIT + (a * i_clock_period) + (b * i_clock_period) + (c * i_clock_period) - time(diff);
+ i_reset <= transport '1'
+ after C_WAIT + (a * i_clock_period) - i_clock_period*4 - time(diff);
+ i_reset <= transport '0'
+ after C_WAIT + (a * i_clock_period) - i_clock_period*3 - time(diff);
+ i_push <= transport '1'
+ after C_WAIT + (a * i_clock_period) - i_clock_period*2 - time(diff);
+ i_push <= transport '0'
+ after C_WAIT + (a * i_clock_period) - i_clock_period*1 - time(diff);
+ end if;
+end process;
+
+-- process to wait for all tests
+process
+begin
+wait for 70 us; -- must have timestamp after all tests
+report "done" severity failure;
+end process;
+
+END;
diff --git a/sr/tb_top.wcfg b/sr/tb_top.wcfg
new file mode 100755
index 0000000..b7c4105
--- /dev/null
+++ b/sr/tb_top.wcfg
@@ -0,0 +1,110 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ i_clock
+ i_clock
+
+
+ state
+ state
+
+
+ i_reset
+ i_reset
+
+
+ i_push
+ i_push
+
+
+ i_phase1
+ i_phase1
+
+
+ i_phase2
+ i_phase2
+
+
+ o_anode[3:0]
+ o_anode[3:0]
+
+
+ o_segment[6:0]
+ o_segment[6:0]
+
+
+ lcdchar[3:0]
+ lcdchar[3:0]
+ UNSIGNEDDECRADIX
+ true
+ #ff00ff
+
+
+ cycles[15:0]
+ cycles[15:0]
+ UNSIGNEDDECRADIX
+ true
+ #ffff00
+
+
+ counter
+ counter
+
+
+ enable
+ enable
+
+
+ tick1
+ tick1
+
+
+ tick2
+ tick2
+
+
+ lcd_clock
+ lcd_clock
+
+
+ bcd_enable
+ bcd_enable
+
+
+ bcd_busy
+ bcd_busy
+
+
+ bcd_binary[15:0]
+ bcd_binary[15:0]
+
+
+ bcd_digits[15:0]
+ bcd_digits[15:0]
+
+
+ g_board_clock
+ g_board_clock
+
+
+ g_lcd_clock_divider
+ g_lcd_clock_divider
+
+
diff --git a/sr/top.ucf b/sr/top.ucf
new file mode 100755
index 0000000..a0ae7d7
--- /dev/null
+++ b/sr/top.ucf
@@ -0,0 +1,21 @@
+NET "i_clock" LOC = "B8";
+
+NET "i_reset" LOC = "R17";
+
+NET "i_push" LOC = "G18";
+
+NET "i_phase1" LOC = "B18";
+NET "i_phase2" LOC = "D18";
+
+NET "o_anode<0>" LOC = "F17";
+NET "o_anode<1>" LOC = "H17";
+NET "o_anode<2>" LOC = "C18";
+NET "o_anode<3>" LOC = "F15";
+
+NET "o_segment<0>" LOC = "L18";
+NET "o_segment<1>" LOC = "F18";
+NET "o_segment<2>" LOC = "D17";
+NET "o_segment<3>" LOC = "D16";
+NET "o_segment<4>" LOC = "G14";
+NET "o_segment<5>" LOC = "J17";
+NET "o_segment<6>" LOC = "H14";
diff --git a/sr/top.vhd b/sr/top.vhd
new file mode 100755
index 0000000..df9f1da
--- /dev/null
+++ b/sr/top.vhd
@@ -0,0 +1,281 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+use IEEE.NUMERIC_STD.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+use WORK.p_constants.ALL;
+
+entity top is
+generic (
+ constant G_BOARD_CLOCK : integer := G_BOARD_CLOCK; -- input clock from board
+ constant G_LCD_CLOCK_DIVIDER : integer := G_LCD_CLOCK_DIVIDER -- divider for lcd
+);
+port (
+ signal i_clock : in std_logic; -- main clock
+ signal i_reset : in std_logic; -- main reset
+ signal i_push : in std_logic; -- release for run p0 process, before input phases
+ signal i_phase1 : in std_logic; -- for first phase
+ signal i_phase2 : in std_logic; -- for second phase
+ signal o_anode : out std_logic_vector(3 downto 0); -- to lcd, anode
+ signal o_segment : out std_logic_vector(6 downto 0) -- to lcd, segment multiplexing
+);
+end top;
+
+architecture Behavioral of top is
+
+type states is (a,b,c,d,e,f); -- states for process p0, e,f is for bcd convert a-d is for calculate phase
+signal state : states;
+type LCDHex is array(3 downto 0) of std_logic_vector(3 downto 0); -- for 4x lcd, slv30 is for hexdecimal 0-f
+signal LCDChar : LCDHex;
+signal counter : integer range 0 to 2**16-1; -- 16bit = FFFF, so we fit in lcd
+signal cycles : std_logic_vector(15 downto 0); -- from counter
+signal enable,tick1,tick2,lcd_clock,bcd_enable,bcd_busy : std_logic; -- signals for operate
+signal bcd_binary : std_logic_vector(G_BCD_BITS-1 downto 0); -- for bcd converter, input
+signal bcd_digits : std_logic_vector(G_BCD_DIGITS*4-1 downto 0); -- also for bcd converter, output
+
+-- XXX based on https://forum.digikey.com/t/binary-to-bcd-converter-vhdl/12530
+COMPONENT binary_to_bcd IS
+ GENERIC(
+ bits : INTEGER := G_BCD_BITS; --size of the binary input numbers in bits
+ digits : INTEGER := G_BCD_DIGITS); --number of BCD digits to convert to
+ PORT(
+ clk : IN STD_LOGIC; --system clock
+ reset_n : IN STD_LOGIC; --active low asynchronus reset
+ ena : IN STD_LOGIC; --latches in new binary number and starts conversion
+ binary : IN STD_LOGIC_VECTOR(bits-1 DOWNTO 0); --binary number to convert
+ busy : OUT STD_LOGIC; --indicates conversion in progress
+ bcd : OUT STD_LOGIC_VECTOR(digits*4-1 DOWNTO 0)); --resulting BCD number
+END COMPONENT binary_to_bcd;
+for all : binary_to_bcd use entity WORK.binary_to_bcd(logic);
+
+begin
+
+-- process for divide clock for lcd, we must slowly the main clock for properly work
+plcddiv : process (i_clock,i_reset) is
+ constant clock_divider : integer := G_BOARD_CLOCK / 1000 / G_LCD_CLOCK_DIVIDER; -- result for plcddiv process
+ variable clock_out : std_logic; -- to output
+ variable counter : integer range 0 to clock_divider - 1 := 0; -- main variable plcddiv
+begin
+ if (i_reset = '1') then -- when main reset, restart all values
+ clock_out := '0'; -- when reset, keep disabled lcd clock
+ counter := 0; -- reset counting
+ elsif (rising_edge(i_clock)) then -- when we have rising edge, use condition below
+ if (counter = clock_divider-1) then -- when we have max counting
+ clock_out := '1'; -- bring out lcd tick
+ counter := 0; -- reset from beginig
+ else
+ clock_out := '0'; -- keep the disabled lcd
+ counter := counter + 1; -- increment counter lcd
+ end if;
+ end if;
+ lcd_clock <= clock_out; -- bring out outside process
+end process plcddiv;
+
+plcdanode : process (lcd_clock,i_reset) is
+ variable count : integer range 0 to 3 := 0;
+begin
+ if (i_reset = '1') then
+ o_anode <= (others => '1');
+ count := 0;
+ elsif (rising_edge(lcd_clock)) then
+ case count is -- multiplexing 4 anodes, when 0 we pull down the voltage for lcd
+ when 0 =>
+ o_anode(3 downto 0) <= "0111"; -- first anode lcd
+ when 1 =>
+ o_anode(3 downto 0) <= "1011"; -- second anode lcd
+ when 2 =>
+ o_anode(3 downto 0) <= "1101"; -- third anode lcd
+ when 3 =>
+ o_anode(3 downto 0) <= "1110"; -- quarter anode lcd
+ when others =>
+ o_anode(3 downto 0) <= "1111"; -- for undefined condition, disable all 4x lcd
+ end case;
+ if (count = 3) then -- counting for 4 anodes, always increment when we have plcddiv tick
+ count := 0;
+ else
+ count := count + 1;
+ end if;
+ end if;
+end process plcdanode;
+
+plcdsegment : process (lcd_clock,i_reset) is -- very likely above
+ variable count : integer range 0 to 3 := 0;
+begin
+ if (i_reset = '1') then -- when global reseting
+ o_segment <= (others => '0'); -- disable all 7 segment
+ count := 0;
+ elsif (rising_edge(lcd_clock)) then
+ case to_integer(unsigned(LCDChar(count))) is -- check the all 4 chars from LCDChar signal and bring out the value to lcd
+ when 0 => o_segment <= "1000000"; -- 0
+ when 1 => o_segment <= "1111001"; -- 1
+ when 2 => o_segment <= "0100100"; -- 2
+ when 3 => o_segment <= "0110000"; -- 3
+ when 4 => o_segment <= "0011001"; -- 4
+ when 5 => o_segment <= "0010010"; -- 5
+ when 6 => o_segment <= "0000010"; -- 6
+ when 7 => o_segment <= "1111000"; -- 7
+ when 8 => o_segment <= "0000000"; -- 8
+ when 9 => o_segment <= "0010000"; -- 9
+ when 10 => o_segment <= "0001000"; -- a
+ when 11 => o_segment <= "0000011"; -- b
+ when 12 => o_segment <= "1000110"; -- c
+ when 13 => o_segment <= "0100001"; -- d
+ when 14 => o_segment <= "0000110"; -- e
+ when 15 => o_segment <= "0001110"; -- f
+ when others => null;
+ end case;
+ if (count = 3) then -- multiplexing lcd 1-4
+ count := 0;
+ else
+ count := count + 1;
+ end if;
+ end if;
+end process plcdsegment;
+
+-- helper for bring out rising edge for phase1, when phase1 begin, tick equal one period main clock
+pre1 : process (i_clock,i_reset,i_phase1) is
+ type states is (a,b,c);
+ variable state : states;
+begin
+ if (i_reset = '1') then -- global reset for all project
+ tick1 <= '0'; -- keep low
+ state := a; -- return to begin FSM
+ elsif (rising_edge(i_clock)) then -- when RE main clock
+ case (state) is
+ when a => -- check when phase1 have 1, then go to state b, else stay on state a, and go out 1 for tick1 signal
+ if (i_phase1 = '1') then
+ state := b;
+ tick1 <= '1';
+ else
+ state := a;
+ tick1 <= '0';
+ end if;
+ when b => -- keep the 0 for next global i_reset
+ state := b;
+ tick1 <= '0';
+ when others => -- when other states, this is for recovery FSM when something will go wrong
+ state := a;
+ tick1 <= '0';
+ end case;
+ end if;
+end process pre1;
+
+-- helper for phase2, same as for phase1/tick1 signal
+pre2 : process (i_clock,i_reset,i_phase2) is
+ type states is (a,b,c);
+ variable state : states;
+begin
+ if (i_reset = '1') then
+ tick2 <= '0';
+ state := a;
+ elsif (rising_edge(i_clock)) then
+ case (state) is
+ when a =>
+ if (i_phase2 = '1') then
+ state := b;
+ tick2 <= '1';
+ else
+ state := a;
+ tick2 <= '0';
+ end if;
+ when b =>
+ state := b;
+ tick2 <= '0';
+ when others =>
+ state := a;
+ tick2 <= '0';
+ end case;
+ end if;
+end process pre2;
+
+-- main counting, when ENABLE comes from main p0 process, then count the cycles between phase1 and phase2
+pcnt : process (i_clock,i_reset,enable) is
+begin
+ if (i_reset = '1') then
+ counter <= 0;
+ elsif (rising_edge(i_clock)) then
+ if (enable = '1') then
+ counter <= counter + 1;
+ else
+ counter <= counter;
+ end if;
+ end if;
+end process pcnt;
+
+-- bring out the converted values to 4x lcd
+LCDChar <= (
+bcd_digits(3 downto 0),
+bcd_digits(7 downto 4),
+bcd_digits(11 downto 8),
+bcd_digits(15 downto 12)
+);
+
+-- main process
+p0 : process (i_clock,i_reset,tick1,tick2) is -- sensitive for properly FSM work, must have tick1 and tick2 because we read from this signals
+begin
+ if (i_reset = '1') then -- when we reset the project, we start from beginig
+ state <= a;
+ enable <= '0';
+ cycles <= (others => '0');
+ bcd_enable <= '0';
+ bcd_binary <= (others => '0');
+ elsif(rising_edge(i_clock)) then -- elsewhere FSM run
+ case (state) is
+ when a => -- wait for triggering
+ if (i_push = '1') then
+ state <= b;
+ else
+ state <= a;
+ end if;
+ when b => -- check when tick 1 or 2 have one, then go to c state, else stay in b and wait for condition
+ if (tick1 = '1' or tick2 = '1') then
+ enable <= '1'; -- run the counting pcnt process
+ state <= c; -- go to c state
+ else -- stay in b state
+ enable <= '0';
+ state <= b;
+ end if;
+ when c =>
+ if (tick2 = '1' or tick1 = '1') then -- check when tick 1 or 2 is positive, then stop counting pcnt process and go to d for BCD converiosn
+ enable <= '0';
+ state <= d;
+ else -- stay and wait for ending tick1 or tick2
+ enable <= '1';
+ state <= c;
+ end if;
+ when d => -- information, for know how much we have ticks between phases
+ cycles <= std_logic_vector(to_unsigned(counter,16));
+ state <= e;
+ when e => -- start conversion from hexdecimals values to human output
+ bcd_enable <= '1';
+ bcd_binary <= cycles(G_BCD_BITS-1 downto 0);
+ state <= f;
+ when f => -- wait when bcd conversion ending
+ if (bcd_busy = '1') then -- conversion in progress
+ state <= f;
+ bcd_enable <= '1';
+ else -- end conversion, return to IDLE state and wait for next measuring
+ state <= a;
+ bcd_enable <= '0';
+ end if;
+ end case;
+ end if;
+end process p0;
+
+-- component to conversion from digikey
+bcd : binary_to_bcd
+generic map (bits => G_BCD_BITS, digits => G_BCD_DIGITS)
+port map (
+clk => i_clock,
+reset_n => not i_reset,
+ena => bcd_enable, -- start and wait for convert
+binary => bcd_binary, -- source values from measurement
+busy => bcd_busy, -- flag for waiting in state f
+bcd => bcd_digits -- output for LCD
+);
+
+end Behavioral;
+
diff --git a/st7735r/draw_box.vhd b/st7735r/draw_box.vhd
new file mode 100755
index 0000000..04e090b
--- /dev/null
+++ b/st7735r/draw_box.vhd
@@ -0,0 +1,481 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:09:37 06/23/2021
+-- Design Name:
+-- Module Name: draw_box - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_package.ALL;
+use WORK.p_screen.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity draw_box is
+port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_run : in std_logic;
+ i_sended : in std_logic;
+ i_color : in COLOR_TYPE;
+ i_raxs : in BYTE_TYPE;
+ i_raxe : in BYTE_TYPE;
+ i_rays : in BYTE_TYPE;
+ i_raye : in BYTE_TYPE;
+ i_caxs : in BYTE_TYPE;
+ i_caxe : in BYTE_TYPE;
+ i_cays : in BYTE_TYPE;
+ i_caye : in BYTE_TYPE;
+ o_data : out BYTE_TYPE;
+ o_enable : out std_logic;
+ o_rs : out std_logic;
+ o_initialized : out std_logic
+);
+end draw_box;
+
+architecture Behavioral of draw_box is
+
+ signal rs,enable,sended,initialized : std_logic;
+ signal send_data,send_command : BYTE_TYPE;
+ signal raxs,raxe,rays,raye,caxs,caxe,cays,caye : BYTE_TYPE;
+ type states is (
+ idle,start,
+ sendracmd,sendracmdw1,sendracmdw1a,
+ sendraxs,sendraxsw1,sendraxsw1a,
+ sendrays,sendraysw1,sendraysw1a,
+ sendraxe,sendraxew1,sendraxew1a,
+ sendraye,sendrayew1,sendrayew1a,
+ sendcacmd,sendcacmdw1,sendcacmdw1a,
+ sendcaxs,sendcaxsw1,sendcaxsw1a,
+ sendcays,sendcaysw1,sendcaysw1a,
+ sendcaxe,sendcaxew1,sendcaxew1a,
+ sendcaye,sendcayew1,sendcayew1a,
+ sendmemwr,sendmemwrw1,sendmemwrw1a,
+ fillarealb,fillarealbw1,fillarealbw1a,
+ fillareahb,fillareahbw1,fillareahbw1a,
+ fillarenaindex,
+ stop);
+ signal state : states;
+
+begin
+
+ o_data <= send_command when rs = '0' else send_data when rs = '1';
+ o_rs <= rs;
+ sended <= i_sended;
+ o_enable <= enable;
+ o_initialized <= initialized;
+ raxs <= i_raxs;
+ raxe <= i_raxe;
+ rays <= i_rays;
+ raye <= i_raye;
+ caxs <= i_caxs;
+ caxe <= i_caxe;
+ cays <= i_cays;
+ caye <= i_caye;
+
+ p0 : process (i_clock,i_reset) is
+ variable w0_index : integer range 0 to 2**25;
+ variable index : integer;
+ variable x,y : integer;
+ begin
+ if (i_reset = '1') then
+ state <= idle;
+ w0_index := 0;
+ enable <= '0';
+ rs <= '0';
+ send_command <= (others => '0');
+ send_data <= (others => '0');
+ initialized <= '0';
+ x := 0;
+ y := 0;
+ index := 0;
+ elsif (rising_edge(i_clock)) then
+ case (state) is
+ when idle =>
+ initialized <= '0';
+ if (i_run = '1') then
+ state <= start;
+ else
+ state <= idle;
+ end if;
+ when start =>
+ state <= sendracmd;
+ when sendracmd =>
+ send_command <= x"2b"; --RASET
+ rs <= '0';
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendracmdw1;
+ else
+ state <= sendracmd;
+ end if;
+ when sendracmdw1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendracmdw1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendracmdw1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendracmdw1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendraxs;
+ w0_index := 0;
+ else
+ state <= sendracmdw1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendraxs => -- c1
+ rs <= '1';
+ send_data <= raxs;
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendraxsw1;
+ else
+ state <= sendraxs;
+ end if;
+ when sendraxsw1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendraxsw1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendraxsw1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendraxsw1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendrays;
+ w0_index := 0;
+ else
+ state <= sendraxsw1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendrays => -- c2
+ rs <= '1';
+ send_data <= raxe;
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendraysw1;
+ else
+ state <= sendrays;
+ end if;
+ when sendraysw1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendraysw1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendraysw1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendraysw1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendraxe;
+ w0_index := 0;
+ else
+ state <= sendraysw1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendraxe => -- c3
+ rs <= '1';
+ send_data <= rays;
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendraxew1;
+ else
+ state <= sendraxe;
+ end if;
+ when sendraxew1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendraxew1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendraxew1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendraxew1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendraye;
+ w0_index := 0;
+ else
+ state <= sendraxew1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendraye => -- c4
+ rs <= '1';
+ send_data <= caxe;
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendrayew1;
+ else
+ state <= sendraye;
+ end if;
+ when sendrayew1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendrayew1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendrayew1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendrayew1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcacmd;
+ w0_index := 0;
+ else
+ state <= sendrayew1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcacmd =>
+ rs <= '0';
+ send_command <= x"2a"; --CASET
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendcacmdw1;
+ else
+ state <= sendcacmd;
+ end if;
+ when sendcacmdw1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcacmdw1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendcacmdw1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcacmdw1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcaxs;
+ w0_index := 0;
+ else
+ state <= sendcacmdw1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcaxs => -- c5
+ rs <= '1';
+ send_data <= caxs;
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendcaxsw1;
+ else
+ state <= sendcaxs;
+ end if;
+ when sendcaxsw1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcaxsw1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendcaxsw1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcaxsw1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcays;
+ w0_index := 0;
+ else
+ state <= sendcaxsw1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcays => -- c6
+ rs <= '1';
+ send_data <= raye;
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendcaysw1;
+ else
+ state <= sendcays;
+ end if;
+ when sendcaysw1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcaysw1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendcaysw1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcaysw1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcaxe;
+ w0_index := 0;
+ else
+ state <= sendcaysw1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcaxe => -- c7
+ rs <= '1';
+ send_data <= cays;
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendcaxew1;
+ else
+ state <= sendcaxe;
+ end if;
+ when sendcaxew1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcaxew1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendcaxew1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcaxew1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcaye;
+ w0_index := 0;
+ else
+ state <= sendcaxew1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcaye => -- c8
+ rs <= '1';
+ send_data <= caye;
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendcayew1;
+ else
+ state <= sendcaye;
+ end if;
+ when sendcayew1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendcayew1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendcayew1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendcayew1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendmemwr;
+ w0_index := 0;
+ else
+ state <= sendcayew1a;
+ w0_index := w0_index + 1;
+ end if;
+ when sendmemwr =>
+ x := to_integer(unsigned(caxe)) - to_integer(unsigned(raxe));
+ y := to_integer(unsigned(caye)) - to_integer(unsigned(raye));
+ rs <= '0';
+ send_command <= x"2c"; --RAMWR
+ enable <= '1';
+ if (sended = '1') then
+ state <= sendmemwrw1;
+ else
+ state <= sendmemwr;
+ end if;
+ when sendmemwrw1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= sendmemwrw1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= sendmemwrw1;
+ w0_index := w0_index + 1;
+ end if;
+ when sendmemwrw1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= fillarealb;
+ w0_index := 0;
+ else
+ state <= sendmemwrw1a;
+ w0_index := w0_index + 1;
+ end if;
+ when fillarealb =>
+ rs <= '1';
+ send_data <= i_color(15 downto 8);
+ enable <= '1';
+ if (sended = '1') then
+ state <= fillarealbw1;
+ else
+ state <= fillarealb;
+ end if;
+ when fillarealbw1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= fillarealbw1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= fillarealbw1;
+ w0_index := w0_index + 1;
+ end if;
+ when fillarealbw1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= fillareahb;
+ w0_index := 0;
+ else
+ state <= fillarealbw1a;
+ w0_index := w0_index + 1;
+ end if;
+ when fillareahb =>
+ rs <= '1';
+ send_data <= i_color(7 downto 0);
+ enable <= '1';
+ if (sended = '1') then
+ state <= fillareahbw1;
+ else
+ state <= fillareahb;
+ end if;
+ when fillareahbw1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= fillareahbw1a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= fillareahbw1;
+ w0_index := w0_index + 1;
+ end if;
+ when fillareahbw1a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= fillarenaindex;
+ w0_index := 0;
+ else
+ state <= fillareahbw1a;
+ w0_index := w0_index + 1;
+ end if;
+ when fillarenaindex =>
+ if (index = (x*y) - 1) then -- XXX TODO x*y - 1 drop last pixel
+ state <= stop;
+ index := 0;
+ enable <= '0';
+ initialized <= '1';
+ else
+ state <= fillarealb;
+ index := index + 1;
+ end if;
+ when stop =>
+ state <= idle;
+ when others =>
+ state <= idle;
+ end case;
+ end if;
+ end process p0;
+
+end Behavioral;
diff --git a/st7735r/initialize.vhd b/st7735r/initialize.vhd
new file mode 100755
index 0000000..260ced8
--- /dev/null
+++ b/st7735r/initialize.vhd
@@ -0,0 +1,452 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:41:34 06/14/2021
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_package.ALL;
+use WORK.p_screen.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity initialize is
+port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_run : in std_logic;
+ i_color : in COLOR_TYPE;
+ i_sended : in std_logic;
+ o_initialized : out std_logic;
+ o_enable : out std_logic;
+ o_data_byte : out BYTE_TYPE;
+ o_reset : out std_logic;
+ o_rs : out std_logic;
+ o_cs : out std_logic
+);
+end initialize;
+
+architecture Behavioral of initialize is
+ signal data_byte : BYTE_TYPE;
+ signal sended : std_logic;
+ type states is (
+ idle,
+ -- XXX initialize
+ smallwait0,smallwait1,smallwait2,
+ swreset,initwait0,initwait0a,slpout,initwait1,initwait1a,
+ start,check_index,initwait4,wait0,wait1,initwait4a,
+ noron,initwait2,initwait2a,dispon,initwait3,initwait3a,
+ csup,
+ -- XXX black screen
+ bsinitwait,bsstart,bs_check_index,bswaitdata0,bswait0,bswait1,
+ bswaitdata0a,bsfillbytel,bsfillbytelwait0,bsfillbytelwait0a,
+ bsfillbyteh,bsfillbytehwait0,bsfillbytehwait0a,bsfill_check_index,
+ bscsup,bsfillwait0,bsfillwait1
+ );
+ signal state : states;
+ signal enable,cs,reset,rs,initialized : std_logic;
+ signal data_index : integer range 0 to 2**16;
+
+begin
+
+ o_enable <= enable;
+ o_cs <= cs;
+ o_reset <= reset;
+ o_rs <= rs;
+ o_initialized <= initialized;
+ sended <= i_sended;
+ o_data_byte <= data_byte;
+
+ p0 : process (i_clock,i_reset,sended) is
+ variable w0_index : integer range 0 to 2**25;
+ constant C_CLOCK_COUNTER_7 : integer := C_CLOCK_COUNTER * 7;
+ constant C_CLOCK_COUNTER_150 : integer := C_CLOCK_COUNTER * 150;
+ constant C_CLOCK_COUNTER_500 : integer := C_CLOCK_COUNTER * 500;
+ constant C_CLOCK_COUNTER_10 : integer := C_CLOCK_COUNTER * 10;
+ constant C_CLOCK_COUNTER_100 : integer := C_CLOCK_COUNTER * 100;
+ begin
+ if (i_reset = '1') then
+ state <= idle;
+ w0_index := 0;
+ data_index <= 0;
+ enable <= '0';
+ cs <= '1';
+ reset <= '1';
+ rs <= '1';
+ initialized <= '0';
+ elsif (rising_edge(i_clock)) then
+ case state is
+ when idle =>
+ initialized <= '0';
+ if (i_run = '1') then
+ state <= smallwait0;
+ else
+ state <= idle;
+ end if;
+ when smallwait0 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= smallwait1;
+ w0_index := 0;
+ reset <= '0';
+ else
+ state <= smallwait0;
+ w0_index := w0_index + 1;
+ cs <= '0';
+ end if;
+ when smallwait1 =>
+ if (w0_index = C_CLOCK_COUNTER_7 - 1) then
+ state <= smallwait2;
+ w0_index := 0;
+ reset <= '1';
+ else
+ state <= smallwait1;
+ w0_index := w0_index + 1;
+ end if;
+ when smallwait2 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= swreset;
+ w0_index := 0;
+ else
+ state <= smallwait2;
+ w0_index := w0_index + 1;
+ end if;
+ when swreset =>
+ data_byte <= x"01";
+ enable <= '1';
+ rs <= '0';
+ if (sended = '1') then
+ state <= initwait0;
+ else
+ state <= swreset;
+ end if;
+ when initwait0 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= initwait0a;
+ w0_index := 0;
+ enable <= '0';
+ rs <= '1';
+ else
+ state <= initwait0;
+ w0_index := w0_index + 1;
+ end if;
+ when initwait0a =>
+ if (w0_index = C_CLOCK_COUNTER_150 - 1) then
+ state <= slpout;
+ w0_index := 0;
+ else
+ state <= initwait0a;
+ w0_index := w0_index + 1;
+ end if;
+ when slpout =>
+ data_byte <= x"11";
+ enable <= '1';
+ rs <= '0';
+ if (sended = '1') then
+ state <= initwait1;
+ else
+ state <= slpout;
+ end if;
+ when initwait1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= initwait1a;
+ w0_index := 0;
+ enable <= '0';
+ rs <= '1';
+ else
+ state <= initwait1;
+ w0_index := w0_index + 1;
+ end if;
+ when initwait1a =>
+ if (w0_index = C_CLOCK_COUNTER_500 - 1) then
+ state <= start;
+ w0_index := 0;
+ else
+ state <= initwait1a;
+ w0_index := w0_index + 1;
+ end if;
+ when start =>
+ data_byte <= data_rom_initscreen(data_index);
+ enable <= '1';
+ if (data_rom_initscreen(data_index + 1) = x"01") then
+ rs <= '0';
+ elsif (data_rom_initscreen(data_index + 1) = x"00") then
+ rs <= '1';
+ end if;
+ if (sended = '1') then
+ state <= check_index;
+ else
+ state <= start;
+ end if;
+ when check_index =>
+ if (data_index = data_size_initscreen - 2) then
+ data_index <= 0;
+ state <= initwait4;
+ else
+ data_index <= data_index + 2;
+ state <= wait0;
+ end if;
+ when wait0 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= wait1;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= wait0;
+ w0_index := w0_index + 1;
+ end if;
+ when wait1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= start;
+ w0_index := 0;
+ else
+ state <= wait1;
+ w0_index := w0_index + 1;
+ end if;
+ when initwait4 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= initwait4a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= initwait4;
+ w0_index := w0_index + 1;
+ end if;
+ when initwait4a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= noron;
+ w0_index := 0;
+ else
+ state <= initwait4a;
+ w0_index := w0_index + 1;
+ end if;
+ when noron =>
+ data_byte <= x"13";
+ enable <= '1';
+ rs <= '0';
+ if (sended = '1') then
+ state <= initwait2;
+ else
+ state <= noron;
+ end if;
+ when initwait2 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= initwait2a;
+ w0_index := 0;
+ enable <= '0';
+ rs <= '1';
+ else
+ state <= initwait2;
+ w0_index := w0_index + 1;
+ end if;
+ when initwait2a =>
+ if (w0_index = C_CLOCK_COUNTER_10 - 1) then
+ state <= dispon;
+ w0_index := 0;
+ else
+ state <= initwait2a;
+ w0_index := w0_index + 1;
+ end if;
+ when dispon =>
+ data_byte <= x"29";
+ enable <= '1';
+ rs <= '0';
+ if (sended = '1') then
+ state <= initwait3;
+ else
+ state <= dispon;
+ end if;
+ when initwait3 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= initwait3a;
+ w0_index := 0;
+ enable <= '0';
+ rs <= '1';
+ else
+ state <= initwait3;
+ w0_index := w0_index + 1;
+ end if;
+ when initwait3a =>
+ if (w0_index = C_CLOCK_COUNTER_100 - 1) then
+ state <= csup;
+ w0_index := 0;
+ else
+ state <= initwait3a;
+ w0_index := w0_index + 1;
+ end if;
+ when csup =>
+ state <= bsinitwait ;
+ enable <= '0';
+ cs <= '1';
+ -----------------------------------------------
+ when bsinitwait =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bsstart;
+ w0_index := 0;
+ else
+ state <= bsinitwait ;
+ w0_index := w0_index + 1;
+ end if;
+ when bsstart =>
+ data_byte <= data_rom_blackscreen(data_index);
+ enable <= '1';
+ if (data_rom_blackscreen(data_index + 1) = x"01") then
+ rs <= '0';
+ elsif (data_rom_blackscreen(data_index + 1) = x"00") then
+ rs <= '1';
+ end if;
+ if (sended = '1') then
+ state <= bs_check_index;
+ else
+ state <= bsstart;
+ end if;
+ when bs_check_index =>
+ if (data_index = data_size_blackscreen - 2) then
+ data_index <= 0;
+ state <= bswaitdata0;
+ else
+ data_index <= data_index + 2;
+ state <= bswait0;
+ end if;
+ when bswait0 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bswait1;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= bswait0;
+ w0_index := w0_index + 1;
+ end if;
+ when bswait1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bsstart;
+ w0_index := 0;
+ else
+ state <= bswait1;
+ w0_index := w0_index + 1;
+ end if;
+ when bswaitdata0 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bswaitdata0a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= bswaitdata0;
+ w0_index := w0_index + 1;
+ end if;
+ when bswaitdata0a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bsfillbytel;
+ w0_index := 0;
+ else
+ state <= bswaitdata0a;
+ w0_index := w0_index + 1;
+ end if;
+ when bsfillbytel =>
+ data_byte <= i_color(15 downto 8);
+ enable <= '1';
+ rs <= '1';
+ if (sended = '1') then
+ state <= bsfillbytelwait0;
+ else
+ state <= bsfillbytel;
+ end if;
+ when bsfillbytelwait0 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bsfillbytelwait0a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= bsfillbytelwait0;
+ w0_index := w0_index + 1;
+ end if;
+ when bsfillbytelwait0a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bsfillbyteh;
+ w0_index := 0;
+ else
+ state <= bsfillbytelwait0a;
+ w0_index := w0_index + 1;
+ end if;
+ when bsfillbyteh =>
+ data_byte <= i_color(7 downto 0);
+ enable <= '1';
+ rs <= '1';
+ if (sended = '1') then
+ state <= bsfillbytehwait0;
+ else
+ state <= bsfillbyteh;
+ end if;
+ when bsfillbytehwait0 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bsfillbytehwait0a;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= bsfillbytehwait0;
+ w0_index := w0_index + 1;
+ end if;
+ when bsfillbytehwait0a =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bsfill_check_index;
+ w0_index := 0;
+ else
+ state <= bsfillbytehwait0a;
+ w0_index := w0_index + 1;
+ end if;
+ when bsfill_check_index =>
+ if (data_index = SCREEN_FILL - 1) then
+ data_index <= 0;
+ state <= bscsup;
+ initialized <= '1';
+ enable <= '0';
+ else
+ data_index <= data_index + 1;
+ state <= bsfillwait0;
+ end if;
+ when bsfillwait0 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bsfillwait1;
+ w0_index := 0;
+ enable <= '0';
+ else
+ state <= bsfillwait0;
+ w0_index := w0_index + 1;
+ end if;
+ when bsfillwait1 =>
+ if (w0_index = C_CLOCK_COUNTER - 1) then
+ state <= bsfillbytel;
+ w0_index := 0;
+ else
+ state <= bsfillwait1;
+ w0_index := w0_index + 1;
+ end if;
+ when bscsup =>
+ state <= idle ;
+ cs <= '1';
+ end case;
+ end if;
+ end process p0;
+
+end Behavioral;
+
diff --git a/st7735r/my_spi.vhd b/st7735r/my_spi.vhd
new file mode 100755
index 0000000..68b84cb
--- /dev/null
+++ b/st7735r/my_spi.vhd
@@ -0,0 +1,128 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:12:21 06/13/2021
+-- Design Name:
+-- Module Name: my_spi - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_package.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity my_spi is
+port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_enable : in std_logic;
+ i_data_byte : in BYTE_TYPE;
+ o_cs : out std_logic;
+ o_do : out std_logic;
+ o_ck : out std_logic;
+ o_sended : out std_logic
+);
+end my_spi;
+
+architecture Behavioral of my_spi is
+ signal clock_divider,clock_data : std_logic;
+ signal data_index : integer range BYTE_SIZE - 1 downto 0;
+ signal ck : std_logic;
+begin
+ o_cs <= '0' when i_enable = '1' else '1';
+ o_do <= i_data_byte(BYTE_SIZE - 1 - data_index) when i_enable = '1' else '0';
+ o_sended <= '1' when data_index = BYTE_SIZE - 1 and i_enable = '1' else '0';
+
+ p0 : process (i_clock,i_reset) is
+ variable clock_counter : integer range 0 to C_CLOCK_COUNTER - 1 := 0;
+ begin
+ if (i_reset = '1') then
+ clock_counter := 0;
+ clock_divider <= '0';
+ elsif (rising_edge(i_clock)) then
+ if (i_enable = '1') then
+ if (clock_counter = C_CLOCK_COUNTER/4 - 1) then
+ clock_divider <= not clock_divider;
+ clock_counter := 0;
+ else
+ clock_counter := clock_counter + 1;
+ end if;
+ else
+ clock_divider <= '0';
+ clock_counter := 0;
+ end if;
+ end if;
+ end process p0;
+
+ p1 : process (clock_divider,i_reset,i_enable) is
+ begin
+ if (i_reset = '1') then
+ ck <= '0';
+ elsif (rising_edge(clock_divider)) then
+ if (i_enable = '1') then
+ ck <= not ck;
+ else
+ ck <= '0';
+ end if;
+ end if;
+ end process p1;
+ o_ck <= ck;
+
+ p2 : process (clock_data,i_reset,i_enable) is
+ begin
+ if (i_reset = '1') then
+ data_index <= 0;
+ elsif (rising_edge(clock_data)) then
+ if (i_enable = '1') then
+ if (data_index = BYTE_SIZE - 1) then
+ data_index <= 0;
+ else
+ data_index <= data_index + 1;
+ end if;
+ else
+ data_index <= 0;
+ end if;
+ end if;
+ end process p2;
+
+ p3 : process (clock_divider,i_reset,i_enable) is
+ constant cd : integer := 2;
+ variable d : integer range 0 to cd - 1;
+ begin
+ if (i_reset = '1') then
+ clock_data <= '0';
+ d := 0;
+ elsif (rising_edge(clock_divider)) then
+ if (i_enable = '1') then
+ if (d = cd - 1) then
+ clock_data <= '1';
+ d := 0;
+ else
+ clock_data <= '0';
+ d := d + 1;
+ end if;
+ else
+ clock_data <= '0';
+ end if;
+ end if;
+ end process p3;
+end Behavioral;
diff --git a/st7735r/p_package.vhd b/st7735r/p_package.vhd
new file mode 100755
index 0000000..b6891dc
--- /dev/null
+++ b/st7735r/p_package.vhd
@@ -0,0 +1,27 @@
+--
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+--
+-- To use any of the example code shown below, uncomment the lines and modify as necessary
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package p_package is
+
+ constant BYTE_SIZE : integer := 8;
+ subtype BYTE_TYPE is std_logic_vector(BYTE_SIZE - 1 downto 0);
+ constant ABOUT_1coma31_MS: integer := 2**16; --XXX ~1.31ms on 50mhz
+-- constant C_CLOCK_COUNTER : integer := 2**16; -- XXX slow
+-- constant C_CLOCK_COUNTER : integer := 2**8; -- XXX fast
+ constant C_CLOCK_COUNTER : integer := 2**4; -- XXX very fast
+-- constant C_CLOCK_COUNTER : integer := 2**3; -- XXX extreme fast
+-- constant C_CLOCK_COUNTER : integer := 2**2; -- XXX monster fast,not work
+
+end p_package;
+
+package body p_package is
+end p_package;
diff --git a/st7735r/p_rom_data.vhd b/st7735r/p_rom_data.vhd
new file mode 100755
index 0000000..d366b51
--- /dev/null
+++ b/st7735r/p_rom_data.vhd
@@ -0,0 +1,35 @@
+--
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+--
+-- To use any of the example code shown below, uncomment the lines and modify as necessary
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use WORK.p_package.ALL;
+
+package p_rom_data is
+
+ -- in bytes
+ -- 00 - NOP
+ -- 01 color -- initialize screen with fill color index
+ -- 02 color x1 y1 x2 y2 - draw [color] box on [x1,y1] with [x2,y2] dimension
+ constant COUNT_ROM_DATA : integer := 28;
+ type ARRAY_ROM_DATA is array(0 to COUNT_ROM_DATA - 1) of BYTE_TYPE;
+ constant C_ROM_DATA : ARRAY_ROM_DATA := (
+ x"00",
+ x"01",x"02",
+ x"02",x"04",x"10",x"10",x"1f",x"6f",
+ x"02",x"04",x"13",x"13",x"15",x"15",
+ x"02",x"04",x"16",x"16",x"18",x"18",
+ x"02",x"04",x"1a",x"1a",x"1c",x"1c",
+ x"00"
+ );
+
+end p_rom_data;
+
+package body p_rom_data is
+end p_rom_data;
diff --git a/st7735r/p_screen.vhd b/st7735r/p_screen.vhd
new file mode 100755
index 0000000..421fd6a
--- /dev/null
+++ b/st7735r/p_screen.vhd
@@ -0,0 +1,145 @@
+--
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+--
+-- To use any of the example code shown below, uncomment the lines and modify as necessary
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use WORK.p_package.ALL;
+
+package p_screen is
+
+ -- XXX based on https://github.com/Dungyichao/STM32F4-LCD_ST7735s/blob/master/ST7735/st7735.c
+ -- XXX based on https://github.com/Dungyichao/STM32F4-LCD_ST7735s/blob/master/ST7735/st7735.h
+
+ constant SCREEN_WIDTH : integer := 128;
+ constant SCREEN_HEIGHT : integer := 160;
+ constant SCREEN_FILL : integer := 2 * SCREEN_WIDTH * SCREEN_HEIGHT;
+
+ subtype COLOR_TYPE is std_logic_vector(15 downto 0);
+ constant SCREEN_BLACK : COLOR_TYPE := x"0000";
+ constant SCREEN_BLUE : COLOR_TYPE := x"001F";
+ constant SCREEN_RED : COLOR_TYPE := x"F800";
+ constant SCREEN_GREEN : COLOR_TYPE := x"07E0";
+ constant SCREEN_CYAN : COLOR_TYPE := x"07FF";
+ constant SCREEN_MAGENTA : COLOR_TYPE := x"F81F";
+ constant SCREEN_YELLOW : COLOR_TYPE := x"FFE0";
+ constant SCREEN_WHITE : COLOR_TYPE := x"FFFF";
+ constant SCREEN_ORANGE : COLOR_TYPE := x"FD60";
+ constant SCREEN_LIGHTGREEN : COLOR_TYPE := x"07EF";
+ constant SCREEN_LIGHTGREY : COLOR_TYPE := x"A514";
+ -- COLOR888_COLOR565(r, g, b) (((r & 0xF8) << 8) | ((g & 0xFC) << 3) | ((b & 0xF8) >> 3))
+
+ constant data_size_initscreen : integer := 83 * 2;
+ type data_array_initscreen is array(0 to data_size_initscreen - 1) of BYTE_TYPE;
+ constant data_rom_initscreen : data_array_initscreen := (
+ x"b1",x"01",--FRMCTR1
+ x"01",x"00",
+ x"2c",x"00",
+ x"2d",x"00",
+ x"b2",x"01",--FRMCTR2
+ x"01",x"00",
+ x"2c",x"00",
+ x"2d",x"00",
+ x"b3",x"01",--FRMCTR3
+ x"01",x"00",
+ x"2c",x"00",
+ x"2d",x"00",
+ x"01",x"00",
+ x"2c",x"00",
+ x"2d",x"00",
+ x"b4",x"01",--INVCTR
+ x"07",x"00",
+ x"c0",x"01",--PWCTR1
+ x"a2",x"00",
+ x"02",x"00",
+ x"84",x"00",
+ x"c1",x"01",--PWCTR2
+ x"c5",x"00",
+ x"c2",x"01",--PWCTR3
+ x"0a",x"00",
+ x"00",x"00",
+ x"c3",x"01",--PWCTR4
+ x"8a",x"00",
+ x"2a",x"00",
+ x"c4",x"01",--PWCTR5
+ x"8a",x"00",
+ x"ee",x"00",
+ x"c5",x"01",--VMCTR1
+ x"0e",x"00",
+ x"20",x"01",--INVOFF
+ x"36",x"01",--MADCTL
+ x"c0",x"00",--ROTATION (ST7735_MADCTL_MX | ST7735_MADCTL_MY) 0x40 | 0x80
+ x"3a",x"01",--COLMOD
+ x"05",x"00",
+ x"2a",x"01",--CASET
+ x"00",x"00",
+ x"00",x"00",
+ x"00",x"00",
+ x"7f",x"00",
+ x"2b",x"01",--RASET
+ x"00",x"00",
+ x"00",x"00",
+ x"00",x"00",
+ x"7f",x"00",
+ x"e0",x"01",--GMCTRP1
+ x"02",x"00",
+ x"1c",x"00",
+ x"07",x"00",
+ x"12",x"00",
+ x"37",x"00",
+ x"32",x"00",
+ x"29",x"00",
+ x"2d",x"00",
+ x"29",x"00",
+ x"25",x"00",
+ x"2b",x"00",
+ x"39",x"00",
+ x"00",x"00",
+ x"01",x"00",
+ x"03",x"00",
+ x"10",x"00",
+ x"e1",x"01",--GMCTRN1
+ x"03",x"00",
+ x"1d",x"00",
+ x"07",x"00",
+ x"06",x"00",
+ x"2e",x"00",
+ x"2c",x"00",
+ x"29",x"00",
+ x"2d",x"00",
+ x"2e",x"00",
+ x"2e",x"00",
+ x"37",x"00",
+ x"3f",x"00",
+ x"00",x"00",
+ x"00",x"00",
+ x"02",x"00",
+ x"10",x"00");
+
+ constant data_size_blackscreen : integer := 11 * 2;
+ type data_array_blackscreen is array(0 to data_size_blackscreen - 1) of BYTE_TYPE;
+ constant data_rom_blackscreen : data_array_blackscreen := (
+ -- XXX sequence for box 1px around
+ -- x"2a",x"01",x"00",x"00",x"01",x"00",x"00",x"00",x"7e",x"00",x"2b",x"01",x"00",x"00",x"01",x"00",x"00",x"00",x"9e",x"00",x"2c",x"01"
+ x"2a",x"01",--CASET
+ x"00",x"00",
+ x"00",x"00",
+ x"00",x"00",
+ x"7f",x"00",
+ x"2b",x"01",--RASET
+ x"00",x"00",
+ x"00",x"00",
+ x"00",x"00",
+ x"9f",x"00",
+ x"2c",x"01" --RAMWR
+ );
+
+end p_screen;
+
+package body p_screen is
+end p_screen;
diff --git a/st7735r/p_spi.vhd b/st7735r/p_spi.vhd
new file mode 100755
index 0000000..64848c5
--- /dev/null
+++ b/st7735r/p_spi.vhd
@@ -0,0 +1,85 @@
+--
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+--
+-- To use any of the example code shown below, uncomment the lines and modify as necessary
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package p_spi is
+
+ -- XXX for simulation
+-- shared variable data_rom_index : integer;
+-- constant R_EDGE : std_logic := '1';
+-- constant F_EDGE : std_logic := '0';
+-- shared variable data_temp : std_logic_vector(0 to BYTE_SIZE-1);
+-- shared variable data_temp_index : integer;
+-- constant Xs : std_logic_vector(0 to BYTE_SIZE - 1) := (others => 'U');
+
+-- function vec2str(vec: std_logic_vector) return string;
+--
+-- procedure check_test(
+-- signal cs : in std_logic;
+-- signal do : in std_logic;
+-- signal ck : in std_logic);
+
+end p_spi;
+
+package body p_spi is
+
+ -- XXX for simulation
+-- function vec2str(vec: std_logic_vector) return string is
+-- variable result: string(0 to vec'right);
+-- begin
+-- for i in vec'range loop
+-- if (vec(i) = '1') then
+-- result(i) := '1';
+-- elsif (vec(i) = '0') then
+-- result(i) := '0';
+-- elsif (vec(i) = 'X') then
+-- result(i) := 'X';
+-- elsif (vec(i) = 'U') then
+-- result(i) := 'U';
+-- else
+-- result(i) := '?';
+-- end if;
+-- end loop;
+-- return result;
+-- end;
+--
+ -- XXX for simulation
+-- procedure check_test(
+-- signal cs : in std_logic;
+-- signal do : in std_logic;
+-- signal ck : in std_logic
+-- ) is
+-- begin
+-- if ((ck'event and ck = R_EDGE) and cs = '0') then
+-- data_temp(data_temp_index) := do;
+-- if (data_temp_index = BYTE_SIZE - 1) then
+-- data_temp_index := 0;
+-- else
+-- data_temp_index := data_temp_index + 1;
+-- end if;
+-- elsif (cs'event and cs = R_EDGE) then
+-- assert (data_rom(data_rom_index) = data_temp)
+-- report "FAIL : (" & integer'image(data_rom_index) & ") " & vec2str(data_temp) & " expect " & vec2str(data_rom(data_rom_index)) severity note;
+-- assert (data_rom(data_rom_index) /= data_temp)
+-- report "OK : (" & integer'image(data_rom_index) & ") " & vec2str(data_temp) & " equals " & vec2str(data_rom(data_rom_index)) severity note;
+-- data_temp_index := 0;
+-- if (data_rom_index = data_size - 1) then
+-- data_rom_index := 0;
+-- assert (false) report "=== END TEST ===" severity note;
+-- else
+-- if (data_temp /= Xs) then -- XXX omit first undefined/uninitialized
+-- data_rom_index := data_rom_index + 1;
+-- end if;
+-- end if;
+-- end if;
+-- end procedure check_test;
+
+end p_spi;
diff --git a/st7735r/st7735r.xise b/st7735r/st7735r.xise
new file mode 100755
index 0000000..4858f76
--- /dev/null
+++ b/st7735r/st7735r.xise
@@ -0,0 +1,381 @@
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diff --git a/st7735r/tb_my_spi.vhd b/st7735r/tb_my_spi.vhd
new file mode 100755
index 0000000..1c888ad
--- /dev/null
+++ b/st7735r/tb_my_spi.vhd
@@ -0,0 +1,132 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:39:23 06/13/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/st7735r/tb_my_spi.vhd
+-- Project Name: st7735r
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: my_spi
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE WORK.p_package.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_my_spi IS
+END tb_my_spi;
+
+ARCHITECTURE behavior OF tb_my_spi IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT my_spi
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+i_enable : IN std_logic;
+i_data_byte : IN std_logic_vector(7 downto 0);
+o_cs : OUT std_logic;
+o_do : OUT std_logic;
+o_ck : INOUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+signal i_enable : std_logic := '0';
+signal i_data_byte : std_logic_vector(7 downto 0) := (others => '0');
+
+--Outputs
+signal o_cs : std_logic;
+signal o_do : std_logic;
+signal o_ck : std_logic;
+
+-- Clock period definitions
+constant i_clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: my_spi PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+i_enable => i_enable,
+i_data_byte => i_data_byte,
+o_cs => o_cs,
+o_do => o_do,
+o_ck => o_ck
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+
+i_reset <= '1';
+wait for i_clock_period*C_CLOCK_COUNTER;
+i_reset <= '0';
+wait for i_clock_period;
+
+-- insert stimulus here
+
+i_enable <= '1';
+i_data_byte <= x"AA";
+--wait for i_clock_period*(BYTE_SIZE+1)*C_CLOCK_COUNTER;
+wait for i_clock_period*BYTE_SIZE*C_CLOCK_COUNTER;
+i_enable <= '0';
+wait for i_clock_period*C_CLOCK_COUNTER*10;
+
+i_enable <= '1';
+i_data_byte <= x"55";
+--wait for i_clock_period*(BYTE_SIZE+1)*C_CLOCK_COUNTER;
+wait for i_clock_period*BYTE_SIZE*C_CLOCK_COUNTER;
+i_enable <= '0';
+wait for i_clock_period*C_CLOCK_COUNTER*10;
+
+i_enable <= '1';
+i_data_byte <= x"00";
+--wait for i_clock_period*(BYTE_SIZE+1)*C_CLOCK_COUNTER;
+wait for i_clock_period*BYTE_SIZE*C_CLOCK_COUNTER;
+i_enable <= '0';
+wait for i_clock_period*C_CLOCK_COUNTER*10;
+
+i_enable <= '1';
+i_data_byte <= x"FF";
+--wait for i_clock_period*(BYTE_SIZE+1)*C_CLOCK_COUNTER;
+wait for i_clock_period*BYTE_SIZE*C_CLOCK_COUNTER;
+i_enable <= '0';
+wait for i_clock_period*C_CLOCK_COUNTER*10;
+
+wait;
+end process;
+
+END;
diff --git a/st7735r/tb_top.vhd b/st7735r/tb_top.vhd
new file mode 100755
index 0000000..5b99b70
--- /dev/null
+++ b/st7735r/tb_top.vhd
@@ -0,0 +1,104 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:58:49 06/14/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/st7735r/tb_top.vhd
+-- Project Name: st7735r
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE work.p_package.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_top IS
+END tb_top;
+
+ARCHITECTURE behavior OF tb_top IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT top
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+o_cs : OUT std_logic;
+o_do : OUT std_logic;
+o_ck : OUT std_logic;
+o_reset : OUT std_logic;
+o_rs : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+
+--Outputs
+signal o_cs : std_logic;
+signal o_do : std_logic;
+signal o_ck : std_logic;
+signal o_reset : std_logic;
+signal o_rs : std_logic;
+
+-- Clock period definitions
+constant i_clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: top PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+o_cs => o_cs,
+o_do => o_do,
+o_ck => o_ck,
+o_reset => o_reset,
+o_rs => o_rs
+);
+
+-- Clock process definitions
+i_clock_process : process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc : process
+begin
+
+i_reset <= '1';
+wait for i_clock_period*C_CLOCK_COUNTER;
+i_reset <= '0';
+wait for i_clock_period*C_CLOCK_COUNTER;
+
+-- insert stimulus here
+
+wait;
+end process;
+
+END;
diff --git a/st7735r/top.vhd b/st7735r/top.vhd
new file mode 100755
index 0000000..d843d85
--- /dev/null
+++ b/st7735r/top.vhd
@@ -0,0 +1,334 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:59:41 06/21/2021
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_package.ALL;
+use WORK.p_screen.ALL;
+use WORK.p_rom_data.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top is
+Port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ o_cs : out std_logic;
+ o_do : out std_logic;
+ o_ck : out std_logic;
+ o_reset : out std_logic;
+ o_rs : out std_logic
+);
+end top;
+
+architecture Behavioral of top is
+
+ component my_spi is
+ port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_enable : in std_logic;
+ i_data_byte : in BYTE_TYPE;
+ o_cs : out std_logic;
+ o_do : out std_logic;
+ o_ck : out std_logic;
+ o_sended : out std_logic
+ );
+ end component my_spi;
+ signal spi_enable,spi_cs,spi_do,spi_ck,spi_sended : std_logic;
+ signal spi_data_byte : BYTE_TYPE;
+
+ component initialize is
+ port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_run : in std_logic;
+ i_color : in COLOR_TYPE;
+ i_sended : in std_logic;
+ o_initialized : out std_logic;
+ o_enable : out std_logic;
+ o_reset : out std_logic;
+ o_rs : out std_logic;
+ o_cs : out std_logic;
+ o_data_byte : out BYTE_TYPE
+ );
+ end component initialize;
+ signal initialize_run,initialize_sended : std_logic;
+ signal initialize_initialized,initialize_enable,initialize_reset,initialize_rs,initialize_cs : std_logic;
+ signal initialize_color : COLOR_TYPE;
+ signal initialize_data_byte : BYTE_TYPE;
+
+ component draw_box is
+ port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_run : in std_logic;
+ i_sended : in std_logic;
+ i_color : in COLOR_TYPE;
+ i_raxs : in BYTE_TYPE;
+ i_raxe : in BYTE_TYPE;
+ i_rays : in BYTE_TYPE;
+ i_raye : in BYTE_TYPE;
+ i_caxs : in BYTE_TYPE;
+ i_caxe : in BYTE_TYPE;
+ i_cays : in BYTE_TYPE;
+ i_caye : in BYTE_TYPE;
+ o_data : out BYTE_TYPE;
+ o_enable : out std_logic;
+ o_rs : out std_logic;
+ o_initialized : out std_logic
+ );
+ end component draw_box;
+ signal drawbox_sended,drawbox_enable,drawbox_rs,drawbox_run,drawbox_initialized : std_logic;
+ signal drawbox_raxs,drawbox_raxe,drawbox_rays,drawbox_raye,drawbox_caxs,drawbox_caxe,drawbox_cays,drawbox_caye : BYTE_TYPE;
+ signal drawbox_data : BYTE_TYPE;
+ signal drawbox_color : COLOR_TYPE;
+
+ type states is (
+ idle,
+ start,get_instruction,execute_instruction,
+ get_color,screen_initialize,screen_initialize_finish,
+ get_draw_box,
+ get_draw_box_c1,get_draw_box_c2,get_draw_box_c3,get_draw_box_c4,get_draw_box_c5,get_draw_box_c6,get_draw_box_c7,get_draw_box_c8,
+ get_draw_box_finish,
+ stop);
+ signal state : states;
+
+ signal index0 : integer range 0 to COUNT_ROM_DATA - 1;
+ signal byte_instruciton : BYTE_TYPE;
+
+begin
+
+ o_cs <= spi_cs; -- TODO use initialize_cs mux
+ o_do <= spi_do;
+ o_ck <= spi_ck;
+ o_reset <= initialize_reset when initialize_run = '1' else '1';
+ o_rs <= initialize_rs when initialize_run = '1' else drawbox_rs when drawbox_run = '1' else '1';
+
+ spi_data_byte <= initialize_data_byte when initialize_run = '1' else drawbox_data when drawbox_run = '1' else (others => '0');
+ spi_enable <= initialize_enable when initialize_run = '1' else drawbox_enable when drawbox_run = '1' else '0';
+ initialize_sended <= spi_sended when initialize_run = '1' else '0';
+ drawbox_sended <= spi_sended when drawbox_run = '1' else '0';
+
+ c0 : my_spi
+ port map (
+ i_clock => i_clock,
+ i_reset => i_reset,
+ i_enable => spi_enable,
+ i_data_byte => spi_data_byte,
+ o_cs => spi_cs,
+ o_do => spi_do,
+ o_ck => spi_ck,
+ o_sended => spi_sended
+ );
+
+ c1 : initialize
+ port map (
+ i_clock => i_clock,
+ i_reset => i_reset,
+ i_run => initialize_run,
+ i_color => initialize_color,
+ i_sended => initialize_sended,
+ o_initialized => initialize_initialized,
+ o_cs => initialize_cs,
+ o_reset => initialize_reset,
+ o_rs => initialize_rs,
+ o_enable => initialize_enable,
+ o_data_byte => initialize_data_byte
+ );
+
+ c2 : draw_box
+ port map (
+ i_clock => i_clock,
+ i_reset => i_reset,
+ i_run => drawbox_run,
+ i_sended => drawbox_sended,
+ i_color => drawbox_color,
+ i_raxs => drawbox_raxs,
+ i_raxe => drawbox_raxe,
+ i_rays => drawbox_rays,
+ i_raye => drawbox_raye,
+ i_caxs => drawbox_caxs,
+ i_caxe => drawbox_caxe,
+ i_cays => drawbox_cays,
+ i_caye => drawbox_caye,
+ o_data => drawbox_data,
+ o_enable => drawbox_enable,
+ o_rs => drawbox_rs,
+ o_initialized => drawbox_initialized
+ );
+
+ p1 : process (byte_instruciton,initialize_run,drawbox_run) is -- TODO use mux
+ begin
+ if (initialize_run = '1' or drawbox_run = '1') then
+ case (byte_instruciton) is
+ when x"00" =>
+ initialize_color <= SCREEN_BLACK;
+ drawbox_color <= SCREEN_BLACK;
+ when x"01" =>
+ initialize_color <= SCREEN_BLUE;
+ drawbox_color <= SCREEN_BLUE;
+ when x"02" =>
+ initialize_color <= SCREEN_RED;
+ drawbox_color <= SCREEN_RED;
+ when x"03" =>
+ initialize_color <= SCREEN_GREEN;
+ drawbox_color <= SCREEN_GREEN;
+ when x"04" =>
+ initialize_color <= SCREEN_CYAN;
+ drawbox_color <= SCREEN_CYAN;
+ when x"05" =>
+ initialize_color <= SCREEN_MAGENTA;
+ drawbox_color <= SCREEN_MAGENTA;
+ when x"06" =>
+ initialize_color <= SCREEN_YELLOW;
+ drawbox_color <= SCREEN_YELLOW;
+ when x"07" =>
+ initialize_color <= SCREEN_WHITE;
+ drawbox_color <= SCREEN_WHITE;
+ when x"08" =>
+ initialize_color <= SCREEN_ORANGE;
+ drawbox_color <= SCREEN_ORANGE;
+ when x"09" =>
+ initialize_color <= SCREEN_LIGHTGREEN;
+ drawbox_color <= SCREEN_LIGHTGREEN;
+ when x"0a" =>
+ initialize_color <= SCREEN_LIGHTGREY;
+ drawbox_color <= SCREEN_LIGHTGREY;
+ when others =>
+ initialize_color <= SCREEN_BLACK;
+ drawbox_color <= SCREEN_BLACK;
+ end case;
+ else
+ initialize_color <= SCREEN_BLACK;
+ drawbox_color <= SCREEN_BLACK;
+ end if;
+ end process p1;
+
+ p_control : process (i_clock,i_reset,initialize_initialized) is
+ begin
+ if (i_reset = '1') then
+ state <= idle;
+ elsif (rising_edge(i_clock)) then
+ case (state) is
+ when idle =>
+ state <= start;
+ byte_instruciton <= (others => '0');
+ initialize_run <= '0';
+ drawbox_run <= '0';
+ index0 <= 0;
+ drawbox_raxs <= (others => '0');
+ drawbox_raxe <= (others => '0');
+ drawbox_rays <= (others => '0');
+ drawbox_raye <= (others => '0');
+ drawbox_caxs <= (others => '0');
+ drawbox_caxe <= (others => '0');
+ drawbox_cays <= (others => '0');
+ drawbox_caye <= (others => '0');
+ when start =>
+ state <= get_instruction;
+ when get_instruction =>
+ state <= execute_instruction;
+ byte_instruciton <= C_ROM_DATA(index0);
+ index0 <= index0 + 1;
+ when execute_instruction =>
+ case (byte_instruciton) is
+ when x"00" =>
+ state <= get_instruction;
+ when x"01" =>
+ state <= get_color;
+ when x"02" =>
+ state <= get_draw_box;
+ when others => null;
+ end case;
+ when get_color =>
+ state <= screen_initialize;
+ byte_instruciton <= C_ROM_DATA(index0);
+ index0 <= index0 + 1;
+ initialize_run <= '1';
+ when screen_initialize =>
+ if (initialize_initialized = '1') then
+ state <= screen_initialize_finish;
+ initialize_run <= '0';
+ else
+ state <= screen_initialize;
+ end if;
+ when screen_initialize_finish =>
+ state <= start;
+ when get_draw_box =>
+ state <= get_draw_box_c1;
+ byte_instruciton <= C_ROM_DATA(index0);
+ index0 <= index0 + 1;
+ drawbox_run <= '1';
+ when get_draw_box_c1 =>
+ state <= get_draw_box_c2;
+ drawbox_raxs <= x"00";
+ when get_draw_box_c2 =>
+ state <= get_draw_box_c3;
+ drawbox_raxe <= C_ROM_DATA(index0);
+ index0 <= index0 + 1;
+ when get_draw_box_c3 =>
+ state <= get_draw_box_c4;
+ drawbox_rays <= x"00";
+ when get_draw_box_c4 =>
+ state <= get_draw_box_c5;
+ drawbox_raye <= C_ROM_DATA(index0);
+ index0 <= index0 + 1;
+ when get_draw_box_c5 =>
+ state <= get_draw_box_c6;
+ drawbox_caxs <= x"00";
+ when get_draw_box_c6 =>
+ state <= get_draw_box_c7;
+ drawbox_caxe <= C_ROM_DATA(index0);
+ index0 <= index0 + 1;
+ when get_draw_box_c7 =>
+ state <= get_draw_box_c8;
+ drawbox_cays <= x"00";
+ when get_draw_box_c8 =>
+ state <= get_draw_box_finish;
+ drawbox_caye <= C_ROM_DATA(index0);
+ index0 <= index0 + 1;
+ when get_draw_box_finish =>
+ if (drawbox_initialized = '1') then
+ state <= stop;
+ drawbox_run <= '0';
+ else
+ state <= get_draw_box_finish;
+ end if;
+ when stop =>
+ if (index0 = COUNT_ROM_DATA - 1) then
+ state <= stop;
+ else
+ state <= start;
+ end if;
+ when others =>
+ state <= idle;
+ end case;
+ end if;
+ end process p_control;
+
+end Behavioral;
+
diff --git a/top.vhd b/top.vhd
deleted file mode 100644
index 737efc6..0000000
--- a/top.vhd
+++ /dev/null
@@ -1,78 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 22:11:54 09/04/2020
--- Design Name:
--- Module Name: top - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use WORK.p_pkg1.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
-use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity top is
-port(
-signal clk : in std_logic;
-signal sda,scl : inout std_logic
-);
-end top;
-
-architecture Behavioral of top is
-
-component test_oled is
-port
-(
-signal i_clk : in std_logic;
-signal i_char : in array1;
-signal io_sda,io_scl : inout std_logic
-);
-end component test_oled;
-
-for all : test_oled use entity WORK.test_oled(Behavioral);
-
---signal font_character : std_logic_vector(11 downto 0) := (others => '0');
-signal font_character : array1(0 to 13-1);
---signal text : array1(0 to 13-1) := (x"4B",x"55",x"52",x"57",x"41",x"20",x"4D",x"41",x"43",x"20",x"3A",x"2D",x"29");
-signal text : array1(0 to 13-1) := ("000101110111","000110101001","000110011010","000110110011","000101000101","000010100000","000110000001","000101000101","000101001111","000010100000","000100100010","000011100001","000011001101");
-
-
-begin
-
-c0 : test_oled
-port map
-(
- i_clk => clk,
- i_char => font_character,
- io_sda => sda,
- io_scl => scl
-);
-
-p0 : process (clk) is
-begin
- if (rising_edge(clk)) then
- font_character <= text;
- end if;
-end process p0;
-
-end Behavioral;
-
diff --git a/vhdl_primitive/AND_N_GATE.vhd b/vhdl_primitive/AND_N_GATE.vhd
new file mode 100755
index 0000000..a1d7fa5
--- /dev/null
+++ b/vhdl_primitive/AND_N_GATE.vhd
@@ -0,0 +1,54 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:01:21 04/18/2021
+-- Design Name:
+-- Module Name: AND_N_GATE - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity AND_N_GATE is
+Generic (
+N : integer := 8
+);
+Port (
+input : in STD_LOGIC_VECTOR (N-1 downto 0);
+output : out STD_LOGIC
+);
+end AND_N_GATE;
+
+-- XXX https://stackoverflow.com/q/53161241
+architecture Behavioral of AND_N_GATE is
+begin
+ p0 : process (input)
+ begin
+ output <= '1';
+ for i in N-1 downto 0 loop
+ if input(i) = '0' then
+ output <= '0';
+ end if;
+ end loop;
+ end process p0;
+end Behavioral;
diff --git a/vhdl_primitive/CLKDIV_3.sch b/vhdl_primitive/CLKDIV_3.sch
new file mode 100644
index 0000000..8b4001f
--- /dev/null
+++ b/vhdl_primitive/CLKDIV_3.sch
@@ -0,0 +1,365 @@
+
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diff --git a/vhdl_primitive/CLKDIV_3_50.sch b/vhdl_primitive/CLKDIV_3_50.sch
new file mode 100644
index 0000000..9eb5073
--- /dev/null
+++ b/vhdl_primitive/CLKDIV_3_50.sch
@@ -0,0 +1,353 @@
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diff --git a/vhdl_primitive/CLKDIV_4dot5.sch b/vhdl_primitive/CLKDIV_4dot5.sch
new file mode 100644
index 0000000..bf66ae3
--- /dev/null
+++ b/vhdl_primitive/CLKDIV_4dot5.sch
@@ -0,0 +1,424 @@
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\ No newline at end of file
diff --git a/vhdl_primitive/DEMUX_12.vhd b/vhdl_primitive/DEMUX_12.vhd
new file mode 100755
index 0000000..e762d61
--- /dev/null
+++ b/vhdl_primitive/DEMUX_12.vhd
@@ -0,0 +1,29 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity DEMUX_12 is
+port (S,A:in STD_LOGIC;B,C:out STD_LOGIC);
+end entity DEMUX_12;
+
+architecture DEMUX_12_BEHAVIORAL_1 of DEMUX_12 is
+component GAND is
+generic (delay_and : time := 1 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GOR is
+generic (delay_or : time := 1 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GOR;
+component GN is
+generic (delay_not : time := 1 ns);
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_LUT);
+for all : GOR use entity WORK.GATE_OR(GATE_OR_LUT);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_LUT);
+signal sa : STD_LOGIC;
+begin
+g1: GN port map (S,sa);
+g3: GAND port map (A,S,B);
+g4: GAND port map (A,sa,C);
+end architecture DEMUX_12_BEHAVIORAL_1;
diff --git a/vhdl_primitive/DET_FF.sch b/vhdl_primitive/DET_FF.sch
new file mode 100644
index 0000000..2b32a70
--- /dev/null
+++ b/vhdl_primitive/DET_FF.sch
@@ -0,0 +1,282 @@
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\ No newline at end of file
diff --git a/vhdl_primitive/FA_COUNT_NUMBER_ONE.sch b/vhdl_primitive/FA_COUNT_NUMBER_ONE.sch
new file mode 100644
index 0000000..389c425
--- /dev/null
+++ b/vhdl_primitive/FA_COUNT_NUMBER_ONE.sch
@@ -0,0 +1,329 @@
+
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diff --git a/vhdl_primitive/FA_MUX41.sch b/vhdl_primitive/FA_MUX41.sch
new file mode 100644
index 0000000..9092804
--- /dev/null
+++ b/vhdl_primitive/FA_MUX41.sch
@@ -0,0 +1,180 @@
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\ No newline at end of file
diff --git a/vhdl_primitive/FDCPE_Q_QB.vhd b/vhdl_primitive/FDCPE_Q_QB.vhd
new file mode 100755
index 0000000..8c05fac
--- /dev/null
+++ b/vhdl_primitive/FDCPE_Q_QB.vhd
@@ -0,0 +1,56 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:23:05 04/18/2021
+-- Design Name:
+-- Module Name: FDCPE_Q_QB - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity FDCPE_Q_QB is
+Generic (
+ INIT : BIT := '0'
+);
+Port (
+ Q : out STD_LOGIC;
+ QB : out STD_LOGIC;
+ C : in STD_LOGIC;
+ CE : in STD_LOGIC;
+ CLR : in STD_LOGIC;
+ D : in STD_LOGIC;
+ PRE : in STD_LOGIC
+);
+end FDCPE_Q_QB;
+
+architecture Behavioral of FDCPE_Q_QB is
+ signal s_q : std_logic;
+begin
+ FDCPE_inst : FDCPE
+ generic map (INIT => INIT)
+ port map (Q=>s_q,C=>C,CE=>CE,CLR=>CLR,D=>D,PRE=>PRE);
+ Q <= s_q;
+ QB <= not s_q;
+end Behavioral;
+
diff --git a/vhdl_primitive/FF_D_DET.vhd b/vhdl_primitive/FF_D_DET.vhd
new file mode 100755
index 0000000..583321b
--- /dev/null
+++ b/vhdl_primitive/FF_D_DET.vhd
@@ -0,0 +1,28 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FF_D_DUAL_EDGE_TRIGGERED is
+port (D,C:in STD_LOGIC;Q:out STD_LOGIC);
+end entity FF_D_DUAL_EDGE_TRIGGERED;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Dual-edge-triggered_D_flip-flop
+architecture Behavioral_D_DET of FF_D_DUAL_EDGE_TRIGGERED is
+component FF_D_PE is
+port (C,D:in STD_LOGIC;Q1,Q2:inout STD_LOGIC);
+end component FF_D_PE;
+component MUX_21 is
+port (S,A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component MUX_21;
+component GN is
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : FF_D_PE use entity WORK.FF_D_POSITIVE_EDGE(Behavioral_D_PE);
+for all : MUX_21 use entity WORK.MUX_21(MUX_21_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc: STD_LOGIC;
+begin
+g1: GN port map (C,sa);
+g2: FF_D_PE port map (sa,D,sb,open);
+g3: FF_D_PE port map (C,D,sc,open);
+g4: MUX_21 port map (C,sb,sc,Q);
+end architecture Behavioral_D_DET;
diff --git a/vhdl_primitive/FF_D_GATED.vhd b/vhdl_primitive/FF_D_GATED.vhd
new file mode 100755
index 0000000..3cbed4a
--- /dev/null
+++ b/vhdl_primitive/FF_D_GATED.vhd
@@ -0,0 +1,82 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FF_D_GATED is
+generic (
+delay_and : TIME := 1 ns;
+delay_or : TIME := 1 ns;
+delay_not : TIME := 1 ns
+);
+port (
+D,E : in STD_LOGIC;
+Q1,Q2 : inout STD_LOGIC
+);
+end entity FF_D_GATED;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Gated_D_latch
+architecture Behavioral_GATED_D_NAND of FF_D_GATED is
+component GAND is
+generic (delay_and : TIME);
+port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+end component GAND;
+component GN is
+generic (delay_not : TIME);
+port (A : in STD_LOGIC; B : out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc,sd,se,sf,sg,sh:STD_LOGIC;
+begin
+g1: GAND generic map (delay_and) port map (sh,E,sa);
+g2: GN generic map (delay_not) port map (sa,sb);
+g3: GAND generic map (delay_and) port map (E,sb,sc);
+g4: GN generic map (delay_not) port map (sc,sd);
+g5: GAND generic map (delay_and) port map (sb,Q2,sg);
+g6: GN generic map (delay_not) port map (sg,Q1);
+g7: GAND generic map (delay_and) port map (sd,Q1,se);
+g8: GN generic map (delay_not) port map (se,Q2);
+
+p0 : process (E,D) is
+begin
+ if (rising_edge(E)) then
+ sh <= D;
+ end if;
+end process p0;
+
+end architecture Behavioral_GATED_D_NAND;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Gated_D_latch
+architecture Behavioral_GATED_D_NOR of FF_D_GATED is
+component GAND is
+generic (delay_and : TIME);
+port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+end component GAND;
+component GOR is
+generic (delay_or : TIME);
+port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+end component GOR;
+component GN is
+generic (delay_not : TIME);
+port (A : in STD_LOGIC; B : out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc,sd,se,sf,sg,sh:STD_LOGIC;
+begin
+g1: GN generic map (delay_not) port map (sh,sa);
+g2: GAND generic map (delay_and) port map (sa,E,sb);
+g3: GAND generic map (delay_and) port map (sh,E,sc);
+g4: GOR generic map (delay_or) port map (sb,Q2,sg);
+g5: GN generic map (delay_not) port map (sg,Q1);
+g6: GOR generic map (delay_or) port map (sc,Q1,se);
+g7: GN generic map (delay_not) port map (se,Q2);
+
+p0 : process (E,D) is
+begin
+ if (rising_edge(E)) then
+ sh <= D;
+ end if;
+end process p0;
+
+end architecture Behavioral_GATED_D_NOR;
diff --git a/vhdl_primitive/FF_D_MS.vhd b/vhdl_primitive/FF_D_MS.vhd
new file mode 100755
index 0000000..6b3268a
--- /dev/null
+++ b/vhdl_primitive/FF_D_MS.vhd
@@ -0,0 +1,30 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FF_D_MASTER_SLAVE is
+port (C,D:in STD_LOGIC;Q1,Q2:inout STD_LOGIC);
+end entity FF_D_MASTER_SLAVE;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Master%E2%80%93slave_edge-triggered_D_flip-flop
+architecture Behavioral_D_MS of FF_D_MASTER_SLAVE is
+component GAND is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GN is
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal X,Y,Z,U,V,W,O,P,sa,sb,sc,sd,se,sf,sg,sh:STD_LOGIC;
+begin
+g1: GN port map (C,X);
+g2: GAND port map (D,X,sa); g3: GN port map(sa,Y);
+g4: GN port map (X,U);
+g5: GAND port map (X,Y,sb); g6: GN port map(sb,V);
+g7: GAND port map (Y,W,sc); g8: GN port map(sc,Z);
+g9: GAND port map (V,Z,sd); g10: GN port map(sd,W);
+g11: GAND port map (Z,U,se); g12: GN port map(se,O);
+g13: GAND port map (O,U,sf); g14: GN port map(sf,P);
+g15: GAND port map (O,Q2,sg); g16: GN port map(sg,Q1);
+g17: GAND port map (P,Q1,sh); g18: GN port map(sh,Q2);
+end architecture Behavioral_D_MS;
diff --git a/vhdl_primitive/FF_D_PE.vhd b/vhdl_primitive/FF_D_PE.vhd
new file mode 100755
index 0000000..b91b744
--- /dev/null
+++ b/vhdl_primitive/FF_D_PE.vhd
@@ -0,0 +1,60 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FF_D_POSITIVE_EDGE is
+port (
+S : in std_logic;
+R : in std_logic;
+C : in std_logic;
+D : in STD_LOGIC;
+Q1,Q2:inout STD_LOGIC);
+end entity FF_D_POSITIVE_EDGE;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Classical_positive-edge-triggered_D_flip-flop
+architecture Behavioral_D_PE of FF_D_POSITIVE_EDGE is
+
+--component GAND is
+--generic (delay_and:time := 0 ns);
+--port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+--end component GAND;
+--component GN is
+--generic (delay_not:time := 0 ns);
+--port (A:in STD_LOGIC;B:out STD_LOGIC);
+--end component GN;
+--for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+--for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+--signal X,Y,Z,V,W,O,sa,sb,sc,sd,se,sf:STD_LOGIC;
+--constant DELAY_AND : time := 1 ps;
+--constant DELAY_NOT : time := 1 ps;
+
+constant WAIT_NAND3 : time := 0 ps;
+signal setu,setd,resetu,resetd : std_logic;
+
+begin
+
+--rst1 <= D when i_reset = '0' else '0';
+--g1: GAND generic map (DELAY_AND) port map (rst1,X,sa);
+--g2: GN generic map (DELAY_NOT) port map(sa,Y);
+--g3: GAND generic map (DELAY_AND) port map (Y,O,sb);
+--g4: GN generic map (DELAY_NOT) port map(sb,X);
+--rst2 <= C when i_reset = '0' else '0';
+--g5: GAND generic map (DELAY_AND) port map (rst2,V,sc);
+--g6: GN generic map (DELAY_NOT) port map(sc,Z);
+--g7: GAND generic map (DELAY_AND) port map (Z,Y,sd);
+--g8: GN generic map (DELAY_NOT) port map(sd,V);
+--rst3 <= Q2 when i_reset = '0' else '0';
+--g9: GAND generic map (DELAY_AND) port map (Z,rst3,se);
+--gA: GN generic map (DELAY_NOT) port map(se,Q1);
+--gB: GAND generic map (DELAY_AND) port map (X,Q1,sf);
+--gC: GN generic map (DELAY_NOT) port map(sf,Q2);
+--gD: GAND generic map (DELAY_AND) port map (C,Z,O);
+
+-- https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29#/media/File:Edge_triggered_D_flip_flop_with_set_and_reset.svg
+g1 : Q1 <= not (S and setd and Q2) after 0 ps;
+g2 : Q2 <= not (Q1 and resetu and R) after 1 ps;
+g3 : setu <= not (S and resetd and setd) after 0 ps;
+g4 : setd <= not (setu and C and R) after 1 ps;
+g5 : resetu <= not (setd and C and resetd) after 0 ps;
+g6 : resetd <= not (resetu and D and R) after 0 ps;
+
+end architecture Behavioral_D_PE;
diff --git a/vhdl_primitive/FF_E_LATCH.vhd b/vhdl_primitive/FF_E_LATCH.vhd
new file mode 100755
index 0000000..9b5ea93
--- /dev/null
+++ b/vhdl_primitive/FF_E_LATCH.vhd
@@ -0,0 +1,29 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FF_E_LATCH is
+port (D,E_H,E_L:in STD_LOGIC;Q:inout STD_LOGIC);
+end entity FF_E_LATCH;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Earle_latch
+architecture Behavioral_E_LATCH of FF_E_LATCH is
+component GAND is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GN is
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc,sd,se,sf,sg,sh,si:STD_LOGIC;
+begin
+g1: GAND port map (E_H,D,sa);
+g2: GN port map (sa,sb);
+g3: GAND port map (D,Q,sc);
+g4: GN port map (sc,sd);
+g5: GAND port map (Q,E_L,se);
+g6: GN port map (se,sf);
+g7: GAND port map (sb,sd,sg);
+g8: GAND port map (sf,sg,sh);
+g9: GN port map (sh,Q);
+end architecture Behavioral_E_LATCH;
diff --git a/vhdl_primitive/FF_JK.vhd b/vhdl_primitive/FF_JK.vhd
new file mode 100755
index 0000000..094a5ef
--- /dev/null
+++ b/vhdl_primitive/FF_JK.vhd
@@ -0,0 +1,209 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FF_JK is
+port (
+ i_r : in STD_LOGIC;
+ J,K,C : in STD_LOGIC;
+ Q1 : inout STD_LOGIC;
+ Q2 : inout STD_LOGIC
+);
+end entity FF_JK;
+
+architecture structural of FF_JK is
+ constant W_NAND2 : time := 1 ps;
+ constant W_NAND3 : time := 2 ps;
+ constant W_Q1MS : time := 10 ps;
+ constant W_Q2MS : time := 1 ps;
+ constant W_C : time := 0 ns;
+ constant W_NOTC : time := 0 ns;
+ constant W_J : time := 0 ns;
+ constant W_K : time := 0 ns;
+
+ signal sa,sb,sc,sd : std_logic := '0';
+ signal se,sg : std_logic := '0';
+ signal sh,sj : std_logic := '0';
+ signal sk,sn : std_logic := '0';
+ signal so,sp : std_logic := '0';
+ signal sr,ss : std_logic := '0';
+ signal st,su : std_logic := '0';
+ signal sw,sx : std_logic := '0';
+ signal sy,sz : std_logic := '0';
+begin
+
+ sa <= C after W_C;
+ sb <= not C after W_NOTC;
+ sc <= j after W_J;
+ sd <= k after W_K;
+
+ -- nand3 1u
+ se <= not (sa and sc and q2 and not i_r);
+ sg <= se after W_NAND3;
+
+ -- nand3 1d
+ sh <= not (sa and sd and q1);
+ sj <= sh after W_NAND3;
+
+ -- nand2 1u
+ sk <= sg nand sp;
+ sn <= sk after W_NAND2;
+
+ -- nand2 1d
+ so <= not (sj and sn and not i_r);
+ sp <= so after W_NAND2;
+
+ -- nand2 1u
+ sr <= sn nand sb;
+ ss <= sr after W_NAND2;
+
+ -- nand2 1d
+ st <= sp nand sb;
+ su <= st after W_NAND2;
+
+ -- nand2 q1
+ sw <= ss nand q2;
+ sx <= sw after W_NAND2;
+
+ -- nand2 q2
+ sy <= su nand q1;
+ sz <= sy after W_NAND2;
+
+ q1 <= sx and not i_r after W_Q1MS; -- XXX metastable
+ q2 <= sz after W_Q2MS;
+
+end architecture Structural;
+
+---- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#JK_flip-flop
+---- XXX strange operation
+--architecture Behavioral_FF_JK of FF_JK is
+--component GAND is
+--port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+--end component GAND;
+--component FF_SR_NOR is
+--port (S,R:in STD_LOGIC;Q1,Q2:inout STD_LOGIC);
+--end component FF_SR_NOR;
+----component GNOT is
+----generic (delay_not : TIME := 0 ns);
+----port (A:in STD_LOGIC;B:out STD_LOGIC);
+----end component GNOT;
+----for all : GNOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+--for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+--for all : FF_SR_NOR use entity WORK.FF_SR(Behavioral_NOR);
+----for all : FF_SR_NOR use entity WORK.FF_SR(Behavioral_NAND);
+----for all : FF_SR_NOR use entity WORK.FF_SR(Behavioral_ANDOR);
+----for all : FF_SR_NOR use entity WORK.FF_SR(Behavioral_NOT_S_NOT_R);
+--signal sa,sb,sc,sd: STD_LOGIC;
+----signal n1,n2 : STD_LOGIC;
+--begin
+--g1: GAND port map (K,C,sa);
+--g2: GAND port map (sa,Q1,sb);
+----gn1 : GNOT port map (sb,n1);
+--g3: GAND port map (C,J,sc);
+--g4: GAND port map (sc,Q2,sd);
+----gn2 : GNOT port map (sd,n2);
+--g5: FF_SR_NOR port map (sb,sd,Q1,Q2);
+--end architecture Behavioral_FF_JK;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#JK_flip-flop
+--architecture Structural of FF_JK is
+--component GAND is port (A,B:in STD_LOGIC;C:out STD_LOGIC); end component GAND;
+--component GOR is port (A,B:in STD_LOGIC;C:out STD_LOGIC); end component GOR;
+--component GNOT is port (A:in STD_LOGIC;B:out STD_LOGIC); end component GNOT;
+--for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+--for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+--for all : GNOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+--signal sa,sb,sc,sd,se,sf,sg,sh,si,sj : std_logic;
+--begin
+--g1 : GAND port map (J,C,sa);
+--g2 : GAND port map (K,C,sb);
+--
+--g3 : GAND port map (sa,Q2,sc);
+--
+--g4 : GNOT port map (sb,sd);
+--g5 : GAND port map (sd,Q1,se);
+--
+--g6 : GOR port map (sc,se,sf);
+--g7 : GNOT port map (sf,sg);
+--Q1 <= sf;
+--Q2 <= sg;
+--end architecture Structural;
+
+--architecture Structural of FF_JK is
+----component GAND is port (A,B:in STD_LOGIC;C:out STD_LOGIC); end component GAND;
+----component GOR is port (A,B:in STD_LOGIC;C:out STD_LOGIC); end component GOR;
+----component GNOT is port (A:in STD_LOGIC;B:out STD_LOGIC); end component GNOT;
+----for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+----for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+----for all : GNOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+--signal sa,sb,sc,sd,se,sf,sg,sh,si,sj : std_logic := '0';
+--constant clock_period : time := 1 ns;
+--begin
+--g1 : sa <= J and C;
+--sb <= sa and Q2 after clock_period;
+--
+--g2 : sc <= K and C;
+--sd <= sc and Q1 after clock_period;
+--
+--g3 : se <= sb nor Q2 after clock_period;
+--
+--g4 : sf <= sd nor Q1 after clock_period;
+--
+--Q1 <= se;
+--Q2 <= sf;
+--end architecture Structural;
+
+
+
+-- p0 : process (C,j,k,q1,q2) is
+-- variable sa,sb,sc,sd : std_logic;
+-- variable se,sf,sg : std_logic;
+-- variable sh,si,sj : std_logic;
+-- variable sk,sn : std_logic;
+-- variable so,sp : std_logic := '0';
+-- variable sr,ss : std_logic := '0';
+-- variable st,su : std_logic;
+-- variable sw,sx : std_logic;
+-- variable sy,sz : std_logic;
+-- begin
+-- sa := C;
+-- sb := not C;
+-- sc := j;
+-- sd := k;
+--
+-- -- nand3 1u
+-- se := sa and sc;
+-- sf := se and q2;
+-- sg := not sf;
+--
+-- -- nand3 1d
+-- sh := sa and sd;
+-- si := sh and q1;
+-- sj := not si;
+--
+-- -- nand2 1u
+-- sk := sg and sp;
+-- sn := not sk;
+--
+-- -- nand2 1d
+-- so := sj and sn;
+-- sp := not so;
+--
+-- -- nand2 1u
+-- sr := sn and sb;
+-- ss := not sr;
+--
+-- -- nand2 1d
+-- st := sp and sb;
+-- su := not st;
+--
+-- -- nand2 q1
+-- sw := ss and q2;
+-- sx := not sw;
+--
+-- -- nand2 q2
+-- sy := su and q1;
+-- sz := not sy;
+--
+-- q1 <= sx;
+-- q2 <= sy;
+-- end process p0;
diff --git a/vhdl_primitive/FF_SR.vhd b/vhdl_primitive/FF_SR.vhd
new file mode 100755
index 0000000..5674cc3
--- /dev/null
+++ b/vhdl_primitive/FF_SR.vhd
@@ -0,0 +1,83 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.all;
+
+entity FF_SR is
+port (S,R:in STD_LOGIC;Q1,Q2:inout STD_LOGIC);
+end entity FF_SR;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#SR_NOR_latch
+architecture Behavioral_NOR of FF_SR is
+component GOR is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GOR;
+component GN is
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal a,b,c,d,e,f,g:STD_LOGIC;
+begin
+g1: GOR port map (S,Q2,g);
+g2: GN port map (g,Q1);
+g3: GOR port map (R,Q1,e);
+g4: GN port map (e,Q2);
+end architecture Behavioral_NOR;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#SR_NAND_latch
+architecture Behavioral_NAND of FF_SR is
+component GAND is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GN is
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal a,b,c,d,e,f,g:STD_LOGIC;
+begin
+g1: GAND port map (S,Q2,g);
+g2: GN port map (g,Q1);
+g3: GAND port map (R,Q1,e);
+g4: GN port map (e,Q2);
+end architecture Behavioral_NAND;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#SR_AND-OR_latch
+architecture Behavioral_ANDOR of FF_SR is
+component GAND is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GOR is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GOR;
+component GN is
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal a,b,c,d,e,f,g:STD_LOGIC;
+begin
+g1: GN port map (R,b);
+g2: GOR port map (S,Q1,a);
+g3: GAND port map (b,a,Q1);
+end architecture Behavioral_ANDOR;
+
+architecture Behavioral_NOT_S_NOT_R of FF_SR is
+component GOR is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GOR;
+component GN is
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal a,b,c,d,e,f,g:STD_LOGIC;
+begin
+g1: GN port map (S,a);
+g2: GN port map (R,b);
+g3: GOR port map (a,d,Q1);
+g4: GN port map (Q1,c);
+g5: GOR port map (b,c,Q2);
+g6: GN port map (Q2,d);
+end architecture Behavioral_NOT_S_NOT_R;
diff --git a/vhdl_primitive/FF_SR_GATED.vhd b/vhdl_primitive/FF_SR_GATED.vhd
new file mode 100755
index 0000000..004083e
--- /dev/null
+++ b/vhdl_primitive/FF_SR_GATED.vhd
@@ -0,0 +1,52 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FF_SR_GATED is
+port (S,R,E:in STD_LOGIC;Q1,Q2:inout STD_LOGIC);
+end entity FF_SR_GATED;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Gated_SR_latch
+architecture Behavioral_GATED_SR_1 of FF_SR_GATED is
+component GAND is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GN is
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc,sd,se,sf,sg:STD_LOGIC;
+begin
+g1: GAND port map (S,E,sa);
+g2: GN port map (sa,sb);
+g3: GAND port map (R,E,sc);
+g4: GN port map (sc,sd);
+g5: GAND port map (sb,Q2,sg);
+g6: GN port map (sg,Q1);
+g7: GAND port map (sd,Q1,se);
+g8: GN port map (se,Q2);
+end architecture Behavioral_GATED_SR_1;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Gated_SR_latch
+architecture Behavioral_GATED_SR_2 of FF_SR_GATED is
+component GAND is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GOR is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GOR;
+component GN is
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc,sd,se,sf,sg:STD_LOGIC;
+begin
+g1: GAND port map (S,E,sa);
+g3: GAND port map (R,E,sb);
+g5: GOR port map (sa,Q2,sg);
+g6: GN port map (sg,Q1);
+g7: GOR port map (sb,Q1,se);
+g8: GN port map (se,Q2);
+end architecture Behavioral_GATED_SR_2;
diff --git a/vhdl_primitive/FULL_ADDER.vhd b/vhdl_primitive/FULL_ADDER.vhd
new file mode 100755
index 0000000..197080b
--- /dev/null
+++ b/vhdl_primitive/FULL_ADDER.vhd
@@ -0,0 +1,22 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FULL_ADDER is
+port (A,B,Cin:in STD_LOGIC;S,Cout:out STD_LOGIC);
+end entity FULL_ADDER;
+
+architecture FULL_ADDER_BEHAVIORAL_1 of FULL_ADDER is
+component HA is
+port (A,B:in STD_LOGIC;S,C:out STD_LOGIC);
+end component HA;
+component GOR is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GOR;
+for all : HA use entity WORK.HALF_ADDER(HALF_ADDER_BEHAVIORAL_1);
+for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+signal sa,sb,sc: STD_LOGIC;
+begin
+g1 : HA port map (A,B,sa,sb);
+g2 : HA port map (sa,Cin,S,sc);
+g3 : GOR port map (sb,sc,Cout);
+end architecture FULL_ADDER_BEHAVIORAL_1;
diff --git a/vhdl_primitive/HALF_ADDER.vhd b/vhdl_primitive/HALF_ADDER.vhd
new file mode 100755
index 0000000..df8d7cb
--- /dev/null
+++ b/vhdl_primitive/HALF_ADDER.vhd
@@ -0,0 +1,20 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity HALF_ADDER is
+port (A,B:in STD_LOGIC;S,C:out STD_LOGIC);
+end entity HALF_ADDER;
+
+architecture HALF_ADDER_BEHAVIORAL_1 of HALF_ADDER is
+component GXOR is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GXOR;
+component GAND is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+for all : GXOR use entity WORK.GATE_XOR(GATE_XOR_BEHAVIORAL_1);
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+begin
+g1 : GXOR port map (A,B,S);
+g2 : GAND port map (A,B,C);
+end architecture HALF_ADDER_BEHAVIORAL_1;
diff --git a/vhdl_primitive/HANDSHAKE_BASED_PULSE_SYNCHRONIZER.sch b/vhdl_primitive/HANDSHAKE_BASED_PULSE_SYNCHRONIZER.sch
new file mode 100644
index 0000000..8561ca6
--- /dev/null
+++ b/vhdl_primitive/HANDSHAKE_BASED_PULSE_SYNCHRONIZER.sch
@@ -0,0 +1,445 @@
+
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\ No newline at end of file
diff --git a/vhdl_primitive/MUX_21.vhd b/vhdl_primitive/MUX_21.vhd
new file mode 100755
index 0000000..513c38b
--- /dev/null
+++ b/vhdl_primitive/MUX_21.vhd
@@ -0,0 +1,30 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity MUX_21 is
+port (S,A,B:in STD_LOGIC;C:out STD_LOGIC);
+end entity MUX_21;
+
+architecture MUX_21_BEHAVIORAL_1 of MUX_21 is
+component GAND is
+generic (delay_and : time := 1 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GOR is
+generic (delay_or : time := 1 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GOR;
+component GN is
+generic (delay_not : time := 1 ns);
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_LUT);
+for all : GOR use entity WORK.GATE_OR(GATE_OR_LUT);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_LUT);
+signal sa,sb,sc : STD_LOGIC;
+begin
+g1: GN port map (S,sa);
+g3: GAND port map (A,S,sb);
+g4: GAND port map (B,sa,sc);
+g5: GOR port map (sb,sc,C);
+end architecture MUX_21_BEHAVIORAL_1;
diff --git a/vhdl_primitive/MUX_SYNCHRONIZER.sch b/vhdl_primitive/MUX_SYNCHRONIZER.sch
new file mode 100644
index 0000000..ca7d83e
--- /dev/null
+++ b/vhdl_primitive/MUX_SYNCHRONIZER.sch
@@ -0,0 +1,281 @@
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\ No newline at end of file
diff --git a/vhdl_primitive/OR_N_GATE.vhd b/vhdl_primitive/OR_N_GATE.vhd
new file mode 100755
index 0000000..31134bb
--- /dev/null
+++ b/vhdl_primitive/OR_N_GATE.vhd
@@ -0,0 +1,56 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:14:20 04/18/2021
+-- Design Name:
+-- Module Name: OR_N_GATE - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity OR_N_GATE is
+Generic (
+N : integer := 8
+);
+Port (
+input : in STD_LOGIC_VECTOR (N-1 downto 0);
+output : out STD_LOGIC
+);
+end OR_N_GATE;
+
+-- XXX https://stackoverflow.com/q/53161241
+architecture Behavioral of OR_N_GATE is
+
+begin
+ p0 : process (input)
+ begin
+ output <= '0';
+ for i in N-1 downto 0 loop
+ if input(i) = '1' then
+ output <= '1';
+ end if;
+ end loop;
+ end process p0;
+end Behavioral;
+
diff --git a/vhdl_primitive/PWM_generator.sym b/vhdl_primitive/PWM_generator.sym
new file mode 100644
index 0000000..20c3a0f
--- /dev/null
+++ b/vhdl_primitive/PWM_generator.sym
@@ -0,0 +1,22 @@
+
+
+ BLOCK
+ 2021-4-18T18:44:57
+
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+
+
+
+
+
+
+
+
+
+
diff --git a/vhdl_primitive/PWM_generator.vhd b/vhdl_primitive/PWM_generator.vhd
new file mode 100755
index 0000000..aa3a7b0
--- /dev/null
+++ b/vhdl_primitive/PWM_generator.vhd
@@ -0,0 +1,185 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:57:51 04/18/2021
+-- Design Name:
+-- Module Name: PWM_generator - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity PWM_generator is
+Generic (
+N : integer := 4
+);
+Port (
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_data : in std_logic_vector(N-1 downto 0);
+o_pwm : out std_logic
+);
+end PWM_generator;
+
+architecture Behavioral of PWM_generator is
+
+ COMPONENT counter_n IS
+ Generic (
+ N : integer
+ );
+ Port (
+ i_clock : in STD_LOGIC;
+ i_reset : in STD_LOGIC;
+ o_count : out STD_LOGIC_VECTOR (N-1 downto 0)
+ );
+ END COMPONENT counter_n;
+
+ COMPONENT FTRSE IS
+ GENERIC (
+ INIT : bit := '0'
+ );
+ PORT (
+ Q : out STD_LOGIC;
+ C : in STD_LOGIC;
+ CE : in STD_LOGIC;
+ R : in STD_LOGIC;
+ S : in STD_LOGIC;
+ T : in STD_LOGIC
+ );
+ END COMPONENT FTRSE;
+
+ COMPONENT x3_nand_x1_nor IS
+ PORT (
+ A : in STD_LOGIC;
+ B : in STD_LOGIC;
+ Q : out STD_LOGIC
+ );
+ END COMPONENT x3_nand_x1_nor;
+
+ COMPONENT OR_N_GATE IS
+ Generic (
+ N : integer
+ );
+ Port (
+ input : in STD_LOGIC_VECTOR (N-1 downto 0);
+ output : out STD_LOGIC
+ );
+ END COMPONENT OR_N_GATE;
+
+ COMPONENT AND_N_GATE IS
+ Generic (
+ N : integer
+ );
+ Port (
+ input : in STD_LOGIC_VECTOR (N-1 downto 0);
+ output : out STD_LOGIC
+ );
+ END COMPONENT AND_N_GATE;
+
+ COMPONENT FDCPE_Q_QB IS
+ Generic (
+ INIT : BIT := '0'
+ );
+ Port (
+ Q : out STD_LOGIC;
+ QB : out STD_LOGIC;
+ C : in STD_LOGIC;
+ CE : in STD_LOGIC;
+ CLR : in STD_LOGIC;
+ D : in STD_LOGIC;
+ PRE : in STD_LOGIC
+ );
+ END COMPONENT FDCPE_Q_QB;
+
+ signal pull_up : std_logic;
+
+ signal counter_output : std_logic_vector(N-1 downto 0);
+ signal c_enable : std_logic := '1';
+
+ signal or_n_input : std_logic_vector(N-1 downto 0);
+ signal or_n_output : std_logic;
+ signal and_n_input : std_logic_vector(N-1 downto 0);
+ signal and_n_output : std_logic;
+
+ signal q_data_input : std_logic_vector(N-1 downto 0);
+ signal data_input_clock,pwm_out_clear : std_logic;
+
+begin
+
+PULLUP_inst : PULLUP
+ port map (O=>pull_up);
+
+data_input_FDCPE_generate : for i in N-1 downto 0 generate
+ FDCPE_inst : FDCPE
+ generic map (INIT => '0')
+ port map (Q=>q_data_input(i),C=>data_input_clock,CE=>c_enable,CLR=>not pull_up,D=>i_data(i),PRE=>not pull_up);
+end generate data_input_FDCPE_generate;
+
+counter_entity : counter_n
+Generic map (
+ N => N
+)
+Port map (
+ i_clock => i_clock,
+ i_reset => i_reset,
+ o_count => counter_output
+);
+
+x3_nand_x1_nor_generate : for i in N-1 downto 0 generate
+ x3_nand_x1_nor_inst : x3_nand_x1_nor
+ PORT MAP (
+ A => q_data_input(i),
+ B => counter_output(i),
+ Q => or_n_input(i)
+ );
+end generate x3_nand_x1_nor_generate;
+
+OR_N_GATE_entity : OR_N_GATE
+Generic map (
+ N => N
+)
+Port map (
+ input => or_n_input,
+ output => or_n_output
+);
+
+and_n_input <= counter_output;
+AND_N_GATE_entity : AND_N_GATE
+Generic map (
+ N => N
+)
+Port map (
+ input => and_n_input,
+ output => and_n_output
+);
+
+FDCPE_Q_QB_clock : FDCPE_Q_QB
+generic map (INIT => '0')
+port map (Q=>data_input_clock,QB=>pwm_out_clear,C=>i_clock,CE=>c_enable,CLR=>i_reset,D=>and_n_output,PRE=>'0');
+
+FDCPE_pwm : FDCPE
+generic map (INIT => '1')
+port map (Q=>o_pwm,C=>not or_n_output,CE=>c_enable,CLR=>not pwm_out_clear,D=>pull_up,PRE=>not pull_up);
+
+end Behavioral;
+
diff --git a/vhdl_primitive/TB_FF_D_GATED.vhd b/vhdl_primitive/TB_FF_D_GATED.vhd
new file mode 100755
index 0000000..335d623
--- /dev/null
+++ b/vhdl_primitive/TB_FF_D_GATED.vhd
@@ -0,0 +1,160 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 01:54:46 08/10/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl/TB_FF_D_GATED.vhd
+-- Project Name: vhdl
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: FF_D_GATED
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY TB_FF_D_GATED IS
+END TB_FF_D_GATED;
+
+ARCHITECTURE behavior OF TB_FF_D_GATED IS
+
+ procedure clk_gen(signal clk : out std_logic; constant wait_start : time; constant HT : time; constant LT : time) is
+ begin
+ clk <= '0';
+ wait for wait_start;
+ loop
+ clk <= '1';
+ wait for HT;
+ clk <= '0';
+ wait for LT;
+ end loop;
+ end procedure;
+
+ COMPONENT FF_D_GATED_NAND
+ GENERIC(
+ DELAY_AND : TIME;
+ DELAY_OR : TIME;
+ DELAY_NOT : TIME
+ );
+ PORT(
+ D : IN std_logic;
+ E : IN std_logic;
+ Q1 : INOUT std_logic;
+ Q2 : INOUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT FF_D_GATED_NOR
+ GENERIC(
+ DELAY_AND : TIME;
+ DELAY_OR : TIME;
+ DELAY_NOT : TIME
+ );
+ PORT(
+ D : IN std_logic;
+ E : IN std_logic;
+ Q1 : INOUT std_logic;
+ Q2 : INOUT std_logic
+ );
+ END COMPONENT;
+
+ for all : FF_D_GATED_NAND use entity WORK.FF_D_GATED(Behavioral_GATED_D_NAND);
+ for all : FF_D_GATED_NOR use entity WORK.FF_D_GATED(Behavioral_GATED_D_NOR);
+
+ signal CLK : std_logic;
+ signal D : std_logic := '0';
+ signal Q1_NAND,Q1_NOR : std_logic;
+ signal Q2_NAND,Q2_NOR : std_logic;
+
+ constant delay_and : TIME := 0 ns;
+ constant delay_or : TIME := 0 ns;
+ constant delay_not : TIME := 0 ns;
+
+BEGIN
+
+ clk_gen(CLK, 10 ns, 20 ns, 20 ns);
+
+ uut1: FF_D_GATED_NAND
+ GENERIC MAP (
+ DELAY_AND => delay_and,
+ DELAY_OR => delay_or,
+ DELAY_NOT => delay_not
+ )
+ PORT MAP (
+ D => D,
+ E => CLK,
+ Q1 => Q1_NAND,
+ Q2 => Q2_NAND
+ );
+
+ uut2: FF_D_GATED_NOR
+ GENERIC MAP (
+ DELAY_AND => delay_and,
+ DELAY_OR => delay_or,
+ DELAY_NOT => delay_not
+ )
+ PORT MAP (
+ D => D,
+ E => CLK,
+ Q1 => Q1_NOR,
+ Q2 => Q2_NOR
+ );
+
+ stim_proc: process
+ begin
+ D <= '0';
+ wait for 15 ns;
+ D <= '1';
+ wait for 10 ns;
+ D <= '0';
+ wait for 10 ns;
+ D <= '1';
+ wait for 5 ns;
+ D <= '0';
+ wait for 5 ns;
+ D <= '1';
+ wait for 10 ns;
+ D <= '0';
+ wait for 10 ns;
+ D <= '1';
+ wait for 15 ns;
+ D <= '0';
+ wait for 5 ns;
+ D <= '1';
+ wait for 15 ns;
+ D <= '0';
+ wait for 20 ns;
+ D <= '1';
+ wait for 5 ns;
+ D <= '0';
+ wait for 10 ns;
+ D <= '1';
+ wait for 5 ns;
+ D <= '0';
+ wait for 5 ns;
+ D <= '1';
+ wait for 10 ns;
+ D <= '0';
+ wait for 10 ns;
+ end process;
+
+END;
diff --git a/vhdl_primitive/TB_FF_SR.vhd b/vhdl_primitive/TB_FF_SR.vhd
new file mode 100755
index 0000000..f38788a
--- /dev/null
+++ b/vhdl_primitive/TB_FF_SR.vhd
@@ -0,0 +1,140 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:59:46 08/08/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl/TB_FF_SR.vhd
+-- Project Name: vhdl
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: FF_SR
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE WORK.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY TB_FF_SR IS
+END TB_FF_SR;
+
+ARCHITECTURE behavior OF TB_FF_SR IS
+
+ procedure clk_gen(signal clk : out std_logic; constant wait_start : time; constant HT : time; constant LT : time) is
+ begin
+ clk <= '0';
+ wait for wait_start;
+ loop
+ clk <= '1';
+ wait for HT;
+ clk <= '0';
+ wait for LT;
+ end loop;
+ end procedure;
+
+ COMPONENT FF_SR_NOR
+ PORT(
+ S : IN std_logic;
+ R : IN std_logic;
+ Q1 : INOUT std_logic;
+ Q2 : INOUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT FF_SR_NAND
+ PORT(
+ S : IN std_logic;
+ R : IN std_logic;
+ Q1 : INOUT std_logic;
+ Q2 : INOUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT FF_SR_ANDOR
+ PORT(
+ S : IN std_logic;
+ R : IN std_logic;
+ Q1 : INOUT std_logic;
+ Q2 : INOUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT FF_SR_NOTS_NOTR
+ PORT(
+ S : IN std_logic;
+ R : IN std_logic;
+ Q1 : INOUT std_logic;
+ Q2 : INOUT std_logic
+ );
+ END COMPONENT;
+
+ for all : FF_SR_NOR use entity WORK.FF_SR(Behavioral_NOR);
+ for all : FF_SR_NAND use entity WORK.FF_SR(Behavioral_NAND);
+ for all : FF_SR_ANDOR use entity WORK.FF_SR(Behavioral_ANDOR);
+ for all : FF_SR_NOTS_NOTR use entity WORK.FF_SR(Behavioral_NOT_S_NOT_R);
+
+ signal CLK1 : std_logic;
+ signal CLK2 : std_logic;
+ signal S : std_logic := '0';
+ signal R : std_logic := '0';
+ signal NOR_Q1,NAND_Q1,ANDOR_Q1,NOTSR_Q1 : std_logic;
+ signal NOR_Q2,NAND_Q2,ANDOR_Q2,NOTSR_Q2 : std_logic;
+
+BEGIN
+
+ clk_gen(CLK1, 3 ns, 20 ns, 50 ns);
+ clk_gen(CLK2, 7 ns, 35 ns, 10 ns);
+
+ uut_NOR: FF_SR_NOR PORT MAP (
+ S => S,
+ R => R,
+ Q1 => NOR_Q1,
+ Q2 => NOR_Q2
+ );
+
+ uut_NAND: FF_SR_NAND PORT MAP (
+ S => S,
+ R => R,
+ Q1 => NAND_Q1,
+ Q2 => NAND_Q2
+ );
+
+ uut_ANDOR: FF_SR_ANDOR PORT MAP (
+ S => S,
+ R => R,
+ Q1 => ANDOR_Q1,
+ Q2 => ANDOR_Q2
+ );
+
+ uut_NOTSR: FF_SR_NOTS_NOTR PORT MAP (
+ S => S,
+ R => R,
+ Q1 => NOTSR_Q1,
+ Q2 => NOTSR_Q2
+ );
+
+ stim_proc: process (CLK1,CLK2) is
+ begin
+ S <= CLK1;
+ R <= CLK2;
+ end process stim_proc;
+
+END;
diff --git a/vhdl_primitive/TB_FF_SR_GATED.vhd b/vhdl_primitive/TB_FF_SR_GATED.vhd
new file mode 100755
index 0000000..c0fe69e
--- /dev/null
+++ b/vhdl_primitive/TB_FF_SR_GATED.vhd
@@ -0,0 +1,156 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 00:52:07 08/10/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl/TB_FF_SR_GATED.vhd
+-- Project Name: vhdl
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: FF_SR_GATED
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY TB_FF_SR_GATED IS
+END TB_FF_SR_GATED;
+
+ARCHITECTURE behavior OF TB_FF_SR_GATED IS
+
+ procedure clk_gen(signal clk : out std_logic; constant wait_start : time; constant HT : time; constant LT : time) is
+ begin
+ clk <= '0';
+ wait for wait_start;
+ loop
+ clk <= '1';
+ wait for HT;
+ clk <= '0';
+ wait for LT;
+ end loop;
+ end procedure;
+
+ COMPONENT FF_SR_GATED1
+ PORT(
+ S : IN std_logic;
+ R : IN std_logic;
+ E : IN std_logic;
+ Q1 : INOUT std_logic;
+ Q2 : INOUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT FF_SR_GATED2
+ PORT(
+ S : IN std_logic;
+ R : IN std_logic;
+ E : IN std_logic;
+ Q1 : INOUT std_logic;
+ Q2 : INOUT std_logic
+ );
+ END COMPONENT;
+
+ for all : FF_SR_GATED1 use entity WORK.FF_SR_GATED(Behavioral_GATED_SR_1);
+ for all : FF_SR_GATED2 use entity WORK.FF_SR_GATED(Behavioral_GATED_SR_2);
+
+ signal CLK : std_logic;
+ signal S : std_logic := '0';
+ signal R : std_logic := '0';
+ signal Q1_1,Q1_2 : std_logic;
+ signal Q2_1,Q2_2 : std_logic;
+
+BEGIN
+
+ clk_gen(CLK, 10 ns, 20 ns, 20 ns);
+
+ uut1: FF_SR_GATED1 PORT MAP (
+ S => S,
+ R => R,
+ E => CLK,
+ Q1 => Q1_1,
+ Q2 => Q2_1
+ );
+
+ uut2: FF_SR_GATED2 PORT MAP (
+ S => S,
+ R => R,
+ E => CLK,
+ Q1 => Q1_2,
+ Q2 => Q2_2
+ );
+
+ stim_proc: process
+ begin
+ S <= '0';
+ R <= '1';
+ wait for 15 ns;
+ S <= '1';
+ R <= '0';
+ wait for 10 ns;
+ S <= '0';
+ R <= '1';
+ wait for 10 ns;
+ S <= '1';
+ R <= '0';
+ wait for 5 ns;
+ S <= '0';
+ R <= '1';
+ wait for 5 ns;
+ S <= '1';
+ R <= '0';
+ wait for 10 ns;
+ S <= '0';
+ R <= '1';
+ wait for 10 ns;
+ S <= '1';
+ R <= '0';
+ wait for 15 ns;
+ S <= '0';
+ R <= '1';
+ wait for 5 ns;
+ S <= '1';
+ R <= '0';
+ wait for 15 ns;
+ S <= '0';
+ R <= '1';
+ wait for 20 ns;
+ S <= '1';
+ R <= '0';
+ wait for 5 ns;
+ S <= '0';
+ R <= '1';
+ wait for 10 ns;
+ S <= '1';
+ R <= '0';
+ wait for 5 ns;
+ S <= '0';
+ R <= '1';
+ wait for 5 ns;
+ S <= '1';
+ R <= '0';
+ wait for 10 ns;
+ S <= '0';
+ R <= '1';
+ wait for 10 ns;
+ end process;
+
+END;
diff --git a/vhdl_primitive/TB_FULL_ADDER.vhd b/vhdl_primitive/TB_FULL_ADDER.vhd
new file mode 100755
index 0000000..9c2071b
--- /dev/null
+++ b/vhdl_primitive/TB_FULL_ADDER.vhd
@@ -0,0 +1,116 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:50:19 09/09/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl/TB_FULL_ADDER.vhd
+-- Project Name: vhdl
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: FULL_ADDER
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY TB_FULL_ADDER IS
+END TB_FULL_ADDER;
+
+ARCHITECTURE behavior OF TB_FULL_ADDER IS
+
+ procedure clk_gen(signal clk : out std_logic; constant wait_start : time; constant HT : time; constant LT : time) is
+ begin
+ clk <= '0';
+ wait for wait_start;
+ loop
+ clk <= '1';
+ wait for HT;
+ clk <= '0';
+ wait for LT;
+ end loop;
+ end procedure;
+
+ COMPONENT FULL_ADDER
+ PORT(
+ A : IN std_logic;
+ B : IN std_logic;
+ Cin : IN std_logic;
+ S : OUT std_logic;
+ Cout : OUT std_logic
+ );
+ END COMPONENT;
+
+ for all : FULL_ADDER use entity WORK.FULL_ADDER(FULL_ADDER_BEHAVIORAL_1);
+
+ signal CLK : std_logic;
+ signal A,B,Cin : std_logic := '0';
+ signal S,Cout : std_logic;
+
+BEGIN
+
+ clk_gen(CLK, 10 ns, 20 ns, 20 ns);
+
+ uut1: FULL_ADDER PORT MAP (
+ A => A,
+ B => B,
+ Cin => Cin,
+ S => S,
+ Cout => Cout
+ );
+
+ stim_proc: process
+ begin
+ A <= '0';
+ B <= '0';
+ Cin <= '0';
+ wait for 50 ns;
+ A <= '0';
+ B <= '0';
+ Cin <= '1';
+ wait for 50 ns;
+ A <= '0';
+ B <= '1';
+ Cin <= '0';
+ wait for 50 ns;
+ A <= '0';
+ B <= '1';
+ Cin <= '1';
+ wait for 50 ns;
+ A <= '1';
+ B <= '0';
+ Cin <= '0';
+ wait for 50 ns;
+ A <= '1';
+ B <= '0';
+ Cin <= '1';
+ wait for 50 ns;
+ A <= '1';
+ B <= '1';
+ Cin <= '0';
+ wait for 50 ns;
+ A <= '1';
+ B <= '1';
+ Cin <= '1';
+ wait for 50 ns;
+ end process;
+
+END;
diff --git a/vhdl_primitive/TB_GATE_XNOR.vhd b/vhdl_primitive/TB_GATE_XNOR.vhd
new file mode 100755
index 0000000..3daf779
--- /dev/null
+++ b/vhdl_primitive/TB_GATE_XNOR.vhd
@@ -0,0 +1,152 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 00:09:42 08/10/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl/TB_GATE_XNOR.vhd
+-- Project Name: vhdl
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: GATE_XNOR
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY TB_GATES_AND_OR_NOT_XOR_XNOR IS
+END TB_GATES_AND_OR_NOT_XOR_XNOR;
+
+ARCHITECTURE behavior OF TB_GATES_AND_OR_NOT_XOR_XNOR IS
+
+ COMPONENT GATE_AND
+ PORT(
+ A : IN std_logic;
+ B : IN std_logic;
+ C : OUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT GATE_OR
+ PORT(
+ A : IN std_logic;
+ B : IN std_logic;
+ C : OUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT GATE_NOT
+ PORT(
+ A : IN std_logic;
+ B : OUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT GATE_XOR1
+ PORT(
+ A : IN std_logic;
+ B : IN std_logic;
+ C : OUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT GATE_XOR2
+ PORT(
+ A : IN std_logic;
+ B : IN std_logic;
+ C : OUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT GATE_XNOR
+ PORT(
+ A : IN std_logic;
+ B : IN std_logic;
+ C : OUT std_logic
+ );
+ END COMPONENT;
+
+ for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+ for all : GATE_OR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+ for all : GATE_XOR1 use entity WORK.GATE_XOR(GATE_XOR_BEHAVIORAL_1);
+ for all : GATE_XOR2 use entity WORK.GATE_XOR(GATE_XOR_BEHAVIORAL_2);
+ for all : GATE_XNOR use entity WORK.GATE_XNOR(GATE_XNOR_BEHAVIORAL_1);
+
+ signal A : std_logic := '0';
+ signal B : std_logic := '0';
+ signal C_AND,C_OR,C_NOT,C_XOR1,C_XOR2,C_XNOR : std_logic;
+
+BEGIN
+
+ uut1: GATE_AND PORT MAP (
+ A => A,
+ B => B,
+ C => C_AND
+ );
+
+ uut2: GATE_OR PORT MAP (
+ A => A,
+ B => B,
+ C => C_OR
+ );
+
+ uut3: GATE_NOT PORT MAP (
+ A => A,
+ B => C_NOT
+ );
+
+ uut4: GATE_XOR1 PORT MAP (
+ A => A,
+ B => B,
+ C => C_XOR1
+ );
+
+ uut5: GATE_XOR2 PORT MAP (
+ A => A,
+ B => B,
+ C => C_XOR2
+ );
+
+ uut6: GATE_XNOR PORT MAP (
+ A => A,
+ B => B,
+ C => C_XNOR
+ );
+
+ stim_proc: process
+ begin
+ wait for 100 ns;
+ A <= '1';
+ B <= '1';
+ wait for 100 ns;
+ A <= '0';
+ B <= '1';
+ wait for 100 ns;
+ A <= '1';
+ B <= '0';
+ wait for 100 ns;
+ A <= '0';
+ B <= '0';
+ wait;
+ end process;
+
+END;
diff --git a/vhdl_primitive/TB_GATE_XOR.vhd b/vhdl_primitive/TB_GATE_XOR.vhd
new file mode 100755
index 0000000..b1ec5c7
--- /dev/null
+++ b/vhdl_primitive/TB_GATE_XOR.vhd
@@ -0,0 +1,94 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:48:40 08/08/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl/TB_GATE_XOR.vhd
+-- Project Name: vhdl
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: GATE_XOR
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY TB_GATE_XOR IS
+END TB_GATE_XOR;
+
+ARCHITECTURE behavior OF TB_GATE_XOR IS
+
+ COMPONENT GATE_XOR_1
+ PORT(
+ A : IN std_logic;
+ B : IN std_logic;
+ C : OUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT GATE_XOR_2
+ PORT(
+ A : IN std_logic;
+ B : IN std_logic;
+ C : OUT std_logic
+ );
+ END COMPONENT;
+
+ for all : GATE_XOR_1 use entity WORK.GATE_XOR(GATE_XOR_BEHAVIORAL_1);
+ for all : GATE_XOR_2 use entity WORK.GATE_XOR(GATE_XOR_BEHAVIORAL_2);
+
+ signal A : std_logic := '0';
+ signal B : std_logic := '0';
+ signal C1,C2 : std_logic;
+
+BEGIN
+
+ uut1: GATE_XOR_1 PORT MAP (
+ A => A,
+ B => B,
+ C => C1
+ );
+
+ uut2: GATE_XOR_2 PORT MAP (
+ A => A,
+ B => B,
+ C => C2
+ );
+
+ stim_proc: process
+ begin
+ wait for 100 ns;
+ A <= '1';
+ B <= '1';
+ wait for 100 ns;
+ A <= '0';
+ B <= '1';
+ wait for 100 ns;
+ A <= '1';
+ B <= '0';
+ wait for 100 ns;
+ A <= '0';
+ B <= '0';
+ wait;
+ end process;
+
+END;
diff --git a/vhdl_primitive/TB_HALF_ADDER.vhd b/vhdl_primitive/TB_HALF_ADDER.vhd
new file mode 100755
index 0000000..f539eec
--- /dev/null
+++ b/vhdl_primitive/TB_HALF_ADDER.vhd
@@ -0,0 +1,94 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:28:46 09/09/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl/TB_HALF_ADDER.vhd
+-- Project Name: vhdl
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: HALF_ADDER
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY TB_HALF_ADDER IS
+END TB_HALF_ADDER;
+
+ARCHITECTURE behavior OF TB_HALF_ADDER IS
+
+ procedure clk_gen(signal clk : out std_logic; constant wait_start : time; constant HT : time; constant LT : time) is
+ begin
+ clk <= '0';
+ wait for wait_start;
+ loop
+ clk <= '1';
+ wait for HT;
+ clk <= '0';
+ wait for LT;
+ end loop;
+ end procedure;
+
+ COMPONENT HALF_ADDER
+ PORT(
+ A : IN std_logic;
+ B : IN std_logic;
+ S : OUT std_logic;
+ C : OUT std_logic
+ );
+ END COMPONENT;
+
+ for all : HALF_ADDER use entity WORK.HALF_ADDER(HALF_ADDER_BEHAVIORAL_1);
+
+ signal CLK : std_logic;
+ signal A,B : std_logic := '0';
+ signal S,C : std_logic;
+
+BEGIN
+
+ clk_gen(CLK, 10 ns, 20 ns, 20 ns);
+
+ uut1: HALF_ADDER PORT MAP (
+ A => A,
+ B => B,
+ S => S,
+ C => C
+ );
+
+ stim_proc: process
+ begin
+ A <= '0';
+ B <= '0';
+ wait for 50 ns;
+ A <= '0';
+ B <= '1';
+ wait for 50 ns;
+ A <= '1';
+ B <= '0';
+ wait for 50 ns;
+ A <= '1';
+ B <= '1';
+ wait for 50 ns;
+ end process;
+
+END;
diff --git a/vhdl_primitive/TOGGLE_SYNCHRONIZER.sch b/vhdl_primitive/TOGGLE_SYNCHRONIZER.sch
new file mode 100644
index 0000000..ffa9d8d
--- /dev/null
+++ b/vhdl_primitive/TOGGLE_SYNCHRONIZER.sch
@@ -0,0 +1,309 @@
+
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\ No newline at end of file
diff --git a/vhdl_primitive/address_decoder.vhd b/vhdl_primitive/address_decoder.vhd
new file mode 100755
index 0000000..18c8740
--- /dev/null
+++ b/vhdl_primitive/address_decoder.vhd
@@ -0,0 +1,47 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:43:31 04/23/2021
+-- Design Name:
+-- Module Name: address_decoder - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity address_decoder is
+Generic (
+ N : integer := 3
+);
+Port (
+ x : in integer range 0 to 2**N-1;
+ y : out bit_vector(2**N-1 downto 0)
+);
+end address_decoder;
+
+architecture Behavioral of address_decoder is
+begin
+ chain : for i in x'range generate
+ y(i) <= '1' when i=x else '0';
+ end generate chain;
+end Behavioral;
diff --git a/vhdl_primitive/big_full_adder.vhd b/vhdl_primitive/big_full_adder.vhd
new file mode 100755
index 0000000..9094ea4
--- /dev/null
+++ b/vhdl_primitive/big_full_adder.vhd
@@ -0,0 +1,63 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:37:18 04/23/2021
+-- Design Name:
+-- Module Name: big_full_adder - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity big_full_adder is
+port (
+ a,b : in std_logic_vector(31 downto 0);
+ cin : in std_logic;
+ sum : out std_logic_vector(31 downto 0);
+ cout : out std_logic
+);
+end big_full_adder;
+
+architecture Behavioral of big_full_adder is
+ component carry_lookahead_adder is
+ Port (
+ a,b : in std_logic_vector(3 downto 0);
+ cin : in std_logic;
+ sum : out std_logic_vector(3 downto 0);
+ cout : out std_logic
+ );
+ end component carry_lookahead_adder;
+ signal carry : std_logic_vector(8 downto 0);
+begin
+ carry(0) <= cin;
+ chain : for i in 1 to 8 generate
+ adder : carry_lookahead_adder port map (
+ a(4*i-1 downto 4*i-4),
+ b(4*i-1 downto 4*i-4),
+ carry(i-1),
+ sum(4*i-1 downto 4*i-4),
+ carry(i)
+ );
+ end generate chain;
+ cout <= carry(8);
+end Behavioral;
diff --git a/vhdl_primitive/carry_lookahead_adder.vhd b/vhdl_primitive/carry_lookahead_adder.vhd
new file mode 100755
index 0000000..a943716
--- /dev/null
+++ b/vhdl_primitive/carry_lookahead_adder.vhd
@@ -0,0 +1,52 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:25:46 04/23/2021
+-- Design Name:
+-- Module Name: carry_lookahead_adder - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity carry_lookahead_adder is
+Port (
+ a,b : in std_logic_vector(3 downto 0);
+ cin : in std_logic;
+ sum : out std_logic_vector(3 downto 0);
+ cout : out std_logic
+);
+end carry_lookahead_adder;
+
+architecture Behavioral of carry_lookahead_adder is
+ signal G,P,c : std_logic_vector(3 downto 0);
+begin
+ G <= a and b;
+ P <= a xor b;
+ c(0) <= cin;
+ c(1) <= g(0) or (p(0) and cin);
+ c(2) <= g(1) or (p(1) and g(0)) or (p(1) and p(0) and cin);
+ c(3) <= g(2) or (p(2) and g(1)) or (p(2) and p(1) and g(0)) or (p(2) and p(1) and p(0) and cin);
+ cout <= g(3) or (p(3) and g(2)) or (p(3) and p(2) and g(1)) or (p(3) and p(2) and p(1) and g(0)) or (p(3) and p(2) and p(1) and p(0) and cin);
+ sum <= P xor c;
+end Behavioral;
diff --git a/vhdl_primitive/carry_ripple_adder.vhd b/vhdl_primitive/carry_ripple_adder.vhd
new file mode 100755
index 0000000..73294bd
--- /dev/null
+++ b/vhdl_primitive/carry_ripple_adder.vhd
@@ -0,0 +1,72 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:31:13 04/23/2021
+-- Design Name:
+-- Module Name: carry_ripple_adder - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity carry_ripple_adder is
+Generic (
+ N : integer := 8
+);
+Port (
+ a,b : in std_logic_vector(N-1 downto 0);
+ cin : in std_logic;
+ s : out std_logic_vector(N-1 downto 0);
+ cout : out std_logic
+);
+end carry_ripple_adder;
+
+architecture struct of carry_ripple_adder is
+ signal carry : std_logic_vector(N-1 downto 0);
+ component full_adder_struct is
+ Port (
+ a,b,cin : in std_logic;
+ s,cout : out std_logic
+ );
+ end component full_adder_struct;
+begin
+ carry(0) <= cin;
+ fa_chain : for i in a'range generate
+ fa : full_addrer_struct PORT MAP (a(i),b(i),carry(i),s(i),carry(i+1));
+ end generate fa_chain;
+ cout <= carry(N);
+end architecture struct;
+
+architecture behavioral of carry_ripple_addrer is
+begin
+ p0 : process (a,b,cin) is
+ variable carry : std_logic_vector(N downto 0);
+ begin
+ carry(0) := cin;
+ l0 : for i in 0 to N-1 loop
+ s(i) <= a(i) xor b(i) xor carry(i);
+ carry(i+1) := (a(i) and b(i)) or (a(i) and carry(i)) or (b(i) and carry(i));
+ end loop l0;
+ cout <= carry(N);
+ end process p0;
+end architecture behavioral;
diff --git a/vhdl_primitive/cb2ce.vhd b/vhdl_primitive/cb2ce.vhd
new file mode 100755
index 0000000..6b8e4ae
--- /dev/null
+++ b/vhdl_primitive/cb2ce.vhd
@@ -0,0 +1,66 @@
+-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/ECS/data/hdlMacro/vhdl/cb2ce.vhd,v 1.5 2012/08/30 17:45:42 robh Exp $
+-------------------------------------------------------------------------------
+-- Copyright (c) 2006 Xilinx, Inc.
+-- All Right Reserved.
+-------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor : Xilinx
+-- \ \ \/ Version : J.23
+-- \ \ Description : Xilinx HDL Macro Library
+-- / / 2-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear
+-- /___/ /\ Filename : CB2CE.vhd
+-- \ \ / \ Timestamp : Fri Jul 28 2006
+-- \___\/\___\
+--
+-- Revision:
+-- 07/28/06 - Initial version.
+-- End Revision
+
+----- CELL CB2CE -----
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity CB2CE is
+
+port (
+ CEO : out STD_LOGIC;
+ Q0 : out STD_LOGIC;
+ Q1 : out STD_LOGIC;
+ TC : out STD_LOGIC;
+ C : in STD_LOGIC;
+ CE : in STD_LOGIC;
+ CLR : in STD_LOGIC
+ );
+end CB2CE;
+
+architecture Behavioral of CB2CE is
+
+ signal COUNT : STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
+ constant TERMINAL_COUNT : STD_LOGIC_VECTOR(1 downto 0) := (others => '1');
+
+begin
+
+process(C, CLR)
+begin
+ if (CLR='1') then
+ COUNT <= (others => '0');
+ elsif (C'event and C = '1') then
+ if (CE='1') then
+ COUNT <= COUNT+1;
+ end if;
+ end if;
+end process;
+
+TC <= '1' when (COUNT = TERMINAL_COUNT) else '0';
+CEO <= '1' when ((COUNT = TERMINAL_COUNT) and CE='1') else '0';
+
+Q1 <= COUNT(1);
+Q0 <= COUNT(0);
+
+end Behavioral;
+
diff --git a/vhdl_primitive/circuit_ripplecounter_dff.vhd b/vhdl_primitive/circuit_ripplecounter_dff.vhd
new file mode 100644
index 0000000..e21e4f3
--- /dev/null
+++ b/vhdl_primitive/circuit_ripplecounter_dff.vhd
@@ -0,0 +1,128 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:45:02 07/05/2021
+-- Design Name:
+-- Module Name: circuit_ripplecounter_dff - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity circuit_ripplecounter_dff is
+port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_input : in std_logic;
+ o_output : out std_logic
+);
+end circuit_ripplecounter_dff;
+
+architecture Behavioral of circuit_ripplecounter_dff is
+
+component ripple_counter is
+Generic (
+N : integer := 32;
+MAX : integer := 1
+);
+Port (
+i_clock : in std_logic;
+i_cpb : in std_logic;
+i_mrb : in std_logic;
+i_ud : in std_logic;
+o_q : inout std_logic_vector(N-1 downto 0);
+o_ping : out std_logic
+);
+end component ripple_counter;
+
+component FF_D_POSITIVE_EDGE is
+port (
+S : in std_logic;
+R : in std_logic;
+C : in std_logic;
+D : in STD_LOGIC;
+Q1,Q2:inout STD_LOGIC);
+end component FF_D_POSITIVE_EDGE;
+
+component GATE_NOT is
+generic (
+delay_not : TIME := 1 ns
+);
+port (
+A : in STD_LOGIC;
+B : out STD_LOGIC
+);
+end component GATE_NOT;
+
+constant RC_N : integer := 6;
+constant RC_MAX : integer := 32;
+signal rc_q : std_logic_vector(RC_N-1 downto 0) := (others => '0');
+signal rc_ping,rc_mrb : std_logic;
+signal ffd_d,ffd_q1,ffd_q2 : std_logic;
+signal not1,not2 : std_logic;
+
+begin
+
+ffd_d <= i_input;
+rc_mrb <= not2 xnor i_input;
+o_output <= not1;
+
+u0 : ripple_counter
+Generic map (
+N => RC_N,
+MAX => RC_MAX
+)
+Port map (
+i_clock => i_clock,
+i_cpb => '1',
+i_mrb => rc_mrb,
+i_ud => '1',
+o_q => rc_q,
+o_ping => rc_ping
+);
+
+u1 : FF_D_POSITIVE_EDGE
+port map (
+S => i_reset,
+R => '1',
+C => rc_q(RC_N-1),
+D => ffd_d,
+Q1 => ffd_q1,
+Q2 => ffd_q2
+);
+
+u2 : GATE_NOT
+generic map (delay_not => 1 ps)
+port map (
+A => ffd_q1,
+B => not1
+);
+
+u3 : GATE_NOT
+generic map (delay_not => 1 ps)
+port map (
+A => not1,
+B => not2
+);
+
+end Behavioral;
diff --git a/vhdl_primitive/clk_gate1.sch b/vhdl_primitive/clk_gate1.sch
new file mode 100644
index 0000000..0260db7
--- /dev/null
+++ b/vhdl_primitive/clk_gate1.sch
@@ -0,0 +1,70 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2000-1-1T10:10:10
+
+
+
+
+
+
+
+ 2000-1-1T10:10:10
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/vhdl_primitive/clock.vhd b/vhdl_primitive/clock.vhd
new file mode 100755
index 0000000..4bc3f37
--- /dev/null
+++ b/vhdl_primitive/clock.vhd
@@ -0,0 +1,54 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:41:31 08/08/2020
+-- Design Name:
+-- Module Name: clock - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock is
+port (clock_out: out STD_LOGIC);
+end clock;
+
+architecture Behavioral of clock is
+component FF_SR_NOR is
+port (S,R:in STD_LOGIC;Q1,Q2:inout STD_LOGIC);
+end component FF_SR_NOR;
+component GN is
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : FF_SR_NOR use entity WORK.FF_SR(Behavioral_NOR);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sCLOCK,Q1,sa,sb: STD_LOGIC;
+begin
+sCLOCK <= '0';
+g1: FF_SR_NOR port map (sCLOCK,sa,Q1,sb);
+g2: GN port map (Q1,sCLOCK);
+p0 : process (sCLOCK) is
+begin
+end process p0;
+end Behavioral;
+
diff --git a/vhdl_primitive/clock_divider.vhd b/vhdl_primitive/clock_divider.vhd
new file mode 100755
index 0000000..abd4b61
--- /dev/null
+++ b/vhdl_primitive/clock_divider.vhd
@@ -0,0 +1,69 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:42:10 09/18/2020
+-- Design Name:
+-- Module Name: clock_divider - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_globals.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_divider is
+Generic (
+ g_board_clock : integer := 1;
+ g_divider : integer := 1
+);
+Port (
+ i_clock : in STD_LOGIC;
+ i_reset : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+);
+end clock_divider;
+
+architecture Behavioral of clock_divider is
+ constant clock_divider : integer := g_board_clock / g_divider;
+ signal clock_out : std_logic;
+begin
+
+p0 : process (i_clock,i_reset,clock_out) is
+ variable counter : integer := 0;
+begin
+ if (i_reset = '1') then
+ clock_out <= '0';
+ counter := 0;
+ elsif (rising_edge(i_clock)) then
+ if (counter = clock_divider-1) then
+ clock_out <= '1';
+ counter := 0;
+ else
+ clock_out <= '0';
+ counter := counter + 1;
+ end if;
+ end if;
+ o_clock <= clock_out;
+end process p0;
+
+end Behavioral;
+
diff --git a/vhdl_primitive/clock_divider_cnt.vhd b/vhdl_primitive/clock_divider_cnt.vhd
new file mode 100755
index 0000000..d5f6890
--- /dev/null
+++ b/vhdl_primitive/clock_divider_cnt.vhd
@@ -0,0 +1,66 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:42:10 09/18/2020
+-- Design Name:
+-- Module Name: clock_divider - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity clock_divider_cnt is
+Generic (
+ g_board_clock : integer;
+ g_divider : integer
+);
+Port (
+ i_reset : in STD_LOGIC;
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+);
+end clock_divider_cnt;
+
+architecture Behavioral of clock_divider_cnt is
+begin
+
+p0 : process (i_clock,i_reset) is
+ variable clock_out : std_logic;
+ variable counter : integer := 0;
+begin
+ if (i_reset = '1') then
+ counter := 0;
+ clock_out := '0';
+ elsif (rising_edge(i_clock)) then
+ if (counter = (g_board_clock / g_divider) - 1) then
+ clock_out := '1';
+ counter := 0;
+ else
+ clock_out := '0';
+ counter := counter + 1;
+ end if;
+ end if;
+ o_clock <= clock_out;
+end process p0;
+
+end Behavioral;
diff --git a/vhdl_primitive/count.vhd b/vhdl_primitive/count.vhd
new file mode 100755
index 0000000..606ee7f
--- /dev/null
+++ b/vhdl_primitive/count.vhd
@@ -0,0 +1,62 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 10:08:00 05/07/2021
+-- Design Name:
+-- Module Name: count - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity COUNT16 is -- XXX check for more than 32 bit in simulator
+port (Clk,Rst,Load: in std_logic;
+Data: in std_logic_vector (3 downto 0);
+Count: out std_logic_vector (3 downto 0)
+);
+end COUNT16;
+
+architecture COUNT16_A of COUNT16 is
+ signal Q: unsigned (3 downto 0);
+ constant MAXCOUNT: unsigned (3 downto 0) := "1111";
+begin
+ process(Rst,Clk)
+ begin
+ if Rst = '1' then
+ Q <= (others => '0');
+ elsif rising_edge(Clk) then
+ if Load = '1' then
+ Q <= UNSIGNED(Data); -- Type conversion
+ elsif Q = MAXCOUNT then
+ Q <= (others => '0');
+ else
+ Q <= Q + 1;
+ end if;
+ end if;
+ Count <= STD_LOGIC_VECTOR(Q); -- Type conversion
+ end process;
+end COUNT16_A;
diff --git a/vhdl_primitive/counter_n.vhd b/vhdl_primitive/counter_n.vhd
new file mode 100755
index 0000000..23aa7f7
--- /dev/null
+++ b/vhdl_primitive/counter_n.vhd
@@ -0,0 +1,58 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:44:15 04/19/2021
+-- Design Name:
+-- Module Name: counter_n - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity counter_n is
+Generic (
+N : integer := 8
+);
+Port (
+i_clock : in STD_LOGIC;
+i_reset : in STD_LOGIC;
+o_count : out STD_LOGIC_VECTOR (N-1 downto 0)
+);
+end counter_n;
+
+architecture Behavioral of counter_n is
+ signal counter : STD_LOGIC_VECTOR (N-1 downto 0);
+begin
+
+p0 : process (i_clock,i_reset) is
+begin
+ o_count <= counter;
+ if (i_reset = '1') then
+ counter <= (others => '0');
+ elsif (rising_edge(i_clock)) then
+ counter <= std_logic_vector(to_unsigned(to_integer(unsigned(counter))+1,N));
+ end if;
+end process p0;
+
+end Behavioral;
+
diff --git a/vhdl_primitive/counter_ping.vhd b/vhdl_primitive/counter_ping.vhd
new file mode 100755
index 0000000..7dcbea4
--- /dev/null
+++ b/vhdl_primitive/counter_ping.vhd
@@ -0,0 +1,63 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:56:47 04/23/2021
+-- Design Name:
+-- Module Name: counter_ping - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity counter_ping is
+generic (
+ max : integer := 1
+);
+port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ o_ping : out std_logic
+);
+end counter_ping;
+
+architecture Behavioral of counter_ping is
+begin
+ p0 : process (i_clock,i_reset) is
+ variable count : integer range 0 to max-1;
+ variable ping : std_logic;
+ begin
+ if (i_reset = '1') then
+ count := 0;
+ ping := '0';
+ elsif (rising_edge(i_clock)) then
+ if (count = max-1) then
+ count := 0;
+ ping := '1';
+ else
+ count := count + 1;
+ ping := '0';
+ end if;
+ end if;
+ o_ping <= ping;
+ end process p0;
+end Behavioral;
diff --git a/vhdl_primitive/counter_test1.vhd b/vhdl_primitive/counter_test1.vhd
new file mode 100644
index 0000000..3c81cc8
--- /dev/null
+++ b/vhdl_primitive/counter_test1.vhd
@@ -0,0 +1,63 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:04:58 12/04/2024
+-- Design Name:
+-- Module Name: counter_test1 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity counter_test1 is
+port (
+i_clock : in std_logic;
+i_reset : in std_logic;
+y_inc : out signed (31 downto 0);
+y_dec : out signed (31 downto 0)
+);
+end counter_test1;
+
+architecture Behavioral of counter_test1 is
+ signal y1 : signed (31 downto 0);
+ signal y2 : signed (31 downto 0);
+begin
+ p0 : process (i_clock, i_reset) is
+ begin
+ if (i_reset = '1') then
+ y1 <= (others => '0');
+ elsif (rising_edge (i_clock)) then
+ y1 <= - (not y1);
+ end if;
+ end process p0;
+ p1 : process (i_clock, i_reset) is
+ begin
+ if (i_reset = '1') then
+ y2 <= (others => '1');
+ elsif (rising_edge (i_clock)) then
+ y2 <= not (- y2);
+ end if;
+ end process p1;
+ y_inc <= y1;
+ y_dec <= y2;
+end Behavioral;
diff --git a/vhdl_primitive/counter_test2.vhd b/vhdl_primitive/counter_test2.vhd
new file mode 100644
index 0000000..2fa6566
--- /dev/null
+++ b/vhdl_primitive/counter_test2.vhd
@@ -0,0 +1,134 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:52:17 02/25/2025
+-- Design Name:
+-- Module Name: counter_test2 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+-- based on https://github.com/smunaut/ice40-playground/blob/d2fa0050129c14a7fc42f64f115366f6f2a51669/projects/usb_audio/rtl/audio_pcm.v#L221
+-- less resources
+-- -use_new_parser no
+entity counter_test2 is
+port (
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_a : in std_logic; -- -
+i_b : in std_logic; -- +
+o_counter : out std_logic_vector (31 downto 0)
+);
+end entity counter_test2;
+
+architecture behavioral of counter_test2 is
+
+signal zero_middle : std_logic_vector (31 downto 1);
+signal counter : std_logic_vector (31 downto 0);
+signal step : std_logic_vector (31 downto 0);
+
+begin
+
+o_counter <= std_logic_vector (counter);
+
+-- LUT based counter
+-- must wait one cycle for change +/- step (floating 1) - nevermind - zero_middle out of p0
+-- synthesis
+--Number of Slices
+--17
+--8672
+--0%
+--Number of Slice Flip Flops
+--32
+--17344
+--0%
+--Number of 4 input LUTs
+--33
+--17344
+--0%
+--Number of bonded IOBs
+--36
+--250
+--14%
+--Number of GCLKs
+--1
+--24
+--4%
+--Macro Statistics
+--# Accumulators : 1
+-- 32-bit up accumulator : 1
+--# Xors : 1
+-- 1-bit xor2 : 1
+p0 : process (i_clock, i_reset) is
+ variable temp : std_logic;
+begin
+ if (i_reset = '1') then
+ counter <= (others => '0');
+ elsif (rising_edge (i_clock)) then
+ counter <= std_logic_vector (to_signed ((to_integer (signed (counter))) + to_integer (signed (step)), 32));
+ end if;
+end process p0;
+zero_middle <= (others => ((i_a) and (not i_b)));
+step <= (zero_middle) & (i_a xor i_b);
+
+-- normal counter
+-- synthesis
+--Number of Slices
+--17
+--8672
+--0%
+--Number of Slice Flip Flops
+--32
+--17344
+--0%
+--Number of 4 input LUTs
+--34
+--17344
+--0%
+--Number of bonded IOBs
+--36
+--250
+--14%
+--Number of GCLKs
+--1
+--24
+--4%
+--Macro Statistics
+--# Counters : 1
+-- 32-bit updown counter : 1
+--p1 : process (i_clock, i_reset) is
+-- variable temp : std_logic;
+--begin
+-- if (i_reset = '1') then
+-- counter <= (others => '0');
+-- elsif (rising_edge (i_clock)) then
+-- if (i_a = '1' and i_b = '0') then
+-- counter <= std_logic_vector (to_signed ((to_integer (signed (counter))) - 1, 32));
+-- elsif (i_a = '0' and i_b = '1') then
+-- counter <= std_logic_vector (to_signed ((to_integer (signed (counter))) + 1, 32));
+-- end if;
+-- end if;
+--end process p1;
+
+end architecture behavioral;
diff --git a/vhdl_primitive/counter_test2_map.map b/vhdl_primitive/counter_test2_map.map
new file mode 100644
index 0000000..eb7b34d
--- /dev/null
+++ b/vhdl_primitive/counter_test2_map.map
@@ -0,0 +1,65 @@
+Release 14.7 Map P.20131013 (lin64)
+Xilinx Map Application Log File for Design 'counter_test2'
+
+Design Information
+------------------
+Command Line : map -filter
+/home/user/_WORKSPACE_/kedziorno/vhdl_projects/vhdl_primitive/iseconfig/filter.f
+ilter -intstyle ise -p xc3s1200e-fg320-4 -cm area -ir off -pr off -c 100 -o
+counter_test2_map.ncd counter_test2.ngd counter_test2.pcf
+Target Device : xc3s1200e
+Target Package : fg320
+Target Speed : -4
+Mapper Version : spartan3e -- $Revision: 1.55 $
+Mapped Date : Tue Feb 25 14:13:05 2025
+
+Mapping design into LUTs...
+Running directed packing...
+Running delay-based LUT packing...
+Running related packing...
+Updating timing models...
+
+Design Summary
+--------------
+
+Design Summary:
+Number of errors: 0
+Number of warnings: 0
+Logic Utilization:
+ Number of Slice Flip Flops: 32 out of 17,344 1%
+ Number of 4 input LUTs: 34 out of 17,344 1%
+Logic Distribution:
+ Number of occupied Slices: 17 out of 8,672 1%
+ Number of Slices containing only related logic: 17 out of 17 100%
+ Number of Slices containing unrelated logic: 0 out of 17 0%
+ *See NOTES below for an explanation of the effects of unrelated logic.
+ Total Number of 4 input LUTs: 34 out of 17,344 1%
+ Number of bonded IOBs: 36 out of 250 14%
+ Number of BUFGMUXs: 1 out of 24 4%
+
+Average Fanout of Non-Clock Nets: 3.75
+
+Peak Memory Usage: 581 MB
+Total REAL time to MAP completion: 2 secs
+Total CPU time to MAP completion: 2 secs
+
+NOTES:
+
+ Related logic is defined as being logic that shares connectivity - e.g. two
+ LUTs are "related" if they share common inputs. When assembling slices,
+ Map gives priority to combine logic that is related. Doing so results in
+ the best timing performance.
+
+ Unrelated logic shares no connectivity. Map will only begin packing
+ unrelated logic into a slice once 99% of the slices are occupied through
+ related logic packing.
+
+ Note that once logic distribution reaches the 99% level through related
+ logic packing, this does not mean the device is completely utilized.
+ Unrelated logic packing will then begin, continuing until all usable LUTs
+ and FFs are occupied. Depending on your timing budget, increased levels of
+ unrelated logic packing may adversely affect the overall timing performance
+ of your design.
+
+Mapping completed.
+See MAP report file "counter_test2_map.mrp" for details.
diff --git a/vhdl_primitive/counter_test2_map.mrp b/vhdl_primitive/counter_test2_map.mrp
new file mode 100644
index 0000000..00ce736
--- /dev/null
+++ b/vhdl_primitive/counter_test2_map.mrp
@@ -0,0 +1,174 @@
+Release 14.7 Map P.20131013 (lin64)
+Xilinx Mapping Report File for Design 'counter_test2'
+
+Design Information
+------------------
+Command Line : map -filter
+/home/user/_WORKSPACE_/kedziorno/vhdl_projects/vhdl_primitive/iseconfig/filter.f
+ilter -intstyle ise -p xc3s1200e-fg320-4 -cm area -ir off -pr off -c 100 -o
+counter_test2_map.ncd counter_test2.ngd counter_test2.pcf
+Target Device : xc3s1200e
+Target Package : fg320
+Target Speed : -4
+Mapper Version : spartan3e -- $Revision: 1.55 $
+Mapped Date : Tue Feb 25 14:13:05 2025
+
+Design Summary
+--------------
+Number of errors: 0
+Number of warnings: 0
+Logic Utilization:
+ Number of Slice Flip Flops: 32 out of 17,344 1%
+ Number of 4 input LUTs: 34 out of 17,344 1%
+Logic Distribution:
+ Number of occupied Slices: 17 out of 8,672 1%
+ Number of Slices containing only related logic: 17 out of 17 100%
+ Number of Slices containing unrelated logic: 0 out of 17 0%
+ *See NOTES below for an explanation of the effects of unrelated logic.
+ Total Number of 4 input LUTs: 34 out of 17,344 1%
+ Number of bonded IOBs: 36 out of 250 14%
+ Number of BUFGMUXs: 1 out of 24 4%
+
+Average Fanout of Non-Clock Nets: 3.75
+
+Peak Memory Usage: 581 MB
+Total REAL time to MAP completion: 2 secs
+Total CPU time to MAP completion: 2 secs
+
+NOTES:
+
+ Related logic is defined as being logic that shares connectivity - e.g. two
+ LUTs are "related" if they share common inputs. When assembling slices,
+ Map gives priority to combine logic that is related. Doing so results in
+ the best timing performance.
+
+ Unrelated logic shares no connectivity. Map will only begin packing
+ unrelated logic into a slice once 99% of the slices are occupied through
+ related logic packing.
+
+ Note that once logic distribution reaches the 99% level through related
+ logic packing, this does not mean the device is completely utilized.
+ Unrelated logic packing will then begin, continuing until all usable LUTs
+ and FFs are occupied. Depending on your timing budget, increased levels of
+ unrelated logic packing may adversely affect the overall timing performance
+ of your design.
+
+Table of Contents
+-----------------
+Section 1 - Errors
+Section 2 - Warnings
+Section 3 - Informational
+Section 4 - Removed Logic Summary
+Section 5 - Removed Logic
+Section 6 - IOB Properties
+Section 7 - RPMs
+Section 8 - Guide Report
+Section 9 - Area Group and Partition Summary
+Section 10 - Timing Report
+Section 11 - Configuration String Information
+Section 12 - Control Set Information
+Section 13 - Utilization by Hierarchy
+
+Section 1 - Errors
+------------------
+
+Section 2 - Warnings
+--------------------
+
+Section 3 - Informational
+-------------------------
+INFO:MapLib:562 - No environment variables are currently set.
+INFO:LIT:244 - All of the single ended outputs in this design are using slew
+ rate limited output drivers. The delay on speed critical single ended outputs
+ can be dramatically reduced by designating them as fast outputs.
+
+Section 4 - Removed Logic Summary
+---------------------------------
+
+Section 5 - Removed Logic
+-------------------------
+
+Section 6 - IOB Properties
+--------------------------
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
+| | | | | Term | Strength | Rate | | | Delay |
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+| i_a | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
+| i_b | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
+| i_clock | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
+| i_reset | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
+| o_counter<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<16> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<17> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<18> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<19> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<20> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<21> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<22> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<23> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<24> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<25> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<26> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<27> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<28> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<29> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<30> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
+| o_counter<31> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+Section 7 - RPMs
+----------------
+
+Section 8 - Guide Report
+------------------------
+Guide not run on this design.
+
+Section 9 - Area Group and Partition Summary
+--------------------------------------------
+
+Partition Implementation Status
+-------------------------------
+
+ No Partitions were found in this design.
+
+-------------------------------
+
+Area Group Information
+----------------------
+
+ No area groups were found in this design.
+
+----------------------
+
+Section 10 - Timing Report
+--------------------------
+This design was not run using timing mode.
+
+Section 11 - Configuration String Details
+-----------------------------------------
+Use the "-detail" map option to print out Configuration Strings
+
+Section 12 - Control Set Information
+------------------------------------
+No control set information for this architecture.
+
+Section 13 - Utilization by Hierarchy
+-------------------------------------
+Use the "-detail" map option to print out the Utilization by Hierarchy section.
diff --git a/vhdl_primitive/dac_delta_sigma.vhd b/vhdl_primitive/dac_delta_sigma.vhd
new file mode 100755
index 0000000..6a8db65
--- /dev/null
+++ b/vhdl_primitive/dac_delta_sigma.vhd
@@ -0,0 +1,52 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:50:09 03/03/2021
+-- Design Name:
+-- Module Name: dac_delta_sigma - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity dac_delta_sigma is
+Port (
+clk : in STD_LOGIC;
+data : in STD_LOGIC_VECTOR (7 downto 0);
+PulseStream : out STD_LOGIC
+);
+end dac_delta_sigma;
+
+architecture Behavioral of dac_delta_sigma is
+ signal sum : STD_LOGIC_VECTOR(8 downto 0) := (others=>'0');
+begin
+ PulseStream <= sum(8);
+ p0 : process (clk,sum) is
+ begin
+ if (rising_edge(clk)) then
+ sum <= ("0" & sum(7 downto 0)) + ("0" & data);
+ end if;
+ end process p0;
+end Behavioral;
diff --git a/vhdl_primitive/debounce.vhd b/vhdl_primitive/debounce.vhd
new file mode 100755
index 0000000..bd8cf95
--- /dev/null
+++ b/vhdl_primitive/debounce.vhd
@@ -0,0 +1,93 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:44:39 03/09/2021
+-- Design Name:
+-- Module Name: debounce - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity debounce is
+Generic (
+ G_BOARD_CLOCK : integer := 50_000_000;
+ G_SIZE : integer := 8
+);
+Port (
+ i_clk : in STD_LOGIC;
+ i_reset : in STD_LOGIC;
+ i_btn : in STD_LOGIC;
+ o_db_btn : out STD_LOGIC
+);
+end debounce;
+
+architecture Behavioral of debounce is
+
+ COMPONENT clock_divider_cnt IS
+ Generic (
+ g_board_clock : integer;
+ g_divider : integer
+ );
+ Port (
+ i_reset : in STD_LOGIC;
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+ );
+ END COMPONENT clock_divider_cnt;
+
+ signal d_clk : std_logic;
+ signal q : std_logic_vector(G_SIZE-1 downto 0);
+ signal qn : std_logic_vector(G_SIZE-1 downto 0);
+
+begin
+
+ clk_div_cnt : clock_divider_cnt
+ GENERIC MAP (
+ g_board_clock => G_BOARD_CLOCK,
+ g_divider => G_BOARD_CLOCK/2/1250
+ )
+ PORT MAP (
+ i_reset => i_reset,
+ i_clock => i_clk,
+ o_clock => d_clk
+ );
+
+ p0 : process (i_clk,i_reset) is
+ begin
+ if (i_reset = '1') then
+ q <= (others => '0');
+ qn <= (others => '1');
+ o_db_btn <= '0';
+ elsif (rising_edge(i_clk)) then
+ q(G_SIZE-1 downto 0) <= q(G_SIZE-2 downto 0) & i_btn;
+ if (q(G_SIZE-1 downto 0) = qn(G_SIZE-1 downto 0)) then
+ o_db_btn <= '1';
+ q <= (others => '0');
+ else
+ o_db_btn <= '0';
+ end if;
+ end if;
+ end process p0;
+
+end Behavioral;
diff --git a/vhdl_primitive/debounce2.vhd b/vhdl_primitive/debounce2.vhd
new file mode 100755
index 0000000..bd8cf95
--- /dev/null
+++ b/vhdl_primitive/debounce2.vhd
@@ -0,0 +1,93 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:44:39 03/09/2021
+-- Design Name:
+-- Module Name: debounce - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity debounce is
+Generic (
+ G_BOARD_CLOCK : integer := 50_000_000;
+ G_SIZE : integer := 8
+);
+Port (
+ i_clk : in STD_LOGIC;
+ i_reset : in STD_LOGIC;
+ i_btn : in STD_LOGIC;
+ o_db_btn : out STD_LOGIC
+);
+end debounce;
+
+architecture Behavioral of debounce is
+
+ COMPONENT clock_divider_cnt IS
+ Generic (
+ g_board_clock : integer;
+ g_divider : integer
+ );
+ Port (
+ i_reset : in STD_LOGIC;
+ i_clock : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+ );
+ END COMPONENT clock_divider_cnt;
+
+ signal d_clk : std_logic;
+ signal q : std_logic_vector(G_SIZE-1 downto 0);
+ signal qn : std_logic_vector(G_SIZE-1 downto 0);
+
+begin
+
+ clk_div_cnt : clock_divider_cnt
+ GENERIC MAP (
+ g_board_clock => G_BOARD_CLOCK,
+ g_divider => G_BOARD_CLOCK/2/1250
+ )
+ PORT MAP (
+ i_reset => i_reset,
+ i_clock => i_clk,
+ o_clock => d_clk
+ );
+
+ p0 : process (i_clk,i_reset) is
+ begin
+ if (i_reset = '1') then
+ q <= (others => '0');
+ qn <= (others => '1');
+ o_db_btn <= '0';
+ elsif (rising_edge(i_clk)) then
+ q(G_SIZE-1 downto 0) <= q(G_SIZE-2 downto 0) & i_btn;
+ if (q(G_SIZE-1 downto 0) = qn(G_SIZE-1 downto 0)) then
+ o_db_btn <= '1';
+ q <= (others => '0');
+ else
+ o_db_btn <= '0';
+ end if;
+ end if;
+ end process p0;
+
+end Behavioral;
diff --git a/vhdl_primitive/debounce_button.vhd b/vhdl_primitive/debounce_button.vhd
new file mode 100755
index 0000000..f2301c9
--- /dev/null
+++ b/vhdl_primitive/debounce_button.vhd
@@ -0,0 +1,96 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:13:46 09/15/2020
+-- Design Name:
+-- Module Name: debounce_button - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity debounce_button is
+generic (g_board_clock : integer);
+Port
+(
+i_button : in STD_LOGIC;
+i_clk : in STD_LOGIC;
+o_stable : out STD_LOGIC
+);
+end debounce_button;
+
+architecture Behavioral of debounce_button is
+
+signal slow_clk_en : std_logic;
+signal Q0,Q1,Q2,Q2_bar : std_logic := '0';
+
+begin
+
+p0 : process (i_clk) is
+ variable aa : integer := 250_000;
+ variable counter : integer := 0;
+ variable clk : std_logic;
+begin
+ if (rising_edge(i_clk)) then
+ if (counter = aa-1) then
+ counter := 0;
+ clk := '1';
+ else
+ clk := '0';
+ end if;
+ end if;
+ counter := counter + 1;
+ slow_clk_en <= clk;
+end process p0;
+
+p1a : process (slow_clk_en) is
+begin
+ if (rising_edge(slow_clk_en)) then
+ --if (slow_clk_en = '1') then
+ Q0 <= i_button;
+ --end if;
+ end if;
+end process p1a;
+
+p1b : process (slow_clk_en) is
+begin
+ if (rising_edge(slow_clk_en)) then
+ --if (slow_clk_en = '1') then
+ Q1 <= Q0;
+ --end if;
+ end if;
+end process p1b;
+
+p1c : process (slow_clk_en) is
+begin
+ if (rising_edge(slow_clk_en)) then
+ --if (slow_clk_en = '1') then
+ Q2 <= Q1;
+ --end if;
+ end if;
+end process p1c;
+
+Q2_bar <= not Q2;
+o_stable <= Q1 and Q2_bar;
+
+end Behavioral;
diff --git a/vhdl_primitive/debouncer1.vhd b/vhdl_primitive/debouncer1.vhd
new file mode 100755
index 0000000..485f92a
--- /dev/null
+++ b/vhdl_primitive/debouncer1.vhd
@@ -0,0 +1,132 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:58:26 04/23/2021
+-- Design Name:
+-- Module Name: debouncer1 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity debouncer1 is
+generic (
+ fclk : integer := 1;
+ twindow : integer := 10
+);
+port (
+ x : in std_logic;
+ clk : in std_logic;
+ rst : in std_logic;
+ y : inout std_logic
+);
+end debouncer1;
+
+--architecture Behavioral of debouncer1 is
+-- constant max : integer := fclk*twindow;
+-- signal count : integer range 0 to max-1;
+--begin
+-- p0 : process (clk,rst) is
+-- begin
+-- if (rst = '1') then
+-- y <= '0';
+-- elsif (rising_edge(clk)) then
+-- if (y /= x) then
+-- count <= count + 1;
+-- if (count=max-1) then
+-- count <= 0;
+-- y <= x;
+-- end if;
+-- else
+-- count <= 0;
+-- end if;
+-- end if;
+-- end process p0;
+--end Behavioral;
+
+architecture struct of debouncer1 is
+ component counter_ping is
+ generic (
+ max : integer := 1
+ );
+ port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ o_ping : out std_logic
+ );
+ end component counter_ping;
+ signal ping : std_logic;
+ signal clearb : std_logic;
+ signal d,q : std_logic;
+ signal p : std_logic;
+ constant max : integer := fclk*twindow;
+begin
+ cp_entity : counter_ping generic map (max=>max) port map (i_clock=>clk,i_reset=>not q,o_ping=>ping);
+-- p1 : process (x,q,ping,p) is
+-- begin
+-- p <= q;
+-- if (ping = '1') then
+-- if (p = q) then
+-- y <= '1';
+-- --q <= '1';
+-- else
+-- y <= '0';
+-- --q <= '0';
+-- end if;
+---- q <= '0';
+-- else
+-- if (p /= q) then
+---- q <= '0';
+-- end if;
+---- y <= '0';
+-- end if;
+-- clearb <= x xor q when rst = '0' else '0';
+-- d <= ping xor q when rst = '0' else '1';
+-- y <= ping xor clearb when rst = '0' else '1';
+-- clearb <= x xor q;
+-- d <= ping xor q;
+-- y <= ping xor clearb;
+-- end process p1;
+ p2 : process (clk,rst) is
+ begin
+ if (rst = '1') then
+-- d <= '0';
+ q <= '0';
+-- ping <= '0';
+-- clearb <= '0';
+ elsif (rising_edge(clk)) then
+ if (ping = '1') then
+ p <= q;
+ if (p /= q) then
+ y <= '1';
+ else
+ y <= '0';
+ end if;
+ elsif (x = '1') then
+ q <= x;
+ else
+ q <= q;
+ end if;
+ end if;
+ end process p2;
+end architecture struct;
diff --git a/vhdl_primitive/decoder.vhd b/vhdl_primitive/decoder.vhd
new file mode 100755
index 0000000..41fdb2c
--- /dev/null
+++ b/vhdl_primitive/decoder.vhd
@@ -0,0 +1,59 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:31:53 04/12/2021
+-- Design Name:
+-- Module Name: decoder - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity decoder is
+Generic (
+SIZE : integer := 4
+);
+Port (
+input : in integer range 0 to SIZE-1;
+output : out integer range 0 to (2**SIZE)-1
+);
+end decoder;
+
+architecture Behavioral of decoder is
+begin
+ -- XXX https://stackoverflow.com/a/4788661 https://stackoverflow.com/a/4788253
+ --output <= 0;
+ p0 : process (input) is
+ begin
+ output <= 2**input;
+ end process p0;
+-- MUX : for i in 0 to (2**SIZE)-1 generate
+-- begin
+-- if (i = conv_integer(input)) then
+-- output(i) <= '1';
+-- else
+-- output(i) <= '0';
+-- end if;
+-- end generate MUX;
+end Behavioral;
+
diff --git a/vhdl_primitive/delayed_circuit.vhd b/vhdl_primitive/delayed_circuit.vhd
new file mode 100755
index 0000000..b8155f4
--- /dev/null
+++ b/vhdl_primitive/delayed_circuit.vhd
@@ -0,0 +1,109 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:57:28 12/18/2021
+-- Design Name:
+-- Module Name: delayed_circuit - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity delayed_circuit is
+port (
+i_clock : in std_logic;
+i_input : in std_logic;
+o_output : out std_logic
+);
+end delayed_circuit;
+
+architecture Behavioral of delayed_circuit is
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 0 ps
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ signal s : std_logic;
+ signal q1,q2 : std_logic;
+
+ constant N : integer := 8;
+ constant N2 : integer := 2**N;
+
+ signal v1 : integer range 0 to N2-1 := 0;
+ signal tv1 : std_logic_vector(31 downto 0) := (others => '0');
+
+ type state is (a,b,c);
+ signal vs : state;
+
+begin
+
+tv1 <= std_logic_vector(to_unsigned(v1,32));
+
+o_output <= s;
+p3 : process (i_input,q2) is
+begin
+ if (rising_edge(q2)) then
+ case (vs) is
+ when a =>
+ s <= '0';
+ if (i_input = '1') then
+ vs <= b;
+ else
+ vs <= a;
+ end if;
+ when b =>
+ s <= '0';
+ if (v1 = N2-1) then
+ vs <= c;
+ v1 <= 0;
+ else
+ vs <= b;
+ v1 <= v1 + 1 after 1 ns;
+ end if;
+ when c =>
+ s <= '1';
+ vs <= a;
+ end case;
+ end if;
+end process p3;
+
+g0 : GATE_NOT port map (A => q1, B => q2);
+LDCPE_inst : LDCPE
+generic map (INIT => '0')
+port map (
+ Q => q1,
+ CLR => i_input,
+ D => q2,
+ G => '1',
+ GE => '1',
+ PRE => '0'
+);
+
+end Behavioral;
diff --git a/vhdl_primitive/delayed_programmable_circuit.vhd b/vhdl_primitive/delayed_programmable_circuit.vhd
new file mode 100755
index 0000000..82271f2
--- /dev/null
+++ b/vhdl_primitive/delayed_programmable_circuit.vhd
@@ -0,0 +1,173 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:35:29 08/22/2021
+-- Design Name:
+-- Module Name: delayed_programmable_circuit - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity delayed_programmable_circuit is
+port (
+i_reg1 : in std_logic;
+i_reg2 : in std_logic;
+i_reg3 : in std_logic;
+i_reg4 : in std_logic;
+i_reg5 : in std_logic;
+i_reg6 : in std_logic;
+i_reg7 : in std_logic;
+i_input : in std_logic;
+o_output : out std_logic
+);
+end delayed_programmable_circuit;
+
+architecture Behavioral of delayed_programmable_circuit is
+
+component MUX_21 is
+port (S,A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component MUX_21;
+
+component GATE_NOT is
+generic (
+delay_not : time := 1 ns
+);
+port (
+A : in STD_LOGIC;
+B : out STD_LOGIC
+);
+end component GATE_NOT;
+for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+component DEMUX_12 is
+port (S,A:in STD_LOGIC;B,C:out STD_LOGIC);
+end component DEMUX_12;
+
+signal mux_out : std_logic_vector(8 downto 1);
+signal normal_line : std_logic_vector(8 downto 1);
+
+signal nots1 : std_logic_vector(2**1 downto 0);
+signal nots2 : std_logic_vector(2**2 downto 0);
+signal nots3 : std_logic_vector(2**3 downto 0);
+signal nots4 : std_logic_vector(2**4 downto 0);
+signal nots5 : std_logic_vector(2**5 downto 0);
+signal nots6 : std_logic_vector(2**6 downto 0);
+signal nots7 : std_logic_vector(2**7 downto 0);
+
+begin
+
+dmx1 : DEMUX_12 port map (
+S => i_reg1, A => i_input,
+B => normal_line(1), C => nots1(0)
+);
+gnots1 : for i in 1 to 2**1 generate
+ gn : GATE_NOT port map (A => nots1(i-1), B => nots1(i));
+end generate gnots1;
+mux1 : MUX_21 port map (
+S => i_reg1,
+A => normal_line(1), B => nots1(2**1),
+C => mux_out(1)
+);
+
+dmx2 : DEMUX_12 port map (
+S => i_reg2, A => mux_out(1),
+B => normal_line(2), C => nots2(0)
+);
+gnots2 : for i in 1 to 2**2 generate
+ gn : GATE_NOT port map (A => nots2(i-1), B => nots2(i));
+end generate gnots2;
+mux2 : MUX_21 port map (
+S => i_reg2,
+A => normal_line(2), B => nots2(2**2),
+C => mux_out(2)
+);
+
+dmx3 : DEMUX_12 port map (
+S => i_reg3, A => mux_out(2),
+B => normal_line(3), C => nots3(0)
+);
+gnots3 : for i in 1 to 2**3 generate
+ gn : GATE_NOT port map (A => nots3(i-1), B => nots3(i));
+end generate gnots3;
+mux3 : MUX_21 port map (
+S => i_reg3,
+A => normal_line(3), B => nots3(2**3),
+C => mux_out(3)
+);
+
+dmx4 : DEMUX_12 port map (
+S => i_reg4, A => mux_out(3),
+B => normal_line(4), C => nots4(0)
+);
+gnots4 : for i in 1 to 2**4 generate
+ gn : GATE_NOT port map (A => nots4(i-1), B => nots4(i));
+end generate gnots4;
+mux4 : MUX_21 port map (
+S => i_reg4,
+A => normal_line(4), B => nots4(2**4),
+C => mux_out(4)
+);
+
+dmx5 : DEMUX_12 port map (
+S => i_reg5, A => mux_out(4),
+B => normal_line(5), C => nots5(0)
+);
+gnots5 : for i in 1 to 2**5 generate
+ gn : GATE_NOT port map (A => nots5(i-1), B => nots5(i));
+end generate gnots5;
+mux5 : MUX_21 port map (
+S => i_reg5,
+A => normal_line(5), B => nots5(2**5),
+C => mux_out(5)
+);
+
+dmx6 : DEMUX_12 port map (
+S => i_reg6, A => mux_out(5),
+B => normal_line(6), C => nots6(0)
+);
+gnots6 : for i in 1 to 2**6 generate
+ gn : GATE_NOT port map (A => nots6(i-1), B => nots6(i));
+end generate gnots6;
+mux6 : MUX_21 port map (
+S => i_reg6,
+A => normal_line(6), B => nots6(2**6),
+C => mux_out(6)
+);
+
+dmx7 : DEMUX_12 port map (
+S => i_reg7, A => mux_out(6),
+B => normal_line(7), C => nots7(0)
+);
+gnots7 : for i in 1 to 2**7 generate
+ gn : GATE_NOT port map (A => nots7(i-1), B => nots7(i));
+end generate gnots7;
+mux7 : MUX_21 port map (
+S => i_reg7,
+A => normal_line(7), B => nots7(2**7),
+C => mux_out(7)
+);
+
+o_output <= mux_out(7);
+
+end Behavioral;
diff --git a/vhdl_primitive/edge_clock.vhd b/vhdl_primitive/edge_clock.vhd
new file mode 100755
index 0000000..3d6c069
--- /dev/null
+++ b/vhdl_primitive/edge_clock.vhd
@@ -0,0 +1,71 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:03:07 07/03/2021
+-- Design Name:
+-- Module Name: edge_clock - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity edge_clock is
+port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_e1 : in std_logic;
+ i_e2 : in std_logic;
+ o_count : out unsigned(31 downto 0)
+);
+end edge_clock;
+
+architecture Behavioral of edge_clock is
+ signal count1,count2 : unsigned(31 downto 0);
+begin
+
+ p0 : process (i_clock,i_reset) is
+ begin
+ if (i_reset = '1') then
+ count1 <= (others => '0');
+ elsif (rising_edge(i_clock)) then
+-- if (i_e1 = '1') then
+ count1 <= count1 + 1;
+-- end if;
+ end if;
+ end process p0;
+
+ p1 : process (i_clock,i_reset) is
+ begin
+ if (i_reset = '1') then
+ count2 <= (others => '0');
+ elsif (falling_edge(i_clock)) then
+-- if (i_e2 = '1') then
+ count2 <= count2 - 1;
+-- end if;
+ end if;
+ end process p1;
+
+ o_count <= count1 when i_clock = '1' else count2 when i_clock = '0';
+
+end Behavioral;
+
diff --git a/vhdl_primitive/ex_4_2_Add_full_0_delay.sym b/vhdl_primitive/ex_4_2_Add_full_0_delay.sym
new file mode 100644
index 0000000..ed85ed5
--- /dev/null
+++ b/vhdl_primitive/ex_4_2_Add_full_0_delay.sym
@@ -0,0 +1,24 @@
+
+
+ BLOCK
+ 2023-6-6T18:0:23
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/vhdl_primitive/ex_4_2_Add_half_0_delay.sym b/vhdl_primitive/ex_4_2_Add_half_0_delay.sym
new file mode 100644
index 0000000..4a26b7e
--- /dev/null
+++ b/vhdl_primitive/ex_4_2_Add_half_0_delay.sym
@@ -0,0 +1,21 @@
+
+
+ BLOCK
+ 2023-6-6T14:25:5
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/vhdl_primitive/ex_4_2_Add_rca_16_0_delay.sym b/vhdl_primitive/ex_4_2_Add_rca_16_0_delay.sym
new file mode 100644
index 0000000..20e71f8
--- /dev/null
+++ b/vhdl_primitive/ex_4_2_Add_rca_16_0_delay.sym
@@ -0,0 +1,27 @@
+
+
+ BLOCK
+ 2023-6-6T17:46:52
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/vhdl_primitive/ex_4_2_Add_rca_4.sym b/vhdl_primitive/ex_4_2_Add_rca_4.sym
new file mode 100644
index 0000000..174c716
--- /dev/null
+++ b/vhdl_primitive/ex_4_2_Add_rca_4.sym
@@ -0,0 +1,27 @@
+
+
+ BLOCK
+ 2023-6-6T18:25:7
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/vhdl_primitive/ex_4_5.sch b/vhdl_primitive/ex_4_5.sch
new file mode 100644
index 0000000..8e32afc
--- /dev/null
+++ b/vhdl_primitive/ex_4_5.sch
@@ -0,0 +1,362 @@
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+ 2000-1-1T10:10:10
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+ 2023-8-10T13:21:20
+
+
+
+
+
+
+
+
+
+
+ 2000-1-1T10:10:10
+
+
+
+
+
+
+
+
+
+
+ 2000-1-1T10:10:10
+
+
+
+
+
+
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+
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+
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+
+
+
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+
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+
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+
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+
+
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+
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+
+
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+
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+
+
+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
+
+
+
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+
+
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+
+
+
+
+
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+
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+
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+
\ No newline at end of file
diff --git a/vhdl_primitive/ff.vhd b/vhdl_primitive/ff.vhd
new file mode 100755
index 0000000..81c107d
--- /dev/null
+++ b/vhdl_primitive/ff.vhd
@@ -0,0 +1,51 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:47:48 04/23/2021
+-- Design Name:
+-- Module Name: ff - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ff is
+Generic (
+ bits : positive
+);
+Port (
+ d : in std_logic; --std_logic_vector(bits-1 downto 0); --d : in bit_vector(bits-1 downto 0);
+ clk : in std_logic; --clk : in bit;
+ q : out std_logic --std_logic_vector(bits-1 downto 0) --q : out bit_vector(bits-1 downto 0)
+);
+end ff;
+
+architecture Behavioral of ff is
+begin
+ p0 : process (clk) is
+ begin
+ if (rising_edge(clk)) then -- clk'event and clk='1'
+ q <= d;
+ end if;
+ end process p0;
+end Behavioral;
diff --git a/vhdl_primitive/ff3_synchronizer.vhd b/vhdl_primitive/ff3_synchronizer.vhd
new file mode 100644
index 0000000..0aa87ac
--- /dev/null
+++ b/vhdl_primitive/ff3_synchronizer.vhd
@@ -0,0 +1,61 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:50:20 07/09/2021
+-- Design Name:
+-- Module Name: ff3_synchronizer - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ff3_synchronizer is
+Port (
+ i_clock : in STD_LOGIC;
+ i_reset : in STD_LOGIC;
+ i_input : in STD_LOGIC;
+ o_pulse : out STD_LOGIC
+);
+end ff3_synchronizer;
+
+architecture Behavioral of ff3_synchronizer is
+ signal d,dd,ddd : std_logic;
+begin
+
+ p0 : process (i_clock,i_reset) is
+ begin
+ if (i_reset = '1') then
+ o_pulse <= '0';
+ d <= '0';
+ dd <= '0';
+ ddd <= '0';
+ elsif (rising_edge(i_clock)) then
+ d <= i_input;
+ dd <= d;
+ ddd <= dd;
+ o_pulse <= dd and not ddd;
+ end if;
+ end process p0;
+
+end Behavioral;
+
diff --git a/vhdl_primitive/fibonacci.vhd b/vhdl_primitive/fibonacci.vhd
new file mode 100755
index 0000000..614d69d
--- /dev/null
+++ b/vhdl_primitive/fibonacci.vhd
@@ -0,0 +1,57 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:04:34 04/23/2021
+-- Design Name:
+-- Module Name: fibonacci - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity fibonacci is
+generic (
+ N : integer := 16
+);
+port (
+ clk,rst : in bit;
+ f : out integer range 0 to 2**N-1
+);
+end fibonacci;
+
+architecture Behavioral of fibonacci is
+ signal a,b,c : integer range 0 to 2**N-1;
+begin
+ p0 : process (clk,rst) is
+ begin
+ if (rst = '1') then
+ b <= 1;
+ c <= 0;
+ elsif (rising_edge(clk)) then
+ c <= b;
+ b <= a;
+ end if;
+ a <= b + c;
+ end process p0;
+ f <= c;
+end Behavioral;
diff --git a/vhdl_primitive/fig33.vhd b/vhdl_primitive/fig33.vhd
new file mode 100644
index 0000000..bd76447
--- /dev/null
+++ b/vhdl_primitive/fig33.vhd
@@ -0,0 +1,58 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:00:52 06/04/2023
+-- Design Name:
+-- Module Name: fig33 - Behavioral
+-- Project Name: Transparent Latch
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity fig33 is
+port (
+signal Data : in bit;
+signal Enable : in bit;
+signal Q_out : out bit;
+signal Qb_out : out bit
+);
+end fig33;
+
+architecture Behavioral of fig33 is
+
+signal q1,q2 : bit;
+signal de,dbe : bit; -- data & enable, dataBAR & enable
+
+begin
+
+de <= Data nand Enable;
+dbe <= (not Data) nand Enable;
+
+q1 <= de nand q2 after 1 ps;
+q2 <= dbe nand q1;
+
+Q_out <= q1;
+Qb_out <= q2;
+
+end Behavioral;
+
diff --git a/vhdl_primitive/fig35.ucf b/vhdl_primitive/fig35.ucf
new file mode 100644
index 0000000..25062e4
--- /dev/null
+++ b/vhdl_primitive/fig35.ucf
@@ -0,0 +1,2 @@
+NET "clock" TNM_NET = "CLK_A";
+TIMESPEC "TS_CLKA" = PERIOD "CLK_A" 10 ns;
diff --git a/vhdl_primitive/fig35.vhd b/vhdl_primitive/fig35.vhd
new file mode 100644
index 0000000..62c9bfe
--- /dev/null
+++ b/vhdl_primitive/fig35.vhd
@@ -0,0 +1,75 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:40:20 06/04/2023
+-- Design Name: Master-slave neg-edge D FF
+-- Module Name: fig35 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity fig35 is
+port (
+Data : in bit;
+clock : in bit;
+Q,Qb : out bit
+);
+end fig35;
+
+architecture Behavioral of fig35 is
+
+component fig33 is
+port (
+signal Data : in bit;
+signal Enable : in bit;
+signal Q_out : out bit;
+signal Qb_out : out bit
+);
+end component fig33;
+
+signal clockbar : bit;
+signal qd : bit;
+
+begin
+
+clockbar <= not clock;
+
+data_latch_master : fig33
+port map (
+Data => Data,
+Enable => not clock,
+Q_out => qd,
+Qb_out => open
+);
+
+data_latch_slave : fig33
+port map (
+Data => qd,
+Enable => not clockbar,
+Q_out => Q,
+Qb_out => Qb
+);
+
+end Behavioral;
+
diff --git a/vhdl_primitive/fig37.ucf b/vhdl_primitive/fig37.ucf
new file mode 100644
index 0000000..25062e4
--- /dev/null
+++ b/vhdl_primitive/fig37.ucf
@@ -0,0 +1,2 @@
+NET "clock" TNM_NET = "CLK_A";
+TIMESPEC "TS_CLKA" = PERIOD "CLK_A" 10 ns;
diff --git a/vhdl_primitive/fig37.vhd b/vhdl_primitive/fig37.vhd
new file mode 100644
index 0000000..5d9b43b
--- /dev/null
+++ b/vhdl_primitive/fig37.vhd
@@ -0,0 +1,128 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:49:51 06/04/2023
+-- Design Name: CMOS MS DFF
+-- Module Name: fig37 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity fig37 is
+port (
+Data : in std_logic;
+Clear_bar : in std_logic;
+clock : in std_logic;
+Q,Qb : out std_logic
+);
+end fig37;
+
+architecture Behavioral of fig37 is
+
+component transmission_gate is
+port (
+ io_a : in std_logic;
+ io_b : out std_logic;
+ i_s : in std_logic
+);
+end component transmission_gate;
+--for all : transmission_gate use entity work.transmission_gate(Behavioral1);
+for all : transmission_gate use entity work.transmission_gate(Behavioral2);
+
+component GATE_NOT is
+generic (
+delay_not : TIME := 1 ps
+);
+port (
+A : in STD_LOGIC;
+B : out STD_LOGIC
+);
+end component GATE_NOT;
+for all : GATE_NOT use entity work.GATE_NOT(GATE_NOT_LUT);
+
+signal a,b,b1,c,c1,d,e,e1,f,f1,g,h,h1 : std_logic := '0';
+attribute KEEP : string;
+attribute KEEP of a : signal is "true";
+attribute KEEP of b : signal is "true";
+attribute KEEP of b1 : signal is "true";
+attribute KEEP of c : signal is "true";
+attribute KEEP of c1 : signal is "true";
+attribute KEEP of d : signal is "true";
+attribute KEEP of e : signal is "true";
+attribute KEEP of e1 : signal is "true";
+attribute KEEP of f : signal is "true";
+attribute KEEP of f1 : signal is "true";
+attribute KEEP of g : signal is "true";
+attribute KEEP of h : signal is "true";
+attribute KEEP of h1 : signal is "true";
+
+begin
+
+inst1 : BUF port map (I=>Data,O=>a);
+
+clock_tg1 : transmission_gate
+port map (
+io_a => a,
+io_b => b,
+i_s => not clock
+);
+
+c <= b nand Clear_bar after 1 ns;
+inst_not1 : GATE_NOT port map (A=>c,B=>d);
+
+clock_tg2 : transmission_gate
+port map (
+io_a => d,
+io_b => b1,
+i_s => clock
+);
+
+inst2 : BUF port map (I=>c,O=>c1);
+
+clock_tg3 : transmission_gate
+port map (
+io_a => c1,
+io_b => e,
+i_s => clock
+);
+
+bt1 : BUFT port map (I=>b1,O=>b,T=>not clock);
+
+inst_not2 : GATE_NOT port map (A=>e,B=>f);
+g <= f nand Clear_bar;
+
+Qb <= g;
+Q <= not g;
+
+clock_tg4 : transmission_gate
+port map (
+io_a => g,
+io_b => e1,
+i_s => not clock
+);
+
+bt2 : BUFT port map (I=>e1,O=>e,T=>clock);
+
+end Behavioral;
+
diff --git a/vhdl_primitive/fig_3_22.ucf b/vhdl_primitive/fig_3_22.ucf
new file mode 100644
index 0000000..19e7bf5
--- /dev/null
+++ b/vhdl_primitive/fig_3_22.ucf
@@ -0,0 +1,3 @@
+NET "clk" TNM_NET = "CLK_A";
+TIMESPEC "TS_CLKA" = PERIOD "CLK_A" 10 ns;
+
diff --git a/vhdl_primitive/fig_3_22.vhd b/vhdl_primitive/fig_3_22.vhd
new file mode 100644
index 0000000..fed2a8c
--- /dev/null
+++ b/vhdl_primitive/fig_3_22.vhd
@@ -0,0 +1,99 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:23:38 06/05/2023
+-- Design Name: My-type Serial BCD to Ex-3 Code Converter
+-- Module Name: fig_3_22 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity fig_3_22 is
+port (
+clk : in std_logic;
+reset : in std_logic;
+Bin : in std_logic;
+Bout : out std_logic
+);
+end fig_3_22;
+
+architecture Behavioral of fig_3_22 is
+
+component NAND2 is
+port(
+O : out std_ulogic;
+I0 : in std_ulogic;
+I1 : in std_ulogic
+);
+end component NAND2;
+
+component NAND3 is
+port(
+O : out std_ulogic;
+I0 : in std_ulogic;
+I1 : in std_ulogic;
+I2 : in std_ulogic
+);
+end component NAND3;
+
+component FDR is
+port(
+Q : out std_ulogic;
+C : in std_ulogic;
+D : in std_ulogic;
+R : in std_ulogic
+);
+end component FDR;
+
+signal d0,d1,d2 : std_logic;
+signal q0,q1,q2 : std_logic;
+signal q0b,q1b,q2b : std_logic;
+
+signal binb,boutb : std_logic;
+signal gate1,gate2,gate3,gate4,gate5,gate6 : std_logic;
+
+begin
+
+binb <= not Bin;
+
+inst_nand1 : NAND3 port map (O=>gate1, I0=>q0 , I1=>q1 , I2=>q2 );
+inst_nand2 : NAND3 port map (O=>gate2, I0=>q0 , I1=>q2b , I2=>binb );
+inst_nand3 : NAND3 port map (O=>gate3, I0=>q0b , I1=>q1b , I2=>Bin );
+inst_nand4 : NAND3 port map (O=>gate4, I0=>gate1, I1=>gate2, I2=>gate3);
+
+inst_FDRq0 : FDR port map (Q=>q0, C=>clk, D=>q1b , R=>reset);
+inst_FDRq1 : FDR port map (Q=>q1, C=>clk, D=>q0 , R=>reset);
+inst_FDRq2 : FDR port map (Q=>q2, C=>clk, D=>gate4, R=>reset);
+q0b <= not q0;
+q1b <= not q1;
+q2b <= not q2;
+
+inst_nand5 : NAND2 port map (O=>gate5, I0=>Bin, I1=>q2 );
+inst_nand6 : NAND2 port map (O=>gate6, I0=>binb, I1=>q2b );
+inst_nand7 : NAND2 port map (O=>boutb, I0=>gate5, I1=>gate6);
+
+Bout <= boutb;
+
+end Behavioral;
+
diff --git a/vhdl_primitive/fig_3_29.ucf b/vhdl_primitive/fig_3_29.ucf
new file mode 100644
index 0000000..40034cb
--- /dev/null
+++ b/vhdl_primitive/fig_3_29.ucf
@@ -0,0 +1,2 @@
+NET "clk" TNM_NET = "CLK_A";
+TIMESPEC "TS_CLKA" = PERIOD "CLK_A" 10 ns;
diff --git a/vhdl_primitive/fig_3_29.vhd b/vhdl_primitive/fig_3_29.vhd
new file mode 100644
index 0000000..a4b10cc
--- /dev/null
+++ b/vhdl_primitive/fig_3_29.vhd
@@ -0,0 +1,108 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:22:23 06/05/2023
+-- Design Name: Me-type NRZ-to-Manchester encoder
+-- Module Name: fig_3_29 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity fig_3_29 is
+port (
+signal Bin : in std_logic;
+signal clk : in std_logic;
+signal reset : in std_logic;
+signal Bout : out std_logic
+);
+end fig_3_29;
+
+architecture Behavioral of fig_3_29 is
+
+component AND3 is
+port(
+O : out std_ulogic;
+I0 : in std_ulogic;
+I1 : in std_ulogic;
+I2 : in std_ulogic
+);
+end component AND3;
+
+component AND2 is
+port(
+O : out std_ulogic;
+I0 : in std_ulogic;
+I1 : in std_ulogic
+);
+end component AND2;
+
+component OR2 is
+port(
+O : out std_ulogic;
+I0 : in std_ulogic;
+I1 : in std_ulogic
+);
+end component OR2;
+
+component INV is
+port(
+O : out std_ulogic;
+I : in std_ulogic
+);
+end component INV;
+
+component FDR_1 is
+generic(
+INIT : bit := '0'
+);
+port(
+Q : out STD_ULOGIC;
+C : in STD_ULOGIC;
+D : in STD_ULOGIC;
+R : in STD_ULOGIC
+);
+end component FDR_1;
+
+signal gate1,gate2,gate3 : std_logic;
+signal q0,q0b,q1,q1b : std_logic;
+signal binb : std_logic;
+
+begin
+
+inst_INVB : INV port map (O=>binb,I=>Bin);
+
+inst_AND3a : AND3 port map (O=>gate1,I0=>q0b,I1=>q1b,I2=>binb);
+inst_AND3b : AND3 port map (O=>gate2,I0=>q0b,I1=>q1b,I2=>Bin);
+
+inst_FDR1 : FDR_1 generic map (INIT=>'1') port map (Q=>q0,C=>clk,D=>gate1,R=>reset);
+inst_INVFF1 : INV port map (O=>q0b,I=>q0);
+inst_FDR2 : FDR_1 generic map (INIT=>'0') port map (Q=>q1,C=>clk,D=>gate2,R=>reset);
+inst_INVFF2 : INV port map (O=>q1b,I=>q1);
+
+inst_OR : OR2 port map (O=>gate3,I0=>q0,I1=>Bin);
+
+inst_AND2 : AND2 port map (O=>Bout,I0=>gate3,I1=>q1b);
+
+end Behavioral;
+
diff --git a/vhdl_primitive/fig_3_34.ucf b/vhdl_primitive/fig_3_34.ucf
new file mode 100644
index 0000000..40034cb
--- /dev/null
+++ b/vhdl_primitive/fig_3_34.ucf
@@ -0,0 +1,2 @@
+NET "clk" TNM_NET = "CLK_A";
+TIMESPEC "TS_CLKA" = PERIOD "CLK_A" 10 ns;
diff --git a/vhdl_primitive/fig_3_34.vhd b/vhdl_primitive/fig_3_34.vhd
new file mode 100644
index 0000000..aec2681
--- /dev/null
+++ b/vhdl_primitive/fig_3_34.vhd
@@ -0,0 +1,87 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:05:17 06/06/2023
+-- Design Name: Mo-type NRZ-to-Manchester encoder
+-- Module Name: fig_3_34 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity fig_3_34 is
+port (
+signal clk : in std_logic;
+signal reset : in std_logic;
+signal Bin : in std_logic;
+signal Bout : out std_logic
+);
+end fig_3_34;
+
+architecture Behavioral of fig_3_34 is
+
+component NAND2 is
+port(
+O : out std_ulogic;
+I0 : in std_ulogic;
+I1 : in std_ulogic
+);
+end component NAND2;
+
+component FDR_1 is
+generic(
+INIT : bit := '0'
+);
+port(
+Q : out STD_ULOGIC;
+C : in STD_ULOGIC;
+D : in STD_ULOGIC;
+R : in STD_ULOGIC
+);
+end component FDR_1;
+
+component INV is
+port(
+O : out std_ulogic;
+I : in std_ulogic
+);
+end component INV;
+
+signal gate1,gate2,gate3 : std_logic;
+signal q0,q0b,q1,q1b : std_logic;
+
+begin
+
+inst_nand1 : NAND2 port map (O=>gate1,I0=>q1b,I1=>q0);
+inst_nand2 : NAND2 port map (O=>gate2,I0=>q0b,I1=>Bin);
+inst_nand3 : NAND2 port map (O=>gate3,I0=>gate1,I1=>gate2);
+
+inst_FDR1 : FDR_1 port map (Q=>q1,C=>clk,D=>gate3,R=>reset);
+inst_INV1 : INV port map (O=>q1b,I=>q1);
+inst_FDR2 : FDR_1 port map (Q=>q0,C=>clk,D=>q0b,R=>reset);
+inst_INV2 : INV port map (O=>q0b,I=>q0);
+
+Bout <= q1;
+
+end Behavioral;
+
diff --git a/vhdl_primitive/fig_4_10.sch b/vhdl_primitive/fig_4_10.sch
new file mode 100644
index 0000000..2020219
--- /dev/null
+++ b/vhdl_primitive/fig_4_10.sch
@@ -0,0 +1,395 @@
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diff --git a/vhdl_primitive/fig_4_5.vhd b/vhdl_primitive/fig_4_5.vhd
new file mode 100644
index 0000000..e12080a
--- /dev/null
+++ b/vhdl_primitive/fig_4_5.vhd
@@ -0,0 +1,76 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:37:47 06/06/2023
+-- Design Name:
+-- Module Name: fig_4_5 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity fig_4_5 is
+port (
+signal x_in1,x_in2 : in std_logic;
+signal x_in3,x_in4,x_in5 : in std_logic;
+signal y_out : out std_logic
+);
+end fig_4_5;
+
+architecture Behavioral of fig_4_5 is
+
+component AND2 is
+port(
+O : out std_ulogic;
+I0 : in std_ulogic;
+I1 : in std_ulogic
+);
+end component AND2;
+
+component AND3 is
+port(
+O : out std_ulogic;
+I0 : in std_ulogic;
+I1 : in std_ulogic;
+I2 : in std_ulogic
+);
+end component AND3;
+
+component NOR2 is
+port(
+O : out std_ulogic;
+I0 : in std_ulogic;
+I1 : in std_ulogic
+);
+end component NOR2;
+
+signal y1,y2 : std_logic;
+
+begin
+
+inst_AND2 : AND2 port map (O=>y1,I0=>x_in1,I1=>x_in2);
+inst_AND3 : AND3 port map (O=>y2,I0=>x_in3,I1=>x_in4,I2=>x_in5);
+inst_NOR2 : NOR2 port map (O=>y_out,I0=>y1,I1=>y2);
+
+end Behavioral;
+
diff --git a/vhdl_primitive/fig_5_11.sch b/vhdl_primitive/fig_5_11.sch
new file mode 100644
index 0000000..2589177
--- /dev/null
+++ b/vhdl_primitive/fig_5_11.sch
@@ -0,0 +1,279 @@
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diff --git a/vhdl_primitive/fig_5_13.sch b/vhdl_primitive/fig_5_13.sch
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diff --git a/vhdl_primitive/fig_5_38.sch b/vhdl_primitive/fig_5_38.sch
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diff --git a/vhdl_primitive/fig_5_38b.sch b/vhdl_primitive/fig_5_38b.sch
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diff --git a/vhdl_primitive/fig_5_9.sch b/vhdl_primitive/fig_5_9.sch
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diff --git a/vhdl_primitive/fig_p5_15.sch b/vhdl_primitive/fig_p5_15.sch
new file mode 100644
index 0000000..f18cba6
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diff --git a/vhdl_primitive/frequency_meter.vhd b/vhdl_primitive/frequency_meter.vhd
new file mode 100755
index 0000000..4714f6c
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+++ b/vhdl_primitive/frequency_meter.vhd
@@ -0,0 +1,78 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:08:20 04/23/2021
+-- Design Name:
+-- Module Name: frequency_meter - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity frequency_meter is
+generic (
+ fclk : integer := 5;
+ fxmax : integer := 15
+);
+port (
+ clk,x : in bit;
+ test : out bit;
+ fx : out integer range 0 to fxmax
+);
+end frequency_meter;
+
+architecture Behavioral of frequency_meter is
+ signal twindow : bit;
+ signal temp : integer range 0 to fxmax;
+begin
+ p0 : process (clk) is
+ variable count : integer range 0 to fclk;
+ begin
+ if (rising_edge(clk)) then
+ count := count + 1;
+ if (count=fclk) then
+ twindow <= '1';
+ elsif (count=fclk+1) then
+ twindow <= '0';
+ count := 0;
+ end if;
+ end if;
+ end process p0;
+ p1 : process (x,twindow) is
+ variable count : integer range 0 to 20;
+ begin
+ if (twindow='1') then
+ count := 0;
+ elsif (x'event and x='1') then -- rising_edge(x)
+ count := count + 1;
+ end if;
+ temp <= count;
+ end process p1;
+ p2 : process (twindow) is
+ begin
+ if (twindow'event and twindow='1') then -- rising_edge(twindow)
+ fx <= temp;
+ end if;
+ end process p2;
+ test <= twindow;
+end Behavioral;
diff --git a/vhdl_primitive/ftrse.vhd b/vhdl_primitive/ftrse.vhd
new file mode 100755
index 0000000..a412e4d
--- /dev/null
+++ b/vhdl_primitive/ftrse.vhd
@@ -0,0 +1,62 @@
+-------------------------------------------------------------------------------
+-- Copyright (c) 2006 Xilinx, Inc.
+-- All Right Reserved.
+-------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor : Xilinx
+-- \ \ \/ Version : J.23
+-- \ \ Description : Xilinx HDL Macro Library
+-- / / Toggle Flip-Flop with Toggle and Clock Enable and Synchronous Reset and Set
+-- /___/ /\ Filename : FTRSE.vhd
+-- \ \ / \ Timestamp : Tues Jul 18 2006
+-- \___\/\___\
+--
+-- Revision:
+-- 07/18/06 - Initial version.
+-- End Revision
+
+----- CELL FTRSE -----
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FTRSE is
+generic(
+ INIT : bit := '0'
+ );
+
+ port (
+ Q : out STD_LOGIC;
+ C : in STD_LOGIC;
+ CE : in STD_LOGIC;
+ R : in STD_LOGIC;
+ S : in STD_LOGIC;
+ T : in STD_LOGIC
+ );
+end FTRSE;
+
+architecture Behavioral of FTRSE is
+signal q_tmp : std_logic := TO_X01(INIT);
+begin
+
+process(C)
+begin
+ if (C'event and C = '1') then
+ if(R='1') then
+ q_tmp <= '0';
+ elsif(S='1') then
+ q_tmp <= '1';
+ elsif(CE='1') then
+ if(T='1') then
+ q_tmp <= not q_tmp;
+ end if;
+ end if;
+ end if;
+end process;
+
+Q <= q_tmp;
+
+end Behavioral;
+
diff --git a/vhdl_primitive/full_adder_struct.vhd b/vhdl_primitive/full_adder_struct.vhd
new file mode 100755
index 0000000..2351ce0
--- /dev/null
+++ b/vhdl_primitive/full_adder_struct.vhd
@@ -0,0 +1,43 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:28:26 04/23/2021
+-- Design Name:
+-- Module Name: full_adder_struct - struct
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity full_adder_struct is
+Port (
+ a,b,cin : in std_logic;
+ s,cout : out std_logic
+);
+end full_adder_struct;
+
+architecture struct of full_adder_struct is
+begin
+ s <= a xor b xor cin;
+ cout <= (a and b) or (a and cin) or (b and cin);
+end struct;
diff --git a/vhdl_primitive/gate_and.vhd b/vhdl_primitive/gate_and.vhd
new file mode 100755
index 0000000..f64c6c0
--- /dev/null
+++ b/vhdl_primitive/gate_and.vhd
@@ -0,0 +1,37 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_AND is
+generic (
+delay_and : TIME := 1 ps
+);
+port (
+A,B : in STD_LOGIC;
+C : out STD_LOGIC
+);
+end entity GATE_AND;
+
+architecture GATE_AND_BEHAVIORAL_1 of GATE_AND is
+begin
+C <= A and B after delay_and;
+end architecture GATE_AND_BEHAVIORAL_1;
+
+architecture GATE_AND_LUT of GATE_AND is
+ signal T : std_logic;
+begin
+-- LUT2: 2-input Look-Up Table with general output
+-- Spartan-3
+-- Xilinx HDL Libraries Guide, version 14.7
+LUT2_inst : LUT2
+generic map (
+ INIT => "1000")
+port map (
+ O => T, -- LUT general output
+ I0 => A, -- LUT input
+ I1 => B -- LUT input
+);
+-- End of LUT2_inst instantiation
+C <= T after delay_and;
+end architecture GATE_AND_LUT;
diff --git a/vhdl_primitive/gate_not.vhd b/vhdl_primitive/gate_not.vhd
new file mode 100755
index 0000000..506dddb
--- /dev/null
+++ b/vhdl_primitive/gate_not.vhd
@@ -0,0 +1,37 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_NOT is
+generic (
+delay_not : TIME := 1 ps
+);
+port (
+A : in STD_LOGIC;
+B : out STD_LOGIC
+);
+end entity GATE_NOT;
+
+architecture GATE_NOT_BEHAVIORAL_1 of GATE_NOT is
+begin
+B <= not A after delay_not;
+end architecture GATE_NOT_BEHAVIORAL_1;
+
+architecture GATE_NOT_LUT of GATE_NOT is
+ signal T : std_logic;
+begin
+-- LUT2: 2-input Look-Up Table with general output
+-- Spartan-3
+-- Xilinx HDL Libraries Guide, version 14.7
+LUT2_inst : LUT2
+generic map (
+ INIT => "0001")
+port map (
+ O => T, -- LUT general output
+ I0 => A, -- LUT input
+ I1 => A -- LUT input
+);
+-- End of LUT2_inst instantiation
+B <= T after delay_not;
+end architecture GATE_NOT_LUT;
diff --git a/vhdl_primitive/gate_or.vhd b/vhdl_primitive/gate_or.vhd
new file mode 100755
index 0000000..223e651
--- /dev/null
+++ b/vhdl_primitive/gate_or.vhd
@@ -0,0 +1,37 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_OR is
+generic (
+delay_or : TIME := 1 ps
+);
+port (
+A,B : in STD_LOGIC;
+C : out STD_LOGIC
+);
+end entity GATE_OR;
+
+architecture GATE_OR_BEHAVIORAL_1 of GATE_OR is
+begin
+C <= A or B after delay_or;
+end architecture GATE_OR_BEHAVIORAL_1;
+
+architecture GATE_OR_LUT of GATE_OR is
+ signal T : std_logic;
+begin
+-- LUT2: 2-input Look-Up Table with general output
+-- Spartan-3
+-- Xilinx HDL Libraries Guide, version 14.7
+LUT2_inst : LUT2
+generic map (
+ INIT => "1110")
+port map (
+ O => T, -- LUT general output
+ I0 => A, -- LUT input
+ I1 => B -- LUT input
+);
+-- End of LUT2_inst instantiation
+C <= T after delay_or;
+end architecture GATE_OR_LUT;
\ No newline at end of file
diff --git a/vhdl_primitive/gate_xnor.vhd b/vhdl_primitive/gate_xnor.vhd
new file mode 100755
index 0000000..755dae3
--- /dev/null
+++ b/vhdl_primitive/gate_xnor.vhd
@@ -0,0 +1,28 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity GATE_XNOR is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end entity GATE_XNOR;
+
+architecture GATE_XNOR_BEHAVIORAL_1 of GATE_XNOR is
+component GAND is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GOR is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GOR;
+component GN is
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc,sd,se,sf,sg: STD_LOGIC;
+begin
+g1: GN port map (A,sa);
+g2: GN port map (B,sb);
+g3: GAND port map (A,B,sc);
+g4: GAND port map (sa,sb,sd);
+g5: GOR port map (sc,sd,C);
+end architecture GATE_XNOR_BEHAVIORAL_1;
diff --git a/vhdl_primitive/gate_xor.vhd b/vhdl_primitive/gate_xor.vhd
new file mode 100755
index 0000000..abb3882
--- /dev/null
+++ b/vhdl_primitive/gate_xor.vhd
@@ -0,0 +1,51 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity GATE_XOR is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end entity GATE_XOR;
+
+architecture GATE_XOR_BEHAVIORAL_1 of GATE_XOR is
+component GAND is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GOR is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GOR;
+component GN is
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc,sd: STD_LOGIC;
+begin
+g1: GN port map (A,sa);
+g2: GN port map (B,sb);
+g3: GAND port map (sa,B,sc);
+g4: GAND port map (A,sb,sd);
+g5: GOR port map (sc,sd,C);
+end architecture GATE_XOR_BEHAVIORAL_1;
+
+architecture GATE_XOR_BEHAVIORAL_2 of GATE_XOR is
+component GAND is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GOR is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GOR;
+component GN is
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc,sd,se: STD_LOGIC;
+begin
+g1: GN port map (A,sa);
+g2: GN port map (B,sb);
+g3: GOR port map (sa,sb,sc);
+g4: GAND port map (A,sc,sd);
+g5: GAND port map (B,sc,se);
+g6: GOR port map (sd,se,C);
+end architecture GATE_XOR_BEHAVIORAL_2;
diff --git a/vhdl_primitive/generic_mux.vhd b/vhdl_primitive/generic_mux.vhd
new file mode 100755
index 0000000..df11984
--- /dev/null
+++ b/vhdl_primitive/generic_mux.vhd
@@ -0,0 +1,49 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:47:26 04/23/2021
+-- Design Name:
+-- Module Name: generic_mux - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity generic_mux is
+Generic (
+ M : integer := 4;
+ N : integer := 3
+);
+Port (
+ x : in matrix (0 to M-1,N-1 downto 0);
+ sel : in integer range 0 to M-1;
+ y : out bit_vector(N-1 downto 0)
+);
+end generic_mux;
+
+architecture Behavioral of generic_mux is
+begin
+ chain : for i in N-1 downto 0 generate
+ y(i) <= x(sel,i);
+ end generate chain;
+end Behavioral;
diff --git a/vhdl_primitive/git_log.txt b/vhdl_primitive/git_log.txt
new file mode 100755
index 0000000..cfebc2c
--- /dev/null
+++ b/vhdl_primitive/git_log.txt
@@ -0,0 +1,53 @@
+commit bd3768793ea02f61d5cb688a765a3d933f3ec976
+Author: kedziorno
+Date: Tue Sep 15 21:14:02 2020 +0200
+
+ reimplement ff_d_gated,add delays to and,or,not - todo check the behaviour of ff_d_gates with new delays
+
+commit 730edcdc940ee688d422488d2ecff08f550d0ed7
+Author: kedziorno
+Date: Tue Sep 15 15:56:30 2020 +0200
+
+ add delay to gates
+
+commit c3a25f087afcf8a1f484752838446dc499049cc2
+Author: kedziorno
+Date: Wed Sep 9 16:59:03 2020 +0200
+
+ add full_adder and tb
+
+commit 728fc5ed339ef3e0f7c51ac3a8c2671bace8951f
+Author: kedziorno
+Date: Wed Sep 9 16:37:11 2020 +0200
+
+ add half_adder and tb
+
+commit 037e657e4d44f32171c98e1f2eca4bea32aa86db
+Author: kedziorno
+Date: Mon Aug 10 02:48:35 2020 +0200
+
+ refac tb_gates
+
+commit 2504dfb899407f83d5b25a34af474c897c976794
+Author: kedziorno
+Date: Mon Aug 10 02:33:30 2020 +0200
+
+ add tb_ for XNOR,FF_SR_GATED,FF_D_GATED
+
+commit 3ea2e7ffe504083f15c9313102c995659f6fc835
+Author: kedziorno
+Date: Sat Aug 8 19:21:57 2020 +0200
+
+ TB_FF_SR
+
+commit 2071df1b58e60f4807f4ceb319cff29ada753195
+Author: kedziorno
+Date: Sat Aug 8 15:46:32 2020 +0200
+
+ add new modules
+
+commit 516134f171fdc8df9423b3b9d6495f8828c0cb13
+Author: kedziorno
+Date: Sat Aug 8 15:30:20 2020 +0200
+
+ initial project with some gates
diff --git a/vhdl_primitive/graycode.vhd b/vhdl_primitive/graycode.vhd
new file mode 100755
index 0000000..e7104b2
--- /dev/null
+++ b/vhdl_primitive/graycode.vhd
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity graycode is
+generic (G_SIZE : integer);
+port (
+ reset : in std_logic;
+ clk : in std_logic;
+ enable : in std_logic;
+ input : in std_logic_vector (G_SIZE-1 downto 0);
+ output : out std_logic_vector (G_SIZE-1 downto 0)
+);
+end entity;
+
+architecture rtl of graycode is
+
+ signal count_i : std_logic_vector (G_SIZE-1 downto 0);
+
+begin
+
+ p0 : process (reset, clk)
+ begin
+ if (reset = '1') then
+ count_i <= (others => '0');
+ elsif (rising_edge(clk)) then
+ if (enable = '1') then
+ count_i(G_SIZE-1 downto 0) <= input(G_SIZE-1 downto 0) xor ('0' & input(G_SIZE-1 downto 1));
+ else
+ count_i <= count_i;
+ end if;
+ end if;
+ end process;
+
+ output <= count_i;
+
+end architecture;
+
diff --git a/vhdl_primitive/hurst_gates.vhd b/vhdl_primitive/hurst_gates.vhd
new file mode 100755
index 0000000..1b7cdf7
--- /dev/null
+++ b/vhdl_primitive/hurst_gates.vhd
@@ -0,0 +1,48 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:37:54 05/08/2021
+-- Design Name:
+-- Module Name: hurst_gates - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity hurst_gates is
+Port (
+a,b,c : in std_logic;
+y1,y2,y3,y4,y5,y6 : out std_logic
+);
+end hurst_gates;
+
+architecture Behavioral of hurst_gates is
+begin
+ y1 <= ((not a) and (not b)) or (a and b and c); --(a xnor b) and ((not a) or c);
+ y2 <= (a and b and c) or ((not a) or (not b) or c) or ((not a) or b or (not c)); --((b xor c) and (not a)) or (a and b and c);
+ y3 <= a and ((b and c) or ((not b) or (not c))); --(b xnor c) and a;
+ y4 <= (a and b and c) or (a and (not b) and (not c)); --(a xnor b) and (b xnor c);
+ y5 <= (a and b) or ((not a) and (not c));
+ y6 <= (a and b and c) or ((not a) and (not c)) or ((not b) and (not c)); --(a and b) xnor c;
+end Behavioral;
+
diff --git a/vhdl_primitive/inv_gate_multilevel_parallel_carry_forward.vhd b/vhdl_primitive/inv_gate_multilevel_parallel_carry_forward.vhd
new file mode 100755
index 0000000..9fd028a
--- /dev/null
+++ b/vhdl_primitive/inv_gate_multilevel_parallel_carry_forward.vhd
@@ -0,0 +1,124 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:49:32 06/20/2022
+-- Design Name:
+-- Module Name: inv_gate_multilevel_parallel_carry_forward - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity inv_gate_multilevel_parallel_carry_forward is
+generic (
+ N : integer := 2;
+ M : integer := 5
+);
+port (
+ signal i_in : in std_logic_vector(N-1 downto 0);
+ signal o_and : out std_logic;
+-- signal o_or : out std_logic
+ signal o_or : out std_logic_vector(M-1 downto 0)
+);
+end inv_gate_multilevel_parallel_carry_forward;
+
+architecture Behavioral of inv_gate_multilevel_parallel_carry_forward is
+
+signal a : std_logic_vector(M-1 downto 0);
+signal a1 : std_logic_vector(M-1 downto 0);
+--signal b : std_logic_vector(N-1 downto 0);
+--signal b1 : std_logic_vector(N-1 downto 0);
+
+begin
+
+--o_or <= a(M-1);
+--o_or <= b(N-1);
+
+--g1 : for i in 0 to M-1 generate
+--begin
+-- aa : block
+-- begin
+ pa : process (a1) is
+ variable ff : std_logic;
+ begin
+-- ff := a1(0);
+ lb : for i in 1 to M-1 loop
+-- ff := ff or a1(i);
+ lc : for j in 1 to i loop
+-- ff := a1(i);
+-- la : for j in 1 to i loop
+ a(i) <= a(j) or a1(j-1);
+-- end loop la;
+ end loop lc;
+-- a(i) <= ff;
+ end loop lb;
+ end process pa;
+-- end block aa;
+--end generate g1;
+
+--g2 : for i in 0 to M-1 generate
+--begin
+-- ab : block
+-- begin
+-- pb : process (b1) is
+-- variable fg : std_logic := b1(i);
+-- begin
+-- la : for j in i to N-1 loop
+-- fg := fg and b1(j-1);
+-- end loop la;
+-- o_and <= fg;
+-- end process pb;
+-- end block ab;
+--end generate g2;
+
+g0 : for i in 0 to M-1 generate
+begin
+ b0 : block
+ begin
+ p0or : process (i_in) is
+ attribute Keep : string;
+ variable j : std_logic := '0';
+ attribute keep of j : variable is "true";
+ begin
+-- j := '0';
+ for k in 0 to N-1 loop
+ j := j or i_in(k);
+ end loop k;
+-- a1(i) <= j;
+ o_or(i) <= j;
+ end process p0or;
+ end block b0;
+-- b1 : block
+-- begin
+-- p0and : process (i_in) is
+-- variable j : std_logic := '1';
+-- begin
+-- for k in 0 to N-1 loop
+-- j := j and i_in(k);
+-- end loop k;
+-- b1(i) <= j;
+-- end process p0and;
+-- end block b1;
+end generate g0;
+
+end Behavioral;
diff --git a/vhdl_primitive/lcd_display.vhd b/vhdl_primitive/lcd_display.vhd
new file mode 100755
index 0000000..33246e0
--- /dev/null
+++ b/vhdl_primitive/lcd_display.vhd
@@ -0,0 +1,134 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:24:00 11/28/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/memorymodule/lcd_display.vhd
+-- Project Name: memorymodule
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_globals.ALL;
+use WORK.p_lcd_display.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity lcd_display is
+Generic (
+ G_BOARD_CLOCK : integer := 1;
+ LCDClockDivider : integer := 1
+);
+Port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_LCDChar : LCDHex;
+ o_anode : out std_logic_vector(G_LCDAnode-1 downto 0);
+ o_segment : out std_logic_vector(G_LCDSegment-1 downto 0)
+);
+end lcd_display;
+
+architecture Behavioral of lcd_display is
+
+ component clock_divider is
+ Generic(
+ g_board_clock : integer;
+ g_divider : integer
+ );
+ Port(
+ i_clock : in STD_LOGIC;
+ i_reset : in STD_LOGIC;
+ o_clock : out STD_LOGIC
+ );
+ end component clock_divider;
+ for all : clock_divider use entity work.clock_divider(Behavioral);
+
+ signal clock_divider_1 : std_logic;
+
+begin
+
+ c_clock_divider_1 : clock_divider
+ Generic Map (
+ g_board_clock => G_BOARD_CLOCK,
+ g_divider => LCDClockDivider
+ )
+ Port Map (
+ i_clock => i_clock,
+ i_reset => i_reset,
+ o_clock => clock_divider_1
+ );
+
+ p0 : process (clock_divider_1) is
+ variable count : integer range 0 to G_LCDAnode := 0;
+ begin
+ if (rising_edge(clock_divider_1)) then
+ case count is
+ when 0 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "0111";
+ when 1 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1011";
+ when 2 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1101";
+ when 3 =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1110";
+ when others =>
+ o_anode(G_LCDAnode-1 downto 0) <= "1111";
+ end case;
+ if (count = G_LCDAnode-1) then
+ count := 0;
+ else
+ count := count + 1;
+ end if;
+ end if;
+ end process p0;
+
+ p1 : process (clock_divider_1) is
+ variable count : integer range 0 to G_LCDAnode := 0;
+ begin
+ if (rising_edge(clock_divider_1)) then
+ case to_integer(unsigned(i_LCDChar(count))) is
+ when 0 => o_segment <= "1000000"; -- 0
+ when 1 => o_segment <= "1111001"; -- 1
+ when 2 => o_segment <= "0100100"; -- 2
+ when 3 => o_segment <= "0110000"; -- 3
+ when 4 => o_segment <= "0011001"; -- 4
+ when 5 => o_segment <= "0010010"; -- 5
+ when 6 => o_segment <= "0000010"; -- 6
+ when 7 => o_segment <= "1111000"; -- 7
+ when 8 => o_segment <= "0000000"; -- 8
+ when 9 => o_segment <= "0010000"; -- 9
+ when 10 => o_segment <= "0001000"; -- a
+ when 11 => o_segment <= "0000011"; -- b
+ when 12 => o_segment <= "1000110"; -- c
+ when 13 => o_segment <= "0100001"; -- d
+ when 14 => o_segment <= "0000110"; -- e
+ when 15 => o_segment <= "0001110"; -- f
+ when others => null;
+ end case;
+ if (count = G_LCDAnode-1) then
+ count := 0;
+ else
+ count := count + 1;
+ end if;
+ end if;
+ end process p1;
+
+end Behavioral;
+
diff --git a/vhdl_primitive/leading_zeros.vhd b/vhdl_primitive/leading_zeros.vhd
new file mode 100755
index 0000000..d9fa88e
--- /dev/null
+++ b/vhdl_primitive/leading_zeros.vhd
@@ -0,0 +1,54 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:06:31 04/23/2021
+-- Design Name:
+-- Module Name: leading_zeros - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity leading_zeros is
+Generic (
+ N : integer := 8
+);
+Port (
+ x : in std_logic_vector(N-1 downto 0);
+ y : out integer range 0 to N
+);
+end leading_zeros;
+
+architecture Behavioral of leading_zeros is
+begin
+ p0 : process(x) is
+ variable temp : integer range 0 to N;
+ begin
+ temp := 0;
+ loop0 : for i in x'range loop
+ exit when x(i) = '1';
+ temp := temp + 1;
+ end loop loop0;
+ y <= temp;
+ end process p0;
+end Behavioral;
diff --git a/vhdl_primitive/leddet.vhd b/vhdl_primitive/leddet.vhd
new file mode 100755
index 0000000..173127d
--- /dev/null
+++ b/vhdl_primitive/leddet.vhd
@@ -0,0 +1,65 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:03:28 05/09/2021
+-- Design Name:
+-- Module Name: leddet - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+-- XXX detect first RE
+Entity LEDDET Is
+Port( Clock : In Std_Ulogic;
+Reset : In Std_Ulogic;
+Trigger: In Std_Ulogic;
+LED : Out Std_Ulogic);
+End LEDDET;
+Architecture RTL of LEDDET is
+Type Seq_state is (S0, S1);
+Signal State: Seq_state;
+Begin
+LED_EX:Process(Clock, Reset)
+Begin
+If Reset='1' then
+LED<='0';
+State<=s0;
+Elsif Rising_Edge(Clock) then
+Case State is -- w jakim jestem stanie?
+When S0=>
+If Trigger='1' then
+LED<='1' after 5ns;
+State<=s1;
+End If;
+When S1=>
+LED<='0' AFTER 5ns;
+If Trigger='0' then
+State<=s0;
+End If;
+End Case;
+End If;
+End Process LED_EX;
+End RTL;
+
+
diff --git a/vhdl_primitive/lfsr.vhd b/vhdl_primitive/lfsr.vhd
new file mode 100755
index 0000000..008183c
--- /dev/null
+++ b/vhdl_primitive/lfsr.vhd
@@ -0,0 +1,40 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+-- https://semiwiki.com/fpga/6129-pseudo-random-generator-tutorial-in-vhdl-part-1-3/
+
+entity lfsr1 is
+generic (G_SIZE : integer);
+port (
+ reset : in std_logic;
+ clk : in std_logic;
+ enable : in std_logic;
+ count : out std_logic_vector (G_SIZE-1 downto 0) -- lfsr output
+);
+end entity;
+
+architecture rtl of lfsr1 is
+
+ signal count_i : std_logic_vector (G_SIZE-1 downto 0);
+ signal feedback : std_logic;
+
+begin
+
+ feedback <= not(count_i(G_SIZE-1) xor count_i(G_SIZE-2)); -- LFSR size 4
+
+ process (reset, clk)
+ begin
+ if (reset = '1') then
+ count_i <= (others => '0');
+ elsif (rising_edge(clk)) then
+ if (enable = '1') then
+ count_i <= count_i(G_SIZE-2 downto 0) & feedback;
+ else
+ count_i <= count_i;
+ end if;
+ end if;
+ end process;
+
+ count <= count_i;
+
+end architecture;
diff --git a/vhdl_primitive/logic_analyser.vhd b/vhdl_primitive/logic_analyser.vhd
new file mode 100755
index 0000000..2ebca39
--- /dev/null
+++ b/vhdl_primitive/logic_analyser.vhd
@@ -0,0 +1,455 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:28:43 05/04/2021
+-- Design Name:
+-- Module Name: logic_analyser - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_globals.ALL;
+use WORK.p_lcd_display.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity logic_analyser is
+Generic (
+G_BOARD_CLOCK : integer := G_BOARD_CLOCK;
+G_BAUD_RATE : integer := 9_600;
+address_size : integer := 4;
+data_size : integer := 8;
+G_RC_N : integer := G_DEBOUNCE_MS_BITS;
+G_RC_MAX : integer := G_DEBOUNCE_MS_COUNT
+);
+Port (
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_catch : in std_logic;
+i_data : in std_logic_vector(data_size-1 downto 0);
+o_rs232_tx : out std_logic;
+o_sended : out std_logic;
+o_seg : out std_logic_vector(G_LCDSegment-1 downto 0);
+--o_dp : out std_logic;
+o_an : out std_logic_vector(G_LCDAnode-1 downto 0);
+o_data : out std_logic_vector(G_Led-1 downto 0)
+);
+end logic_analyser;
+
+architecture Behavioral of logic_analyser is
+
+component nxp_74hc573 is
+generic (
+nbit : integer := 8
+);
+port (
+i_le : in std_logic;
+i_oeb : in std_logic;
+i_d : in std_logic_vector(nbit-1 downto 0);
+o_q : out std_logic_vector(nbit-1 downto 0)
+);
+end component nxp_74hc573;
+
+component sram_62256 is
+Generic (
+address_size : integer := 8;
+data_size : integer := 8
+);
+Port (
+i_ceb : in STD_LOGIC;
+i_web : in STD_LOGIC;
+i_oeb : in STD_LOGIC;
+i_address : in STD_LOGIC_VECTOR (address_size-1 downto 0);
+i_data : in STD_LOGIC_VECTOR (data_size-1 downto 0);
+o_data : out STD_LOGIC_VECTOR (data_size-1 downto 0)
+);
+end component sram_62256;
+
+component ripple_counter is
+Generic (
+N : integer := 32;
+MAX : integer := 1
+);
+Port (
+i_clock : in std_logic;
+i_cpb : in std_logic;
+i_mrb : in std_logic;
+o_q : inout std_logic_vector(N-1 downto 0);
+i_ud : in std_logic;
+o_ping : out std_logic
+);
+end component ripple_counter;
+
+component rs232 is
+Generic (
+G_BOARD_CLOCK : integer := G_BOARD_CLOCK;
+G_BAUD_RATE : integer := G_BAUD_RATE
+);
+Port(
+clk : in STD_LOGIC;
+rst : in STD_LOGIC;
+enable_tx : in STD_LOGIC;
+--enable_rx : in STD_LOGIC;
+byte_to_send : in STD_LOGIC_VECTOR (7 downto 0);
+--byte_received : out STD_LOGIC_VECTOR (7 downto 0);
+--parity_tx : out STD_LOGIC;
+--parity_rx : out STD_LOGIC;
+busy : out STD_LOGIC;
+ready : out STD_LOGIC;
+--is_byte_received : out STD_LOGIC;
+is_byte_sended : out STD_LOGIC;
+RsTx : out STD_LOGIC
+--RsRx : in STD_LOGIC
+);
+end component rs232;
+
+component GATE_AND is
+generic (
+delay_and : TIME := 1 ns
+);
+port (
+A,B : in STD_LOGIC;
+C : out STD_LOGIC
+);
+end component GATE_AND;
+
+component GATE_NOT is
+generic (
+delay_not : TIME := 1 ns
+);
+port (
+A : in STD_LOGIC;
+B : out STD_LOGIC
+);
+end component GATE_NOT;
+
+component FF_D_POSITIVE_EDGE is
+port (C,D:in STD_LOGIC;Q1,Q2:inout STD_LOGIC);
+end component FF_D_POSITIVE_EDGE;
+
+component new_debounce is
+generic ( -- ripplecounter N bits (RC_N=N+1,RC_MAX=2**N)
+G_RC_N : integer := 5;
+G_RC_MAX : integer := 16
+);
+port (
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_b : in std_logic;
+o_db : out std_logic
+);
+end component new_debounce;
+
+component lcd_display is
+Generic (
+G_BOARD_CLOCK : integer := 1;
+LCDClockDivider : integer := 1
+);
+Port (
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_LCDChar : LCDHex;
+o_anode : out std_logic_vector(G_LCDAnode-1 downto 0);
+o_segment : out std_logic_vector(G_LCDSegment-1 downto 0)
+);
+end component lcd_display;
+
+signal latch_le,latch_oeb : std_logic;
+signal latch_d,latch_q : std_logic_vector(data_size-1 downto 0);
+signal sram_ceb,sram_web,sram_oeb : std_logic;
+signal sram_address : std_logic_vector(address_size-1 downto 0);
+signal sram_di,sram_do : std_logic_vector(data_size-1 downto 0);
+signal rc_clock,rc_cpb,rc_mrb,rc_ud,rc_ping : std_logic;
+signal rc_oq : std_logic_vector(address_size downto 0);
+signal rs232_etx,rs232_tx,rs232_byte_sended,rs232_busy,rs232_ready : std_logic;
+signal rs232_b2s : std_logic_vector(7 downto 0);
+signal wr,rd,a,b : std_logic;
+signal catch : std_logic;
+signal LCDChar : LCDHex;
+signal reset_db : std_logic;
+
+constant WAIT_AND : time := 3 ps;
+constant WAIT_NOT : time := 2 ps;
+
+type state_type is (
+idle,start,start_count,check_catch,check_write,wait0,wait1,
+--wait_catch,
+read0,
+st_enable_tx,st_rs232_waiting,st_disable_tx,
+stop
+);
+signal state_c,state_n : state_type;
+
+begin
+
+p0 : process (i_clock,i_reset) is
+begin
+ if (i_reset = '1') then
+ state_c <= idle;
+ elsif (rising_edge(i_clock)) then
+ state_c <= state_n;
+ end if;
+end process p0;
+
+latch_le <= '1' when rc_clock = '0' else '0';
+--latch_oeb <= '0' when (i_clock = '0' and wr = '1') else '0';
+latch_oeb <= '1' when rd = '1' else '0'; -- XXX todo
+sram_web <= '0' when latch_le = '0' else '1';
+sram_oeb <= '0' when rd = '1' and state_c = read0 else '1';
+rc_clock <= not i_clock when (wr = '1' and catch = '1') or (rd = '1' and rs232_etx = '1' and rs232_byte_sended = '1') else '0';
+sram_ceb <= '0' when rc_clock = '1' or rs232_etx = '0' else '1';
+--rc_mrb <= '1' when i_reset = '1' else '0';
+rc_ping <= '0';
+
+db_entity : new_debounce
+generic map (
+G_RC_N => G_RC_N,
+G_RC_MAX => G_RC_MAX
+)
+port map (
+i_clock => i_clock,
+i_reset => reset_db,
+i_b => i_catch,
+o_db => catch
+);
+
+lcddisplay_entity : lcd_display
+Generic Map (
+ G_BOARD_CLOCK => G_BOARD_CLOCK,
+ LCDClockDivider => G_LCDClockDivider
+)
+Port Map (
+ i_clock => i_clock,
+ i_reset => i_reset,
+ i_LCDChar => LCDChar,
+ o_anode => o_an,
+ o_segment => o_seg
+);
+
+p1 : process (state_c,rs232_etx,rs232_byte_sended,sram_address,catch) is
+begin
+-- state_n <= state_c;
+ reset_db <= '0';
+-- o_data <= (others => '0');
+-- o_sended <= '0';
+-- rd <= '1';
+-- wr <= '1';
+-- rc_mrb <= '0';
+-- rs232_etx <= '0';
+-- LCDChar <= (x"0",x"0",x"0",x"0");
+ case (state_c) is
+ when idle =>
+ rs232_etx <= '0';
+ reset_db <= '1';
+ state_n <= start_count;
+ rd <= '0';
+ wr <= '0';
+ rc_cpb <= '1';
+ rc_ud <= '1';
+ rc_mrb <= '1';
+ rs232_etx <= '0';
+ o_sended <= '0';
+ LCDChar <= (x"f",x"0",x"1",x"f");
+ o_data <= "00000001";
+ when start_count =>
+ wr <= '0';
+ rd <= '0';
+ o_sended <= '0';
+ rs232_etx <= '0';
+ state_n <= start;
+ rc_mrb <= '0';
+ LCDChar <= (x"0",x"0",x"0",x"0");
+ o_data <= "00000010";
+ when start =>
+ rc_mrb <= '0';
+ rd <= '0';
+ o_sended <= '0';
+ rs232_etx <= '0';
+ reset_db <= '1';
+ state_n <= check_catch;
+ wr <= '1';
+ LCDChar <= (x"1",x"0",x"0",x"0");
+ o_data <= "00000100";
+ when check_catch =>
+ rc_mrb <= '0';
+ wr <= '1';
+ rd <= '0';
+ o_sended <= '0';
+ rs232_etx <= '0';
+ if (catch = '1') then
+ state_n <= check_write;
+ else
+ state_n <= check_catch;
+ end if;
+ o_data <= "00001000";
+ LCDChar <= (x"2",x"2",x"2",x"2");
+ when check_write =>
+ rc_mrb <= '0';
+ wr <= '1';
+ rd <= '0';
+ o_sended <= '0';
+ rs232_etx <= '0';
+ reset_db <= '1';
+ if (to_integer(unsigned(sram_address)) = 2**address_size-1) then
+ state_n <= wait0;
+ LCDChar <= (x"2",x"0",x"0",x"0");
+ else
+-- state_n <= wait_catch;
+ state_n <= start;
+ LCDChar <= (x"3",x"0",x"0",x"0");
+ end if;
+ o_data <= "00010000";
+-- when wait_catch =>
+-- state_n <= start;
+-- reset_db <= '1';
+ when wait0 =>
+ wr <= '0';
+ rd <= '0';
+ o_sended <= '0';
+ state_n <= wait1;
+ rs232_etx <= '0';
+ rc_mrb <= '1';
+ o_data <= (others => '0');
+ LCDChar <= (x"0",x"0",x"0",x"0");
+ when wait1 =>
+ wr <= '0';
+ rd <= '0';
+ o_sended <= '0';
+ state_n <= read0;
+ rs232_etx <= '0';
+ rc_mrb <= '0';
+ o_data <= (others => '0');
+ LCDChar <= (x"0",x"0",x"0",x"0");
+ when read0 =>
+ rc_mrb <= '0';
+ wr <= '0';
+ o_sended <= '0';
+ rd <= '1';
+ rs232_etx <= '0';
+ if (to_integer(unsigned(sram_address)) = 2**address_size-1) then
+ LCDChar <= (x"6",x"0",x"0",x"0");
+ state_n <= stop;
+ else
+ LCDChar <= (x"7",x"0",x"0",x"0");
+ state_n <= st_enable_tx;
+ end if;
+ o_data <= "00100000";
+ when st_enable_tx =>
+ rc_mrb <= '0';
+ wr <= '0';
+ rd <= '1';
+ o_sended <= '0';
+ state_n <= st_rs232_waiting;
+ rs232_etx <= '1';
+ o_data <= (others => '0');
+ LCDChar <= (x"0",x"0",x"0",x"0");
+ when st_rs232_waiting =>
+ rc_mrb <= '0';
+ wr <= '0';
+ rd <= '1';
+ o_sended <= '0';
+ rs232_etx <= '1';
+ if (rs232_byte_sended = '1') then
+ state_n <= st_disable_tx;
+ LCDChar <= (x"8",x"0",x"0",x"0");
+ else
+ state_n <= st_rs232_waiting;
+ LCDChar <= (x"9",x"0",x"0",x"0");
+ end if;
+ o_data <= "01000000";
+ when st_disable_tx =>
+ rc_mrb <= '0';
+ wr <= '0';
+ rd <= '1';
+ o_sended <= '0';
+ state_n <= read0;
+ rs232_etx <= '0';
+ o_data <= (others => '0');
+ LCDChar <= (x"A",x"0",x"0",x"0");
+ when stop =>
+ rc_mrb <= '0';
+ wr <= '0';
+ rd <= '1';
+ state_n <= idle;
+ o_sended <= '1';
+ rs232_etx <= '0';
+ LCDChar <= (x"B",x"0",x"0",x"0");
+ o_data <= "10000000";
+ end case;
+end process p1;
+
+latch_d <= i_data;
+sram_di <= latch_q;
+sram_address <= rc_oq(address_size-1 downto 0);
+rs232_b2s <= sram_do;
+o_rs232_tx <= rs232_tx;
+
+latch_entity : nxp_74hc573
+generic map (nbit=>data_size)
+port map (
+i_le=>latch_le,
+i_oeb=>latch_oeb,
+i_d=>latch_d,
+o_q=>latch_q
+);
+
+sram_entity : sram_62256
+Generic map (address_size=>address_size,data_size=>data_size)
+Port map (
+i_ceb=>sram_ceb,
+i_web=>sram_web,
+i_oeb=>sram_oeb,
+i_address=>sram_address,
+i_data=>sram_di,
+o_data=>sram_do
+);
+
+rc_entity : ripple_counter
+Generic map (N=>address_size+1,MAX=>2**address_size)
+Port map (
+i_clock=>rc_clock,
+i_cpb=>rc_cpb,
+i_mrb=>rc_mrb,
+i_ud=>rc_ud,
+o_q=>rc_oq,
+o_ping=>rc_ping
+);
+
+rs232_entity : rs232
+Generic map (G_BOARD_CLOCK=>G_BOARD_CLOCK,G_BAUD_RATE=>G_BAUD_RATE)
+Port map (
+clk=>i_clock,
+rst=>i_reset,
+enable_tx=>rs232_etx,
+--enable_rx=>'0',
+byte_to_send=>rs232_b2s,
+--byte_received=>open,
+--parity_tx=>open,
+--parity_rx=>open,
+busy=>rs232_busy,
+ready=>rs232_ready,
+----is_byte_received=>open,
+is_byte_sended=>rs232_byte_sended,
+RsTx=>rs232_tx
+--RsRx=>rs232_rx
+);
+
+end Behavioral;
diff --git a/vhdl_primitive/mem_decoder_col.vhd b/vhdl_primitive/mem_decoder_col.vhd
new file mode 100755
index 0000000..69ffec2
--- /dev/null
+++ b/vhdl_primitive/mem_decoder_col.vhd
@@ -0,0 +1,80 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:41:34 04/26/2021
+-- Design Name:
+-- Module Name: mem_decoder_col - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity mem_decoder_col is
+Generic (
+ constant C_DECODER_2x4_OUT : integer := 4
+);
+Port (
+ signal decoder_col_input : in std_logic_vector(4-1 downto 0);
+ signal decoder_col_output : out std_logic_vector(2**4-1 downto 0);
+ signal e : std_logic
+);
+end mem_decoder_col;
+
+architecture Behavioral of mem_decoder_col is
+ signal enable_a_col : std_logic_vector(C_DECODER_2x4_OUT-1 downto 0);
+ component D2_4E is port(D0:out std_logic;D1:out std_logic;D2:out std_logic;D3:out std_logic;A0:in std_logic;A1:in std_logic;E:in std_logic); end component D2_4E;
+begin
+
+--Work
+--a : for i in (2**(decoder_col_input'left+1))-1 downto 0 generate
+-- decoder_col_output(i) <= '1' when (i=to_integer(unsigned(decoder_col_input))) else '0';
+--end generate a;
+
+ bbb : for i in 0 to 1 generate
+ begin
+ qqq : if (i = 0) generate
+ a : D2_4E port map (
+ D0=>enable_a_col(0),
+ D1=>enable_a_col(1),
+ D2=>enable_a_col(2),
+ D3=>enable_a_col(3),
+ A0=>decoder_col_input(0),
+ A1=>decoder_col_input(1),
+ E=>e);
+ end generate qqq;
+ www : if (i = 1) generate
+ b : for j in 0 to C_DECODER_2x4_OUT-1 generate
+ begin
+ c : D2_4E
+ port map (
+ D0=>decoder_col_output(C_DECODER_2x4_OUT*j+0),
+ D1=>decoder_col_output(C_DECODER_2x4_OUT*j+1),
+ D2=>decoder_col_output(C_DECODER_2x4_OUT*j+2),
+ D3=>decoder_col_output(C_DECODER_2x4_OUT*j+3),
+ A0=>decoder_col_input(2),
+ A1=>decoder_col_input(3),
+ E=>enable_a_col(j));
+ end generate b;
+ end generate www;
+ end generate bbb;
+end Behavioral;
diff --git a/vhdl_primitive/mem_decoder_row.vhd b/vhdl_primitive/mem_decoder_row.vhd
new file mode 100755
index 0000000..ea9b6c4
--- /dev/null
+++ b/vhdl_primitive/mem_decoder_row.vhd
@@ -0,0 +1,68 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:59:12 04/25/2021
+-- Design Name:
+-- Module Name: mem_decoder_row - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity mem_decoder_row is
+Port (
+ signal decoder_row_input : in std_logic_vector(4-1 downto 0);
+ signal decoder_row_output : out std_logic_vector(2**4-1 downto 0);
+ e : in std_logic
+);
+end mem_decoder_row;
+
+architecture Behavioral of mem_decoder_row is
+ component D4_16E is port(D0:out std_logic;D1:out std_logic;D2:out std_logic;D3:out std_logic;D4:out std_logic;D5:out std_logic;D6:out std_logic;D7:out std_logic;D8:out std_logic;D9:out std_logic;D10:out std_logic;D11:out std_logic;D12:out std_logic;D13:out std_logic;D14:out std_logic;D15:out std_logic;A0:in std_logic;A1:in std_logic;A2:in std_logic;A3:in std_logic;E:in std_logic); end component D4_16E;
+begin
+
+a : D4_16E
+port map (
+D0=>decoder_row_output(0),
+D1=>decoder_row_output(1),
+D2=>decoder_row_output(2),
+D3=>decoder_row_output(3),
+D4=>decoder_row_output(4),
+D5=>decoder_row_output(5),
+D6=>decoder_row_output(6),
+D7=>decoder_row_output(7),
+D8=>decoder_row_output(8),
+D9=>decoder_row_output(9),
+D10=>decoder_row_output(10),
+D11=>decoder_row_output(11),
+D12=>decoder_row_output(12),
+D13=>decoder_row_output(13),
+D14=>decoder_row_output(14),
+D15=>decoder_row_output(15),
+A0=>decoder_row_input(0),
+A1=>decoder_row_input(1),
+A2=>decoder_row_input(2),
+A3=>decoder_row_input(3),
+E=>e);
+
+end Behavioral;
diff --git a/vhdl_primitive/multiplexer.vhd b/vhdl_primitive/multiplexer.vhd
new file mode 100755
index 0000000..3783973
--- /dev/null
+++ b/vhdl_primitive/multiplexer.vhd
@@ -0,0 +1,47 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:44:49 04/23/2021
+-- Design Name:
+-- Module Name: multiplexer - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_package1.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity multiplexer is
+generic (
+ bits : positive
+);
+port (
+ i1,i2 : in bit_vector(bits-1 downto 0);
+ sel : in bit;
+ o : out bit_vector(bits-1 downto 0)
+);
+end multiplexer;
+
+architecture Behavioral of multiplexer is
+begin
+ o <= i1 when sel='0' else i2;
+end Behavioral;
diff --git a/vhdl_primitive/neural_net.vhd b/vhdl_primitive/neural_net.vhd
new file mode 100755
index 0000000..1c15d71
--- /dev/null
+++ b/vhdl_primitive/neural_net.vhd
@@ -0,0 +1,80 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:21:26 04/23/2021
+-- Design Name:
+-- Module Name: neural_net - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+ENTITY neural_net IS
+PORT (clk, rst: IN STD_LOGIC;
+ x: IN SIGNED(N-1 DOWNTO 0);
+ y: OUT short_array
+);
+END neural_net;
+
+ARCHITECTURE neural_net OF neural_net IS
+ SIGNAL prod, acc1, acc2: long_array;
+ SIGNAL sigmoid: short_array;
+ SIGNAL counter: INTEGER RANGE 1 TO weights+1;
+BEGIN
+ P0: PROCESS(clk)
+ BEGIN
+ IF (clk'EVENT AND clk='1') THEN
+ IF (rst='1') THEN
+ counter <= 1;
+ ELSE
+ counter <= counter + 1;
+ END IF;
+ END IF;
+ END PROCESS P0;
+ P1 : PROCESS(clk)
+ BEGIN
+ IF (clk'EVENT AND clk='1') THEN
+ IF (rst='1') THEN
+ FOR i IN 1 TO neurons LOOP
+ y(i) <= sigmoid(i);
+ acc2(i) <= (OTHERS=>'0');
+ END LOOP;
+ ELSE
+ FOR i IN 1 TO neurons LOOP
+ acc2(i) <= acc1(i);
+ END LOOP;
+ END IF;
+ END IF;
+ END PROCESS P1;
+ P2 : PROCESS(x, counter)
+ BEGIN
+ FOR i IN 1 TO neurons LOOP
+ prod(i) <= x * TO_SIGNED(weight(i, counter), N);
+ acc1(i) <= prod(i) + acc2(i);
+ IF ((acc2(i)(2*N-1)=prod(i)(2*N-1)) AND (acc1(i)(2*N-1)/=acc2(i)(2*N-1))) THEN
+ acc1(i) <= ((2*N-1)=>acc2(i)(2*N-1),OTHERS=>NOT acc2(i)(2*N-1));
+ END IF;
+ sigmoid(i) <= conv_sigmoid(acc2(i));
+ END LOOP;
+ END PROCESS P2;
+END neural_net;
diff --git a/vhdl_primitive/new_debounce.vhd b/vhdl_primitive/new_debounce.vhd
new file mode 100755
index 0000000..7215db9
--- /dev/null
+++ b/vhdl_primitive/new_debounce.vhd
@@ -0,0 +1,161 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:45:58 07/05/2021
+-- Design Name:
+-- Module Name: new_debounce - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.p_globals.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity new_debounce is
+generic ( -- ripplecounter N bits (RC_N=N+1,RC_MAX=2**N)
+G_RC_N : integer := 5;
+G_RC_MAX : integer := 16
+);
+port (
+i_clock : in std_logic;
+i_reset : in std_logic;
+i_b : in std_logic;
+o_db : out std_logic
+);
+end new_debounce;
+
+architecture Behavioral of new_debounce is
+-- XXX based on MAX16054 datasheet
+
+component ripple_counter is
+Generic (
+N : integer := 32;
+MAX : integer := 1
+);
+Port (
+i_clock : in std_logic;
+i_cpb : in std_logic;
+i_mrb : in std_logic;
+i_ud : in std_logic;
+o_q : inout std_logic_vector(N-1 downto 0);
+o_ping : out std_logic
+);
+end component ripple_counter;
+
+component FF_D_POSITIVE_EDGE is
+port (
+S,R : in std_logic;
+C : in std_logic;
+D : in STD_LOGIC;
+Q1,Q2:inout STD_LOGIC);
+end component FF_D_POSITIVE_EDGE;
+
+component FF_JK is
+port (
+i_r : in STD_LOGIC;
+J,K,C : in STD_LOGIC;
+Q1 : inout STD_LOGIC;
+Q2 : inout STD_LOGIC
+);
+end component FF_JK;
+
+component GATE_NOT is
+generic (
+delay_not : TIME := 1 ns
+);
+port (
+A : in STD_LOGIC;
+B : out STD_LOGIC
+);
+end component GATE_NOT;
+
+constant WAIT_NOT : time := 1 ps;
+
+constant RC_N : integer := G_RC_N;
+constant RC_MAX : integer := G_RC_MAX;
+signal rc_cpb,rc_mrb,rc_ud,rc_ping : std_logic;
+signal rc_q : std_logic_vector(RC_N-1 downto 0);
+signal ffdpe_d,ffdpe_q1,ffdpe_q2 : std_logic;
+signal ffjk_j,ffjk_k,ffjk_q1,ffjk_q2 : std_logic;
+
+signal not1 : std_logic;
+signal not2 : std_logic;
+
+begin
+
+ffdpe_d <= i_b;
+rc_mrb <= not2 xnor i_b;
+ffjk_j <= not1;
+ffjk_k <= not1;
+rc_ud <= '1';
+rc_cpb <= not i_reset;
+o_db <= ffjk_q1;
+
+gnot1 : GATE_NOT
+GENERIC MAP (WAIT_NOT)
+port map (
+A => ffdpe_q1,
+B => not1
+);
+
+gnot2 : GATE_NOT
+GENERIC MAP (WAIT_NOT)
+port map (
+A => not1,
+B => not2
+);
+
+rc_entity : ripple_counter -- XXX
+Generic map (
+N => RC_N,
+MAX => RC_MAX
+)
+Port map (
+i_clock => i_clock,
+i_cpb => rc_cpb,
+i_mrb => rc_mrb,
+i_ud => rc_ud,
+o_q => rc_q,
+o_ping => rc_ping
+);
+
+ffdpe_entity : FF_D_POSITIVE_EDGE
+port map(
+S => not i_reset,
+R => not i_reset,
+C => rc_ping, -- XXX
+D => ffdpe_d,
+Q1 => ffdpe_q1,
+Q2 => ffdpe_q2
+);
+
+ffjk_entity : FF_JK
+port map (
+i_r => i_reset,
+J => ffjk_j,
+K => ffjk_k,
+C => not not2,
+Q1 => ffjk_q1,
+Q2 => ffjk_q2
+);
+
+end Behavioral;
diff --git a/vhdl_primitive/nxp_74hc573.vhd b/vhdl_primitive/nxp_74hc573.vhd
new file mode 100755
index 0000000..53466d8
--- /dev/null
+++ b/vhdl_primitive/nxp_74hc573.vhd
@@ -0,0 +1,70 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 10:01:44 04/12/2021
+-- Design Name:
+-- Module Name: nxp_74hc573 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity nxp_74hc573 is
+generic (
+nbit : integer := 8
+);
+port (
+i_le : in std_logic;
+i_oeb : in std_logic;
+i_d : in std_logic_vector(nbit-1 downto 0);
+o_q : out std_logic_vector(nbit-1 downto 0)
+);
+end nxp_74hc573;
+
+architecture Behavioral of nxp_74hc573 is
+
+signal d : std_logic_vector(nbit-1 downto 0);
+signal q : std_logic_vector(nbit-1 downto 0);
+
+begin
+
+IBUF_generate : for i in 0 to nbit-1 generate
+begin
+IBUF_inst : IBUF
+port map (O => d(i),I => i_d(i));
+end generate IBUF_generate;
+
+LDCE_generate : for i in 0 to nbit-1 generate
+begin
+LDCE_inst : LDCE
+port map (Q => q(i),CLR => '0',D => d(i),G => not i_le,GE => not i_le);
+end generate LDCE_generate;
+
+OBUFT_generate : for i in 0 to nbit-1 generate
+begin
+OBUFT_inst : OBUFT
+port map (O => o_q(i),I => q(i),T => i_oeb);
+end generate OBUFT_generate;
+
+end Behavioral;
+
diff --git a/vhdl_primitive/ones_detector.vhd b/vhdl_primitive/ones_detector.vhd
new file mode 100755
index 0000000..2ad4ecf
--- /dev/null
+++ b/vhdl_primitive/ones_detector.vhd
@@ -0,0 +1,84 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:26:55 04/28/2021
+-- Design Name:
+-- Module Name: ones_detector - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ones_detector is
+Generic (
+ N : integer := 16
+);
+Port (
+ x : in std_logic_vector(N-1 downto 1);
+ y : out std_logic_vector(3 downto 0)
+);
+end ones_detector;
+
+architecture Behavioral of ones_detector is
+
+ component FULL_ADDER is
+ port (A,B,Cin:in STD_LOGIC;S,Cout:out STD_LOGIC);
+ end component FULL_ADDER;
+
+ signal s0,c0 : std_logic_vector(N-1 downto 0);
+ signal s1,c1 : std_logic_vector(N-1 downto 0);
+ signal s2,c2 : std_logic_vector(N-1 downto 0);
+
+begin
+
+g0 : for i in 1 to (N/2)-1 generate
+ g00 : if (i=1) generate
+ fa : FULL_ADDER port map (A=>x(2),B=>x(3),Cin=>x(1),S=>s0(1),Cout=>c0(1));
+ end generate g00;
+ g01 : if (i>1 and i<(N/2)-1) generate
+ fa : FULL_ADDER port map (A=>x(2*i+0),B=>x(2*i+1),Cin=>s0(i-1),S=>s0(i),Cout=>c0(i));
+ end generate g01;
+ g02 : if (i=(N/2)-1) generate
+ fa : FULL_ADDER port map (A=>x(2*i+0),B=>x(2*i+1),Cin=>s0(i-1),S=>y(0),Cout=>c0(i));
+ end generate g02;
+end generate g0;
+
+g1 : for i in 1 to (N/2/2)-1 generate
+ g10 : if (i=1) generate
+ fa : FULL_ADDER port map (A=>c0(2*i),B=>c0(2*i+1),Cin=>c0(2*i-1),S=>s1(1),Cout=>c1(1));
+ end generate g10;
+ g11 : if (i>1 and i<(N/2/2)-1) generate
+ fa : FULL_ADDER port map (A=>c0(2*i),B=>c0(2*i+1),Cin=>s1(i-1),S=>s1(i),Cout=>c1(i));
+ end generate g11;
+ g12 : if (i=(N/2/2)-1) generate
+ fa : FULL_ADDER port map (A=>c0(2*i),B=>c0(2*i+1),Cin=>s1(i-1),S=>y(1),Cout=>c1(i));
+ end generate g12;
+end generate g1;
+
+g2 : for i in 1 to (N/2/2/2)-1 generate
+ g22 : if (i=(N/2/2/2)-1) generate
+ fa : FULL_ADDER port map (A=>c1(2),B=>c1(3),Cin=>c1(1),S=>y(2),Cout=>y(3));
+ end generate g22;
+end generate g2;
+
+end Behavioral;
diff --git a/vhdl_primitive/osc_test1.sch b/vhdl_primitive/osc_test1.sch
new file mode 100644
index 0000000..3cf5d22
--- /dev/null
+++ b/vhdl_primitive/osc_test1.sch
@@ -0,0 +1,110 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2000-1-1T10:10:10
+
+
+
+
+
+
+
+
+ 2000-1-1T10:10:10
+
+
+
+
+
+
+
+
+
+
+
+ 2000-1-1T10:10:10
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/vhdl_primitive/p_globals.vhd b/vhdl_primitive/p_globals.vhd
new file mode 100755
index 0000000..e306f0d
--- /dev/null
+++ b/vhdl_primitive/p_globals.vhd
@@ -0,0 +1,56 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package p_globals is
+
+ -- https://stackoverflow.com/a/21784274
+ -- Returns number of bits required to represent val in binary vector
+ function bits_req(val : natural) return natural;
+
+ constant G_CLOCK1 : integer := 50_000_000; -- XXX main clock
+ constant G_OSC1 : integer := 29_952_000; -- XXX osc on socket
+ constant G_OSC2 : integer := 23_961_600; -- XXX osc on socket
+ constant G_OSC3 : integer := 1_000_000; -- XXX for sim
+ constant G_BOARD_CLOCK : integer := G_OSC3; -- XXX osc on board
+ constant G_LCDSegment : integer := 7;
+ constant G_LCDAnode : integer := 4;
+ constant G_LCDClockDivider : integer := 200;
+ constant G_MemoryAddress : integer := 24;
+ constant G_MemoryData : integer := 16;
+ constant G_Switch : integer := 8;
+ constant G_Button : integer := 4;
+ constant G_Led : integer := 8;
+ constant G_HalfHex : integer := 4;
+ constant G_FullHex : integer := G_HalfHex*2;
+ constant G_DEBOUNCE_SPEED_X : integer := 1;
+ constant G_DEBOUNCE_MS : integer := 50/G_DEBOUNCE_SPEED_X;
+ constant G_DEBOUNCE_DIV : integer := 2*G_DEBOUNCE_SPEED_X;
+-- constant G_DEBOUNCE_MS_COUNT : integer := integer(real((G_DEBOUNCE_MS * 1000 * 1000)/(1_000_000_000/G_BOARD_CLOCK)));
+-- constant G_DEBOUNCE_MS_COUNT : integer := integer(real((0.001*real(G_DEBOUNCE_MS)))/real(1/G_BOARD_CLOCK));
+-- constant G_DEBOUNCE_MS_COUNT : integer := 14976000/G_DEBOUNCE_DIV; -- XXX for 100ms,0.001*50/(1/29952000)
+-- constant G_DEBOUNCE_MS_COUNT : integer := 299520/G_DEBOUNCE_DIV; -- XXX for sim 10ms,0.001*10/(1/29952000)
+-- constant G_DEBOUNCE_MS_COUNT : integer := 299520/1; -- XXX for syn 10ms,0.001*10/(1/29952000)
+ constant G_DEBOUNCE_MS_COUNT : integer := 50000; -- XXX 0.001*50/(1/1000000)
+ constant G_DEBOUNCE_MS_BITS : integer := bits_req(G_DEBOUNCE_MS_COUNT);
+
+end p_globals;
+
+package body p_globals is
+
+ -- https://stackoverflow.com/a/21784274
+ -- Returns number of bits required to represent val in binary vector
+ function bits_req(val : natural) return natural is
+ variable res_v : natural; -- Result
+ variable remain_v : natural; -- Remainder used in iteration
+ begin
+ res_v := 0;
+ remain_v := val;
+ while remain_v > 0 loop -- Iteration for each bit required
+ res_v := res_v + 1;
+ remain_v := remain_v / 2;
+ end loop;
+ return res_v;
+ end function;
+
+end p_globals;
+
diff --git a/vhdl_primitive/p_lcd_display.vhd b/vhdl_primitive/p_lcd_display.vhd
new file mode 100755
index 0000000..7bcf763
--- /dev/null
+++ b/vhdl_primitive/p_lcd_display.vhd
@@ -0,0 +1,13 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use WORK.p_globals.ALL;
+
+package p_lcd_display is
+
+ type LCDHex is array(G_LCDAnode-1 downto 0) of std_logic_vector(G_HalfHex-1 downto 0);
+
+end p_lcd_display;
+
+package body p_lcd_display is
+end p_lcd_display;
+
diff --git a/vhdl_primitive/p_package1.vhd b/vhdl_primitive/p_package1.vhd
new file mode 100755
index 0000000..8b4d61c
--- /dev/null
+++ b/vhdl_primitive/p_package1.vhd
@@ -0,0 +1,47 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.ALL;
+
+package p_package1 is
+ function shift_integer (signal a,b : integer) return integer;
+ type matrix is array (natural range <>,natural range <>) of bit;
+ constant bits : positive := 8;
+ type x_input is array (natural range <>) of bit_vector(bits-1 downto 0);
+ CONSTANT neurons: INTEGER := 3;
+ CONSTANT weights: INTEGER := 5;
+ CONSTANT N: INTEGER := 6;
+ TYPE short_array IS ARRAY (1 TO neurons) OF SIGNED(N-1 DOWNTO 0);
+ TYPE long_array IS ARRAY (1 TO neurons) OF SIGNED(2*N-1 DOWNTO 0);
+ TYPE weight_array IS ARRAY (1 TO neurons, 1 TO weights) OF
+ INTEGER RANGE -(2**(N-1)) TO 2**(N-1)-1;
+ CONSTANT weight: weight_array := ((1, 4, 5, 5, -5),(5, 20, 25, 25, -25),(-30, -30, -30, -30, -30));
+ FUNCTION conv_sigmoid (SIGNAL input: SIGNED) RETURN SIGNED;
+end p_package1;
+
+package body p_package1 is
+ function shift_integer (signal a,b : integer) return integer is
+ begin
+ return a*(2**b);
+ end function shift_integer;
+ FUNCTION conv_sigmoid (SIGNAL input: SIGNED) RETURN SIGNED IS
+ VARIABLE a: INTEGER RANGE 0 TO 4**N-1;
+ VARIABLE b: INTEGER RANGE 0 TO 2**N-1;
+ BEGIN
+ a := TO_INTEGER(ABS(input));
+ IF (a=0) THEN b:=0;
+ ELSIF (a>0 AND a<97) THEN b:=2;
+ ELSIF (a>=97 AND a<198) THEN b:=6;
+ ELSIF (a>=198 AND a<305) THEN b:=10;
+ ELSIF (a>=305 AND a<425) THEN b:=14;
+ ELSIF (a>=425 AND a<567) THEN b:=18;
+ ELSIF (a>=567 AND a<753) THEN b:=22;
+ ELSIF (a>=753 AND a<1047) THEN b:=26;
+ ELSE b:=30;
+ END IF;
+ IF (input(2*N-1)='0') THEN
+ RETURN TO_SIGNED(b, N);
+ ELSE
+ RETURN TO_SIGNED(-b, N);
+ END IF;
+ END conv_sigmoid;
+end p_package1;
diff --git a/vhdl_primitive/parity_detector.vhd b/vhdl_primitive/parity_detector.vhd
new file mode 100755
index 0000000..090663e
--- /dev/null
+++ b/vhdl_primitive/parity_detector.vhd
@@ -0,0 +1,50 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:02:40 04/23/2021
+-- Design Name:
+-- Module Name: parity_detector - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity parity_detector is
+Generic (
+ N : integer := 8
+);
+Port (
+ x : in std_logic_vector(N-1 downto 0);
+ y : out std_logic
+);
+end parity_detector;
+
+architecture Behavioral of parity_detector is
+ signal chain : std_logic_vector(N-1 downto 0);
+begin
+ chain(0) <= x(0);
+ xor_chain : for i in 1 to N-1 generate
+ chain(i) <= chain(i-1) xor x(i);
+ end generate xor_chain;
+ y <= chain(N-1);
+end Behavioral;
diff --git a/vhdl_primitive/priority_encoder.vhd b/vhdl_primitive/priority_encoder.vhd
new file mode 100755
index 0000000..5cdc8cb
--- /dev/null
+++ b/vhdl_primitive/priority_encoder.vhd
@@ -0,0 +1,56 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:50:51 04/23/2021
+-- Design Name:
+-- Module Name: priority_encoder - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity priority_encoder is
+Generic (
+ N : integer := 7
+);
+Port (
+ x : in std_logic_vector(N downto 1);
+ y : out integer range 0 to N
+);
+end priority_encoder;
+
+architecture Behavioral of priority_encoder is
+begin
+ p0 : process(x) is
+ begin
+ l0 : for i in x'range loop
+ if (x(i)='1') then
+ temp := i;
+ exit;
+ else
+ temp := 0;
+ end if;
+ end loop l0;
+ y <= temp;
+ end process p0;
+end Behavioral;
diff --git a/vhdl_primitive/ripple_counter.vhd b/vhdl_primitive/ripple_counter.vhd
new file mode 100755
index 0000000..837468b
--- /dev/null
+++ b/vhdl_primitive/ripple_counter.vhd
@@ -0,0 +1,171 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:32:30 05/04/2021
+-- Design Name:
+-- Module Name: ripple_counter - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity ripple_counter is
+Generic (
+N : integer := 32;
+MAX : integer := 1
+);
+Port (
+i_clock : in std_logic;
+i_cpb : in std_logic;
+i_mrb : in std_logic;
+i_ud : in std_logic;
+o_q : inout std_logic_vector(N-1 downto 0);
+o_ping : out std_logic
+);
+end ripple_counter;
+
+architecture Behavioral of ripple_counter is
+
+ component FF_JK is
+ port (
+ i_r:in STD_LOGIC;
+ J,K,C:in STD_LOGIC;
+ Q1:inout STD_LOGIC;
+ Q2:inout STD_LOGIC
+ );
+ end component FF_JK;
+
+ component FF_D_POSITIVE_EDGE is
+ port (S,R,C,D:in STD_LOGIC;Q1,Q2:inout STD_LOGIC);
+ end component FF_D_POSITIVE_EDGE;
+
+ component GATE_AND is
+ generic (
+ delay_and : TIME := 1 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_AND;
+
+ component GATE_OR is
+ generic (
+ delay_or : TIME := 1 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_OR;
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 1 ns
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+
+ signal cp,mr : std_logic;
+ signal q1,q2 : std_logic_vector(N-1 downto 0);
+ signal ping,ping1,ping2 : std_logic;
+ signal ffjk_and_u,ffjk_and_d,ffjk_or : std_logic_vector(N-1 downto 0); -- XXX omit last FF JK
+ signal ud,udb : std_logic;
+ signal gated_clock : std_logic;
+ signal a : std_logic_vector(N-1 downto 0) := std_logic_vector(to_unsigned(MAX,N));
+ signal b : std_logic_vector(N-1 downto 0) := std_logic_vector(to_unsigned(0,N));
+
+ constant WAIT_AND : time := 0 ps;
+ constant WAIT_OR : time := 0 ps;
+ constant WAIT_NOT : time := 0 ps;
+
+-- attribute keep : string; -- XXX when unconnected signal in g0_and_d
+-- attribute keep of ud : signal is "true";
+-- attribute keep of udb : signal is "true";
+-- attribute keep of ffjk_and_d : signal is "true";
+
+begin
+
+ ffjk_or(N-1) <= '0';
+ gated_clock <= i_clock and cp;
+ ud <= i_ud;
+ o_q <= q1;
+ cp <= i_cpb;
+ mr <= '1' when o_q = a or i_mrb = '1' else '0';
+ --ping <= '1' when o_q = b else '0';
+
+ inst1 : FF_D_POSITIVE_EDGE
+ PORT MAP (
+ S => not mr,
+ R => not mr,
+ D => mr,
+ C => gated_clock,
+ Q1 => ping1,
+ Q2 => ping2
+ );
+ o_ping <= ping1;
+
+ g0_and_u : for i in 0 to N-1 generate -- XXX omit last FF JK
+ g0_and_u_first : if (i=0) generate
+ g0_and_u_first : GATE_AND generic map (WAIT_AND) port map (A=>q1(i),B=>ud,C=>ffjk_and_u(i));
+ end generate g0_and_u_first;
+ g0_and_u_chain : if (i>0) generate
+ g0_and_u_chain : GATE_AND generic map (WAIT_AND) port map (A=>q1(i),B=>ffjk_and_u(i-1),C=>ffjk_and_u(i));
+ end generate g0_and_u_chain;
+ end generate g0_and_u;
+
+ g0_and_d : for i in 0 to N-1 generate -- XXX omit last FF JK
+ g0_and_d_first : if (i=0) generate
+ g0_and_d_first : GATE_AND generic map (WAIT_AND) port map (A=>q2(i),B=>udb,C=>ffjk_and_d(i)); -- XXX udb make unconnected
+ g0_not_clock : GATE_NOT generic map (WAIT_NOT) port map (A=>ud,B=>udb);
+ end generate g0_and_d_first;
+ g0_and_d_chain : if (i>0) generate
+ g0_and_d_chain : GATE_AND generic map (WAIT_AND) port map (A=>q2(i),B=>ffjk_and_d(i-1),C=>ffjk_and_d(i));
+ end generate g0_and_d_chain;
+ end generate g0_and_d;
+
+ g0_or : for i in 0 to N-1 generate -- XXX omit last FF JK
+ g0_or_first : if (i=0) generate
+ g0_or_first : GATE_OR generic map (WAIT_OR) port map (A=>ffjk_and_u(i),B=>ffjk_and_d(i),C=>ffjk_or(i));
+ end generate g0_or_first;
+ g0_or_chain : if (i>0) generate
+ g0_or_chain : GATE_OR generic map (WAIT_OR) port map (A=>ffjk_and_u(i),B=>ffjk_and_d(i),C=>ffjk_or(i));
+ end generate g0_or_chain;
+ end generate g0_or;
+
+ g0 : for i in 0 to N-1 generate
+ ffjk_first : if (i=0) generate
+ ffjk_first : FF_JK port map (i_r=>mr,J=>cp,K=>cp,C=>gated_clock,Q1=>q1(i),Q2=>q2(i));
+ end generate ffjk_first;
+ ffjk_chain : if (i>0 and imr,J=>ffjk_or(i-1),K=>ffjk_or(i-1),C=>gated_clock,Q1=>q1(i),Q2=>q2(i));
+ end generate ffjk_chain;
+ ffjk_last : if (i=N-1) generate
+ ffjk_last : FF_JK port map (i_r=>mr,J=>ffjk_or(i-1),K=>ffjk_or(i-1),C=>gated_clock,Q1=>q1(i),Q2=>q2(i));
+ end generate ffjk_last;
+ end generate g0;
+
+end Behavioral;
diff --git a/vhdl_primitive/rs232.vhd b/vhdl_primitive/rs232.vhd
new file mode 100755
index 0000000..a3af2f5
--- /dev/null
+++ b/vhdl_primitive/rs232.vhd
@@ -0,0 +1,308 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:54:25 09/08/2020
+-- Design Name:
+-- Module Name: module_1 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity rs232 is
+Generic (
+ G_BOARD_CLOCK : integer := 50_000_000;
+ G_BAUD_RATE : integer := 9_600
+);
+Port(
+ clk : in STD_LOGIC;
+ rst : in STD_LOGIC;
+ enable_tx : in STD_LOGIC;
+-- enable_rx : in STD_LOGIC;
+ byte_to_send : in STD_LOGIC_VECTOR (7 downto 0);
+-- byte_received : out STD_LOGIC_VECTOR (7 downto 0);
+-- parity_tx : out STD_LOGIC;
+-- parity_rx : out STD_LOGIC;
+ busy : out STD_LOGIC;
+ ready : out STD_LOGIC;
+-- is_byte_received : out STD_LOGIC;
+ is_byte_sended : out STD_LOGIC;
+ RsTx : out STD_LOGIC
+-- RsRx : in STD_LOGIC
+);
+end rs232;
+
+architecture Behavioral of rs232 is
+
+-- constant recv_bits : integer := 10;
+ constant a : integer := (G_BOARD_CLOCK/G_BAUD_RATE);
+
+-- signal v_i : std_logic_vector(31 downto 0);
+-- signal v_w : std_logic_vector(31 downto 0);
+ signal t_w : std_logic_vector(31 downto 0);
+-- signal temp : std_logic_vector(recv_bits - 1 downto 0);
+-- signal p_tx,p_rx : std_logic;
+
+ type t_state is (
+ idle,
+ start,wstart,
+ b1,wb1,b2,wb2,b3,wb3,b4,wb4,b5,wb5,b6,wb6,b7,wb7,b8,wb8,
+ parity,wparity,
+ stop,wstop
+ );
+ signal tx_state : t_state;
+
+-- type r_state is (
+-- idle,
+-- start,
+-- recv,
+-- wait0,
+-- increment,
+-- parity,
+-- wparity,
+-- stop
+-- );
+-- signal rx_state : r_state;
+
+begin
+
+-- p0 : process (clk,rst) is -- rx mode
+-- begin
+-- if (rst = '1') then
+-- rx_state <= idle;
+-- v_i <= (others => '0');
+-- v_w <= (others => '0');
+-- temp <= (others => '0');
+-- elsif (rising_edge(clk)) then
+-- case (rx_state) is
+-- when idle =>
+-- if (enable_rx = '1') then
+-- rx_state <= start;
+-- v_i <= (others => '0');
+-- v_w <= (others => '0');
+-- is_byte_received <= '0';
+-- elsif (enable_rx = '0') then
+-- rx_state <= idle;
+-- end if;
+-- when start =>
+-- if (RsRx = '1') then
+-- if (to_integer(unsigned(v_i)) = a-1) then
+-- rx_state <= recv;
+-- v_i <= x"00000001"; -- we receive first bit
+-- temp(0) <= RsRx;
+-- else
+-- rx_state <= start;
+-- v_i <= std_logic_vector(to_unsigned(to_integer(unsigned(v_i)) + 1,32));
+-- end if;
+-- elsif (RsRx = '0') then
+-- rx_state <= start;
+-- v_i <= (others => '0');
+-- end if;
+-- when recv =>
+-- rx_state <= wait0;
+-- temp(to_integer(unsigned(v_i))) <= RsRx;
+-- when wait0 =>
+-- if (to_integer(unsigned(v_w)) = a-1) then
+-- rx_state <= increment;
+-- v_w <= (others => '0');
+-- else
+-- rx_state <= wait0;
+-- v_w <= std_logic_vector(to_unsigned(to_integer(unsigned(v_w)) + 1,32));
+-- end if;
+-- when increment =>
+-- if (to_integer(unsigned(v_i)) = recv_bits-2) then
+-- rx_state <= parity;
+-- v_i <= (others => '0');
+-- else
+-- rx_state <= recv;
+-- v_i <= std_logic_vector(to_unsigned(to_integer(unsigned(v_i)) + 1,32));
+-- end if;
+-- when parity =>
+-- rx_state <= wparity;
+-- p_rx <= temp(1) xor temp(2) xor temp(3) xor temp(4) xor temp(5) xor temp(6) xor temp(7) xor temp(8);
+-- when wparity =>
+-- if (to_integer(unsigned(v_w)) = a-1) then
+-- rx_state <= stop;
+-- v_w <= (others => '0');
+-- else
+-- rx_state <= wparity;
+-- v_w <= std_logic_vector(to_unsigned(to_integer(unsigned(v_w)) + 1,32));
+-- end if;
+-- when stop =>
+-- rx_state <= idle;
+-- is_byte_received <= '1';
+-- byte_received <= temp(recv_bits-2 downto 1);
+-- parity_rx <= p_rx; -- recv_bits-1
+-- end case;
+-- end if;
+-- end process p0;
+
+ p1 : process (clk,rst) is -- tx mode
+ begin
+ if (rst = '1') then
+ tx_state <= idle;
+ busy <= '0';
+ ready <= '1';
+ RsTx <= '0';
+ t_w <= (others => '0');
+ elsif (rising_edge(clk)) then
+ case tx_state is
+ when idle =>
+ if (enable_tx = '1') then
+ tx_state <= start;
+ end if;
+ when start =>
+ tx_state <= wstart;
+ busy <= '1';
+ ready <= '0';
+ RsTx <= '1';
+ when wstart =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= b1;
+ t_w <= (others => '0');
+ else
+ tx_state <= wstart;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b1 =>
+ tx_state <= wb1;
+ RsTx <= byte_to_send(0);
+ when wb1 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= b2;
+ t_w <= (others => '0');
+ else
+ tx_state <= wb1;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b2 =>
+ tx_state <= wb2;
+ RsTx <= byte_to_send(1);
+ when wb2 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= b3;
+ t_w <= (others => '0');
+ else
+ tx_state <= wb2;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b3 =>
+ tx_state <= wb3;
+ RsTx <= byte_to_send(2);
+ when wb3 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= b4;
+ t_w <= (others => '0');
+ else
+ tx_state <= wb3;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b4 =>
+ tx_state <= wb4;
+ RsTx <= byte_to_send(3);
+ when wb4 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= b5;
+ t_w <= (others => '0');
+ else
+ tx_state <= wb4;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b5 =>
+ tx_state <= wb5;
+ RsTx <= byte_to_send(4);
+ when wb5 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= b6;
+ t_w <= (others => '0');
+ else
+ tx_state <= wb5;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b6 =>
+ tx_state <= wb6;
+ RsTx <= byte_to_send(5);
+ when wb6 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= b7;
+ t_w <= (others => '0');
+ else
+ tx_state <= wb6;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b7 =>
+ tx_state <= wb7;
+ RsTx <= byte_to_send(6);
+ when wb7 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= b8;
+ t_w <= (others => '0');
+ else
+ tx_state <= wb7;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when b8 =>
+ tx_state <= wb8;
+ RsTx <= byte_to_send(7);
+ when wb8 =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= parity;
+ t_w <= (others => '0');
+ else
+ tx_state <= wb8;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when parity =>
+ tx_state <= wparity;
+-- p_tx <= byte_to_send(0) xor byte_to_send(1) xor byte_to_send(2) xor byte_to_send(3) xor byte_to_send(4) xor byte_to_send(5) xor byte_to_send(6) xor byte_to_send(7);
+-- RsTx <= p_tx;
+ when wparity =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= stop;
+ t_w <= (others => '0');
+ else
+ tx_state <= wparity;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when stop =>
+ tx_state <= wstop;
+ RsTx <= '0';
+ busy <= '0';
+ ready <= '1';
+ when wstop =>
+ if (to_integer(unsigned(t_w)) = a-1) then
+ tx_state <= idle;
+-- parity_tx <= p_tx;
+ t_w <= (others => '0');
+ else
+ tx_state <= wstop;
+ t_w <= std_logic_vector(to_unsigned(to_integer(unsigned(t_w)) + 1,32));
+ end if;
+ when others => null;
+ end case;
+ end if;
+ end process p1;
+
+ is_byte_sended <= '1' when (tx_state = stop and clk = '0') else '0';
+
+end Behavioral;
diff --git a/vhdl_primitive/sar_adc.vhd b/vhdl_primitive/sar_adc.vhd
new file mode 100755
index 0000000..5f01ab9
--- /dev/null
+++ b/vhdl_primitive/sar_adc.vhd
@@ -0,0 +1,103 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:47:54 05/07/2021
+-- Design Name:
+-- Module Name: sar_adc - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity sar_adc is
+Generic (
+G_BOARD_CLOCK : integer := 50_000_000;
+data_size : integer := 8
+);
+Port (
+i_clock : in std_logic;
+i_reset : in std_logic;
+o_data : out std_logic_vector(data_size-1 downto 0);
+o_to_pluscomparator : out std_logic; -- analog input on minuscomparator
+i_from_comparator : in std_logic;
+o_sar_end : inout std_logic
+);
+end sar_adc;
+
+architecture Behavioral of sar_adc is
+
+component dac_delta_sigma is
+Port (
+clk : in STD_LOGIC;
+data : in STD_LOGIC_VECTOR (data_size-1 downto 0);
+PulseStream : out STD_LOGIC
+);
+end component dac_delta_sigma;
+
+component succesive_approximation_register is
+Generic (
+n : integer := data_size
+);
+Port (
+i_clock : in STD_LOGIC;
+i_reset : in STD_LOGIC;
+i_select : in STD_LOGIC;
+o_q : out STD_LOGIC_VECTOR (n-1 downto 0);
+o_end : inout STD_LOGIC
+);
+end component succesive_approximation_register;
+
+signal data2 : std_logic_vector(data_size-1 downto 0);
+signal andgate : std_logic;
+signal divclock : std_logic;
+constant count_max : integer := G_BOARD_CLOCK/100;
+
+begin
+
+p0 : process (i_clock,i_reset) is --XXX use FF
+ variable count : integer range 0 to count_max-1 := 0;
+begin
+ if (i_reset = '1') then
+ count := 0;
+ elsif (rising_edge(i_clock)) then
+ if (count = count_max-1) then
+ count := 0;
+ divclock <= '1';
+ else
+ count := count + 1;
+ divclock <= '0';
+ end if;
+ end if;
+end process p0;
+
+o_data <= data2;
+andgate <= i_clock and i_from_comparator;
+
+dac_entity : dac_delta_sigma
+Port map (clk=>divclock,data=>data2,PulseStream=>o_to_pluscomparator);
+
+sar_entity : succesive_approximation_register
+Generic map (n => data_size)
+Port map (i_clock=>divclock,i_reset=>not andgate,i_select=>not andgate,o_q=>data2,o_end=>o_sar_end);
+
+end Behavioral;
diff --git a/vhdl_primitive/schneider_circuit.vhd b/vhdl_primitive/schneider_circuit.vhd
new file mode 100755
index 0000000..44094b2
--- /dev/null
+++ b/vhdl_primitive/schneider_circuit.vhd
@@ -0,0 +1,50 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:49:49 06/30/2021
+-- Design Name:
+-- Module Name: schneider_circuit - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity schneider_circuit is
+port (
+ x1,x2,x3,x4 : in std_logic;
+ y : out std_logic
+);
+end schneider_circuit;
+
+architecture Behavioral of schneider_circuit is
+ signal g1,g2,g3,g4,g5,g6,g7 : std_logic;
+begin
+ g1 <= x1 nand x3;
+ g2 <= x2 nand x3;
+ g3 <= x2 nand x4;
+ g4 <= g1 nand x2;
+ g5 <= x1 nand g2;
+ g6 <= x4 nand g2;
+ g7 <= g3 nand x3;
+ y <= not (g4 and g5 and g6 and g7);
+end Behavioral;
diff --git a/vhdl_primitive/serial_line_code.ucf b/vhdl_primitive/serial_line_code.ucf
new file mode 100644
index 0000000..2495111
--- /dev/null
+++ b/vhdl_primitive/serial_line_code.ucf
@@ -0,0 +1,4 @@
+NET "clock_1" TNM_NET = "CLK_A";
+NET "clock_2" TNM_NET = "CLK_B";
+TIMESPEC "TS_CLKA" = PERIOD "CLK_A" 8 ns;
+TIMESPEC "TS_CLKB" = PERIOD "CLK_B" 4 ns;
\ No newline at end of file
diff --git a/vhdl_primitive/serial_line_code.vhd b/vhdl_primitive/serial_line_code.vhd
new file mode 100644
index 0000000..0009bc9
--- /dev/null
+++ b/vhdl_primitive/serial_line_code.vhd
@@ -0,0 +1,152 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:58:09 06/03/2023
+-- Design Name: fig_3_24
+-- Module Name: serial_line_code - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity serial_line_code is
+port (
+signal clock_1 : in bit; -- re 1x
+signal clock_2 : in bit; -- fe 2x
+signal reset : in bit;
+signal B_in : in bit;
+signal NRZ_Mealy : out bit;
+signal NRZ_Moore : out bit;
+signal NRZI_Mealy : out bit;
+signal NRZI_Moore : out bit;
+signal RZ : out bit;
+signal Manchester : out bit
+);
+end serial_line_code;
+
+architecture Behavioral of serial_line_code is
+
+signal bin : bit;
+
+signal pbin1,pbin2 : bit;
+signal nrzime : bit;
+signal nrzimo : bit;
+signal regrz : bit;
+
+begin
+
+p_catch_clock : process (clock_2) is
+begin
+ if (clock_2'event and clock_2 = '1') then
+ bin <= clock_1;
+ end if;
+end process p_catch_clock;
+
+p_Manchester : process (clock_2) is
+begin
+ if (clock_2'event and clock_2 = '0') then
+ if (reset = '1') then
+ Manchester <= '0';
+ else
+ if (B_in = '0') then
+ Manchester <= not bin;
+ end if;
+ if (B_in = '1') then
+ Manchester <= bin;
+ end if;
+ end if;
+ end if;
+end process p_Manchester;
+
+p_NRZ_Mealy : process (clock_1) is
+begin
+ if (clock_1'event and clock_1 = '0') then
+ NRZ_Mealy <= B_in;
+ end if;
+end process p_NRZ_Mealy;
+
+p_NRZ_Moore : process (clock_1) is
+begin
+ if (clock_1'event and clock_1 = '1') then
+ NRZ_Moore <= B_in;
+ end if;
+end process p_NRZ_Moore;
+
+p_catch_1 : process (clock_1) is
+begin
+ if (clock_1'event and clock_1 = '0') then
+ if (reset = '1') then
+ pbin1 <= '0';
+ pbin2 <= '0';
+ else
+ pbin1 <= B_in;
+ pbin2 <= pbin1;
+ end if;
+ end if;
+end process p_catch_1;
+
+p_NRZI_Mealy : process (clock_1) is
+begin
+ if (clock_1'event and clock_1 = '0') then
+ if (reset = '1') then
+ nrzime <= '0';
+ else
+ if (((B_in = '1' and pbin2 = '1') or (B_in = '1' and pbin2 = '0'))) then
+ nrzime <= not nrzime;
+ else
+ nrzime <= nrzime;
+ end if;
+ end if;
+ end if;
+end process p_NRZI_Mealy;
+NRZI_Mealy <= nrzime;
+
+p_NRZI_Moore : process (clock_1) is
+begin
+ if (clock_1'event and clock_1 = '1') then
+ if (reset = '1') then
+ nrzimo <= '0';
+ else
+ nrzimo <= nrzime;
+ end if;
+ end if;
+end process p_NRZI_Moore;
+NRZI_Moore <= nrzimo;
+
+p_RZ : process (clock_2) is
+begin
+ if (clock_2'event and clock_2 = '0') then
+ if (reset = '1') then
+ regrz <= '0';
+ else
+ if (nrzime /= nrzimo) then
+ regrz <= '0';
+ else
+ regrz <= '1';
+ end if;
+ end if;
+ end if;
+end process p_RZ;
+RZ <= '0' when ((nrzime = '0' and nrzimo = '0') or (nrzime = '1' and nrzimo = '1')) else regrz;
+
+end Behavioral;
diff --git a/vhdl_primitive/shift_register.vhd b/vhdl_primitive/shift_register.vhd
new file mode 100755
index 0000000..4e71033
--- /dev/null
+++ b/vhdl_primitive/shift_register.vhd
@@ -0,0 +1,75 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:50:01 04/23/2021
+-- Design Name:
+-- Module Name: shift_register - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity shift_register is
+generic (
+ M : integer := 4;
+ N : integer := 8
+);
+port (
+ clk,load : in bit;
+ x : in x_input(1 to M);
+ d : in bit_vector(N-1 downto 0);
+ q : out bit_vector(N-1 downto 0)
+);
+end shift_register;
+
+architecture Behavioral of shift_register is
+ signal temp1 : x_input(0 to M);
+ signal temp2 : x_input(1 to M);
+ component multiplexer is
+ generic (
+ bits : positive
+ );
+ port (
+ i1,i2 : in bit_vector(bits-1 downto 0);
+ sel : in bit;
+ o : out bit_vector(bits-1 downto 0)
+ );
+ end component multiplexer;
+ component ff is
+ Generic (
+ bits : positive
+ );
+ Port (
+ d : in bit_vector(bits-1 downto 0);
+ clk : in bit;
+ q : out bit_vector(bits-1 downto 0)
+ );
+ end component ff;
+begin
+ temp1(0) <= d;
+ g : for i in 1 to M generate
+ mux_e : multiplexer generic map (N) port map (temp1(i-1),x(i),load,temp2(i));
+ ff_e : ff generic map (N) port map (temp2(i),clk,temp1(i));
+ end generate g;
+ q <= temp1(M);
+end Behavioral;
diff --git a/vhdl_primitive/shifter.vhd b/vhdl_primitive/shifter.vhd
new file mode 100755
index 0000000..d0774af
--- /dev/null
+++ b/vhdl_primitive/shifter.vhd
@@ -0,0 +1,43 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:39:24 04/23/2021
+-- Design Name:
+-- Module Name: shifter - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity shifter is
+Port (
+ input : in integer range 0 to 63;
+ shift : in integer range -6 to 6;
+ output : out integer range 0 to 63
+);
+end shifter;
+
+architecture Behavioral of shifter is
+begin
+ output <= shift_integer(input,shift);
+end Behavioral;
diff --git a/vhdl_primitive/signal_generator.vhd b/vhdl_primitive/signal_generator.vhd
new file mode 100755
index 0000000..90dd5e4
--- /dev/null
+++ b/vhdl_primitive/signal_generator.vhd
@@ -0,0 +1,83 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:40:04 04/23/2021
+-- Design Name:
+-- Module Name: signal_generator - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity signal_generator is
+port (
+ clk : in std_logic;
+ x : buffer std_logic;
+ y : out std_logic
+);
+end signal_generator;
+
+architecture Behavioral of signal_generator is
+ type state is (a,b,c);
+ signal pr_state1,nx_state1 : state;
+ signal pr_state2,nx_state2 : state;
+begin
+ p0 : process (clk) is
+ begin
+ if (rising_edge(clk)) then
+ pr_state1 <= nx_state1;
+ end if;
+ end process p0;
+ p1 : process (pr_state1,clk) is
+ begin
+ case pr_state1 is
+ when a =>
+ x <= '1';
+ nx_state1 <= b;
+ when b =>
+ x <= clk;
+ nx_state1 <= c;
+ when c =>
+ x <= '1';
+ nx_state1 <= a;
+ end case;
+ end process p1;
+ p2 : process (clk) is
+ begin
+ if (rising_edge(clk)) then
+ pr_state2 <= nx_state2;
+ end if;
+ end process p2;
+ p3 : process (pr_state1,pr_state2,x) is
+ begin
+ nx_state2 <= pr_state1;
+ case pr_state2 is
+ when a =>
+ y <= x;
+ when b =>
+ y <= '1';
+ when c =>
+ y <= x;
+ end case;
+ end process p3;
+end Behavioral;
diff --git a/vhdl_primitive/sn5474ls245.vhd b/vhdl_primitive/sn5474ls245.vhd
new file mode 100755
index 0000000..fc9ef24
--- /dev/null
+++ b/vhdl_primitive/sn5474ls245.vhd
@@ -0,0 +1,82 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:24:27 07/11/2021
+-- Design Name:
+-- Module Name: sn5474ls245 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity sn5474ls245 is
+Generic (
+ N : integer := 8
+);
+Port (
+ i_dir : in STD_LOGIC;
+ i_eb : in STD_LOGIC;
+ io_a : inout STD_LOGIC_VECTOR (N-1 downto 0);
+ io_b : inout STD_LOGIC_VECTOR (N-1 downto 0)
+);
+end sn5474ls245;
+
+architecture Behavioral of sn5474ls245 is
+ component sn5474ls245_cell is
+ Port (
+ i_s : in STD_LOGIC;
+ i_sb : in STD_LOGIC;
+ io_a : inout STD_LOGIC;
+ io_b : inout STD_LOGIC
+ );
+ end component sn5474ls245_cell;
+
+ signal and2_dir,and2_eb : std_logic;
+-- signal t1,t2 : std_logic_vector(N-1 downto 0);
+-- signal t1,t2 : std_logic := '0';
+ constant WAIT_AND : time := 1 ns;
+begin
+
+ and2_dir <= i_dir and not i_eb after WAIT_AND;
+ and2_eb <= not i_dir and not i_eb after WAIT_AND;
+
+-- g0 : for i in N-1 downto 0 generate
+-- IOBUF_inst1 : IOBUF
+-- port map (O=>t1(i),IO=>io_a(i),I=>t2(i),T=>and2_eb);
+---- port map (O=>t1,IO=>io_a(i),I=>t2,T=>and2_eb);
+-- IOBUF_inst2 : IOBUF
+-- port map (O=>t2(i),IO=>io_b(i),I=>t1(i),T=>and2_dir);
+---- port map (O=>t2,IO=>io_b(i),I=>t1,T=>and2_dir);
+-- end generate g0;
+
+ g0 : for i in io_a'range generate
+ g0_sn : sn5474ls245_cell
+ Port map (
+ i_s => and2_dir,
+ i_sb => and2_eb,
+ io_a => io_a(i),
+ io_b => io_b(i)
+ );
+ end generate g0;
+
+end Behavioral;
diff --git a/vhdl_primitive/sn5474ls245_cell.vhd b/vhdl_primitive/sn5474ls245_cell.vhd
new file mode 100755
index 0000000..3123b23
--- /dev/null
+++ b/vhdl_primitive/sn5474ls245_cell.vhd
@@ -0,0 +1,66 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:18:24 07/11/2021
+-- Design Name:
+-- Module Name: sn5474ls245_cell - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity sn5474ls245_cell is
+Port (
+i_s : in STD_LOGIC;
+i_sb : in STD_LOGIC;
+io_a : inout STD_LOGIC;
+io_b : inout STD_LOGIC
+);
+end sn5474ls245_cell;
+
+architecture Behavioral of sn5474ls245_cell is
+ signal t1,t2 : std_logic;
+begin
+
+-- io_a <= io_b after 1 ns when i_s = '1' and i_sb = '0' else 'Z';
+-- io_b <= io_a after 1 ns when i_s = '0' and i_sb = '1' else 'Z';
+
+IOBUF_inst1 : IOBUF
+generic map (
+DRIVE => 12,
+IBUF_DELAY_VALUE => "12",
+IFD_DELAY_VALUE => "6",
+IOSTANDARD => "DEFAULT",
+SLEW => "SLOW")
+port map (IO=>io_a,I=>t1,O=>t2,T=>i_s);
+
+IOBUF_inst2 : IOBUF
+generic map (
+DRIVE => 12,
+IBUF_DELAY_VALUE => "12",
+IFD_DELAY_VALUE => "6",
+IOSTANDARD => "DEFAULT",
+SLEW => "SLOW")
+port map (IO=>io_b,I=>t2,O=>t1,T=>i_sb);
+
+end Behavioral;
diff --git a/vhdl_primitive/sram_62256.vhd b/vhdl_primitive/sram_62256.vhd
new file mode 100755
index 0000000..953e7c2
--- /dev/null
+++ b/vhdl_primitive/sram_62256.vhd
@@ -0,0 +1,199 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:41:53 04/12/2021
+-- Design Name:
+-- Module Name: sram_62256 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity sram_62256 is
+Generic (
+address_size : integer := 8;
+data_size : integer := 8
+);
+Port (
+i_ceb : in STD_LOGIC;
+i_web : in STD_LOGIC;
+i_oeb : in STD_LOGIC;
+i_address : in STD_LOGIC_VECTOR (address_size-1 downto 0);
+i_data : in STD_LOGIC_VECTOR (data_size-1 downto 0);
+o_data : out STD_LOGIC_VECTOR (data_size-1 downto 0)
+);
+end sram_62256;
+
+architecture Behavioral of sram_62256 is
+
+-- component mem_decoder_col is
+-- Port (
+-- signal decoder_col_input : in std_logic_vector(4-1 downto 0);
+-- signal decoder_col_output : out std_logic_vector(2**4-1 downto 0);
+-- signal e : std_logic
+-- );
+-- end component mem_decoder_col;
+-- component mem_decoder_row
+-- Port (
+-- signal decoder_row_input : IN std_logic_vector(4-1 downto 0);
+-- signal decoder_row_output : OUT std_logic_vector(2**4-1 downto 0);
+-- signal e : IN std_logic
+-- );
+-- end component mem_decoder_row;
+
+ component sram_cell is
+ Generic (
+ N : integer := 4
+ );
+ Port (
+ i_ce : in std_logic;
+ i_we : in std_logic;
+ i_oe : in std_logic;
+ i_address_row : in std_logic_vector(N-1 downto 0);
+ i_address_col : in std_logic_vector(N-1 downto 0);
+ i_bit : in std_logic;
+ o_bit : out std_logic
+ );
+ end component sram_cell;
+
+ constant memory_bits_rows : integer := address_size/2;
+ constant memory_bits_cols : integer := address_size/2;
+ constant memory_rows : integer := 2**memory_bits_rows;
+ constant memory_cols : integer := 2**memory_bits_cols;
+ constant memory_cols_bits : integer := memory_cols*data_size;
+
+ signal ceb,web,oeb,tristate_input,tristate_output : std_logic;
+ signal data_in,data_out : std_logic_vector(data_size-1 downto 0);
+
+ signal decoder_row_input : std_logic_vector(memory_bits_rows-1 downto 0);
+ signal decoder_col_input : std_logic_vector(memory_bits_cols-1 downto 0);
+
+-- signal decoder_row_output : std_logic_vector(memory_rows-1 downto 0);
+-- signal decoder_col_output : std_logic_vector(memory_cols-1 downto 0);
+
+-- type ram is array(memory_rows-1 downto 0,memory_cols-1 downto 0) of std_logic_vector(data_size-1 downto 0);
+-- signal mem : ram;
+
+ function one_position(v : unsigned) return integer is
+ variable r : integer;
+ begin
+ if (v'ascending = true) then
+ r := 0;
+ l0 : for i in 0 to v'left loop
+ if (v(i) = '1') then
+ exit;
+ else
+ r := r + 1;
+ end if;
+ end loop l0;
+ elsif (v'ascending = false) then
+ r := v'left;
+ l1 : for i in v'left downto 0 loop
+ if (v(i) = '1') then
+ exit;
+ else
+ r := r - 1;
+ end if;
+ end loop l1;
+ end if;
+ return r;
+ end function one_position;
+
+-- signal bufi1,bufi2 : std_logic := '0';
+-- signal bufo1,bufo2 : std_logic := '0';
+ signal a3,b3 : std_logic;
+
+begin
+
+-- b3 <= web when i_ceb='0' else not web;
+-- bufi <= '1' when (falling_edge(tristate_input))
+-- else '0';
+-- bufo <= '1' when (falling_edge(tristate_output))
+-- else '0';
+
+-- LDCPE_bufi1 : LDCPE port map (Q=>bufi2,D=>bufi1,GE=>'1',G=>'1',CLR=>not ceb,PRE=>web);
+-- LDCPE_bufi2 : LDCPE port map (Q=>bufi1,D=>bufi2,GE=>'1',G=>'1',CLR=>'0',PRE=>'0');
+-- bufo1 <= bufi1 xor bufi2;
+
+ b3 <= not a3;
+ LDCPE_bufo1 : LDCPE port map (Q=>a3,D=>b3,GE=>'1',G=>'1',CLR=>not web,PRE=>web);
+-- LDCPE_bufo2 : LDCPE port map (Q=>a3,D=>b3,GE=>'1',G=>'1',CLR=>'0',PRE=>bufo1);
+
+-- BUFG_inst2 : LDCPE port map (
+-- Q => bufo,D => tristate_output, GE => not i_ceb, G => tristate_output, CLR => '0', PRE => '0');
+
+ ceb <= not i_ceb;
+ web <= not i_web;
+ oeb <= not i_oeb;
+-- tristate_input <= ceb and web;
+ tristate_output <= ceb and i_web and oeb;
+-- decoder_row_input <= i_address(5 downto 2); -- XXX
+-- decoder_col_input <= i_address(7 downto 6) & i_address(1 downto 0); -- XXX
+ decoder_row_input <= i_address(address_size-1 downto address_size/2); -- XXX
+ decoder_col_input <= i_address(address_size/2-1 downto 0); -- XXX
+-- decoder_row_input <= i_address(7 downto 4); -- XXX
+-- decoder_col_input <= i_address(3 downto 0); -- XXX
+-- decoder_col_input <= i_address; -- XXX
+
+-- process (tristate_input,tristate_output,decoder_row_output,decoder_col_output,data_in) is
+-- variable r : integer range 0 to 2**memory_rows-1;
+-- variable c : integer range 0 to 2**memory_cols-1;
+-- begin
+-- r := one_position(unsigned(decoder_row_output));
+-- c := one_position(unsigned(decoder_col_output));
+-- if (falling_edge(tristate_input) and tristate_output = '0') then
+-- mem(r,c) <= data_in;
+-- end if;
+-- if (tristate_input = '0' and rising_edge(tristate_output)) then
+-- data_out <= mem(r,c);
+-- end if;
+-- end process;
+
+ sram_data_generate : for i in 0 to data_size-1 generate
+ sram_cell_entity : sram_cell
+ Generic map (N=>memory_bits_rows) Port map (
+ i_ce=>ceb,
+ i_we=>web,
+ i_oe=>oeb,
+ i_address_row=>decoder_row_input,
+ i_address_col=>decoder_col_input,
+ i_bit=>data_in(i),
+ o_bit=>data_out(i)
+ );
+ end generate sram_data_generate;
+
+ input_IOBUFDS_generate : for i in 0 to data_size-1 generate
+-- input_IOBUFDS_inst : IOBUF port map (O=>data_in(i), I=>i_data(i), T=>not tristate_input);
+ input_IOBUFDS_inst : IBUF port map (O=>data_in(i), I=>i_data(i));
+ end generate input_IOBUFDS_generate;
+ output_OBUFTDS_generate : for i in 0 to data_size-1 generate
+ output_OBUFTDS_inst : IOBUF port map (O=>o_data(i), I=>data_out(i), T=>tristate_output);
+ end generate output_OBUFTDS_generate;
+
+-- mdc_entity : mem_decoder_col
+-- Port map (decoder_col_input=>decoder_col_input,decoder_col_output=>decoder_col_output,e=>'1');
+
+-- mdr_entity : mem_decoder_row
+-- Port map (decoder_row_input=>decoder_row_input,decoder_row_output=>decoder_row_output,e=>'1');
+
+end Behavioral;
diff --git a/vhdl_primitive/sram_cell.vhd b/vhdl_primitive/sram_cell.vhd
new file mode 100755
index 0000000..8009c5e
--- /dev/null
+++ b/vhdl_primitive/sram_cell.vhd
@@ -0,0 +1,131 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:47:11 05/02/2021
+-- Design Name:
+-- Module Name: sram_cell - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity sram_cell is
+Generic (
+ N : integer := 4
+);
+Port (
+ i_ce : in std_logic;
+ i_we : in std_logic;
+ i_oe : in std_logic;
+ i_address_row : in std_logic_vector(N-1 downto 0);
+ i_address_col : in std_logic_vector(N-1 downto 0);
+ i_bit : in std_logic;
+ o_bit : out std_logic
+);
+end sram_cell;
+
+architecture Behavioral of sram_cell is
+
+ component sram_row is
+ Generic (
+ N : integer
+ );
+ Port (
+ i_we : in std_logic;
+ i_oe : in std_logic;
+ i_address_col : in std_logic_vector(N-1 downto 0);
+ i_bit : in std_logic;
+ o_bit : out std_logic
+ );
+ end component sram_row;
+
+-- signal tristate_input,tristate_output : std_logic_vector(15 downto 0);
+ signal ibit,obit : std_logic_vector(2**N-1 downto 0);
+
+-- signal bufi1,bufi2 : std_logic := '0';
+-- signal bufo1,bufo2 : std_logic := '0';
+
+ signal we,oe : std_logic_vector(2**N-1 downto 0);
+ signal a : integer range 0 to 2**N-1;
+
+begin
+
+-- LDCPE_bufi1 : LDCPE port map (
+-- Q => bufi1,
+-- D => i_we,
+-- GE => i_ce,
+-- G => '1',
+-- CLR => '0',
+-- PRE => '0');
+-- LDCPE_bufi2 : LDCPE port map (
+-- Q => bufi2,
+-- D => bufi1,
+-- GE => i_ce,
+-- G => '1',
+-- CLR => not i_ce,
+-- PRE => '0');
+--
+-- LDCPE_bufo1 : LDCPE port map (
+-- Q => bufo1,
+-- D => i_oe,
+-- GE => i_ce,
+-- G => '1',
+-- CLR => '0',
+-- PRE => '0');
+-- LDCPE_bufo2 : LDCPE port map (
+-- Q => bufo2,
+-- D => bufo1,
+-- GE => i_ce,
+-- G => '1',
+-- CLR => not i_ce,
+-- PRE => '0');
+
+ sram_row_generate : for i in 0 to 2**N-1 generate
+ sram_col : sram_row Generic map (n=>N) Port map (
+ i_we=>we(i),
+ i_oe=>oe(i),
+ i_address_col=>i_address_col,
+ i_bit=>ibit(i),
+ o_bit=>obit(i)
+ );
+ end generate sram_row_generate;
+
+ a <= to_integer(unsigned(i_address_row));
+
+ sh : for i in 0 to 2**N-1 generate
+ we(i) <= '1' when (i=a and i_ce='1' and i_we='1') else '0';
+ end generate sh;
+-- tristate_input(to_integer(unsigned(i_address_row))) <= '1' when i_tristate_input='1' else '0';
+
+ si : for i in 0 to 2**N-1 generate
+ oe(i) <= '1' when (i=a and i_ce='1' and i_oe='1') else '0';
+ end generate si;
+-- tristate_output(to_integer(unsigned(i_address_row))) <= '1' when i_tristate_output='1' else '0';
+
+ sj : for i in 0 to 2**N-1 generate
+ ibit(i) <= i_bit when (i=a and i_ce='1' and i_we='1');
+ end generate sj;
+
+ o_bit <= obit(a) when i_ce='1' and i_oe='1';
+
+end Behavioral;
diff --git a/vhdl_primitive/sram_memory_1.vhd b/vhdl_primitive/sram_memory_1.vhd
new file mode 100755
index 0000000..2534def
--- /dev/null
+++ b/vhdl_primitive/sram_memory_1.vhd
@@ -0,0 +1,58 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:00:30 04/23/2021
+-- Design Name:
+-- Module Name: sram_memory_1 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity sram_memory_1 is
+Generic (
+ N : integer := 8;
+ M : integer := 4
+);
+Port (
+ clk,wr : in std_logic;
+ address : in integer range 0 to 2**M-1;
+ data : inout std_logic_vector(N-1 downto 0)
+);
+end sram_memory_1;
+
+architecture Behavioral of sram_memory_1 is
+ type memory is array (0 to 2**M-1) of std_logic_vector(N-1 downto 0);
+ signal ram : memory;
+begin
+ p0 : process (clk) is
+ begin
+ if (rising_edge(clk)) then
+ if (wr = '1') then
+ ram(address) <= data;
+ end if;
+ end if;
+ end process p0;
+ data <= ram(address) when wr='0' else (others => 'Z');
+end Behavioral;
+
diff --git a/vhdl_primitive/sram_memory_2.vhd b/vhdl_primitive/sram_memory_2.vhd
new file mode 100755
index 0000000..b913f9f
--- /dev/null
+++ b/vhdl_primitive/sram_memory_2.vhd
@@ -0,0 +1,63 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:05:07 04/23/2021
+-- Design Name:
+-- Module Name: sram_memory_2 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity sram_memory_2 is
+Generic (
+ N : integer := 8;
+ M : integer := 4
+);
+Port (
+ clk1,clk2,wr : in std_logic;
+ rd_address,wr_address : in integer range 0 to 2**M-1;
+ data_in : in std_logic_vector(N-1 downto 0);
+ data_out : out std_logic_vector(N-1 downto 0)
+);
+end sram_memory_2;
+
+architecture Behavioral of sram_memory_2 is
+ type memory is array(0 to 2**M-1) of std_logic_vector(N-1 downto 0);
+ signal ram : memory;
+begin
+ p0 : process (clk1) is
+ begin
+ if (rising_edge(clk1)) then
+ if (wr='1') then
+ ram(wr_address) <= data_in;
+ end if;
+ end if;
+ end process p0;
+ p1 : process (clk2) is
+ begin
+ if (rising_edge(clk2)) then
+ data_out <= ram(rd_address);
+ end if;
+ end process p1;
+end Behavioral;
diff --git a/vhdl_primitive/sram_row.vhd b/vhdl_primitive/sram_row.vhd
new file mode 100755
index 0000000..4693905
--- /dev/null
+++ b/vhdl_primitive/sram_row.vhd
@@ -0,0 +1,123 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:05:12 05/01/2021
+-- Design Name:
+-- Module Name: sram_row - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity sram_row is
+Generic (
+ N : integer := 4
+);
+Port (
+ i_we : in std_logic;
+ i_oe : in std_logic;
+ i_address_col : in std_logic_vector(N-1 downto 0);
+ i_bit : in std_logic;
+ o_bit : out std_logic
+);
+end sram_row;
+
+architecture Behavioral of sram_row is
+ signal sram_column : std_logic_vector(2**N-1 downto 0);
+ signal address_col : std_logic_vector(N-1 downto 0);
+
+-- signal bufi,bufo : std_logic;
+ signal we,oe,ibit : std_logic;
+-- attribute keep : string;
+-- attribute keep of sram_column : signal is "true";
+
+begin
+ we <= i_we;
+ oe <= i_oe;
+ address_col <= i_address_col;
+ ibit <= i_bit;
+--BUFG_inst1 : BUFG port map (O => bufi,I => i_tristate_input);
+--BUFG_inst2 : BUFG port map (O => bufo,I => i_tristate_output);
+-- bufi <= not (not i_tristate_input);
+-- bufo <= not (not i_tristate_output);
+-- sram_column_generate : for i in sram_column'range generate
+-- sram_column(i) <= i_bit when (i=to_integer(unsigned(i_address_col)) and rising_edge(i_tristate_input));
+-- end generate sram_column_generate;
+-- sram_column(to_integer(unsigned(i_address_col))) <= i_bit when falling_edge(bufi);
+-- o_bit <= sram_column(to_integer(unsigned(i_address_col))) when falling_edge(bufo);
+-- sram_column(to_integer(unsigned(i_address_col))) <= ibit when we='1' and oe = '0';
+-- p0 : process (we,oe,i_bit,sram_column,address_col) is
+-- begin
+-- if (we = '1' and oe = '0') then
+-- sram_column(to_integer(unsigned(address_col))) <= i_bit;
+-- elsif (oe = '1' and we = '0') then
+-- o_bit <= sram_column(to_integer(unsigned(address_col)));
+-- else
+-- sram_column(to_integer(unsigned(address_col))) <= sram_column(to_integer(unsigned(address_col)));
+-- end if;
+-- end process p0;
+
+-- p0 : process (sram_column,address_col,ibit) is
+-- begin
+-- l0 : for i in 0 to 2**N-1 loop
+-- if (i=to_integer(unsigned(address_col))) then
+-- sram_column(i) <= ibit;
+-- end if;
+-- end loop l0;
+-- end process p0;
+
+ p0 : process (sram_column,address_col,ibit,we) is
+ variable index : integer range 0 to 2**N-1;
+ begin
+ index := to_integer(unsigned(address_col));
+ sram_column(index) <= sram_column(index);
+ if (we = '0') then
+ sram_column(index) <= sram_column(index);
+ elsif (we = '1') then
+ sram_column(index) <= ibit;
+ end if;
+ end process p0;
+
+ p1 : process (sram_column,address_col,ibit,oe) is
+ variable index : integer range 0 to 2**N-1;
+ begin
+ index := to_integer(unsigned(address_col));
+ o_bit <= '0';
+ l0 : for i in 0 to 2**N-1 loop
+ if (i=index) then
+ if (oe = '1') then
+ o_bit <= sram_column(i);
+ end if;
+ end if;
+ end loop l0;
+ end process p1;
+
+-- o_bit <= sram_column(to_integer(unsigned(i_address_col)));
+
+-- g0 : for i in 0 to 2**N-1 generate
+-- LDCE_inst : LDCE
+-- generic map (INIT=>'0')
+-- port map (Q=>sram_column1(i),CLR=>'0',D=>sram_column(i),G=>'1',GE=>'1');
+-- end generate g0;
+
+end Behavioral;
diff --git a/vhdl_primitive/succesive_approximation_register.vhd b/vhdl_primitive/succesive_approximation_register.vhd
new file mode 100755
index 0000000..a62d93a
--- /dev/null
+++ b/vhdl_primitive/succesive_approximation_register.vhd
@@ -0,0 +1,119 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:19:16 04/18/2021
+-- Design Name:
+-- Module Name: succesive_approximation_register - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity succesive_approximation_register is
+Generic (
+n : integer := 4
+);
+Port (
+i_clock : in STD_LOGIC;
+i_reset : in STD_LOGIC;
+i_select : in STD_LOGIC;
+o_q : out STD_LOGIC_VECTOR (n-1 downto 0);
+o_end : inout STD_LOGIC
+);
+end succesive_approximation_register;
+
+architecture Behavioral of succesive_approximation_register is
+
+COMPONENT FDCPE_Q_QB IS
+Generic (
+ INIT : BIT := '0'
+);
+Port (
+ Q : out STD_LOGIC;
+ QB : out STD_LOGIC;
+ C : in STD_LOGIC;
+ CE : in STD_LOGIC;
+ CLR : in STD_LOGIC;
+ D : in STD_LOGIC;
+ PRE : in STD_LOGIC
+);
+END COMPONENT FDCPE_Q_QB;
+
+signal pull_up : std_logic;
+signal first_q,first_qb : std_logic;
+signal q1 : std_logic_vector(n-1 downto 0);
+signal qb1 : std_logic_vector(n-2 downto 0);
+signal q2 : std_logic_vector(n-1 downto 0);
+
+begin
+
+o_end <= q1(n-1);
+
+PULLUP_inst : PULLUP
+port map (O=>pull_up);
+
+first : FDCPE_Q_QB
+generic map (INIT => '0')
+port map (Q=>first_q,QB=>first_qb,C=>i_clock,CE=>'1',CLR=>not pull_up,D=>o_end,PRE=>not i_reset);
+
+FDCPE_g1 : for i in 0 to n-1 generate
+ n1_first : if (i=0) generate
+ FDCPE_inst : FDCPE_Q_QB
+ generic map (INIT => '0')
+ port map (Q=>q1(i),QB=>qb1(i),C=>i_clock,CE=>'1',CLR=>not i_reset,D=>first_q,PRE=>not pull_up);
+ end generate n1_first;
+ n1_chain : if (0 '0')
+ port map (Q=>q1(i),QB=>qb1(i),C=>i_clock,CE=>'1',CLR=>not i_reset,D=>q1(i-1),PRE=>not pull_up);
+ end generate n1_chain;
+ n1_last : if (i=n-1) generate
+ FDCPE_inst : FDCPE
+ generic map (INIT => '0')
+ port map (Q=>q1(n-1),C=>i_clock,CE=>'1',CLR=>not i_reset,D=>q1(i-1),PRE=>not pull_up);
+ end generate n1_last;
+end generate FDCPE_g1;
+
+FDCPE_g2 : for i in 0 to n-1 generate
+ n2_first : if (i=0) generate
+ FDCPE_inst : FDCPE
+ generic map (INIT => '0')
+ port map (Q=>q2(i),C=>first_qb,CE=>'1',CLR=>i_reset,D=>i_select,PRE=>pull_up);
+ end generate n2_first;
+ n2_chain : if (0 '0')
+ port map (Q=>q2(i),C=>qb1(i-1),CE=>'1',CLR=>i_reset,D=>i_select,PRE=>pull_up);
+ end generate n2_chain;
+end generate FDCPE_g2;
+
+OR_gates : for i in 0 to n-1 generate
+ or_first : if (i=0) generate
+ o_q(n-1-i) <= q2(i) or first_qb;
+ end generate or_first;
+ or_rest : if (0" TNM_NET = "CLK_A";
+TIMESPEC "TS_CLKA" = PERIOD "CLK_A" 10 ns;
+NET "Decimal_Digit<2>" TNM_NET = "CLK_B";
+TIMESPEC "TS_CLKB" = PERIOD "CLK_B" 10 ns;
+NET "Decimal_Digit<1>" TNM_NET = "CLK_C";
+TIMESPEC "TS_CLKC" = PERIOD "CLK_C" 10 ns;
+NET "Decimal_Digit<0>" TNM_NET = "CLK_D";
+TIMESPEC "TS_CLKD" = PERIOD "CLK_D" 10 ns;
diff --git a/vhdl_primitive/tab31.vhd b/vhdl_primitive/tab31.vhd
new file mode 100644
index 0000000..88d31be
--- /dev/null
+++ b/vhdl_primitive/tab31.vhd
@@ -0,0 +1,84 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 10:27:24 06/05/2023
+-- Design Name: BCD and Ex-3 decode from 0-9
+-- Module Name: tab31 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity tab31 is
+port (
+signal Decimal_Digit : in bit_vector (3 downto 0);
+signal BCD8421_Codes : out bit_vector (3 downto 0);
+signal Excess3_Codes : out bit_vector (3 downto 0)
+);
+end tab31;
+
+architecture Behavioral of tab31 is
+
+begin
+
+p0 : process (Decimal_Digit) is
+begin
+ case (Decimal_Digit) is
+ when "0000" =>
+ BCD8421_Codes <= "0000";
+ Excess3_Codes <= "0011";
+ when "0001" =>
+ BCD8421_Codes <= "0001";
+ Excess3_Codes <= "0100";
+ when "0010" =>
+ BCD8421_Codes <= "0010";
+ Excess3_Codes <= "0101";
+ when "0011" =>
+ BCD8421_Codes <= "0011";
+ Excess3_Codes <= "0110";
+ when "0100" =>
+ BCD8421_Codes <= "0100";
+ Excess3_Codes <= "0111";
+ when "0101" =>
+ BCD8421_Codes <= "0101";
+ Excess3_Codes <= "1000";
+ when "0110" =>
+ BCD8421_Codes <= "0110";
+ Excess3_Codes <= "1001";
+ when "0111" =>
+ BCD8421_Codes <= "0111";
+ Excess3_Codes <= "1010";
+ when "1000" =>
+ BCD8421_Codes <= "1000";
+ Excess3_Codes <= "1011";
+ when "1001" =>
+ BCD8421_Codes <= "1001";
+ Excess3_Codes <= "1100";
+ when others =>
+ BCD8421_Codes <= "0000";
+ Excess3_Codes <= "0000";
+ end case;
+end process p0;
+
+end Behavioral;
+
diff --git a/vhdl_primitive/tb_CLKDIV_3.vhd b/vhdl_primitive/tb_CLKDIV_3.vhd
new file mode 100644
index 0000000..af8f725
--- /dev/null
+++ b/vhdl_primitive/tb_CLKDIV_3.vhd
@@ -0,0 +1,50 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/CLKDIV_3.sch - Wed Sep 20 12:23:31 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY CLKDIV_3_CLKDIV_3_sch_tb IS
+END CLKDIV_3_CLKDIV_3_sch_tb;
+ARCHITECTURE behavioral OF CLKDIV_3_CLKDIV_3_sch_tb IS
+
+-- XXX Clock divided by 3 with 75% Duty Cycle
+COMPONENT CLKDIV_3
+PORT( clk : IN STD_LOGIC;
+clk_out : OUT STD_LOGIC);
+END COMPONENT;
+
+SIGNAL clk : STD_LOGIC := '0';
+SIGNAL clk_out : STD_LOGIC;
+
+BEGIN
+
+clk <= not clk after 10 ns;
+
+UUT: CLKDIV_3 PORT MAP(
+clk => clk,
+clk_out => clk_out
+);
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+WAIT for 10 us; -- will wait forever
+report "tb done" severity failure;
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_CLKDIV_3_50.vhd b/vhdl_primitive/tb_CLKDIV_3_50.vhd
new file mode 100644
index 0000000..261bc16
--- /dev/null
+++ b/vhdl_primitive/tb_CLKDIV_3_50.vhd
@@ -0,0 +1,50 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/CLKDIV_3_50.sch - Wed Sep 20 13:54:35 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY CLKDIV_3_50_CLKDIV_3_50_sch_tb IS
+END CLKDIV_3_50_CLKDIV_3_50_sch_tb;
+ARCHITECTURE behavioral OF CLKDIV_3_50_CLKDIV_3_50_sch_tb IS
+
+COMPONENT CLKDIV_3_50
+PORT( clk_in : IN STD_LOGIC;
+clk_out : OUT STD_LOGIC);
+END COMPONENT;
+
+SIGNAL clk_in : STD_LOGIC := '0';
+SIGNAL clk_out : STD_LOGIC;
+
+BEGIN
+
+clk_in <= not clk_in after 10 ns;
+
+UUT: CLKDIV_3_50 PORT MAP(
+clk_in => clk_in,
+clk_out => clk_out
+);
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+wait for 11.123 us;
+report "tb done" severity failure;
+WAIT; -- will wait forever
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_CLKDIV_4dot5.vhd b/vhdl_primitive/tb_CLKDIV_4dot5.vhd
new file mode 100644
index 0000000..5fa10b8
--- /dev/null
+++ b/vhdl_primitive/tb_CLKDIV_4dot5.vhd
@@ -0,0 +1,55 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/CLKDIV_4dot5.sch - Mon Sep 18 21:07:35 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY CLKDIV_4dot5_CLKDIV_4dot5_sch_tb IS
+END CLKDIV_4dot5_CLKDIV_4dot5_sch_tb;
+ARCHITECTURE behavioral OF CLKDIV_4dot5_CLKDIV_4dot5_sch_tb IS
+
+COMPONENT CLKDIV_4dot5
+PORT( clk_in : IN STD_LOGIC;
+clk_out : OUT STD_LOGIC);
+END COMPONENT;
+
+SIGNAL clk_in : STD_LOGIC := '0';
+SIGNAL clk_out : STD_LOGIC;
+
+constant clk_in_period : time := 10 ns;
+
+BEGIN
+
+cp : process is
+begin
+clk_in <= not clk_in;
+wait for clk_in_period;
+end process cp;
+
+UUT: CLKDIV_4dot5 PORT MAP(
+clk_in => clk_in,
+clk_out => clk_out
+);
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+wait for 10 us;
+report "tb done" severity failure;
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_DET_FF.vhd b/vhdl_primitive/tb_DET_FF.vhd
new file mode 100644
index 0000000..1d2bb52
--- /dev/null
+++ b/vhdl_primitive/tb_DET_FF.vhd
@@ -0,0 +1,75 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/DET_FF.sch - Mon Sep 18 19:24:29 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY DET_FF_DET_FF_sch_tb IS
+END DET_FF_DET_FF_sch_tb;
+ARCHITECTURE behavioral OF DET_FF_DET_FF_sch_tb IS
+
+COMPONENT DET_FF
+PORT( CLK : IN STD_LOGIC;
+CLR : IN STD_LOGIC;
+D : IN STD_LOGIC;
+Q : OUT STD_LOGIC);
+END COMPONENT;
+
+SIGNAL CLK : STD_LOGIC := '0';
+SIGNAL CLR : STD_LOGIC := '0';
+SIGNAL D : STD_LOGIC := '0';
+SIGNAL Q : STD_LOGIC;
+
+signal clock : std_logic := '0';
+constant clock_period : time := 10 ns;
+
+BEGIN
+
+cp : process is
+begin
+clock <= not clock;
+wait for clock_period/2;
+end process cp;
+
+CLK <= clock;
+
+UUT: DET_FF PORT MAP(
+CLK => CLK,
+CLR => CLR,
+D => D,
+Q => Q
+);
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+CLR <= '1';
+wait for clock_period*2;
+CLR <= '0';
+wait for clock_period*3;
+D <= '1';
+wait for clock_period*2.5;
+D <= '0';
+wait for clock_period*2.5;
+D <= '1';
+wait for clock_period*1.5;
+D <= '0';
+wait for clock_period*1.5;
+report "tb done" severity failure;
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_FA_COUNT_NUMBER_ONE.vhd b/vhdl_primitive/tb_FA_COUNT_NUMBER_ONE.vhd
new file mode 100644
index 0000000..4376dc5
--- /dev/null
+++ b/vhdl_primitive/tb_FA_COUNT_NUMBER_ONE.vhd
@@ -0,0 +1,50 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/FA_COUNT_NUMBER_ONE.sch - Mon Sep 18 20:06:41 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY FA_COUNT_NUMBER_ONE_FA_COUNT_NUMBER_ONE_sch_tb IS
+END FA_COUNT_NUMBER_ONE_FA_COUNT_NUMBER_ONE_sch_tb;
+ARCHITECTURE behavioral OF FA_COUNT_NUMBER_ONE_FA_COUNT_NUMBER_ONE_sch_tb IS
+
+COMPONENT FA_COUNT_NUMBER_ONE
+PORT( INPUT : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+OUTPUT : OUT STD_LOGIC_VECTOR (2 DOWNTO 0));
+END COMPONENT;
+
+SIGNAL INPUT : STD_LOGIC_VECTOR (6 DOWNTO 0);
+SIGNAL OUTPUT : STD_LOGIC_VECTOR (2 DOWNTO 0);
+
+BEGIN
+
+UUT: FA_COUNT_NUMBER_ONE PORT MAP(
+INPUT => INPUT,
+OUTPUT => OUTPUT
+);
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+l0 : for i in 0 to 2**7-1 loop
+INPUT <= std_logic_vector (to_unsigned (i,7));
+wait for 10 ns;
+end loop l0;
+report "tb done" severity failure;
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_FA_MUX41.vhd b/vhdl_primitive/tb_FA_MUX41.vhd
new file mode 100644
index 0000000..32a420f
--- /dev/null
+++ b/vhdl_primitive/tb_FA_MUX41.vhd
@@ -0,0 +1,69 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/FA_MUX41.sch - Mon Sep 18 18:48:00 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY FA_MUX41_FA_MUX41_sch_tb IS
+END FA_MUX41_FA_MUX41_sch_tb;
+ARCHITECTURE behavioral OF FA_MUX41_FA_MUX41_sch_tb IS
+
+COMPONENT FA_MUX41
+PORT( Sum : OUT STD_LOGIC;
+Carry_out : OUT STD_LOGIC;
+Carry_in : IN STD_LOGIC;
+A : IN STD_LOGIC;
+B : IN STD_LOGIC);
+END COMPONENT;
+
+SIGNAL Sum : STD_LOGIC;
+SIGNAL Carry_out : STD_LOGIC;
+SIGNAL Carry_in : STD_LOGIC;
+SIGNAL A : STD_LOGIC;
+SIGNAL B : STD_LOGIC;
+
+signal CBA : std_logic_vector (2 downto 0);
+
+BEGIN
+
+A <= CBA (2);
+B <= CBA (1);
+Carry_in <= CBA (0);
+
+UUT: FA_MUX41 PORT MAP(
+Sum => Sum,
+Carry_out => Carry_out,
+Carry_in => Carry_in,
+A => A,
+B => B
+);
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+CBA <= "000"; wait for 10 ns;
+CBA <= "001"; wait for 10 ns;
+CBA <= "010"; wait for 10 ns;
+CBA <= "011"; wait for 10 ns;
+CBA <= "100"; wait for 10 ns;
+CBA <= "101"; wait for 10 ns;
+CBA <= "110"; wait for 10 ns;
+CBA <= "111"; wait for 10 ns;
+report "tb done" severity failure;
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_HANDSHAKE_BASED_PULSE_SYNCHRONIZER.vhd b/vhdl_primitive/tb_HANDSHAKE_BASED_PULSE_SYNCHRONIZER.vhd
new file mode 100644
index 0000000..6f47cd6
--- /dev/null
+++ b/vhdl_primitive/tb_HANDSHAKE_BASED_PULSE_SYNCHRONIZER.vhd
@@ -0,0 +1,75 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/HANDSHAKE_BASED_PULSE_SYNCHRONIZER.sch - Fri Sep 29 16:29:27 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY HANDSHAKE_BASED_PULSE_SYNCHRONIZER_HANDSHAKE_BASED_PULSE_SYNCHRONIZER_sch_tb IS
+END HANDSHAKE_BASED_PULSE_SYNCHRONIZER_HANDSHAKE_BASED_PULSE_SYNCHRONIZER_sch_tb;
+
+ARCHITECTURE behavioral OF HANDSHAKE_BASED_PULSE_SYNCHRONIZER_HANDSHAKE_BASED_PULSE_SYNCHRONIZER_sch_tb IS
+
+COMPONENT HANDSHAKE_BASED_PULSE_SYNCHRONIZER
+PORT( s_input : IN STD_LOGIC;
+clk_a : IN STD_LOGIC;
+clk_b : IN STD_LOGIC;
+sync_out : OUT STD_LOGIC;
+busy : OUT STD_LOGIC);
+END COMPONENT;
+
+SIGNAL s_input : STD_LOGIC := '0';
+SIGNAL clk_a : STD_LOGIC := '0';
+SIGNAL clk_b : STD_LOGIC := '0';
+SIGNAL sync_out : STD_LOGIC := '0';
+SIGNAL busy : STD_LOGIC := '0';
+
+constant clk_a_period : time := 10 ns;
+constant clk_b_period : time := 20 ns;
+
+BEGIN
+
+pclka : process is
+begin
+clk_a <= not clk_a;
+wait for clk_a_period/2;
+end process pclka;
+
+pclkb : process is
+begin
+clk_b <= not clk_b;
+wait for clk_b_period/2;
+end process pclkb;
+
+UUT: HANDSHAKE_BASED_PULSE_SYNCHRONIZER PORT MAP(
+s_input => s_input,
+clk_a => clk_a,
+clk_b => clk_b,
+sync_out => sync_out,
+busy => busy
+);
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+wait for clk_a_period*10;
+s_input <= '1'; wait for clk_a_period*1; s_input <= '0';
+wait for 1 us;
+report "tb done" severity failure;
+WAIT; -- will wait forever
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_MUX_SYNCHRONIZER.vhd b/vhdl_primitive/tb_MUX_SYNCHRONIZER.vhd
new file mode 100644
index 0000000..e9617f7
--- /dev/null
+++ b/vhdl_primitive/tb_MUX_SYNCHRONIZER.vhd
@@ -0,0 +1,83 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/MUX_SYNCHRONIZER.sch - Fri Sep 29 17:35:02 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY MUX_SYNCHRONIZER_MUX_SYNCHRONIZER_sch_tb IS
+END MUX_SYNCHRONIZER_MUX_SYNCHRONIZER_sch_tb;
+
+ARCHITECTURE behavioral OF MUX_SYNCHRONIZER_MUX_SYNCHRONIZER_sch_tb IS
+
+COMPONENT MUX_SYNCHRONIZER
+PORT( clk_b : IN STD_LOGIC;
+en : IN STD_LOGIC;
+clk_a : IN STD_LOGIC;
+op : OUT STD_LOGIC;
+clk_a_data : IN STD_LOGIC);
+END COMPONENT;
+
+SIGNAL clk_a : STD_LOGIC := '1';
+SIGNAL clk_b : STD_LOGIC := '1';
+SIGNAL en : STD_LOGIC := '0';
+SIGNAL op : STD_LOGIC := '0';
+SIGNAL clk_a_data : STD_LOGIC := '0';
+
+constant clk_a_period : time := 10 ns;
+constant clk_b_period : time := 20 ns;
+
+BEGIN
+
+pclka : process is
+begin
+clk_a <= not clk_a;
+wait for clk_a_period/2;
+end process pclka;
+
+pclkb : process is
+begin
+clk_b <= not clk_b;
+wait for clk_b_period/2;
+end process pclkb;
+
+UUT: MUX_SYNCHRONIZER PORT MAP(
+clk_b => clk_b,
+en => en,
+clk_a => clk_a,
+op => op,
+clk_a_data => clk_a_data
+);
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+wait for clk_a_period*2;
+clk_a_data <= '1'; en <= '1'; wait for clk_a_period*1; en <= '0'; wait for clk_a_period*1;
+clk_a_data <= '1'; en <= '1'; wait for clk_a_period*1; en <= '0'; wait for clk_a_period*1;
+clk_a_data <= '1'; en <= '1'; wait for clk_a_period*1; en <= '0'; wait for clk_a_period*1;
+clk_a_data <= '0'; en <= '1'; wait for clk_a_period*1; en <= '0'; wait for clk_a_period*1;
+clk_a_data <= '1'; en <= '1'; wait for clk_a_period*1; en <= '0'; wait for clk_a_period*1;
+clk_a_data <= '0'; en <= '1'; wait for clk_a_period*1; en <= '0'; wait for clk_a_period*1;
+clk_a_data <= '1'; en <= '1'; wait for clk_a_period*1; en <= '0'; wait for clk_a_period*1;
+clk_a_data <= '0'; en <= '1'; wait for clk_a_period*1; en <= '0'; wait for clk_a_period*1;
+wait for clk_a_period*10;
+wait for 0.5 us;
+report "tb done" severity failure;
+WAIT; -- will wait forever
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_TOGGLE_SYNCHRONIZER.vhd b/vhdl_primitive/tb_TOGGLE_SYNCHRONIZER.vhd
new file mode 100644
index 0000000..4162778
--- /dev/null
+++ b/vhdl_primitive/tb_TOGGLE_SYNCHRONIZER.vhd
@@ -0,0 +1,80 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/TOGGLE_SYNCHRONIZER.sch - Wed Sep 20 14:20:16 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY TOGGLE_SYNCHRONIZER_TOGGLE_SYNCHRONIZER_sch_tb IS
+END TOGGLE_SYNCHRONIZER_TOGGLE_SYNCHRONIZER_sch_tb;
+ARCHITECTURE behavioral OF TOGGLE_SYNCHRONIZER_TOGGLE_SYNCHRONIZER_sch_tb IS
+
+COMPONENT TOGGLE_SYNCHRONIZER
+PORT( s_input : IN STD_LOGIC;
+clk_a : IN STD_LOGIC;
+clk_b : IN STD_LOGIC;
+sync_out : OUT STD_LOGIC);
+END COMPONENT;
+
+SIGNAL s_input : STD_LOGIC := '0';
+SIGNAL clk_a : STD_LOGIC := '0';
+SIGNAL clk_b : STD_LOGIC := '0';
+SIGNAL sync_out : STD_LOGIC;
+
+constant clk_a_period : time := 10.7 ns;
+constant clk_b_period : time := 19.3 ns;
+
+BEGIN
+
+clk_a <= not clk_a after clk_a_period/2;
+clk_b <= not clk_b after clk_b_period/2;
+
+UUT: TOGGLE_SYNCHRONIZER PORT MAP(
+s_input => s_input,
+clk_a => clk_a,
+clk_b => clk_b,
+sync_out => sync_out
+);
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+wait for 4.1 ns;
+
+s_input <= '0';
+wait for 10 ns;
+s_input <= '1';
+wait for 5 ns;
+s_input <= '0';
+
+wait for 3.2 ns;
+
+s_input <= '0';
+wait for 10 ns;
+s_input <= '1';
+wait for 5 ns;
+s_input <= '0';
+
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+tb_done : process
+begin
+wait for 10 us;
+report "tb done" severity failure;
+WAIT; -- will wait forever
+end process tb_done;
+
+END;
diff --git a/vhdl_primitive/tb_and_n_gate.vhd b/vhdl_primitive/tb_and_n_gate.vhd
new file mode 100755
index 0000000..a6b1f23
--- /dev/null
+++ b/vhdl_primitive/tb_and_n_gate.vhd
@@ -0,0 +1,83 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:07:22 04/18/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_and_n_gate.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: AND_N_GATE
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_and_n_gate IS
+END tb_and_n_gate;
+
+ARCHITECTURE behavior OF tb_and_n_gate IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT AND_N_GATE
+PORT(
+input : IN std_logic_vector(7 downto 0);
+output : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal input : std_logic_vector(7 downto 0) := (others => '0');
+
+--Outputs
+signal output : std_logic;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: AND_N_GATE PORT MAP (
+input => input,
+output => output
+);
+
+-- Stimulus process
+stim_proc: process
+begin
+-- insert stimulus here
+input <= (others => '1');
+wait for 100 ns;
+input <= (others => '0');
+wait for 100 ns;
+input <= "10101010";
+wait for 100 ns;
+input <= "01010101";
+wait for 100 ns;
+input <= "00000001";
+wait for 100 ns;
+input <= "10000001";
+wait for 100 ns;
+input <= "11111111";
+wait for 100 ns;
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_circuit_ripplecounter_dff.vhd b/vhdl_primitive/tb_circuit_ripplecounter_dff.vhd
new file mode 100644
index 0000000..d92625c
--- /dev/null
+++ b/vhdl_primitive/tb_circuit_ripplecounter_dff.vhd
@@ -0,0 +1,102 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:57:37 07/05/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_circuit_ripplecounter_dff.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: circuit_ripplecounter_dff
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_circuit_ripplecounter_dff IS
+END tb_circuit_ripplecounter_dff;
+
+ARCHITECTURE behavior OF tb_circuit_ripplecounter_dff IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT circuit_ripplecounter_dff
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+i_input : IN std_logic;
+o_output : OUT std_logic
+);
+END COMPONENT;
+
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+signal i_input : std_logic := '0';
+
+--Outputs
+signal o_output : std_logic;
+
+-- Clock period definitions
+constant i_clock_period : time := 10 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: circuit_ripplecounter_dff PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+i_input => i_input,
+o_output => o_output
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+i_reset <= '1';
+wait for 10*i_clock_period;
+i_reset <= '0';
+wait for i_clock_period*10;
+
+-- insert stimulus here
+i_input <= '1';
+wait for 20*i_clock_period;
+i_input <= '0';
+wait for i_clock_period;
+
+
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_clk_gate1.vhd b/vhdl_primitive/tb_clk_gate1.vhd
new file mode 100644
index 0000000..fe8c39d
--- /dev/null
+++ b/vhdl_primitive/tb_clk_gate1.vhd
@@ -0,0 +1,67 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/clk_gate1.sch - Tue Aug 29 15:19:47 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY clk_gate1_clk_gate1_sch_tb IS
+END clk_gate1_clk_gate1_sch_tb;
+ARCHITECTURE behavioral OF clk_gate1_clk_gate1_sch_tb IS
+
+COMPONENT clk_gate1
+PORT( clk_in : IN STD_LOGIC;
+enable : IN STD_LOGIC;
+clk_out : OUT STD_LOGIC);
+END COMPONENT;
+
+SIGNAL clk_in : STD_LOGIC := '0';
+SIGNAL enable : STD_LOGIC := '0';
+SIGNAL clk_out : STD_LOGIC := '0';
+
+constant clk_in_period : time := 10 ns;
+
+BEGIN
+
+UUT: clk_gate1 PORT MAP(
+clk_in => clk_in,
+enable => enable,
+clk_out => clk_out
+);
+
+pc : process is
+begin
+clk_in <= '0';
+wait for clk_in_period/2;
+clk_in <= '1';
+wait for clk_in_period/2;
+end process pc;
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+--wait for 111.13 ns;
+wait for 109.13 ns;
+enable <= '1';
+--wait for 205.13 ns;
+wait for 206.13 ns;
+enable <= '0';
+wait for 10 us;
+report "tb done" severity failure;
+WAIT; -- will wait forever
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_counter_test1.vhd b/vhdl_primitive/tb_counter_test1.vhd
new file mode 100644
index 0000000..81dff62
--- /dev/null
+++ b/vhdl_primitive/tb_counter_test1.vhd
@@ -0,0 +1,95 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:08:30 12/04/2024
+-- Design Name:
+-- Module Name: /home/user/_WORKSPACE_/kedziorno/vhdl_projects/vhdl_primitive/tb_counter_test1.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: counter_test1
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_counter_test1 IS
+END tb_counter_test1;
+
+ARCHITECTURE behavior OF tb_counter_test1 IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT counter_test1
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+y_inc : OUT signed(31 downto 0);
+y_dec : OUT signed(31 downto 0)
+);
+END COMPONENT;
+
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+
+--Outputs
+signal y_inc : signed(31 downto 0);
+signal y_dec : signed(31 downto 0);
+
+-- Clock period definitions
+constant i_clock_period : time := 10 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: counter_test1 PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+y_inc => y_inc,
+y_dec => y_dec
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+i_reset <= '1';
+wait for 100 ns;
+i_reset <= '0';
+wait for i_clock_period*10;
+-- insert stimulus here
+wait for 1 ms;
+report "tb done" severity failure;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_counter_test2.vhd b/vhdl_primitive/tb_counter_test2.vhd
new file mode 100644
index 0000000..a8649e2
--- /dev/null
+++ b/vhdl_primitive/tb_counter_test2.vhd
@@ -0,0 +1,115 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:59:57 02/25/2025
+-- Design Name:
+-- Module Name: /home/user/_WORKSPACE_/kedziorno/vhdl_projects/vhdl_primitive/tb_counter_test2.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: counter_test2
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_counter_test2 IS
+END tb_counter_test2;
+
+ARCHITECTURE behavior OF tb_counter_test2 IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT counter_test2
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+i_a : IN std_logic;
+i_b : IN std_logic;
+o_counter : OUT std_logic_vector (31 downto 0)
+);
+END COMPONENT counter_test2;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+signal i_a : std_logic := '0';
+signal i_b : std_logic := '0';
+
+--Outputs
+signal o_counter : std_logic_vector (31 downto 0);
+
+-- Clock period definitions
+constant i_clock_period : time := 10 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: counter_test2
+PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+i_a => i_a,
+i_b => i_b,
+o_counter => o_counter
+);
+
+-- Clock process definitions
+i_clock_process : process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process i_clock_process;
+
+-- Stimulus process
+stim_proc : process
+begin
+-- hold reset state for 100 ns.
+i_reset <= '1';
+wait for 100 ns;
+i_reset <= '0';
+wait for i_clock_period*10;
+-- insert stimulus here
+i_a <= '0';
+i_b <= '0';
+wait for i_clock_period*11;
+-- count up
+i_a <= '0';
+i_b <= '1';
+wait for i_clock_period*22;
+-- count down
+i_a <= '1';
+i_b <= '0';
+wait for i_clock_period*22;
+i_a <= '1';
+i_b <= '1';
+wait for i_clock_period*11;
+i_a <= '0';
+i_b <= '0';
+wait for i_clock_period*11;
+wait for i_clock_period*1;
+report "tb done" severity failure;
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_debounce.vhd b/vhdl_primitive/tb_debounce.vhd
new file mode 100755
index 0000000..001b18c
--- /dev/null
+++ b/vhdl_primitive/tb_debounce.vhd
@@ -0,0 +1,348 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:03:02 03/09/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/pwm_led/tb_debounce.vhd
+-- Project Name: pwm_led
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: debounce
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE work.p_globals.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_debounce IS
+END tb_debounce;
+
+ARCHITECTURE behavior OF tb_debounce IS
+
+ -- Constant
+ constant DEBOUNCE_SIZE : integer := 8;
+ constant DEBOUNCE_RC_N : integer := 18; -- XXX -1 bit for 2**n
+ constant DEBOUNCE_RC_MAX : integer := 85000; -- XXX must be ((2**N)/4)*clock_period , 85000=~1.7ms on 20ns clock
+ constant W0_COUNT : integer := 80;
+ constant G_BOARD_CLOCK : integer := 50_000_000;
+ constant LFSR_SIZE : integer := 32;
+ constant LFSR_SIZE_BITS : integer := 32;
+ constant GRAYCODE_SIZE : integer := 8;
+ constant GRAYCODE_SIZE_BITS : integer := 8;
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ component new_debounce is
+ generic ( -- ripplecounter N bits (RC_N=N+1,RC_MAX=2**N)
+ G_RC_N : integer := 5;
+ G_RC_MAX : integer := 16
+ );
+ port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_b : in std_logic;
+ o_db : out std_logic
+ );
+ end component new_debounce;
+
+ COMPONENT lfsr1 IS
+ GENERIC (G_SIZE : integer);
+ PORT (
+ reset : in std_logic;
+ clk : in std_logic;
+ enable : in std_logic;
+ count : out std_logic_vector (G_SIZE-1 downto 0) -- lfsr output
+ );
+ END COMPONENT lfsr1;
+
+ COMPONENT graycode IS
+ GENERIC (G_SIZE : integer);
+ PORT (
+ reset : in std_logic;
+ clk : in std_logic;
+ enable : in std_logic;
+ input : in std_logic_vector (G_SIZE-1 downto 0);
+ output : out std_logic_vector (G_SIZE-1 downto 0)
+ );
+ END COMPONENT graycode;
+
+ --Inputs
+ signal i_clk : std_logic := '0';
+ signal i_btn : std_logic := '0';
+ signal reset : std_logic := '0';
+ signal reset_db : std_logic := '0';
+ signal enable_gc : std_logic := '0';
+ signal enable_lfsr : std_logic := '0';
+ signal i_int : std_logic_vector (GRAYCODE_SIZE_BITS-1 downto 0) := (others => '0');
+
+ --Outputs
+ signal o_db_btn : std_logic;
+ signal o_gc : std_logic_vector (GRAYCODE_SIZE_BITS-1 downto 0);
+ signal o_lfsr : std_logic_vector (LFSR_SIZE_BITS-1 downto 0);
+
+ -- Clock period definitions
+ constant i_clk_period : time := (1_000_000_000/G_BOARD_CLOCK) * 1 ns; -- XXX 50Mhz
+-- constant i_clk_period : time := integer'value(time'image(i_clk_period_original)) * 1000*1 ns;
+
+ -- States
+ type state_type is (idle,start,
+ lfsr_enable,lfsr_disable,lfsr_send,lfsr_increment,lfsr_wait0,
+ gc_send,gc_increment,gc_wait0,
+ stop);
+ signal state : state_type := idle;
+ signal simulation_finish : std_logic := '0';
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+
+ uut : new_debounce
+ generic map (G_RC_N => DEBOUNCE_RC_N, G_RC_MAX => DEBOUNCE_RC_MAX) -- XXX 50 ms
+ port map (
+ i_clock => i_clk,
+ i_reset => reset_db,
+ i_b => i_btn,
+ o_db => o_db_btn
+ );
+
+ uut_lfsr: lfsr1
+ GENERIC MAP (G_SIZE => LFSR_SIZE_BITS)
+ PORT MAP (
+ reset => reset,
+ clk => i_clk,
+ enable => enable_lfsr,
+ count => o_lfsr
+ );
+
+ uut_graycode: graycode
+ GENERIC MAP (G_SIZE => GRAYCODE_SIZE_BITS)
+ PORT MAP (
+ reset => reset,
+ clk => i_clk,
+ enable => enable_gc,
+ input => i_int,
+ output => o_gc
+ );
+
+ -- Clock process definitions
+ i_clk_process :process
+ begin
+ while simulation_finish = '0' loop
+ i_clk <= '0';
+ wait for i_clk_period/2;
+ i_clk <= '1';
+ wait for i_clk_period/2;
+ end loop;
+ report "simulation_finish" severity note;
+ wait;
+ end process;
+
+ p0 : process is
+ begin
+ reset_db <= '1'; -- XXX
+ wait for i_clk_period;
+ reset_db <= '0';
+ wait for i_clk_period;
+
+ wait for 1 ms;
+
+ i_btn <= '1';
+ wait for 3 ms; -- XXX
+ i_btn <= '0';
+ wait for i_clk_period;
+
+ wait for 1 ms;
+
+ reset_db <= '1'; -- XXX
+ wait for i_clk_period;
+ reset_db <= '0';
+ wait for i_clk_period;
+
+ wait for 1 ms;
+
+ i_btn <= '1';
+ wait for 1.8 ms; -- XXX
+ i_btn <= '0';
+ wait for i_clk_period;
+
+ wait for 1 ms;
+
+ reset_db <= '1'; -- XXX
+ wait for i_clk_period;
+ reset_db <= '0';
+ wait for i_clk_period;
+
+ wait for 1 ms;
+
+ i_btn <= '1';
+ wait for 2.2 ms; -- XXX
+ i_btn <= '0';
+ wait for i_clk_period;
+
+ wait for 1 ms;
+
+ reset_db <= '1'; -- XXX
+ wait for i_clk_period;
+ reset_db <= '0';
+ wait for i_clk_period;
+
+ wait for 1 ms;
+
+ i_btn <= '1';
+-- wait for 1_699_999_999.999_999 * 1 ps; -- XXX no catch
+-- wait for 1_700_000_000.000_000 * 1 ps; -- XXX no catch
+-- wait for 1_700_000_000.000_000 * 1 ps + 1 ps; -- XXX no catch
+-- wait for 1_700_000_000.000_000 * 1 ps + 14 ps; -- XXX no catch
+-- wait for 1_700_000_000.000_000 * 1 ps + 15 ps; -- XXX catch
+ wait for 1.75 ms;
+ i_btn <= '0';
+ wait for i_clk_period;
+
+ wait for 1 ms;
+
+ reset_db <= '1'; -- XXX
+ wait for i_clk_period;
+ reset_db <= '0';
+ wait for i_clk_period;
+
+ wait for 1 ms;
+
+ i_btn <= '1';
+ wait for 1.6 ms;
+ i_btn <= '0';
+ wait for i_clk_period;
+
+ wait for 1 ms;
+
+ reset_db <= '1'; -- XXX
+ wait for i_clk_period;
+ reset_db <= '0';
+ wait for i_clk_period;
+
+ simulation_finish <= '1';
+
+ wait;
+ end process p0;
+
+-- -- Stimulus process
+-- stim_proc: process (i_clk) is
+--
+-- constant WAIT0_COUNT : integer := W0_COUNT;
+-- variable wait0 : integer range 0 to WAIT0_COUNT-1 := 0;
+---- LFSR
+-- variable index : integer range 0 to LFSR_SIZE-1 := 0;
+-- constant send_the_same : integer := 1;
+-- variable send_the_same_index : integer range 0 to send_the_same-1 := 0;
+---- GRAYCODE
+-- constant o_gc_max : integer := GRAYCODE_SIZE;
+-- variable o_gc_index : integer range 0 to o_gc_max-1 := 0;
+-- constant gc_max : std_logic_vector(GRAYCODE_SIZE_BITS-1 downto 0) := (others => '1');
+-- variable gc_index : std_logic_vector(GRAYCODE_SIZE_BITS-1 downto 0) := (others => '0');
+--
+-- begin
+--
+-- -- insert stimulus here
+---- GRAYCODE
+-- if (rising_edge(i_clk)) then
+-- case (state) is
+-- when idle =>
+-- REPORT "CLOCK PERIOD " & time'image(i_clk_period) SEVERITY NOTE;
+-- state <= start;
+-- reset <= '1', '0' after 100 ns;
+-- reset_db <= '1';
+-- when start =>
+-- state <= gc_send;
+-- REPORT "GRAYCODE" SEVERITY NOTE;
+-- reset_db <= '0';
+-- when gc_send => -- start from gc mode
+-- reset_db <= '0';
+-- if (o_gc_index = o_gc_max-1) then
+-- state <= gc_increment;
+-- o_gc_index := 0;
+-- enable_gc <= '1';
+-- else
+-- state <= gc_send;
+-- i_btn <= o_gc(o_gc_index);
+-- o_gc_index := o_gc_index + 1;
+-- end if;
+-- when gc_increment =>
+-- enable_gc <= '0';
+-- if (to_integer(unsigned(gc_index)) = to_integer(unsigned(gc_max))-1) then
+-- state <= lfsr_enable; -- jump to lfsr mode
+-- REPORT "LFSR" SEVERITY NOTE;
+-- gc_index := std_logic_vector(to_unsigned(0,GRAYCODE_SIZE_BITS));
+-- else
+-- state <= gc_wait0;
+-- gc_index := std_logic_vector(to_unsigned(to_integer(unsigned(gc_index) + 1),GRAYCODE_SIZE_BITS));
+-- i_int <= gc_index;
+-- end if;
+-- when gc_wait0 =>
+-- if (wait0 < WAIT0_COUNT) then
+-- state <= gc_wait0;
+-- wait0 := wait0 + 1;
+-- i_btn <= '0';
+-- else
+-- state <= gc_send;
+-- wait0 := 0;
+-- reset_db <= '1';
+-- end if;
+-- when lfsr_enable =>
+-- state <= lfsr_disable;
+-- enable_lfsr <= '1';
+-- reset_db <= '0';
+-- when lfsr_disable =>
+-- state <= lfsr_send;
+-- enable_lfsr <= '0';
+-- when lfsr_send =>
+-- if (index = LFSR_SIZE-1) then
+-- state <= lfsr_increment;
+-- index := 0;
+-- else
+-- state <= lfsr_send;
+-- i_btn <= o_lfsr(index);
+-- index := index + 1;
+-- end if;
+-- when lfsr_increment =>
+-- if (o_lfsr = std_logic_vector(to_unsigned(0,LFSR_SIZE_BITS))) then
+-- state <= stop;
+-- else
+-- state <= lfsr_wait0;
+-- end if;
+-- when lfsr_wait0 =>
+-- if (wait0 = WAIT0_COUNT-1) then
+-- state <= lfsr_enable;
+-- wait0 := 0;
+-- reset_db <= '1';
+-- else
+-- state <= lfsr_wait0;
+-- wait0 := wait0 + 1;
+-- i_btn <= '0';
+-- end if;
+-- when stop =>
+-- REPORT "END" SEVERITY NOTE;
+-- simulation_finish <= '1';
+-- state <= stop;
+-- end case;
+-- end if;
+-- end process;
+
+END;
diff --git a/vhdl_primitive/tb_delayed_circuit.vhd b/vhdl_primitive/tb_delayed_circuit.vhd
new file mode 100755
index 0000000..850dc6c
--- /dev/null
+++ b/vhdl_primitive/tb_delayed_circuit.vhd
@@ -0,0 +1,104 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:06:40 12/18/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_delayed_circuit.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: delayed_circuit
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_delayed_circuit IS
+END tb_delayed_circuit;
+
+ARCHITECTURE behavior OF tb_delayed_circuit IS
+
+COMPONENT delayed_circuit
+PORT(
+i_clock : IN std_logic;
+i_input : IN std_logic;
+o_output : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_input : std_logic := '0';
+
+--Outputs
+signal o_output : std_logic;
+
+signal clock : std_logic;
+constant i_clock_period : time := 20 ns;
+
+BEGIN
+
+uut: delayed_circuit PORT MAP (
+i_clock => i_clock,
+i_input => i_input,
+o_output => o_output
+);
+
+-- Clock process definitions
+i_clock_process : process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc : process
+ variable v1 : std_logic_vector(7 downto 0) := "00000001";
+begin
+wait for i_clock_period*1;
+-- insert stimulus here
+--l0 : for i in 0 to 3 loop
+-- l1 : for j in 0 to 7 loop
+-- i_input <= v1(j); wait for i_clock_period*1;
+-- end loop l1;
+-- i_input <= not (v1(0) xor v1(1) xor v1(2) xor v1(3) xor v1(4) xor v1(5) xor v1(6) xor v1(7)); wait for i_clock_period*1;
+-- i_input <= (v1(0) xor v1(1) xor v1(2) xor v1(3) xor v1(4) xor v1(5) xor v1(6) xor v1(7)); wait for i_clock_period*1;
+--end loop l0;
+
+i_input <= '1'; wait for 1 ns;
+i_input <= '0'; wait for 1 ns;
+wait for 256 ns;
+i_input <= '1'; wait for 1 ns;
+i_input <= '0'; wait for 1 ns;
+i_input <= '1'; wait for 1 ns;
+i_input <= '0'; wait for 1 ns;
+i_input <= '1'; wait for 1 ns;
+i_input <= '1'; wait for 1 ns;
+
+
+report "done" severity failure;
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_edge_clock.vhd b/vhdl_primitive/tb_edge_clock.vhd
new file mode 100755
index 0000000..41997fe
--- /dev/null
+++ b/vhdl_primitive/tb_edge_clock.vhd
@@ -0,0 +1,108 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:55:38 07/03/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_edge_clock.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: edge_clock
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_edge_clock IS
+END tb_edge_clock;
+
+ARCHITECTURE behavior OF tb_edge_clock IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT edge_clock
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+i_e1 : IN std_logic;
+i_e2 : IN std_logic;
+o_count : OUT unsigned(31 downto 0)
+);
+END COMPONENT;
+
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+signal i_e1 : std_logic := '0';
+signal i_e2 : std_logic := '0';
+
+--Outputs
+signal o_count : unsigned(31 downto 0);
+
+-- Clock period definitions
+constant i_clock_period : time := 10 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: edge_clock PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+i_e1 => i_e1,
+i_e2 => i_e2,
+o_count => o_count
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+i_reset <= '1';
+wait for 100 ns;
+i_reset <= '0';
+wait for i_clock_period*10;
+
+-- insert stimulus here
+i_e1 <= '1';
+wait for i_clock_period*8.7;
+i_e1 <= '0';
+wait for i_clock_period*4.3;
+i_e2 <= '1';
+wait for i_clock_period*5.1;
+i_e2 <= '0';
+wait for i_clock_period*6.5;
+report "done" severity failure;
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_ex_4_5.vhd b/vhdl_primitive/tb_ex_4_5.vhd
new file mode 100644
index 0000000..8c963ba
--- /dev/null
+++ b/vhdl_primitive/tb_ex_4_5.vhd
@@ -0,0 +1,125 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/ex_4_5.sch - Thu Aug 10 15:44:05 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY ex_4_5_ex_4_5_sch_tb IS
+END ex_4_5_ex_4_5_sch_tb;
+ARCHITECTURE behavioral OF ex_4_5_ex_4_5_sch_tb IS
+
+COMPONENT ex_4_5
+PORT( A1 : IN STD_LOGIC;
+B1 : IN STD_LOGIC;
+A0 : IN STD_LOGIC;
+B0 : IN STD_LOGIC;
+A3 : IN STD_LOGIC;
+B3 : IN STD_LOGIC;
+A2 : IN STD_LOGIC;
+B2 : IN STD_LOGIC;
+A_eq_B : OUT STD_LOGIC;
+A_gt_B : OUT STD_LOGIC;
+A_lt_B : OUT STD_LOGIC);
+END COMPONENT;
+
+SIGNAL A1 : STD_LOGIC;
+SIGNAL B1 : STD_LOGIC;
+SIGNAL A0 : STD_LOGIC;
+SIGNAL B0 : STD_LOGIC;
+SIGNAL A3 : STD_LOGIC;
+SIGNAL B3 : STD_LOGIC;
+SIGNAL A2 : STD_LOGIC;
+SIGNAL B2 : STD_LOGIC;
+SIGNAL A_eq_B : STD_LOGIC;
+SIGNAL A_gt_B : STD_LOGIC;
+SIGNAL A_lt_B : STD_LOGIC;
+
+signal a,b : std_logic_vector (3 downto 0);
+
+BEGIN
+
+a3 <= a (3);
+a2 <= a (2);
+a1 <= a (1);
+a0 <= a (0);
+
+b3 <= b (3);
+b2 <= b (2);
+b1 <= b (1);
+b0 <= b (0);
+
+UUT: ex_4_5 PORT MAP(
+A1 => A1,
+B1 => B1,
+A0 => A0,
+B0 => B0,
+A3 => A3,
+B3 => B3,
+A2 => A2,
+B2 => B2,
+A_eq_B => A_eq_B,
+A_gt_B => A_gt_B,
+A_lt_B => A_lt_B
+);
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+
+l0 : for i in 0 to 15 loop
+
+a <= std_logic_vector (to_unsigned (i, 4)); b <= "0000";
+wait for 10 ns;
+a <= std_logic_vector (to_unsigned (i, 4)); b <= "0001";
+wait for 10 ns;
+a <= std_logic_vector (to_unsigned (i, 4)); b <= "0010";
+wait for 10 ns;
+a <= std_logic_vector (to_unsigned (i, 4)); b <= "0011";
+wait for 10 ns;
+a <= std_logic_vector (to_unsigned (i, 4)); b <= "0100";
+wait for 10 ns;
+a <= std_logic_vector (to_unsigned (i, 4)); b <= "0101";
+wait for 10 ns;
+a <= std_logic_vector (to_unsigned (i, 4)); b <= "0110";
+wait for 10 ns;
+a <= std_logic_vector (to_unsigned (i, 4)); b <= "0111";
+wait for 10 ns;
+a <= std_logic_vector (to_unsigned (i, 4)); b <= "1000";
+wait for 10 ns;
+a <= std_logic_vector (to_unsigned (i, 4)); b <= "1001";
+wait for 10 ns;
+a <= std_logic_vector (to_unsigned (i, 4)); b <= "1010";
+wait for 10 ns;
+a <= std_logic_vector (to_unsigned (i, 4)); b <= "1011";
+wait for 10 ns;
+a <= std_logic_vector (to_unsigned (i, 4)); b <= "1100";
+wait for 10 ns;
+a <= std_logic_vector (to_unsigned (i, 4)); b <= "1101";
+wait for 10 ns;
+a <= std_logic_vector (to_unsigned (i, 4)); b <= "1110";
+wait for 10 ns;
+a <= std_logic_vector (to_unsigned (i, 4)); b <= "1111";
+wait for 10 ns;
+
+end loop l0;
+
+
+report "tb done" severity failure;
+WAIT; -- will wait forever
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_ff3_synchronizer.vhd b/vhdl_primitive/tb_ff3_synchronizer.vhd
new file mode 100644
index 0000000..ae7b9c4
--- /dev/null
+++ b/vhdl_primitive/tb_ff3_synchronizer.vhd
@@ -0,0 +1,94 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:53:38 07/09/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_ff3_synchronizer.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: ff3_synchronizer
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ff3_synchronizer IS
+END tb_ff3_synchronizer;
+
+ARCHITECTURE behavior OF tb_ff3_synchronizer IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT ff3_synchronizer
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+i_input : IN std_logic;
+o_pulse : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+signal i_input : std_logic := '0';
+
+--Outputs
+signal o_pulse : std_logic;
+
+-- Clock period definitions
+constant i_clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: ff3_synchronizer PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+i_input => i_input,
+o_pulse => o_pulse
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+i_reset <= '1';
+wait for 100 ns;
+i_reset <= '0';
+wait for i_clock_period*30+0.1*i_clock_period;
+
+-- insert stimulus here
+i_input <= '1','0' after 0.41*i_clock_period;
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_ff_d_pe.vhd b/vhdl_primitive/tb_ff_d_pe.vhd
new file mode 100644
index 0000000..d73c509
--- /dev/null
+++ b/vhdl_primitive/tb_ff_d_pe.vhd
@@ -0,0 +1,236 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:04:09 06/29/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_ff_d_pe.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: FF_D_POSITIVE_EDGE
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ff_d_pe IS
+END tb_ff_d_pe;
+
+ARCHITECTURE behavior OF tb_ff_d_pe IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT FF_D_POSITIVE_EDGE
+PORT(
+S : IN std_logic;
+R : IN std_logic;
+C : IN std_logic;
+D : IN std_logic;
+Q1 : INOUT std_logic;
+Q2 : INOUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal S : std_logic := '0';
+signal R : std_logic := '0';
+signal C : std_logic := '0';
+signal D : std_logic := '0';
+
+--BiDirs
+signal Q1 : std_logic;
+signal Q2 : std_logic;
+
+signal clock : std_logic;
+constant clock_period : time := 10 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: FF_D_POSITIVE_EDGE PORT MAP (
+S => S,
+R => R,
+C => clock,
+D => D,
+Q1 => Q1,
+Q2 => Q2
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+
+-- insert stimulus here
+
+wait for clock_period*10;
+
+S <= '0';
+R <= '0';
+wait for 100 ns;
+d <= '1';
+wait for clock_period;
+d <= '0';
+wait for clock_period;
+wait for 444 ps;
+d <= '1';
+wait for clock_period*3;
+d <= '0';
+wait for clock_period;
+wait for 444 ps;
+d <= '1';
+wait for clock_period*3+clock_period/2+444 ps;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for clock_period*3+clock_period+444 ps;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for 1 ns;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for 6 ns;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for clock_period;
+d <= '0';
+
+-- XXX q1 on '1',q2 have '1' on RE clock and d=0
+S <= '0';
+R <= '1';
+wait for 100 ns;
+d <= '1';
+wait for clock_period;
+d <= '0';
+wait for clock_period;
+wait for 444 ps;
+d <= '1';
+wait for clock_period*3;
+d <= '0';
+wait for clock_period;
+wait for 444 ps;
+d <= '1';
+wait for clock_period*3+clock_period/2+444 ps;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for clock_period*3+clock_period+444 ps;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for 1 ns;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for 6 ns;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for clock_period;
+d <= '0';
+
+S <= '1';
+R <= '0';
+wait for 100 ns;
+d <= '1';
+wait for clock_period;
+d <= '0';
+wait for clock_period;
+wait for 444 ps;
+d <= '1';
+wait for clock_period*3;
+d <= '0';
+wait for clock_period;
+wait for 444 ps;
+d <= '1';
+wait for clock_period*3+clock_period/2+444 ps;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for clock_period*3+clock_period+444 ps;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for 1 ns;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for 6 ns;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for clock_period;
+d <= '0';
+
+-- XXX look ok, q1 on RE clock and D,q2 is q1 bar
+S <= '1';
+R <= '1';
+wait for 100 ns;
+d <= '1';
+wait for clock_period;
+d <= '0';
+wait for clock_period;
+wait for 444 ps;
+d <= '1';
+wait for clock_period*3;
+d <= '0';
+wait for clock_period;
+wait for 444 ps;
+d <= '1';
+wait for clock_period*3+clock_period/2+444 ps;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for clock_period*3+clock_period+444 ps;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for 1 ns;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for 6 ns;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for clock_period;
+d <= '0';
+S <= '0';
+R <= '0';
+
+wait for 100 ns;
+
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_ff_det.vhd b/vhdl_primitive/tb_ff_det.vhd
new file mode 100644
index 0000000..9f8012d
--- /dev/null
+++ b/vhdl_primitive/tb_ff_det.vhd
@@ -0,0 +1,97 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:58:37 06/29/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_ff_det.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: FF_D_DUAL_EDGE_TRIGGERED
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ff_det IS
+END tb_ff_det;
+
+ARCHITECTURE behavior OF tb_ff_det IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT FF_D_DUAL_EDGE_TRIGGERED
+ PORT(
+ D : IN std_logic;
+ C : IN std_logic;
+ Q : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal D : std_logic := '0';
+ signal C : std_logic := '0';
+
+ --Outputs
+ signal Q : std_logic;
+ -- No clocks detected in port list. Replace below with
+ -- appropriate port name
+
+ constant C_period : time := 10 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+ uut: FF_D_DUAL_EDGE_TRIGGERED PORT MAP (
+ D => D,
+ C => C,
+ Q => Q
+ );
+
+ -- Clock process definitions
+ C_process :process
+ begin
+ C <= '0';
+ wait for C_period/2;
+ C <= '1';
+ wait for C_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+-- wait for 100 ns;
+
+-- wait for _period*10;
+
+ -- insert stimulus here
+wait for c_period*4.5;
+d <= '1';
+wait for c_period;
+d <= '0';
+ wait;
+ end process;
+
+END;
diff --git a/vhdl_primitive/tb_ff_jk.vhd b/vhdl_primitive/tb_ff_jk.vhd
new file mode 100755
index 0000000..356aa94
--- /dev/null
+++ b/vhdl_primitive/tb_ff_jk.vhd
@@ -0,0 +1,192 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:05:50 05/04/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_ff_jk.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: FF_JK
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ff_jk IS
+END tb_ff_jk;
+
+ARCHITECTURE behavior OF tb_ff_jk IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT FF_JK
+PORT(
+i_r : IN STD_LOGIC;
+J : IN std_logic;
+K : IN std_logic;
+C : IN std_logic;
+Q1 : INOUT std_logic;
+Q2 : INOUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_r : std_logic := '0';
+signal J : std_logic := '0';
+signal K : std_logic := '0';
+signal C : std_logic := '0';
+
+--BiDirs
+signal Q1 : std_logic := '0';
+signal Q2 : std_logic := '0';
+
+signal clock : std_logic := '0';
+constant clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: FF_JK PORT MAP (
+i_r => i_r,
+J => J,
+K => K,
+C => C,
+Q1 => Q1,
+Q2 => Q2
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+-- Stimulus process
+--stim_proc: process (clock) is
+-- type vt is array(0 to 3) of std_logic_vector(1 downto 0);
+---- variable v : vt := ("00","01","10","11"); -- bin
+-- variable v : vt := ("00","01","11","10"); -- grey
+-- variable i : integer range 0 to 3 := 0;
+--begin
+---- insert stimulus here
+--C <= '1';
+--if (rising_edge(clock)) then
+--J <= v(i)(0);
+--K <= v(i)(1);
+--if (i=3) then
+--i := 0;
+--else
+--i := i + 1;
+--end if;
+--end if;
+--end process;
+
+i_r <= '1','0' after clock_period/2;
+C <= clock;
+stim_proc: process is
+begin
+-- insert stimulus here
+J <= '1';
+K <= '1';
+wait for clock_period;
+J <= '0';
+K <= '0';
+wait for 10*clock_period;
+J <= '1';
+K <= '1';
+wait for clock_period;
+J <= '0';
+K <= '0';
+wait for 10*clock_period;
+J <= '1';
+K <= '1';
+wait for clock_period;
+J <= '0';
+K <= '0';
+wait for 10*clock_period;
+J <= '1';
+K <= '1';
+wait for clock_period;
+J <= '0';
+K <= '0';
+wait for 10*clock_period;
+J <= '1';
+K <= '1';
+wait for clock_period;
+J <= '0';
+K <= '0';
+wait for 10*clock_period;
+J <= '1';
+K <= '1';
+wait for clock_period;
+J <= '0';
+K <= '0';
+wait for 10*clock_period;
+J <= '1';
+K <= '1';
+wait for clock_period;
+J <= '0';
+K <= '0';
+wait for 10*clock_period;
+J <= '1';
+K <= '1';
+wait for clock_period;
+J <= '0';
+K <= '0';
+wait for 10*clock_period;
+J <= '1';
+K <= '1';
+wait for clock_period;
+J <= '0';
+K <= '0';
+wait for 10*clock_period;
+J <= '1';
+K <= '1';
+wait for clock_period;
+J <= '0';
+K <= '0';
+wait for 10*clock_period;
+J <= '1';
+K <= '1';
+wait for clock_period;
+J <= '0';
+K <= '0';
+wait for 10*clock_period;
+J <= '1';
+K <= '1';
+wait for clock_period;
+J <= '0';
+K <= '0';
+wait for 10*clock_period;
+J <= '1';
+K <= '1';
+wait for clock_period;
+J <= '0';
+K <= '0';
+wait for 10*clock_period;
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_fig33.vhd b/vhdl_primitive/tb_fig33.vhd
new file mode 100644
index 0000000..5db2ce9
--- /dev/null
+++ b/vhdl_primitive/tb_fig33.vhd
@@ -0,0 +1,108 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:05:22 06/04/2023
+-- Design Name: Transparent Latch
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_fig33.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: fig33
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types bit and
+-- bit_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_fig33 IS
+END tb_fig33;
+
+ARCHITECTURE behavior OF tb_fig33 IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT fig33
+PORT(
+Data : IN bit;
+Enable : IN bit;
+Q_out : OUT bit;
+Qb_out : OUT bit
+);
+END COMPONENT;
+
+--Inputs
+signal Data : bit := '0';
+signal Enable : bit := '0';
+
+--Outputs
+signal Q_out : bit;
+signal Qb_out : bit;
+
+signal clock : bit := '0';
+constant clock_period : time := 20 ns;
+
+BEGIN
+
+process_clock : process is
+begin
+ clock <= '0';
+ wait for clock_period/2;
+ clock <= '1';
+ wait for clock_period/2;
+end process process_clock;
+
+-- Instantiate the Unit Under Test (UUT)
+uut: fig33 PORT MAP (
+Data => Data,
+Enable => Enable,
+Q_out => Q_out,
+Qb_out => Qb_out
+);
+
+Data <= '1',
+'0' after 8 ns,
+'1' after 12 ns,
+'0' after 14 ns,
+'1' after 16 ns,
+'0' after 24 ns,
+'1' after 26 ns,
+'0' after 28 ns,
+'1' after 34 ns,
+'0' after 38 ns,
+'1' after 42 ns;
+
+Enable <= '0',
+'1' after 10 ns,
+'0' after 20 ns,
+'1' after 30 ns,
+'0' after 40 ns,
+'1' after 50 ns;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+wait for 100 ns;
+-- insert stimulus here
+
+report "done tb" severity failure;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_fig35.vhd b/vhdl_primitive/tb_fig35.vhd
new file mode 100644
index 0000000..5360117
--- /dev/null
+++ b/vhdl_primitive/tb_fig35.vhd
@@ -0,0 +1,99 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:47:33 06/04/2023
+-- Design Name: Master-slave neg-edge D FF
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_fig35.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: fig35
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types bit and
+-- bit_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_fig35 IS
+END tb_fig35;
+
+ARCHITECTURE behavior OF tb_fig35 IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT fig35
+PORT(
+Data : IN bit;
+clock : IN bit;
+Q : OUT bit;
+Qb : OUT bit
+);
+END COMPONENT;
+
+--Inputs
+signal Data : bit := '0';
+signal clock : bit := '0';
+
+--Outputs
+signal Q : bit;
+signal Qb : bit;
+
+-- Clock period definitions
+constant clock_period : time := 10 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: fig35 PORT MAP (
+Data => Data,
+clock => clock,
+Q => Q,
+Qb => Qb
+);
+
+Data <= '0',
+'1' after 12.5 ns,
+'0' after 17.5 ns,
+'1' after 22.5 ns,
+'0' after 27.5 ns,
+'1' after 42.5 ns,
+'0' after 52.5 ns;
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+wait for 100 ns;
+
+-- insert stimulus here
+
+report "done tb" severity failure;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_fig37.vhd b/vhdl_primitive/tb_fig37.vhd
new file mode 100644
index 0000000..eafcf8e
--- /dev/null
+++ b/vhdl_primitive/tb_fig37.vhd
@@ -0,0 +1,101 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:09:18 06/04/2023
+-- Design Name: CMOS MS DFF
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_fig37.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: fig37
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_fig37 IS
+END tb_fig37;
+
+ARCHITECTURE behavior OF tb_fig37 IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT fig37
+PORT(
+Data : IN std_logic;
+Clear_bar : IN std_logic;
+clock : IN std_logic;
+Q,Qb : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal Data : std_logic := '0';
+signal Clear_bar : std_logic := '0';
+signal clock : std_logic := '0';
+
+--Outputs
+signal Q : std_logic;
+signal Qb : std_logic;
+
+-- Clock period definitions
+constant clock_period : time := 10 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: fig37 PORT MAP (
+Data => Data,
+Clear_bar => Clear_bar,
+clock => clock,
+Qb => Qb,
+Q => Q
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+Data <= '0',
+'1' after 12.5 ns,
+'0' after 17.5 ns,
+'1' after 22.5 ns,
+'0' after 27.5 ns,
+'1' after 42.5 ns,
+'0' after 52.5 ns;
+
+Clear_bar <= '1', '0' after 3 ns, '1' after 4 ns;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+wait for 100 ns;
+-- insert stimulus here
+report "done tb" severity failure;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_fig_3_22.vhd b/vhdl_primitive/tb_fig_3_22.vhd
new file mode 100644
index 0000000..75420fc
--- /dev/null
+++ b/vhdl_primitive/tb_fig_3_22.vhd
@@ -0,0 +1,113 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:09:27 06*05*2023
+-- Design Name:
+-- Module Name: *home*user*workspace*vhdl_projects*vhdl_primitive*tb_fig_3_22.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: fig_3_22
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I*O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_fig_3_22 IS
+END tb_fig_3_22;
+
+ARCHITECTURE behavior OF tb_fig_3_22 IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT fig_3_22
+PORT(
+clk : IN std_logic;
+reset : IN std_logic;
+Bin : IN std_logic;
+Bout : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal clk : std_logic := '0';
+signal reset : std_logic := '0';
+signal Bin : std_logic := '0';
+
+--Outputs
+signal Bout : std_logic;
+
+-- Clock period definitions
+constant clk_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: fig_3_22 PORT MAP (
+clk => clk,
+reset => reset,
+Bin => Bin,
+Bout => Bout
+);
+
+-- Clock process definitions
+clk_process :process
+begin
+clk <= '0';
+wait for clk_period/2;
+clk <= '1';
+wait for clk_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+reset <= '1';
+wait for 100 ns;
+reset <= '0';
+-- insert stimulus here
+wait for clk_period*0.5;
+Bin <= '1'; wait for clk_period;
+Bin <= '0'; wait for clk_period;
+Bin <= '0'; wait for clk_period;
+Bin <= '0'; wait for clk_period;
+Bin <= '0';
+wait for 8*clk_period;
+
+Bin <= '1'; wait for clk_period;
+Bin <= '0'; wait for clk_period;
+Bin <= '0'; wait for clk_period;
+Bin <= '0'; wait for clk_period;
+Bin <= '0';
+wait for 8*clk_period;
+
+Bin <= '1'; wait for clk_period;
+Bin <= '0'; wait for clk_period;
+Bin <= '0'; wait for clk_period;
+Bin <= '0'; wait for clk_period;
+Bin <= '0';
+wait for 8*clk_period;
+
+report "done tb" severity failure;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_fig_3_29.vhd b/vhdl_primitive/tb_fig_3_29.vhd
new file mode 100644
index 0000000..4b63d6b
--- /dev/null
+++ b/vhdl_primitive/tb_fig_3_29.vhd
@@ -0,0 +1,110 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:39:10 06/05/2023
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_fig_3_29.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: fig_3_29
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_fig_3_29 IS
+END tb_fig_3_29;
+
+ARCHITECTURE behavior OF tb_fig_3_29 IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT fig_3_29
+PORT(
+Bin : IN std_logic;
+clk : IN std_logic;
+reset : IN std_logic;
+Bout : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal Bin : std_logic := '0';
+signal reset : std_logic := '0';
+
+--Outputs
+signal Bout : std_logic;
+
+signal clk1x : std_logic := '0';
+signal clk2x : std_logic := '0';
+-- Clock period definitions
+constant clk_period1x : time := 20 ns;
+constant clk_period2x : time := 10 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: fig_3_29 PORT MAP (
+Bin => Bin,
+clk => clk2x,
+reset => reset,
+Bout => Bout
+);
+
+-- Clock process definitions
+clk_process2x :process
+begin
+clk2x <= '0';
+wait for clk_period2x/2;
+clk2x <= '1';
+wait for clk_period2x/2;
+end process;
+
+clk_process1x :process
+begin
+clk1x <= '0';
+wait for clk_period1x/2;
+clk1x <= '1';
+wait for clk_period1x/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+reset <= '1';
+wait for 100 ns;
+reset <= '0';
+-- insert stimulus here
+--wait for clk_period1x*1.0;
+Bin <= '0'; wait for clk_period1x;
+Bin <= '1'; wait for clk_period1x;
+Bin <= '1'; wait for clk_period1x;
+Bin <= '1'; wait for clk_period1x;
+Bin <= '0'; wait for clk_period1x;
+Bin <= '0'; wait for clk_period1x;
+Bin <= '1'; wait for clk_period1x;
+Bin <= '0'; wait for clk_period1x;
+report "tb done" severity failure;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_fig_3_34.vhd b/vhdl_primitive/tb_fig_3_34.vhd
new file mode 100644
index 0000000..872dc3f
--- /dev/null
+++ b/vhdl_primitive/tb_fig_3_34.vhd
@@ -0,0 +1,110 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:16:36 06/06/2023
+-- Design Name: Mo-type NRZ-to-Manchester encoder
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_fig_3_34.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: fig_3_34
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_fig_3_34 IS
+END tb_fig_3_34;
+
+ARCHITECTURE behavior OF tb_fig_3_34 IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT fig_3_34
+PORT(
+clk : IN std_logic;
+reset : IN std_logic;
+Bin : IN std_logic;
+Bout : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal reset : std_logic := '0';
+signal Bin : std_logic := '0';
+
+--Outputs
+signal Bout : std_logic;
+
+signal clk1x : std_logic := '0';
+signal clk2x : std_logic := '0';
+-- Clock period definitions
+constant clk_period1x : time := 20 ns;
+constant clk_period2x : time := 10 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: fig_3_34 PORT MAP (
+clk => clk2x,
+reset => reset,
+Bin => Bin,
+Bout => Bout
+);
+
+-- Clock process definitions
+clk_process1x :process
+begin
+clk1x <= '0';
+wait for clk_period1x/2;
+clk1x <= '1';
+wait for clk_period1x/2;
+end process;
+
+clk_process2x :process
+begin
+clk2x <= '1';
+wait for clk_period2x/2;
+clk2x <= '0';
+wait for clk_period2x/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+reset <= '1';
+wait for 100 ns;
+reset <= '0';
+-- insert stimulus here
+--wait for clk_period1x/1.7;
+Bin <= '0'; wait for clk_period1x;
+Bin <= '1'; wait for clk_period1x;
+Bin <= '1'; wait for clk_period1x;
+Bin <= '1'; wait for clk_period1x;
+Bin <= '0'; wait for clk_period1x;
+Bin <= '0'; wait for clk_period1x;
+Bin <= '1'; wait for clk_period1x;
+Bin <= '0'; wait for clk_period1x;
+report "tb done" severity failure;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_fig_4_10.vhd b/vhdl_primitive/tb_fig_4_10.vhd
new file mode 100644
index 0000000..1b26e79
--- /dev/null
+++ b/vhdl_primitive/tb_fig_4_10.vhd
@@ -0,0 +1,101 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/fig_4_10.sch - Thu Aug 10 14:25:15 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY fig_4_10_fig_4_10_sch_tb IS
+END fig_4_10_fig_4_10_sch_tb;
+ARCHITECTURE behavioral OF fig_4_10_fig_4_10_sch_tb IS
+
+COMPONENT fig_4_10
+PORT( A1 : IN STD_LOGIC;
+B1 : IN STD_LOGIC;
+A0 : IN STD_LOGIC;
+B0 : IN STD_LOGIC;
+A_lt_B : OUT STD_LOGIC;
+A_eq_B : OUT STD_LOGIC;
+A_gt_B : OUT STD_LOGIC);
+END COMPONENT;
+
+SIGNAL A1 : STD_LOGIC;
+SIGNAL B1 : STD_LOGIC;
+SIGNAL A0 : STD_LOGIC;
+SIGNAL B0 : STD_LOGIC;
+SIGNAL A_lt_B : STD_LOGIC;
+SIGNAL A_eq_B : STD_LOGIC;
+SIGNAL A_gt_B : STD_LOGIC;
+
+signal a,b : std_logic_vector (1 downto 0);
+
+BEGIN
+
+A1 <= a (1);
+A0 <= a (0);
+B1 <= b (1);
+B0 <= b (0);
+
+UUT: fig_4_10 PORT MAP(
+A1 => A1,
+B1 => B1,
+A0 => A0,
+B0 => B0,
+A_lt_B => A_lt_B,
+A_eq_B => A_eq_B,
+A_gt_B => A_gt_B
+);
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+a <= "00"; b <= "00";
+wait for 10 ns;
+a <= "00"; b <= "01";
+wait for 10 ns;
+a <= "00"; b <= "10";
+wait for 10 ns;
+a <= "00"; b <= "11";
+wait for 10 ns;
+a <= "01"; b <= "00";
+wait for 10 ns;
+a <= "01"; b <= "01";
+wait for 10 ns;
+a <= "01"; b <= "10";
+wait for 10 ns;
+a <= "01"; b <= "11";
+wait for 10 ns;
+a <= "10"; b <= "00";
+wait for 10 ns;
+a <= "10"; b <= "01";
+wait for 10 ns;
+a <= "10"; b <= "10";
+wait for 10 ns;
+a <= "10"; b <= "11";
+wait for 10 ns;
+a <= "11"; b <= "00";
+wait for 10 ns;
+a <= "11"; b <= "01";
+wait for 10 ns;
+a <= "11"; b <= "10";
+wait for 10 ns;
+a <= "11"; b <= "11";
+wait for 10 ns;
+report "tb done" severity failure;
+WAIT; -- will wait forever
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_fig_4_5.vhd b/vhdl_primitive/tb_fig_4_5.vhd
new file mode 100644
index 0000000..686517e
--- /dev/null
+++ b/vhdl_primitive/tb_fig_4_5.vhd
@@ -0,0 +1,215 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:42:59 06/06/2023
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_fig_4_5.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: fig_4_5
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_fig_4_5 IS
+END tb_fig_4_5;
+
+ARCHITECTURE behavior OF tb_fig_4_5 IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT fig_4_5
+PORT(
+x_in1 : IN std_logic;
+x_in2 : IN std_logic;
+x_in3 : IN std_logic;
+x_in4 : IN std_logic;
+x_in5 : IN std_logic;
+y_out : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal x_in1 : std_logic := '0';
+signal x_in2 : std_logic := '0';
+signal x_in3 : std_logic := '0';
+signal x_in4 : std_logic := '0';
+signal x_in5 : std_logic := '0';
+
+--Outputs
+signal y_out : std_logic;
+
+signal clock : std_logic := '0';
+constant clock_period : time := 10 ns;
+
+BEGIN
+
+cp : process is
+begin
+clock <= not clock; wait for clock_period;
+end process cp;
+
+-- Instantiate the Unit Under Test (UUT)
+uut: fig_4_5 PORT MAP (
+x_in1 => x_in1,
+x_in2 => x_in2,
+x_in3 => x_in3,
+x_in4 => x_in4,
+x_in5 => x_in5,
+y_out => y_out
+);
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+wait for 100 ns;
+-- insert stimulus here
+wait for clock_period*2;
+x_in1 <= '1';
+x_in2 <= '1';
+x_in3 <= '1';
+x_in4 <= '1';
+x_in5 <= '1';
+wait for clock_period;
+x_in1 <= '0';
+x_in2 <= '1';
+x_in3 <= '1';
+x_in4 <= '1';
+x_in5 <= '1';
+wait for clock_period;
+x_in1 <= '1';
+x_in2 <= '0';
+x_in3 <= '1';
+x_in4 <= '1';
+x_in5 <= '1';
+wait for clock_period;
+x_in1 <= '1';
+x_in2 <= '1';
+x_in3 <= '0';
+x_in4 <= '1';
+x_in5 <= '1';
+wait for clock_period;
+x_in1 <= '1';
+x_in2 <= '1';
+x_in3 <= '1';
+x_in4 <= '0';
+x_in5 <= '1';
+wait for clock_period;
+x_in1 <= '1';
+x_in2 <= '1';
+x_in3 <= '1';
+x_in4 <= '1';
+x_in5 <= '0';
+wait for clock_period;
+x_in1 <= '1';
+x_in2 <= '1';
+x_in3 <= '1';
+x_in4 <= '1';
+x_in5 <= '1';
+wait for clock_period;
+x_in1 <= '0';
+x_in2 <= '0';
+x_in3 <= '0';
+x_in4 <= '0';
+x_in5 <= '0';
+wait for clock_period;
+x_in1 <= '1';
+x_in2 <= '0';
+x_in3 <= '0';
+x_in4 <= '0';
+x_in5 <= '0';
+wait for clock_period;
+x_in1 <= '0';
+x_in2 <= '1';
+x_in3 <= '0';
+x_in4 <= '0';
+x_in5 <= '0';
+wait for clock_period;
+x_in1 <= '0';
+x_in2 <= '0';
+x_in3 <= '1';
+x_in4 <= '0';
+x_in5 <= '0';
+wait for clock_period;
+x_in1 <= '0';
+x_in2 <= '0';
+x_in3 <= '0';
+x_in4 <= '1';
+x_in5 <= '0';
+wait for clock_period;
+x_in1 <= '0';
+x_in2 <= '0';
+x_in3 <= '0';
+x_in4 <= '0';
+x_in5 <= '1';
+wait for clock_period;
+x_in1 <= '0';
+x_in2 <= '0';
+x_in3 <= '0';
+x_in4 <= '0';
+x_in5 <= '0';
+wait for clock_period;
+
+x_in1 <= '1';
+x_in2 <= '0';
+x_in3 <= '1';
+x_in4 <= '0';
+x_in5 <= '0';
+wait for clock_period;
+x_in1 <= '1';
+x_in2 <= '1';
+x_in3 <= '1';
+x_in4 <= '1';
+x_in5 <= '0';
+wait for clock_period;
+x_in1 <= '1';
+x_in2 <= '0';
+x_in3 <= '1';
+x_in4 <= '1';
+x_in5 <= '1';
+wait for clock_period;
+
+x_in1 <= '0';
+x_in2 <= '1';
+x_in3 <= '0';
+x_in4 <= '1';
+x_in5 <= '1';
+wait for clock_period;
+x_in1 <= '0';
+x_in2 <= '0';
+x_in3 <= '0';
+x_in4 <= '0';
+x_in5 <= '1';
+wait for clock_period;
+x_in1 <= '0';
+x_in2 <= '1';
+x_in3 <= '0';
+x_in4 <= '0';
+x_in5 <= '0';
+wait for clock_period;
+
+report "done tb" severity failure;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_fig_5_11.vhd b/vhdl_primitive/tb_fig_5_11.vhd
new file mode 100644
index 0000000..af9a787
--- /dev/null
+++ b/vhdl_primitive/tb_fig_5_11.vhd
@@ -0,0 +1,106 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/fig_5_11.sch - Fri Aug 11 18:47:05 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY fig_5_11_fig_5_11_sch_tb IS
+END fig_5_11_fig_5_11_sch_tb;
+ARCHITECTURE behavioral OF fig_5_11_fig_5_11_sch_tb IS
+
+COMPONENT fig_5_11
+PORT( Data5 : IN STD_LOGIC;
+Data4 : IN STD_LOGIC;
+Data6 : IN STD_LOGIC;
+Data3 : IN STD_LOGIC;
+Data2 : IN STD_LOGIC;
+Data1 : IN STD_LOGIC;
+Data7 : IN STD_LOGIC;
+Code0 : OUT STD_LOGIC;
+Code1 : OUT STD_LOGIC;
+Code2 : OUT STD_LOGIC);
+END COMPONENT;
+
+SIGNAL Data5 : STD_LOGIC;
+SIGNAL Data4 : STD_LOGIC;
+SIGNAL Data6 : STD_LOGIC;
+SIGNAL Data3 : STD_LOGIC;
+SIGNAL Data2 : STD_LOGIC;
+SIGNAL Data1 : STD_LOGIC;
+SIGNAL Data7 : STD_LOGIC;
+SIGNAL Code0 : STD_LOGIC;
+SIGNAL Code1 : STD_LOGIC;
+SIGNAL Code2 : STD_LOGIC;
+
+signal Data : std_logic_vector (7 downto 1);
+signal Code : std_logic_vector (2 downto 0);
+
+BEGIN
+
+Data7 <= Data (7);
+Data6 <= Data (6);
+Data5 <= Data (5);
+Data4 <= Data (4);
+Data3 <= Data (3);
+Data2 <= Data (2);
+Data1 <= Data (1);
+
+Code (2) <= Code2;
+Code (1) <= Code1;
+Code (0) <= Code0;
+
+UUT: fig_5_11 PORT MAP(
+Data5 => Data5,
+Data4 => Data4,
+Data6 => Data6,
+Data3 => Data3,
+Data2 => Data2,
+Data1 => Data1,
+Data7 => Data7,
+Code0 => Code0,
+Code1 => Code1,
+Code2 => Code2
+);
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+
+Data <= "0000000"; wait for 10 ns;
+Data <= "1000000"; wait for 10 ns;
+Data <= "0100000"; wait for 10 ns;
+Data <= "0010000"; wait for 10 ns;
+Data <= "0001000"; wait for 10 ns;
+Data <= "0000100"; wait for 10 ns;
+Data <= "0000010"; wait for 10 ns;
+Data <= "0000001"; wait for 10 ns;
+Data <= "0000000"; wait for 10 ns;
+Data <= "0000001"; wait for 10 ns;
+Data <= "0000010"; wait for 10 ns;
+Data <= "0000100"; wait for 10 ns;
+Data <= "0001000"; wait for 10 ns;
+Data <= "0010000"; wait for 10 ns;
+Data <= "0100000"; wait for 10 ns;
+Data <= "1000000"; wait for 10 ns;
+Data <= "0000000"; wait for 10 ns;
+
+report "tb done" severity failure;
+
+WAIT; -- will wait forever
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_fig_5_12.vhd b/vhdl_primitive/tb_fig_5_12.vhd
new file mode 100644
index 0000000..9421f60
--- /dev/null
+++ b/vhdl_primitive/tb_fig_5_12.vhd
@@ -0,0 +1,111 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/fig_5_12.sch - Fri Aug 11 20:17:21 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY fig_5_12_fig_5_12_sch_tb IS
+END fig_5_12_fig_5_12_sch_tb;
+ARCHITECTURE behavioral OF fig_5_12_fig_5_12_sch_tb IS
+
+COMPONENT fig_5_12
+PORT( Code2 : OUT STD_LOGIC;
+Data0 : IN STD_LOGIC;
+Data7 : IN STD_LOGIC;
+Data5 : IN STD_LOGIC;
+Data6 : IN STD_LOGIC;
+Data2 : IN STD_LOGIC;
+Data1 : IN STD_LOGIC;
+Data3 : IN STD_LOGIC;
+Data4 : IN STD_LOGIC;
+Code0 : OUT STD_LOGIC;
+Code1 : OUT STD_LOGIC;
+data_valid : OUT STD_LOGIC);
+END COMPONENT;
+
+SIGNAL Code2 : STD_LOGIC;
+SIGNAL Data0 : STD_LOGIC;
+SIGNAL Data7 : STD_LOGIC;
+SIGNAL Data5 : STD_LOGIC;
+SIGNAL Data6 : STD_LOGIC;
+SIGNAL Data2 : STD_LOGIC;
+SIGNAL Data1 : STD_LOGIC;
+SIGNAL Data3 : STD_LOGIC;
+SIGNAL Data4 : STD_LOGIC;
+SIGNAL Code0 : STD_LOGIC;
+SIGNAL Code1 : STD_LOGIC;
+SIGNAL data_valid : STD_LOGIC;
+
+signal Data : std_logic_vector (7 downto 0);
+signal Code : std_logic_vector (2 downto 0);
+
+BEGIN
+
+Data7 <= Data (7);
+Data6 <= Data (6);
+Data5 <= Data (5);
+Data4 <= Data (4);
+Data3 <= Data (3);
+Data2 <= Data (2);
+Data1 <= Data (1);
+Data0 <= Data (0);
+Code (2) <= Code2;
+Code (1) <= Code1;
+Code (0) <= Code0;
+
+UUT: fig_5_12 PORT MAP(
+Code2 => Code2,
+Data0 => Data0,
+Data7 => Data7,
+Data5 => Data5,
+Data6 => Data6,
+Data2 => Data2,
+Data1 => Data1,
+Data3 => Data3,
+Data4 => Data4,
+Code0 => Code0,
+Code1 => Code1,
+data_valid => data_valid
+);
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+Data <= "00000000"; wait for 10 ns;
+Data <= "00000001"; wait for 10 ns;
+Data <= "00000010"; wait for 10 ns;
+Data <= "00000100"; wait for 10 ns;
+Data <= "00001000"; wait for 10 ns;
+Data <= "00010000"; wait for 10 ns;
+Data <= "00100000"; wait for 10 ns;
+Data <= "01000000"; wait for 10 ns;
+Data <= "10000000"; wait for 10 ns;
+Data <= "00000000"; wait for 10 ns;
+Data <= "00000101"; wait for 10 ns;
+Data <= "00001010"; wait for 10 ns;
+Data <= "00010100"; wait for 10 ns;
+Data <= "00101000"; wait for 10 ns;
+Data <= "01010000"; wait for 10 ns;
+Data <= "10100000"; wait for 10 ns;
+Data <= "01000001"; wait for 10 ns;
+Data <= "10100000"; wait for 10 ns;
+Data <= "00000000"; wait for 10 ns;
+report "tb done" severity failure;
+WAIT; -- will wait forever
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_fig_5_13.vhd b/vhdl_primitive/tb_fig_5_13.vhd
new file mode 100644
index 0000000..d6e47cc
--- /dev/null
+++ b/vhdl_primitive/tb_fig_5_13.vhd
@@ -0,0 +1,98 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/fig_5_13.sch - Fri Aug 11 22:12:10 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY fig_5_13_fig_5_13_sch_tb IS
+END fig_5_13_fig_5_13_sch_tb;
+ARCHITECTURE behavioral OF fig_5_13_fig_5_13_sch_tb IS
+
+COMPONENT fig_5_13
+PORT( Code2 : IN STD_LOGIC;
+Code0 : IN STD_LOGIC;
+Code1 : IN STD_LOGIC;
+Data3 : OUT STD_LOGIC;
+Data4 : OUT STD_LOGIC;
+Data1 : OUT STD_LOGIC;
+Data2 : OUT STD_LOGIC;
+Data5 : OUT STD_LOGIC;
+Data6 : OUT STD_LOGIC;
+Data0 : OUT STD_LOGIC;
+Data7 : OUT STD_LOGIC);
+END COMPONENT;
+
+SIGNAL Code2 : STD_LOGIC;
+SIGNAL Code0 : STD_LOGIC;
+SIGNAL Code1 : STD_LOGIC;
+SIGNAL Data3 : STD_LOGIC;
+SIGNAL Data4 : STD_LOGIC;
+SIGNAL Data1 : STD_LOGIC;
+SIGNAL Data2 : STD_LOGIC;
+SIGNAL Data5 : STD_LOGIC;
+SIGNAL Data6 : STD_LOGIC;
+SIGNAL Data0 : STD_LOGIC;
+SIGNAL Data7 : STD_LOGIC;
+
+signal Data : std_logic_vector (7 downto 0);
+signal Code : std_logic_vector (2 downto 0);
+
+BEGIN
+
+Code2 <= Code (2);
+Code1 <= Code (1);
+Code0 <= Code (0);
+Data (7) <= Data7;
+Data (6) <= Data6;
+Data (5) <= Data5;
+Data (4) <= Data4;
+Data (3) <= Data3;
+Data (2) <= Data2;
+Data (1) <= Data1;
+Data (0) <= Data0;
+
+UUT: fig_5_13 PORT MAP(
+Code2 => Code2,
+Code0 => Code0,
+Code1 => Code1,
+Data3 => Data3,
+Data4 => Data4,
+Data1 => Data1,
+Data2 => Data2,
+Data5 => Data5,
+Data6 => Data6,
+Data0 => Data0,
+Data7 => Data7
+);
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+Code <= "000"; wait for 10 ns;
+Code <= "001"; wait for 10 ns;
+Code <= "010"; wait for 10 ns;
+Code <= "011"; wait for 10 ns;
+Code <= "100"; wait for 10 ns;
+Code <= "101"; wait for 10 ns;
+Code <= "110"; wait for 10 ns;
+Code <= "111"; wait for 10 ns;
+Code <= "000"; wait for 10 ns;
+report "tb done" severity failure;
+WAIT; -- will wait forever
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_fig_5_38.vhd b/vhdl_primitive/tb_fig_5_38.vhd
new file mode 100644
index 0000000..9c5a838
--- /dev/null
+++ b/vhdl_primitive/tb_fig_5_38.vhd
@@ -0,0 +1,73 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/fig_5_38.sch - Sat Aug 12 22:04:57 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY fig_5_38_fig_5_38_sch_tb IS
+END fig_5_38_fig_5_38_sch_tb;
+ARCHITECTURE behavioral OF fig_5_38_fig_5_38_sch_tb IS
+
+COMPONENT fig_5_38
+PORT( Asynch_in : IN STD_LOGIC;
+Synch_out : OUT STD_LOGIC;
+reset : IN STD_LOGIC;
+clock : IN STD_LOGIC);
+END COMPONENT;
+
+SIGNAL Asynch_in : STD_LOGIC;
+SIGNAL Synch_out : STD_LOGIC;
+SIGNAL reset : STD_LOGIC;
+SIGNAL clock : STD_LOGIC;
+
+constant clock_period : time := 10 ns;
+
+BEGIN
+
+UUT: fig_5_38 PORT MAP(
+Asynch_in => Asynch_in,
+Synch_out => Synch_out,
+reset => reset,
+clock => clock
+);
+
+cp : process is
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process cp;
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+reset <= '1'; wait for clock_period; reset <= '0';
+Asynch_in <= '0'; wait for 1 ns;
+Asynch_in <= '1'; wait for 3.3 ns;
+Asynch_in <= '0'; wait for 2 ns;
+Asynch_in <= '1'; wait for 2 ns;
+Asynch_in <= '0'; wait for 1 ns;
+Asynch_in <= '1'; wait for 4 ns;
+Asynch_in <= '0'; wait for 1 ns;
+Asynch_in <= '1'; wait for 5 ns;
+Asynch_in <= '0'; wait for 10 ns;
+report "tb done" severity failure;
+WAIT; -- will wait forever
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_fig_5_38b.vhd b/vhdl_primitive/tb_fig_5_38b.vhd
new file mode 100644
index 0000000..9361027
--- /dev/null
+++ b/vhdl_primitive/tb_fig_5_38b.vhd
@@ -0,0 +1,70 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/fig_5_38b.sch - Sat Aug 12 22:15:00 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY fig_5_38b_fig_5_38b_sch_tb IS
+END fig_5_38b_fig_5_38b_sch_tb;
+ARCHITECTURE behavioral OF fig_5_38b_fig_5_38b_sch_tb IS
+
+COMPONENT fig_5_38b
+PORT( clock : IN STD_LOGIC;
+Synch_out : OUT STD_LOGIC;
+Asynch_in : IN STD_LOGIC);
+END COMPONENT;
+
+SIGNAL clock : STD_LOGIC;
+SIGNAL Synch_out : STD_LOGIC;
+SIGNAL Asynch_in : STD_LOGIC;
+
+constant clock_period : time := 10 ns;
+
+BEGIN
+
+UUT: fig_5_38b PORT MAP(
+clock => clock,
+Synch_out => Synch_out,
+Asynch_in => Asynch_in
+);
+
+cp : process is
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process cp;
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+Asynch_in <= '0'; wait for 1 ns;
+Asynch_in <= '1'; wait for 0.01 ns;
+--Asynch_in <= '0'; wait for 0.01 ns;
+Asynch_in <= '0'; wait for 2 ns;
+Asynch_in <= '0'; wait for 2 ns;
+Asynch_in <= '0'; wait for 1 ns;
+Asynch_in <= '0'; wait for 4 ns;
+Asynch_in <= '0'; wait for 3 ns;
+Asynch_in <= '0'; wait for 5 ns;
+Asynch_in <= '0'; wait for 10 ns;
+report "tb done" severity failure;
+WAIT; -- will wait forever
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_fig_5_9.vhd b/vhdl_primitive/tb_fig_5_9.vhd
new file mode 100644
index 0000000..d6864db
--- /dev/null
+++ b/vhdl_primitive/tb_fig_5_9.vhd
@@ -0,0 +1,101 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/fig_5_9.sch - Fri Aug 11 18:06:35 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY fig_5_9_fig_5_9_sch_tb IS
+END fig_5_9_fig_5_9_sch_tb;
+ARCHITECTURE behavioral OF fig_5_9_fig_5_9_sch_tb IS
+
+COMPONENT fig_5_9
+PORT( A_eq_B : OUT STD_LOGIC;
+A_gt_B : OUT STD_LOGIC;
+B1 : IN STD_LOGIC;
+A1 : IN STD_LOGIC;
+B0 : IN STD_LOGIC;
+A0 : IN STD_LOGIC;
+A_lt_B : OUT STD_LOGIC);
+END COMPONENT;
+
+SIGNAL B1 : STD_LOGIC;
+SIGNAL A1 : STD_LOGIC;
+SIGNAL B0 : STD_LOGIC;
+SIGNAL A0 : STD_LOGIC;
+SIGNAL A_lt_B : STD_LOGIC;
+SIGNAL A_eq_B : STD_LOGIC;
+SIGNAL A_gt_B : STD_LOGIC;
+
+signal a,b : std_logic_vector (1 downto 0);
+
+BEGIN
+
+A1 <= a (1);
+A0 <= a (0);
+B1 <= b (1);
+B0 <= b (0);
+
+UUT: fig_5_9 PORT MAP(
+A_eq_B => A_eq_B,
+A_gt_B => A_gt_B,
+B1 => B1,
+A1 => A1,
+B0 => B0,
+A0 => A0,
+A_lt_B => A_lt_B
+);
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+a <= "00"; b <= "00";
+wait for 10 ns;
+a <= "00"; b <= "01";
+wait for 10 ns;
+a <= "00"; b <= "10";
+wait for 10 ns;
+a <= "00"; b <= "11";
+wait for 10 ns;
+a <= "01"; b <= "00";
+wait for 10 ns;
+a <= "01"; b <= "01";
+wait for 10 ns;
+a <= "01"; b <= "10";
+wait for 10 ns;
+a <= "01"; b <= "11";
+wait for 10 ns;
+a <= "10"; b <= "00";
+wait for 10 ns;
+a <= "10"; b <= "01";
+wait for 10 ns;
+a <= "10"; b <= "10";
+wait for 10 ns;
+a <= "10"; b <= "11";
+wait for 10 ns;
+a <= "11"; b <= "00";
+wait for 10 ns;
+a <= "11"; b <= "01";
+wait for 10 ns;
+a <= "11"; b <= "10";
+wait for 10 ns;
+a <= "11"; b <= "11";
+wait for 10 ns;
+report "tb done" severity failure;
+WAIT; -- will wait forever
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_fig_p5_15.vhd b/vhdl_primitive/tb_fig_p5_15.vhd
new file mode 100644
index 0000000..c31bf42
--- /dev/null
+++ b/vhdl_primitive/tb_fig_p5_15.vhd
@@ -0,0 +1,89 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/fig_p5_15.sch - Sat Aug 12 22:31:22 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY fig_p5_15_fig_p5_15_sch_tb IS
+END fig_p5_15_fig_p5_15_sch_tb;
+ARCHITECTURE behavioral OF fig_p5_15_fig_p5_15_sch_tb IS
+
+COMPONENT fig_p5_15
+PORT( P_odd : OUT STD_LOGIC;
+clk : IN STD_LOGIC;
+reset : IN STD_LOGIC;
+D_in : IN STD_LOGIC);
+END COMPONENT;
+
+SIGNAL P_odd : STD_LOGIC;
+SIGNAL clk : STD_LOGIC;
+SIGNAL reset : STD_LOGIC;
+SIGNAL D_in : STD_LOGIC;
+
+constant clk_period : time := 10 ns;
+
+BEGIN
+
+cp : process is
+begin
+clk <= '0';
+wait for clk_period/2;
+clk <= '1';
+wait for clk_period/2;
+end process cp;
+
+UUT: fig_p5_15 PORT MAP(
+P_odd => P_odd,
+clk => clk,
+reset => reset,
+D_in => D_in
+);
+
+-- *** Test Bench - User Defined Section ***
+tb : PROCESS
+BEGIN
+reset <= '1'; wait for clk_period; reset <= '0';
+D_in <= '0'; wait for clk_period;
+D_in <= '1'; wait for clk_period;
+D_in <= '0'; wait for clk_period;
+D_in <= '1'; wait for clk_period;
+D_in <= '0'; wait for clk_period;
+D_in <= '0'; wait for clk_period;
+D_in <= '1'; wait for clk_period;
+D_in <= '0'; wait for clk_period;
+D_in <= '1'; wait for clk_period;
+D_in <= '0'; wait for clk_period;
+D_in <= '0'; wait for clk_period;
+D_in <= '1'; wait for clk_period;
+D_in <= '1'; wait for clk_period;
+D_in <= '1'; wait for clk_period;
+D_in <= '1'; wait for clk_period;
+D_in <= '1'; wait for clk_period;
+D_in <= '1'; wait for clk_period;
+D_in <= '0'; wait for clk_period;
+D_in <= '1'; wait for clk_period;
+D_in <= '0'; wait for clk_period;
+D_in <= '0'; wait for clk_period;
+D_in <= '1'; wait for clk_period;
+D_in <= '0'; wait for clk_period;
+D_in <= '1'; wait for clk_period;
+D_in <= '0'; wait for clk_period;
+report "tb done" severity failure;
+WAIT; -- will wait forever
+END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_hurst_gates.vhd b/vhdl_primitive/tb_hurst_gates.vhd
new file mode 100755
index 0000000..851a53f
--- /dev/null
+++ b/vhdl_primitive/tb_hurst_gates.vhd
@@ -0,0 +1,130 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:15:12 05/09/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_hurst_gates.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: hurst_gates
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_hurst_gates IS
+END tb_hurst_gates;
+
+ARCHITECTURE behavior OF tb_hurst_gates IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT hurst_gates
+PORT(
+a : IN std_logic;
+b : IN std_logic;
+c : IN std_logic;
+y1 : OUT std_logic;
+y2 : OUT std_logic;
+y3 : OUT std_logic;
+y4 : OUT std_logic;
+y5 : OUT std_logic;
+y6 : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal a : std_logic := '0';
+signal b : std_logic := '0';
+signal c : std_logic := '0';
+
+--Outputs
+signal y1 : std_logic;
+signal y2 : std_logic;
+signal y3 : std_logic;
+signal y4 : std_logic;
+signal y5 : std_logic;
+signal y6 : std_logic;
+
+constant clock_period : time := 10 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: hurst_gates PORT MAP (
+a => a,
+b => b,
+c => c,
+y1 => y1,
+y2 => y2,
+y3 => y3,
+y4 => y4,
+y5 => y5,
+y6 => y6
+);
+
+-- Stimulus process
+stim_proc: process
+ constant N : integer := 4;
+ type input_array is array(0 to N-1) of std_logic_vector(1 downto 0);
+ variable input : input_array := ("01","01","10","11");
+ constant M : integer := 16;
+ type fy1_record is record
+ ip : std_logic_vector(2 downto 0);
+ op : std_logic;
+ end record fy1_record;
+ type fy1_array is array(0 to M-1) of fy1_record;
+ variable fy1 : fy1_array := ( -- a b c
+ (('1', '0', input(0)(1)), input(0)(0)), -- 1 0 x2
+ (('0', '0', input(0)(1)), input(0)(1)), -- 0 0 x2
+ ((not input(0)(0), '0', input(0)(1)), input(0)(0)), -- x1b 0 x2
+ ((input(0)(0), '0', input(0)(1)), not input(0)(0)), -- x1 0 x2
+ ((not input(0)(1), '0', input(0)(1)), input(0)(1)), -- x2b 0 x2
+ ((input(0)(1), '0', input(0)(1)), not input(0)(1)), -- x2 0 x2
+ ((input(0)(0), '1', input(0)(1)), input(0)(0) and input(0)(1)), -- x1 1 x2
+ ((input(0)(0), '1', not input(0)(1)), input(0)(0) and not input(0)(1)), -- x1 1 x2b
+ ((not input(0)(0), '1', not input(0)(1)), not input(0)(0) and input(0)(1)), -- x1b 1 x2b
+ ((not input(0)(0), '1', not input(0)(1)), not input(0)(0) and not input(0)(1)), -- x1b 1 x2b
+ ((not input(0)(0), not input(0)(0), input(0)(1)), input(0)(0) or input(0)(1)), -- x1b x1b x2
+ ((not input(0)(0), not input(0)(0), not input(0)(1)), input(0)(0) or not input(0)(1)), -- x1b x1b x2b
+ ((input(0)(0), input(0)(0), input(0)(1)), not input(0)(0) or input(0)(1)), -- x1 x1 x2
+ ((input(0)(0), input(0)(0), not input(0)(1)), not input(0)(0) or not input(0)(1)), -- x1 x1 x2b
+ ((not input(0)(0), input(0)(1), input(0)(1)), input(0)(0) xor input(0)(1)), -- x1b x2 x2
+ ((input(0)(0), input(0)(1), input(0)(1)), input(0)(0) xnor input(0)(1)) -- x1 x2 x2
+ );
+begin
+ wait for clock_period;
+ -- insert stimulus here
+ l0 : for i in fy1'range loop
+ a <= fy1(i).ip(0);
+ b <= fy1(i).ip(1);
+ c <= fy1(i).ip(2);
+ assert (y1=fy1(i).op)
+ report
+ "fail on i="&integer'image(i)&",y="&std_logic'image(y1)&" expected "&std_logic'image(fy1(i).op)
+ severity warning;
+ wait for clock_period;
+ end loop l0;
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_leddet.vhd b/vhdl_primitive/tb_leddet.vhd
new file mode 100755
index 0000000..03e7beb
--- /dev/null
+++ b/vhdl_primitive/tb_leddet.vhd
@@ -0,0 +1,103 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:04:09 05/09/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_leddet.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: LEDDET
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_leddet IS
+END tb_leddet;
+
+ARCHITECTURE behavior OF tb_leddet IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT LEDDET
+ PORT(
+ Clock : IN std_logic;
+ Reset : IN std_logic;
+ Trigger : IN std_logic;
+ LED : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal Clock : std_logic := '0';
+ signal Reset : std_logic := '0';
+ signal Trigger : std_logic := '0';
+
+ --Outputs
+ signal LED : std_logic;
+
+ -- Clock period definitions
+ constant Clock_period : time := 10 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: LEDDET PORT MAP (
+ Clock => Clock,
+ Reset => Reset,
+ Trigger => Trigger,
+ LED => LED
+ );
+
+ -- Clock process definitions
+ Clock_process :process
+ begin
+ Clock <= '0';
+ wait for Clock_period/2;
+ Clock <= '1';
+ wait for Clock_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ Reset <= '1';
+ wait for 100 ns;
+ Reset <= '0';
+ wait for Clock_period*10;
+ Trigger <= '1';
+ wait for Clock_period*100;
+ Trigger <= '0';
+ wait for Clock_period;
+ Trigger <= '1';
+ wait for Clock_period*100;
+ Trigger <= '0';
+ -- insert stimulus here
+
+ wait;
+ end process;
+
+END;
diff --git a/vhdl_primitive/tb_logic_analyser.vhd b/vhdl_primitive/tb_logic_analyser.vhd
new file mode 100755
index 0000000..31df7dc
--- /dev/null
+++ b/vhdl_primitive/tb_logic_analyser.vhd
@@ -0,0 +1,160 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:32:30 05/04/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_logic_analyser.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: logic_analyser
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE work.p_globals.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_logic_analyser IS
+END tb_logic_analyser;
+
+ARCHITECTURE behavior OF tb_logic_analyser IS
+
+constant G_BOARD_CLOCK : integer := G_BOARD_CLOCK;
+constant G_BAUD_RATE : integer := 115_200;
+constant address_size : integer := 4;
+constant data_size : integer := 8;
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT logic_analyser
+GENERIC(
+G_BOARD_CLOCK : integer;
+G_BAUD_RATE : integer;
+address_size : integer;
+data_size : integer;
+G_RC_N : integer;
+G_RC_MAX : integer
+);
+PORT(
+i_clock : in std_logic;
+i_reset : in std_logic; -- XXX use for catch data
+i_catch : in std_logic;
+i_data : in std_logic_vector(data_size-1 downto 0);
+o_rs232_tx : out std_logic;
+o_sended : out std_logic;
+o_seg : out std_logic_vector(G_LCDSegment-1 downto 0);
+--o_dp : out std_logic;
+o_an : out std_logic_vector(G_LCDAnode-1 downto 0);
+o_data : out std_logic_vector(G_Led-1 downto 0)
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+signal i_catch : std_logic := '0';
+signal i_data : std_logic_vector(data_size-1 downto 0) := (others => '0');
+
+--Outputs
+signal o_rs232_tx : std_logic;
+signal o_sended : std_logic;
+signal o_seg : std_logic_vector(G_LCDSegment-1 downto 0);
+--signal o_dp : std_logic;
+signal o_an : std_logic_vector(G_LCDAnode-1 downto 0);
+signal o_data : std_logic_vector(G_Led-1 downto 0);
+
+-- Clock period definitions
+constant i_clock_period : time := (1_000_000_000/G_BOARD_CLOCK) * 1 ns; -- XXX 50Mhz
+
+constant N : integer := 2**address_size-1;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: logic_analyser
+GENERIC MAP (
+G_BOARD_CLOCK => G_BOARD_CLOCK,
+G_BAUD_RATE => G_BAUD_RATE,
+address_size => address_size,
+data_size => data_size,
+G_RC_N => G_DEBOUNCE_MS_BITS,
+G_RC_MAX => G_DEBOUNCE_MS_COUNT
+)
+PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+i_catch => i_catch,
+i_data => i_data,
+o_rs232_tx => o_rs232_tx,
+o_sended => o_sended,
+o_seg => o_seg,
+--o_dp => o_dp,
+o_an => o_an,
+o_data => o_data
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- Stimulus process
+write_proc : process
+constant W : time := G_DEBOUNCE_MS/G_DEBOUNCE_DIV * 1 ms;
+begin
+
+report "CLOCK PERIOD " & time'image(i_clock_period) severity warning;
+report "DB TICKS " & integer'image(G_DEBOUNCE_MS_COUNT) severity warning;
+report "DB BITS " & integer'image(G_DEBOUNCE_MS_BITS) severity warning;
+
+i_reset <= '1';
+wait for 100 ns;
+i_reset <= '0';
+
+wait for 10*i_clock_period;
+
+-- insert stimulus here
+
+l0 : for i in 0 to N-1 loop
+
+i_data <= std_logic_vector(to_unsigned(i,data_size));
+
+wait for 3*i_clock_period;
+i_catch <= '1';
+--report "catch wait " & integer'image(G_BOARD_CLOCK/G_DEBOUNCE_MS_COUNT) severity warning;
+--wait for W; -- wait for debounce
+wait for 164 * 1 us; -- wait for debounce
+i_catch <= '0';
+wait for 25*i_clock_period;
+
+end loop l0;
+
+wait;
+
+end process write_proc;
+
+assert (o_sended /= '1') report "end test" severity failure;
+
+END;
diff --git a/vhdl_primitive/tb_mem_decoder_col.vhd b/vhdl_primitive/tb_mem_decoder_col.vhd
new file mode 100755
index 0000000..d822e96
--- /dev/null
+++ b/vhdl_primitive/tb_mem_decoder_col.vhd
@@ -0,0 +1,123 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:45:41 04/26/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_mem_decoder_col.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: mem_decoder_col
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_mem_decoder_col IS
+END tb_mem_decoder_col;
+
+ARCHITECTURE behavior OF tb_mem_decoder_col IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT mem_decoder_col
+PORT(
+decoder_col_input : IN std_logic_vector(5 downto 0);
+decoder_col_output : OUT std_logic_vector(63 downto 0);
+e : IN STD_LOGIC
+);
+END COMPONENT;
+
+--Inputs
+signal decoder_col_input : std_logic_vector(5 downto 0) := (others => '0');
+signal e : std_logic := '0';
+
+--Outputs
+signal decoder_col_output : std_logic_vector(63 downto 0);
+
+constant clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: mem_decoder_col PORT MAP (
+decoder_col_input => decoder_col_input,
+decoder_col_output => decoder_col_output,
+e => e
+);
+
+-- Stimulus process
+stim_proc: process
+constant N : integer := 2**(decoder_col_input'left+1);
+function one_position(v : std_logic_vector) return integer is
+ variable r : integer := 0;
+begin
+ l0 : for i in v'range loop
+ if (v(v'high-i) = '1') then
+ exit;
+ else
+ r := r + 1;
+ end if;
+ end loop l0;
+ return r;
+end function one_position;
+function vec2str(vec: std_logic_vector) return string is
+ variable result: string(vec'left downto 0);
+begin
+ for i in vec'reverse_range loop
+ if (vec(i) = '1') then
+ result(i) := '1';
+ elsif (vec(i) = '0') then
+ result(i) := '0';
+ else
+ result(i) := 'X';
+ end if;
+ end loop;
+return result;
+end;
+variable v : std_logic_vector(5 downto 0);
+begin
+
+loop0 : for i in 0 to N-1 loop
+e <= '1';
+v := std_logic_vector(to_unsigned(i,6));
+case (i) is
+when 0 to 15 =>
+ decoder_col_input <= v(3 downto 0) & "00";
+when 16 to 31 =>
+ decoder_col_input <= v(3 downto 0) & "01";
+when 32 to 47 =>
+ decoder_col_input <= v(3 downto 0) & "10";
+when 48 to 63 =>
+ decoder_col_input <= v(3 downto 0) & "11";
+end case;
+wait for clock_period;
+assert (one_position(decoder_col_output) =i) report " ERROR : " & vec2str(decoder_col_output) & " - position " & integer'image(one_position(decoder_col_output)) & " , expect " & integer'image(i) severity note;
+assert (one_position(decoder_col_output)/=i) report " OK : " & vec2str(decoder_col_output) & " - position " & integer'image(one_position(decoder_col_output)) & " , expect " & integer'image(i) severity note;
+e <= '0';
+wait for clock_period;
+assert (i/=N-1) report "end" severity failure;
+end loop loop0;
+wait;
+
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_mem_decoder_row.vhd b/vhdl_primitive/tb_mem_decoder_row.vhd
new file mode 100755
index 0000000..660dbb5
--- /dev/null
+++ b/vhdl_primitive/tb_mem_decoder_row.vhd
@@ -0,0 +1,133 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:06:44 04/25/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_mem_decoder_row.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: mem_decoder_row
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_mem_decoder_row IS
+END tb_mem_decoder_row;
+
+ARCHITECTURE behavior OF tb_mem_decoder_row IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT mem_decoder_row
+PORT(
+decoder_row_input : IN std_logic_vector(8 downto 0);
+decoder_row_output : OUT std_logic_vector(511 downto 0);
+e : IN std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal decoder_row_input : std_logic_vector(8 downto 0) := (others => '0');
+signal e : std_logic;
+
+--Outputs
+signal decoder_row_output : std_logic_vector(511 downto 0);
+
+constant clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: mem_decoder_row PORT MAP (
+decoder_row_input => decoder_row_input,
+decoder_row_output => decoder_row_output,
+e => e
+);
+
+-- Stimulus process
+stim_proc: process
+constant N : integer := 2**(decoder_row_input'left+1);
+function one_position(v : std_logic_vector) return integer is
+ variable r : integer := 0;
+begin
+ l0 : for i in v'range loop
+ if (v(v'high-i) = '1') then
+ exit;
+ else
+ r := r + 1;
+ end if;
+ end loop l0;
+ return r;
+end function one_position;
+--vec2str(decoder_row_output)
+function vec2str(vec: std_logic_vector) return string is
+ variable result: string(vec'left downto 0);
+begin
+ for i in vec'reverse_range loop
+ if (vec(i) = '1') then
+ result(i) := '1';
+ elsif (vec(i) = '0') then
+ result(i) := '0';
+ else
+ result(i) := 'X';
+ end if;
+ end loop;
+return result;
+end;
+variable vu : std_logic_vector(3 downto 0);
+variable vl : std_logic_vector(3 downto 0);
+begin
+
+e <= '1'; -- XXX todo
+
+l0 : for i in 0 to 15 loop
+ vu := std_logic_vector(to_unsigned(i,4));
+ l1 : for j in 0 to 15 loop
+ vl := std_logic_vector(to_unsigned(j,4));
+ decoder_row_input(8 downto 0) <= '0' & vu & vl;
+ wait for clock_period;
+ assert (one_position(decoder_row_output) =to_integer(unsigned(decoder_row_input))) report " ERROR " & " : position " & integer'image(one_position(decoder_row_output)) & " , expect " & integer'image(to_integer(unsigned(decoder_row_input))) severity note;
+ assert (one_position(decoder_row_output)/=to_integer(unsigned(decoder_row_input))) report " OK " & " : position " & integer'image(one_position(decoder_row_output)) & " , expect " & integer'image(to_integer(unsigned(decoder_row_input))) severity note;
+ wait for clock_period;
+ end loop l1;
+end loop l0;
+
+wait for clock_period;
+
+ll0 : for i in 0 to 15 loop
+ vu := std_logic_vector(to_unsigned(i,4));
+ ll1 : for j in 0 to 15 loop
+ vl := std_logic_vector(to_unsigned(j,4));
+ decoder_row_input(8 downto 0) <= '1' & vu & vl;
+ wait for clock_period;
+ assert (one_position(decoder_row_output) =to_integer(unsigned(decoder_row_input))) report " ERROR " & " : position " & integer'image(one_position(decoder_row_output)) & " , expect " & integer'image(to_integer(unsigned(decoder_row_input))) severity note;
+ assert (one_position(decoder_row_output)/=to_integer(unsigned(decoder_row_input))) report " OK " & " : position " & integer'image(one_position(decoder_row_output)) & " , expect " & integer'image(to_integer(unsigned(decoder_row_input))) severity note;
+ wait for clock_period;
+ end loop ll1;
+end loop ll0;
+
+wait;
+
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_nxp_74hc573.vhd b/vhdl_primitive/tb_nxp_74hc573.vhd
new file mode 100755
index 0000000..21c57f9
--- /dev/null
+++ b/vhdl_primitive/tb_nxp_74hc573.vhd
@@ -0,0 +1,112 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 10:44:23 04/12/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_nxp_74hc573.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: nxp_74hc573
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_nxp_74hc573 IS
+END tb_nxp_74hc573;
+
+ARCHITECTURE behavior OF tb_nxp_74hc573 IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT nxp_74hc573
+PORT(
+i_le : IN std_logic;
+i_oeb : IN std_logic;
+i_d : IN std_logic_vector(7 downto 0);
+o_q : OUT std_logic_vector(7 downto 0)
+);
+END COMPONENT;
+
+--Inputs
+signal i_le : std_logic := '0';
+signal i_oeb : std_logic := '0';
+signal i_d : std_logic_vector(7 downto 0) := (others => '0');
+
+--Outputs
+signal o_q : std_logic_vector(7 downto 0);
+
+-- No clocks detected in port list. Replace clock below with
+-- appropriate port name
+signal clock : std_logic := '0';
+
+constant clock_period : time := 1000 ns;
+constant wait0 : time := 2 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: nxp_74hc573 PORT MAP (
+i_le => i_le,
+i_oeb => i_oeb,
+i_d => i_d,
+o_q => o_q
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+constant npattern : integer := 6;
+type array_pattern is array(0 to npattern-1) of std_logic_vector(7 downto 0);
+variable pattern : array_pattern := (
+"01010101","10101010","11111111","11110000","00001111","00000000"
+);
+begin
+-- insert stimulus here
+l0 : for i in 0 to npattern-1 loop
+i_oeb <= '1';
+i_d <= pattern(i);
+i_le <= '1';
+wait for wait0;
+i_le <= '0';
+i_oeb <= '1';
+wait for wait0;
+i_le <= '1';
+i_oeb <= '0';
+wait for wait0;
+i_le <= '0';
+i_oeb <= '0';
+wait for wait0;
+end loop l0;
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_ones_detector.vhd b/vhdl_primitive/tb_ones_detector.vhd
new file mode 100755
index 0000000..b07d895
--- /dev/null
+++ b/vhdl_primitive/tb_ones_detector.vhd
@@ -0,0 +1,118 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:22:53 04/28/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_ones_detector.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: ones_detector
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_ones_detector IS
+END tb_ones_detector;
+
+ARCHITECTURE behavior OF tb_ones_detector IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT ones_detector
+PORT(
+x : IN std_logic_vector(15 downto 1);
+y : OUT std_logic_vector(3 downto 0)
+);
+END COMPONENT;
+
+--Inputs
+signal x : std_logic_vector(15 downto 1) := (others => '0');
+
+--Outputs
+signal y : std_logic_vector(3 downto 0);
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: ones_detector PORT MAP (
+x => x,
+y => y
+);
+
+-- Stimulus process
+stim_proc: process
+constant N : integer := 23;
+type array_data_expect is array(integer range <>) of std_logic_vector(3 downto 0);
+variable data_expect : array_data_expect(0 to N-1) := (
+x"0", -- XXX bad
+x"7",x"F",x"0",x"8",
+x"8",x"B",x"c",x"3",
+x"4",x"7",x"4",x"4",
+x"b",x"b",x"c",x"5",
+x"6",x"a",x"5",x"6",
+x"6",
+x"1" -- XXX bad
+);
+type array_data_in is array(integer range <>) of std_logic_vector(15 downto 1);
+variable data_in : array_data_in(0 to N-1) := (
+std_logic_vector(to_unsigned(to_integer(unsigned'(x"DEAD")),15)),
+"010101010101010",
+"111111111111111",
+"000000000000000",
+"101010101010101",
+
+"110011001100110",
+"110111011101110",
+"111011101110111",
+"000100010001000",
+
+"001000100010001",
+"001100110011001",
+"010001000100001",
+"100010001000100",
+
+"011101110111011",
+"101110111011101",
+"111011011101111",
+"100000010001110",
+
+"001010101000110",
+"100111001111011",
+"000010000111001",
+"100010000100111",
+
+"000011111100000",
+std_logic_vector(to_unsigned(to_integer(unsigned'(x"CAFE")),15))
+);
+begin
+-- insert stimulus here
+loop0 : for i in 0 to N-1 loop
+x <= data_in(i);
+wait for 10 ns;
+assert (y=data_expect(i)) report "error at " & integer'image(i) & " : y is " & integer'image(to_integer(unsigned(y(3 downto 0)))) & " , expect " & integer'image(to_integer(unsigned(data_expect(i))));
+wait for 500 ns;
+end loop loop0;
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_or_n_gate.vhd b/vhdl_primitive/tb_or_n_gate.vhd
new file mode 100755
index 0000000..a6adc78
--- /dev/null
+++ b/vhdl_primitive/tb_or_n_gate.vhd
@@ -0,0 +1,84 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:16:33 04/18/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_or_n_gate.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: OR_N_GATE
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_or_n_gate IS
+END tb_or_n_gate;
+
+ARCHITECTURE behavior OF tb_or_n_gate IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT OR_N_GATE
+PORT(
+input : IN std_logic_vector(7 downto 0);
+output : OUT std_logic
+);
+END COMPONENT;
+
+
+--Inputs
+signal input : std_logic_vector(7 downto 0) := (others => '0');
+
+--Outputs
+signal output : std_logic;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: OR_N_GATE PORT MAP (
+input => input,
+output => output
+);
+
+-- Stimulus process
+stim_proc: process
+begin
+-- insert stimulus here
+input <= (others => '1');
+wait for 100 ns;
+input <= (others => '0');
+wait for 100 ns;
+input <= "10101010";
+wait for 100 ns;
+input <= "01010101";
+wait for 100 ns;
+input <= "00000001";
+wait for 100 ns;
+input <= "10000001";
+wait for 100 ns;
+input <= "11111111";
+wait for 100 ns;
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_osc_test1.vhd b/vhdl_primitive/tb_osc_test1.vhd
new file mode 100644
index 0000000..de06fb8
--- /dev/null
+++ b/vhdl_primitive/tb_osc_test1.vhd
@@ -0,0 +1,47 @@
+-- Vhdl test bench created from schematic /home/user/workspace/vhdl_projects/vhdl_primitive/osc_test1.sch - Sun Aug 27 20:46:24 2023
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY osc_test1_osc_test1_sch_tb IS
+END osc_test1_osc_test1_sch_tb;
+ARCHITECTURE behavioral OF osc_test1_osc_test1_sch_tb IS
+
+ COMPONENT osc_test1
+ PORT( op : OUT STD_LOGIC;
+ ip : IN STD_LOGIC);
+ END COMPONENT;
+
+ SIGNAL op : STD_LOGIC := '0';
+ SIGNAL ip : STD_LOGIC := '0';
+
+BEGIN
+
+ UUT: osc_test1 PORT MAP(
+ op => op,
+ ip => ip
+ );
+
+-- *** Test Bench - User Defined Section ***
+ tb : PROCESS
+ BEGIN
+ ip <= '1';
+ WAIT for 1 ms; -- will wait forever
+ END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/vhdl_primitive/tb_pwm_generator.vhd b/vhdl_primitive/tb_pwm_generator.vhd
new file mode 100755
index 0000000..3ac0b44
--- /dev/null
+++ b/vhdl_primitive/tb_pwm_generator.vhd
@@ -0,0 +1,103 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:39:28 04/19/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_pwm_generator.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: PWM_generator
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_pwm_generator IS
+END tb_pwm_generator;
+
+ARCHITECTURE behavior OF tb_pwm_generator IS
+
+constant N : integer := 4;
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT PWM_generator
+GENERIC(N : integer);
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+i_data : IN std_logic_vector(N-1 downto 0);
+o_pwm : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+signal i_data : std_logic_vector(N-1 downto 0) := (others => '0');
+
+--Outputs
+signal o_pwm : std_logic;
+
+-- Clock period definitions
+constant i_clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: PWM_generator
+GENERIC MAP (N => N)
+PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+i_data => i_data,
+o_pwm => o_pwm
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+i_reset <= '1';
+wait for 100 ns;
+i_reset <= '0';
+wait for i_clock_period*10;
+-- insert stimulus here
+l0 : for i in 0 to (2**N)-1 loop
+i_data <= std_logic_vector(to_unsigned(i,N));
+wait for i_clock_period*(2**N)*2;
+end loop l0;
+i_data <= std_logic_vector(to_unsigned(0,N));
+wait for i_clock_period*(2**N)*2;
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_ripple_counter.vhd b/vhdl_primitive/tb_ripple_counter.vhd
new file mode 100755
index 0000000..7573804
--- /dev/null
+++ b/vhdl_primitive/tb_ripple_counter.vhd
@@ -0,0 +1,177 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:55:32 05/04/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_ripple_counter.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: ripple_counter
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ripple_counter IS
+END tb_ripple_counter;
+
+ARCHITECTURE behavior OF tb_ripple_counter IS
+
+constant N : integer := 8;
+constant MAX : integer := 130;
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT ripple_counter
+GENERIC(
+N : integer;
+MAX : integer
+);
+PORT(
+i_clock : IN std_logic;
+i_cpb : IN std_logic;
+i_mrb : IN std_logic;
+i_ud : IN std_logic;
+o_q : INOUT std_logic_vector(N-1 downto 0);
+o_ping : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_cpb : std_logic := '0';
+signal i_mrb : std_logic := '0';
+signal i_ud : std_logic := '0';
+
+--BiDirs
+signal o_q : std_logic_vector(N-1 downto 0);
+signal o_ping : std_logic;
+
+signal clock : std_logic := '0';
+constant clock_period : time := 10 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: ripple_counter
+GENERIC MAP (
+N => N,
+MAX => MAX
+)
+PORT MAP (
+i_clock => i_clock,
+i_cpb => i_cpb,
+i_mrb => i_mrb,
+i_ud => i_ud,
+o_q => o_q,
+o_ping => o_ping
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+i_clock <= clock;
+
+-- Stimulus process
+stim_proc: process
+begin
+
+---- insert stimulus here
+
+-- reset, ok 0 when reset=1
+wait for clock_period;
+i_mrb <= '1';
+wait for 25*clock_period;
+i_mrb <= '0';
+
+-- wait some time, count down when ud=0
+wait for 100*clock_period;
+
+-- mrb,cpb must be 1 to reset and start count
+i_mrb <= '1';
+i_cpb <= '1';
+i_ud <= '1'; -- count up
+wait for 1*clock_period;
+i_mrb <= '0'; -- start counting
+wait for 4*MAX*clock_period; -- wait MAX ticks
+i_cpb <= '0'; -- ok, count from 0 to MAX-2, MAX-1=0 then ping
+i_ud <= '0';
+
+-- wait some time
+wait for 100*clock_period;
+
+-- dont want reset, reset in middle cpb
+wait for clock_period;
+i_cpb <= '1';
+i_ud <= '0'; -- count down
+wait for (MAX*clock_period)/2 - 241 ns;
+i_mrb <= '1';
+wait for clock_period;
+i_mrb <= '0';
+wait for (MAX*clock_period)/2 + 241 ns;
+wait for (MAX*clock_period)/2 - 123 ns;
+i_mrb <= '1';
+wait for clock_period;
+i_mrb <= '0';
+wait for (MAX*clock_period)/2 + 123 ns;
+wait for (MAX*clock_period)/2 - 177 ns;
+i_mrb <= '1';
+wait for clock_period;
+i_mrb <= '0';
+wait for (MAX*clock_period)/2 + 177 ns;
+wait for (MAX*clock_period)/2 - 89 ns;
+i_mrb <= '1';
+wait for clock_period;
+i_mrb <= '0';
+wait for (MAX*clock_period)/2 + 89 ns;
+i_cpb <= '0'; -- strange
+i_ud <= '0';
+
+-- wait some time, not count, stay on 1
+wait for 100*clock_period;
+
+-- mrb,cpb must be 1 to reset and start count
+wait for clock_period;
+i_mrb <= '1';
+i_cpb <= '1';
+i_ud <= '0'; -- count down
+wait for 1*clock_period; -- wait for reset
+i_mrb <= '0'; -- start counting
+wait for 4*MAX*clock_period;
+i_cpb <= '0'; -- strange
+i_ud <= '0';
+
+wait for 10*clock_period; -- XXX reset
+i_mrb <= '1';
+wait for 100*clock_period;
+i_mrb <= '0';
+
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_sar_adc.vhd b/vhdl_primitive/tb_sar_adc.vhd
new file mode 100755
index 0000000..e8b3115
--- /dev/null
+++ b/vhdl_primitive/tb_sar_adc.vhd
@@ -0,0 +1,114 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:28:32 05/07/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_sar_adc.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: sar_adc
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_sar_adc IS
+END tb_sar_adc;
+
+ARCHITECTURE behavior OF tb_sar_adc IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT sar_adc
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+o_data : OUT std_logic_vector(7 downto 0);
+o_to_pluscomparator : OUT std_logic;
+i_from_comparator : IN std_logic;
+o_sar_end : inout std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+signal i_from_comparator : std_logic := '0';
+
+--Outputs
+signal o_data : std_logic_vector(7 downto 0);
+signal o_to_pluscomparator : std_logic;
+signal o_sar_end : std_logic;
+
+-- Clock period definitions
+constant i_clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: sar_adc PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+o_data => o_data,
+o_to_pluscomparator => o_to_pluscomparator,
+i_from_comparator => i_from_comparator,
+o_sar_end => o_sar_end
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+i_reset <= '1';
+wait for 100 ns;
+i_reset <= '0';
+wait for i_clock_period*10;
+i_from_comparator <= '1';
+wait for i_clock_period;
+i_from_comparator <= '0';
+wait for i_clock_period;
+i_from_comparator <= '1';
+wait for i_clock_period;
+i_from_comparator <= '0';
+wait for i_clock_period;
+i_from_comparator <= '1';
+wait for i_clock_period;
+i_from_comparator <= '0';
+wait for i_clock_period;
+i_from_comparator <= '1';
+wait for i_clock_period;
+i_from_comparator <= '0';
+wait for i_clock_period;
+--o_sar_end <= '1';
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_schneider_circuit.vhd b/vhdl_primitive/tb_schneider_circuit.vhd
new file mode 100755
index 0000000..4d1b1c8
--- /dev/null
+++ b/vhdl_primitive/tb_schneider_circuit.vhd
@@ -0,0 +1,143 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:54:49 06/30/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_schneider_circuit.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: schneider_circuit
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_schneider_circuit IS
+END tb_schneider_circuit;
+
+ARCHITECTURE behavior OF tb_schneider_circuit IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT schneider_circuit
+ PORT(
+ x1 : IN std_logic;
+ x2 : IN std_logic;
+ x3 : IN std_logic;
+ x4 : IN std_logic;
+ y : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal x1 : std_logic := '0';
+ signal x2 : std_logic := '0';
+ signal x3 : std_logic := '0';
+ signal x4 : std_logic := '0';
+
+ --Outputs
+ signal y : std_logic;
+ -- No clocks detected in port list. Replace below with
+ -- appropriate port name
+
+signal clock : std_logic;
+ constant clock_period : time := 10 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: schneider_circuit PORT MAP (
+ x1 => x1,
+ x2 => x2,
+ x3 => x3,
+ x4 => x4,
+ y => y
+ );
+
+ -- Clock process definitions
+ clock_process :process
+ begin
+ clock <= '0';
+ wait for clock_period/2;
+ clock <= '1';
+ wait for clock_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+variable index : integer range 0 to 15 := 0;
+variable xs : std_logic_vector(3 downto 0) := (others => '0');
+ begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+
+ wait for clock_period*10;
+
+ -- insert stimulus here
+
+x1 <= '1';
+x2 <= '1';
+x3 <= '1';
+x4 <= '1';
+wait for clock_period;
+
+x1 <= '0';
+x2 <= '0';
+x3 <= '0';
+x4 <= '0';
+wait for clock_period;
+
+x1 <= 'Z';
+x2 <= 'Z';
+x3 <= 'Z';
+x4 <= 'Z';
+wait for clock_period;
+
+x1 <= '-';
+x2 <= '-';
+x3 <= '-';
+x4 <= '-';
+wait for clock_period;
+
+x1 <= 'U';
+x2 <= 'U';
+x3 <= 'U';
+x4 <= 'U';
+wait for clock_period;
+
+l0 : for i in 0 to 15 loop
+assert (false) report "i="&integer'image(i) severity note;
+xs := std_logic_vector(to_unsigned(i,4));
+x1 <= xs(0);
+x2 <= xs(1);
+x3 <= xs(2);
+x4 <= xs(3);
+wait for clock_period;
+end loop l0;
+
+ wait;
+ end process;
+
+END;
diff --git a/vhdl_primitive/tb_serial_line_code.vhd b/vhdl_primitive/tb_serial_line_code.vhd
new file mode 100644
index 0000000..297666b
--- /dev/null
+++ b/vhdl_primitive/tb_serial_line_code.vhd
@@ -0,0 +1,129 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:19:55 06/03/2023
+-- Design Name: fig_3_24
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_serial_line_code.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: serial_line_code
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types bit and
+-- bit_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_serial_line_code IS
+END tb_serial_line_code;
+
+ARCHITECTURE behavior OF tb_serial_line_code IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT serial_line_code
+PORT(
+clock_1 : IN bit;
+clock_2 : IN bit;
+reset : IN bit;
+B_in : IN bit;
+NRZ_Mealy : OUT bit;
+NRZ_Moore : OUT bit;
+NRZI_Mealy : OUT bit;
+NRZI_Moore : OUT bit;
+RZ : OUT bit;
+Manchester : OUT bit
+);
+END COMPONENT;
+
+--Inputs
+signal clock_1 : bit := '0';
+signal clock_2 : bit := '0';
+signal reset : bit := '0';
+signal B_in : bit := '0';
+
+--Outputs
+signal NRZ_Mealy : bit;
+signal NRZ_Moore : bit;
+signal NRZI_Mealy : bit;
+signal NRZI_Moore : bit;
+signal RZ : bit;
+signal Manchester : bit;
+
+-- Clock period definitions
+constant clock_1_period : time := 10 ns; -- speed 1x
+constant clock_2_period : time := 5 ns; -- speed 2x
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: serial_line_code PORT MAP (
+clock_1 => clock_1,
+clock_2 => clock_2,
+reset => reset,
+B_in => B_in,
+NRZ_Mealy => NRZ_Mealy,
+NRZ_Moore => NRZ_Moore,
+NRZI_Mealy => NRZI_Mealy,
+NRZI_Moore => NRZI_Moore,
+RZ => RZ,
+Manchester => Manchester
+);
+
+-- Clock process definitions
+clock_1_process :process
+begin
+clock_1 <= '0';
+wait for clock_1_period/2;
+clock_1 <= '1';
+wait for clock_1_period/2;
+end process;
+
+clock_2_process :process
+begin
+clock_2 <= '0';
+wait for clock_2_period/2;
+clock_2 <= '1';
+wait for clock_2_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+reset <= '1';
+wait for 100 ns;
+reset <= '0';
+--wait for clock_1_period;
+-- insert stimulus here
+B_in <= '0'; wait for clock_1_period;
+B_in <= '1'; wait for clock_1_period;
+B_in <= '1'; wait for clock_1_period;
+B_in <= '1'; wait for clock_1_period;
+B_in <= '0'; wait for clock_1_period;
+B_in <= '0'; wait for clock_1_period;
+B_in <= '1'; wait for clock_1_period;
+B_in <= '0'; wait for clock_1_period;
+B_in <= '0'; wait for clock_1_period;
+B_in <= '0'; wait for clock_1_period;
+report "tb done" severity failure;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_signal_generator.vhd b/vhdl_primitive/tb_signal_generator.vhd
new file mode 100755
index 0000000..e47cc89
--- /dev/null
+++ b/vhdl_primitive/tb_signal_generator.vhd
@@ -0,0 +1,85 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 08:12:33 12/13/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_signal_generator.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: signal_generator
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_signal_generator IS
+END tb_signal_generator;
+
+ARCHITECTURE behavior OF tb_signal_generator IS
+
+COMPONENT signal_generator
+PORT(
+clk : IN std_logic;
+x : BUFFER std_logic;
+y : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal clk : std_logic := '0';
+
+--Outputs
+signal x : std_logic;
+signal y : std_logic;
+
+-- Clock period definitions
+constant clk_period : time := 10 ns;
+
+BEGIN
+
+uut: signal_generator PORT MAP (
+clk => clk,
+x => x,
+y => y
+);
+
+-- Clock process definitions
+clk_process :process
+begin
+clk <= '1';
+wait for (clk_period/2)*1;
+clk <= '0';
+wait for (clk_period/2)*9;
+end process;
+
+-- Stimulus process
+stim_proc : process
+begin
+-- insert stimulus here
+--x <= '1';
+--wait for clk_period*10;
+--x <= '0';
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_sn5474ls245.vhd b/vhdl_primitive/tb_sn5474ls245.vhd
new file mode 100755
index 0000000..16ea307
--- /dev/null
+++ b/vhdl_primitive/tb_sn5474ls245.vhd
@@ -0,0 +1,153 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:37:08 07/11/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_sn5474ls245.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: sn5474ls245
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_sn5474ls245 IS
+END tb_sn5474ls245;
+
+ARCHITECTURE behavior OF tb_sn5474ls245 IS
+
+constant N : integer := 8;
+constant CP : time := 20 ns;
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT sn5474ls245
+GENERIC(
+N : integer
+);
+PORT(
+i_dir : IN std_logic;
+i_eb : IN std_logic;
+io_a : INOUT std_logic_vector(N-1 downto 0);
+io_b : INOUT std_logic_vector(N-1 downto 0)
+);
+END COMPONENT;
+
+--Inputs
+signal i_dir : std_logic := 'U';
+signal i_eb : std_logic := 'U';
+
+--BiDirs
+signal io_a : std_logic_vector(N-1 downto 0) := (others => 'Z');
+signal io_b : std_logic_vector(N-1 downto 0) := (others => 'Z');
+
+signal a2b,b2a : std_logic_vector(N-1 downto 0) := (others => 'U');
+
+signal clock : std_logic;
+constant clock_period : time := CP;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: sn5474ls245
+GENERIC MAP (
+N => N
+)
+PORT MAP (
+i_dir => i_dir,
+i_eb => i_eb,
+io_a => io_a,
+io_b => io_b
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+constant TN : integer := 4;
+type at is array (0 to TN-1) of std_logic_vector(N-1 downto 0);
+variable t : at := (x"00",x"aa",x"bb",x"ff");
+constant first : std_logic_vector(N-1 downto 0) := t(0);
+constant last : std_logic_vector(N-1 downto 0) := t(t'length-1);
+function to_s(a : std_logic_vector) return string is
+variable ts : string(a'range) := (others => NUL);
+begin
+l0 : for i in a'range loop
+ts(i) := std_logic'image(a(i))(2); -- XXX 'X' = 1-',2-X,3-'
+end loop l0;
+return ts;
+end function;
+begin
+-- hold reset state for 100 ns.
+wait for 100 ns;
+i_dir <= 'U';
+i_eb <= 'U';
+wait for clock_period*10;
+
+-- insert stimulus here
+
+i_dir <= '0';
+i_eb <= '0';
+io_b <= t(1);
+--io_a <= t(1);
+wait for clock_period*1;
+b2a <= io_a;
+--b <= io_b;
+
+wait for clock_period*40;
+i_dir <= 'U';
+i_eb <= '1';
+io_a <= (others => 'Z');
+io_b <= (others => 'Z');
+a2b <= (others => 'U');
+b2a <= (others => 'U');
+wait for clock_period*40;
+
+i_dir <= '1';
+i_eb <= '0';
+--io_b <= t(2);
+io_a <= t(2);
+wait for clock_period*1;
+--a <= io_a;
+a2b <= io_b;
+
+wait for clock_period*40;
+i_dir <= 'U';
+i_eb <= '1';
+io_a <= (others => 'Z');
+io_b <= (others => 'Z');
+a2b <= (others => 'U');
+b2a <= (others => 'U');
+wait for clock_period*40;
+
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_sram_62256.vhd b/vhdl_primitive/tb_sram_62256.vhd
new file mode 100755
index 0000000..f3fd4e3
--- /dev/null
+++ b/vhdl_primitive/tb_sram_62256.vhd
@@ -0,0 +1,186 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:46:35 04/13/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_sram_62256.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: sram_62256
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_sram_62256 IS
+END tb_sram_62256;
+
+ARCHITECTURE behavior OF tb_sram_62256 IS
+
+constant address_size : integer := 8; -- 2;
+constant data_size : integer := 8; -- 2;
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT sram_62256
+GENERIC(
+address_size : integer := address_size;
+data_size : integer := data_size
+);
+PORT(
+i_ceb : IN std_logic;
+i_web : IN std_logic;
+i_oeb : IN std_logic;
+i_address : IN std_logic_vector(address_size-1 downto 0);
+i_data : in STD_LOGIC_VECTOR (data_size-1 downto 0);
+o_data : out STD_LOGIC_VECTOR (data_size-1 downto 0)
+);
+END COMPONENT;
+
+--Inputs
+signal i_ceb : std_logic := '1';
+signal i_web : std_logic := '1';
+signal i_oeb : std_logic := '1';
+signal i_address : std_logic_vector(address_size-1 downto 0) := (others => '0');
+
+--BiDirs
+signal i_data : std_logic_vector(data_size-1 downto 0) := (others => '0');
+signal o_data : std_logic_vector(data_size-1 downto 0);
+
+-- No clocks detected in port list. Replace below with
+-- appropriate port name
+constant clock_period : time := 100 ns;
+signal clock : std_logic := '0';
+
+procedure rd_data(
+address : in std_logic_vector(address_size-1 downto 0);
+signal i_address : out std_logic_vector(address_size-1 downto 0);
+signal i_ceb : out std_logic;
+signal i_web : out std_logic;
+signal i_oeb : out std_logic
+) is
+begin
+ wait for 10*clock_period;
+ i_ceb <= '0';
+ i_address <= address;
+ wait for 01*clock_period;
+ i_web <= '1';
+ i_oeb <= '0';
+ wait for 01*clock_period;
+ i_web <= '1';
+ i_oeb <= '1';
+ wait for 02*clock_period;
+ i_ceb <= '1';
+end procedure;
+
+procedure wr_data(
+address : in std_logic_vector(address_size-1 downto 0);
+data : in std_logic_vector(data_size-1 downto 0);
+signal i_address : out std_logic_vector(address_size-1 downto 0);
+signal i_data : out std_logic_vector(data_size-1 downto 0);
+signal i_ceb : out std_logic;
+signal i_web : out std_logic;
+signal i_oeb : out std_logic
+) is
+begin
+ wait for 10*clock_period;
+ i_ceb <= '0';
+ i_address <= address;
+ i_data <= data;
+ wait for 01*clock_period;
+ i_web <= '0';
+ i_oeb <= '1';
+ wait for 01*clock_period;
+ i_web <= '1';
+ i_oeb <= '1';
+ wait for 02*clock_period;
+ i_ceb <= '1';
+end procedure;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: sram_62256
+GENERIC MAP (
+address_size => address_size,
+data_size => data_size
+)
+PORT MAP (
+i_ceb => i_ceb,
+i_web => i_web,
+i_oeb => i_oeb,
+i_address => i_address,
+i_data => i_data,
+o_data => o_data
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- insert stimulus here
+wait for clock_period;
+-- XXX address reverse order
+-- XXX write
+l0 : for i in 0 to 2**address_size-1 loop
+wr_data(std_logic_vector(to_unsigned(i,address_size)),std_logic_vector(to_unsigned(i,data_size)),i_address,i_data,i_ceb,i_web,i_oeb);
+end loop l0;
+
+wait for clock_period;
+i_data <= (others => 'Z');
+wait for clock_period;
+
+-- XXX rw1
+l1 : for i in 0 to 2**address_size-1 loop
+rd_data(std_logic_vector(to_unsigned(i,address_size)),i_address,i_ceb,i_web,i_oeb);
+wait for clock_period; -- XXX wait for data
+assert (o_data=std_logic_vector(to_unsigned(i,data_size))) report "Error on " & integer'image(i);
+end loop l1;
+
+wait for clock_period;
+i_data <= (others => 'Z');
+wait for clock_period;
+
+-- XXX rw2
+l3 : for i in 0 to 2**address_size-1 loop
+wr_data(std_logic_vector(to_unsigned(i,address_size)),std_logic_vector(to_unsigned(i,data_size)),i_address,i_data,i_ceb,i_web,i_oeb);
+wait for clock_period;
+i_data <= (others => 'Z');
+rd_data(std_logic_vector(to_unsigned(i,address_size)),i_address,i_ceb,i_web,i_oeb);
+wait for clock_period; -- XXX wait for data
+assert (o_data=std_logic_vector(to_unsigned(i,data_size))) report "Error on " & integer'image(i);
+end loop l3;
+
+assert (false) report "end test" severity failure;
+
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_sram_row.vhd b/vhdl_primitive/tb_sram_row.vhd
new file mode 100755
index 0000000..557568f
--- /dev/null
+++ b/vhdl_primitive/tb_sram_row.vhd
@@ -0,0 +1,199 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:18:54 05/01/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_sram_row.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: sram_row
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_sram_row IS
+END tb_sram_row;
+
+ARCHITECTURE behavior OF tb_sram_row IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT sram_row
+PORT(
+i_we : IN std_logic;
+i_oe : IN std_logic;
+i_address_col : IN std_logic_vector(3 downto 0);
+i_bit : IN std_logic;
+o_bit : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_tristate_input : std_logic := '0';
+signal i_tristate_output : std_logic := '0';
+signal i_address_col : std_logic_vector(3 downto 0) := (others => '0');
+signal i_bit : std_logic := '0';
+
+--Outputs
+signal o_bit : std_logic;
+
+constant clock_period : time := 10 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: sram_row PORT MAP (
+i_we => i_tristate_input,
+i_oe => i_tristate_output,
+i_address_col => i_address_col,
+i_bit => i_bit,
+o_bit => o_bit
+);
+
+-- Stimulus process
+stim_proc: process
+begin
+-- insert stimulus here
+-- write
+i_tristate_input <= '1';
+i_address_col <= x"0";
+i_bit <= '1';
+wait for clock_period;
+i_tristate_input <= '0';
+wait for clock_period;
+
+i_tristate_input <= '1';
+i_address_col <= x"1";
+i_bit <= '0';
+wait for clock_period;
+i_tristate_input <= '0';
+wait for clock_period;
+
+i_tristate_input <= '1';
+i_address_col <= x"2";
+i_bit <= '1';
+wait for clock_period;
+i_tristate_input <= '0';
+wait for clock_period;
+
+i_tristate_input <= '1';
+i_address_col <= x"3";
+i_bit <= '0';
+wait for clock_period;
+i_tristate_input <= '0';
+wait for clock_period;
+
+i_tristate_input <= '1';
+i_address_col <= x"4";
+i_bit <= '1';
+wait for clock_period;
+i_tristate_input <= '0';
+wait for clock_period;
+
+i_tristate_input <= '1';
+i_address_col <= x"5";
+i_bit <= '0';
+wait for clock_period;
+i_tristate_input <= '0';
+wait for clock_period;
+
+i_tristate_input <= '1';
+i_address_col <= x"6";
+i_bit <= '1';
+wait for clock_period;
+i_tristate_input <= '0';
+wait for clock_period;
+
+i_tristate_input <= '1';
+i_address_col <= x"7";
+i_bit <= '0';
+wait for clock_period;
+i_tristate_input <= '0';
+wait for clock_period;
+
+i_tristate_input <= '1';
+i_address_col <= x"8";
+i_bit <= '1';
+wait for clock_period;
+i_tristate_input <= '0';
+wait for clock_period;
+
+-- read
+i_tristate_output <= '1';
+i_address_col <= x"0";
+wait for clock_period;
+i_tristate_output <= '0';
+wait for clock_period;
+
+i_tristate_output <= '1';
+i_address_col <= x"1";
+wait for clock_period;
+i_tristate_output <= '0';
+wait for clock_period;
+
+i_tristate_output <= '1';
+i_address_col <= x"2";
+wait for clock_period;
+i_tristate_output <= '0';
+wait for clock_period;
+
+i_tristate_output <= '1';
+i_address_col <= x"3";
+wait for clock_period;
+i_tristate_output <= '0';
+wait for clock_period;
+
+i_tristate_output <= '1';
+i_address_col <= x"4";
+wait for clock_period;
+i_tristate_output <= '0';
+wait for clock_period;
+
+i_tristate_output <= '1';
+i_address_col <= x"5";
+wait for clock_period;
+i_tristate_output <= '0';
+wait for clock_period;
+
+i_tristate_output <= '1';
+i_address_col <= x"6";
+wait for clock_period;
+i_tristate_output <= '0';
+wait for clock_period;
+
+i_tristate_output <= '1';
+i_address_col <= x"7";
+wait for clock_period;
+i_tristate_output <= '0';
+wait for clock_period;
+
+i_tristate_output <= '1';
+i_address_col <= x"8";
+wait for clock_period;
+i_tristate_output <= '0';
+wait for clock_period;
+
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_succesive_approximation_register.vhd b/vhdl_primitive/tb_succesive_approximation_register.vhd
new file mode 100755
index 0000000..fc9f909
--- /dev/null
+++ b/vhdl_primitive/tb_succesive_approximation_register.vhd
@@ -0,0 +1,112 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:41:51 04/18/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_succesive_approximation_register.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: succesive_approximation_register
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_succesive_approximation_register IS
+END tb_succesive_approximation_register;
+
+ARCHITECTURE behavior OF tb_succesive_approximation_register IS
+
+constant N : integer := 16;
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT succesive_approximation_register
+GENERIC(
+n : INTEGER := N
+);
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+i_select : IN std_logic;
+o_q : OUT std_logic_vector(N-1 downto 0);
+o_end : INOUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+signal i_select : std_logic := '0';
+
+--BiDirs
+signal o_end : std_logic;
+
+--Outputs
+signal o_q : std_logic_vector(N-1 downto 0);
+
+-- Clock period definitions
+constant i_clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: succesive_approximation_register
+GENERIC MAP (
+n => N
+)
+PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+i_select => i_select,
+o_q => o_q,
+o_end => o_end
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+i_reset <= '0';
+wait for i_clock_period;
+i_reset <= '1';
+-- insert stimulus here
+l0 : for i in 0 to 2**N-1 loop
+--wait for i_clock_period*17; -- XXX must be less than (2**N)
+--i_select <= '1';
+--o_end <= '0';
+--wait for i_clock_period;
+--i_select <= '0';
+--o_end <= '0';
+end loop l0;
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_tab31.vhd b/vhdl_primitive/tb_tab31.vhd
new file mode 100644
index 0000000..4ed43db
--- /dev/null
+++ b/vhdl_primitive/tb_tab31.vhd
@@ -0,0 +1,99 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 10:34:45 06/05/2023
+-- Design Name: BCD and Ex-3 decode from 0-9
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_tab31.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: tab31
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- bit_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_tab31 IS
+END tb_tab31;
+
+ARCHITECTURE behavior OF tb_tab31 IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT tab31
+PORT(
+Decimal_Digit : IN bit_vector(3 downto 0);
+BCD8421_Codes : OUT bit_vector(3 downto 0);
+Excess3_Codes : OUT bit_vector(3 downto 0)
+);
+END COMPONENT;
+
+--Inputs
+signal Decimal_Digit : bit_vector(3 downto 0) := (others => '0');
+
+--Outputs
+signal BCD8421_Codes : bit_vector(3 downto 0);
+signal Excess3_Codes : bit_vector(3 downto 0);
+
+signal clock : bit := '0';
+constant clock_period : time := 10 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: tab31 PORT MAP (
+Decimal_Digit => Decimal_Digit,
+BCD8421_Codes => BCD8421_Codes,
+Excess3_Codes => Excess3_Codes
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+Decimal_Digit <= "1111",
+"1001" after 10 ns,
+"1000" after 20 ns,
+"0111" after 30 ns,
+"0110" after 40 ns,
+"0101" after 50 ns,
+"0100" after 60 ns,
+"0011" after 70 ns,
+"0010" after 80 ns,
+"0001" after 90 ns,
+"0000" after 100 ns,
+"1111" after 110 ns;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+wait for 200 ns;
+-- insert stimulus here
+report "tb done" severity failure;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_test_debouncebutton_lcddisplay.vhd b/vhdl_primitive/tb_test_debouncebutton_lcddisplay.vhd
new file mode 100755
index 0000000..7561b61
--- /dev/null
+++ b/vhdl_primitive/tb_test_debouncebutton_lcddisplay.vhd
@@ -0,0 +1,109 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:12:11 07/09/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_test_debouncebutton_lcddisplay.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: test_debouncebutton_lcddisplay
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE work.p_globals.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_test_debouncebutton_lcddisplay IS
+END tb_test_debouncebutton_lcddisplay;
+
+ARCHITECTURE behavior OF tb_test_debouncebutton_lcddisplay IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT test_debouncebutton_lcddisplay
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+i_up : IN std_logic;
+i_down : IN std_logic;
+o_seg : OUT std_logic_vector(6 downto 0);
+o_an : OUT std_logic_vector(3 downto 0)
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+signal i_up : std_logic := '0';
+signal i_down : std_logic := '0';
+
+--Outputs
+signal o_seg : std_logic_vector(6 downto 0);
+signal o_an : std_logic_vector(3 downto 0);
+
+-- Clock period definitions
+constant i_clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: test_debouncebutton_lcddisplay PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+i_up => i_up,
+i_down => i_down,
+o_seg => o_seg,
+o_an => o_an
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+i_reset <= '1';
+wait for 100 ns;
+i_reset <= '0';
+wait for i_clock_period*10;
+
+-- insert stimulus here
+i_up <= '1';
+wait for G_DEBOUNCE_MS*1000*1000*1 ns;
+i_up <= '0';
+wait for i_clock_period;
+i_down <= '1';
+wait for G_DEBOUNCE_MS*1000*1000*1 ns;
+i_down <= '0';
+wait for i_clock_period;
+
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_test_oscilator_socket.vhd b/vhdl_primitive/tb_test_oscilator_socket.vhd
new file mode 100644
index 0000000..5a38f4f
--- /dev/null
+++ b/vhdl_primitive/tb_test_oscilator_socket.vhd
@@ -0,0 +1,94 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:34:52 07/02/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_test_oscilator_socket.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: test_oscilator_socket
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_test_oscilator_socket IS
+END tb_test_oscilator_socket;
+
+ARCHITECTURE behavior OF tb_test_oscilator_socket IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT test_oscilator_socket
+PORT(
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+o_led : OUT std_logic
+);
+END COMPONENT;
+
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+
+--Outputs
+signal o_led : std_logic;
+
+-- Clock period definitions
+constant i_clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: test_oscilator_socket PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+o_led => o_led
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+i_reset <= '1';
+wait for 100 ns;
+i_reset <= '0';
+wait for i_clock_period*10;
+
+-- insert stimulus here
+
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_top_dpc.vhd b/vhdl_primitive/tb_top_dpc.vhd
new file mode 100755
index 0000000..3e0f899
--- /dev/null
+++ b/vhdl_primitive/tb_top_dpc.vhd
@@ -0,0 +1,97 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:14:52 08/24/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_top_dpc.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top_dpc
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_top_dpc IS
+END tb_top_dpc;
+
+ARCHITECTURE behavior OF tb_top_dpc IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT top_dpc
+GENERIC (
+n : integer := 50_000_000
+);
+PORT (
+i_clock : IN std_logic;
+i_reset : IN std_logic;
+o_led : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_reset : std_logic := '0';
+
+--Outputs
+signal o_led : std_logic;
+
+-- Clock period definitions
+constant i_clock_period : time := 10 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: top_dpc
+GENERIC MAP (
+n => 1_000
+)
+PORT MAP (
+i_clock => i_clock,
+i_reset => i_reset,
+o_led => o_led
+);
+
+-- Clock process definitions
+i_clock_process :process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+i_reset <= '1';
+wait for 100 ns;
+i_reset <= '0';
+wait for i_clock_period*10;
+-- insert stimulus here
+
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_top_ripcnt.vhd b/vhdl_primitive/tb_top_ripcnt.vhd
new file mode 100755
index 0000000..a4423d1
--- /dev/null
+++ b/vhdl_primitive/tb_top_ripcnt.vhd
@@ -0,0 +1,94 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 23:21:53 06/25/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_top_ripcnt.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: top_ripple_counter
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_top_ripcnt IS
+END tb_top_ripcnt;
+
+ARCHITECTURE behavior OF tb_top_ripcnt IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT top_ripple_counter
+ PORT(
+ i_clock : IN std_logic;
+ i_reset : IN std_logic;
+ o_led : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal i_clock : std_logic := '0';
+ signal i_reset : std_logic := '0';
+
+ --BiDirs
+ signal o_led : std_logic;
+
+ -- Clock period definitions
+ constant i_clock_period : time := 10 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: top_ripple_counter PORT MAP (
+ i_clock => i_clock,
+ i_reset => i_reset,
+ o_led => o_led
+ );
+
+ -- Clock process definitions
+ i_clock_process :process
+ begin
+ i_clock <= '0';
+ wait for i_clock_period/2;
+ i_clock <= '1';
+ wait for i_clock_period/2;
+ end process;
+
+i_reset <= '1', '0' after i_clock_period;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+
+ wait for i_clock_period*10;
+
+ -- insert stimulus here
+
+ wait;
+ end process;
+
+END;
diff --git a/vhdl_primitive/tb_transmission_gate.vhd b/vhdl_primitive/tb_transmission_gate.vhd
new file mode 100755
index 0000000..82a34df
--- /dev/null
+++ b/vhdl_primitive/tb_transmission_gate.vhd
@@ -0,0 +1,112 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:21:54 07/01/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_transmission_gate.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: transmission_gate
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_transmission_gate IS
+END tb_transmission_gate;
+
+ARCHITECTURE behavior OF tb_transmission_gate IS
+
+COMPONENT transmission_gate
+PORT(
+ io_a : inout std_logic;
+ io_b : inout std_logic;
+ i_s : in std_logic
+);
+END COMPONENT;
+
+signal a : std_logic;
+signal b : std_logic;
+signal s : std_logic;
+
+constant clock_period : time := 100 ns;
+signal clock : std_logic;
+
+signal mux0 : std_logic;
+
+BEGIN
+
+uut: transmission_gate PORT MAP (
+io_a => a,
+io_b => b,
+i_s => s
+);
+
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+with s select mux0 <=
+a when '1',
+b when '0',
+'Z' when others;
+
+-- Stimulus process
+stim_proc: process
+begin
+wait for 100 ns;
+
+s <= '1';
+a <= '0';
+wait for 10*clock_period;
+s <= '1';
+a <= '1';
+wait for 10*clock_period;
+s <= '1';
+b <= '0';
+wait for 10*clock_period;
+s <= '1';
+b <= '1';
+wait for 10*clock_period;
+
+s <= '0';
+a <= '0';
+wait for 10*clock_period;
+s <= '0';
+a <= '1';
+wait for 10*clock_period;
+s <= '0';
+b <= '0';
+wait for 10*clock_period;
+s <= '0';
+b <= '1';
+wait for 10*clock_period;
+
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_universal_function.vhd b/vhdl_primitive/tb_universal_function.vhd
new file mode 100755
index 0000000..2bc664b
--- /dev/null
+++ b/vhdl_primitive/tb_universal_function.vhd
@@ -0,0 +1,131 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:46:06 05/08/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_universal_function.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: universal_function
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_universal_function IS
+END tb_universal_function;
+
+ARCHITECTURE behavior OF tb_universal_function IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT universal_function
+PORT(
+i_x1 : IN std_logic;
+i_x2 : IN std_logic;
+o_x1b : OUT std_logic;
+o_x2b : OUT std_logic;
+o_x1b_or_x2b : OUT std_logic;
+o_x1_and_x2 : OUT std_logic;
+o_x1_or_x2b : OUT std_logic;
+o_x1b_and_x2 : OUT std_logic;
+o_x1_xor_x2 : OUT std_logic;
+o_x1_eq_x2 : OUT std_logic;
+o_x1b_or_x2 : OUT std_logic;
+o_x1_and_x2b : OUT std_logic;
+o_x1_or_x2 : OUT std_logic;
+o_x1b_and_x2b : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_x1 : std_logic := '0';
+signal i_x2 : std_logic := '0';
+
+--Outputs
+signal o_x1b : std_logic;
+signal o_x2b : std_logic;
+signal o_x1b_or_x2b : std_logic;
+signal o_x1_and_x2 : std_logic;
+signal o_x1_or_x2b : std_logic;
+signal o_x1b_and_x2 : std_logic;
+signal o_x1_xor_x2 : std_logic;
+signal o_x1_eq_x2 : std_logic;
+signal o_x1b_or_x2 : std_logic;
+signal o_x1_and_x2b : std_logic;
+signal o_x1_or_x2 : std_logic;
+signal o_x1b_and_x2b : std_logic;
+
+constant clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: universal_function PORT MAP (
+i_x1 => i_x1,
+i_x2 => i_x2,
+o_x1b => o_x1b,
+o_x2b => o_x2b,
+o_x1b_or_x2b => o_x1b_or_x2b,
+o_x1_and_x2 => o_x1_and_x2,
+o_x1_or_x2b => o_x1_or_x2b,
+o_x1b_and_x2 => o_x1b_and_x2,
+o_x1_xor_x2 => o_x1_xor_x2,
+o_x1_eq_x2 => o_x1_eq_x2,
+o_x1b_or_x2 => o_x1b_or_x2,
+o_x1_and_x2b => o_x1_and_x2b,
+o_x1_or_x2 => o_x1_or_x2,
+o_x1b_and_x2b => o_x1b_and_x2b
+);
+
+-- Stimulus process
+stim_proc: process
+ constant N : integer := 4;
+ type input_array is array(0 to N-1) of std_logic_vector(1 downto 0);
+ variable xi : input_array := ("00","01","10","11");
+begin
+ wait for clock_period*10;
+ -- insert stimulus here
+ l0 : for i in 0 to N-1 loop
+ i_x1 <= xi(i)(0);
+ i_x2 <= xi(i)(1);
+
+ assert(o_x1b = ( not i_x1 ) ) report "fail on x1b" severity warning;
+ assert(o_x2b = ( not i_x2 ) ) report "fail on x2b" severity warning;
+
+ assert(o_x1b_or_x2b = ( not i_x1 or not i_x2) ) report "fail on x1b or x2b" severity warning;
+ assert(o_x1_and_x2 = ( i_x1 and i_x2) ) report "fail on x1 and x2" severity warning;
+ assert(o_x1_or_x2b = ( i_x1 or not i_x2) ) report "fail on x1 or x2b" severity warning;
+ assert(o_x1b_and_x2 = ( not i_x1 and i_x2) ) report "fail on x1b and x2" severity warning;
+ assert(o_x1_xor_x2 = ( i_x1 xor i_x2) ) report "fail on x1 xor x2" severity warning;
+ assert(o_x1_eq_x2 = ( i_x1 xnor i_x2) ) report "fail on x1 xnor x2" severity warning;
+ assert(o_x1b_or_x2 = ( not i_x1 or i_x2) ) report "fail on x1b or x2" severity warning;
+ assert(o_x1_and_x2b = ( i_x1 and not i_x2) ) report "fail on x1 and x2b" severity warning;
+ assert(o_x1_or_x2 = ( i_x1 or i_x2) ) report "fail on x1 or x2" severity warning;
+ assert(o_x1b_and_x2b = ( not i_x1 and not i_x2) ) report "fail on x1b and x2b" severity warning;
+
+ wait for clock_period;
+ end loop l0;
+ wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/tb_x3_nand_x1_nor.vhd b/vhdl_primitive/tb_x3_nand_x1_nor.vhd
new file mode 100755
index 0000000..ff7836e
--- /dev/null
+++ b/vhdl_primitive/tb_x3_nand_x1_nor.vhd
@@ -0,0 +1,107 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:33:31 04/19/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_x3_nand_x1_nor.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: x3_nand_x1_nor
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_x3_nand_x1_nor IS
+END tb_x3_nand_x1_nor;
+
+ARCHITECTURE behavior OF tb_x3_nand_x1_nor IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+COMPONENT x3_nand_x1_nor
+PORT(
+A : IN std_logic;
+B : IN std_logic;
+Q : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal A : std_logic := '0';
+signal B : std_logic := '0';
+
+--Outputs
+signal Q : std_logic;
+
+constant clock_period : time := 20 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: x3_nand_x1_nor PORT MAP (
+A => A,
+B => B,
+Q => Q
+);
+
+-- Stimulus process
+stim_proc: process
+begin
+-- hold reset state for 100 ns.
+wait for 100 ns;
+wait for clock_period*10;
+-- insert stimulus here
+A <= '1';
+B <= '1';
+wait for clock_period;
+A <= '0';
+B <= '1';
+wait for clock_period;
+A <= '1';
+B <= '0';
+wait for clock_period;
+A <= '0';
+B <= '0';
+wait for clock_period;
+A <= '1';
+B <= '1';
+wait for clock_period;
+A <= '1';
+B <= '1';
+wait for clock_period;
+A <= '0';
+B <= '1';
+wait for clock_period;
+A <= '1';
+B <= '0';
+wait for clock_period;
+A <= '0';
+B <= '0';
+wait for clock_period;
+A <= '1';
+B <= '1';
+wait for clock_period;
+wait;
+end process;
+
+END;
diff --git a/vhdl_primitive/test_debouncebutton_lcddisplay.vhd b/vhdl_primitive/test_debouncebutton_lcddisplay.vhd
new file mode 100755
index 0000000..f9934ad
--- /dev/null
+++ b/vhdl_primitive/test_debouncebutton_lcddisplay.vhd
@@ -0,0 +1,159 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:11:25 07/06/2021
+-- Design Name:
+-- Module Name: test_debouncebutton_lcddisplay - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.p_globals.all;
+use work.p_lcd_display.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity test_debouncebutton_lcddisplay is
+port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_up : in std_logic;
+ i_down : in std_logic;
+ o_seg : out std_logic_vector(G_LCDSegment-1 downto 0);
+ o_an : out std_logic_vector(G_LCDAnode-1 downto 0)
+);
+end test_debouncebutton_lcddisplay;
+
+architecture Behavioral of test_debouncebutton_lcddisplay is
+
+ component new_debounce is
+ generic ( -- ripplecounter N bits (RC_N=N+1,RC_MAX=2**N)
+ G_RC_N : integer := 5;
+ G_RC_MAX : integer := 16
+ );
+ port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_b : in std_logic;
+ o_db : out std_logic
+ );
+ end component new_debounce;
+
+ component lcd_display is
+ Generic (
+ G_BOARD_CLOCK : integer := 1;
+ LCDClockDivider : integer := 1
+ );
+ Port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ i_LCDChar : LCDHex;
+ o_anode : out std_logic_vector(G_LCDAnode-1 downto 0);
+ o_segment : out std_logic_vector(G_LCDSegment-1 downto 0)
+ );
+ end component lcd_display;
+
+ constant G_RC_N : integer := G_DEBOUNCE_MS_BITS;
+ constant G_RC_MAX : integer := G_DEBOUNCE_MS_COUNT;
+ constant BITS : integer := 16;
+ signal LCDChar : LCDHex;
+ signal db_up,db_down : std_logic;
+ signal counter : integer range 0 to 2**BITS-1 := 0;
+ signal increment : integer range -1 to 1;
+ signal output : std_logic_vector(BITS-1 downto 0);
+ signal counter_enable : std_logic;
+ signal db_up_reset,db_down_reset : std_logic;
+
+begin
+
+ p0 : process (i_clock,i_reset,db_up,db_down,counter_enable) is
+ begin
+ if (i_reset = '1') then
+ counter <= 0;
+ counter_enable <= '0';
+ db_up_reset <= '1';
+ db_down_reset <= '1';
+ elsif (rising_edge(i_clock)) then
+ if (db_up = '1') then
+ increment <= 1;
+ counter_enable <= '1';
+ db_up_reset <= '1';
+ elsif (db_down = '1') then
+ increment <= -1;
+ counter_enable <= '1';
+ db_down_reset <= '1';
+ else
+ increment <= 0;
+ counter_enable <= '0';
+ db_up_reset <= '0';
+ db_down_reset <= '0';
+ end if;
+ if (counter_enable = '1') then
+ if (counter = 2**BITS-1) then
+ counter <= 0;
+ elsif (counter = -1) then
+ counter <= 2**BITS-1;
+ end if;
+ counter <= counter + increment;
+ end if;
+ end if;
+ end process p0;
+ output <= std_logic_vector(to_unsigned(counter,BITS));
+ LCDChar <= (output(3 downto 0),output(7 downto 4),output(11 downto 8),output(15 downto 12));
+
+ db_entity_up : new_debounce
+ generic map (
+ G_RC_N => G_RC_N,
+ G_RC_MAX => G_RC_MAX
+ )
+ port map (
+ i_clock => i_clock,
+ i_reset => db_up_reset,
+ i_b => i_up,
+ o_db => db_up
+ );
+
+ db_entity_down : new_debounce
+ generic map (
+ G_RC_N => G_RC_N,
+ G_RC_MAX => G_RC_MAX
+ )
+ port map (
+ i_clock => i_clock,
+ i_reset => db_down_reset,
+ i_b => i_down,
+ o_db => db_down
+ );
+
+ lcddisplay_entity : lcd_display
+ Generic Map (
+ G_BOARD_CLOCK => G_BOARD_CLOCK,
+ LCDClockDivider => G_LCDClockDivider
+ )
+ Port Map (
+ i_clock => i_clock,
+ i_reset => i_reset,
+ i_LCDChar => LCDChar,
+ o_anode => o_an,
+ o_segment => o_seg
+ );
+
+end Behavioral;
diff --git a/vhdl_primitive/test_oscilator_socket.vhd b/vhdl_primitive/test_oscilator_socket.vhd
new file mode 100644
index 0000000..b889556
--- /dev/null
+++ b/vhdl_primitive/test_oscilator_socket.vhd
@@ -0,0 +1,66 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:25:20 07/02/2021
+-- Design Name:
+-- Module Name: test_oscilator_socket - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity test_oscilator_socket is
+port (
+i_clock : in std_logic;
+i_reset : in std_logic;
+o_led : out std_logic
+);
+end test_oscilator_socket;
+
+architecture Behavioral of test_oscilator_socket is
+
+component counter_ping is
+generic (
+ max : integer := 1
+);
+port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ o_ping : out std_logic
+);
+end component counter_ping;
+
+begin
+
+u0 : counter_ping
+generic map (
+-- max => 50_000_000
+ max => 8_000_000
+)
+port map (
+ i_clock => i_clock,
+ i_reset => i_reset,
+ o_ping => o_led
+);
+
+end Behavioral;
diff --git a/vhdl_primitive/top_dpc.vhd b/vhdl_primitive/top_dpc.vhd
new file mode 100755
index 0000000..ed5e7ee
--- /dev/null
+++ b/vhdl_primitive/top_dpc.vhd
@@ -0,0 +1,146 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:08:36 08/23/2021
+-- Design Name:
+-- Module Name: top_dpc - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top_dpc is
+generic (
+n : integer := 50_000_000
+);
+port (
+i_clock : in std_logic;
+i_reset : in std_logic;
+o_led : out std_logic
+);
+end top_dpc;
+
+architecture Behavioral of top_dpc is
+
+component delayed_programmable_circuit is
+port (
+i_reg1 : in std_logic;
+i_reg2 : in std_logic;
+i_reg3 : in std_logic;
+i_reg4 : in std_logic;
+i_reg5 : in std_logic;
+i_reg6 : in std_logic;
+i_reg7 : in std_logic;
+i_input : in std_logic;
+o_output : out std_logic
+);
+end component delayed_programmable_circuit;
+
+signal reg : std_logic_vector(7 downto 1);
+
+type states is (idle,start,
+reg1,reg2,reg3,reg4,reg5,reg6,reg7,reg8
+);
+signal state : states;
+
+signal clock_divider : std_logic;
+
+begin
+
+p_clockdivider : process (i_clock,i_reset) is
+ constant C_CD : integer := n;
+ variable count : integer range 0 to C_CD - 1;
+begin
+ if (i_reset = '1') then
+ clock_divider <= '0';
+ count := 0;
+ elsif (rising_edge(i_clock)) then
+ if (count = C_CD - 1) then
+ clock_divider <= '1';
+ count := 0;
+ else
+ clock_divider <= '0';
+ count := count + 1;
+ end if;
+ end if;
+end process p_clockdivider;
+
+p0 : process (clock_divider,i_reset) is
+begin
+ if (i_reset = '1') then
+ state <= idle;
+ reg <= (others => '0');
+ elsif (rising_edge(clock_divider)) then
+ case (state) is
+ when idle =>
+ state <= start;
+ reg <= "1111111";
+ when start =>
+ state <= reg1;
+ reg <= "0000000";
+ when reg1 =>
+ state <= reg2;
+ reg <= "0000001";
+ when reg2 =>
+ state <= reg3;
+ reg <= "0000010";
+ when reg3 =>
+ state <= reg4;
+ reg <= "0000100";
+ when reg4 =>
+ state <= reg5;
+ reg <= "0001000";
+ when reg5 =>
+ state <= reg6;
+ reg <= "0010000";
+ when reg6 =>
+ state <= reg7;
+ reg <= "0100000";
+ when reg7 =>
+ state <= reg8;
+ reg <= "1000000";
+ when reg8 =>
+ state <= idle;
+ reg <= "0000000";
+ when others =>
+ state <= idle;
+ reg <= "0000000";
+ end case;
+ end if;
+end process p0;
+
+entity_dpc : delayed_programmable_circuit
+port map (
+i_reg1 => reg(1),
+i_reg2 => reg(2),
+i_reg3 => reg(3),
+i_reg4 => reg(4),
+i_reg5 => reg(5),
+i_reg6 => reg(6),
+i_reg7 => reg(7),
+i_input => clock_divider,
+o_output => o_led
+);
+
+end Behavioral;
+
diff --git a/vhdl_primitive/top_ripple_counter.vhd b/vhdl_primitive/top_ripple_counter.vhd
new file mode 100755
index 0000000..1d65e0c
--- /dev/null
+++ b/vhdl_primitive/top_ripple_counter.vhd
@@ -0,0 +1,131 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:12:43 06/25/2021
+-- Design Name:
+-- Module Name: top_ripple_counter - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top_ripple_counter is
+port (
+ i_clock : in std_logic;
+ i_reset : in std_logic;
+ o_led : out std_logic
+);
+end top_ripple_counter;
+
+architecture Behavioral of top_ripple_counter is
+
+---- XXX log2(MAX)-1/+1? for syn
+ -- XXX for this settings see like led toogle after 1s
+-- constant N : integer := 26; -- XXX 0-25 ff jk regs
+-- constant MAX : integer := 49_999_999; -- XXX for this on 0-50*10^6-1 hz
+
+---- XXX log2(MAX)-1/+1? for sim
+ constant N : integer := 8;
+ constant MAX : integer := 130;
+
+ component ripple_counter is
+ Generic (
+ N : integer := 12;
+ MAX : integer := 571
+ );
+ Port (
+ i_clock : in std_logic;
+ i_cpb : in std_logic;
+ i_mrb : in std_logic;
+ i_ud : in std_logic;
+ o_q : inout std_logic_vector(N-1 downto 0);
+ o_ping : out std_logic
+ );
+ end component ripple_counter;
+
+ signal i_cpb : std_logic;
+ signal i_mrb : std_logic;
+ signal o_q : std_logic_vector(N-1 downto 0);
+ signal o_ping : std_logic;
+ signal led : std_logic;
+
+ type states is (idle,start);
+ signal state : states;
+
+ component FF_JK is
+ port (
+ i_r:in STD_LOGIC;
+ J,K,C:in STD_LOGIC;
+ Q1:inout STD_LOGIC;
+ Q2:inout STD_LOGIC
+ );
+ end component FF_JK;
+
+begin
+
+ o_led <= led;
+
+ p0 : process (i_clock,i_reset) is
+ begin
+ if (i_reset = '1') then
+ state <= idle;
+ elsif (rising_edge(i_clock)) then
+ case state is
+ when idle =>
+ state <= start;
+ i_mrb <= '1';
+ i_cpb <= '0';
+ when start =>
+ state <= start;
+ i_mrb <= '0';
+ i_cpb <= '1';
+ end case;
+ end if;
+ end process p0;
+
+ u1 : FF_JK
+ port map (
+ i_r => i_mrb,
+ J => o_ping,
+ K => o_ping,
+ C => not i_clock,
+ Q1 => led,
+ Q2 => open
+ );
+
+ u0 : ripple_counter
+ generic map (
+ N => N,
+ MAX => MAX
+ )
+ port map (
+ i_clock => i_clock,
+ i_cpb => i_cpb,
+ i_mrb => i_mrb,
+ i_ud => '1',
+ o_q => o_q,
+ o_ping => o_ping
+ );
+
+end Behavioral;
+
diff --git a/vhdl_primitive/transmission_gate.vhd b/vhdl_primitive/transmission_gate.vhd
new file mode 100755
index 0000000..b6502a3
--- /dev/null
+++ b/vhdl_primitive/transmission_gate.vhd
@@ -0,0 +1,79 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:20:23 07/01/2021
+-- Design Name:
+-- Module Name: transmission_gate - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity transmission_gate is
+port (
+ io_a : inout std_logic;
+ io_b : inout std_logic;
+ i_s : in std_logic
+);
+end transmission_gate;
+
+architecture Behavioral of transmission_gate is
+
+ signal s,sb,t1,t2 : std_logic;
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 1 ns
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+
+begin
+
+--IOBUF_inst : IOBUF
+--generic map (
+--DRIVE => 12,
+--IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"12"
+--IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"6"
+--IOSTANDARD => "DEFAULT",
+--SLEW => "SLOW")
+--port map (
+--O => O, -- Buffer output
+--IO => IO, -- Buffer inout port (connect directly to top-level port)
+--I => I, -- Buffer input
+--T => T -- 3-state enable input, high=input, low=output
+--);
+
+s <= i_s;
+GNOT : GATE_NOT GENERIC MAP (1 ns) PORT MAP (A=>s,B=>sb);
+
+IOBUF_inst1 : IOBUF
+port map (O=>t1,IO=>io_a,I=>t2,T=>s);
+
+IOBUF_inst2 : IOBUF
+port map (O=>t2,IO=>io_b,I=>t1,T=>sb);
+
+end Behavioral;
diff --git a/vhdl_primitive/ulm_cell.vhd b/vhdl_primitive/ulm_cell.vhd
new file mode 100755
index 0000000..1b3bab8
--- /dev/null
+++ b/vhdl_primitive/ulm_cell.vhd
@@ -0,0 +1,48 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:33:12 05/08/2021
+-- Design Name:
+-- Module Name: ulm_cell - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ulm_cell is
+Port (
+a,b,c : in std_logic;
+f1,f2 : out std_logic
+);
+end ulm_cell;
+
+architecture Behavioral of ulm_cell is
+ signal s1,s2,s3,s4 : std_logic; -- f=ACb+BC
+begin
+ s1 <= not c;
+ s2 <= s1 nand a;
+ s3 <= c nand b;
+ s4 <= s2 nand s3;
+ f1 <= s4;
+ f2 <= s4;
+end Behavioral;
diff --git a/vhdl_primitive/universal_function.vhd b/vhdl_primitive/universal_function.vhd
new file mode 100755
index 0000000..6d69cb9
--- /dev/null
+++ b/vhdl_primitive/universal_function.vhd
@@ -0,0 +1,80 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:23:10 05/08/2021
+-- Design Name:
+-- Module Name: universal_function - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+-- generate 12 functions from 2
+entity universal_function is
+Port (
+i_x1,i_x2 : in std_logic;
+o_x1b,o_x2b : out std_logic;
+o_x1b_or_x2b : out std_logic;
+o_x1_and_x2 : out std_logic;
+o_x1_or_x2b : out std_logic;
+o_x1b_and_x2 : out std_logic;
+o_x1_xor_x2 : out std_logic;
+o_x1_eq_x2 : out std_logic;
+o_x1b_or_x2 : out std_logic;
+o_x1_and_x2b : out std_logic;
+o_x1_or_x2 : out std_logic;
+o_x1b_and_x2b : out std_logic
+);
+end universal_function;
+
+architecture Behavioral of universal_function is
+ signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14 : std_logic;
+begin
+ -- 3x7400
+ s1 <= i_x1 nand i_x1;
+ s2 <= i_x1;
+ s3 <= i_x2 nand i_x2;
+ s4 <= i_x2;
+ s5 <= s2 nand s4;
+ s6 <= s1 nand s4;
+ s7 <= s2 nand s3;
+ s8 <= s3 nand s1;
+ s14 <= s13 nand s13;
+ s9 <= s5 nand s5;
+ s10 <= s6 nand s6;
+ s13 <= s6 nand s7;
+ s11 <= s7 nand s7;
+ s12 <= s8 nand s8;
+ o_x1b <= s1;
+ o_x2b <= s3;
+ o_x1b_or_x2b <= s5;
+ o_x1_and_x2 <= s9;
+ o_x1_or_x2b <= s6;
+ o_x1b_and_x2 <= s10;
+ o_x1_xor_x2 <= s13;
+ o_x1_eq_x2 <= s14;
+ o_x1b_or_x2 <= s7;
+ o_x1_and_x2b <= s11;
+ o_x1_or_x2 <= s8;
+ o_x1b_and_x2b <= s12;
+end Behavioral;
diff --git a/vhdl_primitive/vhdl_primitive.xise b/vhdl_primitive/vhdl_primitive.xise
new file mode 100755
index 0000000..418e78e
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+++ b/vhdl_primitive/vhdl_primitive.xise
@@ -0,0 +1,884 @@
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diff --git a/vhdl_primitive/x3_nand_x1_nor.vhd b/vhdl_primitive/x3_nand_x1_nor.vhd
new file mode 100755
index 0000000..fafa676
--- /dev/null
+++ b/vhdl_primitive/x3_nand_x1_nor.vhd
@@ -0,0 +1,50 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 10:58:51 04/19/2021
+-- Design Name:
+-- Module Name: x3_nand_x1_nor - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity x3_nand_x1_nor is
+Port (
+A : in STD_LOGIC;
+B : in STD_LOGIC;
+Q : out STD_LOGIC
+);
+end x3_nand_x1_nor;
+
+architecture Behavioral of x3_nand_x1_nor is
+ signal g_nand1,g_nand2,g_nand3,g_nor1 : std_logic; -- XXX 0,1=1
+begin
+ process (A,B) is
+ begin
+ g_nand1 <= A nand B;
+ g_nand2 <= g_nand1 nand A;
+ g_nand3 <= g_nand1 nand B;
+ Q <= g_nand2 nor g_nand3;
+ end process;
+end Behavioral;
diff --git a/weirdboyjim_circuits/DEMUX_12.vhd b/weirdboyjim_circuits/DEMUX_12.vhd
new file mode 100755
index 0000000..34b8910
--- /dev/null
+++ b/weirdboyjim_circuits/DEMUX_12.vhd
@@ -0,0 +1,29 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity DEMUX_12 is
+port (S,A:in STD_LOGIC;B,C:out STD_LOGIC);
+end entity DEMUX_12;
+
+architecture DEMUX_12_BEHAVIORAL_1 of DEMUX_12 is
+component GAND is
+generic (delay_and : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GOR is
+generic (delay_or : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GOR;
+component GN is
+generic (delay_not : time := 0 ns);
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_LUT);
+for all : GOR use entity WORK.GATE_OR(GATE_OR_LUT);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_LUT);
+signal sa : STD_LOGIC;
+begin
+g1: GN port map (S,sa);
+g3: GAND port map (A,S,B);
+g4: GAND port map (A,sa,C);
+end architecture DEMUX_12_BEHAVIORAL_1;
diff --git a/weirdboyjim_circuits/FF_D_DET.vhd b/weirdboyjim_circuits/FF_D_DET.vhd
new file mode 100755
index 0000000..59b719e
--- /dev/null
+++ b/weirdboyjim_circuits/FF_D_DET.vhd
@@ -0,0 +1,114 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FF_D_DUAL_EDGE_TRIGGERED is
+generic (
+delay_not : time := 0 ns;
+delay_and : time := 0 ns;
+delay_or : time := 0 ns;
+delay_nor2 : time := 0 ns;
+delay_nand2 : time := 0 ns;
+delay_nand3 : time := 0 ns
+);
+port (S,R,D,C:in STD_LOGIC;Q:out STD_LOGIC);
+end entity FF_D_DUAL_EDGE_TRIGGERED;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Dual-edge-triggered_D_flip-flop
+architecture Behavioral_D_DET of FF_D_DUAL_EDGE_TRIGGERED is
+component FF_D_PE is
+generic (
+delay_not : time := 0 ns;
+delay_and : time := 0 ns;
+delay_nor2 : time := 0 ns;
+delay_nand2 : time := 0 ns;
+delay_nand3 : time := 0 ns
+);
+port (S,R,C,D:in STD_LOGIC;Q1,Q2:inout STD_LOGIC);
+end component FF_D_PE;
+component MUX_21 is
+port (S,A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component MUX_21;
+component GN is
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : FF_D_PE use entity WORK.FF_D_POSITIVE_EDGE(Behavioral_D_PE);
+for all : MUX_21 use entity WORK.MUX_21(MUX_21_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc: STD_LOGIC;
+signal null_s,null_r : std_logic := '0';
+begin
+g1: GN port map (C,sa);
+g2: FF_D_PE port map (null_s,null_r,sa,D,sb,open);
+g3: FF_D_PE port map (null_s,null_r,C,D,sc,open);
+g4: MUX_21 port map (C,sb,sc,Q);
+end architecture Behavioral_D_DET;
+
+architecture D_DET_LUT of FF_D_DUAL_EDGE_TRIGGERED is
+
+ component FF_D_PE is
+ generic (
+ delay_not : time := 0 ns;
+ delay_and : time := 0 ns;
+ delay_nor2 : time := 0 ns;
+ delay_nand2 : time := 0 ns;
+ delay_nand3 : time := 0 ns
+ );
+ port (S,R,C,D:in STD_LOGIC;Q1,Q2:out STD_LOGIC);
+ end component FF_D_PE;
+-- for all : FF_D_PE use entity WORK.FF_D_POSITIVE_EDGE(Behavioral_D_PE);
+-- for all : FF_D_PE use entity WORK.FF_D_POSITIVE_EDGE(D_PE_LUT_1);
+-- for all : FF_D_PE use entity WORK.FF_D_POSITIVE_EDGE(D_PE_LUT_2);
+ for all : FF_D_PE use entity WORK.FF_D_POSITIVE_EDGE(D_PE_LUT_3);
+
+ component MUX_21 is
+ generic (
+ delay_and : TIME := 0 ns;
+ delay_or : TIME := 0 ns;
+ delay_not : TIME := 0 ns
+ );
+ port (
+ S,A,B:in STD_LOGIC;
+ C:out STD_LOGIC
+ );
+ end component MUX_21;
+ for all : MUX_21 use entity WORK.MUX_21(MUX_21_LUT_1);
+
+ component GN is
+ generic (delay_not : time := 0 ns);
+ port (A:in STD_LOGIC;B:out STD_LOGIC);
+ end component GN;
+ for all : GN use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ signal sa,sb,sc: STD_LOGIC;
+ signal null_s,null_r : std_logic;
+
+begin
+
+ g1: GN generic map (delay_not) port map (A => C, B => sa);
+ g2: FF_D_PE
+ generic map (
+ delay_not => delay_not,
+ delay_and => delay_and,
+ delay_nor2 => delay_nor2,
+ delay_nand2 => delay_nand2,
+ delay_nand3 => delay_nand3
+ )
+ port map (S => S, R => R, C => sa, D => D, Q1 => sb, Q2 => open);
+ g3: FF_D_PE
+ generic map (
+ delay_not => delay_not,
+ delay_and => delay_and,
+ delay_nor2 => delay_nor2,
+ delay_nand2 => delay_nand2,
+ delay_nand3 => delay_nand3
+ )
+ port map (S => S, R => R, C => C, D => D, Q1 => sc, Q2 => open);
+ g4: MUX_21
+ generic map (
+ delay_and => delay_and,
+ delay_or => delay_or,
+ delay_not => delay_not
+ )
+ port map (S => C, A => sb, B => sc, C => Q);
+
+end architecture D_DET_LUT;
diff --git a/weirdboyjim_circuits/FF_D_GATED.vhd b/weirdboyjim_circuits/FF_D_GATED.vhd
new file mode 100755
index 0000000..c8d0163
--- /dev/null
+++ b/weirdboyjim_circuits/FF_D_GATED.vhd
@@ -0,0 +1,149 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FF_D_GATED is
+generic (
+delay_and : TIME := 0 ns;
+delay_or : TIME := 0 ns;
+delay_not : TIME := 0 ns
+);
+port (
+D,E : in STD_LOGIC;
+Q1,Q2 : out STD_LOGIC
+);
+end entity FF_D_GATED;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Gated_D_latch
+architecture Behavioral_GATED_D_NAND of FF_D_GATED is
+component GAND is
+generic (delay_and : TIME := 0 ns);
+port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+end component GAND;
+component GN is
+generic (delay_not : TIME := 0 ns);
+port (A : in STD_LOGIC; B : out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc,sd,se,sf,sg,sh:STD_LOGIC;
+signal q1out : std_logic;
+signal q2out : std_logic;
+begin
+Q1 <= q1out;
+Q2 <= q2out;
+g1: GAND generic map (delay_and) port map (D,E,sa);
+g2: GN generic map (delay_not) port map (sa,sb);
+g3: GAND generic map (delay_and) port map (E,sb,sc);
+g4: GN generic map (delay_not) port map (sc,sd);
+g5: GAND generic map (delay_and) port map (sb,q2out,sg);
+g6: GN generic map (delay_not) port map (sg,q1out);
+g7: GAND generic map (delay_and) port map (sd,q1out,se);
+g8: GN generic map (delay_not) port map (se,q2out);
+
+end architecture Behavioral_GATED_D_NAND;
+
+architecture GATED_D_NAND_LUT of FF_D_GATED is
+
+ component GAND is
+ generic (delay_and : TIME := 0 ns);
+ port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+ end component GAND;
+ for all : GAND use entity WORK.GATE_AND(GATE_AND_LUT);
+
+ component GN is
+ generic (delay_not : TIME := 0 ns);
+ port (A : in STD_LOGIC; B : out STD_LOGIC);
+ end component GN;
+ for all : GN use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ signal sa,sb,sc,sd,se,sf,sg,sh:STD_LOGIC;
+ signal q1out : std_logic;
+ signal q2out : std_logic;
+
+begin
+
+ Q1 <= q1out;
+ Q2 <= q2out;
+
+ g1: GAND generic map (delay_and) port map (A => D, B => E, C => sa);
+ g2: GN generic map (delay_not) port map (A => sa, B => sb);
+ g3: GAND generic map (delay_and) port map (A => E, B => sb, C => sc);
+ g4: GN generic map (delay_not) port map (A => sc, B => sd);
+ g5: GAND generic map (delay_and) port map (A => sb, B => q2out, C => sg);
+ g6: GN generic map (delay_not) port map (A => sg, B => q1out);
+ g7: GAND generic map (delay_and) port map (A => sd, B => q1out, C => se);
+ g8: GN generic map (delay_not) port map (A => se, B => q2out);
+
+end architecture GATED_D_NAND_LUT;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Gated_D_latch
+architecture Behavioral_GATED_D_NOR of FF_D_GATED is
+component GAND is
+generic (delay_and : TIME := 0 ns);
+port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+end component GAND;
+component GOR is
+generic (delay_or : TIME := 0 ns);
+port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+end component GOR;
+component GN is
+generic (delay_not : TIME := 0 ns);
+port (A : in STD_LOGIC; B : out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc,sd,se,sf,sg,sh:STD_LOGIC;
+signal q1out : std_logic;
+signal q2out : std_logic;
+begin
+Q1 <= q1out;
+Q2 <= q2out;
+g1: GN generic map (delay_not) port map (D,sa);
+g2: GAND generic map (delay_and) port map (sa,E,sb);
+g3: GAND generic map (delay_and) port map (D,E,sc);
+g4: GOR generic map (delay_or) port map (sb,q2out,sg);
+g5: GN generic map (delay_not) port map (sg,q1out);
+g6: GOR generic map (delay_or) port map (sc,q1out,se);
+g7: GN generic map (delay_not) port map (se,q2out);
+
+end architecture Behavioral_GATED_D_NOR;
+
+architecture GATED_D_NOR_LUT of FF_D_GATED is
+
+ component GAND is
+ generic (delay_and : TIME := 0 ns);
+ port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+ end component GAND;
+ for all : GAND use entity WORK.GATE_AND(GATE_AND_LUT);
+
+ component GOR is
+ generic (delay_or : TIME := 0 ns);
+ port (A,B : in STD_LOGIC; C : out STD_LOGIC);
+ end component GOR;
+ for all : GOR use entity WORK.GATE_OR(GATE_OR_LUT);
+
+ component GN is
+ generic (delay_not : TIME := 0 ns);
+ port (A : in STD_LOGIC; B : out STD_LOGIC);
+ end component GN;
+ for all : GN use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ signal sa,sb,sc,sd,se,sf,sg,sh:STD_LOGIC;
+ signal q1out : std_logic;
+ signal q2out : std_logic;
+
+begin
+
+ Q1 <= q1out;
+ Q2 <= q2out;
+
+ g1: GN generic map (delay_not) port map (A => D, B => sa);
+ g2: GAND generic map (delay_and) port map (A => sa, B => E, C => sb);
+ g3: GAND generic map (delay_and) port map (A => D, B => E, C => sc);
+ g4: GOR generic map (delay_or) port map (A => sb, B => q2out, C => sg);
+ g5: GN generic map (delay_not) port map (A => sg, B => q1out);
+ g6: GOR generic map (delay_or) port map (A => sc, B => q1out, C => se);
+ g7: GN generic map (delay_not) port map (A => se, B => q2out);
+
+end architecture GATED_D_NOR_LUT;
diff --git a/weirdboyjim_circuits/FF_D_MS.vhd b/weirdboyjim_circuits/FF_D_MS.vhd
new file mode 100755
index 0000000..2d3e930
--- /dev/null
+++ b/weirdboyjim_circuits/FF_D_MS.vhd
@@ -0,0 +1,70 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FF_D_MASTER_SLAVE is
+port (C,D:in STD_LOGIC;Q1,Q2:out STD_LOGIC);
+end entity FF_D_MASTER_SLAVE;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Master%E2%80%93slave_edge-triggered_D_flip-flop
+architecture Behavioral_D_MS of FF_D_MASTER_SLAVE is
+component GAND is
+generic (delay_and : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GN is
+generic (delay_not : time := 0 ns);
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal X,Y,Z,U,V,W,O,P,sa,sb,sc,sd,se,sf,sg,sh:STD_LOGIC;
+signal q1out,q2out : std_logic;
+begin
+Q1 <= q1out;
+Q2 <= q2out;
+g1: GN port map (C,X);
+g2: GAND port map (D,X,sa); g3: GN port map(sa,Y);
+g4: GN port map (X,U);
+g5: GAND port map (X,Y,sb); g6: GN port map(sb,V);
+g7: GAND port map (Y,W,sc); g8: GN port map(sc,Z);
+g9: GAND port map (V,Z,sd); g10: GN port map(sd,W);
+g11: GAND port map (Z,U,se); g12: GN port map(se,O);
+g13: GAND port map (O,U,sf); g14: GN port map(sf,P);
+g15: GAND port map (O,q2out,sg); g16: GN port map(sg,q1out);
+g17: GAND port map (P,q1out,sh); g18: GN port map(sh,q2out);
+end architecture Behavioral_D_MS;
+
+architecture D_MS_LUT of FF_D_MASTER_SLAVE is
+
+ component GAND is
+ generic (delay_and : time := 0 ns);
+ port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+ end component GAND;
+ for all : GAND use entity WORK.GATE_AND(GATE_AND_LUT);
+
+ component GN is
+ generic (delay_not : time := 0 ns);
+ port (A:in STD_LOGIC;B:out STD_LOGIC);
+ end component GN;
+ for all : GN use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ signal X,Y,Z,U,V,W,O,P,sa,sb,sc,sd,se,sf,sg,sh:STD_LOGIC;
+ signal q1out,q2out : std_logic;
+
+begin
+
+ Q1 <= q1out;
+ Q2 <= q2out;
+
+ g1: GN port map (A => C, B => X);
+ g2: GAND port map (A => D, B => X, C => sa); g3: GN port map (A => sa, B => Y);
+ g4: GN port map (A => X, B => U);
+ g5: GAND port map (A => X, B => Y, C => sb); g6: GN port map (A => sb, B => V);
+ g7: GAND port map (A => Y, B => W, C => sc); g8: GN port map (A => sc, B => Z);
+ g9: GAND port map (A => V, B => Z, C => sd); g10: GN port map (A => sd, B => W);
+ g11: GAND port map (A => Z, B => U, C => se); g12: GN port map (A => se, B => O);
+ g13: GAND port map (A => O, B => U, C => sf); g14: GN port map (A => sf, B => P);
+ g15: GAND port map (A => O, B => q2out, C => sg); g16: GN port map (A => sg, B => q1out);
+ g17: GAND port map (A => P, B => q1out, C => sh); g18: GN port map (A => sh, B => q2out);
+
+end architecture D_MS_LUT;
diff --git a/weirdboyjim_circuits/FF_D_PE.vhd b/weirdboyjim_circuits/FF_D_PE.vhd
new file mode 100755
index 0000000..01895fc
--- /dev/null
+++ b/weirdboyjim_circuits/FF_D_PE.vhd
@@ -0,0 +1,212 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FF_D_POSITIVE_EDGE is
+generic (
+delay_not : time := 0 ns;
+delay_and : time := 0 ns;
+delay_nor2 : time := 0 ns;
+delay_nand2 : time := 0 ns;
+delay_nand3 : time := 0 ns
+);
+port (
+S : in std_logic;
+R : in std_logic;
+C : in std_logic;
+D : in STD_LOGIC;
+Q1,Q2:out STD_LOGIC
+);
+end entity FF_D_POSITIVE_EDGE;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Classical_positive-edge-triggered_D_flip-flop
+architecture Behavioral_D_PE of FF_D_POSITIVE_EDGE is
+
+--component GAND is
+--generic (delay_and:time := 0 ns);
+--port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+--end component GAND;
+--component GN is
+--generic (delay_not:time := 0 ns);
+--port (A:in STD_LOGIC;B:out STD_LOGIC);
+--end component GN;
+--for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+--for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+--signal X,Y,Z,V,W,O,sa,sb,sc,sd,se,sf:STD_LOGIC;
+--constant DELAY_AND : time := 1 ps;
+--constant DELAY_NOT : time := 1 ps;
+
+constant WAIT_NAND3 : time := 0 ps;
+signal setu,setd,resetu,resetd : std_logic;
+signal q1out,q2out : std_logic;
+
+begin
+
+--rst1 <= D when i_reset = '0' else '0';
+--g1: GAND generic map (DELAY_AND) port map (rst1,X,sa);
+--g2: GN generic map (DELAY_NOT) port map(sa,Y);
+--g3: GAND generic map (DELAY_AND) port map (Y,O,sb);
+--g4: GN generic map (DELAY_NOT) port map(sb,X);
+--rst2 <= C when i_reset = '0' else '0';
+--g5: GAND generic map (DELAY_AND) port map (rst2,V,sc);
+--g6: GN generic map (DELAY_NOT) port map(sc,Z);
+--g7: GAND generic map (DELAY_AND) port map (Z,Y,sd);
+--g8: GN generic map (DELAY_NOT) port map(sd,V);
+--rst3 <= Q2 when i_reset = '0' else '0';
+--g9: GAND generic map (DELAY_AND) port map (Z,rst3,se);
+--gA: GN generic map (DELAY_NOT) port map(se,Q1);
+--gB: GAND generic map (DELAY_AND) port map (X,Q1,sf);
+--gC: GN generic map (DELAY_NOT) port map(sf,Q2);
+--gD: GAND generic map (DELAY_AND) port map (C,Z,O);
+
+-- https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29#/media/File:Edge_triggered_D_flip_flop_with_set_and_reset.svg
+Q1 <= q1out;
+Q2 <= q2out;
+g1 : q1out <= not (S and setd and q2out) after delay_nand3;
+g2 : q2out <= not (q1out and resetu and R) after delay_nand3;
+g3 : setu <= not (S and resetd and setd) after delay_nand3;
+g4 : setd <= not (setu and C and R) after delay_nand3;
+g5 : resetu <= not (setd and C and resetd) after delay_nand3;
+g6 : resetd <= not (resetu and D and R) after delay_nand3;
+
+end architecture Behavioral_D_PE;
+
+architecture D_PE_LUT_1 of FF_D_POSITIVE_EDGE is
+
+ component GATE_NAND2 is
+ generic (
+ delay_nand2 : TIME := 0 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_NAND2;
+ for all : GATE_NAND2 use entity WORK.GATE_NAND2(GATE_NAND2_LUT);
+
+ component GATE_NAND3 is
+ generic (
+ delay_nand3 : TIME := 0 ns
+ );
+ port (
+ A,B,C : in STD_LOGIC;
+ D : out STD_LOGIC
+ );
+ end component GATE_NAND3;
+ for all : GATE_NAND3 use entity WORK.GATE_NAND3(GATE_NAND3_LUT);
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 0 ns
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ signal D_not,R_latch,S_latch : std_logic;
+ signal q1out,q2out : std_logic;
+
+begin
+
+ q1 <= q1out;
+ q2 <= q2out;
+
+ g0 : GATE_NOT generic map (delay_not) port map (A => D, B => D_not);
+
+ g1 : GATE_NAND2 generic map (delay_nand2) port map (A => D, B => C, C => R_latch);
+ g2 : GATE_NAND2 generic map (delay_nand2) port map (A => D_not, B => C, C => S_latch);
+
+ g3 : GATE_NAND3 generic map (delay_nand3) port map (A => '0', B => S_latch, C => q2out, D => q1out);
+ g4 : GATE_NAND3 generic map (delay_nand3) port map (A => '0', B => R_latch, C => q1out, D => q2out);
+
+end architecture D_PE_LUT_1;
+
+architecture D_PE_LUT_2 of FF_D_POSITIVE_EDGE is
+
+ component GATE_AND is
+ generic (
+ delay_and : TIME := 0 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_AND;
+ for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_LUT);
+
+ component GATE_NOR2 is
+ generic (
+ delay_nor2 : TIME := 0 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_NOR2;
+ for all : GATE_NOR2 use entity WORK.GATE_NOR2(GATE_NOR2_LUT);
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 0 ns
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ signal D_not,R_latch,R_latch1,S_latch,S_latch1 : std_logic := '0';
+ signal q1out : std_logic := '1';
+ signal q2out : std_logic := '0';
+
+begin
+
+ q1 <= q1out;
+ q2 <= q2out;
+
+-- g5 : GATE_NOT generic map (delay_not) port map (A => S_latch1, B => S_latch);
+-- g6 : GATE_NOT generic map (delay_not) port map (A => R_latch1, B => R_latch);
+
+ g0 : GATE_NOT generic map (delay_not) port map (A => D, B => D_not);
+
+ g1 : GATE_AND generic map (delay_and) port map (A => D, B => C, C => S_latch1);
+ g2 : GATE_AND generic map (delay_and) port map (A => D_not, B => C, C => R_latch1);
+
+ g3 : GATE_NOR2 generic map (delay_nor2) port map (A => S_latch1, B => q2out, C => q1out);
+ g4 : GATE_NOR2 generic map (delay_nor2) port map (A => R_latch1, B => q1out, C => q2out);
+
+end architecture D_PE_LUT_2;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#/media/File:Edge_triggered_D_flip_flop_with_set_and_reset.svg
+architecture D_PE_LUT_3 of FF_D_POSITIVE_EDGE is
+
+ component GATE_NAND3 is
+ generic (
+ delay_nand3 : TIME := 0 ns
+ );
+ port (
+ A,B,C : in STD_LOGIC;
+ D : out STD_LOGIC
+ );
+ end component GATE_NAND3;
+ for all : GATE_NAND3 use entity WORK.GATE_NAND3(GATE_NAND3_LUT);
+
+ signal E,F,G,H : std_logic;
+ signal q1out,q2out : std_logic;
+
+begin
+
+ Q1 <= q1out;
+ Q2 <= q2out;
+
+ g0 : GATE_NAND3 generic map (delay_nand3) port map (A => S, B => H, C => F, D => E);
+ g1 : GATE_NAND3 generic map (delay_nand3) port map (A => E, B => C, C => R, D => F);
+ g2 : GATE_NAND3 generic map (delay_nand3) port map (A => F, B => C, C => H, D => G);
+ g3 : GATE_NAND3 generic map (delay_nand3) port map (A => G, B => D, C => R, D => H);
+ g4 : GATE_NAND3 generic map (delay_nand3) port map (A => S, B => F, C => q2out, D => q1out);
+ g5 : GATE_NAND3 generic map (delay_nand3) port map (A => q1out, B => G, C => R, D => q2out);
+
+end architecture D_PE_LUT_3;
diff --git a/weirdboyjim_circuits/FF_E_LATCH.vhd b/weirdboyjim_circuits/FF_E_LATCH.vhd
new file mode 100755
index 0000000..db11415
--- /dev/null
+++ b/weirdboyjim_circuits/FF_E_LATCH.vhd
@@ -0,0 +1,95 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FF_E_LATCH is
+generic (
+delay_and : time := 0 ns;
+delay_and3 : time := 0 ns;
+delay_not : time := 0 ns;
+delay_nand2 : time := 0 ns;
+delay_nand3 : time := 0 ns
+);
+port (D,E_H,E_L:in STD_LOGIC;Q:out STD_LOGIC);
+end entity FF_E_LATCH;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Earle_latch
+architecture Behavioral_E_LATCH of FF_E_LATCH is
+component GAND is
+generic (delay_and : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GAND3 is
+generic (delay_and3 : time := 0 ns);
+port (A,B,C:in STD_LOGIC;D:out STD_LOGIC);
+end component GAND3;
+component GN is
+generic (delay_not : time := 0 ns);
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GAND3 use entity WORK.GATE_AND3(GATE_AND3_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc,sd,se,sf,sg,sh,si:STD_LOGIC;
+signal qout : std_logic;
+begin
+Q <= qout;
+g1: GAND generic map (delay_and) port map (A => E_H, B => D, C => sa);
+g2: GN generic map (delay_not) port map (A => sa, B => sb);
+g3: GAND generic map (delay_and) port map (A => D, B => qout, C => sc);
+g4: GN generic map (delay_not) port map (A => sc, B =>sd);
+g5: GAND generic map (delay_and) port map (A => qout, B => E_L, C => se);
+g6: GN generic map (delay_not) port map (A => se, B => sf);
+g7: GAND3 generic map (delay_and3) port map (A => sb, B => sd, C => sf, D => sh);
+g8: GN generic map (delay_not) port map (A => sh, B => qout);
+end architecture Behavioral_E_LATCH;
+
+architecture LUT_E_LATCH of FF_E_LATCH is
+component GAND is
+generic (delay_and : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GAND3 is
+generic (delay_and3 : time := 0 ns);
+port (A,B,C:in STD_LOGIC;D:out STD_LOGIC);
+end component GAND3;
+component GN is
+generic (delay_not : time := 0 ns);
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_LUT);
+for all : GAND3 use entity WORK.GATE_AND3(GATE_AND3_LUT);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_LUT);
+signal sa,sb,sc,sd,se,sf,sg,sh,si:STD_LOGIC;
+signal qout : std_logic;
+begin
+Q <= qout;
+g1: GAND generic map (delay_and) port map (A => E_H, B => D, C => sa);
+g2: GN generic map (delay_not) port map (A => sa, B => sb);
+g3: GAND generic map (delay_and) port map (A => D, B => qout, C => sc);
+g4: GN generic map (delay_not) port map (A => sc, B => sd);
+g5: GAND generic map (delay_and) port map (A => qout, B => E_L, C => se);
+g6: GN generic map (delay_not) port map (A => se, B => sf);
+g7: GAND3 generic map (delay_and3) port map (A => sb, B => sd, C => sf, D => sh);
+g8: GN generic map (delay_not) port map (A => sh, B => qout);
+end architecture LUT_E_LATCH;
+
+architecture LUT_E_LATCH_NAND of FF_E_LATCH is
+component GNAND2 is
+generic (delay_nand2 : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GNAND2;
+component GNAND3 is
+generic (delay_nand3 : time := 0 ns);
+port (A,B,C:in STD_LOGIC;D:out STD_LOGIC);
+end component GNAND3;
+for all : GNAND2 use entity WORK.GATE_NAND2(GATE_NAND2_LUT);
+for all : GNAND3 use entity WORK.GATE_NAND3(GATE_NAND3_LUT);
+signal sa,sb,sc,sd,se,sf,sg,sh,si:STD_LOGIC;
+signal qout : std_logic;
+begin
+Q <= qout;
+g1: GNAND2 generic map (delay_nand2) port map (A => E_H, B => D, C => sb);
+g2: GNAND2 generic map (delay_nand2) port map (A => D, B => qout, C => sd);
+g3: GNAND2 generic map (delay_nand2) port map (A => qout, B => E_L, C => sf);
+g4: GNAND3 generic map (delay_nand3) port map (A => sb, B => sd, C => sf, D => qout);
+end architecture LUT_E_LATCH_NAND;
diff --git a/weirdboyjim_circuits/FF_JK.vhd b/weirdboyjim_circuits/FF_JK.vhd
new file mode 100755
index 0000000..da2fe10
--- /dev/null
+++ b/weirdboyjim_circuits/FF_JK.vhd
@@ -0,0 +1,377 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity FF_JK is
+port (
+ i_r : in STD_LOGIC;
+ J,K,C : in STD_LOGIC;
+ Q1 : out STD_LOGIC;
+ Q2 : out STD_LOGIC
+);
+end entity FF_JK;
+
+architecture LUT of FF_JK is
+
+ constant W_NOT : time := 0 ns;
+ constant W_AND : time := 1 ns;
+ constant W_NAND2 : time := 0 ns;
+ constant W_NAND3 : time := 0 ns;
+ constant W_NAND4 : time := 0 ns;
+ constant W_NAND : time := W_NAND2;
+ constant W_Q1MS : time := 1 ns;
+ constant W_Q2MS : time := 0 ns;
+ constant W_C : time := 0 ns;
+ constant W_NOTC : time := 0 ns;
+ constant W_J : time := 0 ns;
+ constant W_K : time := 0 ns;
+
+ signal sa,sb,sc,sd : std_logic;
+ signal se,sg : std_logic;
+ signal sh,sj : std_logic;
+ signal sk,sn : std_logic;
+ signal so,sp : std_logic;
+ signal sr,ss : std_logic;
+ signal st,su : std_logic;
+ signal sw,sx : std_logic;
+ signal sy,sz : std_logic;
+ signal i_rb : std_logic;
+ signal q1out,q2out : std_logic;
+
+-- component GATE_NAND3 is
+-- Generic (
+-- DELAY_NAND3 : time := 1 ps
+-- );
+-- Port (
+-- A,B,C : in STD_LOGIC;
+-- D : out STD_LOGIC
+-- );
+-- end component GATE_NAND3;
+-- for all : GATE_NAND3 use entity WORK.GATE_NAND3(GATE_NAND3_LUT);
+
+ component GATE_AND is
+ generic (
+ delay_and : TIME := 0 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_AND;
+ for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_LUT);
+
+ component GATE_NAND is
+ Generic (
+ DELAY_NAND : time := 0 ns
+ );
+ Port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_NAND;
+ for all : GATE_NAND use entity WORK.GATE_NAND(GATE_NAND_LUT);
+
+ component GATE_NAND3 is
+ Generic (
+ DELAY_NAND3 : time := 0 ns
+ );
+ Port (
+ A,B,C : in STD_LOGIC;
+ D : out STD_LOGIC
+ );
+ end component GATE_NAND3;
+ for all : GATE_NAND3 use entity WORK.GATE_NAND3(GATE_NAND3_LUT);
+
+ component GATE_NAND4 is
+ Generic (
+ DELAY_NAND4 : time := 0 ns
+ );
+ Port (
+ A,B,C,D : in STD_LOGIC;
+ E : out STD_LOGIC
+ );
+ end component GATE_NAND4;
+ for all : GATE_NAND4 use entity WORK.GATE_NAND4(GATE_NAND4_LUT);
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 0 ns
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+begin
+
+ Q1 <= q1out after W_Q1MS;
+ Q2 <= q2out after W_Q2MS;
+
+-- sa <= C after W_C;
+ -- clock bar
+ clock_b : GATE_NOT GENERIC MAP (W_NOT)
+ PORT MAP (A=>C,B=>sb);
+-- sb <= not C after W_NOTC;
+-- sc <= j after W_J;
+-- sd <= k after W_K;
+
+ -- reset bar
+ i_rbar : GATE_NOT GENERIC MAP (W_NOT)
+ PORT MAP (A=>i_r,B=>i_rb);
+
+ -- nand3 1u plus i_r bar
+ nand3_1u : GATE_NAND4 GENERIC MAP (W_NAND4)
+ PORT MAP (A=>C,B=>j,C=>q2out,D=>i_rb,E=>sg);
+-- se <= not (sa and sc and q2 and not i_r);
+-- sg <= se after W_NAND3;
+
+ -- nand3 1d
+ nand3_1d : GATE_NAND3 GENERIC MAP (W_NAND3)
+ PORT MAP (A=>C,B=>k,C=>q1out,D=>sj);
+-- sh <= not (sa and sd and q1);
+-- sj <= sh after W_NAND3;
+
+ -- nand2 1u
+ nand2_1u_1 : GATE_NAND GENERIC MAP (W_NAND)
+ PORT MAP (A=>sg,B=>sp,C=>sn);
+-- sk <= sg nand sp;
+-- sn <= sk after W_NAND2;
+
+ -- nand2 1d plus i_r bar
+ nand2_1d_1 : GATE_NAND3 GENERIC MAP (W_NAND3)
+ PORT MAP (A=>sj,B=>sn,C=>i_rb,D=>sp);
+-- so <= not (sj and sn and not i_r);
+-- sp <= so after 1 ns;
+
+ -- nand2 1u
+ nand2_1u_2 : GATE_NAND GENERIC MAP (W_NAND)
+ PORT MAP (A=>sn,B=>sb,C=>ss);
+-- sr <= sn nand sb;
+-- ss <= sr after W_NAND2;
+
+ -- nand2 1d
+ nand2_1d_2 : GATE_NAND GENERIC MAP (W_NAND)
+ PORT MAP (A=>sp,B=>sb,C=>su);
+-- st <= sp nand sb;
+-- su <= st after W_NAND2;
+
+ -- nand2 q1
+ nand2_q1 : GATE_NAND GENERIC MAP (W_NAND)
+ PORT MAP (A=>ss,B=>q2out,C=>sx);
+-- sw <= ss nand q2;
+-- sx <= sw after 1 ns;
+
+ -- nand2 q2
+ nand2_q2 : GATE_NAND GENERIC MAP (W_NAND)
+ PORT MAP (A=>su,B=>q1out,C=>q2out);
+-- sy <= su nand q1;
+-- sz <= sy after W_NAND2;
+
+ q1_out : GATE_AND GENERIC MAP (W_AND)
+ PORT MAP (A=>sx,B=>i_rb,C=>q1out);
+-- q1 <= sx and not i_r after 1 ns; -- XXX metastable
+-- q2_out : BUF PORT MAP (I=>sz,O=>q2out);
+-- q2 <= sz after W_Q2MS;
+
+end architecture LUT;
+
+--architecture structural of FF_JK is
+-- constant W_NAND2 : time := 0 ns;
+-- constant W_NAND3 : time := 0 ns;
+-- constant W_Q1MS : time := 0 ns;
+-- constant W_Q2MS : time := 0 ns;
+-- constant W_C : time := 0 ns;
+-- constant W_NOTC : time := 0 ns;
+-- constant W_J : time := 0 ns;
+-- constant W_K : time := 0 ns;
+--
+-- signal sa,sb,sc,sd : std_logic := '0';
+-- signal se,sg : std_logic := '0';
+-- signal sh,sj : std_logic := '0';
+-- signal sk,sn : std_logic := '0';
+-- signal so,sp : std_logic := '0';
+-- signal sr,ss : std_logic := '0';
+-- signal st,su : std_logic := '0';
+-- signal sw,sx : std_logic := '0';
+-- signal sy,sz : std_logic := '0';
+--begin
+--
+-- sa <= C after W_C;
+-- sb <= not C after W_NOTC;
+-- sc <= j after W_J;
+-- sd <= k after W_K;
+--
+-- -- nand3 1u
+-- se <= not (sa and sc and q2 and not i_r);
+-- sg <= se after W_NAND3;
+--
+-- -- nand3 1d
+-- sh <= not (sa and sd and q1);
+-- sj <= sh after W_NAND3;
+--
+-- -- nand2 1u
+-- sk <= sg nand sp;
+-- sn <= sk after W_NAND2;
+--
+-- -- nand2 1d
+-- so <= not (sj and sn and not i_r);
+-- sp <= so after 1 ns;
+--
+-- -- nand2 1u
+-- sr <= sn nand sb;
+-- ss <= sr after W_NAND2;
+--
+-- -- nand2 1d
+-- st <= sp nand sb;
+-- su <= st after W_NAND2;
+--
+-- -- nand2 q1
+-- sw <= ss nand q2;
+-- sx <= sw after 1 ns;
+--
+-- -- nand2 q2
+-- sy <= su nand q1;
+-- sz <= sy after W_NAND2;
+--
+-- q1 <= sx and not i_r after 1 ns; -- XXX metastable
+-- q2 <= sz after W_Q2MS;
+--
+--end architecture Structural;
+
+---- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#JK_flip-flop
+---- XXX strange operation
+--architecture Behavioral_FF_JK of FF_JK is
+--component GAND is
+--port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+--end component GAND;
+--component FF_SR_NOR is
+--port (S,R:in STD_LOGIC;Q1,Q2:inout STD_LOGIC);
+--end component FF_SR_NOR;
+----component GNOT is
+----generic (delay_not : TIME := 0 ns);
+----port (A:in STD_LOGIC;B:out STD_LOGIC);
+----end component GNOT;
+----for all : GNOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+--for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+--for all : FF_SR_NOR use entity WORK.FF_SR(Behavioral_NOR);
+----for all : FF_SR_NOR use entity WORK.FF_SR(Behavioral_NAND);
+----for all : FF_SR_NOR use entity WORK.FF_SR(Behavioral_ANDOR);
+----for all : FF_SR_NOR use entity WORK.FF_SR(Behavioral_NOT_S_NOT_R);
+--signal sa,sb,sc,sd: STD_LOGIC;
+----signal n1,n2 : STD_LOGIC;
+--begin
+--g1: GAND port map (K,C,sa);
+--g2: GAND port map (sa,Q1,sb);
+----gn1 : GNOT port map (sb,n1);
+--g3: GAND port map (C,J,sc);
+--g4: GAND port map (sc,Q2,sd);
+----gn2 : GNOT port map (sd,n2);
+--g5: FF_SR_NOR port map (sb,sd,Q1,Q2);
+--end architecture Behavioral_FF_JK;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#JK_flip-flop
+--architecture Structural of FF_JK is
+--component GAND is port (A,B:in STD_LOGIC;C:out STD_LOGIC); end component GAND;
+--component GOR is port (A,B:in STD_LOGIC;C:out STD_LOGIC); end component GOR;
+--component GNOT is port (A:in STD_LOGIC;B:out STD_LOGIC); end component GNOT;
+--for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+--for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+--for all : GNOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+--signal sa,sb,sc,sd,se,sf,sg,sh,si,sj : std_logic;
+--begin
+--g1 : GAND port map (J,C,sa);
+--g2 : GAND port map (K,C,sb);
+--
+--g3 : GAND port map (sa,Q2,sc);
+--
+--g4 : GNOT port map (sb,sd);
+--g5 : GAND port map (sd,Q1,se);
+--
+--g6 : GOR port map (sc,se,sf);
+--g7 : GNOT port map (sf,sg);
+--Q1 <= sf;
+--Q2 <= sg;
+--end architecture Structural;
+
+--architecture Structural of FF_JK is
+----component GAND is port (A,B:in STD_LOGIC;C:out STD_LOGIC); end component GAND;
+----component GOR is port (A,B:in STD_LOGIC;C:out STD_LOGIC); end component GOR;
+----component GNOT is port (A:in STD_LOGIC;B:out STD_LOGIC); end component GNOT;
+----for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+----for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+----for all : GNOT use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+--signal sa,sb,sc,sd,se,sf,sg,sh,si,sj : std_logic := '0';
+--constant clock_period : time := 1 ns;
+--begin
+--g1 : sa <= J and C;
+--sb <= sa and Q2 after clock_period;
+--
+--g2 : sc <= K and C;
+--sd <= sc and Q1 after clock_period;
+--
+--g3 : se <= sb nor Q2 after clock_period;
+--
+--g4 : sf <= sd nor Q1 after clock_period;
+--
+--Q1 <= se;
+--Q2 <= sf;
+--end architecture Structural;
+
+
+
+-- p0 : process (C,j,k,q1,q2) is
+-- variable sa,sb,sc,sd : std_logic;
+-- variable se,sf,sg : std_logic;
+-- variable sh,si,sj : std_logic;
+-- variable sk,sn : std_logic;
+-- variable so,sp : std_logic := '0';
+-- variable sr,ss : std_logic := '0';
+-- variable st,su : std_logic;
+-- variable sw,sx : std_logic;
+-- variable sy,sz : std_logic;
+-- begin
+-- sa := C;
+-- sb := not C;
+-- sc := j;
+-- sd := k;
+--
+-- -- nand3 1u
+-- se := sa and sc;
+-- sf := se and q2;
+-- sg := not sf;
+--
+-- -- nand3 1d
+-- sh := sa and sd;
+-- si := sh and q1;
+-- sj := not si;
+--
+-- -- nand2 1u
+-- sk := sg and sp;
+-- sn := not sk;
+--
+-- -- nand2 1d
+-- so := sj and sn;
+-- sp := not so;
+--
+-- -- nand2 1u
+-- sr := sn and sb;
+-- ss := not sr;
+--
+-- -- nand2 1d
+-- st := sp and sb;
+-- su := not st;
+--
+-- -- nand2 q1
+-- sw := ss and q2;
+-- sx := not sw;
+--
+-- -- nand2 q2
+-- sy := su and q1;
+-- sz := not sy;
+--
+-- q1 <= sx;
+-- q2 <= sy;
+-- end process p0;
diff --git a/weirdboyjim_circuits/FF_SR_GATED.vhd b/weirdboyjim_circuits/FF_SR_GATED.vhd
new file mode 100755
index 0000000..a2463d6
--- /dev/null
+++ b/weirdboyjim_circuits/FF_SR_GATED.vhd
@@ -0,0 +1,164 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FF_SR_GATED is
+generic (
+delay_and : time := 0 ns;
+delay_or : time := 0 ns;
+delay_not : time := 0 ns;
+delay_nand2 : time := 0 ns;
+delay_nor2 : time := 0 ns
+);
+port (S,R,E:in STD_LOGIC;Q1,Q2:inout STD_LOGIC);
+end entity FF_SR_GATED;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Gated_SR_latch
+architecture Behavioral_GATED_SR_1 of FF_SR_GATED is
+component GAND is
+generic (delay_and : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GN is
+generic (delay_not : time := 0 ns);
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc,sd,se,sf,sg:STD_LOGIC;
+signal q1out,q2out : std_logic;
+begin
+Q1 <= q1out;
+Q2 <= q2out;
+g1: GAND generic map (delay_and) port map (S,E,sa);
+g2: GN generic map (delay_not) port map (sa,sb);
+g3: GAND generic map (delay_and) port map (R,E,sc);
+g4: GN generic map (delay_not) port map (sc,sd);
+g5: GAND generic map (delay_and) port map (sb,q2out,sg);
+g6: GN generic map (delay_not) port map (sg,q1out);
+g7: GAND generic map (delay_and) port map (sd,q1out,se);
+g8: GN generic map (delay_not) port map (se,q2out);
+end architecture Behavioral_GATED_SR_1;
+
+architecture LUT_GATED_SR_1 of FF_SR_GATED is
+component GAND is
+generic (delay_and : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GN is
+generic (delay_not : time := 0 ns);
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_LUT);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_LUT);
+signal sa,sb,sc,sd,se,sf,sg:STD_LOGIC;
+signal q1out,q2out : std_logic;
+begin
+Q1 <= q1out;
+Q2 <= q2out;
+g1: GAND generic map (delay_and) port map (S,E,sa);
+g2: GN generic map (delay_not) port map (sa,sb);
+g3: GAND generic map (delay_and) port map (R,E,sc);
+g4: GN generic map (delay_not) port map (sc,sd);
+g5: GAND generic map (delay_and) port map (sb,q2out,sg);
+g6: GN generic map (delay_not) port map (sg,q1out);
+g7: GAND generic map (delay_and) port map (sd,q1out,se);
+g8: GN generic map (delay_not) port map (se,q2out);
+end architecture LUT_GATED_SR_1;
+
+architecture LUT_GATED_SR_1_WON of FF_SR_GATED is
+component GNAND2 is
+generic (delay_nand2 : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GNAND2;
+for all : GNAND2 use entity WORK.GATE_NAND2(GATE_NAND2_LUT);
+signal sa,sb,sc,sd,se,sf,sg:STD_LOGIC;
+signal q1out,q2out : std_logic;
+begin
+Q1 <= q1out;
+Q2 <= q2out;
+g1: GNAND2 generic map (delay_nand2) port map (S,E,sb);
+g2: GNAND2 generic map (delay_nand2) port map (R,E,sd);
+g3: GNAND2 generic map (delay_nand2) port map (sb,q2out,q1out);
+g4: GNAND2 generic map (delay_nand2) port map (sd,q1out,q2out);
+end architecture LUT_GATED_SR_1_WON;
+
+-- https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Gated_SR_latch
+architecture Behavioral_GATED_SR_2 of FF_SR_GATED is
+component GAND is
+generic (delay_and : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GOR is
+generic (delay_or : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GOR;
+component GN is
+generic (delay_not : time := 0 ns);
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc,sd,se,sf,sg:STD_LOGIC;
+signal q1out,q2out : std_logic;
+begin
+Q1 <= q1out;
+Q2 <= q2out;
+g1: GAND generic map (delay_and) port map (S,E,sa);
+g2: GAND generic map (delay_and) port map (R,E,sb);
+g3: GOR generic map (delay_or) port map (sa,q2out,sg);
+g4: GN generic map (delay_not) port map (sg,q1out);
+g5: GOR generic map (delay_or) port map (sb,q1out,se);
+g6: GN generic map (delay_not) port map (se,q2out);
+end architecture Behavioral_GATED_SR_2;
+
+architecture LUT_GATED_SR_2 of FF_SR_GATED is
+component GAND is
+generic (delay_and : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GOR is
+generic (delay_or : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GOR;
+component GN is
+generic (delay_not : time := 0 ns);
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_LUT);
+for all : GOR use entity WORK.GATE_OR(GATE_OR_LUT);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_LUT);
+signal sa,sb,sc,sd,se,sf,sg:STD_LOGIC;
+signal q1out,q2out : std_logic;
+begin
+Q1 <= q1out;
+Q2 <= q2out;
+g1: GAND generic map (delay_and) port map (S,E,sa);
+g2: GAND generic map (delay_and) port map (R,E,sb);
+g3: GOR generic map (delay_or) port map (sa,q2out,sg);
+g4: GN generic map (delay_not) port map (sg,q1out);
+g5: GOR generic map (delay_or) port map (sb,q1out,se);
+g6: GN generic map (delay_not) port map (se,q2out);
+end architecture LUT_GATED_SR_2;
+
+architecture LUT_GATED_SR_2_WON of FF_SR_GATED is
+component GAND is
+generic (delay_and : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GNOR2 is
+generic (delay_nor2 : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GNOR2;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_LUT);
+for all : GNOR2 use entity WORK.GATE_NOR2(GATE_NOR2_LUT);
+signal sa,sb,sc,sd,se,sf,sg:STD_LOGIC;
+signal q1out,q2out : std_logic;
+begin
+Q1 <= q1out;
+Q2 <= q2out;
+g1: GAND generic map (delay_and) port map (S,E,sa);
+g2: GAND generic map (delay_and) port map (R,E,sb);
+g3: GNOR2 generic map (delay_nor2) port map (sa,q2out,q1out);
+g4: GNOR2 generic map (delay_nor2) port map (sb,q1out,q2out);
+end architecture LUT_GATED_SR_2_WON;
diff --git a/weirdboyjim_circuits/MUX_21.vhd b/weirdboyjim_circuits/MUX_21.vhd
new file mode 100755
index 0000000..a7ed01e
--- /dev/null
+++ b/weirdboyjim_circuits/MUX_21.vhd
@@ -0,0 +1,38 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity MUX_21 is
+generic (
+delay_and : TIME := 0 ns;
+delay_or : TIME := 0 ns;
+delay_not : TIME := 0 ns
+);
+port (
+S,A,B:in STD_LOGIC;
+C:out STD_LOGIC
+);
+end entity MUX_21;
+
+architecture MUX_21_LUT_1 of MUX_21 is
+component GAND is
+generic (delay_and : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GOR is
+generic (delay_or : time := 0 ns);
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GOR;
+component GN is
+generic (delay_not : time := 0 ns);
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_LUT);
+for all : GOR use entity WORK.GATE_OR(GATE_OR_LUT);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_LUT);
+signal sa,sb,sc : STD_LOGIC;
+begin
+g1: GN generic map (delay_not) port map (S,sa);
+g3: GAND generic map (delay_and) port map (A,S,sb);
+g4: GAND generic map (delay_and) port map (B,sa,sc);
+g5: GOR generic map (delay_or) port map (sb,sc,C);
+end architecture MUX_21_LUT_1;
diff --git a/weirdboyjim_circuits/README.txt b/weirdboyjim_circuits/README.txt
new file mode 100755
index 0000000..929cd23
--- /dev/null
+++ b/weirdboyjim_circuits/README.txt
@@ -0,0 +1 @@
+Some circuits in VHDL based on https://easyeda.com/weirdboyjim and https://www.youtube.com/c/weirdboyjim/playlists
diff --git a/weirdboyjim_circuits/TB_FF_E_LATCH.vhd b/weirdboyjim_circuits/TB_FF_E_LATCH.vhd
new file mode 100755
index 0000000..954589f
--- /dev/null
+++ b/weirdboyjim_circuits/TB_FF_E_LATCH.vhd
@@ -0,0 +1,158 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:24:33 01/12/2022
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/weirdboyjim_circuits/TB_FF_E_LATCH.vhd
+-- Project Name: weirdboyjim_circuits
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: FF_E_LATCH
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY TB_FF_E_LATCH IS
+END TB_FF_E_LATCH;
+
+ARCHITECTURE behavior OF TB_FF_E_LATCH IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT FF_E_LATCH
+GENERIC(
+delay_and : time := 0 ns;
+delay_and3 : time := 0 ns;
+delay_not : time := 0 ns;
+delay_nand2 : time := 0 ns;
+delay_nand3 : time := 0 ns
+);
+PORT(
+D : IN std_logic;
+E_H : IN std_logic;
+E_L : IN std_logic;
+Q : OUT std_logic
+);
+END COMPONENT FF_E_LATCH;
+--for all : FF_E_LATCH use entity WORK.FF_E_LATCH(Behavioral_E_LATCH);
+--for all : FF_E_LATCH use entity WORK.FF_E_LATCH(LUT_E_LATCH);
+for all : FF_E_LATCH use entity WORK.FF_E_LATCH(LUT_E_LATCH_NAND);
+
+
+--Inputs
+signal D : std_logic := '0';
+signal E_H : std_logic := '0';
+signal E_L : std_logic := '0';
+
+--Outputs
+signal Q : std_logic;
+
+constant clock_period : time := 20 ns;
+signal clock : std_logic;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: FF_E_LATCH
+GENERIC MAP (
+delay_and => 0 ns,
+delay_and3 => 0 ns,
+delay_not => 0 ns,
+delay_nand2 => 1 ns,
+delay_nand3 => 0 ns
+)
+PORT MAP (
+D => D,
+E_H => E_H,
+E_L => E_L,
+Q => Q
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+D <= not clock;
+-- Stimulus process
+stim_proc: process
+begin
+E_H <= '0';
+E_L <= '1';
+wait for 15 ns;
+E_H <= '1';
+E_L <= '0';
+wait for 10 ns;
+E_H <= '0';
+E_L <= '1';
+wait for 10 ns;
+E_H <= '1';
+E_L <= '0';
+wait for 6 ns;
+E_H <= '0';
+E_L <= '1';
+wait for 4 ns;
+E_H <= '1';
+E_L <= '0';
+wait for 10 ns;
+E_H <= '0';
+E_L <= '1';
+wait for 10 ns;
+E_H <= '1';
+E_L <= '0';
+wait for 15 ns;
+E_H <= '0';
+E_L <= '1';
+wait for 5 ns;
+E_H <= '1';
+E_L <= '0';
+wait for 15 ns;
+E_H <= '0';
+E_L <= '1';
+wait for 20 ns;
+E_H <= '1';
+E_L <= '0';
+wait for 5 ns;
+E_H <= '0';
+E_L <= '1';
+wait for 10 ns;
+E_H <= '1';
+E_L <= '0';
+wait for 5 ns;
+E_H <= '0';
+E_L <= '1';
+wait for 5 ns;
+E_H <= '1';
+E_L <= '0';
+wait for 10 ns;
+E_H <= '0';
+E_L <= '1';
+wait for 10 ns;
+report "done" severity failure;
+end process;
+
+END;
diff --git a/weirdboyjim_circuits/TB_FF_SR_GATED.vhd b/weirdboyjim_circuits/TB_FF_SR_GATED.vhd
new file mode 100755
index 0000000..9c0cf01
--- /dev/null
+++ b/weirdboyjim_circuits/TB_FF_SR_GATED.vhd
@@ -0,0 +1,329 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 00:52:07 08/10/2020
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl/TB_FF_SR_GATED.vhd
+-- Project Name: vhdl
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: FF_SR_GATED
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY TB_FF_SR_GATED IS
+END TB_FF_SR_GATED;
+
+ARCHITECTURE behavior OF TB_FF_SR_GATED IS
+
+ procedure clk_gen(signal clk : out std_logic; constant wait_start : time; constant HT : time; constant LT : time) is
+ begin
+ clk <= '0';
+ wait for wait_start;
+ loop
+ clk <= '1';
+ wait for HT;
+ clk <= '0';
+ wait for LT;
+ end loop;
+ end procedure;
+
+ COMPONENT FF_SR_GATED1
+ GENERIC(
+ delay_and : time := 0 ns;
+ delay_or : time := 0 ns;
+ delay_not : time := 0 ns;
+ delay_nand2 : time := 0 ns;
+ delay_nor2 : time := 0 ns
+ );
+ PORT(
+ S : IN std_logic;
+ R : IN std_logic;
+ E : IN std_logic;
+ Q1 : INOUT std_logic;
+ Q2 : INOUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT FF_SR_GATED2
+ GENERIC(
+ delay_and : time := 0 ns;
+ delay_or : time := 0 ns;
+ delay_not : time := 0 ns;
+ delay_nand2 : time := 0 ns;
+ delay_nor2 : time := 0 ns
+ );
+ PORT(
+ S : IN std_logic;
+ R : IN std_logic;
+ E : IN std_logic;
+ Q1 : INOUT std_logic;
+ Q2 : INOUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT FF_SR_GATED3
+ GENERIC(
+ delay_and : time := 0 ns;
+ delay_or : time := 0 ns;
+ delay_not : time := 0 ns;
+ delay_nand2 : time := 0 ns;
+ delay_nor2 : time := 0 ns
+ );
+ PORT(
+ S : IN std_logic;
+ R : IN std_logic;
+ E : IN std_logic;
+ Q1 : INOUT std_logic;
+ Q2 : INOUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT FF_SR_GATED4
+ GENERIC(
+ delay_and : time := 0 ns;
+ delay_or : time := 0 ns;
+ delay_not : time := 0 ns;
+ delay_nand2 : time := 0 ns;
+ delay_nor2 : time := 0 ns
+ );
+ PORT(
+ S : IN std_logic;
+ R : IN std_logic;
+ E : IN std_logic;
+ Q1 : INOUT std_logic;
+ Q2 : INOUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT FF_SR_GATED5
+ GENERIC(
+ delay_and : time := 0 ns;
+ delay_or : time := 0 ns;
+ delay_not : time := 0 ns;
+ delay_nand2 : time := 0 ns;
+ delay_nor2 : time := 0 ns
+ );
+ PORT(
+ S : IN std_logic;
+ R : IN std_logic;
+ E : IN std_logic;
+ Q1 : INOUT std_logic;
+ Q2 : INOUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT FF_SR_GATED6
+ GENERIC(
+ delay_and : time := 0 ns;
+ delay_or : time := 0 ns;
+ delay_not : time := 0 ns;
+ delay_nand2 : time := 0 ns;
+ delay_nor2 : time := 0 ns
+ );
+ PORT(
+ S : IN std_logic;
+ R : IN std_logic;
+ E : IN std_logic;
+ Q1 : INOUT std_logic;
+ Q2 : INOUT std_logic
+ );
+ END COMPONENT;
+
+ for all : FF_SR_GATED1 use entity WORK.FF_SR_GATED(Behavioral_GATED_SR_1);
+ for all : FF_SR_GATED2 use entity WORK.FF_SR_GATED(Behavioral_GATED_SR_2);
+ for all : FF_SR_GATED3 use entity WORK.FF_SR_GATED(LUT_GATED_SR_1);
+ for all : FF_SR_GATED4 use entity WORK.FF_SR_GATED(LUT_GATED_SR_2);
+ for all : FF_SR_GATED5 use entity WORK.FF_SR_GATED(LUT_GATED_SR_1_WON);
+ for all : FF_SR_GATED6 use entity WORK.FF_SR_GATED(LUT_GATED_SR_2_WON);
+
+ signal CLK : std_logic;
+ signal S : std_logic := '0';
+ signal R : std_logic := '0';
+ signal Q1_1,Q1_2,Q1_3,Q1_4,Q1_5,Q1_6 : std_logic;
+ signal Q2_1,Q2_2,Q2_3,Q2_4,Q2_5,Q2_6 : std_logic;
+
+ constant delay_and : time := 0 ns;
+ constant delay_or : time := 0 ns;
+ constant delay_not : time := 0 ns;
+ constant delay_nand2 : time := 0 ns;
+ constant delay_nor2 : time := 0 ns;
+
+BEGIN
+
+ clk_gen(CLK, 10 ns, 20 ns, 20 ns);
+
+ uut1: FF_SR_GATED1
+ GENERIC MAP (
+ delay_and => delay_and,
+ delay_or => delay_or,
+ delay_not => delay_not,
+ delay_nand2 => delay_nand2,
+ delay_nor2 => delay_nor2
+ )
+ PORT MAP (
+ S => S,
+ R => R,
+ E => CLK,
+ Q1 => Q1_1,
+ Q2 => Q2_1
+ );
+
+ uut2: FF_SR_GATED2
+ GENERIC MAP (
+ delay_and => delay_and,
+ delay_or => delay_or,
+ delay_not => delay_not,
+ delay_nand2 => delay_nand2,
+ delay_nor2 => delay_nor2
+ )
+ PORT MAP (
+ S => S,
+ R => R,
+ E => CLK,
+ Q1 => Q1_2,
+ Q2 => Q2_2
+ );
+
+ uut3: FF_SR_GATED3
+ GENERIC MAP (
+ delay_and => delay_and,
+ delay_or => delay_or,
+ delay_not => delay_not,
+ delay_nand2 => delay_nand2,
+ delay_nor2 => delay_nor2
+ )
+ PORT MAP (
+ S => S,
+ R => R,
+ E => CLK,
+ Q1 => Q1_3,
+ Q2 => Q2_3
+ );
+
+ uut4: FF_SR_GATED4
+ GENERIC MAP (
+ delay_and => delay_and,
+ delay_or => delay_or,
+ delay_not => delay_not,
+ delay_nand2 => delay_nand2,
+ delay_nor2 => delay_nor2
+ )
+ PORT MAP (
+ S => S,
+ R => R,
+ E => CLK,
+ Q1 => Q1_4,
+ Q2 => Q2_4
+ );
+
+ uut5: FF_SR_GATED5
+ GENERIC MAP (
+ delay_and => delay_and,
+ delay_or => delay_or,
+ delay_not => delay_not,
+ delay_nand2 => delay_nand2,
+ delay_nor2 => delay_nor2
+ )
+ PORT MAP (
+ S => S,
+ R => R,
+ E => CLK,
+ Q1 => Q1_5,
+ Q2 => Q2_5
+ );
+
+ uut6: FF_SR_GATED6
+ GENERIC MAP (
+ delay_and => delay_and,
+ delay_or => delay_or,
+ delay_not => delay_not,
+ delay_nand2 => delay_nand2,
+ delay_nor2 => delay_nor2
+ )
+ PORT MAP (
+ S => S,
+ R => R,
+ E => CLK,
+ Q1 => Q1_6,
+ Q2 => Q2_6
+ );
+
+ stim_proc: process
+ begin
+ S <= '0';
+ R <= '1';
+ wait for 15 ns;
+ S <= '1';
+ R <= '0';
+ wait for 10 ns;
+ S <= '0';
+ R <= '1';
+ wait for 10 ns;
+ S <= '1';
+ R <= '0';
+ wait for 5 ns;
+ S <= '0';
+ R <= '1';
+ wait for 5 ns;
+ S <= '1';
+ R <= '0';
+ wait for 10 ns;
+ S <= '0';
+ R <= '1';
+ wait for 10 ns;
+ S <= '1';
+ R <= '0';
+ wait for 15 ns;
+ S <= '0';
+ R <= '1';
+ wait for 5 ns;
+ S <= '1';
+ R <= '0';
+ wait for 15 ns;
+ S <= '0';
+ R <= '1';
+ wait for 20 ns;
+ S <= '1';
+ R <= '0';
+ wait for 5 ns;
+ S <= '0';
+ R <= '1';
+ wait for 10 ns;
+ S <= '1';
+ R <= '0';
+ wait for 5 ns;
+ S <= '0';
+ R <= '1';
+ wait for 5 ns;
+ S <= '1';
+ R <= '0';
+ wait for 10 ns;
+ S <= '0';
+ R <= '1';
+ wait for 10 ns;
+ report "done" severity failure;
+ end process;
+
+END;
diff --git a/weirdboyjim_circuits/converted_ldcpe2fft.vhd b/weirdboyjim_circuits/converted_ldcpe2fft.vhd
new file mode 100755
index 0000000..47651fc
--- /dev/null
+++ b/weirdboyjim_circuits/converted_ldcpe2fft.vhd
@@ -0,0 +1,282 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:46:40 12/05/2021
+-- Design Name:
+-- Module Name: converted_ldcpe2fft - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_package1.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity converted_ldcpe2fft is
+port (
+ signal i_t : in std_logic;
+ signal i_sd,i_rd : in std_logic;
+ signal o_q1,o_q2 : out std_logic
+);
+end converted_ldcpe2fft;
+
+architecture Behavioral of converted_ldcpe2fft is
+
+-- component delayed_circuit is
+-- port (
+-- i_clock : in std_logic;
+-- i_input : in std_logic;
+-- o_output : out std_logic
+-- );
+-- end component delayed_circuit;
+-- for all : delayed_circuit use entity WORK.delayed_circuit(Behavioral);
+
+-- component FF_D_DUAL_EDGE_TRIGGERED is
+-- port (S,R,D,C:in STD_LOGIC;Q:out STD_LOGIC);
+-- end component FF_D_DUAL_EDGE_TRIGGERED;
+-- for all : FF_D_DUAL_EDGE_TRIGGERED use entity WORK.FF_D_DUAL_EDGE_TRIGGERED(D_DET_LUT);
+
+-- component FF_D_MASTER_SLAVE is
+-- port (
+-- C,D:in STD_LOGIC;
+-- Q1,Q2:inout STD_LOGIC
+-- );
+-- end component FF_D_MASTER_SLAVE;
+-- for all : FF_D_MASTER_SLAVE use entity WORK.FF_D_MASTER_SLAVE(D_MS_LUT);
+--
+-- component FF_D_GATED is
+-- generic (
+-- delay_and : TIME := 0 ns;
+-- delay_or : TIME := 0 ns;
+-- delay_not : TIME := 0 ns
+-- );
+-- port (
+-- D,E : in STD_LOGIC;
+-- Q1,Q2 : out STD_LOGIC
+-- );
+-- end component FF_D_GATED;
+-- for all : FF_D_GATED use entity WORK.FF_D_GATED(GATED_D_NOR_LUT);
+-- for all : FF_D_GATED use entity WORK.FF_D_GATED(GATED_D_NAND_LUT);
+-- for all : FF_D_GATED use entity WORK.FF_D_GATED(Behavioral_GATED_D_NAND);
+-- for all : FF_D_GATED use entity WORK.FF_D_GATED(Behavioral_GATED_D_NOR);
+
+-- component FF_D_POSITIVE_EDGE is
+-- port (
+-- S : in std_logic;
+-- R : in std_logic;
+-- C : in std_logic;
+-- D : in STD_LOGIC;
+-- Q1,Q2:inout STD_LOGIC);
+-- end component FF_D_POSITIVE_EDGE;
+-- for all : FF_D_POSITIVE_EDGE use entity WORK.FF_D_POSITIVE_EDGE(D_PE_LUT_2);
+
+-- component delayed_programmable_circuit is
+-- port (
+-- i_reg1 : in std_logic;
+-- i_reg2 : in std_logic;
+-- i_reg3 : in std_logic;
+-- i_reg4 : in std_logic;
+-- i_reg5 : in std_logic;
+-- i_reg6 : in std_logic;
+-- i_reg7 : in std_logic;
+-- i_input : in std_logic;
+-- o_output : out std_logic
+-- );
+-- end component delayed_programmable_circuit;
+-- for all : delayed_programmable_circuit use entity WORK.delayed_programmable_circuit(Behavioral);
+
+-- component GATE_NOT is
+-- generic (
+-- delay_not : TIME := 0 ps
+-- );
+-- port (
+-- A : in STD_LOGIC;
+-- B : out STD_LOGIC
+-- );
+-- end component GATE_NOT;
+-- for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ component FF_JK is
+ port (
+ i_r : in STD_LOGIC;
+ J,K,C : in STD_LOGIC;
+ Q1 : out STD_LOGIC;
+ Q2 : out STD_LOGIC
+ );
+ end component FF_JK;
+ for all : FF_JK use entity WORK.FF_JK(LUT);
+
+ signal t,d,i_sd_not,dpc_xorout,dpc_q1,q1_not,xorout_not : std_logic;
+ signal xorout : std_logic;
+ signal q1 : std_logic;
+ signal q2 : std_logic;
+
+ signal chain_not : std_logic_vector(1847 downto 0);
+ signal first_not,last_not : std_logic;
+ attribute KEEP : string;
+ attribute KEEP of chain_not : signal is "true";
+
+begin
+
+t <= i_t after 1 ns;
+
+dpc_xorout <= xorout after 1 ns; -- XXX dc off
+--first_not <= xorout after 0 ns;
+--dc : delayed_circuit
+--port map (
+-- i_clock => 'X',
+-- i_input => xorout,
+---- i_input => t,
+---- i_input => first_not,
+-- o_output => dpc_xorout
+--);
+
+ i_sd_not <= not i_sd;
+
+ o_q1 <= q1;
+ o_q2 <= q2;
+
+-- dpc_inst : delayed_programmable_circuit
+-- port map (
+-- i_reg1 => '1',
+-- i_reg2 => '1',
+-- i_reg3 => '1',
+-- i_reg4 => '1',
+-- i_reg5 => '1',
+-- i_reg6 => '1',
+-- i_reg7 => '1',
+-- i_input => xorout,
+-- o_output => dpc_xorout
+-- );
+
+-- XORCY_inst : xorout <= t xor q1 after 1 ns; -- XXX half cycle 199 ps
+ XORCY_inst : XORCY
+ port map (
+ O => xorout, -- XOR output signal
+ CI => t, -- Carry input signal
+-- LI => dpc_q1 -- LUT4 input signal
+ LI => q1 -- LUT4 input signal
+ );
+
+-- xorgate_delay : dpc_xorout <= xorout after 10 ns; -- XXX must be clock_period/2
+-- xorgate_delay : dpc_xorout <= xorout after 1 ns;
+-- q1_delay : dpc_q1 <= q1 after 1 ns;
+
+-- xorout_first_not : GATE_NOT generic map (1 ps) port map (A => xorout, B => xorout_not);
+-- xorout_last_not : GATE_NOT generic map (1 ps) port map (A => xorout_not, B => dpc_xorout);
+
+-- q1_first_not : GATE_NOT generic map (0 ns) port map (A => q1, B => q1_not);
+-- q1_last_not : GATE_NOT generic map (1 ns) port map (A => q1_not, B => dpc_q1);
+
+-- g0_first_not : GATE_NOT generic map (1 ns) port map (A => xorout, B => chain_not(0));
+-- g0_last_not : GATE_NOT generic map (1 ns) port map (A => chain_not(1847), B => first_not);
+-- dpc_xorout <= first_not after (1848+2)*1 ns; -- XXX for sim, must be 256*not_delay
+-- dpc_xorout <= first_not after 0 ns;
+
+-- g0 : for i in 1 to 1847 generate
+-- g0_chain : if (i>0) generate
+-- g0_chain_not : GATE_NOT generic map (1 ns) port map (A => chain_not(i-1), B => chain_not(i));
+-- end generate g0_chain;
+-- end generate g0;
+
+-- q2 <= not q1;
+-- FDCPE_inst : FDCPE
+-- generic map (INIT => '0')
+-- port map (
+-- Q => q1,
+-- C => t,
+-- CE => '1',
+-- CLR => i_rd,
+-- D => dpc_xorout,
+-- PRE => i_sd_not
+-- );
+
+-- q2 <= not q1;
+-- LDCPE_inst : LDCPE
+-- generic map (INIT => '0') --Initial value of latch ('0' or '1')
+-- port map (
+-- Q => q1, -- Data output
+-- CLR => i_rd, -- Asynchronous clear/reset input
+-- D => dpc_xorout, -- Data input
+-- G => '1', -- Gate input
+-- GE => '1', -- Gate enable input
+-- PRE => i_sd_not -- Asynchronous preset/set input
+-- );
+
+-- XXX work
+-- ffd : FF_D_GATED
+-- generic map (
+-- delay_and => 1 ns,
+-- delay_or => 0 ns,
+-- delay_not => 0 ns
+-- )
+-- port map (
+-- D => dpc_xorout,
+---- D => xorout,
+-- E => t,
+-- Q1 => q1,
+-- Q2 => q2
+-- );
+
+-- ffd : FF_D_POSITIVE_EDGE
+-- port map (
+-- S => i_sd,
+-- R => i_rd,
+-- C => '1',
+-- D => dpc_xorout,
+-- Q1 => q1,
+-- Q2 => q2
+-- );
+
+-- XXX fail
+-- ffd : FF_D_MASTER_SLAVE
+-- port map (
+-- C => t, -- XXX must have clock
+---- D => xorout,
+-- D => dpc_xorout,
+-- Q1 => q1,
+-- Q2 => q2
+-- );
+
+-- XXX fail
+-- q2 <= not q1;
+-- ffd : FF_D_DUAL_EDGE_TRIGGERED
+-- port map (
+-- S => i_sd,
+-- R => i_rd,
+---- D => xorout,
+-- D => dpc_xorout,
+---- C => xorout,
+-- C => t,
+-- Q => q1
+-- );
+
+ ffd : FF_JK
+ port map (
+ i_r => i_rd,
+ J => dpc_xorout,
+ K => dpc_xorout,
+ C => t,
+ Q1 => q1,
+ Q2 => q2
+ );
+
+end Behavioral;
diff --git a/weirdboyjim_circuits/delayed_circuit.vhd b/weirdboyjim_circuits/delayed_circuit.vhd
new file mode 100755
index 0000000..be84b98
--- /dev/null
+++ b/weirdboyjim_circuits/delayed_circuit.vhd
@@ -0,0 +1,121 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:57:28 12/18/2021
+-- Design Name:
+-- Module Name: delayed_circuit - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_package1.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity delayed_circuit is
+port (
+i_clock : in std_logic;
+i_input : in std_logic;
+o_output : out std_logic
+);
+end delayed_circuit;
+
+architecture Behavioral of delayed_circuit is
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 0 ps
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ signal t : std_logic;
+ signal q1,q2 : std_logic;
+ signal tq1,tq2 : std_logic;
+
+ constant N : integer := 8; --14;
+ constant N2 : integer := 2**N;
+
+ signal tv1 : std_logic_vector(31 downto 0) := (others => '0');
+
+begin
+
+--tv1 <= std_logic_vector(to_unsigned(v1,32));
+
+t <= i_input after 0 ns;
+p3 : process (t,q2) is
+ constant cv2 : integer := P1_CV2;
+ type state is (a,b,c);
+ variable vs : state;
+ variable v1 : integer range 0 to N2-1 := 0;
+ variable v2 : integer range 0 to cv2-1 := 0;
+ variable s : std_logic;
+begin
+ if (rising_edge(q2)) then
+ case (vs) is
+ when a =>
+ s := '0';
+ if (t = '1') then
+ vs := b;
+ else
+ vs := a;
+ end if;
+ when b =>
+ s := '0';
+ if (v1 = N2-1) then
+ vs := c;
+ v1 := 0;
+ else
+ vs := b;
+ v1 := v1 + 1;
+ end if;
+ when c =>
+ s := '1';
+ if (v2 = cv2-1) then
+ vs := a;
+ v2 := 0;
+ else
+ vs := c;
+ v2 := v2 + 1;
+ end if;
+ end case;
+ end if;
+ o_output <= s;
+end process p3;
+
+tq1 <= q1 after 0 ns;
+g0 : GATE_NOT generic map (0 ns) port map (A => tq1, B => q2);
+LDCPE_inst : LDCPE
+generic map (INIT => '0')
+port map (
+ Q => q1,
+ CLR => '0',
+ D => q2,
+ G => '1',
+ GE => '1',
+ PRE => '0'
+);
+
+end Behavioral;
diff --git a/weirdboyjim_circuits/delayed_programmable_circuit.vhd b/weirdboyjim_circuits/delayed_programmable_circuit.vhd
new file mode 100755
index 0000000..1b4d3f1
--- /dev/null
+++ b/weirdboyjim_circuits/delayed_programmable_circuit.vhd
@@ -0,0 +1,173 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:35:29 08/22/2021
+-- Design Name:
+-- Module Name: delayed_programmable_circuit - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity delayed_programmable_circuit is
+port (
+i_reg1 : in std_logic;
+i_reg2 : in std_logic;
+i_reg3 : in std_logic;
+i_reg4 : in std_logic;
+i_reg5 : in std_logic;
+i_reg6 : in std_logic;
+i_reg7 : in std_logic;
+i_input : in std_logic;
+o_output : out std_logic
+);
+end delayed_programmable_circuit;
+
+architecture Behavioral of delayed_programmable_circuit is
+
+component MUX_21 is
+port (S,A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component MUX_21;
+
+component GATE_NOT is
+generic (
+delay_not : time := 0 ns
+);
+port (
+A : in STD_LOGIC;
+B : out STD_LOGIC
+);
+end component GATE_NOT;
+for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+component DEMUX_12 is
+port (S,A:in STD_LOGIC;B,C:out STD_LOGIC);
+end component DEMUX_12;
+
+signal mux_out : std_logic_vector(8 downto 1);
+signal normal_line : std_logic_vector(8 downto 1);
+
+signal nots1 : std_logic_vector(2**1 downto 0);
+signal nots2 : std_logic_vector(2**2 downto 0);
+signal nots3 : std_logic_vector(2**3 downto 0);
+signal nots4 : std_logic_vector(2**4 downto 0);
+signal nots5 : std_logic_vector(2**5 downto 0);
+signal nots6 : std_logic_vector(2**6 downto 0);
+signal nots7 : std_logic_vector(2**7 downto 0);
+
+begin
+
+dmx1 : DEMUX_12 port map (
+S => i_reg1, A => i_input,
+B => normal_line(1), C => nots1(0)
+);
+gnots1 : for i in 1 to 2**1 generate
+ gn : GATE_NOT port map (A => nots1(i-1), B => nots1(i));
+end generate gnots1;
+mux1 : MUX_21 port map (
+S => i_reg1,
+A => normal_line(1), B => nots1(2**1),
+C => mux_out(1)
+);
+
+dmx2 : DEMUX_12 port map (
+S => i_reg2, A => mux_out(1),
+B => normal_line(2), C => nots2(0)
+);
+gnots2 : for i in 1 to 2**2 generate
+ gn : GATE_NOT port map (A => nots2(i-1), B => nots2(i));
+end generate gnots2;
+mux2 : MUX_21 port map (
+S => i_reg2,
+A => normal_line(2), B => nots2(2**2),
+C => mux_out(2)
+);
+
+dmx3 : DEMUX_12 port map (
+S => i_reg3, A => mux_out(2),
+B => normal_line(3), C => nots3(0)
+);
+gnots3 : for i in 1 to 2**3 generate
+ gn : GATE_NOT port map (A => nots3(i-1), B => nots3(i));
+end generate gnots3;
+mux3 : MUX_21 port map (
+S => i_reg3,
+A => normal_line(3), B => nots3(2**3),
+C => mux_out(3)
+);
+
+dmx4 : DEMUX_12 port map (
+S => i_reg4, A => mux_out(3),
+B => normal_line(4), C => nots4(0)
+);
+gnots4 : for i in 1 to 2**4 generate
+ gn : GATE_NOT port map (A => nots4(i-1), B => nots4(i));
+end generate gnots4;
+mux4 : MUX_21 port map (
+S => i_reg4,
+A => normal_line(4), B => nots4(2**4),
+C => mux_out(4)
+);
+
+dmx5 : DEMUX_12 port map (
+S => i_reg5, A => mux_out(4),
+B => normal_line(5), C => nots5(0)
+);
+gnots5 : for i in 1 to 2**5 generate
+ gn : GATE_NOT port map (A => nots5(i-1), B => nots5(i));
+end generate gnots5;
+mux5 : MUX_21 port map (
+S => i_reg5,
+A => normal_line(5), B => nots5(2**5),
+C => mux_out(5)
+);
+
+dmx6 : DEMUX_12 port map (
+S => i_reg6, A => mux_out(5),
+B => normal_line(6), C => nots6(0)
+);
+gnots6 : for i in 1 to 2**6 generate
+ gn : GATE_NOT port map (A => nots6(i-1), B => nots6(i));
+end generate gnots6;
+mux6 : MUX_21 port map (
+S => i_reg6,
+A => normal_line(6), B => nots6(2**6),
+C => mux_out(6)
+);
+
+dmx7 : DEMUX_12 port map (
+S => i_reg7, A => mux_out(6),
+B => normal_line(7), C => nots7(0)
+);
+gnots7 : for i in 1 to 2**7 generate
+ gn : GATE_NOT port map (A => nots7(i-1), B => nots7(i));
+end generate gnots7;
+mux7 : MUX_21 port map (
+S => i_reg7,
+A => normal_line(7), B => nots7(2**7),
+C => mux_out(7)
+);
+
+o_output <= mux_out(7);
+
+end Behavioral;
diff --git a/weirdboyjim_circuits/gate_and.vhd b/weirdboyjim_circuits/gate_and.vhd
new file mode 100755
index 0000000..83a974c
--- /dev/null
+++ b/weirdboyjim_circuits/gate_and.vhd
@@ -0,0 +1,37 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_AND is
+generic (
+delay_and : TIME := 0 ns
+);
+port (
+A,B : in STD_LOGIC;
+C : out STD_LOGIC
+);
+end entity GATE_AND;
+
+architecture GATE_AND_BEHAVIORAL_1 of GATE_AND is
+begin
+C <= A and B after delay_and;
+end architecture GATE_AND_BEHAVIORAL_1;
+
+architecture GATE_AND_LUT of GATE_AND is
+ signal T : std_logic;
+begin
+-- LUT2: 2-input Look-Up Table with general output
+-- Spartan-3
+-- Xilinx HDL Libraries Guide, version 14.7
+LUT2_inst : LUT2
+generic map (
+ INIT => "1000")
+port map (
+ O => T, -- LUT general output
+ I0 => A, -- LUT input
+ I1 => B -- LUT input
+);
+-- End of LUT2_inst instantiation
+C <= T after delay_and;
+end architecture GATE_AND_LUT;
diff --git a/weirdboyjim_circuits/gate_and3.vhd b/weirdboyjim_circuits/gate_and3.vhd
new file mode 100755
index 0000000..18b2294
--- /dev/null
+++ b/weirdboyjim_circuits/gate_and3.vhd
@@ -0,0 +1,34 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_AND3 is
+generic (
+delay_and3 : TIME := 0 ps
+);
+port (
+A,B,C : in STD_LOGIC;
+D : out STD_LOGIC
+);
+end entity GATE_AND3;
+
+architecture GATE_AND3_BEHAVIORAL_1 of GATE_AND3 is
+begin
+D <= (A and B and C) after delay_and3;
+end architecture GATE_AND3_BEHAVIORAL_1;
+
+architecture GATE_AND3_LUT of GATE_AND3 is
+ signal T : std_logic;
+begin
+LUT3_inst : LUT3
+generic map (
+ INIT => "10000000")
+port map (
+ O => T,
+ I0 => A,
+ I1 => B,
+ I2 => C
+);
+D <= T after delay_and3;
+end architecture GATE_AND3_LUT;
diff --git a/weirdboyjim_circuits/gate_and4.vhd b/weirdboyjim_circuits/gate_and4.vhd
new file mode 100755
index 0000000..9a54b28
--- /dev/null
+++ b/weirdboyjim_circuits/gate_and4.vhd
@@ -0,0 +1,35 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_AND4 is
+generic (
+delay_and4 : TIME := 0 ps
+);
+port (
+A,B,C,D : in STD_LOGIC;
+E : out STD_LOGIC
+);
+end entity GATE_AND4;
+
+architecture GATE_AND4_BEHAVIORAL_1 of GATE_AND4 is
+begin
+E <= A and B and C and D after delay_and4;
+end architecture GATE_AND4_BEHAVIORAL_1;
+
+architecture GATE_AND4_LUT of GATE_AND4 is
+ signal T : std_logic;
+begin
+LUT4_inst : LUT4
+generic map (
+ INIT => "1000000000000000")
+port map (
+ O => T,
+ I0 => A,
+ I1 => B,
+ I2 => C,
+ I3 => D
+);
+E <= T after delay_and4;
+end architecture GATE_AND4_LUT;
diff --git a/weirdboyjim_circuits/gate_nand.vhd b/weirdboyjim_circuits/gate_nand.vhd
new file mode 100755
index 0000000..362e59c
--- /dev/null
+++ b/weirdboyjim_circuits/gate_nand.vhd
@@ -0,0 +1,64 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 09:50:05 09/12/2021
+-- Design Name:
+-- Module Name: gate_and3 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity GATE_NAND is
+Generic (
+DELAY_NAND : time := 0 ps
+);
+Port (
+A,B : in STD_LOGIC;
+C : out STD_LOGIC
+);
+end GATE_NAND;
+
+architecture GATE_NAND_BEHAVIORAL_1 of GATE_NAND is
+ signal T : std_logic;
+begin
+C <= A nand B after DELAY_NAND;
+end GATE_NAND_BEHAVIORAL_1;
+
+architecture GATE_NAND_LUT of GATE_NAND is
+ signal T : std_logic;
+begin
+-- LUT2: 2-input Look-Up Table with general output
+-- Spartan-3
+-- Xilinx HDL Libraries Guide, version 14.7
+gate_nand_LUT2_L : LUT2
+generic map (
+ INIT => "0111")
+port map (
+ O => T, -- LUT local output
+ I0 => A, -- LUT input
+ I1 => B -- LUT input
+);
+-- End of LUT2_inst instantiation
+C <= T after DELAY_NAND;
+end architecture GATE_NAND_LUT;
diff --git a/weirdboyjim_circuits/gate_nand2.vhd b/weirdboyjim_circuits/gate_nand2.vhd
new file mode 100755
index 0000000..81436cb
--- /dev/null
+++ b/weirdboyjim_circuits/gate_nand2.vhd
@@ -0,0 +1,38 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_NAND2 is
+generic (
+delay_nand2 : TIME := 0 ns
+);
+port (
+A,B : in STD_LOGIC;
+C : out STD_LOGIC
+);
+end entity GATE_NAND2;
+
+architecture GATE_NAND2_BEHAVIORAL_1 of GATE_NAND2 is
+begin
+--C <= not (A and B) after delay_nand2;
+C <= A nand B after delay_nand2;
+end architecture GATE_NAND2_BEHAVIORAL_1;
+
+architecture GATE_NAND2_LUT of GATE_NAND2 is
+ signal T : std_logic;
+begin
+-- LUT2: 2-input Look-Up Table with general output
+-- Spartan-3
+-- Xilinx HDL Libraries Guide, version 14.7
+LUT2_inst : LUT2
+generic map (
+ INIT => "0111")
+port map (
+ O => T, -- LUT general output
+ I0 => A, -- LUT input
+ I1 => B -- LUT input
+);
+-- End of LUT2_inst instantiation
+C <= T after delay_nand2;
+end architecture GATE_NAND2_LUT;
diff --git a/weirdboyjim_circuits/gate_nand3.vhd b/weirdboyjim_circuits/gate_nand3.vhd
new file mode 100755
index 0000000..f68101d
--- /dev/null
+++ b/weirdboyjim_circuits/gate_nand3.vhd
@@ -0,0 +1,35 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_NAND3 is
+generic (
+delay_nand3 : TIME := 0 ns
+);
+port (
+A,B,C : in STD_LOGIC;
+D : out STD_LOGIC
+);
+end entity GATE_NAND3;
+
+architecture GATE_NAND3_BEHAVIORAL_1 of GATE_NAND3 is
+begin
+--C <= not (A and B and C) after delay_nand3;
+D <= (A nand B) nand C after delay_nand3;
+end architecture GATE_NAND3_BEHAVIORAL_1;
+
+architecture GATE_NAND3_LUT of GATE_NAND3 is
+ signal T : std_logic;
+begin
+LUT3_inst : LUT3
+generic map (
+ INIT => "01111111")
+port map (
+ O => T,
+ I0 => A,
+ I1 => B,
+ I2 => C
+);
+D <= T after delay_nand3;
+end architecture GATE_NAND3_LUT;
diff --git a/weirdboyjim_circuits/gate_nand4.vhd b/weirdboyjim_circuits/gate_nand4.vhd
new file mode 100755
index 0000000..ae2a40d
--- /dev/null
+++ b/weirdboyjim_circuits/gate_nand4.vhd
@@ -0,0 +1,67 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 09:50:05 09/12/2021
+-- Design Name:
+-- Module Name: gate_and3 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity GATE_NAND4 is
+Generic (
+DELAY_NAND4 : time := 0 ps
+);
+Port (
+A,B,C,D : in STD_LOGIC;
+E : out STD_LOGIC
+);
+end GATE_NAND4;
+
+architecture GATE_NAND4_BEHAVIORAL_1 of GATE_NAND4 is
+ signal T : std_logic;
+begin
+T <= not (A and B and C and D);
+E <= T after DELAY_NAND4;
+end GATE_NAND4_BEHAVIORAL_1;
+
+architecture GATE_NAND4_LUT of GATE_NAND4 is
+ signal T : std_logic;
+begin
+-- LUT4: 4-input Look-Up Table with general output
+-- Spartan-3
+-- Xilinx HDL Libraries Guide, version 14.7
+gate_nand4_LUT4_L : LUT4
+generic map (
+ INIT => X"7FFF")
+port map (
+ O => T, -- LUT local output
+ I0 => A, -- LUT input
+ I1 => B, -- LUT input
+ I2 => C, -- LUT input
+ I3 => D -- LUT input
+);
+-- End of LUT4_inst instantiation
+E <= T after DELAY_NAND4;
+end architecture GATE_NAND4_LUT;
diff --git a/weirdboyjim_circuits/gate_nor2.vhd b/weirdboyjim_circuits/gate_nor2.vhd
new file mode 100755
index 0000000..268f24c
--- /dev/null
+++ b/weirdboyjim_circuits/gate_nor2.vhd
@@ -0,0 +1,38 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_NOR2 is
+generic (
+delay_nor2 : TIME := 0 ns
+);
+port (
+A,B : in STD_LOGIC;
+C : out STD_LOGIC
+);
+end entity GATE_NOR2;
+
+architecture GATE_NOR2_BEHAVIORAL_1 of GATE_NOR2 is
+begin
+--C <= not (A or B) after delay_nor2;
+C <= A nor B after delay_nor2;
+end architecture GATE_NOR2_BEHAVIORAL_1;
+
+architecture GATE_NOR2_LUT of GATE_NOR2 is
+ signal T : std_logic;
+begin
+-- LUT2: 2-input Look-Up Table with general output
+-- Spartan-3
+-- Xilinx HDL Libraries Guide, version 14.7
+LUT2_inst : LUT2
+generic map (
+ INIT => "0001")
+port map (
+ O => T, -- LUT general output
+ I0 => A, -- LUT input
+ I1 => B -- LUT input
+);
+-- End of LUT2_inst instantiation
+C <= T after delay_nor2;
+end architecture GATE_NOR2_LUT;
diff --git a/weirdboyjim_circuits/gate_nor3.vhd b/weirdboyjim_circuits/gate_nor3.vhd
new file mode 100755
index 0000000..2277a9a
--- /dev/null
+++ b/weirdboyjim_circuits/gate_nor3.vhd
@@ -0,0 +1,61 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:15:22 01/08/2022
+-- Design Name:
+-- Module Name: gate_nor3 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity GATE_NOR3 is
+generic (
+ delay_nor3 : TIME := 0 ns
+);
+port (
+ A,B,C : in STD_LOGIC;
+ D : out STD_LOGIC
+);
+end entity GATE_NOR3;
+
+architecture GATE_NOR3_BEHAVIORAL_1 of GATE_NOR3 is
+begin
+--D <= not (A or B or C) after delay_nor3;
+D <= ((A nor B) nor C) after delay_nor3;
+end architecture GATE_NOR3_BEHAVIORAL_1;
+
+architecture GATE_NOR3_LUT of GATE_NOR3 is
+ signal T : std_logic;
+begin
+ LUT3_inst : LUT3
+ generic map (
+ INIT => "00000001")
+ port map (
+ O => T,
+ I0 => A,
+ I1 => B,
+ I2 => C
+ );
+ D <= T after delay_nor3;
+end architecture GATE_NOR3_LUT;
diff --git a/weirdboyjim_circuits/gate_nor4.vhd b/weirdboyjim_circuits/gate_nor4.vhd
new file mode 100755
index 0000000..ebde5e8
--- /dev/null
+++ b/weirdboyjim_circuits/gate_nor4.vhd
@@ -0,0 +1,62 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:20:48 01/08/2022
+-- Design Name:
+-- Module Name: gate_nor4 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity GATE_NOR4 is
+generic (
+ delay_nor4 : TIME := 0 ns
+);
+port (
+ A,B,C,D : in STD_LOGIC;
+ E : out STD_LOGIC
+);
+end entity GATE_NOR4;
+
+architecture GATE_NOR4_BEHAVIORAL_1 of GATE_NOR4 is
+begin
+--E <= not (A or B or C or D) after delay_nor4;
+E <= (((A nor B) nor C) nor D) after delay_nor4;
+end architecture GATE_NOR4_BEHAVIORAL_1;
+
+architecture GATE_NOR4_LUT of GATE_NOR4 is
+ signal T : std_logic;
+begin
+ LUT4_inst : LUT4
+ generic map (
+ INIT => "0000000000000001")
+ port map (
+ O => T,
+ I0 => A,
+ I1 => B,
+ I2 => C,
+ I3 => D
+ );
+ E <= T after delay_nor4;
+end architecture GATE_NOR4_LUT;
diff --git a/weirdboyjim_circuits/gate_not.vhd b/weirdboyjim_circuits/gate_not.vhd
new file mode 100755
index 0000000..b3abf38
--- /dev/null
+++ b/weirdboyjim_circuits/gate_not.vhd
@@ -0,0 +1,37 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_NOT is
+generic (
+delay_not : TIME := 0 ns
+);
+port (
+A : in STD_LOGIC;
+B : out STD_LOGIC
+);
+end entity GATE_NOT;
+
+architecture GATE_NOT_BEHAVIORAL_1 of GATE_NOT is
+begin
+B <= not A after delay_not;
+end architecture GATE_NOT_BEHAVIORAL_1;
+
+architecture GATE_NOT_LUT of GATE_NOT is
+ signal T : std_logic;
+begin
+-- LUT2: 2-input Look-Up Table with general output
+-- Spartan-3
+-- Xilinx HDL Libraries Guide, version 14.7
+LUT2_inst : LUT2
+generic map (
+ INIT => "0001")
+port map (
+ O => T, -- LUT general output
+ I0 => A, -- LUT input
+ I1 => A -- LUT input
+);
+-- End of LUT2_inst instantiation
+B <= T after delay_not;
+end architecture GATE_NOT_LUT;
diff --git a/weirdboyjim_circuits/gate_or.vhd b/weirdboyjim_circuits/gate_or.vhd
new file mode 100755
index 0000000..57297f3
--- /dev/null
+++ b/weirdboyjim_circuits/gate_or.vhd
@@ -0,0 +1,37 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_OR is
+generic (
+delay_or : TIME := 0 ns
+);
+port (
+A,B : in STD_LOGIC;
+C : out STD_LOGIC
+);
+end entity GATE_OR;
+
+architecture GATE_OR_BEHAVIORAL_1 of GATE_OR is
+begin
+C <= A or B after delay_or;
+end architecture GATE_OR_BEHAVIORAL_1;
+
+architecture GATE_OR_LUT of GATE_OR is
+ signal T : std_logic;
+begin
+-- LUT2: 2-input Look-Up Table with general output
+-- Spartan-3
+-- Xilinx HDL Libraries Guide, version 14.7
+LUT2_inst : LUT2
+generic map (
+ INIT => "1110")
+port map (
+ O => T, -- LUT general output
+ I0 => A, -- LUT input
+ I1 => B -- LUT input
+);
+-- End of LUT2_inst instantiation
+C <= T after delay_or;
+end architecture GATE_OR_LUT;
diff --git a/weirdboyjim_circuits/gate_or2_bar.vhd b/weirdboyjim_circuits/gate_or2_bar.vhd
new file mode 100755
index 0000000..fe48e0b
--- /dev/null
+++ b/weirdboyjim_circuits/gate_or2_bar.vhd
@@ -0,0 +1,35 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity GATE_OR2_BAR is
+generic (
+delay_or2_bar : TIME := 0 ps
+);
+port (
+A,B : in STD_LOGIC;
+C : out STD_LOGIC
+);
+end entity GATE_OR2_BAR;
+
+architecture GATE_OR2_BAR_BEHAVIORAL_1 of GATE_OR2_BAR is
+begin
+C <= (not A) or (not B) after delay_or2_bar;
+end architecture GATE_OR2_BAR_BEHAVIORAL_1;
+
+architecture GATE_OR2_BAR_LUT of GATE_OR2_BAR is
+ signal T,A_not,B_not : std_logic;
+begin
+A_not <= not A;
+B_not <= not B;
+LUT2_inst : LUT2
+generic map (
+ INIT => "1110")
+port map (
+ O => T,
+ I0 => A_not,
+ I1 => B_not
+);
+C <= T after delay_or2_bar;
+end architecture GATE_OR2_BAR_LUT;
diff --git a/weirdboyjim_circuits/gate_xnor.vhd b/weirdboyjim_circuits/gate_xnor.vhd
new file mode 100755
index 0000000..99a4eba
--- /dev/null
+++ b/weirdboyjim_circuits/gate_xnor.vhd
@@ -0,0 +1,50 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity GATE_XNOR is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end entity GATE_XNOR;
+
+architecture GATE_XNOR_BEHAVIORAL_1 of GATE_XNOR is
+component GAND is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GOR is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GOR;
+component GN is
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc,sd,se,sf,sg: STD_LOGIC;
+begin
+g1: GN port map (A,sa);
+g2: GN port map (B,sb);
+g3: GAND port map (A,B,sc);
+g4: GAND port map (sa,sb,sd);
+g5: GOR port map (sc,sd,C);
+end architecture GATE_XNOR_BEHAVIORAL_1;
+
+architecture GATE_XNOR_LUT of GATE_XNOR is
+component GAND is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GOR is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GOR;
+component GN is
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_LUT);
+for all : GOR use entity WORK.GATE_OR(GATE_OR_LUT);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_LUT);
+signal sa,sb,sc,sd,se,sf,sg: STD_LOGIC;
+begin
+g1: GN port map (A,sa);
+g2: GN port map (B,sb);
+g3: GAND port map (A,B,sc);
+g4: GAND port map (sa,sb,sd);
+g5: GOR port map (sc,sd,C);
+end architecture GATE_XNOR_LUT;
diff --git a/weirdboyjim_circuits/gate_xor.vhd b/weirdboyjim_circuits/gate_xor.vhd
new file mode 100755
index 0000000..abb3882
--- /dev/null
+++ b/weirdboyjim_circuits/gate_xor.vhd
@@ -0,0 +1,51 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity GATE_XOR is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end entity GATE_XOR;
+
+architecture GATE_XOR_BEHAVIORAL_1 of GATE_XOR is
+component GAND is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GOR is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GOR;
+component GN is
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc,sd: STD_LOGIC;
+begin
+g1: GN port map (A,sa);
+g2: GN port map (B,sb);
+g3: GAND port map (sa,B,sc);
+g4: GAND port map (A,sb,sd);
+g5: GOR port map (sc,sd,C);
+end architecture GATE_XOR_BEHAVIORAL_1;
+
+architecture GATE_XOR_BEHAVIORAL_2 of GATE_XOR is
+component GAND is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GAND;
+component GOR is
+port (A,B:in STD_LOGIC;C:out STD_LOGIC);
+end component GOR;
+component GN is
+port (A:in STD_LOGIC;B:out STD_LOGIC);
+end component GN;
+for all : GAND use entity WORK.GATE_AND(GATE_AND_BEHAVIORAL_1);
+for all : GOR use entity WORK.GATE_OR(GATE_OR_BEHAVIORAL_1);
+for all : GN use entity WORK.GATE_NOT(GATE_NOT_BEHAVIORAL_1);
+signal sa,sb,sc,sd,se: STD_LOGIC;
+begin
+g1: GN port map (A,sa);
+g2: GN port map (B,sb);
+g3: GOR port map (sa,sb,sc);
+g4: GAND port map (A,sc,sd);
+g5: GAND port map (B,sc,se);
+g6: GOR port map (sd,se,C);
+end architecture GATE_XOR_BEHAVIORAL_2;
diff --git a/weirdboyjim_circuits/ic_74hct00.vhd b/weirdboyjim_circuits/ic_74hct00.vhd
new file mode 100755
index 0000000..805f2c1
--- /dev/null
+++ b/weirdboyjim_circuits/ic_74hct00.vhd
@@ -0,0 +1,62 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:10:49 11/28/2021
+-- Design Name:
+-- Module Name: ic_74hct32 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ic_74hct00 is
+port (
+ i_1a,i_1b : in std_logic;
+ o_1y : out std_logic;
+ i_2a,i_2b : in std_logic;
+ o_2y : out std_logic;
+ i_3a,i_3b : in std_logic;
+ o_3y : out std_logic;
+ i_4a,i_4b : in std_logic;
+ o_4y : out std_logic
+);
+end ic_74hct00;
+
+architecture Behavioral of ic_74hct00 is
+
+ component ic_74hct00_onegate is
+ port (
+ signal i_A,i_B : in std_logic;
+ signal o_Y : out std_logic
+ );
+ end component ic_74hct00_onegate;
+ for all : ic_74hct00_onegate use entity WORK.ic_74hct00_onegate(Behavioral);
+
+begin
+
+ u1 : ic_74hct00_onegate port map (i_A => i_1a, i_B => i_1b, o_Y => o_1y);
+ u2 : ic_74hct00_onegate port map (i_A => i_2a, i_B => i_2b, o_Y => o_2y);
+ u3 : ic_74hct00_onegate port map (i_A => i_3a, i_B => i_3b, o_Y => o_3y);
+ u4 : ic_74hct00_onegate port map (i_A => i_4a, i_B => i_4b, o_Y => o_4y);
+
+end Behavioral;
diff --git a/weirdboyjim_circuits/ic_74hct00_onegate.vhd b/weirdboyjim_circuits/ic_74hct00_onegate.vhd
new file mode 100755
index 0000000..85e06ee
--- /dev/null
+++ b/weirdboyjim_circuits/ic_74hct00_onegate.vhd
@@ -0,0 +1,74 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:41:21 11/28/2021
+-- Design Name:
+-- Module Name: ic_74hct32_onegate - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ic_74hct00_onegate is
+port (
+ signal i_A,i_B : in std_logic;
+ signal o_Y : out std_logic
+);
+end ic_74hct00_onegate;
+
+-- https://assets.nexperia.com/documents/data-sheet/74HC_HCT00.pdf
+architecture Behavioral of ic_74hct00_onegate is
+
+ component GATE_NOR2 is
+ generic (
+ delay_nor2 : TIME := 0 ps
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_NOR2;
+ for all : GATE_NOR2 use entity WORK.GATE_NOR2(GATE_NOR2_LUT);
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 0 ps
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ signal not1a,not1b,nor2out,not2,not3 : std_logic;
+
+begin
+
+ inst_not1a : GATE_NOT port map (A => i_A, B => not1a);
+ inst_not1b : GATE_NOT port map (A => i_B, B => not1b);
+ inst_nand2 : GATE_NOR2 port map (A => not1a, B => not1b, C => nor2out);
+ inst_not2 : GATE_NOT port map (A => nor2out, B => not2);
+ o_Y <= not2;
+
+end Behavioral;
diff --git a/weirdboyjim_circuits/ic_74hct161.vhd b/weirdboyjim_circuits/ic_74hct161.vhd
new file mode 100755
index 0000000..71817bb
--- /dev/null
+++ b/weirdboyjim_circuits/ic_74hct161.vhd
@@ -0,0 +1,451 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:56:14 01/08/2022
+-- Design Name:
+-- Module Name: ic_74hct161 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity ic_74hct161 is
+port (
+ signal i_d0,i_d1,i_d2,i_d3 : in std_logic;
+ signal i_cet : in std_logic;
+ signal i_cep : in std_logic;
+ signal i_pe_b : in std_logic;
+ signal i_cp : in std_logic;
+ signal i_mr_b : in std_logic;
+ signal o_q0,o_q1,o_q2,o_q3 : out std_logic;
+ signal o_tc : out std_logic
+);
+end ic_74hct161;
+
+architecture Behavioral of ic_74hct161 is
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 0 ns
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ component GATE_NAND2 is
+ generic (
+ delay_nand2 : TIME := 0 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_NAND2;
+ for all : GATE_NAND2 use entity WORK.GATE_NAND2(GATE_NAND2_LUT);
+
+ component GATE_NOR2 is
+ generic (
+ delay_nor2 : TIME := 0 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_NOR2;
+ for all : GATE_NOR2 use entity WORK.GATE_NOR2(GATE_NOR2_LUT);
+
+ component GATE_NOR3 is
+ generic (
+ delay_nor3 : TIME := 0 ns
+ );
+ port (
+ A,B,C : in STD_LOGIC;
+ D : out STD_LOGIC
+ );
+ end component GATE_NOR3;
+ for all : GATE_NOR3 use entity WORK.GATE_NOR3(GATE_NOR3_LUT);
+
+ component GATE_NOR4 is
+ generic (
+ delay_nor4 : TIME := 0 ns
+ );
+ port (
+ A,B,C,D : in STD_LOGIC;
+ E : out STD_LOGIC
+ );
+ end component GATE_NOR4;
+ for all : GATE_NOR4 use entity WORK.GATE_NOR4(GATE_NOR4_LUT);
+
+ component GATE_AND2 is
+ generic (
+ delay_and : TIME := 0 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_AND2;
+ for all : GATE_AND2 use entity WORK.GATE_AND(GATE_AND_LUT);
+
+ component GATE_XNOR2 is
+ port (
+ A,B:in STD_LOGIC;
+ C:out STD_LOGIC
+ );
+ end component GATE_XNOR2;
+ for all : GATE_XNOR2 use entity WORK.GATE_XNOR(GATE_XNOR_LUT);
+
+ component GATE_OR2 is
+ generic (
+ delay_or : TIME := 0 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_OR2;
+ for all : GATE_OR2 use entity WORK.GATE_OR(GATE_OR_LUT);
+
+ component GATE_NAND5 is
+ port (
+ signal a,b,c,d,e : in std_logic;
+ signal f : out std_logic
+ );
+ end component GATE_NAND5;
+ for all : GATE_NAND5 use entity WORK.my_nand5(Behavioral);
+
+-- component FF_D_POSITIVE_EDGE is
+-- port (
+-- S : in std_logic;
+-- R : in std_logic;
+-- C : in std_logic;
+-- D : in STD_LOGIC;
+-- Q1,Q2:out STD_LOGIC
+-- );
+-- end component FF_D_POSITIVE_EDGE;
+-- for all : FF_D_POSITIVE_EDGE use entity WORK.FF_D_POSITIVE_EDGE(D_PE_LUT_1);
+---- for all : FF_D_POSITIVE_EDGE use entity WORK.FF_D_POSITIVE_EDGE(D_PE_LUT_2);
+---- for all : FF_D_POSITIVE_EDGE use entity WORK.FF_D_POSITIVE_EDGE(D_PE_LUT_3);
+
+-- component FF_D_MASTER_SLAVE is
+-- port (
+-- C,D : in STD_LOGIC;
+-- Q1,Q2:out STD_LOGIC
+-- );
+-- end component FF_D_MASTER_SLAVE;
+-- for all : FF_D_MASTER_SLAVE use entity WORK.FF_D_MASTER_SLAVE(D_MS_LUT);
+
+-- component FF_D_GATED is
+-- generic (
+-- delay_and : TIME := 0 ns;
+-- delay_or : TIME := 0 ns;
+-- delay_not : TIME := 0 ns
+-- );
+-- port (
+-- D,E : in STD_LOGIC;
+-- Q1,Q2 : out STD_LOGIC
+-- );
+-- end component FF_D_GATED;
+-- for all : FF_D_GATED use entity WORK.FF_D_GATED(GATED_D_NOR_LUT);
+---- for all : FF_D_GATED use entity WORK.FF_D_GATED(GATED_D_NAND_LUT);
+
+-- component FF_D_DUAL_EDGE_TRIGGERED is
+-- generic (
+-- delay_not : time := 1 ns;
+-- delay_and : time := 1 ns;
+-- delay_or : time := 1 ns;
+-- delay_nor2 : time := 1 ns;
+-- delay_nand2 : time := 1 ns;
+-- delay_nand3 : time := 1 ns
+-- );
+-- port (
+-- S,R,D,C : in STD_LOGIC;
+-- Q:out STD_LOGIC
+-- );
+-- end component FF_D_DUAL_EDGE_TRIGGERED;
+-- for all : FF_D_DUAL_EDGE_TRIGGERED use entity WORK.FF_D_DUAL_EDGE_TRIGGERED(D_DET_LUT);
+
+-- component FF_E_LATCH is
+-- generic (
+-- delay_and : time := 0 ns;
+-- delay_and3 : time := 0 ns;
+-- delay_not : time := 0 ns;
+-- delay_nand2 : time := 0 ns;
+-- delay_nand3 : time := 0 ns
+-- );
+-- port (
+-- D,E_H,E_L:in STD_LOGIC;
+-- Q:out STD_LOGIC
+-- );
+-- end component FF_E_LATCH;
+----for all : FF_E_LATCH use entity WORK.FF_E_LATCH(Behavioral_E_LATCH);
+----for all : FF_E_LATCH use entity WORK.FF_E_LATCH(LUT_E_LATCH);
+--for all : FF_E_LATCH use entity WORK.FF_E_LATCH(LUT_E_LATCH_NAND);
+
+ component FF_SR_GATED is
+ generic (
+ delay_and : time := 0 ns;
+ delay_or : time := 0 ns;
+ delay_not : time := 0 ns;
+ delay_nand2 : time := 0 ns;
+ delay_nor2 : time := 0 ns
+ );
+ port (
+ S,R,E : in STD_LOGIC;
+ Q1,Q2 : inout STD_LOGIC
+ );
+ end component FF_SR_GATED;
+-- for all : FF_SR_GATED use entity WORK.FF_SR_GATED(Behavioral_GATED_SR_1);
+-- for all : FF_SR_GATED use entity WORK.FF_SR_GATED(Behavioral_GATED_SR_2);
+-- for all : FF_SR_GATED use entity WORK.FF_SR_GATED(LUT_GATED_SR_1);
+-- for all : FF_SR_GATED use entity WORK.FF_SR_GATED(LUT_GATED_SR_2);
+-- for all : FF_SR_GATED use entity WORK.FF_SR_GATED(LUT_GATED_SR_1_WON);
+ for all : FF_SR_GATED use entity WORK.FF_SR_GATED(LUT_GATED_SR_2_WON);
+
+ signal i_pe_b_not,i_pe_b_not_not,i_cp_not,i_mr_b_not,i_cet_cep_nand2,tc_not : std_logic;
+ signal ffd0_q1,ffd1_q1,ffd2_q1,ffd3_q1 : std_logic;
+ signal ffd0_q2,ffd1_q2,ffd2_q2,ffd3_q2 : std_logic;
+ signal ffd0_d,ffd1_d,ffd2_d,ffd3_d : std_logic;
+ signal g10,g11,g12,g13 : std_logic;
+ signal g20,g21,g22 : std_logic;
+ signal g30,g31,g32,g33,g34,g35,g36,g37 : std_logic;
+ signal g40,g41,g42 : std_logic;
+
+ constant delay_and : time := 4 ns;
+ constant delay_and3 : time := 0 ns;
+ constant delay_or : time := 0 ns;
+ constant delay_not : time := 0 ns;
+ constant delay_nand2 : time := 1 ns;
+ constant delay_nand3 : time := 0 ns;
+ constant delay_nor2 : time := 5 ns;
+
+begin
+
+ inst_i_pe_b_not : GATE_NOT
+ port map (A => i_pe_b, B => i_pe_b_not);
+ inst_i_cp_not : GATE_NOT
+ port map (A => i_cp, B => i_cp_not);
+ inst_i_mr_b_not : GATE_NOT
+ port map (A => i_mr_b, B => i_mr_b_not);
+
+ inst_i_cet_cep_nand2 : GATE_NAND2
+ port map (A => i_cet, B => i_cep, C => i_cet_cep_nand2);
+
+ inst_g00 : GATE_NOT
+ port map (A => i_cet_cep_nand2, B => g10);
+ inst_g01 : GATE_NOR2
+ port map (A => i_cet_cep_nand2, B => ffd0_q2, C => g11);
+ inst_g02 : GATE_NOR3
+ port map (A => i_cet_cep_nand2, B => ffd0_q2, C => ffd1_q2, D => g12);
+ inst_g03 : GATE_NOR4
+ port map (A => i_cet_cep_nand2, B => ffd0_q2, C => ffd1_q2, D => ffd2_q2, E => g13);
+
+ inst_g40 : GATE_AND2
+ port map (A => g13, B => ffd3_q2, C => g40);
+ inst_g41 : GATE_NOR2
+ port map (A => g13, B => ffd3_q2, C => g41);
+ inst_g42 : GATE_OR2
+ port map (A => g40, B => g41, C => g42);
+
+ inst_g10 : GATE_XNOR2
+ port map (A => g10, B => ffd0_q2, C => g20);
+ inst_g11 : GATE_XNOR2
+ port map (A => g11, B => ffd1_q2, C => g21);
+ inst_g12 : GATE_XNOR2
+ port map (A => g12, B => ffd2_q2, C => g22);
+
+ inst_i_pe_b_not_not : GATE_NOT
+ port map (A => i_pe_b_not, B => i_pe_b_not_not);
+
+ inst_g20 : GATE_AND2
+ port map (A => i_d0, B => i_pe_b_not, C => g30);
+ inst_g21 : GATE_AND2
+ port map (A => g20, B => i_pe_b_not_not, C => g31);
+ inst_g30 : GATE_NOR2
+ port map (A => g30, B => g31, C => ffd0_d);
+
+ inst_g22 : GATE_AND2
+ port map (A => i_d1, B => i_pe_b_not, C => g32);
+ inst_g23 : GATE_AND2
+ port map (A => g21, B => i_pe_b_not_not, C => g33);
+ inst_g31 : GATE_NOR2
+ port map (A => g32, B => g33, C => ffd1_d);
+
+ inst_g24 : GATE_AND2
+ port map (A => i_d2, B => i_pe_b_not, C => g34);
+ inst_g25 : GATE_AND2
+ port map (A => g22, B => i_pe_b_not_not, C => g35);
+ inst_g32 : GATE_NOR2
+ port map (A => g34, B => g35, C => ffd2_d);
+
+ inst_g26 : GATE_AND2
+ port map (A => i_d3, B => i_pe_b_not, C => g36);
+ inst_g27 : GATE_AND2
+ port map (A => g42, B => i_pe_b_not_not, C => g37);
+ inst_g33 : GATE_NOR2
+ port map (A => g36, B => g37, C => ffd3_d);
+
+ -- XXX conversjon SR to D, almost work
+ ffd0 : FF_SR_GATED
+ generic map (
+ delay_and => delay_and,
+ delay_or => delay_or,
+ delay_not => delay_not,
+ delay_nand2 => delay_nand2,
+ delay_nor2 => delay_nor2
+ )
+ port map (S => ffd0_d, R => not ffd0_d, Q1 => ffd0_q1, Q2 => ffd0_q2, E => i_cp_not);
+ ffd1 : FF_SR_GATED
+ generic map (
+ delay_and => delay_and,
+ delay_or => delay_or,
+ delay_not => delay_not,
+ delay_nand2 => delay_nand2,
+ delay_nor2 => delay_nor2
+ )
+ port map (S => ffd1_d, R => not ffd1_d, Q1 => ffd1_q1, Q2 => ffd1_q2, E => i_cp_not);
+ ffd2 : FF_SR_GATED
+ generic map (
+ delay_and => delay_and,
+ delay_or => delay_or,
+ delay_not => delay_not,
+ delay_nand2 => delay_nand2,
+ delay_nor2 => delay_nor2
+ )
+ port map (S => ffd2_d, R => not ffd2_d, Q1 => ffd2_q1, Q2 => ffd2_q2, E => i_cp_not);
+ ffd3 : FF_SR_GATED
+ generic map (
+ delay_and => delay_and,
+ delay_or => delay_or,
+ delay_not => delay_not,
+ delay_nand2 => delay_nand2,
+ delay_nor2 => delay_nor2
+ )
+ port map (S => ffd3_d, R => not ffd3_d, Q1 => ffd3_q1, Q2 => ffd3_q2, E => i_cp_not);
+
+-- -- XXX dont work
+-- ffd0_q2 <= not ffd0_q1;
+-- ffd0 : FF_E_LATCH
+-- generic map (
+-- delay_and => delay_and,
+-- delay_and3 => delay_and3,
+-- delay_not => delay_not,
+-- delay_nand2 => delay_nand2,
+-- delay_nand3 => delay_nand3
+-- )
+-- port map (E_H => not ffd0_d, E_L => ffd0_d, Q => ffd0_q1, D => i_cp_not);
+-- ffd1_q2 <= not ffd1_q1;
+-- ffd1 : FF_E_LATCH
+-- generic map (
+-- delay_and => delay_and,
+-- delay_and3 => delay_and3,
+-- delay_not => delay_not,
+-- delay_nand2 => delay_nand2,
+-- delay_nand3 => delay_nand3
+-- )
+-- port map (E_H => not ffd1_d, E_L => ffd1_d, Q => ffd1_q1, D => i_cp_not);
+-- ffd2_q2 <= not ffd2_q1;
+-- ffd2 : FF_E_LATCH
+-- generic map (
+-- delay_and => delay_and,
+-- delay_and3 => delay_and3,
+-- delay_not => delay_not,
+-- delay_nand2 => delay_nand2,
+-- delay_nand3 => delay_nand3
+-- )
+-- port map (E_H => not ffd2_d, E_L => ffd2_d, Q => ffd2_q1, D => i_cp_not);
+-- ffd3_q2 <= not ffd3_q1;
+-- ffd3 : FF_E_LATCH
+-- generic map (
+-- delay_and => delay_and,
+-- delay_and3 => delay_and3,
+-- delay_not => delay_not,
+-- delay_nand2 => delay_nand2,
+-- delay_nand3 => delay_nand3
+-- )
+-- port map (E_H => not ffd3_d, E_L => ffd3_d, Q => ffd3_q1, D => i_cp_not);
+
+-- ffd0_q2 <= not ffd0_q1;
+-- ffd0 : FF_D_DUAL_EDGE_TRIGGERED port map (S => not i_mr_b_not, R => i_mr_b_not, Q => ffd0_q1, C => i_cp_not, D => not ffd0_d);
+-- ffd1_q2 <= not ffd1_q1;
+-- ffd1 : FF_D_DUAL_EDGE_TRIGGERED port map (S => not i_mr_b_not, R => i_mr_b_not, Q => ffd1_q1, C => i_cp_not, D => not ffd1_d);
+-- ffd2_q2 <= not ffd2_q1;
+-- ffd2 : FF_D_DUAL_EDGE_TRIGGERED port map (S => not i_mr_b_not, R => i_mr_b_not, Q => ffd2_q1, C => i_cp_not, D => not ffd2_d);
+-- ffd3_q2 <= not ffd3_q1;
+-- ffd3 : FF_D_DUAL_EDGE_TRIGGERED port map (S => not i_mr_b_not, R => i_mr_b_not, Q => ffd3_q1, C => i_cp_not, D => not ffd3_d);
+
+-- ffd0 : FF_D_GATED
+-- port map (E => i_cp_not, D => not ffd0_d, Q1 => ffd0_q1, Q2 => ffd0_q2);
+-- ffd1 : FF_D_GATED
+-- port map (E => i_cp_not, D => not ffd1_d, Q1 => ffd1_q1, Q2 => ffd1_q2);
+-- ffd2 : FF_D_GATED
+-- port map (E => i_cp_not, D => not ffd2_d, Q1 => ffd2_q1, Q2 => ffd2_q2);
+-- ffd3 : FF_D_GATED
+-- port map (E => i_cp_not, D => not ffd3_d, Q1 => ffd3_q1, Q2 => ffd3_q2);
+
+-- ffd0 : FF_D_MASTER_SLAVE
+-- port map (C => i_cp_not, D => not ffd0_d, Q1 => ffd0_q1, Q2 => ffd0_q2);
+-- ffd1 : FF_D_MASTER_SLAVE
+-- port map (C => i_cp_not, D => not ffd1_d, Q1 => ffd1_q1, Q2 => ffd1_q2);
+-- ffd2 : FF_D_MASTER_SLAVE
+-- port map (C => i_cp_not, D => not ffd2_d, Q1 => ffd2_q1, Q2 => ffd2_q2);
+-- ffd3 : FF_D_MASTER_SLAVE
+-- port map (C => i_cp_not, D => not ffd3_d, Q1 => ffd3_q1, Q2 => ffd3_q2);
+
+-- ffd0 : FF_D_POSITIVE_EDGE
+-- port map (S => '0', R => i_mr_b_not, C => not i_cp_not, D => not ffd0_d, Q1 => ffd0_q1, Q2 => ffd0_q2);
+-- ffd1 : FF_D_POSITIVE_EDGE
+-- port map (S => '0', R => i_mr_b_not, C => not i_cp_not, D => not ffd1_d, Q1 => ffd1_q1, Q2 => ffd1_q2);
+-- ffd2 : FF_D_POSITIVE_EDGE
+-- port map (S => '0', R => i_mr_b_not, C => not i_cp_not, D => not ffd2_d, Q1 => ffd2_q1, Q2 => ffd2_q2);
+-- ffd3 : FF_D_POSITIVE_EDGE
+-- port map (S => '0', R => i_mr_b_not, C => not i_cp_not, D => not ffd3_d, Q1 => ffd3_q1, Q2 => ffd3_q2);
+
+-- ffd0_q2 <= not ffd0_q1;
+-- ffd0 : FDCE generic map (INIT => '0') port map (Q => ffd0_q1, C => not i_cp_not, CE => '1', CLR => i_mr_b_not, D => not ffd0_d);
+-- ffd1_q2 <= not ffd1_q1;
+-- ffd1 : FDCE generic map (INIT => '0') port map (Q => ffd1_q1, C => not i_cp_not, CE => '1', CLR => i_mr_b_not, D => not ffd1_d);
+-- ffd2_q2 <= not ffd2_q1;
+-- ffd2 : FDCE generic map (INIT => '0') port map (Q => ffd2_q1, C => not i_cp_not, CE => '1', CLR => i_mr_b_not, D => not ffd2_d);
+-- ffd3_q2 <= not ffd3_q1;
+-- ffd3 : FDCE generic map (INIT => '0') port map (Q => ffd3_q1, C => not i_cp_not, CE => '1', CLR => i_mr_b_not, D => not ffd3_d);
+
+ inst_o_tc : GATE_NAND5
+ port map (a => ffd0_q1, b => ffd1_q1, c => ffd2_q1, d => ffd3_q1, e => i_cet, f => tc_not);
+ inst_tc_not : GATE_NOT
+ port map (A => tc_not, B => o_tc);
+
+ inst_o_q0 : GATE_NOT
+ port map (A => ffd0_q2, B => o_q0);
+ inst_o_q1 : GATE_NOT
+ port map (A => ffd1_q2, B => o_q1);
+ inst_o_q2 : GATE_NOT
+ port map (A => ffd2_q2, B => o_q2);
+ inst_o_q3 : GATE_NOT
+ port map (A => ffd3_q2, B => o_q3);
+
+end Behavioral;
+
diff --git a/weirdboyjim_circuits/ic_74hct163.vhd b/weirdboyjim_circuits/ic_74hct163.vhd
new file mode 100755
index 0000000..c1aac7d
--- /dev/null
+++ b/weirdboyjim_circuits/ic_74hct163.vhd
@@ -0,0 +1,265 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:20:14 01/09/2022
+-- Design Name:
+-- Module Name: ic_74hct163 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity ic_74hct163 is
+port (
+ signal i_d0,i_d1,i_d2,i_d3 : in std_logic;
+ signal i_cet : in std_logic;
+ signal i_cep : in std_logic;
+ signal i_pe_b : in std_logic;
+ signal i_cp : in std_logic;
+ signal i_mr_b : in std_logic;
+ signal o_q0,o_q1,o_q2,o_q3 : out std_logic;
+ signal o_tc : out std_logic
+);
+end ic_74hct163;
+
+architecture Behavioral of ic_74hct163 is
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 0 ns
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ component GATE_NAND2 is
+ generic (
+ delay_nand2 : TIME := 0 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_NAND2;
+ for all : GATE_NAND2 use entity WORK.GATE_NAND2(GATE_NAND2_LUT);
+
+ component GATE_NOR2 is
+ generic (
+ delay_nor2 : TIME := 0 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_NOR2;
+ for all : GATE_NOR2 use entity WORK.GATE_NOR2(GATE_NOR2_LUT);
+
+ component GATE_NOR3 is
+ generic (
+ delay_nor3 : TIME := 0 ns
+ );
+ port (
+ A,B,C : in STD_LOGIC;
+ D : out STD_LOGIC
+ );
+ end component GATE_NOR3;
+ for all : GATE_NOR3 use entity WORK.GATE_NOR3(GATE_NOR3_LUT);
+
+ component GATE_NOR4 is
+ generic (
+ delay_nor4 : TIME := 0 ns
+ );
+ port (
+ A,B,C,D : in STD_LOGIC;
+ E : out STD_LOGIC
+ );
+ end component GATE_NOR4;
+ for all : GATE_NOR4 use entity WORK.GATE_NOR4(GATE_NOR4_LUT);
+
+ component GATE_AND2 is
+ generic (
+ delay_and : TIME := 0 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_AND2;
+ for all : GATE_AND2 use entity WORK.GATE_AND(GATE_AND_LUT);
+
+ component GATE_XNOR2 is
+ port (
+ A,B:in STD_LOGIC;
+ C:out STD_LOGIC
+ );
+ end component GATE_XNOR2;
+ for all : GATE_XNOR2 use entity WORK.GATE_XNOR(GATE_XNOR_LUT);
+
+ component GATE_OR2 is
+ generic (
+ delay_or : TIME := 0 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_OR2;
+ for all : GATE_OR2 use entity WORK.GATE_OR(GATE_OR_LUT);
+
+ component GATE_NAND5 is
+ port (
+ signal a,b,c,d,e : in std_logic;
+ signal f : out std_logic
+ );
+ end component GATE_NAND5;
+ for all : GATE_NAND5 use entity WORK.my_nand5(Behavioral);
+
+-- component FF_D_POSITIVE_EDGE is
+-- port (
+-- S : in std_logic;
+-- R : in std_logic;
+-- C : in std_logic;
+-- D : in STD_LOGIC;
+-- Q1,Q2:out STD_LOGIC
+-- );
+-- end component FF_D_POSITIVE_EDGE;
+---- for all : FF_D_POSITIVE_EDGE use entity WORK.FF_D_POSITIVE_EDGE(D_PE_LUT_1);
+---- for all : FF_D_POSITIVE_EDGE use entity WORK.FF_D_POSITIVE_EDGE(D_PE_LUT_2);
+-- for all : FF_D_POSITIVE_EDGE use entity WORK.FF_D_POSITIVE_EDGE(D_PE_LUT_3);
+
+ signal i_pe_b_not,i_pe_b_not_not,i_cp_not,i_mr_b_not,i_cet_cep_nand2,tc_not : std_logic;
+ signal ffd0_q1,ffd1_q1,ffd2_q1,ffd3_q1 : std_logic;
+ signal ffd0_q2,ffd1_q2,ffd2_q2,ffd3_q2 : std_logic;
+ signal ffd0_d,ffd1_d,ffd2_d,ffd3_d : std_logic;
+ signal g10,g11,g12,g13 : std_logic;
+ signal g20,g21,g22 : std_logic;
+ signal g30,g31,g32,g33,g34,g35,g36,g37 : std_logic;
+ signal g40,g41,g42 : std_logic;
+ signal g50,g51 : std_logic;
+
+begin
+
+ inst_i_mr_b_not : GATE_NOT
+ port map (A => i_mr_b, B => i_mr_b_not);
+ inst_i_pe_b_mr_b_nor2 : GATE_NOR2
+ port map (A => i_pe_b, B => i_mr_b_not, C => g50);
+ inst_g50 : GATE_NOR2
+ port map (A => i_mr_b_not, B => g50, C => g51);
+
+ inst_i_cp_not : GATE_NOT
+ port map (A => i_cp, B => i_cp_not);
+
+ inst_i_cet_cep_nand2 : GATE_NAND2
+ port map (A => i_cet, B => i_cep, C => i_cet_cep_nand2);
+
+ inst_g00 : GATE_NOT
+ port map (A => i_cet_cep_nand2, B => g10);
+ inst_g01 : GATE_NOR2
+ port map (A => i_cet_cep_nand2, B => ffd0_q2, C => g11);
+ inst_g02 : GATE_NOR3
+ port map (A => i_cet_cep_nand2, B => ffd0_q2, C => ffd1_q2, D => g12);
+ inst_g03 : GATE_NOR4
+ port map (A => i_cet_cep_nand2, B => ffd0_q2, C => ffd1_q2, D => ffd2_q2, E => g13);
+
+ inst_g40 : GATE_AND2
+ port map (A => g13, B => ffd3_q2, C => g40);
+ inst_g41 : GATE_NOR2
+ port map (A => g13, B => ffd3_q2, C => g41);
+ inst_g42 : GATE_OR2
+ port map (A => g40, B => g41, C => g42);
+
+ inst_g10 : GATE_XNOR2
+ port map (A => g10, B => ffd0_q2, C => g20);
+ inst_g11 : GATE_XNOR2
+ port map (A => g11, B => ffd1_q2, C => g21);
+ inst_g12 : GATE_XNOR2
+ port map (A => g12, B => ffd2_q2, C => g22);
+
+ inst_i_pe_b_not_not : GATE_NOT
+ port map (A => i_pe_b_not, B => i_pe_b_not_not);
+
+ inst_g20 : GATE_AND2
+ port map (A => i_d0, B => g50, C => g30);
+ inst_g21 : GATE_AND2
+ port map (A => g20, B => g51, C => g31);
+ inst_g30 : GATE_NOR2
+ port map (A => g30, B => g31, C => ffd0_d);
+
+ inst_g22 : GATE_AND2
+ port map (A => i_d1, B => g50, C => g32);
+ inst_g23 : GATE_AND2
+ port map (A => g21, B => g51, C => g33);
+ inst_g31 : GATE_NOR2
+ port map (A => g32, B => g33, C => ffd1_d);
+
+ inst_g24 : GATE_AND2
+ port map (A => i_d2, B => g50, C => g34);
+ inst_g25 : GATE_AND2
+ port map (A => g22, B => g51, C => g35);
+ inst_g32 : GATE_NOR2
+ port map (A => g34, B => g35, C => ffd2_d);
+
+ inst_g26 : GATE_AND2
+ port map (A => i_d3, B => g50, C => g36);
+ inst_g27 : GATE_AND2
+ port map (A => g42, B => g51, C => g37);
+ inst_g33 : GATE_NOR2
+ port map (A => g36, B => g37, C => ffd3_d);
+
+-- ffd0 : FF_D_POSITIVE_EDGE
+-- port map (S => not i_mr_b_not, R => i_mr_b_not, C => i_cp_not, D => not ffd0_d, Q1 => ffd0_q1, Q2 => ffd0_q2);
+-- ffd1 : FF_D_POSITIVE_EDGE
+-- port map (S => not i_mr_b_not, R => i_mr_b_not, C => i_cp_not, D => not ffd1_d, Q1 => ffd1_q1, Q2 => ffd1_q2);
+-- ffd2 : FF_D_POSITIVE_EDGE
+-- port map (S => not i_mr_b_not, R => i_mr_b_not, C => i_cp_not, D => not ffd2_d, Q1 => ffd2_q1, Q2 => ffd2_q2);
+-- ffd3 : FF_D_POSITIVE_EDGE
+-- port map (S => not i_mr_b_not, R => i_mr_b_not, C => i_cp_not, D => not ffd3_d, Q1 => ffd3_q1, Q2 => ffd3_q2);
+
+ ffd0_q2 <= not ffd0_q1;
+ ffd0 : FDCE generic map (INIT => '0') port map (Q => ffd0_q1, C => not i_cp_not, CE => '1', CLR => i_mr_b_not, D => not ffd0_d);
+ ffd1_q2 <= not ffd1_q1;
+ ffd1 : FDCE generic map (INIT => '0') port map (Q => ffd1_q1, C => not i_cp_not, CE => '1', CLR => i_mr_b_not, D => not ffd1_d);
+ ffd2_q2 <= not ffd2_q1;
+ ffd2 : FDCE generic map (INIT => '0') port map (Q => ffd2_q1, C => not i_cp_not, CE => '1', CLR => i_mr_b_not, D => not ffd2_d);
+ ffd3_q2 <= not ffd3_q1;
+ ffd3 : FDCE generic map (INIT => '0') port map (Q => ffd3_q1, C => not i_cp_not, CE => '1', CLR => i_mr_b_not, D => not ffd3_d);
+
+ inst_o_tc : GATE_NAND5
+ port map (a => ffd0_q1, b => ffd1_q1, c => ffd2_q1, d => ffd3_q1, e => i_cet, f => tc_not);
+ inst_o_tc_not : GATE_NOT
+ port map (A => tc_not, B => o_tc);
+
+ inst_o_q0 : GATE_NOT
+ port map (A => ffd0_q2, B => o_q0);
+ inst_o_q1 : GATE_NOT
+ port map (A => ffd1_q2, B => o_q1);
+ inst_o_q2 : GATE_NOT
+ port map (A => ffd2_q2, B => o_q2);
+ inst_o_q3 : GATE_NOT
+ port map (A => ffd3_q2, B => o_q3);
+
+end Behavioral;
+
diff --git a/weirdboyjim_circuits/ic_74hct164.vhd b/weirdboyjim_circuits/ic_74hct164.vhd
new file mode 100755
index 0000000..8fa10cd
--- /dev/null
+++ b/weirdboyjim_circuits/ic_74hct164.vhd
@@ -0,0 +1,108 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:52:38 12/08/2021
+-- Design Name:
+-- Module Name: ic_74hct164 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity ic_74hct164 is
+port (
+ signal i_dsa : in std_logic;
+ signal i_dsb : in std_logic;
+ signal i_cp : in std_logic;
+ signal i_mr : in std_logic;
+ signal o_q0,o_q1,o_q2,o_q3,o_q4,o_q5,o_q6,o_q7 : out std_logic
+);
+end ic_74hct164;
+
+architecture Behavioral of ic_74hct164 is
+
+ component GATE_AND is
+ generic (
+ delay_and : TIME := 0 ps
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_AND;
+ for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_LUT);
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 0 ps
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ signal q : std_logic_vector(7 downto 0);
+ signal i_mr_not,dsadsb : std_logic;
+
+begin
+
+ o_q0 <= q(0);
+ o_q1 <= q(1);
+ o_q2 <= q(2);
+ o_q3 <= q(3);
+ o_q4 <= q(4);
+ o_q5 <= q(5);
+ o_q6 <= q(6);
+ o_q7 <= q(7);
+
+ i_mr_not_inst : GATE_NOT port map (A => i_mr, B => i_mr_not);
+ gate_and_dsadsb_inst : GATE_AND port map (A => i_dsa, B => i_dsb, C => dsadsb);
+
+ g0 : for i in 0 to 7 generate
+ g0_first : if (i = 0) generate
+ FDCE_inst : FDCE
+ generic map (INIT => '1')
+ port map (
+ Q => q(0),
+ C => i_cp,
+ CE => '1',
+ CLR => i_mr_not,
+ D => dsadsb
+ );
+ end generate g0_first;
+ g0_chain : if (i > 0) generate
+ FDCE_inst : FDCE
+ generic map (INIT => '0')
+ port map (
+ Q => q(i),
+ C => i_cp,
+ CE => '1',
+ CLR => i_mr_not,
+ D => q(i-1)
+ );
+ end generate g0_chain;
+ end generate g0;
+
+end Behavioral;
diff --git a/weirdboyjim_circuits/ic_74hct193.ucf b/weirdboyjim_circuits/ic_74hct193.ucf
new file mode 100755
index 0000000..e69de29
diff --git a/weirdboyjim_circuits/ic_74hct193.vhd b/weirdboyjim_circuits/ic_74hct193.vhd
new file mode 100755
index 0000000..400f42a
--- /dev/null
+++ b/weirdboyjim_circuits/ic_74hct193.vhd
@@ -0,0 +1,280 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:46:00 11/28/2021
+-- Design Name:
+-- Module Name: ic_74hct193 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use WORK.p_package1.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity ic_74hct193 is
+port (
+ signal i_clock : in std_logic;
+ signal i_d0 : in std_logic;
+ signal i_d1 : in std_logic;
+ signal i_d2 : in std_logic;
+ signal i_d3 : in std_logic;
+ signal o_q0 : out std_logic;
+ signal o_q1 : out std_logic;
+ signal o_q2 : out std_logic;
+ signal o_q3 : out std_logic;
+ signal i_cpd : in std_logic; -- count down clock input LH
+ signal i_cpu : in std_logic; -- count up clock input LH
+ signal i_pl : in std_logic; -- asynch parallel load input LOW
+ signal o_tcu : out std_logic; -- carry - terminal count up output LOW
+ signal o_tcd : out std_logic; -- borrow - terminal count down output LOW
+ signal i_mr : in std_logic -- asynch master reset input HIGH
+);
+end ic_74hct193;
+
+architecture Behavioral of ic_74hct193 is
+
+-- component delayed_circuit is
+-- port (
+-- i_clock : in std_logic;
+-- i_input : in std_logic;
+-- o_output : out std_logic
+-- );
+-- end component delayed_circuit;
+-- for all : delayed_circuit use entity WORK.delayed_circuit(Behavioral);
+
+ component GATE_AND is
+ generic (
+ delay_and : TIME := 0 ps
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_AND;
+ for all : GATE_AND use entity WORK.GATE_AND(GATE_AND_LUT);
+
+ component GATE_NAND2 is
+ generic (
+ delay_nand2 : TIME := 0 ps
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_NAND2;
+ for all : GATE_NAND2 use entity WORK.GATE_NAND2(GATE_NAND2_LUT);
+
+ component GATE_AND3 is
+ generic (
+ delay_and3 : TIME := 0 ps
+ );
+ port (
+ A,B,C : in STD_LOGIC;
+ D : out STD_LOGIC
+ );
+ end component GATE_AND3;
+ for all : GATE_AND3 use entity WORK.GATE_AND3(GATE_AND3_LUT);
+
+ component GATE_NAND3 is
+ generic (
+ delay_nand3 : TIME := 0 ps
+ );
+ port (
+ A,B,C : in STD_LOGIC;
+ D : out STD_LOGIC
+ );
+ end component GATE_NAND3;
+ for all : GATE_NAND3 use entity WORK.GATE_NAND3(GATE_NAND3_LUT);
+
+ component GATE_AND4 is
+ generic (
+ delay_and4 : TIME := 0 ps
+ );
+ port (
+ A,B,C,D : in STD_LOGIC;
+ E : out STD_LOGIC
+ );
+ end component GATE_AND4;
+ for all : GATE_AND4 use entity WORK.GATE_AND4(GATE_AND4_LUT);
+
+ component GATE_NAND5 is
+ port (
+ signal a,b,c,d,e : in std_logic;
+ signal f : out std_logic
+ );
+ end component GATE_NAND5;
+ for all : GATE_NAND5 use entity WORK.my_nand5(Behavioral);
+
+ component GATE_NOR2 is
+ generic (
+ delay_nor2 : TIME := 0 ps
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_NOR2;
+ for all : GATE_NOR2 use entity WORK.GATE_NOR2(GATE_NOR2_LUT);
+
+ component GATE_OR2_BAR is
+ generic (
+ delay_or2_bar : TIME := 0 ps
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_OR2_BAR;
+ for all : GATE_OR2_BAR use entity WORK.GATE_OR2_BAR(GATE_OR2_BAR_LUT);
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 0 ps
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ component converted_ldcpe2fft is
+ port (
+ signal i_t : in std_logic;
+ signal i_sd,i_rd : in std_logic;
+ signal o_q1,o_q2 : out std_logic
+ );
+ end component converted_ldcpe2fft;
+ for all : converted_ldcpe2fft use entity WORK.converted_ldcpe2fft(Behavioral);
+
+ signal ff_jk_t,ff_jk_t_dc,ff_jk_t_dc_not : std_logic_vector(3 downto 0);
+ signal ff_jk_q1,ff_jk_q2,ff_jk_q1_dc : std_logic_vector(3 downto 0);
+ signal ff_jk_r : std_logic_vector(3 downto 0);
+ signal i_cpu_not,i_cpd_not,i_mr_not,i_pl_not : std_logic;
+ signal ibuf_i_cpu_not,ibuf_i_cpd_not : std_logic;
+
+ signal gate_and2_u,gate_and2_d : std_logic;
+ signal gate_and3_u,gate_and3_d : std_logic;
+ signal gate_and4_u,gate_and4_d : std_logic;
+
+ signal gate_or2_bar_slv30 : std_logic_vector(3 downto 0);
+ signal gate_nand3_slv30 : std_logic_vector(3 downto 0);
+
+ signal edre_not1_cpu,edre_not2_cpu,edre_not3_cpu,edre_not4_cpu,edre_out_cpu : std_logic;
+ signal edre_not1_cpd,edre_not2_cpd,edre_not3_cpd,edre_not4_cpd,edre_out_cpd : std_logic;
+
+begin
+
+-- g0_dc : for i in 0 to 3 generate
+-- dc : delayed_circuit
+-- port map (
+-- i_clock => 'X',
+-- i_input => ff_jk_q1(i),
+-- o_output => ff_jk_q1_dc(i)
+-- );
+-- end generate g0_dc;
+
+-- g0_dc_not : for i in 0 to 3 generate
+-- dc_not : GATE_NOT port map (A => ff_jk_t_dc(i), B => ff_jk_t_dc_not(i));
+-- end generate g0_dc_not;
+
+ o_q0 <= ff_jk_q1(0);
+ o_q1 <= ff_jk_q1(1);
+ o_q2 <= ff_jk_q1(2);
+ o_q3 <= ff_jk_q1(3);
+
+ i_mr_not_inst : GATE_NOT port map (A => i_mr, B => i_mr_not);
+ i_pl_not_inst : GATE_NOT port map (A => i_pl, B => i_pl_not);
+
+-- i_cpu_IBUF_inst : IBUF generic map (IBUF_DELAY_VALUE => "0", IFD_DELAY_VALUE => "AUTO", IOSTANDARD => "DEFAULT") port map (O => ibuf_i_cpu_not, I => i_cpu);
+-- i_cpd_IBUF_inst : IBUF generic map (IBUF_DELAY_VALUE => "0", IFD_DELAY_VALUE => "AUTO", IOSTANDARD => "DEFAULT") port map (O => ibuf_i_cpd_not, I => i_cpd);
+-- i_cpu_not_inst : GATE_NOT port map (A => ibuf_i_cpu_not, B => i_cpu_not);
+-- i_cpd_not_inst : GATE_NOT port map (A => ibuf_i_cpd_not, B => i_cpd_not);
+ i_cpu_not_inst : GATE_NOT port map (A => i_cpu, B => i_cpu_not);
+ i_cpd_not_inst : GATE_NOT port map (A => i_cpd, B => i_cpd_not);
+
+ ff_jk_first_nor2 : GATE_NOR2 port map (A => edre_out_cpu, B => edre_out_cpd, C => ff_jk_t(0));
+
+ gate_and2_u_inst1 : GATE_AND port map (A => ff_jk_q1(0), B => edre_out_cpu, C => gate_and2_u);
+ gate_and2_d_inst1 : GATE_AND port map (A => ff_jk_q2(0), B => edre_out_cpd, C => gate_and2_d);
+ ff_jk_chain1_nor2 : GATE_NOR2 port map (A => gate_and2_u, B => gate_and2_d, C => ff_jk_t(1));
+
+ gate_and3_u_inst2 : GATE_AND3 port map (A => ff_jk_q1(1), B => ff_jk_q1(0), C => edre_out_cpu, D => gate_and3_u);
+ gate_and3_d_inst2 : GATE_AND3 port map (A => ff_jk_q2(1), B => ff_jk_q2(0), C => edre_out_cpd, D => gate_and3_d);
+ ff_jk_chain2_nor2 : GATE_NOR2 port map (A => gate_and3_u, B => gate_and3_d, C => ff_jk_t(2));
+
+ gate_and4_u_inst3 : GATE_AND4 port map (A => ff_jk_q1(2), B => ff_jk_q1(1), C => ff_jk_q1(0), D => edre_out_cpu, E => gate_and4_u);
+ gate_and4_d_inst3 : GATE_AND4 port map (A => ff_jk_q2(2), B => ff_jk_q2(1), C => ff_jk_q2(0), D => edre_out_cpd, E => gate_and4_d);
+ ff_jk_chain3_nor2 : GATE_NOR2 port map (A => gate_and4_u, B => gate_and4_d, C => ff_jk_t(3));
+
+ gate_nand3_inst1 : GATE_NAND3 port map (A => i_pl_not, B => i_mr_not, C => i_d0, D => gate_nand3_slv30(0));
+ gate_nand2_inst1 : GATE_NAND2 port map (A => i_pl_not, B => gate_nand3_slv30(0), C => gate_or2_bar_slv30(0));
+
+ gate_nand3_inst2 : GATE_NAND3 port map (A => i_pl_not, B => i_mr_not, C => i_d1, D => gate_nand3_slv30(1));
+ gate_nand2_inst2 : GATE_NAND2 port map (A => i_pl_not, B => gate_nand3_slv30(1), C => gate_or2_bar_slv30(1));
+
+ gate_nand3_inst3 : GATE_NAND3 port map (A => i_pl_not, B => i_mr_not, C => i_d2, D => gate_nand3_slv30(2));
+ gate_nand2_inst3 : GATE_NAND2 port map (A => i_pl_not, B => gate_nand3_slv30(2), C => gate_or2_bar_slv30(2));
+
+ gate_nand3_inst4 : GATE_NAND3 port map (A => i_pl_not, B => i_mr_not, C => i_d3, D => gate_nand3_slv30(3));
+ gate_nand2_inst4 : GATE_NAND2 port map (A => i_pl_not, B => gate_nand3_slv30(3), C => gate_or2_bar_slv30(3));
+
+ gate_or2_bar_inst1 : GATE_OR2_BAR port map (A => i_mr_not, B => gate_or2_bar_slv30(0), C => ff_jk_r(0));
+ gate_or2_bar_inst2 : GATE_OR2_BAR port map (A => i_mr_not, B => gate_or2_bar_slv30(1), C => ff_jk_r(1));
+ gate_or2_bar_inst3 : GATE_OR2_BAR port map (A => i_mr_not, B => gate_or2_bar_slv30(2), C => ff_jk_r(2));
+ gate_or2_bar_inst4 : GATE_OR2_BAR port map (A => i_mr_not, B => gate_or2_bar_slv30(3), C => ff_jk_r(3));
+
+ gate_nand5_tcu_not : GATE_NAND5 port map (a => edre_out_cpu, b => ff_jk_q1(0), c => ff_jk_q1(1), d => ff_jk_q1(2), e => ff_jk_q1(3), f => o_tcu);
+ gate_nand5_tcd_not : GATE_NAND5 port map (a => edre_out_cpd, b => ff_jk_q2(0), c => ff_jk_q2(1), d => ff_jk_q2(2), e => ff_jk_q2(3), f => o_tcd);
+
+ ff_jk_generate : for i in 0 to 3 generate
+ ff_jk_first_generate : if (i = 0) generate
+ ff_jk_first : converted_ldcpe2fft port map (
+ i_t => ff_jk_t(0),
+ i_sd => gate_nand3_slv30(0),
+ i_rd => ff_jk_r(0),
+ o_q1 => ff_jk_q1(0),
+ o_q2 => ff_jk_q2(0)
+ );
+ end generate ff_jk_first_generate;
+ ff_jk_chain_generate : if (i > 0) generate
+ ff_jk_chain : converted_ldcpe2fft port map (
+ i_t => ff_jk_t(i),
+ i_sd => gate_nand3_slv30(i),
+ i_rd => ff_jk_r(i),
+ o_q1 => ff_jk_q1(i),
+ o_q2 => ff_jk_q2(i)
+ );
+ end generate ff_jk_chain_generate;
+ end generate ff_jk_generate;
+
+ edge_detector_re_not1_cpu_not : GATE_NOT generic map (1 ns) port map (A => i_cpu_not, B => edre_not1_cpu);
+ edge_detector_re_not2_cpu_not : GATE_NOT generic map (0 ps) port map (A => edre_not1_cpu, B => edre_not2_cpu);
+ edge_detector_re_not3_cpu_not : GATE_NOT generic map (0 ps) port map (A => edre_not2_cpu, B => edre_not3_cpu);
+ edge_detector_re_and_cpu_not : GATE_AND port map (A => i_cpu_not, B => edre_not3_cpu, C => edre_out_cpu);
+
+ edge_detector_re_not1_cpd_not : GATE_NOT generic map (1 ns) port map (A => i_cpd_not, B => edre_not1_cpd);
+ edge_detector_re_not2_cpd_not : GATE_NOT generic map (0 ps) port map (A => edre_not1_cpd, B => edre_not2_cpd);
+ edge_detector_re_not3_cpd_not : GATE_NOT generic map (0 ps) port map (A => edre_not2_cpd, B => edre_not3_cpd);
+ edge_detector_re_and_cpd_not : GATE_AND port map (A => i_cpd_not, B => edre_not3_cpd, C => edre_out_cpd);
+
+end Behavioral;
diff --git a/weirdboyjim_circuits/ic_74hct32.vhd b/weirdboyjim_circuits/ic_74hct32.vhd
new file mode 100755
index 0000000..e05e43e
--- /dev/null
+++ b/weirdboyjim_circuits/ic_74hct32.vhd
@@ -0,0 +1,62 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:10:49 11/28/2021
+-- Design Name:
+-- Module Name: ic_74hct32 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ic_74hct32 is
+port (
+ i_1a,i_1b : in std_logic;
+ o_1y : out std_logic;
+ i_2a,i_2b : in std_logic;
+ o_2y : out std_logic;
+ i_3a,i_3b : in std_logic;
+ o_3y : out std_logic;
+ i_4a,i_4b : in std_logic;
+ o_4y : out std_logic
+);
+end ic_74hct32;
+
+architecture Behavioral of ic_74hct32 is
+
+ component ic_74hct32_onegate is
+ port (
+ signal i_A,i_B : in std_logic;
+ signal o_Y : out std_logic
+ );
+ end component ic_74hct32_onegate;
+ for all : ic_74hct32_onegate use entity WORK.ic_74hct32_onegate(Behavioral);
+
+begin
+
+ u1 : ic_74hct32_onegate port map (i_A => i_1a, i_B => i_1b, o_Y => o_1y);
+ u2 : ic_74hct32_onegate port map (i_A => i_2a, i_B => i_2b, o_Y => o_2y);
+ u3 : ic_74hct32_onegate port map (i_A => i_3a, i_B => i_3b, o_Y => o_3y);
+ u4 : ic_74hct32_onegate port map (i_A => i_4a, i_B => i_4b, o_Y => o_4y);
+
+end Behavioral;
diff --git a/weirdboyjim_circuits/ic_74hct32_onegate.vhd b/weirdboyjim_circuits/ic_74hct32_onegate.vhd
new file mode 100755
index 0000000..face6fa
--- /dev/null
+++ b/weirdboyjim_circuits/ic_74hct32_onegate.vhd
@@ -0,0 +1,75 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:41:21 11/28/2021
+-- Design Name:
+-- Module Name: ic_74hct32_onegate - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ic_74hct32_onegate is
+port (
+ signal i_A,i_B : in std_logic;
+ signal o_Y : out std_logic
+);
+end ic_74hct32_onegate;
+
+-- https://assets.nexperia.com/documents/data-sheet/74HC_HCT32.pdf
+architecture Behavioral of ic_74hct32_onegate is
+
+ component GATE_NAND2 is
+ generic (
+ delay_nand2 : TIME := 0 ps
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_NAND2;
+ for all : GATE_NAND2 use entity WORK.GATE_NAND2(GATE_NAND2_LUT);
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 0 ps
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ signal not1a,not1b,nand2out,not2,not3 : std_logic;
+
+begin
+
+ inst_not1a : GATE_NOT port map (A => i_A, B => not1a);
+ inst_not1b : GATE_NOT port map (A => i_B, B => not1b);
+ inst_nand2 : GATE_NAND2 port map (A => not1a, B => not1b, C => nand2out);
+ inst_not2 : GATE_NOT port map (A => nand2out, B => not2);
+ inst_not3 : GATE_NOT port map (A => not2, B => not3);
+ o_Y <= not3;
+
+end Behavioral;
diff --git a/weirdboyjim_circuits/ic_74hct574.vhd b/weirdboyjim_circuits/ic_74hct574.vhd
new file mode 100755
index 0000000..f2a68f5
--- /dev/null
+++ b/weirdboyjim_circuits/ic_74hct574.vhd
@@ -0,0 +1,101 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:53:18 12/09/2021
+-- Design Name:
+-- Module Name: ic_74hct574 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity ic_74hct574 is
+port (
+ signal i_d0,i_d1,i_d2,i_d3,i_d4,i_d5,i_d6,i_d7 : in std_logic;
+ signal i_cp : in std_logic;
+ signal i_oe : in std_logic;
+ signal o_q0,o_q1,o_q2,o_q3,o_q4,o_q5,o_q6,o_q7 : out std_logic
+);
+end ic_74hct574;
+
+architecture Behavioral of ic_74hct574 is
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 0 ps
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ signal i_oe_not : std_logic;
+ signal d,q,q_ff : std_logic_vector(7 downto 0);
+
+begin
+
+ d(0) <= i_d0;
+ d(1) <= i_d1;
+ d(2) <= i_d2;
+ d(3) <= i_d3;
+ d(4) <= i_d4;
+ d(5) <= i_d5;
+ d(6) <= i_d6;
+ d(7) <= i_d7;
+
+ o_q0 <= q(0);
+ o_q1 <= q(1);
+ o_q2 <= q(2);
+ o_q3 <= q(3);
+ o_q4 <= q(4);
+ o_q5 <= q(5);
+ o_q6 <= q(6);
+ o_q7 <= q(7);
+
+ i_oe_not_inst : GATE_NOT port map (A => i_oe, B => i_oe_not);
+
+ ff_generate : for i in 0 to 7 generate
+ FDCE_inst : FDCE
+ generic map (INIT => '0')
+ port map (
+ Q => q_ff(i),
+ C => i_cp,
+ CE => i_oe_not,
+ CLR => i_oe,
+ D => d(i)
+ );
+ end generate ff_generate;
+
+ obuf_generate : for i in 0 to 7 generate
+ OBUFT_inst : OBUFT
+ generic map (DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW")
+ port map (
+ O => q(i),
+ I => q_ff(i),
+ T => i_oe
+ );
+ end generate obuf_generate;
+
+end Behavioral;
diff --git a/weirdboyjim_circuits/ic_sn74als165.vhd b/weirdboyjim_circuits/ic_sn74als165.vhd
new file mode 100755
index 0000000..cee5cf8
--- /dev/null
+++ b/weirdboyjim_circuits/ic_sn74als165.vhd
@@ -0,0 +1,143 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:03:08 12/09/2021
+-- Design Name:
+-- Module Name: ic_sn74als165 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity ic_sn74als165 is
+port (
+ signal i_sh_ld : in std_logic;
+ signal i_clk,i_clk_inh : in std_logic;
+ signal i_ser : in std_logic;
+ signal i_d0,i_d1,i_d2,i_d3,i_d4,i_d5,i_d6,i_d7 : in std_logic;
+ signal o_q7,o_q7_not : out std_logic
+);
+end ic_sn74als165;
+
+architecture Behavioral of ic_sn74als165 is
+
+ component GATE_NAND2 is
+ generic (
+ delay_nand2 : TIME := 0 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_NAND2;
+ for all : GATE_NAND2 use entity WORK.GATE_NAND2(GATE_NAND2_LUT);
+
+ component GATE_NOT is
+ generic (
+ delay_not : TIME := 0 ns
+ );
+ port (
+ A : in STD_LOGIC;
+ B : out STD_LOGIC
+ );
+ end component GATE_NOT;
+ for all : GATE_NOT use entity WORK.GATE_NOT(GATE_NOT_LUT);
+
+ component GATE_OR is
+ generic (
+ delay_or : TIME := 0 ns
+ );
+ port (
+ A,B : in STD_LOGIC;
+ C : out STD_LOGIC
+ );
+ end component GATE_OR;
+ for all : GATE_OR use entity WORK.GATE_OR(GATE_OR_LUT);
+
+ signal q,i_d,gate_nand2_u,gate_nand2_d,gate_nand2_u_not,gate_nand2_d_not : std_logic_vector(7 downto 0);
+ signal i_sh_ld_not,i_clk_inh_not : std_logic;
+ signal clock_pulse : std_logic;
+
+begin
+
+ o_q7 <= q(7);
+ o_q7_not <= not q(7);
+
+ i_d(0) <= i_d0;
+ i_d(1) <= i_d1;
+ i_d(2) <= i_d2;
+ i_d(3) <= i_d3;
+ i_d(4) <= i_d4;
+ i_d(5) <= i_d5;
+ i_d(6) <= i_d6;
+ i_d(7) <= i_d7;
+
+ i_sh_ld_not_inst : GATE_NOT port map (A => i_sh_ld, B => i_sh_ld_not);
+
+ i_clk_inst : GATE_OR port map (A => i_clk, B => i_clk_inh, C => clock_pulse);
+
+ generate_nand2_up : for i in 0 to 7 generate
+ nand2_up : GATE_NAND2 port map (A => i_sh_ld_not, B => i_d(i), C => gate_nand2_u(i));
+ end generate generate_nand2_up;
+
+ generate_nand2_down : for i in 0 to 7 generate
+ nand2_down : GATE_NAND2 port map (A => i_sh_ld_not, B => gate_nand2_u(i), C => gate_nand2_d(i));
+ end generate generate_nand2_down;
+
+ fdcpe_generate : for i in 0 to 7 generate
+ fdcpe_first : if (i = 0) generate
+ FDCPE_inst : FDCPE
+ generic map (INIT => '0')
+ port map (
+ Q => q(0),
+ C => clock_pulse,
+ CE => '1',
+ CLR => gate_nand2_d_not(0),
+ D => i_ser,
+ PRE => gate_nand2_u_not(0)
+ );
+ end generate fdcpe_first;
+ fdcpe_chain : if (i > 0) generate
+ FDCPE_inst : FDCPE
+ generic map (INIT => '0')
+ port map (
+ Q => q(i),
+ C => clock_pulse,
+ CE => '1',
+ CLR => gate_nand2_d_not(i),
+ D => q(i-1),
+ PRE => gate_nand2_u_not(i)
+ );
+ end generate fdcpe_chain;
+ end generate fdcpe_generate;
+
+ gate_nand2_d_not_generate : for i in 0 to 7 generate
+ gate_nand2_d_not_inst : GATE_NOT port map (A => gate_nand2_d(i), B => gate_nand2_d_not(i));
+ end generate gate_nand2_d_not_generate;
+
+ gate_nand2_u_not_generate : for i in 0 to 7 generate
+ gate_nand2_u_not_inst : GATE_NOT port map (A => gate_nand2_u(i), B => gate_nand2_u_not(i));
+ end generate gate_nand2_u_not_generate;
+
+end Behavioral;
+
diff --git a/weirdboyjim_circuits/marker_add.tcl b/weirdboyjim_circuits/marker_add.tcl
new file mode 100755
index 0000000..4f2256f
--- /dev/null
+++ b/weirdboyjim_circuits/marker_add.tcl
@@ -0,0 +1,23 @@
+# based on https://support.xilinx.com/s/article/35500?language=en_US
+# script add markers from source_file
+set source_file "wbj_ts.txt"
+if { [catch { open "$source_file" r } hfset] } {
+ puts "error, could not open file $source_file"
+} else {
+ set line "0 ps"
+ while { ![eof $hfset] } {
+ set line [gets $hfset]
+ set sl [string bytelength $line]
+ if { $sl > 0 } {
+ set re_line ""
+ regexp {^[^0]([0-9]{1,}).([pm]s)} $line re_line
+ set rel [string bytelength $re_line]
+ if { $rel > 0 } {
+ puts "marker add $re_line"
+ marker add "$re_line"
+ }
+ }
+ }
+ catch { close $hfset }
+ puts "markers add ok"
+}
diff --git a/weirdboyjim_circuits/my_lut5.vhd b/weirdboyjim_circuits/my_lut5.vhd
new file mode 100755
index 0000000..c807e1b
--- /dev/null
+++ b/weirdboyjim_circuits/my_lut5.vhd
@@ -0,0 +1,93 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 08:23:29 12/07/2021
+-- Design Name:
+-- Module Name: my_lut5 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity my_lut5 is
+generic (
+ init : std_logic_vector(0 to 31) := "00000000000000000000000000000000"
+);
+port (
+ signal i0,i1,i2,i3,i4 : in std_logic;
+ signal o : out std_logic
+);
+end entity my_lut5;
+
+-- XXX based on https://stackoverflow.com/q/38073868
+architecture Behavioral_1 of my_lut5 is -- XXX not work
+ signal h4,g4,ii : std_logic;
+begin
+
+ lut4_h4 : LUT4
+ generic map (INIT => to_bitvector(init(16 to 31)))
+ port map (O => h4, I0 => i0, I1 => i1, I2 => i2, I3 => i3);
+
+ lut4_g4 : LUT4
+ generic map (INIT => to_bitvector(init(16 to 31)))
+ port map (O => g4, I0 => i0, I1 => i1, I2 => i2, I3 => i3);
+
+ lut4_out : LUT4
+ generic map (INIT => to_bitvector(init(0 to 15)))
+ port map (O => o, I0 => g4, I1 => h4, I2 => i4, I3 => '0');
+
+end architecture Behavioral_1;
+
+---- XXX based on https://stackoverflow.com/q/38073868
+architecture Behavioral_2 of my_lut5 is -- XXX not work
+ signal hh : std_logic;
+begin
+
+ lut4_in : LUT4
+ generic map (INIT => to_bitvector(init(0 to 15)))
+ port map (O => hh, I0 => i1, I1 => i2, I2 => i3, I3 => i4);
+
+ lut4_out : LUT4
+ generic map (INIT => to_bitvector(init(16 to 31)))
+ port map (O => o, I0 => i0, I1 => i1, I2 => i2, I3 => hh);
+
+end architecture Behavioral_2;
+
+---- XXX based on Xilinx xapp466 p3 Figure5
+architecture Behavioral_3 of my_lut5 is -- XXX seems to work correctly
+ signal gg,hh : std_logic;
+ constant cinit1 : std_logic_vector(0 to 15) := init(0 to 15);
+ constant cinit2 : std_logic_vector(0 to 15) := init(16 to 31);
+begin
+
+ MUXF5_inst : MUXF5 port map (O => o, I0 => hh, I1 => gg, S => i4);
+
+ lut4_a : LUT4
+ generic map (INIT => to_bitvector(cinit1))
+ port map (O => gg, I0 => i0, I1 => i1, I2 => i2, I3 => i3);
+
+ lut4_b : LUT4
+ generic map (INIT => to_bitvector(cinit2))
+ port map (O => hh, I0 => i0, I1 => i1, I2 => i2, I3 => i3);
+
+end architecture Behavioral_3;
diff --git a/weirdboyjim_circuits/nand5.vhd b/weirdboyjim_circuits/nand5.vhd
new file mode 100755
index 0000000..8fe3fb5
--- /dev/null
+++ b/weirdboyjim_circuits/nand5.vhd
@@ -0,0 +1,65 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:15:59 12/07/2021
+-- Design Name:
+-- Module Name: nand5 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity my_nand5 is
+port (
+ signal a,b,c,d,e : in std_logic;
+ signal f : out std_logic
+);
+end my_nand5;
+
+architecture Behavioral of my_nand5 is
+
+ component my_lut5 is
+ generic (
+ init : std_logic_vector(0 to 31) := "00000000000000000000000000000000"
+ );
+ port (
+ signal i0,i1,i2,i3,i4 : in std_logic;
+ signal o : out std_logic
+ );
+ end component my_lut5;
+ for all : my_lut5 use entity WORK.my_lut5(Behavioral_3);
+
+begin
+
+ uut3 : my_lut5
+ GENERIC MAP (init => "01111111111111111111111111111111")
+ PORT MAP (
+ i0 => a,
+ i1 => b,
+ i2 => c,
+ i3 => d,
+ i4 => e,
+ o => f
+ );
+
+end Behavioral;
diff --git a/weirdboyjim_circuits/p_package1.vhd b/weirdboyjim_circuits/p_package1.vhd
new file mode 100755
index 0000000..506d7f4
--- /dev/null
+++ b/weirdboyjim_circuits/p_package1.vhd
@@ -0,0 +1,65 @@
+--
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+--
+-- To use any of the example code shown below, uncomment the lines and modify as necessary
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package p_package1 is
+
+constant P1_CV1 : integer := 10;
+constant P1_CV2 : integer := (P1_CV1*10)/2;
+
+-- type is
+-- record
+-- : std_logic_vector( 7 downto 0);
+-- : std_logic;
+-- end record;
+--
+-- Declare constants
+--
+-- constant : time := ns;
+-- constant : integer := (signal : in ) return ;
+-- procedure ( : in );
+--
+
+end p_package1;
+
+package body p_package1 is
+
+---- Example 1
+-- function (signal : in ) return is
+-- variable : ;
+-- begin
+-- := xor ;
+-- return ;
+-- end ;
+
+---- Example 2
+-- function (signal : in ;
+-- signal : in ) return is
+-- begin
+-- if ( = '1') then
+-- return ;
+-- else
+-- return 'Z';
+-- end if;
+-- end ;
+
+---- Procedure Example
+-- procedure ( : in ) is
+--
+-- begin
+--
+-- end ;
+
+end p_package1;
diff --git a/weirdboyjim_circuits/tb_converted_ldcpe2fft.vhd b/weirdboyjim_circuits/tb_converted_ldcpe2fft.vhd
new file mode 100755
index 0000000..48bb968
--- /dev/null
+++ b/weirdboyjim_circuits/tb_converted_ldcpe2fft.vhd
@@ -0,0 +1,115 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:54:33 12/05/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/weirdboyjim_circuits/tb_converted_ldcpe2fft.vhd
+-- Project Name: weirdboyjim_circuits
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: converted_ldcpe2fft
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_converted_ldcpe2fft IS
+END tb_converted_ldcpe2fft;
+
+ARCHITECTURE behavior OF tb_converted_ldcpe2fft IS
+
+COMPONENT converted_ldcpe2fft
+PORT(
+i_t : IN std_logic;
+i_sd : IN std_logic;
+i_rd : IN std_logic;
+o_q1 : OUT std_logic;
+o_q2 : OUT std_logic
+);
+END COMPONENT converted_ldcpe2fft;
+for all : converted_ldcpe2fft use entity WORK.converted_ldcpe2fft(Behavioral);
+
+--Inputs
+signal i_t : std_logic := '0';
+signal i_sd : std_logic := '0';
+signal i_rd : std_logic := '0';
+
+--Outputs
+signal o_q1 : std_logic;
+signal o_q2 : std_logic;
+
+signal clock : std_logic;
+constant clock_period : time := 10 ns;
+
+BEGIN
+
+uut: converted_ldcpe2fft PORT MAP (
+ i_t => i_t,
+ i_sd => i_sd,
+ i_rd => i_rd,
+ o_q1 => o_q1,
+ o_q2 => o_q2
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+ clock <= '0';
+ wait for clock_period/2;
+ clock <= '1';
+ wait for clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc : process
+begin
+i_sd <= '1';
+wait for clock_period*1;
+i_sd <= '0';
+i_rd <= '1';
+wait for clock_period*1;
+i_rd <= '0';
+l0 : for i in 0 to 128 loop
+ i_t <= not i_t;
+ wait for clock_period*30;
+end loop l0;
+--i_t <= '1'; wait for clock_period*9;
+--i_t <= '0'; wait for clock_period*11;
+--i_t <= '1'; wait for clock_period*13;
+--i_t <= '0'; wait for clock_period*15;
+--i_t <= '1'; wait for clock_period*17;
+--i_t <= '0'; wait for clock_period*19;
+--i_t <= '1'; wait for clock_period*21;
+--i_t <= '1'; wait for clock_period*23;
+--i_t <= '1'; wait for clock_period*25;
+wait for clock_period*200;
+i_sd <= '0';
+i_rd <= '0';
+-- insert stimulus here
+wait for clock_period;
+i_t <= '0';
+
+report "done" severity failure;
+wait;
+end process;
+
+END;
diff --git a/weirdboyjim_circuits/tb_delayed_circuit.vhd b/weirdboyjim_circuits/tb_delayed_circuit.vhd
new file mode 100755
index 0000000..850dc6c
--- /dev/null
+++ b/weirdboyjim_circuits/tb_delayed_circuit.vhd
@@ -0,0 +1,104 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:06:40 12/18/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_delayed_circuit.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: delayed_circuit
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_delayed_circuit IS
+END tb_delayed_circuit;
+
+ARCHITECTURE behavior OF tb_delayed_circuit IS
+
+COMPONENT delayed_circuit
+PORT(
+i_clock : IN std_logic;
+i_input : IN std_logic;
+o_output : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_clock : std_logic := '0';
+signal i_input : std_logic := '0';
+
+--Outputs
+signal o_output : std_logic;
+
+signal clock : std_logic;
+constant i_clock_period : time := 20 ns;
+
+BEGIN
+
+uut: delayed_circuit PORT MAP (
+i_clock => i_clock,
+i_input => i_input,
+o_output => o_output
+);
+
+-- Clock process definitions
+i_clock_process : process
+begin
+i_clock <= '0';
+wait for i_clock_period/2;
+i_clock <= '1';
+wait for i_clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc : process
+ variable v1 : std_logic_vector(7 downto 0) := "00000001";
+begin
+wait for i_clock_period*1;
+-- insert stimulus here
+--l0 : for i in 0 to 3 loop
+-- l1 : for j in 0 to 7 loop
+-- i_input <= v1(j); wait for i_clock_period*1;
+-- end loop l1;
+-- i_input <= not (v1(0) xor v1(1) xor v1(2) xor v1(3) xor v1(4) xor v1(5) xor v1(6) xor v1(7)); wait for i_clock_period*1;
+-- i_input <= (v1(0) xor v1(1) xor v1(2) xor v1(3) xor v1(4) xor v1(5) xor v1(6) xor v1(7)); wait for i_clock_period*1;
+--end loop l0;
+
+i_input <= '1'; wait for 1 ns;
+i_input <= '0'; wait for 1 ns;
+wait for 256 ns;
+i_input <= '1'; wait for 1 ns;
+i_input <= '0'; wait for 1 ns;
+i_input <= '1'; wait for 1 ns;
+i_input <= '0'; wait for 1 ns;
+i_input <= '1'; wait for 1 ns;
+i_input <= '1'; wait for 1 ns;
+
+
+report "done" severity failure;
+wait;
+end process;
+
+END;
diff --git a/weirdboyjim_circuits/tb_ff_d_det.vhd b/weirdboyjim_circuits/tb_ff_d_det.vhd
new file mode 100755
index 0000000..f26378a
--- /dev/null
+++ b/weirdboyjim_circuits/tb_ff_d_det.vhd
@@ -0,0 +1,119 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 23:54:03 12/17/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/weirdboyjim_circuits/tb_ff_d_det.vhd
+-- Project Name: weirdboyjim_circuits
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: FF_D_DUAL_EDGE_TRIGGERED
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ff_d_det IS
+END tb_ff_d_det;
+
+ARCHITECTURE behavior OF tb_ff_d_det IS
+
+COMPONENT FF_D_DUAL_EDGE_TRIGGERED
+PORT(
+D : IN std_logic;
+C : IN std_logic;
+Q : OUT std_logic
+);
+END COMPONENT FF_D_DUAL_EDGE_TRIGGERED;
+for all : FF_D_DUAL_EDGE_TRIGGERED use entity WORK.FF_D_DUAL_EDGE_TRIGGERED(D_DET_LUT);
+--for all : FF_D_DUAL_EDGE_TRIGGERED use entity WORK.FF_D_DUAL_EDGE_TRIGGERED(Behavioral_D_DET);
+
+--Inputs
+signal D : std_logic := '0';
+signal C : std_logic := '0';
+
+--Outputs
+signal Q : std_logic;
+
+signal clock : std_logic;
+constant clock_period : time := 20 ns;
+
+BEGIN
+
+uut: FF_D_DUAL_EDGE_TRIGGERED PORT MAP (
+D => D,
+C => C,
+Q => Q
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+C <= clock;
+-- Stimulus process
+stim_proc : process
+begin
+wait for clock_period*10;
+-- insert stimulus here
+D <= '1'; wait for clock_period*1;
+D <= '0'; wait for clock_period*1;
+D <= '1'; wait for clock_period*1;
+D <= '0'; wait for clock_period*1;
+D <= '1'; wait for clock_period*1;
+D <= '0'; wait for clock_period*1;
+D <= '1'; wait for clock_period*1;
+D <= 'U'; wait for clock_period*10.5;
+D <= '1'; wait for clock_period*0.5;
+D <= '0'; wait for clock_period*0.5;
+D <= '1'; wait for clock_period*0.5;
+D <= '0'; wait for clock_period*0.5;
+D <= '1'; wait for clock_period*0.5;
+D <= '0'; wait for clock_period*0.5;
+D <= '1'; wait for clock_period*0.5;
+D <= 'U'; wait for clock_period*10.5;
+D <= '1'; wait for clock_period*0.5;
+D <= '0'; wait for clock_period*1.5;
+D <= '1'; wait for clock_period*0.5;
+D <= '0'; wait for clock_period*1.5;
+D <= '1'; wait for clock_period*0.5;
+D <= '0'; wait for clock_period*1.5;
+D <= '1'; wait for clock_period*0.5;
+D <= 'U'; wait for clock_period*10.5;
+D <= '1'; wait for clock_period*1.5;
+D <= '0'; wait for clock_period*0.5;
+D <= '1'; wait for clock_period*1.5;
+D <= '0'; wait for clock_period*0.5;
+D <= '1'; wait for clock_period*1.5;
+D <= '0'; wait for clock_period*0.5;
+D <= '1'; wait for clock_period*1.5;
+
+report "done" severity failure;
+wait;
+end process;
+
+END;
diff --git a/weirdboyjim_circuits/tb_ff_d_gated.vhd b/weirdboyjim_circuits/tb_ff_d_gated.vhd
new file mode 100755
index 0000000..37513b6
--- /dev/null
+++ b/weirdboyjim_circuits/tb_ff_d_gated.vhd
@@ -0,0 +1,118 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:47:57 12/15/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/weirdboyjim_circuits/tb_ff_d_gated.vhd
+-- Project Name: weirdboyjim_circuits
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: FF_D_GATED
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ff_d_gated IS
+END tb_ff_d_gated;
+
+ARCHITECTURE behavior OF tb_ff_d_gated IS
+
+COMPONENT FF_D_GATED
+GENERIC (
+delay_and : TIME := 0 ns;
+delay_or : TIME := 0 ns;
+delay_not : TIME := 0 ns
+);
+PORT (
+D : IN std_logic;
+E : IN std_logic;
+Q1 : INOUT std_logic;
+Q2 : INOUT std_logic
+);
+END COMPONENT FF_D_GATED;
+--for all : FF_D_GATED use entity work.FF_D_GATED(GATED_D_NOR_LUT);
+--for all : FF_D_GATED use entity work.FF_D_GATED(Behavioral_GATED_D_NOR);
+--for all : FF_D_GATED use entity work.FF_D_GATED(GATED_D_NAND_LUT);
+for all : FF_D_GATED use entity work.FF_D_GATED(Behavioral_GATED_D_NAND);
+
+--Inputs
+signal D : std_logic := '0';
+signal E : std_logic := '0';
+
+--Out
+signal Q1 : std_logic;
+signal Q2 : std_logic;
+
+signal clock : std_logic;
+constant clock_period : time := 20 ns;
+
+BEGIN
+
+uut: FF_D_GATED
+GENERIC MAP (
+delay_and => 0 ns,
+delay_or => 0 ns,
+delay_not => 0 ns
+)
+PORT MAP (
+D => D,
+E => E,
+Q1 => Q1,
+Q2 => Q2
+);
+
+-- Clock process definitions
+clock_process : process
+begin
+ clock <= '0';
+ wait for clock_period/2;
+ clock <= '1';
+ wait for clock_period/2;
+end process;
+
+-- Stimulus process
+stim_proc : process
+begin
+-- insert stimulus here
+E <= '1'; wait for clock_period*1;
+D <= '1'; wait for clock_period*0.6;
+D <= '0'; wait for clock_period*0.4;
+E <= '0'; wait for clock_period*1;
+
+E <= '1'; wait for clock_period*1;
+D <= '1'; wait for clock_period*0.6;
+E <= '0'; wait for clock_period*0.4;
+D <= '0'; wait for clock_period*1;
+
+--D <= '1'; wait for clock_period*1;
+--D <= '0'; wait for clock_period*1;
+--D <= '1'; wait for clock_period*1;
+--D <= '0'; wait for clock_period*1;
+--D <= '1'; wait for clock_period*1;
+--D <= '0'; wait for clock_period*1;
+--D <= '1'; wait for clock_period*1;
+
+report "done" severity failure;
+end process;
+
+END;
diff --git a/weirdboyjim_circuits/tb_ff_d_ms.vhd b/weirdboyjim_circuits/tb_ff_d_ms.vhd
new file mode 100755
index 0000000..8424a8f
--- /dev/null
+++ b/weirdboyjim_circuits/tb_ff_d_ms.vhd
@@ -0,0 +1,105 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 23:16:03 12/17/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/weirdboyjim_circuits/tb_ff_d_ms.vhd
+-- Project Name: weirdboyjim_circuits
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: FF_D_MASTER_SLAVE
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ff_d_ms IS
+END tb_ff_d_ms;
+
+ARCHITECTURE behavior OF tb_ff_d_ms IS
+
+COMPONENT FF_D_MASTER_SLAVE
+PORT(
+C : IN std_logic;
+D : IN std_logic;
+Q1 : INOUT std_logic;
+Q2 : INOUT std_logic
+);
+END COMPONENT FF_D_MASTER_SLAVE;
+--for all : FF_D_MASTER_SLAVE use entity WORK.FF_D_MASTER_SLAVE(Behavioral_D_MS);
+for all : FF_D_MASTER_SLAVE use entity WORK.FF_D_MASTER_SLAVE(D_MS_LUT);
+
+--Inputs
+signal C : std_logic := '0';
+signal D : std_logic := '0';
+
+--BiDirs
+signal Q1 : std_logic;
+signal Q2 : std_logic;
+
+signal clock : std_logic;
+constant clock_period : time := 20 ns;
+
+BEGIN
+
+uut: FF_D_MASTER_SLAVE PORT MAP (
+C => C,
+D => D,
+Q1 => Q1,
+Q2 => Q2
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+C <= clock;
+
+-- Stimulus process
+stim_proc : process
+begin
+wait for clock_period*11;
+-- insert stimulus here
+D <= '1'; wait for clock_period*0.5;
+D <= '0'; wait for clock_period*0.5;
+D <= '1'; wait for clock_period*0.5;
+D <= '0'; wait for clock_period*0.5;
+D <= '1'; wait for clock_period*0.5;
+D <= '0'; wait for clock_period*0.5;
+D <= 'U'; wait for clock_period*2;
+D <= '1'; wait for clock_period*1;
+D <= '0'; wait for clock_period*1;
+D <= '1'; wait for clock_period*1;
+D <= '0'; wait for clock_period*1;
+D <= '1'; wait for clock_period*1;
+D <= '0'; wait for clock_period*1;
+
+report "done" severity failure;
+wait;
+end process;
+
+END;
diff --git a/weirdboyjim_circuits/tb_ff_d_pe.vhd b/weirdboyjim_circuits/tb_ff_d_pe.vhd
new file mode 100755
index 0000000..01dc648
--- /dev/null
+++ b/weirdboyjim_circuits/tb_ff_d_pe.vhd
@@ -0,0 +1,239 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:04:09 06/29/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/vhdl_primitive/tb_ff_d_pe.vhd
+-- Project Name: vhdl_primitive
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: FF_D_POSITIVE_EDGE
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ff_d_pe IS
+END tb_ff_d_pe;
+
+ARCHITECTURE behavior OF tb_ff_d_pe IS
+
+-- Component Declaration for the Unit Under Test (UUT)
+
+COMPONENT FF_D_POSITIVE_EDGE
+PORT(
+S : IN std_logic;
+R : IN std_logic;
+C : IN std_logic;
+D : IN std_logic;
+Q1 : OUT std_logic;
+Q2 : OUT std_logic
+);
+END COMPONENT;
+for all : FF_D_POSITIVE_EDGE use entity WORK.FF_D_POSITIVE_EDGE(D_PE_LUT_2);
+
+--Inputs
+signal S : std_logic := '0';
+signal R : std_logic := '0';
+signal C : std_logic := '0';
+signal D : std_logic := '0';
+
+--BiDirs
+signal Q1 : std_logic;
+signal Q2 : std_logic;
+
+signal clock : std_logic;
+constant clock_period : time := 10 ns;
+
+BEGIN
+
+-- Instantiate the Unit Under Test (UUT)
+uut: FF_D_POSITIVE_EDGE PORT MAP (
+S => S,
+R => R,
+C => C,
+D => D,
+Q1 => Q1,
+Q2 => Q2
+);
+
+-- Clock process definitions
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+C <= '1';
+
+-- Stimulus process
+stim_proc: process
+begin
+
+-- insert stimulus here
+
+wait for clock_period*10;
+
+S <= '0';
+R <= '0';
+wait for 100 ns;
+d <= '1';
+wait for clock_period;
+d <= '0';
+wait for clock_period;
+wait for 444 ps;
+d <= '1';
+wait for clock_period*3;
+d <= '0';
+wait for clock_period;
+wait for 444 ps;
+d <= '1';
+wait for clock_period*3+clock_period/2+444 ps;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for clock_period*3+clock_period+444 ps;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for 1 ns;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for 6 ns;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for clock_period;
+d <= '0';
+
+-- XXX q1 on '1',q2 have '1' on RE clock and d=0
+S <= '0';
+R <= '1';
+wait for 100 ns;
+d <= '1';
+wait for clock_period;
+d <= '0';
+wait for clock_period;
+wait for 444 ps;
+d <= '1';
+wait for clock_period*3;
+d <= '0';
+wait for clock_period;
+wait for 444 ps;
+d <= '1';
+wait for clock_period*3+clock_period/2+444 ps;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for clock_period*3+clock_period+444 ps;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for 1 ns;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for 6 ns;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for clock_period;
+d <= '0';
+
+S <= '1';
+R <= '0';
+wait for 100 ns;
+d <= '1';
+wait for clock_period;
+d <= '0';
+wait for clock_period;
+wait for 444 ps;
+d <= '1';
+wait for clock_period*3;
+d <= '0';
+wait for clock_period;
+wait for 444 ps;
+d <= '1';
+wait for clock_period*3+clock_period/2+444 ps;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for clock_period*3+clock_period+444 ps;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for 1 ns;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for 6 ns;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for clock_period;
+d <= '0';
+
+-- XXX look ok, q1 on RE clock and D,q2 is q1 bar
+S <= '1';
+R <= '1';
+wait for 100 ns;
+d <= '1';
+wait for clock_period;
+d <= '0';
+wait for clock_period;
+wait for 444 ps;
+d <= '1';
+wait for clock_period*3;
+d <= '0';
+wait for clock_period;
+wait for 444 ps;
+d <= '1';
+wait for clock_period*3+clock_period/2+444 ps;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for clock_period*3+clock_period+444 ps;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for 1 ns;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for 6 ns;
+d <= '0';
+wait for clock_period;
+d <= '1';
+wait for clock_period;
+d <= '0';
+S <= '0';
+R <= '0';
+
+wait for 100 ns;
+
+wait;
+end process;
+
+END;
diff --git a/weirdboyjim_circuits/tb_gate_nand5.vhd b/weirdboyjim_circuits/tb_gate_nand5.vhd
new file mode 100755
index 0000000..dcee268
--- /dev/null
+++ b/weirdboyjim_circuits/tb_gate_nand5.vhd
@@ -0,0 +1,100 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 08:35:05 12/07/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/weirdboyjim_circuits/tb_my_lut5.vhd
+-- Project Name: weirdboyjim_circuits
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: my_lut5
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_gate_nand5 IS
+END tb_gate_nand5;
+
+ARCHITECTURE behavior OF tb_gate_nand5 IS
+
+ COMPONENT my_nand5
+ PORT(
+ a : IN std_logic;
+ b : IN std_logic;
+ c : IN std_logic;
+ d : IN std_logic;
+ e : IN std_logic;
+ f : OUT std_logic
+ );
+ END COMPONENT my_nand5;
+ for all : my_nand5 use entity WORK.my_nand5(Behavioral);
+
+ --Inputs
+ signal i0 : std_logic := '0';
+ signal i1 : std_logic := '0';
+ signal i2 : std_logic := '0';
+ signal i3 : std_logic := '0';
+ signal i4 : std_logic := '0';
+
+ --Outputs
+ signal o : std_logic;
+
+ signal vtemp : std_logic_vector(4 downto 0);
+
+BEGIN
+
+ uut1 : my_nand5
+ PORT MAP (
+ a => i0,
+ b => i1,
+ c => i2,
+ d => i3,
+ e => i4,
+ f => o
+ );
+
+ -- Stimulus process
+ stim_proc : process
+ variable temp : std_logic_vector(4 downto 0) := (others => '0');
+ begin
+ -- insert stimulus here
+ l0 : for i in 0 to 31 loop
+ temp := std_logic_vector(to_unsigned(i,5));
+ vtemp <= temp;
+ i0 <= temp(0);
+ i1 <= temp(1);
+ i2 <= temp(2);
+ i3 <= temp(3);
+ i4 <= temp(4);
+ wait for 30 ns;
+ end loop l0;
+ i0 <= 'U';
+ i1 <= 'U';
+ i2 <= 'U';
+ i3 <= 'U';
+ i4 <= 'U';
+ wait for 50 ns;
+ wait;
+ end process;
+
+END;
diff --git a/weirdboyjim_circuits/tb_gate_nor2.vhd b/weirdboyjim_circuits/tb_gate_nor2.vhd
new file mode 100755
index 0000000..74b7b76
--- /dev/null
+++ b/weirdboyjim_circuits/tb_gate_nor2.vhd
@@ -0,0 +1,110 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:02:20 12/06/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/weirdboyjim_circuits/tb_gate_nor2.vhd
+-- Project Name: weirdboyjim_circuits
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: GATE_NOR2
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_gate_nor2 IS
+END tb_gate_nor2;
+
+ARCHITECTURE behavior OF tb_gate_nor2 IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT GATE_NOR2
+ PORT(
+ A : IN std_logic;
+ B : IN std_logic;
+ C : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal A : std_logic := '0';
+ signal B : std_logic := '0';
+
+ --Outputs
+ signal C : std_logic;
+ -- No clocks detected in port list. Replace below with
+ -- appropriate port name
+
+-- constant _period : time := 10 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: GATE_NOR2 PORT MAP (
+ A => A,
+ B => B,
+ C => C
+ );
+
+ -- Clock process definitions
+-- _process :process
+-- begin
+-- <= '0';
+-- wait for _period/2;
+-- <= '1';
+-- wait for _period/2;
+-- end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ A <= 'X';
+ B <= 'X';
+ wait for 100 ns;
+ A <= '0';
+ B <= '0';
+ wait for 100 ns;
+ A <= '0';
+ B <= '1';
+ wait for 100 ns;
+ A <= '1';
+ B <= '0';
+ wait for 100 ns;
+ A <= '1';
+ B <= '1';
+ wait for 100 ns;
+ A <= 'X';
+ B <= 'X';
+ wait for 100 ns;
+-- wait for _period*10;
+
+ -- insert stimulus here
+
+ wait;
+ end process;
+
+END;
diff --git a/weirdboyjim_circuits/tb_ic_74hct00.vhd b/weirdboyjim_circuits/tb_ic_74hct00.vhd
new file mode 100755
index 0000000..62fd713
--- /dev/null
+++ b/weirdboyjim_circuits/tb_ic_74hct00.vhd
@@ -0,0 +1,140 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:22:01 11/28/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/weirdboyjim_circuits/tb_ic_74hct32.vhd
+-- Project Name: weirdboyjim_circuits
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: ic_74hct32
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ic_74hct00 IS
+END tb_ic_74hct00;
+
+ARCHITECTURE behavior OF tb_ic_74hct00 IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT ic_74hct00
+ PORT(
+ i_1a : IN std_logic;
+ i_1b : IN std_logic;
+ o_1y : OUT std_logic;
+ i_2a : IN std_logic;
+ i_2b : IN std_logic;
+ o_2y : OUT std_logic;
+ i_3a : IN std_logic;
+ i_3b : IN std_logic;
+ o_3y : OUT std_logic;
+ i_4a : IN std_logic;
+ i_4b : IN std_logic;
+ o_4y : OUT std_logic
+ );
+ END COMPONENT;
+
+ --Inputs
+ signal i_1a : std_logic := 'U';
+ signal i_1b : std_logic := 'U';
+ signal i_2a : std_logic := 'U';
+ signal i_2b : std_logic := 'U';
+ signal i_3a : std_logic := 'U';
+ signal i_3b : std_logic := 'U';
+ signal i_4a : std_logic := 'U';
+ signal i_4b : std_logic := 'U';
+
+ --Outputs
+ signal o_1y : std_logic;
+ signal o_2y : std_logic;
+ signal o_3y : std_logic;
+ signal o_4y : std_logic;
+
+ signal clock : std_logic;
+ constant clock_period : time := 20 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: ic_74hct00 PORT MAP (
+ i_1a => i_1a,
+ i_1b => i_1b,
+ o_1y => o_1y,
+ i_2a => i_2a,
+ i_2b => i_2b,
+ o_2y => o_2y,
+ i_3a => i_3a,
+ i_3b => i_3b,
+ o_3y => o_3y,
+ i_4a => i_4a,
+ i_4b => i_4b,
+ o_4y => o_4y
+ );
+
+ -- Clock process definitions
+ clock_process : process
+ begin
+ clock <= '0';
+ wait for clock_period/2;
+ clock <= '1';
+ wait for clock_period/2;
+ end process;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+ wait for clock_period * 10;
+
+ -- insert stimulus here
+
+ i_1a <= '0'; i_1b <= '0'; wait for clock_period * 10;
+ i_1a <= '0'; i_1b <= '1'; wait for clock_period * 10;
+ i_1a <= '1'; i_1b <= '0'; wait for clock_period * 10;
+ i_1a <= '1'; i_1b <= '1'; wait for clock_period * 10;
+ i_1a <= 'U'; i_1b <= 'U'; wait for clock_period * 10;
+
+ i_2a <= '0'; i_2b <= '0'; wait for clock_period * 10;
+ i_2a <= '0'; i_2b <= '1'; wait for clock_period * 10;
+ i_2a <= '1'; i_2b <= '0'; wait for clock_period * 10;
+ i_2a <= '1'; i_2b <= '1'; wait for clock_period * 10;
+ i_2a <= 'U'; i_2b <= 'U'; wait for clock_period * 10;
+
+ i_3a <= '0'; i_3b <= '0'; wait for clock_period * 10;
+ i_3a <= '0'; i_3b <= '1'; wait for clock_period * 10;
+ i_3a <= '1'; i_3b <= '0'; wait for clock_period * 10;
+ i_3a <= '1'; i_3b <= '1'; wait for clock_period * 10;
+ i_3a <= 'U'; i_3b <= 'U'; wait for clock_period * 10;
+
+ i_4a <= '0'; i_4b <= '0'; wait for clock_period * 10;
+ i_4a <= '0'; i_4b <= '1'; wait for clock_period * 10;
+ i_4a <= '1'; i_4b <= '0'; wait for clock_period * 10;
+ i_4a <= '1'; i_4b <= '1'; wait for clock_period * 10;
+ i_4a <= 'U'; i_4b <= 'U'; wait for clock_period * 10;
+
+ wait;
+ end process;
+
+END;
diff --git a/weirdboyjim_circuits/tb_ic_74hct161.vhd b/weirdboyjim_circuits/tb_ic_74hct161.vhd
new file mode 100755
index 0000000..0b3d4ec
--- /dev/null
+++ b/weirdboyjim_circuits/tb_ic_74hct161.vhd
@@ -0,0 +1,140 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:41:12 01/08/2022
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/weirdboyjim_circuits/tb_ic_74hct161.vhd
+-- Project Name: weirdboyjim_circuits
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: ic_74hct161
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ic_74hct161 IS
+END tb_ic_74hct161;
+
+ARCHITECTURE behavior OF tb_ic_74hct161 IS
+
+COMPONENT ic_74hct161
+PORT(
+i_d0 : IN std_logic;
+i_d1 : IN std_logic;
+i_d2 : IN std_logic;
+i_d3 : IN std_logic;
+i_cet : IN std_logic;
+i_cep : IN std_logic;
+i_pe_b : IN std_logic;
+i_cp : IN std_logic;
+i_mr_b : IN std_logic;
+o_q0 : OUT std_logic;
+o_q1 : OUT std_logic;
+o_q2 : OUT std_logic;
+o_q3 : OUT std_logic;
+o_tc : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_d0 : std_logic := '0';
+signal i_d1 : std_logic := '0';
+signal i_d2 : std_logic := '0';
+signal i_d3 : std_logic := '0';
+signal i_cet : std_logic := '0';
+signal i_cep : std_logic := '0';
+signal i_pe_b : std_logic := '1';
+signal i_cp : std_logic := '0';
+signal i_mr_b : std_logic := '1';
+
+--Outputs
+signal o_q0 : std_logic;
+signal o_q1 : std_logic;
+signal o_q2 : std_logic;
+signal o_q3 : std_logic;
+signal o_tc : std_logic;
+
+signal vtemp1,vtemp2 : std_logic_vector(3 downto 0);
+
+signal clock : std_logic;
+constant clock_period : time := 20 ns;
+
+BEGIN
+
+vtemp1(0) <= o_q0;
+vtemp1(1) <= o_q1;
+vtemp1(2) <= o_q2;
+vtemp1(3) <= o_q3;
+
+vtemp2(0) <= i_d0;
+vtemp2(1) <= i_d1;
+vtemp2(2) <= i_d2;
+vtemp2(3) <= i_d3;
+
+uut: ic_74hct161 PORT MAP (
+i_d0 => i_d0,
+i_d1 => i_d1,
+i_d2 => i_d2,
+i_d3 => i_d3,
+i_cet => i_cet,
+i_cep => i_cep,
+i_pe_b => i_pe_b,
+i_cp => i_cp,
+i_mr_b => i_mr_b,
+o_q0 => o_q0,
+o_q1 => o_q1,
+o_q2 => o_q2,
+o_q3 => o_q3,
+o_tc => o_tc
+);
+
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+i_cp <= clock;
+
+-- 74hc161.pdf, p6
+i_d2 <= '1' after clock_period*0.5, '0' after clock_period*4;
+i_d3 <= '1' after clock_period*0.5, '0' after clock_period*4;
+i_mr_b <= '0' after clock_period*2.25, '1' after clock_period*2.75;
+i_pe_b <= '0' after clock_period*3.125, '1' after clock_period*3.625;
+i_cep <= '1' after clock_period*3.75, '0' after clock_period*9.75, '1' after clock_period*12.75;
+i_cet <= '1' after clock_period*3.75, '0' after clock_period*12.75;
+
+-- Stimulus process
+stim_proc : process
+begin
+
+wait for clock_period*20;
+-- insert stimulus here
+report "done" severity failure;
+
+wait;
+end process;
+
+END;
diff --git a/weirdboyjim_circuits/tb_ic_74hct163.vhd b/weirdboyjim_circuits/tb_ic_74hct163.vhd
new file mode 100755
index 0000000..98646cf
--- /dev/null
+++ b/weirdboyjim_circuits/tb_ic_74hct163.vhd
@@ -0,0 +1,140 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:21:12 01/09/2022
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/weirdboyjim_circuits/tb_ic_74hct163.vhd
+-- Project Name: weirdboyjim_circuits
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: ic_74hct161
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ic_74hct163 IS
+END tb_ic_74hct163;
+
+ARCHITECTURE behavior OF tb_ic_74hct163 IS
+
+COMPONENT ic_74hct163
+PORT(
+i_d0 : IN std_logic;
+i_d1 : IN std_logic;
+i_d2 : IN std_logic;
+i_d3 : IN std_logic;
+i_cet : IN std_logic;
+i_cep : IN std_logic;
+i_pe_b : IN std_logic;
+i_cp : IN std_logic;
+i_mr_b : IN std_logic;
+o_q0 : OUT std_logic;
+o_q1 : OUT std_logic;
+o_q2 : OUT std_logic;
+o_q3 : OUT std_logic;
+o_tc : OUT std_logic
+);
+END COMPONENT;
+
+--Inputs
+signal i_d0 : std_logic := '0';
+signal i_d1 : std_logic := '0';
+signal i_d2 : std_logic := '0';
+signal i_d3 : std_logic := '0';
+signal i_cet : std_logic := '0';
+signal i_cep : std_logic := '0';
+signal i_pe_b : std_logic := '1';
+signal i_cp : std_logic := '0';
+signal i_mr_b : std_logic := '1';
+
+--Outputs
+signal o_q0 : std_logic;
+signal o_q1 : std_logic;
+signal o_q2 : std_logic;
+signal o_q3 : std_logic;
+signal o_tc : std_logic;
+
+signal vtemp1,vtemp2 : std_logic_vector(3 downto 0);
+
+signal clock : std_logic;
+constant clock_period : time := 20 ns;
+
+BEGIN
+
+vtemp1(0) <= o_q0;
+vtemp1(1) <= o_q1;
+vtemp1(2) <= o_q2;
+vtemp1(3) <= o_q3;
+
+vtemp2(0) <= i_d0;
+vtemp2(1) <= i_d1;
+vtemp2(2) <= i_d2;
+vtemp2(3) <= i_d3;
+
+uut: ic_74hct163 PORT MAP (
+i_d0 => i_d0,
+i_d1 => i_d1,
+i_d2 => i_d2,
+i_d3 => i_d3,
+i_cet => i_cet,
+i_cep => i_cep,
+i_pe_b => i_pe_b,
+i_cp => i_cp,
+i_mr_b => i_mr_b,
+o_q0 => o_q0,
+o_q1 => o_q1,
+o_q2 => o_q2,
+o_q3 => o_q3,
+o_tc => o_tc
+);
+
+clock_process :process
+begin
+clock <= '0';
+wait for clock_period/2;
+clock <= '1';
+wait for clock_period/2;
+end process;
+
+i_cp <= clock;
+
+-- 74hct163.pdf,p6
+i_d2 <= '1' after clock_period*0.5, '0' after clock_period*5;
+i_d3 <= '1' after clock_period*0.5, '0' after clock_period*5;
+i_mr_b <= '0' after clock_period*3, '1' after clock_period*3.75;
+i_pe_b <= '0' after clock_period*4, '1' after clock_period*4.625;
+i_cep <= '1' after clock_period*4.75, '0' after clock_period*10.75, '1' after clock_period*13.75;
+i_cet <= '1' after clock_period*4.75, '0' after clock_period*13.75;
+
+-- Stimulus process
+stim_proc : process
+begin
+
+wait for clock_period*20;
+-- insert stimulus here
+report "done" severity failure;
+
+wait;
+end process;
+
+END;
diff --git a/weirdboyjim_circuits/tb_ic_74hct164.vhd b/weirdboyjim_circuits/tb_ic_74hct164.vhd
new file mode 100755
index 0000000..25bd63c
--- /dev/null
+++ b/weirdboyjim_circuits/tb_ic_74hct164.vhd
@@ -0,0 +1,136 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:59:56 12/08/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/weirdboyjim_circuits/tb_ic_74hct164.vhd
+-- Project Name: weirdboyjim_circuits
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: ic_74hct164
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ic_74hct164 IS
+END tb_ic_74hct164;
+
+ARCHITECTURE behavior OF tb_ic_74hct164 IS
+
+ COMPONENT ic_74hct164
+ PORT(
+ i_dsa : IN std_logic;
+ i_dsb : IN std_logic;
+ i_cp : IN std_logic;
+ i_mr : IN std_logic;
+ o_q0 : OUT std_logic;
+ o_q1 : OUT std_logic;
+ o_q2 : OUT std_logic;
+ o_q3 : OUT std_logic;
+ o_q4 : OUT std_logic;
+ o_q5 : OUT std_logic;
+ o_q6 : OUT std_logic;
+ o_q7 : OUT std_logic
+ );
+ END COMPONENT;
+ for all : ic_74hct164 use entity WORK.ic_74hct164(Behavioral);
+
+ --Inputs
+ signal i_dsa : std_logic := '0';
+ signal i_dsb : std_logic := '0';
+ signal i_cp : std_logic := '0';
+ signal i_mr : std_logic := '0';
+
+ --Outputs
+ signal o_q0 : std_logic;
+ signal o_q1 : std_logic;
+ signal o_q2 : std_logic;
+ signal o_q3 : std_logic;
+ signal o_q4 : std_logic;
+ signal o_q5 : std_logic;
+ signal o_q6 : std_logic;
+ signal o_q7 : std_logic;
+
+ signal clock : std_logic;
+ constant clock_period : time := 20 ns;
+
+ signal vtemp : std_logic_vector(7 downto 0);
+
+BEGIN
+
+ vtemp(0) <= o_q0;
+ vtemp(1) <= o_q1;
+ vtemp(2) <= o_q2;
+ vtemp(3) <= o_q3;
+ vtemp(4) <= o_q4;
+ vtemp(5) <= o_q5;
+ vtemp(6) <= o_q6;
+ vtemp(7) <= o_q7;
+
+ uut: ic_74hct164 PORT MAP (
+ i_dsa => i_dsa,
+ i_dsb => i_dsb,
+ i_cp => i_cp,
+ i_mr => i_mr,
+ o_q0 => o_q0,
+ o_q1 => o_q1,
+ o_q2 => o_q2,
+ o_q3 => o_q3,
+ o_q4 => o_q4,
+ o_q5 => o_q5,
+ o_q6 => o_q6,
+ o_q7 => o_q7
+ );
+
+ clock_process :process
+ begin
+ clock <= '0';
+ wait for clock_period/2;
+ clock <= '1';
+ wait for clock_period/2;
+ end process;
+
+ i_cp <= clock;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ i_mr <= '0';
+ wait for 100 ns;
+ i_mr <= '0';
+ wait for clock_period*10;
+ i_mr <= '1';
+ i_dsa <= '1';
+ -- insert stimulus here
+ i_dsb <= '1'; wait for clock_period*1;
+ i_dsb <= '0'; wait for clock_period*1;
+ i_dsb <= '1'; wait for clock_period*1;
+ i_dsb <= '0'; wait for clock_period*1;
+ i_dsb <= '1'; wait for clock_period*1;
+ i_dsb <= '0'; wait for clock_period*1;
+ i_dsb <= '1'; wait for clock_period*1;
+ i_dsb <= '1'; wait for clock_period*1;
+ wait;
+ end process;
+
+END;
diff --git a/weirdboyjim_circuits/tb_ic_74hct193.vhd b/weirdboyjim_circuits/tb_ic_74hct193.vhd
new file mode 100755
index 0000000..3922e4a
--- /dev/null
+++ b/weirdboyjim_circuits/tb_ic_74hct193.vhd
@@ -0,0 +1,417 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:08:54 12/03/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/weirdboyjim_circuits/tb_ic_74hct193.vhd
+-- Project Name: weirdboyjim_circuits
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: ic_74hct193
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ic_74hct193 IS
+END tb_ic_74hct193;
+
+ARCHITECTURE behavior OF tb_ic_74hct193 IS
+
+ COMPONENT ic_74hct193
+ PORT(
+ i_clock : IN std_logic;
+ i_d0 : IN std_logic;
+ i_d1 : IN std_logic;
+ i_d2 : IN std_logic;
+ i_d3 : IN std_logic;
+ o_q0 : OUT std_logic;
+ o_q1 : OUT std_logic;
+ o_q2 : OUT std_logic;
+ o_q3 : OUT std_logic;
+ i_cpd : IN std_logic;
+ i_cpu : IN std_logic;
+ i_pl : IN std_logic;
+ o_tcu : OUT std_logic;
+ o_tcd : OUT std_logic;
+ i_mr : IN std_logic
+ );
+ END COMPONENT;
+
+ --Inputs
+ signal i_d0 : std_logic := '0';
+ signal i_d1 : std_logic := '0';
+ signal i_d2 : std_logic := '0';
+ signal i_d3 : std_logic := '0';
+ signal i_cpd : std_logic := '0';
+ signal i_cpu : std_logic := '0';
+ signal i_pl : std_logic := '0';
+ signal i_mr : std_logic := '0';
+
+ --Outputs
+ signal o_q0 : std_logic;
+ signal o_q1 : std_logic;
+ signal o_q2 : std_logic;
+ signal o_q3 : std_logic;
+ signal o_tcu : std_logic;
+ signal o_tcd : std_logic;
+
+ signal o_d03 : std_logic_vector(3 downto 0);
+
+ signal clock : std_logic;
+ constant clock_period : time := 100 ps;
+
+BEGIN
+
+ o_d03(0) <= o_q0;
+ o_d03(1) <= o_q1;
+ o_d03(2) <= o_q2;
+ o_d03(3) <= o_q3;
+
+ uut: ic_74hct193 PORT MAP (
+ i_clock => clock,
+ i_d0 => i_d0,
+ i_d1 => i_d1,
+ i_d2 => i_d2,
+ i_d3 => i_d3,
+ o_q0 => o_q0,
+ o_q1 => o_q1,
+ o_q2 => o_q2,
+ o_q3 => o_q3,
+ i_cpd => i_cpd,
+ i_cpu => i_cpu,
+ i_pl => i_pl,
+ o_tcu => o_tcu,
+ o_tcd => o_tcd,
+ i_mr => i_mr
+ );
+
+ clock_process :process
+ begin
+ clock <= '0';
+ wait for clock_period/2;
+ clock <= '1';
+ wait for clock_period/2;
+ end process;
+
+ stim_proc: process
+ begin
+ wait for clock_period*10;
+ -- insert stimulus here
+-- i_mr <= '1';
+-- i_pl <= '0';
+-- wait for clock_period*10;
+-- i_mr <= '0';
+-- i_pl <= '0';
+
+ i_cpu <= '1'; -- XXX when 0 count up
+ i_cpd <= '1'; -- XXX when 0 count down
+
+ -- XXX reset counter
+ i_mr <= '1'; wait for 10 ns; i_mr <= '0'; wait for 10 ns;
+
+ -- XXX count 0 to 15,increment on RE i_cpu, clock_period must have 100 ps
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '1'; wait for clock_period*1;
+
+ wait for clock_period * 100;
+-- i_cpu <= 'U'; -- XXX with U counter have X output
+-- i_cpd <= 'U';
+-- wait for clock_period * 100;
+ i_cpu <= '1';
+ i_cpd <= '1';
+
+ -- XXX count 15 to 0,decrement on RE i_cpd, clock_period must have 100 ps
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '1'; wait for clock_period*1;
+
+ wait for clock_period * 100;
+-- i_cpu <= 'U';
+-- i_cpd <= 'U';
+ wait for clock_period * 100;
+
+ -- XXX load 0xA to counter
+ i_pl <= '1';
+ wait for clock_period * 100;
+ i_d0 <= '0';
+ i_d1 <= '1';
+ i_d2 <= '0';
+ i_cpu <= '0' after clock_period*10,'1' after clock_period*11; -- XXX when i_pl is high, counter is halted - ok
+ i_d3 <= '1';
+ wait for clock_period * 100;
+ i_pl <= '0';
+
+ -- XXX count from loaded with i_pl,increment on RE i_cpu, clock_period must have 100 ps
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '1'; wait for clock_period*1;
+
+ wait for clock_period * 100;
+-- i_cpu <= 'U'; -- XXX with U counter have X output
+-- i_cpd <= 'U';
+-- wait for clock_period * 100;
+ i_cpu <= '1';
+ i_cpd <= '1';
+
+ -- XXX count from loaded with i_pl,decrement on RE i_cpd, clock_period must have 100 ps
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '1'; wait for clock_period*1;
+
+ -- XXX load 0x5 to counter
+ i_pl <= '1';
+ wait for clock_period * 100;
+ i_d0 <= '1';
+ i_cpu <= '0' after clock_period*10,'1' after clock_period*11; -- XXX when i_pl is high, counter is halted - ok
+ i_d1 <= '0';
+ i_d2 <= '1';
+ i_d3 <= '0';
+ wait for clock_period * 100;
+ i_pl <= '0';
+
+ -- XXX count from loaded with i_pl,increment on RE i_cpu, clock_period must have 100 ps
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '0'; wait for clock_period*1;
+ i_cpu <= '1'; wait for clock_period*100;
+ i_cpu <= '1'; wait for clock_period*1;
+
+ wait for clock_period * 100;
+-- i_cpu <= 'U'; -- XXX with U counter have X output
+-- i_cpd <= 'U';
+-- wait for clock_period * 100;
+ i_cpu <= '1';
+ i_cpd <= '1';
+
+ -- XXX count from loaded with i_pl,decrement on RE i_cpd, clock_period must have 100 ps
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '0'; wait for clock_period*1;
+ i_cpd <= '1'; wait for clock_period*100;
+ i_cpd <= '1'; wait for clock_period*1;
+
+ wait;
+ end process;
+
+END;
diff --git a/weirdboyjim_circuits/tb_ic_74hct32.vhd b/weirdboyjim_circuits/tb_ic_74hct32.vhd
new file mode 100755
index 0000000..6f850a0
--- /dev/null
+++ b/weirdboyjim_circuits/tb_ic_74hct32.vhd
@@ -0,0 +1,140 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:22:01 11/28/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/weirdboyjim_circuits/tb_ic_74hct32.vhd
+-- Project Name: weirdboyjim_circuits
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: ic_74hct32
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ic_74hct32 IS
+END tb_ic_74hct32;
+
+ARCHITECTURE behavior OF tb_ic_74hct32 IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT ic_74hct32
+ PORT(
+ i_1a : IN std_logic;
+ i_1b : IN std_logic;
+ o_1y : OUT std_logic;
+ i_2a : IN std_logic;
+ i_2b : IN std_logic;
+ o_2y : OUT std_logic;
+ i_3a : IN std_logic;
+ i_3b : IN std_logic;
+ o_3y : OUT std_logic;
+ i_4a : IN std_logic;
+ i_4b : IN std_logic;
+ o_4y : OUT std_logic
+ );
+ END COMPONENT;
+
+ --Inputs
+ signal i_1a : std_logic := 'U';
+ signal i_1b : std_logic := 'U';
+ signal i_2a : std_logic := 'U';
+ signal i_2b : std_logic := 'U';
+ signal i_3a : std_logic := 'U';
+ signal i_3b : std_logic := 'U';
+ signal i_4a : std_logic := 'U';
+ signal i_4b : std_logic := 'U';
+
+ --Outputs
+ signal o_1y : std_logic;
+ signal o_2y : std_logic;
+ signal o_3y : std_logic;
+ signal o_4y : std_logic;
+
+ signal clock : std_logic;
+ constant clock_period : time := 20 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: ic_74hct32 PORT MAP (
+ i_1a => i_1a,
+ i_1b => i_1b,
+ o_1y => o_1y,
+ i_2a => i_2a,
+ i_2b => i_2b,
+ o_2y => o_2y,
+ i_3a => i_3a,
+ i_3b => i_3b,
+ o_3y => o_3y,
+ i_4a => i_4a,
+ i_4b => i_4b,
+ o_4y => o_4y
+ );
+
+ -- Clock process definitions
+ clock_process : process
+ begin
+ clock <= '0';
+ wait for clock_period/2;
+ clock <= '1';
+ wait for clock_period/2;
+ end process;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+ wait for clock_period * 10;
+
+ -- insert stimulus here
+
+ i_1a <= '0'; i_1b <= '0'; wait for clock_period * 10;
+ i_1a <= '0'; i_1b <= '1'; wait for clock_period * 10;
+ i_1a <= '1'; i_1b <= '0'; wait for clock_period * 10;
+ i_1a <= '1'; i_1b <= '1'; wait for clock_period * 10;
+ i_1a <= 'U'; i_1b <= 'U'; wait for clock_period * 10;
+
+ i_2a <= '0'; i_2b <= '0'; wait for clock_period * 10;
+ i_2a <= '0'; i_2b <= '1'; wait for clock_period * 10;
+ i_2a <= '1'; i_2b <= '0'; wait for clock_period * 10;
+ i_2a <= '1'; i_2b <= '1'; wait for clock_period * 10;
+ i_2a <= 'U'; i_2b <= 'U'; wait for clock_period * 10;
+
+ i_3a <= '0'; i_3b <= '0'; wait for clock_period * 10;
+ i_3a <= '0'; i_3b <= '1'; wait for clock_period * 10;
+ i_3a <= '1'; i_3b <= '0'; wait for clock_period * 10;
+ i_3a <= '1'; i_3b <= '1'; wait for clock_period * 10;
+ i_3a <= 'U'; i_3b <= 'U'; wait for clock_period * 10;
+
+ i_4a <= '0'; i_4b <= '0'; wait for clock_period * 10;
+ i_4a <= '0'; i_4b <= '1'; wait for clock_period * 10;
+ i_4a <= '1'; i_4b <= '0'; wait for clock_period * 10;
+ i_4a <= '1'; i_4b <= '1'; wait for clock_period * 10;
+ i_4a <= 'U'; i_4b <= 'U'; wait for clock_period * 10;
+
+ wait;
+ end process;
+
+END;
diff --git a/weirdboyjim_circuits/tb_ic_74hct574.vhd b/weirdboyjim_circuits/tb_ic_74hct574.vhd
new file mode 100755
index 0000000..5c5a79d
--- /dev/null
+++ b/weirdboyjim_circuits/tb_ic_74hct574.vhd
@@ -0,0 +1,165 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:10:24 12/09/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/weirdboyjim_circuits/tb_ic_74hct574.vhd
+-- Project Name: weirdboyjim_circuits
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: ic_74hct574
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.math_real.ALL; -- XXX random uniform
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_ic_74hct574 IS
+END tb_ic_74hct574;
+
+ARCHITECTURE behavior OF tb_ic_74hct574 IS
+
+ COMPONENT ic_74hct574
+ PORT(
+ i_d0 : IN std_logic;
+ i_d1 : IN std_logic;
+ i_d2 : IN std_logic;
+ i_d3 : IN std_logic;
+ i_d4 : IN std_logic;
+ i_d5 : IN std_logic;
+ i_d6 : IN std_logic;
+ i_d7 : IN std_logic;
+ i_cp : IN std_logic;
+ i_oe : IN std_logic;
+ o_q0 : OUT std_logic;
+ o_q1 : OUT std_logic;
+ o_q2 : OUT std_logic;
+ o_q3 : OUT std_logic;
+ o_q4 : OUT std_logic;
+ o_q5 : OUT std_logic;
+ o_q6 : OUT std_logic;
+ o_q7 : OUT std_logic
+ );
+ END COMPONENT;
+
+ --Inputs
+ signal i_d0 : std_logic := '0';
+ signal i_d1 : std_logic := '0';
+ signal i_d2 : std_logic := '0';
+ signal i_d3 : std_logic := '0';
+ signal i_d4 : std_logic := '0';
+ signal i_d5 : std_logic := '0';
+ signal i_d6 : std_logic := '0';
+ signal i_d7 : std_logic := '0';
+ signal i_cp : std_logic := '0';
+ signal i_oe : std_logic := '0';
+
+ --Outputs
+ signal o_q0 : std_logic;
+ signal o_q1 : std_logic;
+ signal o_q2 : std_logic;
+ signal o_q3 : std_logic;
+ signal o_q4 : std_logic;
+ signal o_q5 : std_logic;
+ signal o_q6 : std_logic;
+ signal o_q7 : std_logic;
+
+ signal clock : std_logic;
+ constant clock_period : time := 20 ns;
+
+ signal temp : std_logic_vector(7 downto 0);
+
+BEGIN
+
+ uut: ic_74hct574 PORT MAP (
+ i_d0 => i_d0,
+ i_d1 => i_d1,
+ i_d2 => i_d2,
+ i_d3 => i_d3,
+ i_d4 => i_d4,
+ i_d5 => i_d5,
+ i_d6 => i_d6,
+ i_d7 => i_d7,
+ i_cp => i_cp,
+ i_oe => i_oe,
+ o_q0 => o_q0,
+ o_q1 => o_q1,
+ o_q2 => o_q2,
+ o_q3 => o_q3,
+ o_q4 => o_q4,
+ o_q5 => o_q5,
+ o_q6 => o_q6,
+ o_q7 => o_q7
+ );
+
+ clock_process :process
+ begin
+ clock <= '0';
+ wait for clock_period/2;
+ clock <= '1';
+ wait for clock_period/2;
+ end process;
+
+ i_cp <= clock;
+
+ -- Stimulus process
+ stim_proc : process
+ variable vtemp : std_logic_vector(7 downto 0);
+ variable seed1, seed2 : integer := 999;
+ variable random : integer := 0;
+ -- XXX https://vhdlwhiz.com/random-numbers/
+ impure function rand_int(min_val, max_val : integer) return integer is
+ variable r : real;
+ begin
+ uniform(seed1, seed2, r);
+ return integer(
+ round(r * real(max_val - min_val + 1) + real(min_val) - 0.5));
+ end function;
+ begin
+ wait for 100 ns;
+ wait for clock_period*1;
+ -- insert stimulus here
+ l0 : for i in 0 to 255 loop
+ vtemp := std_logic_vector(to_unsigned(i,8));
+ random := rand_int(0,255);
+ i_d0 <= vtemp(0);
+ i_d1 <= vtemp(1);
+ i_d2 <= vtemp(2);
+ i_d3 <= vtemp(3);
+ i_d4 <= vtemp(4);
+ i_d5 <= vtemp(5);
+ i_d6 <= vtemp(6);
+ i_d7 <= vtemp(7);
+ temp <= vtemp;
+ wait for clock_period*1;
+ if (random = i) then
+ i_oe <= '0';
+ else
+ i_oe <= '1';
+ end if;
+ end loop l0;
+ wait for clock_period*1;
+
+ wait;
+ end process;
+
+END;
diff --git a/weirdboyjim_circuits/tb_ic_sn74als165.vhd b/weirdboyjim_circuits/tb_ic_sn74als165.vhd
new file mode 100755
index 0000000..3fe8022
--- /dev/null
+++ b/weirdboyjim_circuits/tb_ic_sn74als165.vhd
@@ -0,0 +1,143 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:50:27 12/09/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/weirdboyjim_circuits/tb_ic_sn74als165.vhd
+-- Project Name: weirdboyjim_circuits
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: ic_sn74als165
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY tb_ic_sn74als165 IS
+END tb_ic_sn74als165;
+
+ARCHITECTURE behavior OF tb_ic_sn74als165 IS
+
+ COMPONENT ic_sn74als165
+ PORT(
+ i_sh_ld : IN std_logic;
+ i_clk : IN std_logic;
+ i_clk_inh : IN std_logic;
+ i_ser : IN std_logic;
+ i_d0 : IN std_logic;
+ i_d1 : IN std_logic;
+ i_d2 : IN std_logic;
+ i_d3 : IN std_logic;
+ i_d4 : IN std_logic;
+ i_d5 : IN std_logic;
+ i_d6 : IN std_logic;
+ i_d7 : IN std_logic;
+ o_q7 : OUT std_logic;
+ o_q7_not : OUT std_logic
+ );
+ END COMPONENT;
+
+ --Inputs
+ signal i_sh_ld : std_logic := '0';
+ signal i_clk : std_logic := '0';
+ signal i_clk_inh : std_logic := '0';
+ signal i_ser : std_logic := '0';
+ signal i_d0 : std_logic := '0';
+ signal i_d1 : std_logic := '0';
+ signal i_d2 : std_logic := '0';
+ signal i_d3 : std_logic := '0';
+ signal i_d4 : std_logic := '0';
+ signal i_d5 : std_logic := '0';
+ signal i_d6 : std_logic := '0';
+ signal i_d7 : std_logic := '0';
+
+ --Outputs
+ signal o_q7 : std_logic;
+ signal o_q7_not : std_logic;
+
+ signal clock : std_logic;
+ constant clock_period : time := 20 ns;
+
+BEGIN
+
+ uut: ic_sn74als165 PORT MAP (
+ i_sh_ld => i_sh_ld,
+ i_clk => i_clk,
+ i_clk_inh => i_clk_inh,
+ i_ser => i_ser,
+ i_d0 => i_d0,
+ i_d1 => i_d1,
+ i_d2 => i_d2,
+ i_d3 => i_d3,
+ i_d4 => i_d4,
+ i_d5 => i_d5,
+ i_d6 => i_d6,
+ i_d7 => i_d7,
+ o_q7 => o_q7,
+ o_q7_not => o_q7_not
+ );
+
+ clock_process :process
+ begin
+ clock <= '0';
+ wait for clock_period/2;
+ clock <= '1';
+ wait for clock_period/2;
+ end process;
+
+ i_clk <= clock;
+ i_clk_inh <= '1';
+
+ -- Stimulus process
+ stim_proc : process
+ begin
+ i_sh_ld <= '1';
+ wait for 100 ns;
+ i_sh_ld <= '0';
+ wait for clock_period*1;
+ i_sh_ld <= '1';
+ -- insert stimulus here
+ i_ser <= '1'; wait for clock_period*1;
+ i_ser <= '1'; wait for clock_period*1;
+ i_ser <= '0'; wait for clock_period*1;
+ i_ser <= '1'; wait for clock_period*1;
+ i_ser <= '0'; wait for clock_period*1;
+ i_ser <= '1'; wait for clock_period*1;
+ i_ser <= '0'; wait for clock_period*1;
+ i_ser <= '1'; wait for clock_period*1;
+ i_ser <= 'U';
+ wait for clock_period*10;
+ i_sh_ld <= '0';
+ i_d0 <= '1';
+ i_d1 <= '1';
+ i_d2 <= '0';
+ i_d3 <= '1';
+ i_d4 <= '0';
+ i_d5 <= '1';
+ i_d6 <= '0';
+ i_d7 <= '1';
+ wait for clock_period*1;
+ i_sh_ld <= '1';
+ wait;
+ end process;
+
+END;
diff --git a/weirdboyjim_circuits/tb_my_lut5.vhd b/weirdboyjim_circuits/tb_my_lut5.vhd
new file mode 100755
index 0000000..b2f2c64
--- /dev/null
+++ b/weirdboyjim_circuits/tb_my_lut5.vhd
@@ -0,0 +1,183 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 08:35:05 12/07/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/weirdboyjim_circuits/tb_my_lut5.vhd
+-- Project Name: weirdboyjim_circuits
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: my_lut5
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_my_lut5 IS
+END tb_my_lut5;
+
+ARCHITECTURE behavior OF tb_my_lut5 IS
+
+ COMPONENT my_lut5_1
+ GENERIC (init : std_logic_vector(0 to 31) := "00000000000000000000000000000000");
+ PORT(
+ i0 : IN std_logic;
+ i1 : IN std_logic;
+ i2 : IN std_logic;
+ i3 : IN std_logic;
+ i4 : IN std_logic;
+ o : OUT std_logic
+ );
+ END COMPONENT my_lut5_1;
+ for all : my_lut5_1 use entity WORK.my_lut5(Behavioral_1);
+
+ COMPONENT my_lut5_2
+ GENERIC (init : std_logic_vector(0 to 31) := "00000000000000000000000000000000");
+ PORT(
+ i0 : IN std_logic;
+ i1 : IN std_logic;
+ i2 : IN std_logic;
+ i3 : IN std_logic;
+ i4 : IN std_logic;
+ o : OUT std_logic
+ );
+ END COMPONENT my_lut5_2;
+ for all : my_lut5_2 use entity WORK.my_lut5(Behavioral_2);
+
+ COMPONENT my_lut5_3
+ GENERIC (init : std_logic_vector(0 to 31) := "00000000000000000000000000000000");
+ PORT(
+ i0 : IN std_logic;
+ i1 : IN std_logic;
+ i2 : IN std_logic;
+ i3 : IN std_logic;
+ i4 : IN std_logic;
+ o : OUT std_logic
+ );
+ END COMPONENT my_lut5_3;
+ for all : my_lut5_3 use entity WORK.my_lut5(Behavioral_3);
+
+ --Inputs
+ signal i0a,i0b,i0c : std_logic := '0';
+ signal i1a,i1b,i1c : std_logic := '0';
+ signal i2a,i2b,i2c : std_logic := '0';
+ signal i3a,i3b,i3c : std_logic := '0';
+ signal i4a,i4b,i4c : std_logic := '0';
+
+ --Outputs
+ signal oa,ob,oc : std_logic;
+
+ signal vtemp : std_logic_vector(4 downto 0);
+
+BEGIN
+
+ uut1 : my_lut5_1
+ GENERIC MAP (init => "10000000000000000000000000000000")
+ PORT MAP (
+ i0 => i0a,
+ i1 => i1a,
+ i2 => i2a,
+ i3 => i3a,
+ i4 => i4a,
+ o => oa
+ );
+
+ uut2 : my_lut5_2
+ GENERIC MAP (init => "10000000000000000000000000000000")
+ PORT MAP (
+ i0 => i0b,
+ i1 => i1b,
+ i2 => i2b,
+ i3 => i3b,
+ i4 => i4b,
+ o => ob
+ );
+
+ -- XXX work ok
+ uut3 : my_lut5_3
+ GENERIC MAP (init => "10000000000000000000000000000000")
+ PORT MAP (
+ i0 => i0c,
+ i1 => i1c,
+ i2 => i2c,
+ i3 => i3c,
+ i4 => i4c,
+ o => oc
+ );
+
+ -- Stimulus process
+ stim_proc : process
+ variable temp : std_logic_vector(4 downto 0) := (others => '0');
+ begin
+ -- insert stimulus here
+ l0 : for i in 0 to 31 loop
+ temp := std_logic_vector(to_unsigned(i,5));
+ vtemp <= temp;
+ i0a <= temp(0);
+ i1a <= temp(1);
+ i2a <= temp(2);
+ i3a <= temp(3);
+ i4a <= temp(4);
+ wait for 30 ns;
+ end loop l0;
+ i0a <= 'U';
+ i1a <= 'U';
+ i2a <= 'U';
+ i3a <= 'U';
+ i4a <= 'U';
+ wait for 50 ns;
+ l1 : for i in 0 to 31 loop
+ temp := std_logic_vector(to_unsigned(i,5));
+ vtemp <= temp;
+ i0b <= temp(0);
+ i1b <= temp(1);
+ i2b <= temp(2);
+ i3b <= temp(3);
+ i4b <= temp(4);
+ wait for 30 ns;
+ end loop l1;
+ i0b <= 'U';
+ i1b <= 'U';
+ i2b <= 'U';
+ i3b <= 'U';
+ i4b <= 'U';
+ wait for 50 ns;
+ l2 : for i in 0 to 31 loop
+ temp := std_logic_vector(to_unsigned(i,5));
+ vtemp <= temp;
+ i0c <= temp(0);
+ i1c <= temp(1);
+ i2c <= temp(2);
+ i3c <= temp(3);
+ i4c <= temp(4);
+ wait for 30 ns;
+ end loop l2;
+ i0c <= 'U';
+ i1c <= 'U';
+ i2c <= 'U';
+ i3c <= 'U';
+ i4c <= 'U';
+ wait for 50 ns;
+ wait;
+ end process;
+
+END;
diff --git a/weirdboyjim_circuits/tb_weirdboyjim_uart.tcl b/weirdboyjim_circuits/tb_weirdboyjim_uart.tcl
new file mode 100755
index 0000000..950d9c0
--- /dev/null
+++ b/weirdboyjim_circuits/tb_weirdboyjim_uart.tcl
@@ -0,0 +1,2 @@
+run all
+source marker_add.tcl
diff --git a/weirdboyjim_circuits/tb_weirdboyjim_uart.vhd b/weirdboyjim_circuits/tb_weirdboyjim_uart.vhd
new file mode 100755
index 0000000..05f872e
--- /dev/null
+++ b/weirdboyjim_circuits/tb_weirdboyjim_uart.vhd
@@ -0,0 +1,276 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 07:20:18 12/11/2021
+-- Design Name:
+-- Module Name: /home/user/workspace/vhdl_projects/weirdboyjim_circuits/tb_weirdboyjim_uart.vhd
+-- Project Name: weirdboyjim_circuits
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: weirdboyjim_uart
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE std.textio.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_weirdboyjim_uart IS
+END tb_weirdboyjim_uart;
+
+ARCHITECTURE behavior OF tb_weirdboyjim_uart IS
+
+COMPONENT weirdboyjim_uart
+PORT(
+signal i_reset : in std_logic;
+signal txUartClock : in std_logic;
+signal rxUartClock : in std_logic;
+signal tx : out std_logic;
+signal txData : in std_logic_vector(7 downto 0);
+signal TFcount_slv30 : std_logic_vector(3 downto 0);
+signal Rx : in std_logic;
+signal RevData : out std_logic_vector(7 downto 0)
+);
+END COMPONENT;
+
+--Inputs
+signal i_reset : std_logic;
+signal txUartClock,rxUartClock : std_logic := '0';
+signal txData : std_logic_vector(7 downto 0);
+signal TFcount_slv30 : std_logic_vector(3 downto 0);
+signal Rx : std_logic;
+
+--Outputs
+signal tx : std_logic;
+signal RevData : std_logic_vector(7 downto 0);
+
+-- Clock period definitions
+signal uartClock : std_logic;
+constant t : integer := 2**4;
+constant uartClockPeriod : time := 1 ms;
+constant txUartClock_period : time := uartClockPeriod;
+constant rxUartClock_period : time := uartClockPeriod;
+
+signal tf_flag : std_logic;
+signal tx_run,rx_run : std_logic := '0';
+
+BEGIN
+
+uut: weirdboyjim_uart PORT MAP (
+i_reset => i_reset,
+txUartClock => txUartClock,
+rxUartClock => rxUartClock,
+tx => tx,
+txData => txData,
+TFcount_slv30 => TFcount_slv30,
+Rx => Rx,
+RevData => RevData
+);
+
+-- Clock process definitions
+
+--txUartClock_process : process (uartClock,i_reset,tx_run)
+-- type states is (a,b,c);
+-- variable state : states := a;
+--begin
+-- if (i_reset = '1') then
+-- txUartClock <= '0';
+-- elsif (rising_edge(uartClock)) then
+-- case state is
+-- when a =>
+-- if (tx_run = '1') then
+-- state := b;
+-- end if;
+-- when b =>
+-- txUartClock <= '1';
+-- if (tx_run = '1') then
+-- state := c;
+-- else
+-- state := a;
+-- end if;
+-- when c =>
+-- txUartClock <= '0';
+-- if (tx_run = '1') then
+-- state := b;
+-- else
+-- state := a;
+-- end if;
+-- end case;
+-- end if;
+--end process;
+
+--rxUartClock_process : process (uartClock,rx_run)
+-- type states is (a,b,c);
+-- variable state : states := a;
+--begin
+-- if (rising_edge(uartClock)) then
+-- case state is
+-- when a =>
+-- if (rx_run = '1') then
+-- state := b;
+-- end if;
+-- when b =>
+-- rxUartClock <= '1';
+-- if (rx_run = '1') then
+-- state := c;
+-- else
+-- state := a;
+-- end if;
+-- when c =>
+-- rxUartClock <= '0';
+-- if (rx_run = '1') then
+-- state := b;
+-- else
+-- state := a;
+-- end if;
+-- end case;
+-- end if;
+--end process;
+
+txUartClock_process : txUartClock <= not txUartClock after txUartClock_period/2 when tx_run = '1' else '0';
+rxUartClock_process : rxUartClock <= not rxUartClock after rxUartClock_period/2 when rx_run = '1' else '0';
+
+uartClock_process : process
+begin
+ uartClock <= '0';
+ wait for uartClockPeriod/2;
+ uartClock <= '1';
+ wait for uartClockPeriod/2;
+end process;
+
+TFcount_process : process(rxUartClock,txUartClock,i_reset)
+ constant N : integer := t;
+ variable vtemp : integer range 0 to N-1 := 0;
+begin
+ if (i_reset = '1') then
+ vtemp := 0;
+ elsif (rising_edge(rxUartClock) or rising_edge(txUartClock)) then
+ TFcount_slv30 <= std_logic_vector(to_unsigned(vtemp,4));
+ if (vtemp = N-1) then
+ vtemp := 0;
+ else
+ vtemp := vtemp + 1;
+ end if;
+ end if;
+end process;
+
+tf_flag <= '1' when TFcount_slv30 = "0000" else '0';
+
+-- Stimulus process
+stim_proc: process
+constant N : integer := 9;
+type va is array(integer range <>) of std_logic_vector(7 downto 0);
+constant v : va(0 to N-1) := (
+"11111111",
+"00000000",
+"10101011",
+"11010101",
+"01010100",
+"00101010",
+"11111111",
+"00000000",
+"11111111"
+);
+type tsa is array(0 to N-1) of time;
+variable ts : tsa := (others => 0 ns);
+file wbj_ts : text open write_mode is "wbj_ts.txt";
+variable wbj_ts_row : line;
+function vec2str(vec: std_logic_vector) return string is
+variable result: string(0 to vec'left);
+begin
+for i in vec'range loop
+if (vec(i) = '1') then
+result(i) := '1';
+elsif (vec(i) = '0') then
+result(i) := '0';
+elsif (vec(i) = 'X') then
+result(i) := 'X';
+elsif (vec(i) = 'U') then
+result(i) := 'U';
+else
+result(i) := '?';
+end if;
+end loop;
+return result;
+end;
+
+begin
+
+i_reset <= '1';
+wait for uartClockPeriod;
+i_reset <= '0';
+wait for uartClockPeriod;
+
+--tx_l0 : for txi in 0 to v'length - 1 loop
+-- i_reset <= '1';
+-- wait for txUartClock_period;
+-- i_reset <= '0';
+-- wait for txUartClock_period;
+-- tx_run <= '1';
+-- wait for txUartClock_period;
+-- txData <= v(txi);
+-- wait for txUartClock_period*256;
+-- tx_run <= '0';
+-- wait for txUartClock_period*t*10;
+--end loop tx_l0;
+
+rx_l0 : for rxi in 0 to v'length - 1 loop
+ i_reset <= '1';
+ wait for rxUartClock_period;
+ i_reset <= '0';
+ wait for rxUartClock_period;
+ rx_run <= '1';
+ wait for rxUartClock_period;
+ Rx <= '0'; -- XXX start bit
+ wait for rxUartClock_period*t;
+ rx_l1 : for j in 0 to 7 loop
+ Rx <= v(rxi)(j); -- XXX look and fix data order
+ wait for rxUartClock_period*t;
+ end loop rx_l1;
+ Rx <= '1'; -- XXX stop bit
+-- wait for rxUartClock_period*t; -- XXX t
+ wait for rxUartClock_period; -- XXX 1/t
+ rx_run <= '0';
+ wait for rxUartClock_period*t;
+ Rx <= '1';
+ wait for rxUartClock_period*t*10;
+ if (v(rxi) /= RevData) then
+ assert (v(rxi) = RevData) report "rx : " & vec2str(RevData) & " expected " & vec2str(v(rxi)) severity warning;
+ ts(rxi) := now;
+ end if;
+end loop rx_l0;
+
+wait for uartClockPeriod;
+
+l10 : for i in 0 to ts'length-1 loop
+ report "add timestamps marker " & time'image(ts(i)) & " to file";
+ write(wbj_ts_row,time'image(ts(i)));
+ writeline(wbj_ts,wbj_ts_row);
+end loop l10;
+
+file_close(wbj_ts);
+
+-- insert stimulus here
+report "done" severity failure;
+wait;
+end process;
+
+END;
diff --git a/weirdboyjim_circuits/weirdboyjim_circuits.xise b/weirdboyjim_circuits/weirdboyjim_circuits.xise
new file mode 100755
index 0000000..9d5a807
--- /dev/null
+++ b/weirdboyjim_circuits/weirdboyjim_circuits.xise
@@ -0,0 +1,445 @@
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diff --git a/weirdboyjim_circuits/weirdboyjim_uart.vhd b/weirdboyjim_circuits/weirdboyjim_uart.vhd
new file mode 100755
index 0000000..b581dc5
--- /dev/null
+++ b/weirdboyjim_circuits/weirdboyjim_uart.vhd
@@ -0,0 +1,378 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:25:12 11/28/2021
+-- Design Name:
+-- Module Name: weirdboyjim_uart - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity weirdboyjim_uart is
+port (
+ signal i_reset : in std_logic;
+ signal txUartClock : in std_logic;
+ signal rxUartClock : in std_logic;
+ signal tx : out std_logic;
+ signal txData : in std_logic_vector(7 downto 0);
+ signal TFcount_slv30 : std_logic_vector(3 downto 0);
+ signal Rx : in std_logic;
+ signal RevData : out std_logic_vector(7 downto 0)
+);
+end weirdboyjim_uart;
+
+-- https://easyeda.com/weirdboyjim/UART
+architecture Behavioral of weirdboyjim_uart is
+
+ component ic_74hct32 is
+ port (
+ i_1a,i_1b : in std_logic;
+ o_1y : out std_logic;
+ i_2a,i_2b : in std_logic;
+ o_2y : out std_logic;
+ i_3a,i_3b : in std_logic;
+ o_3y : out std_logic;
+ i_4a,i_4b : in std_logic;
+ o_4y : out std_logic
+ );
+ end component ic_74hct32;
+ for all : ic_74hct32 use entity WORK.ic_74hct32(Behavioral);
+
+ component ic_74hct193 is
+ port (
+ signal i_clock : in std_logic;
+ signal i_d0 : in std_logic;
+ signal i_d1 : in std_logic;
+ signal i_d2 : in std_logic;
+ signal i_d3 : in std_logic;
+ signal o_q0 : out std_logic;
+ signal o_q1 : out std_logic;
+ signal o_q2 : out std_logic;
+ signal o_q3 : out std_logic;
+ signal i_cpd : in std_logic; -- count down clock input LH
+ signal i_cpu : in std_logic; -- count up clock input LH
+ signal i_pl : in std_logic; -- asynch parallel load input LOW
+ signal o_tcu : out std_logic; -- carry - terminal count up output LOW
+ signal o_tcd : out std_logic; -- borrow - terminal count down output LOW
+ signal i_mr : in std_logic -- asynch master reset input HIGH
+ );
+ end component ic_74hct193;
+ for all : ic_74hct193 use entity WORK.ic_74hct193(Behavioral);
+
+ component ic_74hct00 is
+ port (
+ i_1a,i_1b : in std_logic;
+ o_1y : out std_logic;
+ i_2a,i_2b : in std_logic;
+ o_2y : out std_logic;
+ i_3a,i_3b : in std_logic;
+ o_3y : out std_logic;
+ i_4a,i_4b : in std_logic;
+ o_4y : out std_logic
+ );
+ end component ic_74hct00;
+ for all : ic_74hct00 use entity WORK.ic_74hct00(Behavioral);
+
+ component ic_sn74als165 is
+ port (
+ signal i_sh_ld : in std_logic;
+ signal i_clk,i_clk_inh : in std_logic;
+ signal i_ser : in std_logic;
+ signal i_d0,i_d1,i_d2,i_d3,i_d4,i_d5,i_d6,i_d7 : in std_logic;
+ signal o_q7,o_q7_not : out std_logic
+ );
+ end component ic_sn74als165;
+ for all : ic_sn74als165 use entity WORK.ic_sn74als165(Behavioral);
+
+ component ic_74hct164 is
+ port (
+ signal i_dsa : in std_logic;
+ signal i_dsb : in std_logic;
+ signal i_cp : in std_logic;
+ signal i_mr : in std_logic;
+ signal o_q0,o_q1,o_q2,o_q3,o_q4,o_q5,o_q6,o_q7 : out std_logic
+ );
+ end component ic_74hct164;
+ for all : ic_74hct164 use entity WORK.ic_74hct164(Behavioral);
+
+ signal itxClock,txStart,txDataReady,txDataRead,TFDataRead : std_logic;
+ signal u9_1a,u9_1b,u9_2a,u9_2b,u9_3a,u9_3b,u9_4a,u9_4b,u9_1y,u9_2y,u9_3y,u9_4y : std_logic;
+ signal u8_1a,u8_1b,u8_2a,u8_2b,u8_3a,u8_3b,u8_4a,u8_4b,u8_1y,u8_2y,u8_3y,u8_4y : std_logic;
+ signal u5_d0,u5_d1,u5_d2,u5_d3,u5_q0,u5_q1,u5_q2,u5_q3,u5_cpd,u5_cpu,u5_pl,u5_tcu,u5_tcd,u5_mr : std_logic;
+ signal u7_d0,u7_d1,u7_d2,u7_d3,u7_q0,u7_q1,u7_q2,u7_q3,u7_cpd,u7_cpu,u7_pl,u7_tcu,u7_tcd,u7_mr : std_logic;
+ signal u10_sh_ld,u10_clk,u10_clk_inh,u10_ser,u10_d0,u10_d1,u10_d2,u10_d3,u10_d4,u10_d5,u10_d6,u10_d7,u10_q7,u10_q7_not : std_logic;
+ signal u11_sh_ld,u11_clk,u11_clk_inh,u11_ser,u11_d0,u11_d1,u11_d2,u11_d3,u11_d4,u11_d5,u11_d6,u11_d7,u11_q7,u11_q7_not : std_logic;
+ signal u1_d0,u1_d1,u1_d2,u1_d3,u1_q0,u1_q1,u1_q2,u1_q3,u1_cpd,u1_cpu,u1_pl,u1_tcu,u1_tcd,u1_mr : std_logic;
+ signal u2_1a,u2_1b,u2_2a,u2_2b,u2_3a,u2_3b,u2_4a,u2_4b,u2_1y,u2_2y,u2_3y,u2_4y : std_logic;
+ signal u3_d0,u3_d1,u3_d2,u3_d3,u3_q0,u3_q1,u3_q2,u3_q3,u3_cpd,u3_cpu,u3_pl,u3_tcu,u3_tcd,u3_mr : std_logic;
+ signal u4_dsa,u4_dsb,u4_cp,u4_mr,u4_q0,u4_q1,u4_q2,u4_q3,u4_q4,u4_q5,u4_q6,u4_q7 : std_logic;
+
+ signal Dev12_Assert,StatusCopy,ByteRev,RevClock : std_logic := '0';
+
+begin
+
+ U9_inst : ic_74hct32 port map (
+ i_1a => u9_1a, i_1b => u9_1b, o_1y => u9_1y,
+ i_2a => u9_2a, i_2b => u9_2b, o_2y => u9_2y,
+ i_3a => u9_3a, i_3b => u9_3b, o_3y => u9_3y,
+ i_4a => u9_4a, i_4b => u9_4b, o_4y => u9_4y
+ );
+
+ U9_connect1 : u9_1a <= u9_4y;
+ U9_connect2 : u9_1b <= u9_3y;
+ U9_connect3 : txDataReady <= u9_1y;
+ U9_connect4 : u9_2a <= '0';
+ U9_connect5 : u9_2b <= '0';
+-- U9_connect6 : u9_2y <= 'X';
+ U9_connect7 : u9_3a <= TFcount_slv30(0);
+ U9_connect8 : u9_3b <= TFcount_slv30(1);
+ U9_connect9 : u9_4a <= TFcount_slv30(2);
+ U9_connect10 : u9_4b <= TFcount_slv30(3);
+
+ U5_inst : ic_74hct193 port map (
+ i_clock => 'X',
+ i_d0 => u5_d0, i_d1 => u5_d1, i_d2 => u5_d2, i_d3 => u5_d3,
+ o_q0 => u5_q0, o_q1 => u5_q1, o_q2 => u5_q2, o_q3 => u5_q3,
+ i_cpd => u5_cpd, i_cpu => u5_cpu, i_pl => u5_pl,
+ o_tcu => u5_tcu, o_tcd => u5_tcd, i_mr => u5_mr
+ );
+
+ U5_connect1 : u5_d0 <= '0';
+ U5_connect2 : u5_d1 <= '0';
+ U5_connect3 : u5_d2 <= '0';
+ U5_connect4 : u5_d3 <= '0';
+-- U5_connect5 : u5_q0 <= 'X';
+-- U5_connect6 : u5_q1 <= 'X';
+-- U5_connect7 : u5_q2 <= 'X';
+ U5_connect8 : itxClock <= u5_q3;
+ U5_connect9 : u5_cpd <= '1';
+ U5_connect10 : u5_cpu <= txUartClock;
+ U5_connect11 : u5_pl <= '1';
+-- U5_connect12 : u5_tcu <= 'X';
+-- U5_connect13 : u5_tcd <= 'X';
+ U5_connect14 : u5_mr <= i_reset;
+
+ U7_inst : ic_74hct193 port map (
+ i_clock => 'X',
+ i_d0 => u7_d0, i_d1 => u7_d1, i_d2 => u7_d2, i_d3 => u7_d3,
+ o_q0 => u7_q0, o_q1 => u7_q1, o_q2 => u7_q2, o_q3 => u7_q3,
+ i_cpd => u7_cpd, i_cpu => u7_cpu, i_pl => u7_pl,
+ o_tcu => u7_tcu, o_tcd => u7_tcd, i_mr => u7_mr
+ );
+
+ U7_connect1 : u7_d0 <= '1';
+ U7_connect2 : u7_d1 <= '0';
+ U7_connect3 : u7_d2 <= '1';
+ U7_connect4 : u7_d3 <= '0';
+-- U7_connect5 : u7_q0 <= 'X';
+-- U7_connect6 : u7_q1 <= 'X';
+-- U7_connect7 : u7_q2 <= 'X';
+-- U7_connect8 : u7_q3 <= 'X';
+ U7_connect9 : u7_cpd <= '1';
+ U7_connect10 : u7_cpu <= itxClock;
+ U7_connect11 : u7_pl <= u8_4y;
+-- U7_connect12 : u7_tcu <= u8_3a;
+-- U7_connect13 : u7_tcd <= 'X';
+ U7_connect14 : u7_mr <= i_reset;
+
+ U8_inst : ic_74hct00 port map (
+ i_1a => u8_1a, i_1b => u8_1b, o_1y => u8_1y,
+ i_2a => u8_2a, i_2b => u8_2b, o_2y => u8_2y,
+ i_3a => u8_3a, i_3b => u8_3b, o_3y => u8_3y,
+ i_4a => u8_4a, i_4b => u8_4b, o_4y => u8_4y
+ );
+
+ U8_connect1 : u8_1a <= itxClock;
+ U8_connect2 : u8_1b <= txDataReady;
+-- U8_connect3 : u8_1y <= 'X';
+ U8_connect4 : u8_2a <= '0';
+ U8_connect5 : u8_2b <= '0';
+-- U8_connect6 : u8_2y <= 'X';
+ U8_connect7 : u8_3a <= u7_tcu;
+ U8_connect8 : txStart <= u8_4y; -- XXX for sim
+ U8 : u8_3b <= u8_4y;
+ U8_connect9 : TFDataRead <= u8_3y;
+ U8_connect10 : u8_4a <= u8_3y;
+ U8_connect11 : u8_4b <= u8_1y;
+ U8_connect12 : txStart <= u8_4y;
+
+ U10_inst : ic_sn74als165 port map (
+ i_sh_ld => u10_sh_ld,
+ i_clk => u10_clk,
+ i_clk_inh => u10_clk_inh,
+ i_ser => u10_ser,
+ i_d0 => u10_d0,
+ i_d1 => u10_d1,
+ i_d2 => u10_d2,
+ i_d3 => u10_d3,
+ i_d4 => u10_d4,
+ i_d5 => u10_d5,
+ i_d6 => u10_d6,
+ i_d7 => u10_d7,
+ o_q7 => u10_q7,
+ o_q7_not => u10_q7_not
+ );
+
+ U10_connect1 : u10_sh_ld <= txStart;
+ U10_connect2 : u10_clk <= itxClock;
+ U10_connect3 : u10_clk_inh <= '0';
+ U10_connect4 : u10_ser <= u11_q7;
+ U10_connect5 : u10_d0 <= txData(5);
+ U10_connect6 : u10_d1 <= txData(4);
+ U10_connect7 : u10_d2 <= txData(3);
+ U10_connect8 : u10_d3 <= txData(2);
+ U10_connect9 : u10_d4 <= txData(1);
+ U10_connect10 : u10_d5 <= txData(0);
+ U10_connect11 : u10_d6 <= '0';
+ U10_connect12 : u10_d7 <= '1';
+ U10_connect13 : tx <= u10_q7;
+-- U10_connect14 : u10_q7_not <= 'X';
+
+ U11_inst : ic_sn74als165 port map (
+ i_sh_ld => u11_sh_ld,
+ i_clk => u11_clk,
+ i_clk_inh => u11_clk_inh,
+ i_ser => u11_ser,
+ i_d0 => u11_d0,
+ i_d1 => u11_d1,
+ i_d2 => u11_d2,
+ i_d3 => u11_d3,
+ i_d4 => u11_d4,
+ i_d5 => u11_d5,
+ i_d6 => u11_d6,
+ i_d7 => u11_d7,
+ o_q7 => u11_q7,
+ o_q7_not => u11_q7_not
+ );
+
+ U11_connect1 : u11_sh_ld <= txStart;
+ U11_connect2 : u11_clk <= itxClock;
+ U11_connect3 : u11_clk_inh <= '0';
+ U11_connect4 : u11_ser <= '1';
+ U11_connect5 : u11_d0 <= '1';
+ U11_connect6 : u11_d1 <= '1';
+ U11_connect7 : u11_d2 <= '1';
+ U11_connect8 : u11_d3 <= '1';
+ U11_connect9 : u11_d4 <= '1';
+ U11_connect10 : u11_d5 <= '1';
+ U11_connect11 : u11_d6 <= txData(7);
+ U11_connect12 : u11_d7 <= txData(6);
+-- U11_connect13 : u11_q7 <= u10_ser;
+-- U11_connect14 : u11_q7_not <= 'X';
+
+ U1_inst : ic_74hct193 port map (
+ i_clock => 'X',
+ i_d0 => u1_d0, i_d1 => u1_d1, i_d2 => u1_d2, i_d3 => u1_d3,
+ o_q0 => u1_q0, o_q1 => u1_q1, o_q2 => u1_q2, o_q3 => u1_q3,
+ i_cpd => u1_cpd, i_cpu => u1_cpu, i_pl => u1_pl,
+ o_tcu => u1_tcu, o_tcd => u1_tcd, i_mr => u1_mr
+ );
+
+ U1_connect1 : u1_d0 <= '1';
+ U1_connect2 : u1_d1 <= '0';
+ U1_connect3 : u1_d2 <= '0';
+ U1_connect4 : u1_d3 <= '1';
+-- U1_connect5 : u1_q0 <= 'X';
+-- U1_connect6 : u1_q1 <= 'X';
+-- U1_connect7 : u1_q2 <= 'X';
+-- U1_connect8 : u1_q3 <= 'X';
+ U1_connect9 : u1_cpd <= RevClock;
+ U1_connect10 : u1_cpu <= '1';
+ U1_connect11 : u1_pl <= u2_3y;
+-- U1_connect12 : u1_tcu <= 'X';
+ U1_connect13 : u2_4b <= u1_tcd;
+ U1_connect14 : u1_mr <= i_reset; --'1';
+
+ U2_inst : ic_74hct00 port map (
+ i_1a => u2_1a, i_1b => u2_1b, o_1y => u2_1y,
+ i_2a => u2_2a, i_2b => u2_2b, o_2y => u2_2y,
+ i_3a => u2_3a, i_3b => u2_3b, o_3y => u2_3y,
+ i_4a => u2_4a, i_4b => u2_4b, o_4y => u2_4y
+ );
+
+ U2_connect1 : u2_1a <= Dev12_Assert;
+ U2_connect2 : u2_1b <= Dev12_Assert;
+ U2_connect3 : StatusCopy <= u2_1y;
+ U2_connect4 : u2_2a <= '0';
+ U2_connect5 : u2_2b <= '0';
+-- U2_connect6 : u2_2y <= 'X';
+ U2_connect7 : u2_3a <= Rx;
+ U2_connect9 : u2_3b <= u2_4y;
+ U2_connect11 : u2_4a <= u2_3y;
+ U2_connect12 : u2_4b <= u1_tcd;
+ U2_connect13 : ByteRev <= u2_4y;
+
+ U3_inst : ic_74hct193 port map (
+ i_clock => 'X',
+ i_d0 => u3_d0, i_d1 => u3_d1, i_d2 => u3_d2, i_d3 => u3_d3,
+ o_q0 => u3_q0, o_q1 => u3_q1, o_q2 => u3_q2, o_q3 => u3_q3,
+ i_cpd => u3_cpd, i_cpu => u3_cpu, i_pl => u3_pl,
+ o_tcu => u3_tcu, o_tcd => u3_tcd, i_mr => u3_mr
+ );
+
+ U3_connect1 : u3_d0 <= '0';
+ U3_connect2 : u3_d1 <= '0';
+ U3_connect3 : u3_d2 <= '0';
+ U3_connect4 : u3_d3 <= '0';
+-- U3_connect5 : u3_q0 <= 'X';
+-- U3_connect6 : u3_q1 <= 'X';
+-- U3_connect7 : u3_q2 <= 'X';
+ U3_connect8 : RevClock <= u3_q3;
+ U3_connect9 : u3_cpd <= '1';
+ U3_connect10 : u3_cpu <= rxUartClock;
+ U3_connect11 : u3_pl <= '1';
+-- U3_connect12 : u3_tcu <= 'X';
+-- U3_connect13 : u3_tcd <= 'X';
+ U3_connect14 : u3_mr <= i_reset; --u2_4y;
+
+ U4_inst : ic_74hct164 port map (
+ i_dsa => U4_dsa,
+ i_dsb => U4_dsb,
+ i_cp => U4_cp,
+ i_mr => U4_mr,
+ o_q0 => U4_q0,
+ o_q1 => U4_q1,
+ o_q2 => U4_q2,
+ o_q3 => U4_q3,
+ o_q4 => U4_q4,
+ o_q5 => U4_q5,
+ o_q6 => U4_q6,
+ o_q7 => U4_q7
+ );
+
+ U4_connect1 : U4_dsa <= Rx;
+ U4_connect2 : U4_dsb <= '1';
+ U4_connect3 : U4_cp <= RevClock;
+ U4_connect4 : U4_mr <= '1';
+ U4_connect5 : RevData(7) <= U4_q0;
+ U4_connect6 : RevData(6) <= U4_q1;
+ U4_connect7 : RevData(5) <= U4_q2;
+ U4_connect8 : RevData(4) <= U4_q3;
+ U4_connect9 : RevData(3) <= U4_q4;
+ U4_connect10 : RevData(2) <= U4_q5;
+ U4_connect11 : RevData(1) <= U4_q6;
+ U4_connect12 : RevData(0) <= U4_q7;
+
+end Behavioral;
+