From 3f09969e866ca520f45967d4d1d0aa98fb46c7a7 Mon Sep 17 00:00:00 2001
From: coolsnowwolf <coolsowwolf@gmail.com>
Date: Thu, 4 Aug 2022 19:47:00 +0000
Subject: [PATCH 1/9] kernel: refresh RTL 5.19 patch
---
package/lean/r8125/patches/020-5.19-support.patch | 2 +-
package/lean/r8152/patches/010-5.19-support.patch | 2 +-
package/lean/r8168/patches/030-5.19-support.patch | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/package/lean/r8125/patches/020-5.19-support.patch b/package/lean/r8125/patches/020-5.19-support.patch
index 778e21888a902d..481c7739ebef18 100644
--- a/package/lean/r8125/patches/020-5.19-support.patch
+++ b/package/lean/r8125/patches/020-5.19-support.patch
@@ -4,7 +4,7 @@
#define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
#define FIRMWARE_8168FP_4 "rtl_nic/rtl8168fp-4.fw"
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0)
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0)
+static inline void netif_set_gso_max_size(struct net_device *dev,
+ unsigned int size)
+{
diff --git a/package/lean/r8152/patches/010-5.19-support.patch b/package/lean/r8152/patches/010-5.19-support.patch
index 3046862320daf7..944e5bfcc94c1b 100644
--- a/package/lean/r8152/patches/010-5.19-support.patch
+++ b/package/lean/r8152/patches/010-5.19-support.patch
@@ -4,7 +4,7 @@
#define RTL_ADVERTISED_1000_FULL BIT(5)
#define RTL_ADVERTISED_2500_FULL BIT(6)
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0)
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0)
+static inline void netif_set_gso_max_size(struct net_device *dev,
+ unsigned int size)
+{
diff --git a/package/lean/r8168/patches/030-5.19-support.patch b/package/lean/r8168/patches/030-5.19-support.patch
index 07c94921fe6dfa..d4dca31255a876 100644
--- a/package/lean/r8168/patches/030-5.19-support.patch
+++ b/package/lean/r8168/patches/030-5.19-support.patch
@@ -4,7 +4,7 @@
#define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
#define FIRMWARE_8168FP_4 "rtl_nic/rtl8168fp-4.fw"
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0)
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0)
+static inline void netif_set_gso_max_size(struct net_device *dev,
+ unsigned int size)
+{
From bda5611e48fffc0362504a2967e139aa1d460bde Mon Sep 17 00:00:00 2001
From: coolsnowwolf <31687149+coolsnowwolf@users.noreply.github.com>
Date: Fri, 5 Aug 2022 11:18:08 +0800
Subject: [PATCH 2/9] ntfs3-mount : add support kernel 5.19
---
package/lean/ntfs3-mount/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/package/lean/ntfs3-mount/Makefile b/package/lean/ntfs3-mount/Makefile
index e3b266a317d0d6..61dd214bac1e56 100644
--- a/package/lean/ntfs3-mount/Makefile
+++ b/package/lean/ntfs3-mount/Makefile
@@ -10,7 +10,7 @@ define Package/ntfs3-mount
CATEGORY:=Utilities
SUBMENU:=Filesystem
TITLE:=NTFS mount script for Paragon NTFS3 driver
- DEPENDS:=+LINUX_5_4:kmod-fs-ntfs3-oot +(LINUX_5_15||LINUX_5_18):kmod-fs-ntfs3
+ DEPENDS:=+LINUX_5_4:kmod-fs-ntfs3-oot +(LINUX_5_15||LINUX_5_18||LINUX_5_19):kmod-fs-ntfs3
PKGARCH:=all
endef
From cabbef2b4e4618e8acd4f0819642b1e6d5e7e1ae Mon Sep 17 00:00:00 2001
From: lovehackintosh <92633080+lovehackintosh@users.noreply.github.com>
Date: Fri, 5 Aug 2022 11:19:25 +0800
Subject: [PATCH 3/9] kernel: bump 5.10 to 5.10.135 (#9887)
All patches automatically rebased.
Signed-off-by: John Audia <therealgraysky@proton.me>
Co-authored-by: John Audia <therealgraysky@proton.me>
---
include/kernel-5.10 | 4 ++--
.../ath79/patches-5.10/910-unaligned_access_hacks.patch | 8 ++++----
...ix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch | 2 +-
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/kernel-5.10 b/include/kernel-5.10
index c2df3cb11a3770..8a4895d91b2ef4 100644
--- a/include/kernel-5.10
+++ b/include/kernel-5.10
@@ -1,2 +1,2 @@
-LINUX_VERSION-5.10 = .134
-LINUX_KERNEL_HASH-5.10.134 = ec3513acdf033dd8f8ac2545cd1bb826b0669e151185e5f70408a5c9fe273269
+LINUX_VERSION-5.10 = .135
+LINUX_KERNEL_HASH-5.10.135 = e499a61be9ce670716dd27b5124bb9ef6c6bc0e8fab443abf717a77136543344
diff --git a/target/linux/ath79/patches-5.10/910-unaligned_access_hacks.patch b/target/linux/ath79/patches-5.10/910-unaligned_access_hacks.patch
index ad19f8eaf97d2e..713f01f20f508f 100644
--- a/target/linux/ath79/patches-5.10/910-unaligned_access_hacks.patch
+++ b/target/linux/ath79/patches-5.10/910-unaligned_access_hacks.patch
@@ -305,7 +305,7 @@
list_for_each_entry(p, head, list) {
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
-@@ -612,48 +612,53 @@ static void tcp_options_write(__be32 *pt
+@@ -609,48 +609,53 @@ static void tcp_options_write(__be32 *pt
u16 options = opts->options; /* mungable copy */
if (unlikely(OPTION_MD5 & options)) {
@@ -382,7 +382,7 @@
}
if (unlikely(opts->num_sack_blocks)) {
-@@ -661,16 +666,17 @@ static void tcp_options_write(__be32 *pt
+@@ -658,16 +663,17 @@ static void tcp_options_write(__be32 *pt
tp->duplicate_sack : tp->selective_acks;
int this_sack;
@@ -406,7 +406,7 @@
}
tp->rx_opt.dsack = 0;
-@@ -683,13 +689,14 @@ static void tcp_options_write(__be32 *pt
+@@ -680,13 +686,14 @@ static void tcp_options_write(__be32 *pt
if (foc->exp) {
len = TCPOLEN_EXP_FASTOPEN_BASE + foc->len;
@@ -706,7 +706,7 @@
EXPORT_SYMBOL(xfrm_parse_spi);
--- a/net/ipv4/tcp_input.c
+++ b/net/ipv4/tcp_input.c
-@@ -4092,14 +4092,16 @@ static bool tcp_parse_aligned_timestamp(
+@@ -4093,14 +4093,16 @@ static bool tcp_parse_aligned_timestamp(
{
const __be32 *ptr = (const __be32 *)(th + 1);
diff --git a/target/linux/generic/pending-5.10/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch b/target/linux/generic/pending-5.10/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch
index 0d1d3e1137c721..f788deabac16d9 100644
--- a/target/linux/generic/pending-5.10/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch
+++ b/target/linux/generic/pending-5.10/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch
@@ -71,7 +71,7 @@ Signed-off-by: Tobias Wolf <dev-NTEO@vplace.de>
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
-@@ -7055,7 +7055,7 @@ static void __ref alloc_node_mem_map(str
+@@ -7059,7 +7059,7 @@ static void __ref alloc_node_mem_map(str
if (pgdat == NODE_DATA(0)) {
mem_map = NODE_DATA(0)->node_mem_map;
if (page_to_pfn(mem_map) != pgdat->node_start_pfn)
From 766e12fcd555e0274dbb06cb4d96295955022c49 Mon Sep 17 00:00:00 2001
From: lean <coolsnowwolf@gmail.com>
Date: Fri, 5 Aug 2022 12:00:06 +0800
Subject: [PATCH 4/9] rockchip: add kernel 5.19 support
---
target/linux/rockchip/Makefile | 2 +-
target/linux/rockchip/armv8/config-5.19 | 846 ++++++++++++++++++
.../boot/dts/rockchip/rk3328-doornet1.dts | 495 ++++++++++
.../boot/dts/rockchip/rk3328-nanopi-r2c.dts | 47 +
.../rockchip/rk3328-orangepi-r1-plus-lts.dts | 70 ++
.../dts/rockchip/rk3328-orangepi-r1-plus.dts | 39 +
.../boot/dts/rockchip/rk3399-doornet2.dts | 113 +++
.../boot/dts/rockchip/rk3399-doornet2.dtsi | 636 +++++++++++++
.../boot/dts/rockchip/rk3399-nanopi4-opp.dtsi | 152 ++++
.../boot/dts/rockchip/rk3399-rock-pi-4.dts | 19 +
...kchip-add-EEPROM-node-for-NanoPi-R4S.patch | 31 +
...-rockchip-add-Quartz64-A-fan-pinctrl.patch | 39 +
...ip-enable-sdr-104-for-sdmmc-on-Quart.patch | 32 +
...ip-enable-sfc-controller-on-Quartz64.patch | 41 +
...ckchip-Add-rk3568-PCIe2x1-controller.patch | 74 ++
...ip-Enable-PCIe-controller-on-quartz6.patch | 80 ++
...ip-add-pine64-touch-panel-display-to.patch | 131 +++
...4-dts-rockchip-rk356x-Add-VOP2-nodes.patch | 106 +++
...4-dts-rockchip-rk356x-Add-HDMI-nodes.patch | 56 ++
...chip-rk3568-evb-Enable-VOP2-and-hdmi.patch | 90 ++
...ip-enable-vop2-and-hdmi-tx-on-quartz.patch | 91 ++
...ip-enable-vop2-and-hdmi-tx-on-rock-3.patch | 93 ++
...ts-rockchip-adjust-whitespace-around.patch | 105 +++
...kchip-Add-HDMI-audio-nodes-to-rk356x.patch | 67 ++
...chip-Enable-HDMI-audio-on-Quartz64-A.patch | 40 +
...4-dts-rockchip-add-RTC-to-BPI-R2-Pro.patch | 53 ++
...ip-set-display-regulators-to-always-.patch | 44 +
...ip-enable-vop2-and-hdmi-tx-on-BPI-R2.patch | 90 ++
...chip-Enable-HDMI-audio-on-BPI-R2-Pro.patch | 40 +
...ip-configure-thermal-shutdown-for-BP.patch | 26 +
...ockchip-enable-the-gpu-on-BPI-R2-Pro.patch | 28 +
...ip-Add-missing-space-around-regulato.patch | 31 +
...s-rockchip-add-ROCK-Pi-S-DTS-support.patch | 245 +++++
...kchip-rock-pi-s-add-more-peripherals.patch | 100 +++
...ip-align-gpio-key-node-names-with-dt.patch | 369 ++++++++
...ip-enable-hdmi-tx-audio-on-rk3568-ev.patch | 40 +
...chip-enable-hdmi-tx-audio-on-rock-3a.patch | 39 +
...ip-Add-mt7531-dsa-node-to-BPI-R2-Pro.patch | 72 ++
...t7530-rework-mt7530_hw_vlan_-add-del.patch | 87 ++
...et-dsa-mt7530-rework-mt753-01-_setup.patch | 75 ++
...et-cpu-port-via-dp-cpu_dp-instead-of.patch | 117 +++
...-Kconfig-dependencies-for-display-po.patch | 46 +
...ove-unneeded-semicolon-from-vop2-dri.patch | 29 +
...ix-spelling-mistake-aligened-aligned.patch | 26 +
...2-unlock-on-error-path-in-vop2_crtc_.patch | 27 +
...-drm-Drop-drm_edid.h-from-drm_crtc.h.patch | 569 ++++++++++++
...-Don-t-crash-for-invalid-duplicate_s.patch | 33 +
...-an-error-handling-path-rockchip_dp_.patch | 36 +
...o-usb2-Prevent-incorrect-error-on-pr.patch | 28 +
...hip-inno-usb2-Sync-initial-otg-state.patch | 33 +
...indings-phy-rockchip-add-PCIe-v3-phy.patch | 97 ++
...ings-soc-grf-add-pcie30-phy-pipe-grf.patch | 28 +
.../0046-phy-rockchip-Support-PCIe-v3.patch | 390 ++++++++
...ts-rockchip-rk3568-Add-PCIe-v3-nodes.patch | 144 +++
...chip-Add-PCIe-v3-nodes-to-BPI-R2-Pro.patch | 127 +++
...no-usb2-Ignore-OTG-IRQs-in-host-mode.patch | 34 +
...56x-fix-upper-usb-port-on-BPI-R2-Pro.patch | 28 +
.../0051-rockchip-add-pci3-for-rock3-a.patch | 211 +++++
...FriendlyElec-NanoPi-R5S-rk3568-board.patch | 844 +++++++++++++++++
...-rockchip-use-system-LED-for-OpenWrt.patch | 31 +
...dd-OF-node-for-USB-eth-on-NanoPi-R2S.patch | 24 +
...add-support-for-FriendlyARM-NanoPi-N.patch | 397 ++++++++
62 files changed, 8132 insertions(+), 1 deletion(-)
create mode 100644 target/linux/rockchip/armv8/config-5.19
create mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts
create mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
create mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
create mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
create mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dts
create mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi
create mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi
create mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
create mode 100644 target/linux/rockchip/patches-5.19/0000-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch
create mode 100644 target/linux/rockchip/patches-5.19/0001-arm64-dts-rockchip-add-Quartz64-A-fan-pinctrl.patch
create mode 100644 target/linux/rockchip/patches-5.19/0002-arm64-dts-rockchip-enable-sdr-104-for-sdmmc-on-Quart.patch
create mode 100644 target/linux/rockchip/patches-5.19/0003-arm64-dts-rockchip-enable-sfc-controller-on-Quartz64.patch
create mode 100644 target/linux/rockchip/patches-5.19/0004-arm64-dts-rockchip-Add-rk3568-PCIe2x1-controller.patch
create mode 100644 target/linux/rockchip/patches-5.19/0005-arm64-dts-rockchip-Enable-PCIe-controller-on-quartz6.patch
create mode 100644 target/linux/rockchip/patches-5.19/0006-arm64-dts-rockchip-add-pine64-touch-panel-display-to.patch
create mode 100644 target/linux/rockchip/patches-5.19/0007-arm64-dts-rockchip-rk356x-Add-VOP2-nodes.patch
create mode 100644 target/linux/rockchip/patches-5.19/0008-arm64-dts-rockchip-rk356x-Add-HDMI-nodes.patch
create mode 100644 target/linux/rockchip/patches-5.19/0009-arm64-dts-rockchip-rk3568-evb-Enable-VOP2-and-hdmi.patch
create mode 100644 target/linux/rockchip/patches-5.19/0010-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-quartz.patch
create mode 100644 target/linux/rockchip/patches-5.19/0011-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-rock-3.patch
create mode 100644 target/linux/rockchip/patches-5.19/0013-arm64-dts-rockchip-adjust-whitespace-around.patch
create mode 100644 target/linux/rockchip/patches-5.19/0014-arm64-dts-rockchip-Add-HDMI-audio-nodes-to-rk356x.patch
create mode 100644 target/linux/rockchip/patches-5.19/0015-arm64-dts-rockchip-Enable-HDMI-audio-on-Quartz64-A.patch
create mode 100644 target/linux/rockchip/patches-5.19/0017-arm64-dts-rockchip-add-RTC-to-BPI-R2-Pro.patch
create mode 100644 target/linux/rockchip/patches-5.19/0019-arm64-dts-rockchip-set-display-regulators-to-always-.patch
create mode 100644 target/linux/rockchip/patches-5.19/0020-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-BPI-R2.patch
create mode 100644 target/linux/rockchip/patches-5.19/0021-arm64-dts-rockchip-Enable-HDMI-audio-on-BPI-R2-Pro.patch
create mode 100644 target/linux/rockchip/patches-5.19/0022-arm64-dts-rockchip-configure-thermal-shutdown-for-BP.patch
create mode 100644 target/linux/rockchip/patches-5.19/0023-arm64-dts-rockchip-enable-the-gpu-on-BPI-R2-Pro.patch
create mode 100644 target/linux/rockchip/patches-5.19/0024-arm64-dts-rockchip-Add-missing-space-around-regulato.patch
create mode 100644 target/linux/rockchip/patches-5.19/0025-arm64-dts-rockchip-add-ROCK-Pi-S-DTS-support.patch
create mode 100644 target/linux/rockchip/patches-5.19/0026-arm64-dts-rockchip-rock-pi-s-add-more-peripherals.patch
create mode 100644 target/linux/rockchip/patches-5.19/0027-arm64-dts-rockchip-align-gpio-key-node-names-with-dt.patch
create mode 100644 target/linux/rockchip/patches-5.19/0028-arm64-dts-rockchip-enable-hdmi-tx-audio-on-rk3568-ev.patch
create mode 100644 target/linux/rockchip/patches-5.19/0029-arm64-dts-rockchip-enable-hdmi-tx-audio-on-rock-3a.patch
create mode 100644 target/linux/rockchip/patches-5.19/0030-arm64-dts-rockchip-Add-mt7531-dsa-node-to-BPI-R2-Pro.patch
create mode 100644 target/linux/rockchip/patches-5.19/0031-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch
create mode 100644 target/linux/rockchip/patches-5.19/0032-net-dsa-mt7530-rework-mt753-01-_setup.patch
create mode 100644 target/linux/rockchip/patches-5.19/0033-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch
create mode 100644 target/linux/rockchip/patches-5.19/0034-drm-rockchip-Fix-Kconfig-dependencies-for-display-po.patch
create mode 100644 target/linux/rockchip/patches-5.19/0035-drm-rockchip-remove-unneeded-semicolon-from-vop2-dri.patch
create mode 100644 target/linux/rockchip/patches-5.19/0036-drm-rockchip-Fix-spelling-mistake-aligened-aligned.patch
create mode 100644 target/linux/rockchip/patches-5.19/0037-drm-rockchip-vop2-unlock-on-error-path-in-vop2_crtc_.patch
create mode 100644 target/linux/rockchip/patches-5.19/0038-drm-Drop-drm_edid.h-from-drm_crtc.h.patch
create mode 100644 target/linux/rockchip/patches-5.19/0039-drm-rockchip-vop-Don-t-crash-for-invalid-duplicate_s.patch
create mode 100644 target/linux/rockchip/patches-5.19/0040-drm-rockchip-Fix-an-error-handling-path-rockchip_dp_.patch
create mode 100644 target/linux/rockchip/patches-5.19/0042-phy-rockchip-inno-usb2-Prevent-incorrect-error-on-pr.patch
create mode 100644 target/linux/rockchip/patches-5.19/0043-phy-rockchip-inno-usb2-Sync-initial-otg-state.patch
create mode 100644 target/linux/rockchip/patches-5.19/0044-dt-bindings-phy-rockchip-add-PCIe-v3-phy.patch
create mode 100644 target/linux/rockchip/patches-5.19/0045-dt-bindings-soc-grf-add-pcie30-phy-pipe-grf.patch
create mode 100644 target/linux/rockchip/patches-5.19/0046-phy-rockchip-Support-PCIe-v3.patch
create mode 100644 target/linux/rockchip/patches-5.19/0047-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch
create mode 100644 target/linux/rockchip/patches-5.19/0048-arm64-dts-rockchip-Add-PCIe-v3-nodes-to-BPI-R2-Pro.patch
create mode 100644 target/linux/rockchip/patches-5.19/0049-phy-rockchip-inno-usb2-Ignore-OTG-IRQs-in-host-mode.patch
create mode 100644 target/linux/rockchip/patches-5.19/0050-arm64-dts-rk356x-fix-upper-usb-port-on-BPI-R2-Pro.patch
create mode 100644 target/linux/rockchip/patches-5.19/0051-rockchip-add-pci3-for-rock3-a.patch
create mode 100644 target/linux/rockchip/patches-5.19/0052-rockchip-add-FriendlyElec-NanoPi-R5S-rk3568-board.patch
create mode 100644 target/linux/rockchip/patches-5.19/0053-rockchip-use-system-LED-for-OpenWrt.patch
create mode 100644 target/linux/rockchip/patches-5.19/0054-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch
create mode 100644 target/linux/rockchip/patches-5.19/111-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-N.patch
diff --git a/target/linux/rockchip/Makefile b/target/linux/rockchip/Makefile
index 4cac4d40f905c7..e616ba05cbd241 100644
--- a/target/linux/rockchip/Makefile
+++ b/target/linux/rockchip/Makefile
@@ -7,7 +7,7 @@ BOARDNAME:=Rockchip
FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-part squashfs
SUBTARGETS:=armv8
-KERNEL_PATCHVER=5.18
+KERNEL_PATCHVER=5.15
KERNEL_TESTING_PATCHVER=5.4
define Target/Description
diff --git a/target/linux/rockchip/armv8/config-5.19 b/target/linux/rockchip/armv8/config-5.19
new file mode 100644
index 00000000000000..1591ae509a122e
--- /dev/null
+++ b/target/linux/rockchip/armv8/config-5.19
@@ -0,0 +1,846 @@
+CONFIG_64BIT=y
+CONFIG_AF_UNIX_OOB=y
+CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=33
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARC_EMAC_CORE=y
+CONFIG_ARM64=y
+CONFIG_ARM64_CNP=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_ARM64_ERRATUM_1024718=y
+CONFIG_ARM64_ERRATUM_1530923=y
+CONFIG_ARM64_ERRATUM_2051678=y
+CONFIG_ARM64_ERRATUM_2077057=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_845719=y
+CONFIG_ARM64_ERRATUM_858921=y
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_MODULE_PLTS=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PAN=y
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_RAS_EXTN=y
+CONFIG_ARM64_SME=y
+CONFIG_ARM64_SVE=y
+# CONFIG_ARM64_SW_TTBR0_PAN is not set
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_VA_BITS=48
+# CONFIG_ARM64_VA_BITS_39 is not set
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
+# CONFIG_ARMV8_DEPRECATED is not set
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_FFA_SMCCC=y
+CONFIG_ARM_FFA_TRANSPORT=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+CONFIG_ARM_MHU=y
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+CONFIG_ARM_PSCI_FW=y
+CONFIG_ARM_RK3399_DMC_DEVFREQ=y
+CONFIG_ARM_SCMI_CPUFREQ=y
+CONFIG_ARM_SCMI_HAVE_SHMEM=y
+CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
+CONFIG_ARM_SCMI_POWER_DOMAIN=y
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC=y
+# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
+CONFIG_ARM_SCPI_CPUFREQ=y
+CONFIG_ARM_SCPI_POWER_DOMAIN=y
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_ARM_SMCCC_SOC_ID=y
+CONFIG_ARM_SMMU=y
+CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
+# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
+CONFIG_ARM_SMMU_V3=y
+# CONFIG_ARM_SMMU_V3_SVA is not set
+CONFIG_ATA=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_BINARY_PRINTF=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_INTEGRITY_T10=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_NVME=y
+CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BLOCK_COMPAT=y
+CONFIG_BLOCK_LEGACY_AUTOLOAD=y
+CONFIG_BRCMSTB_GISB_ARB=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CHARGER_GPIO=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_PX30=y
+CONFIG_CLK_RK3308=y
+CONFIG_CLK_RK3328=y
+CONFIG_CLK_RK3368=y
+CONFIG_CLK_RK3399=y
+CONFIG_CLK_RK3568=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=5
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_COMMON_CLK_ROCKCHIP=y
+# CONFIG_COMMON_CLK_RS9_PCIE is not set
+CONFIG_COMMON_CLK_SCMI=y
+CONFIG_COMMON_CLK_SCPI=y
+CONFIG_COMPAT=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
+CONFIG_COMPAT_OLD_SIGACTION=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_ISOLATION=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC64=y
+CONFIG_CRC64_ROCKSOFT=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC64_ROCKSOFT=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_RNG2=y
+# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
+# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+# CONFIG_DEVFREQ_THERMAL is not set
+CONFIG_DEVMEM=y
+# CONFIG_DEVPORT is not set
+# CONFIG_DM9051 is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DNOTIFY=y
+CONFIG_DRM=y
+# CONFIG_DRM_ANALOGIX_ANX7625 is not set
+CONFIG_DRM_BRIDGE=y
+# CONFIG_DRM_CHIPONE_ICN6211 is not set
+CONFIG_DRM_DEBUG_MODESET_LOCK=y
+CONFIG_DRM_DISPLAY_HDMI_HELPER=y
+CONFIG_DRM_DISPLAY_HELPER=y
+CONFIG_DRM_DW_HDMI=y
+CONFIG_DRM_DW_MIPI_DSI=y
+# CONFIG_DRM_FSL_LDB is not set
+CONFIG_DRM_GEM_CMA_HELPER=y
+# CONFIG_DRM_ITE_IT6505 is not set
+# CONFIG_DRM_ITE_IT66121 is not set
+CONFIG_DRM_KMS_HELPER=y
+# CONFIG_DRM_LONTIUM_LT8912B is not set
+# CONFIG_DRM_LONTIUM_LT9211 is not set
+# CONFIG_DRM_LONTIUM_LT9611UXC is not set
+CONFIG_DRM_MIPI_DSI=y
+CONFIG_DRM_NOMODESET=y
+CONFIG_DRM_PANEL=y
+# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set
+# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set
+CONFIG_DRM_PANEL_BRIDGE=y
+# CONFIG_DRM_PANEL_DSI_CM is not set
+# CONFIG_DRM_PANEL_EDP is not set
+# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
+# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
+# CONFIG_DRM_PANEL_JDI_R63452 is not set
+# CONFIG_DRM_PANEL_KHADAS_TS050 is not set
+# CONFIG_DRM_PANEL_MIPI_DBI is not set
+# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set
+# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set
+# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set
+# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set
+# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set
+# CONFIG_DRM_RCAR_MIPI_DSI is not set
+# CONFIG_DRM_RCAR_USE_LVDS is not set
+CONFIG_DRM_ROCKCHIP=y
+# CONFIG_DRM_SIMPLEDRM is not set
+# CONFIG_DRM_SSD130X is not set
+# CONFIG_DRM_TI_SN65DSI83 is not set
+CONFIG_DTC=y
+CONFIG_DT_IDLE_GENPD=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DWMAC_DWC_QOS_ETH=y
+CONFIG_DWMAC_GENERIC=y
+CONFIG_DWMAC_ROCKCHIP=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EMAC_ROCKCHIP=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FANOTIFY=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+# CONFIG_FORTIFY_SOURCE is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FRAME_WARN=2048
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_FUN_ETH is not set
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC12_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PHY_MIPI_DPHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+# CONFIG_GPIO_CASCADE is not set
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_ROCKCHIP=y
+# CONFIG_GPIO_SIM is not set
+CONFIG_GRO_CELLS=y
+# CONFIG_HARDENED_USERCOPY is not set
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HDMI=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_HOTPLUG_PCI_SHPC=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y
+# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set
+CONFIG_HWMON=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HZ=250
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_RK3X=y
+CONFIG_IGB=y
+CONFIG_IGB_HWMON=y
+CONFIG_IGC=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_INDIRECT_PIO=y
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_MATRIXKMAP=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_RK805_PWRKEY=y
+CONFIG_INPUT_SPARSEKMAP=y
+CONFIG_IOMMU_API=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+CONFIG_IOMMU_DMA=y
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOMMU_IO_PGTABLE=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IO_STRICT_DEVMEM is not set
+CONFIG_IO_URING=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JUMP_LABEL=y
+CONFIG_KALLSYMS=y
+CONFIG_KCMP=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEXEC_FILE=y
+# CONFIG_KEXEC_SIG is not set
+CONFIG_KSM=y
+# CONFIG_LAN966X_SWITCH is not set
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+# CONFIG_LEDS_PWM_MULTICOLOR is not set
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_LIBCRC32C=y
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_LTO_NONE=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MAILBOX=y
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_GPIO=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEDIATEK_GE_PHY=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_KHADAS_MCU is not set
+# CONFIG_MFD_MAX77714 is not set
+CONFIG_MFD_RK808=y
+# CONFIG_MFD_SIMPLE_MFD_I2C is not set
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_DW=y
+# CONFIG_MMC_DW_BLUEFIELD is not set
+# CONFIG_MMC_DW_EXYNOS is not set
+# CONFIG_MMC_DW_HI3798CV200 is not set
+# CONFIG_MMC_DW_K3 is not set
+# CONFIG_MMC_DW_PCI is not set
+CONFIG_MMC_DW_PLTFM=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MOTORCOMM_PHY=y
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+CONFIG_MQ_IOSCHED_DEADLINE=y
+# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MT7530=y
+# CONFIG_NET_DSA_REALTEK is not set
+CONFIG_NET_DSA_TAG_MTK=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SOCK_MSG=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_VENDOR_DAVICOM=y
+CONFIG_NET_VENDOR_FUNGIBLE=y
+CONFIG_NLS=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NTFS_FS=y
+CONFIG_NTFS_RW=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_NVME_CORE=y
+# CONFIG_NVME_HWMON is not set
+# CONFIG_NVME_MULTIPATH is not set
+# CONFIG_NVME_VERBOSE_ERRORS is not set
+# CONFIG_OCTEON_EP is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_RESOLVE=y
+CONFIG_OLD_SIGSUSPEND3=y
+# CONFIG_OVERLAY_FS_XINO_AUTO is not set
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_SPLIT_BTF=y
+CONFIG_PAHOLE_VERSION=121
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PATA_SIS=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_PME=y
+CONFIG_PCIE_ROCKCHIP=y
+CONFIG_PCIE_ROCKCHIP_DW_HOST=y
+CONFIG_PCIE_ROCKCHIP_HOST=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCI_STUB=y
+CONFIG_PCS_XPCS=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PHY_ROCKCHIP_DP=y
+CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
+CONFIG_PHY_ROCKCHIP_EMMC=y
+CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y
+CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
+CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
+CONFIG_PHY_ROCKCHIP_PCIE=y
+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_PHY_ROCKCHIP_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RK805=y
+CONFIG_PINCTRL_ROCKCHIP=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PL330_DMA=y
+CONFIG_PLATFORM_MHU=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEVFREQ=y
+CONFIG_PM_DEVFREQ_EVENT=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_OPP=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_PPS=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPTION=y
+CONFIG_PREEMPT_BUILD=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_VMCORE=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_PWM_SYSFS=y
+# CONFIG_PWM_XILINX is not set
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_QUOTA=y
+CONFIG_QUOTACTL=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_RAID_ATTRS=y
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_RANDOMIZE_KSTACK_OFFSET=y
+CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+# CONFIG_RAVE_SP_CORE is not set
+CONFIG_RCU_TRACE=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_ARM_SCMI is not set
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK808=y
+# CONFIG_REGULATOR_RT5190A is not set
+# CONFIG_REGULATOR_RT5759 is not set
+# CONFIG_REGULATOR_SY7636A is not set
+# CONFIG_REGULATOR_TPS6286X is not set
+CONFIG_RELOCATABLE=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SCMI=y
+CONFIG_RFS_ACCEL=y
+# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
+# CONFIG_ROCKCHIP_CDN_DP is not set
+CONFIG_ROCKCHIP_DW_HDMI=y
+CONFIG_ROCKCHIP_DW_MIPI_DSI=y
+CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_ROCKCHIP_GRF=y
+CONFIG_ROCKCHIP_INNO_HDMI=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_ROCKCHIP_IOMMU=y
+# CONFIG_ROCKCHIP_LVDS is not set
+CONFIG_ROCKCHIP_MBOX=y
+# CONFIG_ROCKCHIP_OTP is not set
+CONFIG_ROCKCHIP_PHY=y
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+# CONFIG_ROCKCHIP_RGB is not set
+CONFIG_ROCKCHIP_RK3066_HDMI=y
+CONFIG_ROCKCHIP_THERMAL=y
+CONFIG_ROCKCHIP_TIMER=y
+CONFIG_ROCKCHIP_VOP=y
+CONFIG_ROCKCHIP_VOP2=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPS=y
+CONFIG_RSEQ=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_RK808=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_NVMEM=y
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_HOST=y
+CONFIG_SATA_PMP=y
+CONFIG_SATA_SIS=y
+CONFIG_SCHED_MC=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_PROC_FS is not set
+# CONFIG_SCSI_SAS_ATA is not set
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SENSORS_ARM_SCMI is not set
+CONFIG_SENSORS_ARM_SCPI=y
+# CONFIG_SENSORS_NCT6775_I2C is not set
+# CONFIG_SENSORS_SY7636A is not set
+# CONFIG_SENSORS_TMP464 is not set
+CONFIG_SERIAL_8250_ASPEED_VUART=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FINTEK=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_PCIPS2=y
+CONFIG_SERIO_RAW=y
+# CONFIG_SFC_SIENA is not set
+CONFIG_SG_POOL=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_SMP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BUS=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_ROCKCHIP=y
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+CONFIG_SRAM=y
+CONFIG_SRCU=y
+CONFIG_STACKDEPOT=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR_PER_TASK=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_STACKTRACE=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+# CONFIG_STMMAC_SELFTESTS is not set
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_SWAP is not set
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYSVIPC_COMPAT=y
+# CONFIG_TEXTSEARCH is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_EMULATION=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+# CONFIG_TINYDRM_ILI9163 is not set
+CONFIG_TRACE_CLOCK=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+CONFIG_TRANS_TABLE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_TYPEC=y
+# CONFIG_TYPEC_DP_ALTMODE is not set
+CONFIG_TYPEC_FUSB302=y
+# CONFIG_TYPEC_HD3SS3220 is not set
+# CONFIG_TYPEC_MUX_FSA4480 is not set
+# CONFIG_TYPEC_MUX_PI3USB30532 is not set
+# CONFIG_TYPEC_RT1719 is not set
+# CONFIG_TYPEC_STUSB160X is not set
+# CONFIG_TYPEC_TCPCI is not set
+CONFIG_TYPEC_TCPM=y
+# CONFIG_TYPEC_TPS6598X is not set
+# CONFIG_TYPEC_WUSB3801 is not set
+# CONFIG_UACCE is not set
+# CONFIG_UCLAMP_TASK is not set
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_HOST=y
+CONFIG_USB_DWC3_OF_SIMPLE=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+CONFIG_USB_HID=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_PHY=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USERIO=y
+CONFIG_VIDEOMODE_HELPERS=y
+# CONFIG_VIRTIO_MENU is not set
+CONFIG_VMAP_STACK=y
+# CONFIG_VMWARE_VMCI is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_WATCHDOG is not set
+CONFIG_XARRAY_MULTI=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts
new file mode 100644
index 00000000000000..6f9cf81f89370a
--- /dev/null
+++ b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-doornet1.dts
@@ -0,0 +1,495 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 EmbedFire <embedfire@embedfire.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "rk3328-dram-nanopi2-timing.dtsi"
+#include "rk3328.dtsi"
+
+/ {
+ model = "EmbedFire DoorNet1";
+ compatible = "embedfire,doornet1", "rockchip,rk3328";
+
+ aliases {
+ led-boot = &sys_led;
+ led-failsafe = &sys_led;
+ led-running = &sys_led;
+ led-upgrade = &sys_led;
+ // mmc1 = &sdmmc;
+ // mmc0 = &emmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac_clk: gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&reset_button_pin>;
+ pinctrl-names = "default";
+
+ reset {
+ label = "reset";
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ debounce-interval = <50>;
+ };
+ };
+
+ vcc_rtl8153: vcc-rtl8153-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtl8153_en_drv>;
+ regulator-always-on;
+ regulator-name = "vcc_rtl8153";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ };
+
+ dmc: dmc {
+ compatible = "rockchip,rk3328-dmc";
+ devfreq-events = <&dfi>;
+ center-supply = <&vdd_log>;
+ clocks = <&cru SCLK_DDRCLK>;
+ clock-names = "dmc_clk";
+ operating-points-v2 = <&dmc_opp_table>;
+ ddr_timing = <&ddr_timing>;
+ upthreshold = <40>;
+ downdifferential = <20>;
+ auto-min-freq = <786000>;
+ auto-freq-en = <1>;
+ #cooling-cells = <2>;
+ status = "okay";
+
+ ddr_power_model: ddr_power_model {
+ compatible = "ddr_power_model";
+ dynamic-power-coefficient = <120>;
+ static-power-coefficient = <200>;
+ ts = <32000 4700 (-80) 2>;
+ thermal-zone = "soc-thermal";
+ };
+ };
+
+ dmc_opp_table: dmc-opp-table {
+ compatible = "operating-points-v2";
+
+ rockchip,leakage-voltage-sel = <
+ 1 10 0
+ 11 254 1
+ >;
+ nvmem-cells = <&logic_leakage>;
+ nvmem-cell-names = "ddr_leakage";
+
+ opp-786000000 {
+ opp-hz = /bits/ 64 <786000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ opp-798000000 {
+ opp-hz = /bits/ 64 <798000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ opp-840000000 {
+ opp-hz = /bits/ 64 <840000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ opp-924000000 {
+ opp-hz = /bits/ 64 <924000000>;
+ opp-microvolt = <1100000>;
+ opp-microvolt-L0 = <1100000>;
+ opp-microvolt-L1 = <1075000>;
+ };
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <1175000>;
+ opp-microvolt-L0 = <1175000>;
+ opp-microvolt-L1 = <1150000>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
+ pinctrl-names = "default";
+
+ lan_led: led-0 {
+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ label = "doornet1:green:lan";
+ };
+
+ sys_led: led-1 {
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ label = "doornet1:red:sys";
+ };
+
+ wan_led: led-2 {
+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
+ label = "doornet1:green:wan";
+ };
+
+ wifi_enable: wifi_enable {
+ gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
+ label = "wifi-enable";
+ };
+ };
+
+ vcc_io_sdio: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ enable-active-high;
+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&sdio_vcc_pin>;
+ pinctrl-names = "default";
+ regulator-name = "vcc_io_sdio";
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-settling-time-us = <5000>;
+ regulator-type = "voltage";
+ startup-delay-us = <2000>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ vin-supply = <&vcc_io_33>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&sdmmc0m1_pin>;
+ pinctrl-names = "default";
+ regulator-name = "vcc_sd";
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io_33>;
+ };
+
+ vdd_5v: vdd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&dfi {
+ status = "okay";
+};
+
+&gmac2io {
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
+ clock_in_out = "input";
+ phy-mode = "rgmii";
+ phy-supply = <&vcc_io_33>;
+ pinctrl-0 = <&rgmiim1_pins>;
+ pinctrl-names = "default";
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-delays-us = <0 1000000 50000>;
+ snps,reset-active-low;
+ tx_delay = <0x18>;
+ rx_delay = <0x24>;
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ rk805: pmic@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-0 = <&pmic_int_l>;
+ pinctrl-names = "default";
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vdd_5v>;
+ vcc2-supply = <&vdd_5v>;
+ vcc3-supply = <&vdd_5v>;
+ vcc4-supply = <&vdd_5v>;
+ vcc5-supply = <&vcc_io_33>;
+ vcc6-supply = <&vdd_5v>;
+
+ regulators {
+ vdd_log: DCDC_REG1 {
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <1075000>;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <1225000>;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io_33: DCDC_REG4 {
+ regulator-name = "vcc_io_33";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_18: LDO_REG1 {
+ regulator-name = "vcc_18";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc18_emmc: LDO_REG2 {
+ regulator-name = "vcc18_emmc";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-name = "vdd_10";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+ };
+ };
+ usb {
+ rtl8153_en_drv: rtl8153-en-drv {
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&io_domains {
+ pmuio-supply = <&vcc_io_33>;
+ vccio1-supply = <&vcc_io_33>;
+ vccio2-supply = <&vcc18_emmc>;
+ vccio3-supply = <&vcc_io_sdio>;
+ vccio4-supply = <&vcc_18>;
+ vccio5-supply = <&vcc_io_33>;
+ vccio6-supply = <&vcc_io_33>;
+ status = "okay";
+};
+
+&pinctrl {
+ button {
+ reset_button_pin: reset-button-pin {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ ethernet-phy {
+ eth_phy_reset_pin: eth-phy-reset-pin {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ leds {
+ lan_led_pin: lan-led-pin {
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ sys_led_pin: sys-led-pin {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wan_led_pin: wan-led-pin {
+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_pin: wifi_pin{
+ rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sd {
+ sdio_vcc_pin: sdio-vcc-pin {
+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
+ pinctrl-names = "default";
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vcc_io_sdio>;
+ status = "okay";
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <150000000>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ vmmc-supply = <&vcc_io_33>;
+ vqmmc-supply = <&vcc18_emmc>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <0>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+};
+
+&u2phy_host {
+ status = "okay";
+};
+
+&u2phy_otg {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb20_otg {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usbdrd3 {
+ status = "okay";
+};
+
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Second port is for USB 3.0 */
+ rtl8153: device@2 {
+ compatible = "usbbda,8153";
+ reg = <2>;
+
+ realtek,led-data = <0x87>;
+ };
+};
diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
new file mode 100644
index 00000000000000..adf91a0306cc45
--- /dev/null
+++ b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
+ */
+
+/dts-v1/;
+
+#include "rk3328-nanopi-r2s.dts"
+
+/ {
+ model = "FriendlyElec NanoPi R2C";
+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
+};
+
+&gmac2io {
+ phy-handle = <&yt8521s>;
+
+ mdio {
+ /delete-node/ ethernet-phy@1;
+
+ yt8521s: ethernet-phy@3 {
+ compatible = "ethernet-phy-id0000.011a",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ pinctrl-0 = <ð_phy_reset_pin>;
+ pinctrl-names = "default";
+ reset-assert-us = <10000>;
+ reset-deassert-us = <50000>;
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&lan_led {
+ label = "nanopi-r2c:green:lan";
+};
+
+&sys_led {
+ label = "nanopi-r2c:red:sys";
+};
+
+&wan_led {
+ label = "nanopi-r2c:green:wan";
+};
diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
new file mode 100644
index 00000000000000..ee37573d6a8b58
--- /dev/null
+++ b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+#include "rk3328-orangepi-r1-plus.dts"
+
+/ {
+ model = "Xunlong Orange Pi R1 Plus LTS";
+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
+};
+
+/delete-node/ &rtl8211e;
+&gmac2io {
+ phy-handle = <ðphy3>;
+ snps,reset-delays-us = <0 15000 50000>;
+ tx_delay = <0x19>;
+ rx_delay = <0x05>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy3: ethernet-phy@0 {
+ reg = <0x0>;
+ keep-clkout-on;
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
+ pinctrl-names = "default";
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vcc_io_sdio>;
+ status = "okay";
+};
+
+&dmc_opp_table {
+ opp-1056000000 {
+ status = "disabled";
+ };
+ opp-924000000 {
+ status = "disabled";
+ };
+ opp-840000000 {
+ status = "disabled";
+ };
+ opp-798000000 {
+ status = "disabled";
+ };
+};
+
+&sys_led {
+ label = "orangepi-r1-plus-lts:red:sys";
+};
+
+&wan_led {
+ label = "orangepi-r1-plus-lts:green:wan";
+};
+
+&lan_led {
+ label = "orangepi-r1-plus-lts:green:lan";
+};
diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
new file mode 100644
index 00000000000000..ed585daf438d64
--- /dev/null
+++ b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+#include "rk3328-nanopi-r2s.dts"
+
+/ {
+ model = "Xunlong Orange Pi R1 Plus";
+ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
+};
+
+&lan_led {
+ label = "orangepi-r1-plus:green:lan";
+};
+
+&spi0 {
+ max-freq = <48000000>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
+&sys_led {
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+ label = "orangepi-r1-plus:red:sys";
+};
+
+&sys_led_pin {
+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&wan_led {
+ label = "orangepi-r1-plus:green:wan";
+};
diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dts b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dts
new file mode 100644
index 00000000000000..7b9d5efafaac94
--- /dev/null
+++ b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dts
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3399-doornet2.dtsi"
+
+/ {
+ model = "EmbedFire DoorNet2 1GB";
+ compatible = "embedfire,doornet2", "rockchip,rk3399";
+
+ aliases {
+ led-boot = &sys_led;
+ led-failsafe = &sys_led;
+ led-running = &sys_led;
+ led-upgrade = &sys_led;
+ };
+
+ /delete-node/ display-subsystem;
+
+ gpio-leds {
+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
+
+ /delete-node/ status;
+
+ lan_led: led-lan {
+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
+ label = "green:lan";
+ };
+
+ sys_led: led-sys {
+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+ label = "red:sys";
+ default-state = "on";
+ };
+
+ wan_led: led-wan {
+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+ label = "green:wan";
+ };
+ };
+
+ gpio-keys {
+ pinctrl-0 = <&reset_button_pin>;
+
+ /delete-node/ power;
+
+ reset {
+ debounce-interval = <50>;
+ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ vdd_5v: vdd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&pcie0 {
+ max-link-speed = <1>;
+ num-lanes = <1>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+
+ pcie@0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ pcie-eth@0,0 {
+ compatible = "realtek,r8168";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x870>;
+ };
+ };
+};
+
+&pinctrl {
+ gpio-leds {
+ /delete-node/ leds-gpio;
+
+ lan_led_pin: lan-led-pin {
+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ sys_led_pin: sys-led-pin {
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wan_led_pin: wan-led-pin {
+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ rockchip-key {
+ /delete-node/ power-key;
+
+ reset_button_pin: reset-button-pin {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&u2phy0_host {
+ phy-supply = <&vdd_5v>;
+};
+
+&vcc3v3_sys {
+ vin-supply = <&vcc5v0_sys>;
+};
diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi
new file mode 100644
index 00000000000000..4f6bddafe68171
--- /dev/null
+++ b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi
@@ -0,0 +1,636 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include "rk3399.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3_sys";
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "vcc5v0_sys";
+ vin-supply = <&vdd_5v>;
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_s3";
+ vin-supply = <&vcc_1v8>;
+ };
+
+ vcc3v0_sd: vcc3v0-sd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_pwr_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc3v0_sd";
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vbus_typec: vbus-typec {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "vbus_typec";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&power_key>;
+
+ power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_gpio>;
+
+ status {
+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+ label = "status_led";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_reg_on_h>;
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ assigned-clock-parents = <&clkin_gmac>;
+ clock_in_out = "input";
+ phy-supply = <&vcc3v3_s3>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 100000 50000>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <160>;
+ i2c-scl-falling-time-ns = <30>;
+ status = "okay";
+
+ vdd_cpu_b: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpu_b_sleep>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_cpu_b";
+ regulator-ramp-delay = <1000>;
+ vin-supply = <&vcc3v3_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: regulator@41 {
+ compatible = "silergy,syr828";
+ reg = <0x41>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpu_sleep>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_gpu";
+ regulator-ramp-delay = <1000>;
+ vin-supply = <&vcc3v3_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ clock-output-names = "xin32k", "rtc_clko_wifi";
+ #clock-cells = <1>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ vcc10-supply = <&vcc3v3_sys>;
+ vcc11-supply = <&vcc3v3_sys>;
+ vcc12-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_3v0>;
+
+ regulators {
+ vdd_center: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-name = "vdd_center";
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_l: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-name = "vdd_cpu_l";
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc1v8_cam: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_cam";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v0_touch: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc3v0_touch";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmupll: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_pmupll";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_sdio: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <3000000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_sdio";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcca3v0_codec: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcca3v0_codec";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v5: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc_1v5";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcca1v8_codec: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_codec";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v0: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc_3v0";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc3v3_s3: SWITCH_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc3v3_s3";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_s0: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc3v3_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <200000>;
+ i2c-scl-rising-time-ns = <150>;
+ i2c-scl-falling-time-ns = <30>;
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&io_domains {
+ bt656-supply = <&vcc_1v8>;
+ audio-supply = <&vcca1v8_codec>;
+ sdmmc-supply = <&vcc_sdio>;
+ gpio1830-supply = <&vcc_3v0>;
+ status = "okay";
+};
+
+&pcie_phy {
+ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
+ assigned-clock-rates = <100000000>;
+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
+ max-link-speed = <2>;
+ num-lanes = <4>;
+ status = "okay";
+};
+
+&pinctrl {
+ fusb30x {
+ fusb0_int: fusb0-int {
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ gpio-leds {
+ leds_gpio: leds-gpio {
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ ethernet-phy {
+ eth_phy_reset_pin: eth-phy-reset-pin {
+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ pmic {
+ cpu_b_sleep: cpu-b-sleep {
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ gpu_sleep: gpu-sleep {
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ rockchip-key {
+ power_key: power-key {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio {
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_reg_on_h: bt-reg-on-h {
+ /* external pullup to VCC1V8_PMUPLL */
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_reg_on_h: wifi-reg_on-h {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc {
+ sdmmc0_det_l: sdmmc0-det-l {
+ rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ sdmmc0_pwr_h: sdmmc0-pwr-h {
+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmu1830-supply = <&vcc_3v0>;
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca1v8_s3>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v0_sd>;
+ vqmmc-supply = <&vcc_sdio>;
+ status = "okay";
+};
+
+&tcphy0 {
+ status = "okay";
+};
+
+&tcphy1 {
+ status = "okay";
+};
+
+&tsadc {
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_host {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
+&u2phy1 {
+ status = "okay";
+};
+
+&u2phy1_otg {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
+
diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi
new file mode 100644
index 00000000000000..0c700e32ddbc71
--- /dev/null
+++ b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * Copyright (c) 2020 Tianling Shen <cnsztl@gmail.com>
+ * Copyright (c) 2020 gzelvis <gzelvis@gmail.com>
+ */
+
+/ {
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <40000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <800000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <850000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <925000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1125000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <1225000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1275000>;
+ };
+ };
+
+ cluster1_opp: opp-table-1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <40000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <800000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <825000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <875000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <950000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1200000>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <1250000>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-microvolt = <1325000>;
+ };
+ };
+
+ gpu_opp_table: opp-table-2 {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <800000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <297000000>;
+ opp-microvolt = <800000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <825000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <875000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <925000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1100000>;
+ };
+ };
+};
+
+&cpu_l0 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l1 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l2 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l3 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_b0 {
+ operating-points-v2 = <&cluster1_opp>;
+};
+
+&cpu_b1 {
+ operating-points-v2 = <&cluster1_opp>;
+};
+
+&gpu {
+ operating-points-v2 = <&gpu_opp_table>;
+};
diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
new file mode 100644
index 00000000000000..f6e7710a01cb4f
--- /dev/null
+++ b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
+ * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
+ */
+
+/* TODO
+ * Delete this file and migrate RockPi 4 to RockPi 4A after
+ * removing Kernel 5.4.
+ */
+
+
+/dts-v1/;
+#include "rk3399-rock-pi-4.dtsi"
+
+/ {
+ model = "Radxa ROCK Pi 4";
+ compatible = "radxa,rockpi4", "rockchip,rk3399";
+};
diff --git a/target/linux/rockchip/patches-5.19/0000-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch b/target/linux/rockchip/patches-5.19/0000-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch
new file mode 100644
index 00000000000000..792028b29290f5
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0000-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch
@@ -0,0 +1,31 @@
+From af20b3384e8723077cc6484160b0cf4e9be321de Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Mon, 7 Jun 2021 15:45:37 +0800
+Subject: [PATCH] arm64: dts: rockchip: add EEPROM node for NanoPi R4S
+
+NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which
+stores the MAC address.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+@@ -68,6 +68,15 @@
+ status = "disabled";
+ };
+
++&i2c2 {
++ eeprom@51 {
++ compatible = "microchip,24c02", "atmel,24c02";
++ reg = <0x51>;
++ pagesize = <16>;
++ read-only; /* This holds our MAC */
++ };
++};
++
+ &i2c4 {
+ status = "disabled";
+ };
diff --git a/target/linux/rockchip/patches-5.19/0001-arm64-dts-rockchip-add-Quartz64-A-fan-pinctrl.patch b/target/linux/rockchip/patches-5.19/0001-arm64-dts-rockchip-add-Quartz64-A-fan-pinctrl.patch
new file mode 100644
index 00000000000000..e430e6972eb35f
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0001-arm64-dts-rockchip-add-Quartz64-A-fan-pinctrl.patch
@@ -0,0 +1,39 @@
+From 2c26cd88f13382b6965bbf5a8fc1c56384c6c3f6 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Wed, 11 May 2022 11:01:15 -0400
+Subject: [PATCH 01/51] arm64: dts: rockchip: add Quartz64-A fan pinctrl
+
+The Quartz64 Model A fan is bound to a single gpio. Prevent pinctrl
+issues in the future by binding the pinctrl assignment for the gpio.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+Link: https://lore.kernel.org/r/20220511150117.113070-5-pgwipeout@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+@@ -32,6 +32,8 @@
+ gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ gpio-fan,speed-map = <0 0
+ 4500 1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&fan_en_h>;
+ #cooling-cells = <2>;
+ };
+
+@@ -524,6 +526,12 @@
+ };
+ };
+
++ fan {
++ fan_en_h: fan-en-h {
++ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
+ leds {
+ work_led_enable_h: work-led-enable-h {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/target/linux/rockchip/patches-5.19/0002-arm64-dts-rockchip-enable-sdr-104-for-sdmmc-on-Quart.patch b/target/linux/rockchip/patches-5.19/0002-arm64-dts-rockchip-enable-sdr-104-for-sdmmc-on-Quart.patch
new file mode 100644
index 00000000000000..87e3c6866a551c
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0002-arm64-dts-rockchip-enable-sdr-104-for-sdmmc-on-Quart.patch
@@ -0,0 +1,32 @@
+From eda045fa2ca7b1567457048a389cda854a3a01e5 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Wed, 11 May 2022 11:01:16 -0400
+Subject: [PATCH 02/51] arm64: dts: rockchip: enable sdr-104 for sdmmc on
+ Quartz A
+
+Now that we have working io-domain support, we can enable higher date
+rates on the sdmmc card.
+
+Before:
+Timing buffered disk reads: 68 MB in 3.08 seconds = 22.07 MB/sec
+
+After:
+Timing buffered disk reads: 188 MB in 3.02 seconds = 62.29 MB/sec
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+Link: https://lore.kernel.org/r/20220511150117.113070-6-pgwipeout@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+@@ -596,6 +596,7 @@
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
++ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
diff --git a/target/linux/rockchip/patches-5.19/0003-arm64-dts-rockchip-enable-sfc-controller-on-Quartz64.patch b/target/linux/rockchip/patches-5.19/0003-arm64-dts-rockchip-enable-sfc-controller-on-Quartz64.patch
new file mode 100644
index 00000000000000..48ee021876e310
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0003-arm64-dts-rockchip-enable-sfc-controller-on-Quartz64.patch
@@ -0,0 +1,41 @@
+From 591f44f27342906ccd58eb7e63ec3ef5810bd7eb Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Wed, 11 May 2022 11:01:17 -0400
+Subject: [PATCH 03/51] arm64: dts: rockchip: enable sfc controller on Quartz64
+ Model A
+
+Add the sfc controller binding for the Quartz64 Model A. This is not
+populated by default, so leave it disabled.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+Link: https://lore.kernel.org/r/20220511150117.113070-7-pgwipeout@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3566-quartz64-a.dts | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+@@ -617,6 +617,22 @@
+ status = "okay";
+ };
+
++&sfc {
++ pinctrl-0 = <&fspi_pins>;
++ pinctrl-names = "default";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ flash@0 {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <24000000>;
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <1>;
++ };
++};
++
+ /* spdif is exposed on con40 pin 18 */
+ &spdif {
+ status = "okay";
diff --git a/target/linux/rockchip/patches-5.19/0004-arm64-dts-rockchip-Add-rk3568-PCIe2x1-controller.patch b/target/linux/rockchip/patches-5.19/0004-arm64-dts-rockchip-Add-rk3568-PCIe2x1-controller.patch
new file mode 100644
index 00000000000000..cea47965f73d32
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0004-arm64-dts-rockchip-Add-rk3568-PCIe2x1-controller.patch
@@ -0,0 +1,74 @@
+From 83729931332a2f15b0452f7dc8ea7a2e1b431842 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Fri, 29 Apr 2022 08:38:30 -0400
+Subject: [PATCH 04/51] arm64: dts: rockchip: Add rk3568 PCIe2x1 controller
+
+The PCIe2x1 controller is common between the rk3568 and rk3566. It is a
+single lane PCIe2 compliant controller.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+Link: https://lore.kernel.org/r/20220429123832.2376381-5-pgwipeout@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 50 ++++++++++++++++++++++++
+ 1 file changed, 50 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -752,6 +752,56 @@
+ reg = <0x0 0xfe1a8100 0x0 0x20>;
+ };
+
++ pcie2x1: pcie@fe260000 {
++ compatible = "rockchip,rk3568-pcie";
++ reg = <0x3 0xc0000000 0x0 0x00400000>,
++ <0x0 0xfe260000 0x0 0x00010000>,
++ <0x3 0x3f000000 0x0 0x01000000>;
++ reg-names = "dbi", "apb", "config";
++ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "sys", "pmc", "msi", "legacy", "err";
++ bus-range = <0x0 0xf>;
++ clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
++ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
++ <&cru CLK_PCIE20_AUX_NDFT>;
++ clock-names = "aclk_mst", "aclk_slv",
++ "aclk_dbi", "pclk", "aux";
++ device_type = "pci";
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0 0 0 1 &pcie_intc 0>,
++ <0 0 0 2 &pcie_intc 1>,
++ <0 0 0 3 &pcie_intc 2>,
++ <0 0 0 4 &pcie_intc 3>;
++ linux,pci-domain = <0>;
++ num-ib-windows = <6>;
++ num-ob-windows = <2>;
++ max-link-speed = <2>;
++ msi-map = <0x0 &gic 0x0 0x1000>;
++ num-lanes = <1>;
++ phys = <&combphy2 PHY_TYPE_PCIE>;
++ phy-names = "pcie-phy";
++ power-domains = <&power RK3568_PD_PIPE>;
++ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
++ 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
++ resets = <&cru SRST_PCIE20_POWERUP>;
++ reset-names = "pipe";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ status = "disabled";
++
++ pcie_intc: legacy-interrupt-controller {
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++ interrupt-controller;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
++ };
++ };
++
+ sdmmc0: mmc@fe2b0000 {
+ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xfe2b0000 0x0 0x4000>;
diff --git a/target/linux/rockchip/patches-5.19/0005-arm64-dts-rockchip-Enable-PCIe-controller-on-quartz6.patch b/target/linux/rockchip/patches-5.19/0005-arm64-dts-rockchip-Enable-PCIe-controller-on-quartz6.patch
new file mode 100644
index 00000000000000..0980512db97a2d
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0005-arm64-dts-rockchip-Enable-PCIe-controller-on-quartz6.patch
@@ -0,0 +1,80 @@
+From 5b1b78762d3fb4cf20aec4b22fbfab33960a6fdc Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Fri, 29 Apr 2022 08:38:31 -0400
+Subject: [PATCH 05/51] arm64: dts: rockchip: Enable PCIe controller on
+ quartz64-a
+
+Add the nodes to enable the PCIe controller on the Quartz64 Model A
+board.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+Link: https://lore.kernel.org/r/20220429123832.2376381-6-pgwipeout@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3566-quartz64-a.dts | 34 +++++++++++++++++++
+ 1 file changed, 34 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+@@ -127,6 +127,18 @@
+ vin-supply = <&vcc12v_dcin>;
+ };
+
++ vcc3v3_pcie_p: vcc3v3-pcie-p-regulator {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie_enable_h>;
++ regulator-name = "vcc3v3_pcie_p";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc_3v3>;
++ };
++
+ vcc5v0_usb: vcc5v0_usb {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+@@ -203,6 +215,10 @@
+ status = "okay";
+ };
+
++&combphy2 {
++ status = "okay";
++};
++
+ &cpu0 {
+ cpu-supply = <&vdd_cpu>;
+ };
+@@ -511,6 +527,14 @@
+ };
+ };
+
++&pcie2x1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie_reset_h>;
++ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_pcie_p>;
++ status = "okay";
++};
++
+ &pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+@@ -542,6 +566,16 @@
+ };
+ };
+
++ pcie {
++ pcie_enable_h: pcie-enable-h {
++ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ pcie_reset_h: pcie-reset-h {
++ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
diff --git a/target/linux/rockchip/patches-5.19/0006-arm64-dts-rockchip-add-pine64-touch-panel-display-to.patch b/target/linux/rockchip/patches-5.19/0006-arm64-dts-rockchip-add-pine64-touch-panel-display-to.patch
new file mode 100644
index 00000000000000..e714d89bb46421
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0006-arm64-dts-rockchip-add-pine64-touch-panel-display-to.patch
@@ -0,0 +1,131 @@
+From 175ce006fe4ebf077322e5818127acfade41296f Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Wed, 11 May 2022 07:35:16 -0400
+Subject: [PATCH 06/51] arm64: dts: rockchip: add pine64 touch panel display to
+ rockpro64
+
+The Pine64 touch panel is a panel consisting of the Feiyang fy07024di26a30d
+panel with a Goodix gt911 touch screen. Add the device tree nodes to the
+rockpro64 to permit attaching this display to the device.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+Link: https://lore.kernel.org/r/20220511113517.4172962-4-pgwipeout@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3399-rockpro64.dtsi | 70 +++++++++++++++++--
+ 1 file changed, 66 insertions(+), 4 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+@@ -20,6 +20,15 @@
+ stdout-path = "serial2:1500000n8";
+ };
+
++ /* enable for panel backlight support */
++ backlight: backlight {
++ compatible = "pwm-backlight";
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <5>;
++ pwms = <&pwm0 0 1000000 0>;
++ status = "disabled";
++ };
++
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+@@ -107,6 +116,14 @@
+ };
+ };
+
++ avdd: avdd-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "avdd";
++ regulator-min-microvolt = <11000000>;
++ regulator-max-microvolt = <11000000>;
++ vin-supply = <&vcc3v3_s0>;
++ };
++
+ vcc12v_dcin: vcc12v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+@@ -400,8 +417,6 @@
+
+ vcc3v0_touch: LDO_REG2 {
+ regulator-name = "vcc3v0_touch";
+- regulator-always-on;
+- regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+@@ -490,8 +505,6 @@
+
+ vcc3v3_s0: SWITCH_REG2 {
+ regulator-name = "vcc3v3_s0";
+- regulator-always-on;
+- regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+@@ -565,6 +578,19 @@
+ vbus-supply = <&vcc5v0_typec>;
+ status = "okay";
+ };
++
++ /* enable for pine64 touch screen support */
++ touch: touchscreen@5d {
++ compatible = "goodix,gt911";
++ reg = <0x5d>;
++ interrupt-parent = <&gpio4>;
++ interrupts = <RK_PD5 IRQ_TYPE_EDGE_FALLING>;
++ AVDD28-supply = <&vcc3v0_touch>;
++ VDDIO-supply = <&vcc3v0_touch>;
++ irq-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
++ reset-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
++ status = "disabled";
++ };
+ };
+
+ &i2s0 {
+@@ -600,6 +626,42 @@
+ gpio1830-supply = <&vcc_3v0>;
+ };
+
++/* enable for pine64 panel display support */
++&mipi_dsi {
++ clock-master;
++ status = "disabled";
++
++ ports {
++ mipi_out: port@1 {
++ reg = <1>;
++
++ mipi_out_panel: endpoint {
++ remote-endpoint = <&mipi_in_panel>;
++ };
++ };
++ };
++
++ mipi_panel: panel@0 {
++ compatible = "feiyang,fy07024di26a30d";
++ reg = <0>;
++ avdd-supply = <&avdd>;
++ backlight = <&backlight>;
++ dvdd-supply = <&vcc3v3_s0>;
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ reg = <0>;
++
++ mipi_in_panel: endpoint {
++ remote-endpoint = <&mipi_out_panel>;
++ };
++ };
++ };
++ };
++};
++
+ &pcie0 {
+ ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
diff --git a/target/linux/rockchip/patches-5.19/0007-arm64-dts-rockchip-rk356x-Add-VOP2-nodes.patch b/target/linux/rockchip/patches-5.19/0007-arm64-dts-rockchip-rk356x-Add-VOP2-nodes.patch
new file mode 100644
index 00000000000000..8105f0840a435c
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0007-arm64-dts-rockchip-rk356x-Add-VOP2-nodes.patch
@@ -0,0 +1,106 @@
+From ec7cbc7e9111d3d655f25807e8511492359bb0fd Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Fri, 22 Apr 2022 09:28:33 +0200
+Subject: [PATCH 07/51] arm64: dts: rockchip: rk356x: Add VOP2 nodes
+
+The VOP2 is the display output controller on the RK3568. Add the node
+for it to the dtsi file along with the required display-subsystem node
+and the iommu node.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Acked-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20220422072841.2206452-17-s.hauer@pengutronix.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3566.dtsi | 4 ++
+ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 ++
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 51 ++++++++++++++++++++++++
+ 3 files changed, 59 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
+@@ -29,3 +29,7 @@
+ extcon = <&usb2phy0>;
+ maximum-speed = "high-speed";
+ };
++
++&vop {
++ compatible = "rockchip,rk3566-vop";
++};
+--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+@@ -137,3 +137,7 @@
+ phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
++
++&vop {
++ compatible = "rockchip,rk3568-vop";
++};
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -129,6 +129,11 @@
+ };
+ };
+
++ display_subsystem: display-subsystem {
++ compatible = "rockchip,display-subsystem";
++ ports = <&vop_out>;
++ };
++
+ firmware {
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+@@ -632,6 +637,52 @@
+ };
+ };
+
++ vop: vop@fe040000 {
++ reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
++ reg-names = "vop", "gamma-lut";
++ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
++ <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
++ clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
++ iommus = <&vop_mmu>;
++ power-domains = <&power RK3568_PD_VO>;
++ rockchip,grf = <&grf>;
++ status = "disabled";
++
++ vop_out: ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ vp0: port@0 {
++ reg = <0>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ vp1: port@1 {
++ reg = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ vp2: port@2 {
++ reg = <2>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++ };
++ };
++
++ vop_mmu: iommu@fe043e00 {
++ compatible = "rockchip,rk3568-iommu";
++ reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
++ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
++ clock-names = "aclk", "iface";
++ #iommu-cells = <0>;
++ status = "disabled";
++ };
++
+ qos_gpu: qos@fe128000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe128000 0x0 0x20>;
diff --git a/target/linux/rockchip/patches-5.19/0008-arm64-dts-rockchip-rk356x-Add-HDMI-nodes.patch b/target/linux/rockchip/patches-5.19/0008-arm64-dts-rockchip-rk356x-Add-HDMI-nodes.patch
new file mode 100644
index 00000000000000..eed468bdfa1a93
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0008-arm64-dts-rockchip-rk356x-Add-HDMI-nodes.patch
@@ -0,0 +1,56 @@
+From 98180f4652c2c994cc2cc6088932086ee5c6e4d9 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Fri, 22 Apr 2022 09:28:34 +0200
+Subject: [PATCH 08/51] arm64: dts: rockchip: rk356x: Add HDMI nodes
+
+Add support for the HDMI port found on RK3568.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Link: https://lore.kernel.org/r/20220422072841.2206452-18-s.hauer@pengutronix.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 32 ++++++++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -683,6 +683,38 @@
+ status = "disabled";
+ };
+
++ hdmi: hdmi@fe0a0000 {
++ compatible = "rockchip,rk3568-dw-hdmi";
++ reg = <0x0 0xfe0a0000 0x0 0x20000>;
++ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru PCLK_HDMI_HOST>,
++ <&cru CLK_HDMI_SFR>,
++ <&cru CLK_HDMI_CEC>,
++ <&pmucru CLK_HDMI_REF>,
++ <&cru HCLK_VO>;
++ clock-names = "iahb", "isfr", "cec", "ref";
++ pinctrl-names = "default";
++ pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
++ power-domains = <&power RK3568_PD_VO>;
++ reg-io-width = <4>;
++ rockchip,grf = <&grf>;
++ #sound-dai-cells = <0>;
++ status = "disabled";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ hdmi_in: port@0 {
++ reg = <0>;
++ };
++
++ hdmi_out: port@1 {
++ reg = <1>;
++ };
++ };
++ };
++
+ qos_gpu: qos@fe128000 {
+ compatible = "rockchip,rk3568-qos", "syscon";
+ reg = <0x0 0xfe128000 0x0 0x20>;
diff --git a/target/linux/rockchip/patches-5.19/0009-arm64-dts-rockchip-rk3568-evb-Enable-VOP2-and-hdmi.patch b/target/linux/rockchip/patches-5.19/0009-arm64-dts-rockchip-rk3568-evb-Enable-VOP2-and-hdmi.patch
new file mode 100644
index 00000000000000..c4316b5d19eba4
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0009-arm64-dts-rockchip-rk3568-evb-Enable-VOP2-and-hdmi.patch
@@ -0,0 +1,90 @@
+From 7ccf41205a3deb146e7cc4fffb59fb1eb490a649 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Fri, 22 Apr 2022 09:28:35 +0200
+Subject: [PATCH 09/51] arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi
+
+This enabled the VOP2 display controller along with hdmi and the
+required port routes which is enough to get a picture out of the
+hdmi port of the board.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Link: https://lore.kernel.org/r/20220422072841.2206452-19-s.hauer@pengutronix.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3568-evb1-v10.dts | 47 +++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
+@@ -8,6 +8,7 @@
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3568.dtsi"
+
+ / {
+@@ -34,6 +35,17 @@
+ regulator-max-microvolt = <12000000>;
+ };
+
++ hdmi-con {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi_con_in: endpoint {
++ remote-endpoint = <&hdmi_out_con>;
++ };
++ };
++ };
++
+ leds {
+ compatible = "gpio-leds";
+
+@@ -209,6 +221,24 @@
+ status = "okay";
+ };
+
++&hdmi {
++ avdd-0v9-supply = <&vdda0v9_image>;
++ avdd-1v8-supply = <&vcca1v8_image>;
++ status = "okay";
++};
++
++&hdmi_in {
++ hdmi_in_vp0: endpoint {
++ remote-endpoint = <&vp0_out_hdmi>;
++ };
++};
++
++&hdmi_out {
++ hdmi_out_con: endpoint {
++ remote-endpoint = <&hdmi_con_in>;
++ };
++};
++
+ &i2c0 {
+ status = "okay";
+
+@@ -635,3 +665,20 @@
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+ };
++
++&vop {
++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++ status = "okay";
++};
++
++&vop_mmu {
++ status = "okay";
++};
++
++&vp0 {
++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++ remote-endpoint = <&hdmi_in_vp0>;
++ };
++};
diff --git a/target/linux/rockchip/patches-5.19/0010-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-quartz.patch b/target/linux/rockchip/patches-5.19/0010-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-quartz.patch
new file mode 100644
index 00000000000000..3b4489aa95d703
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0010-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-quartz.patch
@@ -0,0 +1,91 @@
+From d6eb924b01522decb987cb8c70d66c6b732a91e4 Mon Sep 17 00:00:00 2001
+From: Michael Riesch <michael.riesch@wolfvision.net>
+Date: Fri, 22 Apr 2022 09:28:36 +0200
+Subject: [PATCH 10/51] arm64: dts: rockchip: enable vop2 and hdmi tx on
+ quartz64a
+
+Enable the RK356x Video Output Processor (VOP) 2 on the Pine64
+Quartz64 Model A.
+
+Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Link: https://lore.kernel.org/r/20220422072841.2206452-20-s.hauer@pengutronix.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3566-quartz64-a.dts | 47 +++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+@@ -4,6 +4,7 @@
+
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3566.dtsi"
+
+ / {
+@@ -37,6 +38,17 @@
+ #cooling-cells = <2>;
+ };
+
++ hdmi-con {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi_con_in: endpoint {
++ remote-endpoint = <&hdmi_out_con>;
++ };
++ };
++ };
++
+ leds {
+ compatible = "gpio-leds";
+
+@@ -280,6 +292,24 @@
+ status = "okay";
+ };
+
++&hdmi {
++ avdd-0v9-supply = <&vdda_0v9>;
++ avdd-1v8-supply = <&vcc_1v8>;
++ status = "okay";
++};
++
++&hdmi_in {
++ hdmi_in_vp0: endpoint {
++ remote-endpoint = <&vp0_out_hdmi>;
++ };
++};
++
++&hdmi_out {
++ hdmi_out_con: endpoint {
++ remote-endpoint = <&hdmi_con_in>;
++ };
++};
++
+ &i2c0 {
+ status = "okay";
+
+@@ -782,3 +812,20 @@
+ phy-supply = <&vcc5v0_usb20_host>;
+ status = "okay";
+ };
++
++&vop {
++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++ status = "okay";
++};
++
++&vop_mmu {
++ status = "okay";
++};
++
++&vp0 {
++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++ remote-endpoint = <&hdmi_in_vp0>;
++ };
++};
diff --git a/target/linux/rockchip/patches-5.19/0011-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-rock-3.patch b/target/linux/rockchip/patches-5.19/0011-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-rock-3.patch
new file mode 100644
index 00000000000000..2b7a680907b586
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0011-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-rock-3.patch
@@ -0,0 +1,93 @@
+From 284f0150efd541d60156bcfea1d575b24d320cc3 Mon Sep 17 00:00:00 2001
+From: Michael Riesch <michael.riesch@wolfvision.net>
+Date: Fri, 22 Apr 2022 09:28:37 +0200
+Subject: [PATCH 11/51] arm64: dts: rockchip: enable vop2 and hdmi tx on
+ rock-3a
+
+Enable the RK356x Video Output Processor (VOP) 2 on the Radxa
+ROCK3 Model A.
+
+Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
+Reported-by: kernel test robot <lkp@intel.com>
+Link: https://lore.kernel.org/r/20220310210352.451136-4-michael.riesch@wolfvision.net
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Link: https://lore.kernel.org/r/20220422072841.2206452-21-s.hauer@pengutronix.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3568-rock-3a.dts | 47 +++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+@@ -4,6 +4,7 @@
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3568.dtsi"
+
+ / {
+@@ -20,6 +21,17 @@
+ stdout-path = "serial2:1500000n8";
+ };
+
++ hdmi-con {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi_con_in: endpoint {
++ remote-endpoint = <&hdmi_out_con>;
++ };
++ };
++ };
++
+ leds {
+ compatible = "gpio-leds";
+
+@@ -166,6 +178,24 @@
+ status = "okay";
+ };
+
++&hdmi {
++ avdd-0v9-supply = <&vdda0v9_image>;
++ avdd-1v8-supply = <&vcca1v8_image>;
++ status = "okay";
++};
++
++&hdmi_in {
++ hdmi_in_vp0: endpoint {
++ remote-endpoint = <&vp0_out_hdmi>;
++ };
++};
++
++&hdmi_out {
++ hdmi_out_con: endpoint {
++ remote-endpoint = <&hdmi_con_in>;
++ };
++};
++
+ &i2c0 {
+ status = "okay";
+
+@@ -560,3 +590,20 @@
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+ };
++
++&vop {
++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++ status = "okay";
++};
++
++&vop_mmu {
++ status = "okay";
++};
++
++&vp0 {
++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++ remote-endpoint = <&hdmi_in_vp0>;
++ };
++};
diff --git a/target/linux/rockchip/patches-5.19/0013-arm64-dts-rockchip-adjust-whitespace-around.patch b/target/linux/rockchip/patches-5.19/0013-arm64-dts-rockchip-adjust-whitespace-around.patch
new file mode 100644
index 00000000000000..2896d4254ba9a2
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0013-arm64-dts-rockchip-adjust-whitespace-around.patch
@@ -0,0 +1,105 @@
+From 6ca0fc50d82e4ee0c1f5a2ba35cc692cfb4eeeec Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Thu, 26 May 2022 22:42:16 +0200
+Subject: [PATCH 13/51] arm64: dts: rockchip: adjust whitespace around '='
+
+Fix whitespace coding style: use single space instead of tabs or
+multiple spaces around '=' sign in property assignment. No functional
+changes (same DTB).
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20220526204218.832029-1-krzysztof.kozlowski@linaro.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/px30.dtsi | 2 +-
+ arch/arm64/boot/dts/rockchip/rk3368.dtsi | 6 +++---
+ arch/arm64/boot/dts/rockchip/rk3399-evb.dts | 2 +-
+ arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts | 2 +-
+ arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts | 2 +-
+ arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 2 +-
+ 6 files changed, 8 insertions(+), 8 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
++++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
+@@ -528,7 +528,7 @@
+ i2c0: i2c@ff180000 {
+ compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xff180000 0x0 0x1000>;
+- clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
++ clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+@@ -1084,7 +1084,7 @@
+
+ gmac {
+ rgmii_pins: rgmii-pins {
+- rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
++ rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ <3 RK_PC3 1 &pcfg_pull_none>,
+ <3 RK_PB0 1 &pcfg_pull_none_12ma>,
+@@ -1102,7 +1102,7 @@
+ };
+
+ rmii_pins: rmii-pins {
+- rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
++ rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ <3 RK_PC3 1 &pcfg_pull_none>,
+ <3 RK_PB0 1 &pcfg_pull_none_12ma>,
+@@ -1257,7 +1257,7 @@
+
+ spdif {
+ spdif_tx: spdif-tx {
+- rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
++ rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
+ };
+ };
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
+@@ -55,7 +55,7 @@
+ };
+
+ edp_panel: edp-panel {
+- compatible ="lg,lp079qx1-sp0v";
++ compatible = "lg,lp079qx1-sp0v";
+ backlight = <&backlight>;
+ enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+ power-supply = <&vcc3v3_s0>;
+--- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
+@@ -49,7 +49,7 @@
+ sgtl5000_clk: sgtl5000-oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+- clock-frequency = <24576000>;
++ clock-frequency = <24576000>;
+ };
+
+ dc_12v: dc-12v {
+--- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
+@@ -88,7 +88,7 @@
+ };
+
+ edp_panel: edp-panel {
+- compatible ="lg,lp079qx1-sp0v";
++ compatible = "lg,lp079qx1-sp0v";
+ backlight = <&backlight>;
+ enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+--- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
+@@ -347,7 +347,7 @@
+
+ pcie {
+ pcie_pwr: pcie-pwr {
+- rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
++ rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
diff --git a/target/linux/rockchip/patches-5.19/0014-arm64-dts-rockchip-Add-HDMI-audio-nodes-to-rk356x.patch b/target/linux/rockchip/patches-5.19/0014-arm64-dts-rockchip-Add-HDMI-audio-nodes-to-rk356x.patch
new file mode 100644
index 00000000000000..5f5d06dd4ce6df
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0014-arm64-dts-rockchip-Add-HDMI-audio-nodes-to-rk356x.patch
@@ -0,0 +1,67 @@
+From 7a32752d0d94ea613092aaa45db136626a55a1ab Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Date: Sat, 11 Jun 2022 08:52:59 +0200
+Subject: [PATCH 14/51] arm64: dts: rockchip: Add HDMI audio nodes to rk356x
+
+This adds the i2s0 node and an hdmi-sound sound device to the
+rk356x device tree. On the rk356[68], the i2s0 controller is
+connected to HDMI audio.
+
+Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
+Tested-by: Peter Geis <pgwipeout@gmail.com>
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Link: https://lore.kernel.org/r/20220611065300.885212-2-frattaroli.nicolas@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 33 ++++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -183,6 +183,22 @@
+ };
+ };
+
++ hdmi_sound: hdmi-sound {
++ compatible = "simple-audio-card";
++ simple-audio-card,name = "HDMI";
++ simple-audio-card,format = "i2s";
++ simple-audio-card,mclk-fs = <256>;
++ status = "disabled";
++
++ simple-audio-card,codec {
++ sound-dai = <&hdmi>;
++ };
++
++ simple-audio-card,cpu {
++ sound-dai = <&i2s0_8ch>;
++ };
++ };
++
+ pmu {
+ compatible = "arm,cortex-a55-pmu";
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
+@@ -950,6 +966,23 @@
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
++
++ i2s0_8ch: i2s@fe400000 {
++ compatible = "rockchip,rk3568-i2s-tdm";
++ reg = <0x0 0xfe400000 0x0 0x1000>;
++ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
++ assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
++ assigned-clock-rates = <1188000000>, <1188000000>;
++ clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
++ clock-names = "mclk_tx", "mclk_rx", "hclk";
++ dmas = <&dmac1 0>;
++ dma-names = "tx";
++ resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
++ reset-names = "tx-m", "rx-m";
++ rockchip,grf = <&grf>;
++ #sound-dai-cells = <0>;
++ status = "disabled";
++ };
+
+ i2s1_8ch: i2s@fe410000 {
+ compatible = "rockchip,rk3568-i2s-tdm";
diff --git a/target/linux/rockchip/patches-5.19/0015-arm64-dts-rockchip-Enable-HDMI-audio-on-Quartz64-A.patch b/target/linux/rockchip/patches-5.19/0015-arm64-dts-rockchip-Enable-HDMI-audio-on-Quartz64-A.patch
new file mode 100644
index 00000000000000..09369e3d838f70
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0015-arm64-dts-rockchip-Enable-HDMI-audio-on-Quartz64-A.patch
@@ -0,0 +1,40 @@
+From 2d330dcbbb5f3ce5ff55a2642aac4fb0d0e0a79e Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Date: Sat, 11 Jun 2022 08:53:00 +0200
+Subject: [PATCH 15/51] arm64: dts: rockchip: Enable HDMI audio on Quartz64 A
+
+This enables the i2s0 controller and the hdmi-sound node on
+the PINE64 Quartz64 Model A single-board computer.
+
+Tested-by: Peter Geis <pgwipeout@gmail.com>
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Link: https://lore.kernel.org/r/20220611065300.885212-3-frattaroli.nicolas@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+@@ -310,6 +310,10 @@
+ };
+ };
+
++&hdmi_sound {
++ status = "okay";
++};
++
+ &i2c0 {
+ status = "okay";
+
+@@ -540,6 +544,10 @@
+ status = "okay";
+ };
+
++&i2s0_8ch {
++ status = "okay";
++};
++
+ &i2s1_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_sclktx
diff --git a/target/linux/rockchip/patches-5.19/0017-arm64-dts-rockchip-add-RTC-to-BPI-R2-Pro.patch b/target/linux/rockchip/patches-5.19/0017-arm64-dts-rockchip-add-RTC-to-BPI-R2-Pro.patch
new file mode 100644
index 00000000000000..e7609aef6f929e
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0017-arm64-dts-rockchip-add-RTC-to-BPI-R2-Pro.patch
@@ -0,0 +1,53 @@
+From 0a691542952f6706436e383f984c38b361c986ee Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Wed, 8 Jun 2022 18:11:49 +0200
+Subject: [PATCH 17/51] arm64: dts: rockchip: add RTC to BPI-R2 Pro
+
+Add devicetree node for hym8563 rtc to Bananapi R2 Pro board.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20220608161150.58919-3-linux@fw-web.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 23 +++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -389,6 +389,23 @@
+ };
+ };
+
++&i2c3 {
++ status = "okay";
++
++ hym8563: rtc@51 {
++ compatible = "haoyu,hym8563";
++ reg = <0x51>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>;
++ #clock-cells = <0>;
++ clock-frequency = <32768>;
++ clock-output-names = "rtcic_32kout";
++ pinctrl-names = "default";
++ pinctrl-0 = <&hym8563_int>;
++ wakeup-source;
++ };
++};
++
+ &i2c5 {
+ /* pin 3 (SDA) + 4 (SCL) of header con2 */
+ status = "disabled";
+@@ -411,6 +428,12 @@
+ };
+ };
+
++ hym8563 {
++ hym8563_int: hym8563-int {
++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins =
diff --git a/target/linux/rockchip/patches-5.19/0019-arm64-dts-rockchip-set-display-regulators-to-always-.patch b/target/linux/rockchip/patches-5.19/0019-arm64-dts-rockchip-set-display-regulators-to-always-.patch
new file mode 100644
index 00000000000000..902ccaa14710aa
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0019-arm64-dts-rockchip-set-display-regulators-to-always-.patch
@@ -0,0 +1,44 @@
+From 032baf8d6c3493e0dcad2c780361faa7ac4f9dde Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Mon, 6 Jun 2022 19:07:59 +0200
+Subject: [PATCH 19/51] arm64: dts: rockchip: set display regulators to
+ always-on on BPI-R2-Pro
+
+The gpu power supply needs to stay always on until the issues with power-
+domains not being regulator aware is resolved. Otherwise we run into
+issues where the gpu-regulator gets shut down and we start getting mmu
+faults.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20220606170803.478082-2-linux@fw-web.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -215,6 +215,7 @@
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
++ regulator-always-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+@@ -264,6 +265,7 @@
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
++ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+@@ -359,6 +361,7 @@
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
++ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
diff --git a/target/linux/rockchip/patches-5.19/0020-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-BPI-R2.patch b/target/linux/rockchip/patches-5.19/0020-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-BPI-R2.patch
new file mode 100644
index 00000000000000..725f4630642196
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0020-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-BPI-R2.patch
@@ -0,0 +1,90 @@
+From ffb2555c106a820acc90d31c201d9879b4400623 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Mon, 6 Jun 2022 19:08:00 +0200
+Subject: [PATCH 20/51] arm64: dts: rockchip: enable vop2 and hdmi tx on
+ BPI-R2-Pro
+
+Enable the RK356x Video Output Processor (VOP) 2 on the
+BananaPi R2 Pro board.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20220606170803.478082-3-linux@fw-web.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 47 +++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -8,6 +8,7 @@
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3568.dtsi"
+
+ / {
+@@ -54,6 +55,17 @@
+ regulator-max-microvolt = <12000000>;
+ };
+
++ hdmi-con {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi_con_in: endpoint {
++ remote-endpoint = <&hdmi_out_con>;
++ };
++ };
++ };
++
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+@@ -174,6 +186,24 @@
+ status = "okay";
+ };
+
++&hdmi {
++ avdd-0v9-supply = <&vdda0v9_image>;
++ avdd-1v8-supply = <&vcca1v8_image>;
++ status = "okay";
++};
++
++&hdmi_in {
++ hdmi_in_vp0: endpoint {
++ remote-endpoint = <&vp0_out_hdmi>;
++ };
++};
++
++&hdmi_out {
++ hdmi_out_con: endpoint {
++ remote-endpoint = <&hdmi_con_in>;
++ };
++};
++
+ &i2c0 {
+ status = "okay";
+
+@@ -613,3 +643,20 @@
+ phy-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+ };
++
++&vop {
++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++ status = "okay";
++};
++
++&vop_mmu {
++ status = "okay";
++};
++
++&vp0 {
++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++ remote-endpoint = <&hdmi_in_vp0>;
++ };
++};
diff --git a/target/linux/rockchip/patches-5.19/0021-arm64-dts-rockchip-Enable-HDMI-audio-on-BPI-R2-Pro.patch b/target/linux/rockchip/patches-5.19/0021-arm64-dts-rockchip-Enable-HDMI-audio-on-BPI-R2-Pro.patch
new file mode 100644
index 00000000000000..65ca0a5f65b488
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0021-arm64-dts-rockchip-Enable-HDMI-audio-on-BPI-R2-Pro.patch
@@ -0,0 +1,40 @@
+From 16fa52e8e2aae8debb651ac5f84a8d49499a301e Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Mon, 6 Jun 2022 19:08:01 +0200
+Subject: [PATCH 21/51] arm64: dts: rockchip: Enable HDMI audio on BPI R2 Pro
+
+This enables the i2s0 controller and the hdmi-sound node on
+the Bananapi R2 Pro single-board computer.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20220606170803.478082-4-linux@fw-web.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -204,6 +204,10 @@
+ };
+ };
+
++&hdmi_sound {
++ status = "okay";
++};
++
+ &i2c0 {
+ status = "okay";
+
+@@ -444,6 +448,11 @@
+ status = "disabled";
+ };
+
++&i2s0_8ch {
++ /* hdmi sound */
++ status = "okay";
++};
++
+ &mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
diff --git a/target/linux/rockchip/patches-5.19/0022-arm64-dts-rockchip-configure-thermal-shutdown-for-BP.patch b/target/linux/rockchip/patches-5.19/0022-arm64-dts-rockchip-configure-thermal-shutdown-for-BP.patch
new file mode 100644
index 00000000000000..7238aabbf9fba2
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0022-arm64-dts-rockchip-configure-thermal-shutdown-for-BP.patch
@@ -0,0 +1,26 @@
+From 6976a5970ca53ac9dba444f4929528c3400152a5 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Mon, 6 Jun 2022 19:08:02 +0200
+Subject: [PATCH 22/51] arm64: dts: rockchip: configure thermal shutdown for
+ BPI-R2-Pro
+
+Add thermal shutdown configuration for use of GPU.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20220606170803.478082-5-linux@fw-web.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -588,6 +588,8 @@
+ };
+
+ &tsadc {
++ rockchip,hw-tshut-mode = <1>;
++ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+ };
+
diff --git a/target/linux/rockchip/patches-5.19/0023-arm64-dts-rockchip-enable-the-gpu-on-BPI-R2-Pro.patch b/target/linux/rockchip/patches-5.19/0023-arm64-dts-rockchip-enable-the-gpu-on-BPI-R2-Pro.patch
new file mode 100644
index 00000000000000..8a86137080df3f
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0023-arm64-dts-rockchip-enable-the-gpu-on-BPI-R2-Pro.patch
@@ -0,0 +1,28 @@
+From 92e9e89c7fe9178cb56dba0faf4b0fabbc19d97d Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Mon, 6 Jun 2022 19:08:03 +0200
+Subject: [PATCH 23/51] arm64: dts: rockchip: enable the gpu on BPI-R2-Pro
+
+Enable the GPU core on the Rockchip RK3568 BananaPi R2 Pro
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20220606170803.478082-6-linux@fw-web.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -186,6 +186,11 @@
+ status = "okay";
+ };
+
++&gpu {
++ mali-supply = <&vdd_gpu>;
++ status = "okay";
++};
++
+ &hdmi {
+ avdd-0v9-supply = <&vdda0v9_image>;
+ avdd-1v8-supply = <&vcca1v8_image>;
diff --git a/target/linux/rockchip/patches-5.19/0024-arm64-dts-rockchip-Add-missing-space-around-regulato.patch b/target/linux/rockchip/patches-5.19/0024-arm64-dts-rockchip-Add-missing-space-around-regulato.patch
new file mode 100644
index 00000000000000..41a6973b825803
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0024-arm64-dts-rockchip-Add-missing-space-around-regulato.patch
@@ -0,0 +1,31 @@
+From fe99ab9113e33c825d1efb8d66f79e217e3108bf Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Niklas=20S=C3=B6derlund?=
+ <niklas.soderlund+renesas@ragnatech.se>
+Date: Mon, 13 Jun 2022 00:31:57 +0200
+Subject: [PATCH 24/51] arm64: dts: rockchip: Add missing space around
+ regulator-name on rk3368-orion-r68
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add the missing space around the regulator-name property before the typo
+spreads to other files.
+
+Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Link: https://lore.kernel.org/r/20220612223201.2740248-3-niklas.soderlund+renesas@ragnatech.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
+@@ -134,7 +134,7 @@
+
+ vccio_sd: vcc-io-sd-regulator {
+ compatible = "regulator-fixed";
+- regulator-name= "vccio_sd";
++ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
diff --git a/target/linux/rockchip/patches-5.19/0025-arm64-dts-rockchip-add-ROCK-Pi-S-DTS-support.patch b/target/linux/rockchip/patches-5.19/0025-arm64-dts-rockchip-add-ROCK-Pi-S-DTS-support.patch
new file mode 100644
index 00000000000000..f787cd2282a41c
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0025-arm64-dts-rockchip-add-ROCK-Pi-S-DTS-support.patch
@@ -0,0 +1,245 @@
+From 50373d43ecd2504c240f0048087bf0a1fd6e8b4c Mon Sep 17 00:00:00 2001
+From: Akash Gajjar <akash@openedev.com>
+Date: Tue, 14 Jun 2022 08:48:56 +0200
+Subject: [PATCH 25/51] arm64: dts: rockchip: add ROCK Pi S DTS support
+
+ROCK Pi S is RK3308 based SBC from radxa.com. ROCK Pi S has a,
+- 256MB/512MB DDR3 RAM
+- SD, NAND flash (optional on board 1/2/4/8Gb)
+- 100MB ethernet, PoE (optional)
+- Onboard 802.11 b/g/n wifi + Bluetooth 4.0 Module
+- USB2.0 Type-A HOST x1
+- USB3.0 Type-C OTG x1
+- 26-pin expansion header
+- USB Type-C DC 5V Power Supply
+
+This patch enables
+- Console
+- NAND Flash
+- SD Card
+
+Signed-off-by: Akash Gajjar <akash@openedev.com>
+[sjoerd: Sort dt nodes, drop properties duplicated from dtsi]
+Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
+Link: https://lore.kernel.org/r/20220614064858.1445817-3-sjoerd@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 1 +
+ .../boot/dts/rockchip/rk3308-rock-pi-s.dts | 201 ++++++++++++++++++
+ 2 files changed, 202 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engi
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
+@@ -0,0 +1,201 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2019 Akash Gajjar <akash@openedev.com>
++ * Copyright (c) 2019 Jagan Teki <jagan@openedev.com>
++ */
++
++/dts-v1/;
++#include "rk3308.dtsi"
++
++/ {
++ model = "Radxa ROCK Pi S";
++ compatible = "radxa,rockpis", "rockchip,rk3308";
++
++ chosen {
++ stdout-path = "serial0:1500000n8";
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&green_led_gio>, <&heartbeat_led_gpio>;
++
++ green-led {
++ default-state = "on";
++ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++ label = "rockpis:green:power";
++ linux,default-trigger = "default-on";
++ };
++
++ blue-led {
++ default-state = "on";
++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
++ label = "rockpis:blue:user";
++ linux,default-trigger = "heartbeat";
++ };
++ };
++
++ sdio_pwrseq: sdio-pwrseq {
++ compatible = "mmc-pwrseq-simple";
++ pinctrl-0 = <&wifi_enable_h>;
++ pinctrl-names = "default";
++ reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
++ };
++
++ vcc_1v8: vcc-1v8 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_1v8";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ vin-supply = <&vcc_io>;
++ };
++
++ vcc_io: vcc-io {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_io";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc_ddr: vcc-ddr {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_ddr";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1500000>;
++ regulator-max-microvolt = <1500000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc5v0_otg: vcc5v0-otg {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&otg_vbus_drv>;
++ regulator-name = "vcc5v0_otg";
++ regulator-always-on;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc5v0_sys: vcc5v0-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ vdd_core: vdd-core {
++ compatible = "pwm-regulator";
++ pwms = <&pwm0 0 5000 1>;
++ pwm-supply = <&vcc5v0_sys>;
++ regulator-name = "vdd_core";
++ regulator-min-microvolt = <827000>;
++ regulator-max-microvolt = <1340000>;
++ regulator-init-microvolt = <1015000>;
++ regulator-settling-time-up-us = <250>;
++ regulator-always-on;
++ regulator-boot-on;
++ };
++
++ vdd_log: vdd-log {
++ compatible = "regulator-fixed";
++ regulator-name = "vdd_log";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1050000>;
++ regulator-max-microvolt = <1050000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++};
++
++&cpu0 {
++ cpu-supply = <&vdd_core>;
++};
++
++&emmc {
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ mmc-hs200-1_8v;
++ non-removable;
++ vmmc-supply = <&vcc_io>;
++ status = "okay";
++};
++
++&i2c1 {
++ status = "okay";
++};
++
++&pinctrl {
++ pinctrl-names = "default";
++ pinctrl-0 = <&rtc_32k>;
++
++ leds {
++ green_led_gio: green-led-gpio {
++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ heartbeat_led_gpio: heartbeat-led-gpio {
++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ usb {
++ otg_vbus_drv: otg-vbus-drv {
++ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ sdio-pwrseq {
++ wifi_enable_h: wifi-enable-h {
++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ wifi_host_wake: wifi-host-wake {
++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
++ };
++ };
++};
++
++&pwm0 {
++ status = "okay";
++ pinctrl-0 = <&pwm0_pin_pull_down>;
++};
++
++&saradc {
++ vref-supply = <&vcc_1v8>;
++ status = "okay";
++};
++
++&sdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ cap-sd-highspeed;
++ cap-sdio-irq;
++ keep-power-in-suspend;
++ max-frequency = <1000000>;
++ mmc-pwrseq = <&sdio_pwrseq>;
++ non-removable;
++ sd-uhs-sdr104;
++ status = "okay";
++};
++
++&sdmmc {
++ cap-sd-highspeed;
++ status = "okay";
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&uart4 {
++ status = "okay";
++};
diff --git a/target/linux/rockchip/patches-5.19/0026-arm64-dts-rockchip-rock-pi-s-add-more-peripherals.patch b/target/linux/rockchip/patches-5.19/0026-arm64-dts-rockchip-rock-pi-s-add-more-peripherals.patch
new file mode 100644
index 00000000000000..20b5695fe22d5e
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0026-arm64-dts-rockchip-rock-pi-s-add-more-peripherals.patch
@@ -0,0 +1,100 @@
+From a1bee6a014cf68d8298c370115f7036f0dcb4f59 Mon Sep 17 00:00:00 2001
+From: Sjoerd Simons <sjoerd@collabora.com>
+Date: Tue, 14 Jun 2022 08:48:57 +0200
+Subject: [PATCH 26/51] arm64: dts: rockchip: rock-pi-s add more peripherals
+
+This enables the following peripherals:
+* Onboard ethernet support
+* Bluetooth
+* USB 2 port
+* OTG port via type-c connector
+* Hardware watchog
+
+Also add aliases for the mmc devices and the ethernet interface
+
+Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
+Link: https://lore.kernel.org/r/20220614064858.1445817-4-sjoerd@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3308-rock-pi-s.dts | 52 +++++++++++++++++++
+ 1 file changed, 52 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
+@@ -11,6 +11,12 @@
+ model = "Radxa ROCK Pi S";
+ compatible = "radxa,rockpis", "rockchip,rk3308";
+
++ aliases {
++ ethernet0 = &gmac;
++ mmc0 = &emmc;
++ mmc1 = &sdmmc;
++ };
++
+ chosen {
+ stdout-path = "serial0:1500000n8";
+ };
+@@ -129,6 +135,15 @@
+ status = "okay";
+ };
+
++&gmac {
++ clock_in_out = "output";
++ phy-supply = <&vcc_io>;
++ snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
++ snps,reset-active-low;
++ snps,reset-delays-us = <0 50000 50000>;
++ status = "okay";
++};
++
+ &i2c1 {
+ status = "okay";
+ };
+@@ -192,10 +207,47 @@
+ status = "okay";
+ };
+
++&u2phy {
++ status = "okay";
++
++ u2phy_host: host-port {
++ phy-supply = <&vcc5v0_otg>;
++ status = "okay";
++ };
++
++ u2phy_otg: otg-port {
++ phy-supply = <&vcc5v0_otg>;
++ status = "okay";
++ };
++};
++
+ &uart0 {
+ status = "okay";
+ };
+
+ &uart4 {
+ status = "okay";
++
++ bluetooth {
++ compatible = "realtek,rtl8723bs-bt";
++ device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
++ host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
++ };
++};
++
++&usb_host_ehci {
++ status = "okay";
++};
++
++&usb_host_ohci {
++ status = "okay";
++};
++
++&usb20_otg {
++ dr_mode = "peripheral";
++ status = "okay";
++};
++
++&wdt {
++ status = "okay";
+ };
diff --git a/target/linux/rockchip/patches-5.19/0027-arm64-dts-rockchip-align-gpio-key-node-names-with-dt.patch b/target/linux/rockchip/patches-5.19/0027-arm64-dts-rockchip-align-gpio-key-node-names-with-dt.patch
new file mode 100644
index 00000000000000..3df5bf71fc4a79
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0027-arm64-dts-rockchip-align-gpio-key-node-names-with-dt.patch
@@ -0,0 +1,369 @@
+From deefbffc188d3b0c9e08fa1ce31bb098839a9995 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Wed, 15 Jun 2022 17:53:19 -0700
+Subject: [PATCH 27/51] arm64: dts: rockchip: align gpio-key node names with
+ dtschema
+
+The node names should be generic and DT schema expects certain pattern
+(e.g. with key/button/switch).
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20220616005333.18491-26-krzysztof.kozlowski@linaro.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3308-evb.dts | 2 +-
+ .../boot/dts/rockchip/rk3326-odroid-go2.dts | 32 +++++++++----------
+ .../boot/dts/rockchip/rk3328-nanopi-r2s.dts | 2 +-
+ arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi | 2 +-
+ .../boot/dts/rockchip/rk3368-geekbox.dts | 2 +-
+ .../dts/rockchip/rk3368-orion-r68-meta.dts | 2 +-
+ .../boot/dts/rockchip/rk3368-px5-evb.dts | 2 +-
+ arch/arm64/boot/dts/rockchip/rk3368-r88.dts | 2 +-
+ .../boot/dts/rockchip/rk3399-firefly.dts | 2 +-
+ .../dts/rockchip/rk3399-gru-chromebook.dtsi | 2 +-
+ .../boot/dts/rockchip/rk3399-gru-kevin.dts | 2 +-
+ .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 2 +-
+ .../boot/dts/rockchip/rk3399-khadas-edge.dtsi | 2 +-
+ .../boot/dts/rockchip/rk3399-nanopi-r4s.dts | 4 +--
+ .../boot/dts/rockchip/rk3399-nanopi4.dtsi | 2 +-
+ .../boot/dts/rockchip/rk3399-orangepi.dts | 2 +-
+ .../boot/dts/rockchip/rk3399-pinebook-pro.dts | 4 +--
+ .../boot/dts/rockchip/rk3399-roc-pc.dtsi | 2 +-
+ .../boot/dts/rockchip/rk3399-rockpro64.dtsi | 2 +-
+ .../boot/dts/rockchip/rk3399-sapphire.dtsi | 2 +-
+ .../boot/dts/rockchip/rk3566-pinenote.dtsi | 2 +-
+ 21 files changed, 38 insertions(+), 38 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3308-evb.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3308-evb.dts
+@@ -75,7 +75,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key>;
+
+- power {
++ key-power {
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ label = "GPIO Key Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
+@@ -71,82 +71,82 @@
+ * |------------------------------------------------|
+ */
+
+- sw1 {
++ button-sw1 {
+ gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
+ label = "DPAD-UP";
+ linux,code = <BTN_DPAD_UP>;
+ };
+- sw2 {
++ button-sw2 {
+ gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>;
+ label = "DPAD-DOWN";
+ linux,code = <BTN_DPAD_DOWN>;
+ };
+- sw3 {
++ button-sw3 {
+ gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
+ label = "DPAD-LEFT";
+ linux,code = <BTN_DPAD_LEFT>;
+ };
+- sw4 {
++ button-sw4 {
+ gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
+ label = "DPAD-RIGHT";
+ linux,code = <BTN_DPAD_RIGHT>;
+ };
+- sw5 {
++ button-sw5 {
+ gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>;
+ label = "BTN-A";
+ linux,code = <BTN_EAST>;
+ };
+- sw6 {
++ button-sw6 {
+ gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "BTN-B";
+ linux,code = <BTN_SOUTH>;
+ };
+- sw7 {
++ button-sw7 {
+ gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
+ label = "BTN-Y";
+ linux,code = <BTN_WEST>;
+ };
+- sw8 {
++ button-sw8 {
+ gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
+ label = "BTN-X";
+ linux,code = <BTN_NORTH>;
+ };
+- sw9 {
++ button-sw9 {
+ gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
+ label = "F1";
+ linux,code = <BTN_TRIGGER_HAPPY1>;
+ };
+- sw10 {
++ button-sw10 {
+ gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>;
+ label = "F2";
+ linux,code = <BTN_TRIGGER_HAPPY2>;
+ };
+- sw11 {
++ button-sw11 {
+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
+ label = "F3";
+ linux,code = <BTN_TRIGGER_HAPPY3>;
+ };
+- sw12 {
++ button-sw12 {
+ gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>;
+ label = "F4";
+ linux,code = <BTN_TRIGGER_HAPPY4>;
+ };
+- sw13 {
++ button-sw13 {
+ gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>;
+ label = "F5";
+ linux,code = <BTN_TRIGGER_HAPPY5>;
+ };
+- sw14 {
++ button-sw14 {
+ gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "F6";
+ linux,code = <BTN_TRIGGER_HAPPY6>;
+ };
+- sw15 {
++ button-sw15 {
+ gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
+ label = "TOP-LEFT";
+ linux,code = <BTN_TL>;
+ };
+- sw16 {
++ button-sw16 {
+ gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
+ label = "TOP-RIGHT";
+ linux,code = <BTN_TR>;
+--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+@@ -34,7 +34,7 @@
+ pinctrl-0 = <&reset_button_pin>;
+ pinctrl-names = "default";
+
+- reset {
++ key-reset {
+ label = "reset";
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+--- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
+@@ -76,7 +76,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key>;
+
+- power {
++ key-power {
+ wakeup-source;
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
+@@ -43,7 +43,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key>;
+
+- power {
++ key-power {
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+ linux,code = <KEY_POWER>;
+--- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
+@@ -44,7 +44,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key>;
+
+- power {
++ key-power {
+ wakeup-source;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ label = "GPIO Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
+@@ -30,7 +30,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key>;
+
+- power {
++ key-power {
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+ linux,code = <KEY_POWER>;
+--- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
+@@ -37,7 +37,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key>;
+
+- power {
++ key-power {
+ wakeup-source;
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
+@@ -87,7 +87,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwrbtn>;
+
+- power {
++ key-power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
+@@ -206,7 +206,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l>;
+
+- wake_on_bt: wake-on-bt {
++ wake_on_bt: key-wake-on-bt {
+ label = "Wake-on-Bluetooth";
+ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WAKEUP>;
+--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
+@@ -92,7 +92,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>;
+
+- pen-insert {
++ switch-pen-insert {
+ label = "Pen Insert";
+ /* Insert = low, eject = high */
+ gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
+--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
+@@ -183,7 +183,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pen_eject_odl>;
+
+- pen-insert {
++ switch-pen-insert {
+ label = "Pen Insert";
+ /* Insert = low, eject = high */
+ gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+--- a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
+@@ -136,7 +136,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwrbtn>;
+
+- power {
++ key-power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+@@ -46,9 +46,9 @@
+ gpio-keys {
+ pinctrl-0 = <&reset_button_pin>;
+
+- /delete-node/ power;
++ /delete-node/ key-power;
+
+- reset {
++ key-reset {
+ debounce-interval = <50>;
+ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+ label = "reset";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+@@ -111,7 +111,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&power_key>;
+
+- power {
++ key-power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
+@@ -78,7 +78,7 @@
+ compatible = "gpio-keys";
+ autorepeat;
+
+- power {
++ key-power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+@@ -76,7 +76,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&lidbtn_pin>;
+
+- lid {
++ switch-lid {
+ debounce-interval = <20>;
+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>;
+ label = "Lid";
+@@ -92,7 +92,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwrbtn_pin>;
+
+- power {
++ key-power {
+ debounce-interval = <20>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
+@@ -54,7 +54,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key_l>;
+
+- power {
++ key-power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+@@ -42,7 +42,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwrbtn>;
+
+- power {
++ key-power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
+@@ -53,7 +53,7 @@
+ compatible = "gpio-keys";
+ autorepeat;
+
+- power {
++ key-power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+--- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
+@@ -49,7 +49,7 @@
+ pinctrl-0 = <&hall_int_l>;
+ pinctrl-names = "default";
+
+- cover {
++ switch-cover {
+ label = "cover";
+ gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
diff --git a/target/linux/rockchip/patches-5.19/0028-arm64-dts-rockchip-enable-hdmi-tx-audio-on-rk3568-ev.patch b/target/linux/rockchip/patches-5.19/0028-arm64-dts-rockchip-enable-hdmi-tx-audio-on-rk3568-ev.patch
new file mode 100644
index 00000000000000..ed38b3cc617551
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0028-arm64-dts-rockchip-enable-hdmi-tx-audio-on-rk3568-ev.patch
@@ -0,0 +1,40 @@
+From ff2aa1ec6f09917d03959bc2250eccf5f9c24f0c Mon Sep 17 00:00:00 2001
+From: Michael Riesch <michael.riesch@wolfvision.net>
+Date: Wed, 15 Jun 2022 01:03:53 +0200
+Subject: [PATCH 28/51] arm64: dts: rockchip: enable hdmi tx audio on
+ rk3568-evb1-v10
+
+Enable the I2S0 controller and the hdmi-sound node on the Rockchip
+RK3568 EVB1.
+
+Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
+Link: https://lore.kernel.org/r/20220614230354.3756364-1-michael.riesch@wolfvision.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
+@@ -239,6 +239,10 @@
+ };
+ };
+
++&hdmi_sound {
++ status = "okay";
++};
++
+ &i2c0 {
+ status = "okay";
+
+@@ -496,6 +500,10 @@
+ };
+ };
+
++&i2s0_8ch {
++ status = "okay";
++};
++
+ &i2s1_8ch {
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
diff --git a/target/linux/rockchip/patches-5.19/0029-arm64-dts-rockchip-enable-hdmi-tx-audio-on-rock-3a.patch b/target/linux/rockchip/patches-5.19/0029-arm64-dts-rockchip-enable-hdmi-tx-audio-on-rock-3a.patch
new file mode 100644
index 00000000000000..176ac8cb6dde31
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0029-arm64-dts-rockchip-enable-hdmi-tx-audio-on-rock-3a.patch
@@ -0,0 +1,39 @@
+From f33757d7c1a25febc85546f9a398e23ad449de05 Mon Sep 17 00:00:00 2001
+From: Michael Riesch <michael.riesch@wolfvision.net>
+Date: Wed, 15 Jun 2022 01:03:54 +0200
+Subject: [PATCH 29/51] arm64: dts: rockchip: enable hdmi tx audio on rock-3a
+
+Enable the I2S0 controller and the hdmi-sound node on the Radxa
+ROCK3 Model A.
+
+Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
+Link: https://lore.kernel.org/r/20220614230354.3756364-2-michael.riesch@wolfvision.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+@@ -196,6 +196,10 @@
+ };
+ };
+
++&hdmi_sound {
++ status = "okay";
++};
++
+ &i2c0 {
+ status = "okay";
+
+@@ -436,6 +440,10 @@
+ };
+ };
+
++&i2s0_8ch {
++ status = "okay";
++};
++
+ &i2s1_8ch {
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
diff --git a/target/linux/rockchip/patches-5.19/0030-arm64-dts-rockchip-Add-mt7531-dsa-node-to-BPI-R2-Pro.patch b/target/linux/rockchip/patches-5.19/0030-arm64-dts-rockchip-Add-mt7531-dsa-node-to-BPI-R2-Pro.patch
new file mode 100644
index 00000000000000..797c4538b90f27
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0030-arm64-dts-rockchip-Add-mt7531-dsa-node-to-BPI-R2-Pro.patch
@@ -0,0 +1,72 @@
+From a502eafcfbed31cb01e71e23553f9348a08c3cfe Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 10 Jun 2022 19:05:41 +0200
+Subject: [PATCH 30/51] arm64: dts: rockchip: Add mt7531 dsa node to BPI-R2-Pro
+ board
+
+Add Device Tree node for mt7531 switch connected to gmac0.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 48 +++++++++++++++++++
+ 1 file changed, 48 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -458,6 +458,54 @@
+ status = "okay";
+ };
+
++&mdio0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ switch@0 {
++ compatible = "mediatek,mt7531";
++ reg = <0>;
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@1 {
++ reg = <1>;
++ label = "lan0";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan1";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan2";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "lan3";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ phy-mode = "rgmii";
++
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ pause;
++ };
++ };
++ };
++ };
++};
++
+ &mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
diff --git a/target/linux/rockchip/patches-5.19/0031-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch b/target/linux/rockchip/patches-5.19/0031-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch
new file mode 100644
index 00000000000000..ba29830411603d
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0031-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch
@@ -0,0 +1,87 @@
+From fd0e3d705a8ee61e822c9f4e74c34567a9a31335 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 10 Jun 2022 19:05:37 +0200
+Subject: [PATCH 31/51] net: dsa: mt7530: rework mt7530_hw_vlan_{add,del}
+
+Rework vlan_add/vlan_del functions in preparation for dynamic cpu port.
+
+Currently BIT(MT7530_CPU_PORT) is added to new_members, even though
+mt7530_port_vlan_add() will be called on the CPU port too.
+
+Let DSA core decide when to call port_vlan_add for the CPU port, rather
+than doing it implicitly.
+
+We can do autonomous forwarding in a certain VLAN, but not add br0 to that
+VLAN and avoid flooding the CPU with those packets, if software knows it
+doesn't need to process them.
+
+Suggested-by: Vladimir Oltean <olteanv@gmail.com>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 30 ++++++++++++------------------
+ 1 file changed, 12 insertions(+), 18 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1527,11 +1527,11 @@ static void
+ mt7530_hw_vlan_add(struct mt7530_priv *priv,
+ struct mt7530_hw_vlan_entry *entry)
+ {
++ struct dsa_port *dp = dsa_to_port(priv->ds, entry->port);
+ u8 new_members;
+ u32 val;
+
+- new_members = entry->old_members | BIT(entry->port) |
+- BIT(MT7530_CPU_PORT);
++ new_members = entry->old_members | BIT(entry->port);
+
+ /* Validate the entry with independent learning, create egress tag per
+ * VLAN and joining the port as one of the port members.
+@@ -1542,22 +1542,20 @@ mt7530_hw_vlan_add(struct mt7530_priv *p
+
+ /* Decide whether adding tag or not for those outgoing packets from the
+ * port inside the VLAN.
+- */
+- val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
+- MT7530_VLAN_EGRESS_TAG;
+- mt7530_rmw(priv, MT7530_VAWD2,
+- ETAG_CTRL_P_MASK(entry->port),
+- ETAG_CTRL_P(entry->port, val));
+-
+- /* CPU port is always taken as a tagged port for serving more than one
++ * CPU port is always taken as a tagged port for serving more than one
+ * VLANs across and also being applied with egress type stack mode for
+ * that VLAN tags would be appended after hardware special tag used as
+ * DSA tag.
+ */
++ if (dsa_port_is_cpu(dp))
++ val = MT7530_VLAN_EGRESS_STACK;
++ else if (entry->untagged)
++ val = MT7530_VLAN_EGRESS_UNTAG;
++ else
++ val = MT7530_VLAN_EGRESS_TAG;
+ mt7530_rmw(priv, MT7530_VAWD2,
+- ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
+- ETAG_CTRL_P(MT7530_CPU_PORT,
+- MT7530_VLAN_EGRESS_STACK));
++ ETAG_CTRL_P_MASK(entry->port),
++ ETAG_CTRL_P(entry->port, val));
+ }
+
+ static void
+@@ -1576,11 +1574,7 @@ mt7530_hw_vlan_del(struct mt7530_priv *p
+ return;
+ }
+
+- /* If certain member apart from CPU port is still alive in the VLAN,
+- * the entry would be kept valid. Otherwise, the entry is got to be
+- * disabled.
+- */
+- if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
++ if (new_members) {
+ val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
+ VLAN_VALID;
+ mt7530_write(priv, MT7530_VAWD1, val);
diff --git a/target/linux/rockchip/patches-5.19/0032-net-dsa-mt7530-rework-mt753-01-_setup.patch b/target/linux/rockchip/patches-5.19/0032-net-dsa-mt7530-rework-mt753-01-_setup.patch
new file mode 100644
index 00000000000000..0ce93ecd67c5cf
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0032-net-dsa-mt7530-rework-mt753-01-_setup.patch
@@ -0,0 +1,75 @@
+From 65046fea942259fb22ae9cdfb86971d8c4e4237b Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 10 Jun 2022 19:05:38 +0200
+Subject: [PATCH 32/51] net: dsa: mt7530: rework mt753[01]_setup
+
+Enumerate available cpu-ports instead of using hardcoded constant.
+
+Suggested-by: Vladimir Oltean <olteanv@gmail.com>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 25 +++++++++++++++++++++----
+ 1 file changed, 21 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2092,11 +2092,12 @@ static int
+ mt7530_setup(struct dsa_switch *ds)
+ {
+ struct mt7530_priv *priv = ds->priv;
++ struct device_node *dn = NULL;
+ struct device_node *phy_node;
+ struct device_node *mac_np;
+ struct mt7530_dummy_poll p;
+ phy_interface_t interface;
+- struct device_node *dn;
++ struct dsa_port *cpu_dp;
+ u32 id, val;
+ int ret, i;
+
+@@ -2104,7 +2105,19 @@ mt7530_setup(struct dsa_switch *ds)
+ * controller also is the container for two GMACs nodes representing
+ * as two netdev instances.
+ */
+- dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
++ dsa_switch_for_each_cpu_port(cpu_dp, ds) {
++ dn = cpu_dp->master->dev.of_node->parent;
++ /* It doesn't matter which CPU port is found first,
++ * their masters should share the same parent OF node
++ */
++ break;
++ }
++
++ if (!dn) {
++ dev_err(ds->dev, "parent OF node of DSA master not found");
++ return -EINVAL;
++ }
++
+ ds->assisted_learning_on_cpu_port = true;
+ ds->mtu_enforcement_ingress = true;
+
+@@ -2266,6 +2279,7 @@ mt7531_setup(struct dsa_switch *ds)
+ {
+ struct mt7530_priv *priv = ds->priv;
+ struct mt7530_dummy_poll p;
++ struct dsa_port *cpu_dp;
+ u32 val, id;
+ int ret, i;
+
+@@ -2338,8 +2352,11 @@ mt7531_setup(struct dsa_switch *ds)
+ CORE_PLL_GROUP4, val);
+
+ /* BPDU to CPU port */
+- mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
+- BIT(MT7530_CPU_PORT));
++ dsa_switch_for_each_cpu_port(cpu_dp, ds) {
++ mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
++ BIT(cpu_dp->index));
++ break;
++ }
+ mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
+ MT753X_BPDU_CPU_ONLY);
+
diff --git a/target/linux/rockchip/patches-5.19/0033-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch b/target/linux/rockchip/patches-5.19/0033-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch
new file mode 100644
index 00000000000000..d06f4703f41d20
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0033-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch
@@ -0,0 +1,117 @@
+From 28650c65d8ca16a1b607a06fd0bce67371143069 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 10 Jun 2022 19:05:39 +0200
+Subject: [PATCH 33/51] net: dsa: mt7530: get cpu-port via dp->cpu_dp instead
+ of constant
+
+Replace last occurences of hardcoded cpu-port by cpu_dp member of
+dsa_port struct.
+
+Now the constant can be dropped.
+
+Suggested-by: Vladimir Oltean <olteanv@gmail.com>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 27 ++++++++++++++++++++-------
+ drivers/net/dsa/mt7530.h | 1 -
+ 2 files changed, 20 insertions(+), 8 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1038,6 +1038,7 @@ static int
+ mt7530_port_enable(struct dsa_switch *ds, int port,
+ struct phy_device *phy)
+ {
++ struct dsa_port *dp = dsa_to_port(ds, port);
+ struct mt7530_priv *priv = ds->priv;
+
+ mutex_lock(&priv->reg_mutex);
+@@ -1046,7 +1047,11 @@ mt7530_port_enable(struct dsa_switch *ds
+ * restore the port matrix if the port is the member of a certain
+ * bridge.
+ */
+- priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
++ if (dsa_port_is_user(dp)) {
++ struct dsa_port *cpu_dp = dp->cpu_dp;
++
++ priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index));
++ }
+ priv->ports[port].enable = true;
+ mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
+ priv->ports[port].pm);
+@@ -1195,7 +1200,8 @@ mt7530_port_bridge_join(struct dsa_switc
+ struct netlink_ext_ack *extack)
+ {
+ struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
+- u32 port_bitmap = BIT(MT7530_CPU_PORT);
++ struct dsa_port *cpu_dp = dp->cpu_dp;
++ u32 port_bitmap = BIT(cpu_dp->index);
+ struct mt7530_priv *priv = ds->priv;
+
+ mutex_lock(&priv->reg_mutex);
+@@ -1272,9 +1278,12 @@ mt7530_port_set_vlan_unaware(struct dsa_
+ * the CPU port get out of VLAN filtering mode.
+ */
+ if (all_user_ports_removed) {
+- mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
++ struct dsa_port *dp = dsa_to_port(ds, port);
++ struct dsa_port *cpu_dp = dp->cpu_dp;
++
++ mt7530_write(priv, MT7530_PCR_P(cpu_dp->index),
+ PCR_MATRIX(dsa_user_ports(priv->ds)));
+- mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG
++ mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG
+ | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
+ }
+ }
+@@ -1312,6 +1321,7 @@ mt7530_port_bridge_leave(struct dsa_swit
+ struct dsa_bridge bridge)
+ {
+ struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
++ struct dsa_port *cpu_dp = dp->cpu_dp;
+ struct mt7530_priv *priv = ds->priv;
+
+ mutex_lock(&priv->reg_mutex);
+@@ -1340,8 +1350,8 @@ mt7530_port_bridge_leave(struct dsa_swit
+ */
+ if (priv->ports[port].enable)
+ mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
+- PCR_MATRIX(BIT(MT7530_CPU_PORT)));
+- priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
++ PCR_MATRIX(BIT(cpu_dp->index)));
++ priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index));
+
+ /* When a port is removed from the bridge, the port would be set up
+ * back to the default as is at initial boot which is a VLAN-unaware
+@@ -1508,6 +1518,9 @@ static int
+ mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
+ struct netlink_ext_ack *extack)
+ {
++ struct dsa_port *dp = dsa_to_port(ds, port);
++ struct dsa_port *cpu_dp = dp->cpu_dp;
++
+ if (vlan_filtering) {
+ /* The port is being kept as VLAN-unaware port when bridge is
+ * set up with vlan_filtering not being set, Otherwise, the
+@@ -1515,7 +1528,7 @@ mt7530_port_vlan_filtering(struct dsa_sw
+ * for becoming a VLAN-aware port.
+ */
+ mt7530_port_set_vlan_aware(ds, port);
+- mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
++ mt7530_port_set_vlan_aware(ds, cpu_dp->index);
+ } else {
+ mt7530_port_set_vlan_unaware(ds, port);
+ }
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -8,7 +8,6 @@
+
+ #define MT7530_NUM_PORTS 7
+ #define MT7530_NUM_PHYS 5
+-#define MT7530_CPU_PORT 6
+ #define MT7530_NUM_FDB_RECORDS 2048
+ #define MT7530_ALL_MEMBERS 0xff
+
diff --git a/target/linux/rockchip/patches-5.19/0034-drm-rockchip-Fix-Kconfig-dependencies-for-display-po.patch b/target/linux/rockchip/patches-5.19/0034-drm-rockchip-Fix-Kconfig-dependencies-for-display-po.patch
new file mode 100644
index 00000000000000..47cb28b7b92e47
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0034-drm-rockchip-Fix-Kconfig-dependencies-for-display-po.patch
@@ -0,0 +1,46 @@
+From 83aef06999a8ee66444ef52986834780f5e4f94a Mon Sep 17 00:00:00 2001
+From: Ren Zhijie <renzhijie2@huawei.com>
+Date: Sat, 7 May 2022 18:09:10 +0800
+Subject: [PATCH 34/51] drm/rockchip: Fix Kconfig dependencies for display-port
+ encoders
+
+The DP-helper module has been replaced by the display-helper module.
+So the driver have to select it.
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Fixes: 1e0f66420b13("drm/display: Introduce a DRM display-helper module")
+Signed-off-by: Ren Zhijie <renzhijie2@huawei.com>
+Reviewed-by: Andy Yan <andy.yan@rock-chips.com>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220507100910.93705-1-renzhijie2@huawei.com
+---
+ drivers/gpu/drm/rockchip/Kconfig | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/rockchip/Kconfig
++++ b/drivers/gpu/drm/rockchip/Kconfig
+@@ -2,7 +2,6 @@
+ config DRM_ROCKCHIP
+ tristate "DRM Support for Rockchip"
+ depends on DRM && ROCKCHIP_IOMMU
+- select DRM_DISPLAY_HELPER if ROCKCHIP_ANALOGIX_DP
+ select DRM_GEM_CMA_HELPER
+ select DRM_KMS_HELPER
+ select DRM_PANEL
+@@ -38,6 +37,7 @@ config ROCKCHIP_VOP2
+ config ROCKCHIP_ANALOGIX_DP
+ bool "Rockchip specific extensions for Analogix DP driver"
+ depends on ROCKCHIP_VOP
++ select DRM_DISPLAY_HELPER
+ select DRM_DISPLAY_DP_HELPER
+ help
+ This selects support for Rockchip SoC specific extensions
+@@ -47,6 +47,8 @@ config ROCKCHIP_ANALOGIX_DP
+ config ROCKCHIP_CDN_DP
+ bool "Rockchip cdn DP"
+ depends on EXTCON=y || (EXTCON=m && DRM_ROCKCHIP=m)
++ select DRM_DISPLAY_HELPER
++ select DRM_DISPLAY_DP_HELPER
+ help
+ This selects support for Rockchip SoC specific extensions
+ for the cdn DP driver. If you want to enable Dp on
diff --git a/target/linux/rockchip/patches-5.19/0035-drm-rockchip-remove-unneeded-semicolon-from-vop2-dri.patch b/target/linux/rockchip/patches-5.19/0035-drm-rockchip-remove-unneeded-semicolon-from-vop2-dri.patch
new file mode 100644
index 00000000000000..86923bcc3f3278
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0035-drm-rockchip-remove-unneeded-semicolon-from-vop2-dri.patch
@@ -0,0 +1,29 @@
+From 9226222a72f2a336495728d24cd9bff7685f1cbe Mon Sep 17 00:00:00 2001
+From: Yang Li <yang.lee@linux.alibaba.com>
+Date: Fri, 6 May 2022 07:26:59 +0800
+Subject: [PATCH 35/51] drm/rockchip: remove unneeded semicolon from vop2
+ driver
+
+Eliminate the following coccicheck warning:
+./drivers/gpu/drm/rockchip/rockchip_drm_vop2.c:1476:2-3: Unneeded
+semicolon
+
+Reported-by: Abaci Robot <abaci@linux.alibaba.com>
+Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220505232659.4405-1-yang.lee@linux.alibaba.com
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+@@ -1473,7 +1473,7 @@ static void rk3568_set_intf_mux(struct v
+ default:
+ drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id);
+ return;
+- };
++ }
+
+ dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD;
+
diff --git a/target/linux/rockchip/patches-5.19/0036-drm-rockchip-Fix-spelling-mistake-aligened-aligned.patch b/target/linux/rockchip/patches-5.19/0036-drm-rockchip-Fix-spelling-mistake-aligened-aligned.patch
new file mode 100644
index 00000000000000..0b3925a6926eb5
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0036-drm-rockchip-Fix-spelling-mistake-aligened-aligned.patch
@@ -0,0 +1,26 @@
+From c130c07b62dd4cc18c9b10ab65da6c6a5d41fcfa Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.i.king@gmail.com>
+Date: Thu, 5 May 2022 12:10:44 +0100
+Subject: [PATCH 36/51] drm/rockchip: Fix spelling mistake "aligened" ->
+ "aligned"
+
+There is a spelling mistake in a drm_err message. Fix it.
+
+Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220505111044.374174-1-colin.i.king@gmail.com
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+@@ -1202,7 +1202,7 @@ static void vop2_plane_atomic_update(str
+ */
+ stride = (fb->pitches[0] << 3) / bpp;
+ if ((stride & 0x3f) && (xmirror || rotate_90 || rotate_270))
+- drm_err(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligened\n",
++ drm_err(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligned\n",
+ vp->id, win->data->name, stride);
+
+ rb_swap = vop2_afbc_rb_swap(fb->format->format);
diff --git a/target/linux/rockchip/patches-5.19/0037-drm-rockchip-vop2-unlock-on-error-path-in-vop2_crtc_.patch b/target/linux/rockchip/patches-5.19/0037-drm-rockchip-vop2-unlock-on-error-path-in-vop2_crtc_.patch
new file mode 100644
index 00000000000000..44b785076bfd84
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0037-drm-rockchip-vop2-unlock-on-error-path-in-vop2_crtc_.patch
@@ -0,0 +1,27 @@
+From 118f07ebcff85e505941b9806171d2fab0cb7b8e Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Mon, 9 May 2022 12:05:05 +0300
+Subject: [PATCH 37/51] drm/rockchip: vop2: unlock on error path in
+ vop2_crtc_atomic_enable()
+
+This error path needs an unlock before returning.
+
+Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://patchwork.freedesktop.org/patch/msgid/YnjZQRV9lpub2ET8@kili
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+@@ -1524,6 +1524,7 @@ static void vop2_crtc_atomic_enable(stru
+ if (ret < 0) {
+ drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n",
+ vp->id, ret);
++ vop2_unlock(vop2);
+ return;
+ }
+
diff --git a/target/linux/rockchip/patches-5.19/0038-drm-Drop-drm_edid.h-from-drm_crtc.h.patch b/target/linux/rockchip/patches-5.19/0038-drm-Drop-drm_edid.h-from-drm_crtc.h.patch
new file mode 100644
index 00000000000000..95eb69b22e4378
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0038-drm-Drop-drm_edid.h-from-drm_crtc.h.patch
@@ -0,0 +1,569 @@
+From 38666f6a53492c98e2224bb292b89671bc2ed866 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Tue, 14 Jun 2022 12:02:45 +0300
+Subject: [PATCH 38/51] drm: Drop drm_edid.h from drm_crtc.h
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+drm_crtc.h has no need for drm_edid.h, so don't include it.
+Avoids useless rebuilds of the entire universe when
+touching drm_edid.h.
+
+Quite a few placs do currently depend on drm_edid.h without
+actually including it directly. All of those need to be fixed
+up.
+
+v2: Fix up i915 and msm some more
+v3: Fix alphabetical ordering (Sam)
+
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220614090245.30283-1-ville.syrjala@linux.intel.com
+Acked-by: Sam Ravnborg <sam@ravnborg.org>
+Acked-by: Jani Nikula <jani.nikula@intel.com>
+---
+ drivers/gpu/drm/arm/malidp_mw.c | 1 +
+ drivers/gpu/drm/aspeed/aspeed_gfx_out.c | 1 +
+ drivers/gpu/drm/ast/ast_mode.c | 1 +
+ drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1 +
+ drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 1 +
+ drivers/gpu/drm/bridge/lontium-lt8912b.c | 1 +
+ drivers/gpu/drm/bridge/parade-ps8640.c | 1 +
+ drivers/gpu/drm/bridge/simple-bridge.c | 1 +
+ drivers/gpu/drm/bridge/ti-tfp410.c | 1 +
+ drivers/gpu/drm/display/drm_dp_helper.c | 1 +
+ drivers/gpu/drm/display/drm_dp_mst_topology.c | 1 +
+ drivers/gpu/drm/drm_client_modeset.c | 1 +
+ drivers/gpu/drm/drm_kms_helper_common.c | 1 +
+ drivers/gpu/drm/drm_modes.c | 1 +
+ drivers/gpu/drm/exynos/exynos_mixer.c | 1 +
+ drivers/gpu/drm/gma500/cdv_intel_dp.c | 1 +
+ drivers/gpu/drm/gma500/oaktrail_hdmi.c | 1 +
+ drivers/gpu/drm/gma500/oaktrail_lvds.c | 1 +
+ drivers/gpu/drm/gma500/psb_intel_modes.c | 2 ++
+ drivers/gpu/drm/gud/gud_connector.c | 1 +
+ drivers/gpu/drm/i915/display/intel_bios.c | 1 +
+ drivers/gpu/drm/i915/display/intel_dp.c | 1 +
+ drivers/gpu/drm/i915/display/intel_lspcon.c | 1 +
+ drivers/gpu/drm/i915/display/intel_opregion.c | 2 ++
+ drivers/gpu/drm/imx/imx-ldb.c | 1 +
+ drivers/gpu/drm/imx/imx-tve.c | 1 +
+ drivers/gpu/drm/imx/parallel-display.c | 1 +
+ drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c | 2 ++
+ drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 1 +
+ drivers/gpu/drm/omapdrm/dss/hdmi4.c | 1 +
+ drivers/gpu/drm/omapdrm/dss/hdmi5.c | 1 +
+ drivers/gpu/drm/panel/panel-edp.c | 1 +
+ drivers/gpu/drm/panel/panel-simple.c | 1 +
+ drivers/gpu/drm/qxl/qxl_display.c | 1 +
+ drivers/gpu/drm/rcar-du/rcar_du_writeback.c | 1 +
+ drivers/gpu/drm/rockchip/rk3066_hdmi.c | 1 +
+ drivers/gpu/drm/solomon/ssd130x.c | 1 +
+ drivers/gpu/drm/stm/ltdc.c | 1 +
+ drivers/gpu/drm/tiny/arcpgu.c | 1 +
+ drivers/gpu/drm/tiny/bochs.c | 1 +
+ drivers/gpu/drm/tiny/cirrus.c | 1 +
+ drivers/gpu/drm/tiny/gm12u320.c | 1 +
+ drivers/gpu/drm/udl/udl_connector.c | 1 +
+ drivers/gpu/drm/vboxvideo/vbox_mode.c | 1 +
+ drivers/gpu/drm/virtio/virtgpu_display.c | 1 +
+ drivers/gpu/drm/virtio/virtgpu_vq.c | 2 ++
+ drivers/gpu/drm/vkms/vkms_output.c | 1 +
+ drivers/gpu/drm/vkms/vkms_writeback.c | 1 +
+ include/drm/drm_crtc.h | 1 -
+ 49 files changed, 52 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/arm/malidp_mw.c
++++ b/drivers/gpu/drm/arm/malidp_mw.c
+@@ -9,6 +9,7 @@
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_crtc.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_fb_cma_helper.h>
+ #include <drm/drm_fourcc.h>
+ #include <drm/drm_gem_cma_helper.h>
+--- a/drivers/gpu/drm/aspeed/aspeed_gfx_out.c
++++ b/drivers/gpu/drm/aspeed/aspeed_gfx_out.c
+@@ -4,6 +4,7 @@
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_connector.h>
+ #include <drm/drm_crtc_helper.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_probe_helper.h>
+
+ #include "aspeed_gfx.h"
+--- a/drivers/gpu/drm/ast/ast_mode.c
++++ b/drivers/gpu/drm/ast/ast_mode.c
+@@ -36,6 +36,7 @@
+ #include <drm/drm_atomic_state_helper.h>
+ #include <drm/drm_crtc.h>
+ #include <drm/drm_crtc_helper.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_fourcc.h>
+ #include <drm/drm_gem_atomic_helper.h>
+ #include <drm/drm_gem_framebuffer_helper.h>
+--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
++++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+@@ -24,6 +24,7 @@
+ #include <drm/drm_bridge.h>
+ #include <drm/drm_crtc.h>
+ #include <drm/drm_device.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_panel.h>
+ #include <drm/drm_print.h>
+ #include <drm/drm_probe_helper.h>
+--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
++++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+@@ -43,6 +43,7 @@
+ #include <drm/drm_bridge.h>
+ #include <drm/drm_connector.h>
+ #include <drm/drm_crtc_helper.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_modeset_helper_vtables.h>
+ #include <drm/drm_print.h>
+ #include <drm/drm_probe_helper.h>
+--- a/drivers/gpu/drm/bridge/lontium-lt8912b.c
++++ b/drivers/gpu/drm/bridge/lontium-lt8912b.c
+@@ -11,6 +11,7 @@
+
+ #include <drm/drm_probe_helper.h>
+ #include <drm/drm_atomic_helper.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_mipi_dsi.h>
+ #include <drm/drm_of.h>
+
+--- a/drivers/gpu/drm/bridge/parade-ps8640.c
++++ b/drivers/gpu/drm/bridge/parade-ps8640.c
+@@ -16,6 +16,7 @@
+ #include <drm/display/drm_dp_aux_bus.h>
+ #include <drm/display/drm_dp_helper.h>
+ #include <drm/drm_bridge.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_mipi_dsi.h>
+ #include <drm/drm_of.h>
+ #include <drm/drm_panel.h>
+--- a/drivers/gpu/drm/bridge/simple-bridge.c
++++ b/drivers/gpu/drm/bridge/simple-bridge.c
+@@ -15,6 +15,7 @@
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_bridge.h>
+ #include <drm/drm_crtc.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_print.h>
+ #include <drm/drm_probe_helper.h>
+
+--- a/drivers/gpu/drm/bridge/ti-tfp410.c
++++ b/drivers/gpu/drm/bridge/ti-tfp410.c
+@@ -14,6 +14,7 @@
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_bridge.h>
+ #include <drm/drm_crtc.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_print.h>
+ #include <drm/drm_probe_helper.h>
+
+--- a/drivers/gpu/drm/display/drm_dp_helper.c
++++ b/drivers/gpu/drm/display/drm_dp_helper.c
+@@ -32,6 +32,7 @@
+
+ #include <drm/display/drm_dp_helper.h>
+ #include <drm/display/drm_dp_mst_helper.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_print.h>
+ #include <drm/drm_vblank.h>
+ #include <drm/drm_panel.h>
+--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
++++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
+@@ -42,6 +42,7 @@
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_drv.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_print.h>
+ #include <drm/drm_probe_helper.h>
+
+--- a/drivers/gpu/drm/drm_client_modeset.c
++++ b/drivers/gpu/drm/drm_client_modeset.c
+@@ -19,6 +19,7 @@
+ #include <drm/drm_crtc.h>
+ #include <drm/drm_device.h>
+ #include <drm/drm_drv.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_encoder.h>
+ #include <drm/drm_print.h>
+
+--- a/drivers/gpu/drm/drm_kms_helper_common.c
++++ b/drivers/gpu/drm/drm_kms_helper_common.c
+@@ -27,6 +27,7 @@
+
+ #include <linux/module.h>
+
++#include <drm/drm_edid.h>
+ #include <drm/drm_print.h>
+
+ #include "drm_crtc_helper_internal.h"
+--- a/drivers/gpu/drm/drm_modes.c
++++ b/drivers/gpu/drm/drm_modes.c
+@@ -41,6 +41,7 @@
+
+ #include <drm/drm_crtc.h>
+ #include <drm/drm_device.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_modes.h>
+ #include <drm/drm_print.h>
+
+--- a/drivers/gpu/drm/exynos/exynos_mixer.c
++++ b/drivers/gpu/drm/exynos/exynos_mixer.c
+@@ -25,6 +25,7 @@
+ #include <linux/spinlock.h>
+ #include <linux/wait.h>
+
++#include <drm/drm_edid.h>
+ #include <drm/drm_fourcc.h>
+ #include <drm/drm_vblank.h>
+ #include <drm/exynos_drm.h>
+--- a/drivers/gpu/drm/gma500/cdv_intel_dp.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c
+@@ -32,6 +32,7 @@
+ #include <drm/display/drm_dp_helper.h>
+ #include <drm/drm_crtc.h>
+ #include <drm/drm_crtc_helper.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_simple_kms_helper.h>
+
+ #include "gma_display.h"
+--- a/drivers/gpu/drm/gma500/oaktrail_hdmi.c
++++ b/drivers/gpu/drm/gma500/oaktrail_hdmi.c
+@@ -27,6 +27,7 @@
+ #include <linux/delay.h>
+
+ #include <drm/drm.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_simple_kms_helper.h>
+
+ #include "psb_drv.h"
+--- a/drivers/gpu/drm/gma500/oaktrail_lvds.c
++++ b/drivers/gpu/drm/gma500/oaktrail_lvds.c
+@@ -13,6 +13,7 @@
+
+ #include <asm/intel-mid.h>
+
++#include <drm/drm_edid.h>
+ #include <drm/drm_simple_kms_helper.h>
+
+ #include "intel_bios.h"
+--- a/drivers/gpu/drm/gma500/psb_intel_modes.c
++++ b/drivers/gpu/drm/gma500/psb_intel_modes.c
+@@ -7,6 +7,8 @@
+
+ #include <linux/i2c.h>
+
++#include <drm/drm_edid.h>
++
+ #include "psb_intel_drv.h"
+
+ /**
+--- a/drivers/gpu/drm/gud/gud_connector.c
++++ b/drivers/gpu/drm/gud/gud_connector.c
+@@ -10,6 +10,7 @@
+ #include <drm/drm_atomic_state_helper.h>
+ #include <drm/drm_connector.h>
+ #include <drm/drm_drv.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_encoder.h>
+ #include <drm/drm_file.h>
+ #include <drm/drm_modeset_helper_vtables.h>
+--- a/drivers/gpu/drm/i915/display/intel_bios.c
++++ b/drivers/gpu/drm/i915/display/intel_bios.c
+@@ -25,6 +25,7 @@
+ *
+ */
+
++#include <drm/drm_edid.h>
+ #include <drm/display/drm_dp_helper.h>
+ #include <drm/display/drm_dsc_helper.h>
+
+--- a/drivers/gpu/drm/i915/display/intel_dp.c
++++ b/drivers/gpu/drm/i915/display/intel_dp.c
+@@ -40,6 +40,7 @@
+ #include <drm/display/drm_hdmi_helper.h>
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_crtc.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_probe_helper.h>
+
+ #include "g4x_dp.h"
+--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
++++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
+@@ -26,6 +26,7 @@
+ #include <drm/display/drm_dp_dual_mode_helper.h>
+ #include <drm/display/drm_hdmi_helper.h>
+ #include <drm/drm_atomic_helper.h>
++#include <drm/drm_edid.h>
+
+ #include "intel_de.h"
+ #include "intel_display_types.h"
+--- a/drivers/gpu/drm/i915/display/intel_opregion.c
++++ b/drivers/gpu/drm/i915/display/intel_opregion.c
+@@ -30,6 +30,8 @@
+ #include <linux/firmware.h>
+ #include <acpi/video.h>
+
++#include <drm/drm_edid.h>
++
+ #include "i915_drv.h"
+ #include "intel_acpi.h"
+ #include "intel_backlight.h"
+--- a/drivers/gpu/drm/imx/imx-ldb.c
++++ b/drivers/gpu/drm/imx/imx-ldb.c
+@@ -21,6 +21,7 @@
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_bridge.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_managed.h>
+ #include <drm/drm_of.h>
+--- a/drivers/gpu/drm/imx/imx-tve.c
++++ b/drivers/gpu/drm/imx/imx-tve.c
+@@ -18,6 +18,7 @@
+ #include <video/imx-ipu-v3.h>
+
+ #include <drm/drm_atomic_helper.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_managed.h>
+ #include <drm/drm_probe_helper.h>
+--- a/drivers/gpu/drm/imx/parallel-display.c
++++ b/drivers/gpu/drm/imx/parallel-display.c
+@@ -14,6 +14,7 @@
+
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_bridge.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_managed.h>
+ #include <drm/drm_of.h>
+--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c
++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c
+@@ -3,6 +3,8 @@
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
++#include <drm/drm_edid.h>
++
+ #include "dpu_writeback.h"
+
+ static int dpu_wb_conn_get_modes(struct drm_connector *connector)
+--- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
++++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
+@@ -6,6 +6,7 @@
+
+ #include <linux/delay.h>
+ #include <drm/drm_bridge_connector.h>
++#include <drm/drm_edid.h>
+
+ #include "msm_kms.h"
+ #include "hdmi.h"
+--- a/drivers/gpu/drm/omapdrm/dss/hdmi4.c
++++ b/drivers/gpu/drm/omapdrm/dss/hdmi4.c
+@@ -29,6 +29,7 @@
+
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_state_helper.h>
++#include <drm/drm_edid.h>
+
+ #include "omapdss.h"
+ #include "hdmi4_core.h"
+--- a/drivers/gpu/drm/omapdrm/dss/hdmi5.c
++++ b/drivers/gpu/drm/omapdrm/dss/hdmi5.c
+@@ -32,6 +32,7 @@
+
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_state_helper.h>
++#include <drm/drm_edid.h>
+
+ #include "omapdss.h"
+ #include "hdmi5_core.h"
+--- a/drivers/gpu/drm/panel/panel-edp.c
++++ b/drivers/gpu/drm/panel/panel-edp.c
+@@ -39,6 +39,7 @@
+ #include <drm/display/drm_dp_helper.h>
+ #include <drm/drm_crtc.h>
+ #include <drm/drm_device.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_panel.h>
+
+ /**
+--- a/drivers/gpu/drm/panel/panel-simple.c
++++ b/drivers/gpu/drm/panel/panel-simple.c
+@@ -35,6 +35,7 @@
+
+ #include <drm/drm_crtc.h>
+ #include <drm/drm_device.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_mipi_dsi.h>
+ #include <drm/drm_panel.h>
+
+--- a/drivers/gpu/drm/qxl/qxl_display.c
++++ b/drivers/gpu/drm/qxl/qxl_display.c
+@@ -30,6 +30,7 @@
+ #include <drm/drm_drv.h>
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_gem_framebuffer_helper.h>
+ #include <drm/drm_plane_helper.h>
+ #include <drm/drm_probe_helper.h>
+--- a/drivers/gpu/drm/rcar-du/rcar_du_writeback.c
++++ b/drivers/gpu/drm/rcar-du/rcar_du_writeback.c
+@@ -7,6 +7,7 @@
+
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_device.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_fourcc.h>
+ #include <drm/drm_probe_helper.h>
+ #include <drm/drm_writeback.h>
+--- a/drivers/gpu/drm/rockchip/rk3066_hdmi.c
++++ b/drivers/gpu/drm/rockchip/rk3066_hdmi.c
+@@ -4,6 +4,7 @@
+ * Zheng Yang <zhengyang@rock-chips.com>
+ */
+
++#include <drm/drm_edid.h>
+ #include <drm/drm_of.h>
+ #include <drm/drm_probe_helper.h>
+ #include <drm/drm_simple_kms_helper.h>
+--- a/drivers/gpu/drm/solomon/ssd130x.c
++++ b/drivers/gpu/drm/solomon/ssd130x.c
+@@ -20,6 +20,7 @@
+
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_damage_helper.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_fb_cma_helper.h>
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_format_helper.h>
+--- a/drivers/gpu/drm/stm/ltdc.c
++++ b/drivers/gpu/drm/stm/ltdc.c
+@@ -25,6 +25,7 @@
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_bridge.h>
+ #include <drm/drm_device.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_fb_cma_helper.h>
+ #include <drm/drm_fourcc.h>
+ #include <drm/drm_gem_atomic_helper.h>
+--- a/drivers/gpu/drm/tiny/arcpgu.c
++++ b/drivers/gpu/drm/tiny/arcpgu.c
+@@ -10,6 +10,7 @@
+ #include <drm/drm_debugfs.h>
+ #include <drm/drm_device.h>
+ #include <drm/drm_drv.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_fb_cma_helper.h>
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_fourcc.h>
+--- a/drivers/gpu/drm/tiny/bochs.c
++++ b/drivers/gpu/drm/tiny/bochs.c
+@@ -5,6 +5,7 @@
+ #include <drm/drm_aperture.h>
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_drv.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_fourcc.h>
+ #include <drm/drm_gem_framebuffer_helper.h>
+--- a/drivers/gpu/drm/tiny/cirrus.c
++++ b/drivers/gpu/drm/tiny/cirrus.c
+@@ -29,6 +29,7 @@
+ #include <drm/drm_connector.h>
+ #include <drm/drm_damage_helper.h>
+ #include <drm/drm_drv.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_file.h>
+ #include <drm/drm_format_helper.h>
+--- a/drivers/gpu/drm/tiny/gm12u320.c
++++ b/drivers/gpu/drm/tiny/gm12u320.c
+@@ -11,6 +11,7 @@
+ #include <drm/drm_connector.h>
+ #include <drm/drm_damage_helper.h>
+ #include <drm/drm_drv.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_file.h>
+ #include <drm/drm_format_helper.h>
+--- a/drivers/gpu/drm/udl/udl_connector.c
++++ b/drivers/gpu/drm/udl/udl_connector.c
+@@ -8,6 +8,7 @@
+ */
+
+ #include <drm/drm_atomic_state_helper.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_crtc_helper.h>
+ #include <drm/drm_probe_helper.h>
+
+--- a/drivers/gpu/drm/vboxvideo/vbox_mode.c
++++ b/drivers/gpu/drm/vboxvideo/vbox_mode.c
+@@ -15,6 +15,7 @@
+
+ #include <drm/drm_atomic.h>
+ #include <drm/drm_atomic_helper.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_fourcc.h>
+ #include <drm/drm_gem_atomic_helper.h>
+--- a/drivers/gpu/drm/virtio/virtgpu_display.c
++++ b/drivers/gpu/drm/virtio/virtgpu_display.c
+@@ -27,6 +27,7 @@
+
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_damage_helper.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_fourcc.h>
+ #include <drm/drm_gem_framebuffer_helper.h>
+ #include <drm/drm_probe_helper.h>
+--- a/drivers/gpu/drm/virtio/virtgpu_vq.c
++++ b/drivers/gpu/drm/virtio/virtgpu_vq.c
+@@ -31,6 +31,8 @@
+ #include <linux/virtio_config.h>
+ #include <linux/virtio_ring.h>
+
++#include <drm/drm_edid.h>
++
+ #include "virtgpu_drv.h"
+ #include "virtgpu_trace.h"
+
+--- a/drivers/gpu/drm/vkms/vkms_output.c
++++ b/drivers/gpu/drm/vkms/vkms_output.c
+@@ -2,6 +2,7 @@
+
+ #include "vkms_drv.h"
+ #include <drm/drm_atomic_helper.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_probe_helper.h>
+ #include <drm/drm_simple_kms_helper.h>
+
+--- a/drivers/gpu/drm/vkms/vkms_writeback.c
++++ b/drivers/gpu/drm/vkms/vkms_writeback.c
+@@ -3,6 +3,7 @@
+ #include <linux/iosys-map.h>
+
+ #include <drm/drm_atomic.h>
++#include <drm/drm_edid.h>
+ #include <drm/drm_fourcc.h>
+ #include <drm/drm_writeback.h>
+ #include <drm/drm_probe_helper.h>
+--- a/include/drm/drm_crtc.h
++++ b/include/drm/drm_crtc.h
+@@ -41,7 +41,6 @@
+ #include <drm/drm_connector.h>
+ #include <drm/drm_device.h>
+ #include <drm/drm_property.h>
+-#include <drm/drm_edid.h>
+ #include <drm/drm_plane.h>
+ #include <drm/drm_blend.h>
+ #include <drm/drm_color_mgmt.h>
diff --git a/target/linux/rockchip/patches-5.19/0039-drm-rockchip-vop-Don-t-crash-for-invalid-duplicate_s.patch b/target/linux/rockchip/patches-5.19/0039-drm-rockchip-vop-Don-t-crash-for-invalid-duplicate_s.patch
new file mode 100644
index 00000000000000..4bc1c5b6cf928d
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0039-drm-rockchip-vop-Don-t-crash-for-invalid-duplicate_s.patch
@@ -0,0 +1,33 @@
+From efaa0a55ce429107697f641921336cc51518693a Mon Sep 17 00:00:00 2001
+From: Brian Norris <briannorris@chromium.org>
+Date: Fri, 17 Jun 2022 17:26:52 -0700
+Subject: [PATCH 39/51] drm/rockchip: vop: Don't crash for invalid
+ duplicate_state()
+
+It's possible for users to try to duplicate the CRTC state even when the
+state doesn't exist. drm_atomic_helper_crtc_duplicate_state() (and other
+users of __drm_atomic_helper_crtc_duplicate_state()) already guard this
+with a WARN_ON() instead of crashing, so let's do that here too.
+
+Fixes: 4e257d9eee23 ("drm/rockchip: get rid of rockchip_drm_crtc_mode_config")
+Signed-off-by: Brian Norris <briannorris@chromium.org>
+Reviewed-by: Sean Paul <seanpaul@chromium.org>
+Reviewed-by: Douglas Anderson <dianders@chromium.org>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://patchwork.freedesktop.org/patch/msgid/20220617172623.1.I62db228170b1559ada60b8d3e1637e1688424926@changeid
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -1570,6 +1570,9 @@ static struct drm_crtc_state *vop_crtc_d
+ {
+ struct rockchip_crtc_state *rockchip_state;
+
++ if (WARN_ON(!crtc->state))
++ return NULL;
++
+ rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
+ if (!rockchip_state)
+ return NULL;
diff --git a/target/linux/rockchip/patches-5.19/0040-drm-rockchip-Fix-an-error-handling-path-rockchip_dp_.patch b/target/linux/rockchip/patches-5.19/0040-drm-rockchip-Fix-an-error-handling-path-rockchip_dp_.patch
new file mode 100644
index 00000000000000..9843250604df75
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0040-drm-rockchip-Fix-an-error-handling-path-rockchip_dp_.patch
@@ -0,0 +1,36 @@
+From 189fcc50d8531f4904a96aac754fd61c26c4dd3c Mon Sep 17 00:00:00 2001
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Date: Sat, 18 Jun 2022 19:08:05 +0200
+Subject: [PATCH 40/51] drm/rockchip: Fix an error handling path
+ rockchip_dp_probe()
+
+Should component_add() fail, we should call analogix_dp_remove() in the
+error handling path, as already done in the remove function.
+
+Fixes: 152cce0006ab ("drm/bridge: analogix_dp: Split bind() into probe() and real bind()")
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://patchwork.freedesktop.org/patch/msgid/b719d9061bb97eb85145fbd3c5e63f4549f2e13e.1655572071.git.christophe.jaillet@wanadoo.fr
+---
+ drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
++++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+@@ -408,7 +408,15 @@ static int rockchip_dp_probe(struct plat
+ if (IS_ERR(dp->adp))
+ return PTR_ERR(dp->adp);
+
+- return component_add(dev, &rockchip_dp_component_ops);
++ ret = component_add(dev, &rockchip_dp_component_ops);
++ if (ret)
++ goto err_dp_remove;
++
++ return 0;
++
++err_dp_remove:
++ analogix_dp_remove(dp->adp);
++ return ret;
+ }
+
+ static int rockchip_dp_remove(struct platform_device *pdev)
diff --git a/target/linux/rockchip/patches-5.19/0042-phy-rockchip-inno-usb2-Prevent-incorrect-error-on-pr.patch b/target/linux/rockchip/patches-5.19/0042-phy-rockchip-inno-usb2-Prevent-incorrect-error-on-pr.patch
new file mode 100644
index 00000000000000..09ce9f00a16603
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0042-phy-rockchip-inno-usb2-Prevent-incorrect-error-on-pr.patch
@@ -0,0 +1,28 @@
+From cc4992ccf916a3040c349d51ad40f2a2dd2e4e0c Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Sat, 25 Jun 2022 17:27:11 -0400
+Subject: [PATCH 42/51] phy: rockchip-inno-usb2: Prevent incorrect error on
+ probe
+
+If a phy supply is designated but isn't available at probe time, an
+EPROBE_DEFER is returned. Use dev_err_probe to prevent this from
+incorrectly printing during boot.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+Link: https://lore.kernel.org/r/20220625212711.558495-1-pgwipeout@gmail.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -1283,7 +1283,7 @@ static int rockchip_usb2phy_probe(struct
+
+ phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
+ if (IS_ERR(phy)) {
+- dev_err(dev, "failed to create phy\n");
++ dev_err_probe(dev, PTR_ERR(phy), "failed to create phy\n");
+ ret = PTR_ERR(phy);
+ goto put_child;
+ }
diff --git a/target/linux/rockchip/patches-5.19/0043-phy-rockchip-inno-usb2-Sync-initial-otg-state.patch b/target/linux/rockchip/patches-5.19/0043-phy-rockchip-inno-usb2-Sync-initial-otg-state.patch
new file mode 100644
index 00000000000000..2435844a0a3e88
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0043-phy-rockchip-inno-usb2-Sync-initial-otg-state.patch
@@ -0,0 +1,33 @@
+From c65316cf05c7597c0d8dc23373b840aafd34ffb8 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Tue, 21 Jun 2022 20:31:40 -0400
+Subject: [PATCH 43/51] phy: rockchip-inno-usb2: Sync initial otg state
+
+The initial otg state for the phy defaults to device mode. The actual
+state isn't detected until an ID IRQ fires. Fix this by syncing the ID
+state during initialization.
+
+Fixes: 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ")
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+Reviewed-by: Samuel Holland <samuel@sholland.org>
+Link: https://lore.kernel.org/r/20220622003140.30365-1-pgwipeout@gmail.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -1162,6 +1162,12 @@ static int rockchip_usb2phy_otg_port_ini
+ EXTCON_USB_HOST, &rport->event_nb);
+ if (ret)
+ dev_err(rphy->dev, "register USB HOST notifier failed\n");
++
++ if (!of_property_read_bool(rphy->dev->of_node, "extcon")) {
++ /* do initial sync of usb state */
++ ret = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
++ extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !ret);
++ }
+ }
+
+ out:
diff --git a/target/linux/rockchip/patches-5.19/0044-dt-bindings-phy-rockchip-add-PCIe-v3-phy.patch b/target/linux/rockchip/patches-5.19/0044-dt-bindings-phy-rockchip-add-PCIe-v3-phy.patch
new file mode 100644
index 00000000000000..39daf9fd85ec60
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0044-dt-bindings-phy-rockchip-add-PCIe-v3-phy.patch
@@ -0,0 +1,97 @@
+From dd3c111b13d57d95d69c345897460ef65a6aaefd Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Sun, 19 Jun 2022 10:26:01 +0200
+Subject: [PATCH 44/51] dt-bindings: phy: rockchip: add PCIe v3 phy
+
+Add a new binding file for Rockchip PCIe v3 phy driver.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+---
+ .../bindings/phy/rockchip,pcie3-phy.yaml | 80 +++++++++++++++++++
+ 1 file changed, 80 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
+@@ -0,0 +1,80 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip PCIe v3 phy
++
++maintainers:
++ - Heiko Stuebner <heiko@sntech.de>
++
++properties:
++ compatible:
++ enum:
++ - rockchip,rk3568-pcie3-phy
++
++ reg:
++ maxItems: 1
++
++ clocks:
++ minItems: 3
++ maxItems: 3
++
++ clock-names:
++ items:
++ - const: refclk_m
++ - const: refclk_n
++ - const: pclk
++
++ data-lanes:
++ description: which lanes (by position) should be mapped to which
++ controller (value). 0 means lane disabled, higher value means used.
++ (controller-number +1 )
++ $ref: /schemas/types.yaml#/definitions/uint32-array
++ minItems: 2
++ maxItems: 16
++ items:
++ minimum: 0
++ maximum: 16
++
++ "#phy-cells":
++ const: 0
++
++ resets:
++ maxItems: 1
++
++ reset-names:
++ const: phy
++
++ rockchip,phy-grf:
++ $ref: /schemas/types.yaml#/definitions/phandle
++ description: phandle to the syscon managing the phy "general register files"
++
++ rockchip,pipe-grf:
++ $ref: /schemas/types.yaml#/definitions/phandle
++ description: phandle to the syscon managing the pipe "general register files"
++
++required:
++ - compatible
++ - reg
++ - rockchip,phy-grf
++ - "#phy-cells"
++
++additionalProperties: false
++
++examples:
++ - |
++ #include <dt-bindings/clock/rk3568-cru.h>
++ pcie30phy: phy@fe8c0000 {
++ compatible = "rockchip,rk3568-pcie3-phy";
++ reg = <0xfe8c0000 0x20000>;
++ #phy-cells = <0>;
++ clocks = <&pmucru CLK_PCIE30PHY_REF_M>,
++ <&pmucru CLK_PCIE30PHY_REF_N>,
++ <&cru PCLK_PCIE30PHY>;
++ clock-names = "refclk_m", "refclk_n", "pclk";
++ resets = <&cru SRST_PCIE30PHY>;
++ reset-names = "phy";
++ rockchip,phy-grf = <&pcie30_phy_grf>;
++ };
diff --git a/target/linux/rockchip/patches-5.19/0045-dt-bindings-soc-grf-add-pcie30-phy-pipe-grf.patch b/target/linux/rockchip/patches-5.19/0045-dt-bindings-soc-grf-add-pcie30-phy-pipe-grf.patch
new file mode 100644
index 00000000000000..d1980cd6734191
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0045-dt-bindings-soc-grf-add-pcie30-phy-pipe-grf.patch
@@ -0,0 +1,28 @@
+From 566b57d307a104490a476a74866b507682443da6 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Sun, 19 Jun 2022 10:26:02 +0200
+Subject: [PATCH 45/51] dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf
+
+Add compatibles for PCIe v3 General Register Files.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+---
+ Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
++++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+@@ -16,9 +16,12 @@ properties:
+ - enum:
+ - rockchip,rk3288-sgrf
+ - rockchip,rk3566-pipe-grf
++ - rockchip,rk3568-pcie3-phy-grf
+ - rockchip,rk3568-pipe-grf
+ - rockchip,rk3568-pipe-phy-grf
+ - rockchip,rk3568-usb2phy-grf
++ - rockchip,rk3588-pcie3-phy-grf
++ - rockchip,rk3588-pcie3-pipe-grf
+ - rockchip,rv1108-usbgrf
+ - const: syscon
+ - items:
diff --git a/target/linux/rockchip/patches-5.19/0046-phy-rockchip-Support-PCIe-v3.patch b/target/linux/rockchip/patches-5.19/0046-phy-rockchip-Support-PCIe-v3.patch
new file mode 100644
index 00000000000000..d774aaa1045807
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0046-phy-rockchip-Support-PCIe-v3.patch
@@ -0,0 +1,390 @@
+From 46207bac2522eab8dd18f4ecd18c2597c841534e Mon Sep 17 00:00:00 2001
+From: Shawn Lin <shawn.lin@rock-chips.com>
+Date: Sun, 19 Jun 2022 10:26:03 +0200
+Subject: [PATCH 46/51] phy: rockchip: Support PCIe v3
+
+RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566.
+It use a dedicated PCIe-phy. Add support for this.
+
+Initial support by Shawn Lin, modifications by Peter Geis and Frank
+Wunderlich.
+
+Add data-lanes property for splitting pcie-lanes across controllers.
+
+The data-lanes is an array where x=0 means lane is disabled and x > 0
+means controller x is assigned to phy lane.
+
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Suggested-by: Peter Geis <pgwipeout@gmail.com>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+---
+ drivers/phy/rockchip/Kconfig | 9 +
+ drivers/phy/rockchip/Makefile | 1 +
+ .../phy/rockchip/phy-rockchip-snps-pcie3.c | 317 ++++++++++++++++++
+ include/linux/phy/pcie.h | 12 +
+ 4 files changed, 339 insertions(+)
+ create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+ create mode 100644 include/linux/phy/pcie.h
+
+--- a/drivers/phy/rockchip/Kconfig
++++ b/drivers/phy/rockchip/Kconfig
+@@ -83,6 +83,15 @@ config PHY_ROCKCHIP_PCIE
+ help
+ Enable this to support the Rockchip PCIe PHY.
+
++config PHY_ROCKCHIP_SNPS_PCIE3
++ tristate "Rockchip Snps PCIe3 PHY Driver"
++ depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
++ depends on HAS_IOMEM
++ select GENERIC_PHY
++ select MFD_SYSCON
++ help
++ Enable this to support the Rockchip snps PCIe3 PHY.
++
+ config PHY_ROCKCHIP_TYPEC
+ tristate "Rockchip TYPEC PHY Driver"
+ depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST)
+--- a/drivers/phy/rockchip/Makefile
++++ b/drivers/phy/rockchip/Makefile
+@@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) +=
+ obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
+ obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o
+ obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
++obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
+ obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
+ obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
+--- /dev/null
++++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+@@ -0,0 +1,317 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Rockchip PCIE3.0 phy driver
++ *
++ * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/mfd/syscon.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/phy/pcie.h>
++#include <linux/phy/phy.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++
++/* Register for RK3568 */
++#define GRF_PCIE30PHY_CON1 0x4
++#define GRF_PCIE30PHY_CON6 0x18
++#define GRF_PCIE30PHY_CON9 0x24
++#define GRF_PCIE30PHY_STATUS0 0x80
++#define SRAM_INIT_DONE(reg) (reg & BIT(14))
++
++#define RK3568_BIFURCATION_LANE_0_1 BIT(0)
++
++/* Register for RK3588 */
++#define PHP_GRF_PCIESEL_CON 0x100
++#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
++#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
++#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
++#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
++
++#define RK3588_BIFURCATION_LANE_0_1 BIT(0)
++#define RK3588_BIFURCATION_LANE_2_3 BIT(1)
++#define RK3588_LANE_AGGREGATION BIT(2)
++
++struct rockchip_p3phy_ops;
++
++struct rockchip_p3phy_priv {
++ const struct rockchip_p3phy_ops *ops;
++ void __iomem *mmio;
++ /* mode: RC, EP */
++ int mode;
++ /* pcie30_phymode: Aggregation, Bifurcation */
++ int pcie30_phymode;
++ struct regmap *phy_grf;
++ struct regmap *pipe_grf;
++ struct reset_control *p30phy;
++ struct phy *phy;
++ struct clk_bulk_data *clks;
++ int num_clks;
++ int num_lanes;
++ u32 lanes[4];
++};
++
++struct rockchip_p3phy_ops {
++ int (*phy_init)(struct rockchip_p3phy_priv *priv);
++};
++
++static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
++{
++ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
++
++ /* Actually We don't care EP/RC mode, but just record it */
++ switch (submode) {
++ case PHY_MODE_PCIE_RC:
++ priv->mode = PHY_MODE_PCIE_RC;
++ break;
++ case PHY_MODE_PCIE_EP:
++ priv->mode = PHY_MODE_PCIE_EP;
++ break;
++ default:
++ dev_err(&phy->dev, "%s, invalid mode\n", __func__);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
++{
++ struct phy *phy = priv->phy;
++ bool bifurcation = false;
++ int ret;
++ u32 reg;
++
++ /* Deassert PCIe PMA output clamp mode */
++ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, BIT(15) | BIT(31));
++
++ for (int i = 0; i < priv->num_lanes; i++) {
++ dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]);
++ if (priv->lanes[i] > 1)
++ bifurcation = true;
++ }
++
++ /* Set bifurcation if needed, and it doesn't care RC/EP */
++ if (bifurcation) {
++ dev_info(&phy->dev, "bifurcation enabled\n");
++ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
++ (0xf << 16) | RK3568_BIFURCATION_LANE_0_1);
++ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,
++ BIT(15) | BIT(31));
++ } else {
++ dev_info(&phy->dev, "bifurcation disabled\n");
++ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
++ (0xf << 16) & ~RK3568_BIFURCATION_LANE_0_1);
++ }
++
++ reset_control_deassert(priv->p30phy);
++
++ ret = regmap_read_poll_timeout(priv->phy_grf,
++ GRF_PCIE30PHY_STATUS0,
++ reg, SRAM_INIT_DONE(reg),
++ 0, 500);
++ if (ret)
++ dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n",
++ __func__, reg);
++ return ret;
++}
++
++static const struct rockchip_p3phy_ops rk3568_ops = {
++ .phy_init = rockchip_p3phy_rk3568_init,
++};
++
++static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
++{
++ u32 reg = 0;
++ u8 mode = 0;
++ int ret;
++
++ /* Deassert PCIe PMA output clamp mode */
++ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24));
++
++ /* Set bifurcation if needed */
++ for (int i = 0; i < priv->num_lanes; i++) {
++ if (!priv->lanes[i])
++ mode |= (BIT(i) << 3);
++
++ if (priv->lanes[i] > 1)
++ mode |= (BIT(i) >> 1);
++ }
++
++ if (!mode)
++ reg = RK3588_LANE_AGGREGATION;
++ else {
++ if (mode & (BIT(0) | BIT(1)))
++ reg |= RK3588_BIFURCATION_LANE_0_1;
++
++ if (mode & (BIT(2) | BIT(3)))
++ reg |= RK3588_BIFURCATION_LANE_2_3;
++ }
++
++ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg);
++
++ /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
++ if (!IS_ERR(priv->pipe_grf)) {
++ reg = (mode & (BIT(6) | BIT(7))) >> 6;
++ if (reg)
++ regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
++ (reg << 16) | reg);
++ }
++
++ reset_control_deassert(priv->p30phy);
++
++ ret = regmap_read_poll_timeout(priv->phy_grf,
++ RK3588_PCIE3PHY_GRF_PHY0_STATUS1,
++ reg, RK3588_SRAM_INIT_DONE(reg),
++ 0, 500);
++ ret |= regmap_read_poll_timeout(priv->phy_grf,
++ RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
++ reg, RK3588_SRAM_INIT_DONE(reg),
++ 0, 500);
++ if (ret)
++ pr_err("%s: lock failed 0x%x, check input refclk and power supply\n",
++ __func__, reg);
++ return ret;
++}
++
++static const struct rockchip_p3phy_ops rk3588_ops = {
++ .phy_init = rockchip_p3phy_rk3588_init,
++};
++
++static int rochchip_p3phy_init(struct phy *phy)
++{
++ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
++ int ret;
++
++ ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
++ if (ret) {
++ pr_err("failed to enable PCIe bulk clks %d\n", ret);
++ return ret;
++ }
++
++ reset_control_assert(priv->p30phy);
++ udelay(1);
++
++ if (priv->ops->phy_init) {
++ ret = priv->ops->phy_init(priv);
++ if (ret)
++ clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
++ }
++
++ return ret;
++}
++
++static int rochchip_p3phy_exit(struct phy *phy)
++{
++ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
++
++ clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
++ reset_control_assert(priv->p30phy);
++ return 0;
++}
++
++static const struct phy_ops rochchip_p3phy_ops = {
++ .init = rochchip_p3phy_init,
++ .exit = rochchip_p3phy_exit,
++ .set_mode = rockchip_p3phy_set_mode,
++ .owner = THIS_MODULE,
++};
++
++static int rockchip_p3phy_probe(struct platform_device *pdev)
++{
++ struct phy_provider *phy_provider;
++ struct device *dev = &pdev->dev;
++ struct rockchip_p3phy_priv *priv;
++ struct device_node *np = dev->of_node;
++ struct resource *res;
++ int ret;
++
++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ priv->mmio = devm_ioremap_resource(dev, res);
++ if (IS_ERR(priv->mmio)) {
++ ret = PTR_ERR(priv->mmio);
++ return ret;
++ }
++
++ priv->ops = of_device_get_match_data(&pdev->dev);
++ if (!priv->ops) {
++ dev_err(&pdev->dev, "no of match data provided\n");
++ return -EINVAL;
++ }
++
++ priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf");
++ if (IS_ERR(priv->phy_grf)) {
++ dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
++ return PTR_ERR(priv->phy_grf);
++ }
++
++ priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
++ "rockchip,pipe-grf");
++ if (IS_ERR(priv->pipe_grf))
++ dev_info(dev, "failed to find rockchip,pipe_grf regmap\n");
++
++ priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes",
++ priv->lanes, 2,
++ ARRAY_SIZE(priv->lanes));
++
++ /* if no data-lanes assume aggregation */
++ if (priv->num_lanes == -EINVAL) {
++ dev_dbg(dev, "no data-lanes property found\n");
++ priv->num_lanes = 1;
++ priv->lanes[0] = 1;
++ } else if (priv->num_lanes < 0) {
++ dev_err(dev, "failed to read data-lanes property %d\n", priv->num_lanes);
++ return priv->num_lanes;
++ }
++
++ priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops);
++ if (IS_ERR(priv->phy)) {
++ dev_err(dev, "failed to create combphy\n");
++ return PTR_ERR(priv->phy);
++ }
++
++ priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy");
++ if (IS_ERR(priv->p30phy)) {
++ return dev_err_probe(dev, PTR_ERR(priv->p30phy),
++ "failed to get phy reset control\n");
++ }
++ if (!priv->p30phy)
++ dev_info(dev, "no phy reset control specified\n");
++
++ priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
++ if (priv->num_clks < 1)
++ return -ENODEV;
++
++ dev_set_drvdata(dev, priv);
++ phy_set_drvdata(priv->phy, priv);
++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++ return PTR_ERR_OR_ZERO(phy_provider);
++}
++
++static const struct of_device_id rockchip_p3phy_of_match[] = {
++ { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops },
++ { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops },
++ { },
++};
++MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match);
++
++static struct platform_driver rockchip_p3phy_driver = {
++ .probe = rockchip_p3phy_probe,
++ .driver = {
++ .name = "rockchip-snps-pcie3-phy",
++ .of_match_table = rockchip_p3phy_of_match,
++ },
++};
++module_platform_driver(rockchip_p3phy_driver);
++MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver");
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/include/linux/phy/pcie.h
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
++ */
++#ifndef __PHY_PCIE_H
++#define __PHY_PCIE_H
++
++#define PHY_MODE_PCIE_RC 20
++#define PHY_MODE_PCIE_EP 21
++#define PHY_MODE_PCIE_BIFURCATION 22
++
++#endif
diff --git a/target/linux/rockchip/patches-5.19/0047-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch b/target/linux/rockchip/patches-5.19/0047-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch
new file mode 100644
index 00000000000000..be8b38690eebc2
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0047-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch
@@ -0,0 +1,144 @@
+From a465b1f69305f3ce3f46e642412c0f6dcb13a618 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Sun, 19 Jun 2022 10:26:04 +0200
+Subject: [PATCH 47/51] arm64: dts: rockchip: rk3568: Add PCIe v3 nodes
+
+Add nodes to rk356x devicetree to support PCIe v3.
+
+Co-developed-by: Peter Geis <pgwipeout@gmail.com>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++++++++++++++++++
+ 1 file changed, 122 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+@@ -42,6 +42,128 @@
+ reg = <0x0 0xfe190200 0x0 0x20>;
+ };
+
++ pcie30_phy_grf: syscon@fdcb8000 {
++ compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
++ reg = <0x0 0xfdcb8000 0x0 0x10000>;
++ };
++
++ pcie30phy: phy@fe8c0000 {
++ compatible = "rockchip,rk3568-pcie3-phy";
++ reg = <0x0 0xfe8c0000 0x0 0x20000>;
++ #phy-cells = <0>;
++ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
++ <&cru PCLK_PCIE30PHY>;
++ clock-names = "refclk_m", "refclk_n", "pclk";
++ resets = <&cru SRST_PCIE30PHY>;
++ reset-names = "phy";
++ rockchip,phy-grf = <&pcie30_phy_grf>;
++ status = "disabled";
++ };
++
++ pcie3x1: pcie@fe270000 {
++ compatible = "rockchip,rk3568-pcie";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ bus-range = <0x0 0xf>;
++ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
++ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
++ <&cru CLK_PCIE30X1_AUX_NDFT>;
++ clock-names = "aclk_mst", "aclk_slv",
++ "aclk_dbi", "pclk", "aux";
++ device_type = "pci";
++ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
++ <0 0 0 2 &pcie3x1_intc 1>,
++ <0 0 0 3 &pcie3x1_intc 2>,
++ <0 0 0 4 &pcie3x1_intc 3>;
++ linux,pci-domain = <1>;
++ num-ib-windows = <6>;
++ num-ob-windows = <2>;
++ max-link-speed = <3>;
++ msi-map = <0x0 &gic 0x1000 0x1000>;
++ num-lanes = <1>;
++ phys = <&pcie30phy>;
++ phy-names = "pcie-phy";
++ power-domains = <&power RK3568_PD_PIPE>;
++ reg = <0x3 0xc0400000 0x0 0x00400000>,
++ <0x0 0xfe270000 0x0 0x00010000>,
++ <0x3 0x7f000000 0x0 0x01000000>;
++ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
++ <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
++ reg-names = "dbi", "apb", "config";
++ resets = <&cru SRST_PCIE30X1_POWERUP>;
++ reset-names = "pipe";
++ /* bifurcation; lane1 when using 1+1 */
++ status = "disabled";
++
++ pcie3x1_intc: legacy-interrupt-controller {
++ interrupt-controller;
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
++ };
++ };
++
++ pcie3x2: pcie@fe280000 {
++ compatible = "rockchip,rk3568-pcie";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ bus-range = <0x0 0xf>;
++ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
++ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
++ <&cru CLK_PCIE30X2_AUX_NDFT>;
++ clock-names = "aclk_mst", "aclk_slv",
++ "aclk_dbi", "pclk", "aux";
++ device_type = "pci";
++ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
++ <0 0 0 2 &pcie3x2_intc 1>,
++ <0 0 0 3 &pcie3x2_intc 2>,
++ <0 0 0 4 &pcie3x2_intc 3>;
++ linux,pci-domain = <2>;
++ num-ib-windows = <6>;
++ num-ob-windows = <2>;
++ max-link-speed = <3>;
++ msi-map = <0x0 &gic 0x2000 0x1000>;
++ num-lanes = <2>;
++ phys = <&pcie30phy>;
++ phy-names = "pcie-phy";
++ power-domains = <&power RK3568_PD_PIPE>;
++ reg = <0x3 0xc0800000 0x0 0x00400000>,
++ <0x0 0xfe280000 0x0 0x00010000>,
++ <0x3 0xbf000000 0x0 0x01000000>;
++ ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
++ <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
++ reg-names = "dbi", "apb", "config";
++ resets = <&cru SRST_PCIE30X2_POWERUP>;
++ reset-names = "pipe";
++ /* bifurcation; lane0 when using 1+1 */
++ status = "disabled";
++
++ pcie3x2_intc: legacy-interrupt-controller {
++ interrupt-controller;
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
++ };
++ };
++
+ gmac0: ethernet@fe2a0000 {
+ compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0xfe2a0000 0x0 0x10000>;
diff --git a/target/linux/rockchip/patches-5.19/0048-arm64-dts-rockchip-Add-PCIe-v3-nodes-to-BPI-R2-Pro.patch b/target/linux/rockchip/patches-5.19/0048-arm64-dts-rockchip-Add-PCIe-v3-nodes-to-BPI-R2-Pro.patch
new file mode 100644
index 00000000000000..bc1e26bd379f09
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0048-arm64-dts-rockchip-Add-PCIe-v3-nodes-to-BPI-R2-Pro.patch
@@ -0,0 +1,127 @@
+From fa0c39b4564ea4cdbda88dc701b51ce615a11342 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Sun, 19 Jun 2022 10:26:05 +0200
+Subject: [PATCH 48/51] arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro
+
+Add Nodes to Bananapi-R2-Pro board to support PCIe v3 and
+set PCIe related regulators to always on.
+
+Suggested-by: Peter Geis <pgwipeout@gmail.com>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+---
+ .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 90 +++++++++++++++++++
+ 1 file changed, 90 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -86,6 +86,62 @@
+ vin-supply = <&dc_12v>;
+ };
+
++ pcie30_avdd0v9: pcie30-avdd0v9 {
++ compatible = "regulator-fixed";
++ regulator-name = "pcie30_avdd0v9";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <900000>;
++ vin-supply = <&vcc3v3_sys>;
++ };
++
++ pcie30_avdd1v8: pcie30-avdd1v8 {
++ compatible = "regulator-fixed";
++ regulator-name = "pcie30_avdd1v8";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ vin-supply = <&vcc3v3_sys>;
++ };
++
++ /* pi6c pcie clock generator feeds both ports */
++ vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v3_pcie";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ enable-active-high;
++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
++ startup-delay-us = <200000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
++ vcc3v3_minipcie: vcc3v3-minipcie-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v3_minipcie";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ enable-active-high;
++ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
++ startup-delay-us = <50000>;
++ vin-supply = <&vcc3v3_pi6c_05>;
++ };
++
++ /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
++ vcc3v3_ngff: vcc3v3-ngff-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v3_ngff";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ enable-active-high;
++ gpio = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>;
++ startup-delay-us = <50000>;
++ vin-supply = <&vcc3v3_pi6c_05>;
++ };
++
+ vcc5v0_usb: vcc5v0_usb {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+@@ -513,6 +569,27 @@
+ };
+ };
+
++&pcie30phy {
++ data-lanes = <1 2>;
++ status = "okay";
++};
++
++&pcie3x1 {
++ /* M.2 slot */
++ num-lanes = <1>;
++ reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_ngff>;
++ status = "okay";
++};
++
++&pcie3x2 {
++ /* mPCIe slot */
++ num-lanes = <1>;
++ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_minipcie>;
++ status = "okay";
++};
++
+ &pinctrl {
+ leds {
+ blue_led_pin: blue-led-pin {
+@@ -708,6 +785,19 @@
+ status = "okay";
+ };
+
++&usb2phy1 {
++ /* USB for PCIe/M2 */
++ status = "okay";
++};
++
++&usb2phy1_host {
++ status = "okay";
++};
++
++&usb2phy1_otg {
++ status = "okay";
++};
++
+ &vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
diff --git a/target/linux/rockchip/patches-5.19/0049-phy-rockchip-inno-usb2-Ignore-OTG-IRQs-in-host-mode.patch b/target/linux/rockchip/patches-5.19/0049-phy-rockchip-inno-usb2-Ignore-OTG-IRQs-in-host-mode.patch
new file mode 100644
index 00000000000000..575a59b6ffe8ef
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0049-phy-rockchip-inno-usb2-Ignore-OTG-IRQs-in-host-mode.patch
@@ -0,0 +1,34 @@
+From 3ddee7849f0ab4b4edcc812c6569236b53796640 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 8 Jul 2022 01:14:34 -0500
+Subject: [PATCH 49/51] phy: rockchip-inno-usb2: Ignore OTG IRQs in host mode
+
+When the OTG port is fixed to host mode, the driver does not request its
+IRQs, nor does it enable those IRQs in hardware. Similarly, the driver
+should ignore the OTG port IRQs when handling the shared interrupt.
+
+Otherwise, it would update the extcon based on an ID pin which may be in
+an undefined state, or try to queue a uninitialized work item.
+
+Fixes: 6a98df08ccd5 ("phy: rockchip-inno-usb2: Fix muxed interrupt support")
+Reported-by: Frank Wunderlich <frank-w@public-files.de>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Tested-by: Frank Wunderlich <frank-w@public-files.de>
+Tested-by: Peter Geis <pgwipeout@gmail.com>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -978,7 +978,9 @@ static irqreturn_t rockchip_usb2phy_irq(
+
+ switch (rport->port_id) {
+ case USB2PHY_PORT_OTG:
+- ret |= rockchip_usb2phy_otg_mux_irq(irq, rport);
++ if (rport->mode != USB_DR_MODE_HOST &&
++ rport->mode != USB_DR_MODE_UNKNOWN)
++ ret |= rockchip_usb2phy_otg_mux_irq(irq, rport);
+ break;
+ case USB2PHY_PORT_HOST:
+ ret |= rockchip_usb2phy_linestate_irq(irq, rport);
diff --git a/target/linux/rockchip/patches-5.19/0050-arm64-dts-rk356x-fix-upper-usb-port-on-BPI-R2-Pro.patch b/target/linux/rockchip/patches-5.19/0050-arm64-dts-rk356x-fix-upper-usb-port-on-BPI-R2-Pro.patch
new file mode 100644
index 00000000000000..c79420f0a61f7d
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0050-arm64-dts-rk356x-fix-upper-usb-port-on-BPI-R2-Pro.patch
@@ -0,0 +1,28 @@
+From c4e625e488b938bd312cde239cd902c479cba02e Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 8 Jul 2022 15:27:06 +0200
+Subject: [PATCH 50/51] arm64: dts: rk356x: fix upper usb port on BPI-R2-Pro
+
+- extcon is no more needed in 5.19 - so drop it
+ commit 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ")
+- dr_mode was changed from host to otg in rk356x.dtsi
+ commit bc405bb3eeee ("arm64: dts: rockchip: enable otg/drd
+ operation of usb_host0_xhci in rk356x")
+ change it back on board level as id-pin on r2pro is not connected
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -755,7 +755,7 @@
+ };
+
+ &usb_host0_xhci {
+- extcon = <&usb2phy0>;
++ dr_mode = "host";
+ status = "okay";
+ };
+
diff --git a/target/linux/rockchip/patches-5.19/0051-rockchip-add-pci3-for-rock3-a.patch b/target/linux/rockchip/patches-5.19/0051-rockchip-add-pci3-for-rock3-a.patch
new file mode 100644
index 00000000000000..204d3881b77af3
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0051-rockchip-add-pci3-for-rock3-a.patch
@@ -0,0 +1,211 @@
+From 18b08ab3fd6216d62a96cc8033ad5bb915fd5fcf Mon Sep 17 00:00:00 2001
+From: Marty Jones <mj8263788@gmail.com>
+Date: Mon, 11 Jul 2022 08:51:36 -0400
+Subject: [PATCH 51/51] rockchip: add pci3 for rock3 a
+
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3568-rock-3a.dts | 93 ++++++++++++++++---
+ 1 file changed, 78 insertions(+), 15 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+@@ -87,7 +87,40 @@
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+- vcc5v0_usb: vcc5v0-usb {
++ pcie30_avdd0v9: pcie30-avdd0v9 {
++ compatible = "regulator-fixed";
++ regulator-name = "pcie30_avdd0v9";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <900000>;
++ vin-supply = <&vcc3v3_sys>;
++ };
++
++ pcie30_avdd1v8: pcie30-avdd1v8 {
++ compatible = "regulator-fixed";
++ regulator-name = "pcie30_avdd1v8";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ vin-supply = <&vcc3v3_sys>;
++ };
++
++ pcie30_3v3: gpio-regulator {
++ compatible = "regulator-gpio";
++ regulator-name = "pcie30_3v3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <100000>;
++ regulator-max-microvolt = <3300000>;
++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
++ gpios-states = <0x1>;
++ states = <100000 0x0
++ 3300000 0x1>;
++ };
++
++ vcc5v0_usb: vcc5v0_usb {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+@@ -109,7 +142,7 @@
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+- vcc5v0_usb_hub: vcc5v0-usb-hub-regulator {
++ vcc5v0_usb_hub: vcc5v0-usb-hub {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+@@ -120,7 +153,7 @@
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+- vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
++ vcc5v0_usb_otg: vcc5v0-usb-otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+@@ -141,6 +174,10 @@
+ status = "okay";
+ };
+
++&combphy2 {
++ status = "okay";
++};
++
+ &cpu0 {
+ cpu-supply = <&vdd_cpu>;
+ };
+@@ -159,17 +196,25 @@
+
+ &gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+- assigned-clock-rates = <0>, <125000000>;
++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy1>;
+- phy-mode = "rgmii-id";
++ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus>;
++
++ snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
++ snps,reset-active-low;
++ /* Reset time is 20ms, 100ms for rtl8211f */
++ snps,reset-delays-us = <0 20000 100000>;
++
++ tx_delay = <0x3c>;
++ rx_delay = <0x2f>;
++
+ status = "okay";
+ };
+
+@@ -313,6 +358,7 @@
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
++ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+@@ -349,6 +395,7 @@
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
++ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+@@ -407,6 +454,7 @@
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
++ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+@@ -427,6 +475,7 @@
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
++ regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+@@ -453,14 +502,30 @@
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+- pinctrl-names = "default";
+- pinctrl-0 = <ð_phy_rst>;
+- reset-assert-us = <20000>;
+- reset-deassert-us = <100000>;
+- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ };
+ };
+
++&pcie30phy {
++ status = "okay";
++};
++
++&pcie3x2 {
++ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&pcie30_3v3>;
++ //num-lanes = <2>;
++ pinctrl-0 = <&pcie30x2m1_pins>;
++ bus-scan-delay-ms = <1000>;
++ status = "okay";
++};
++
++&pcie2x1 {
++ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&pcie30_3v3>;
++ pinctrl-0 = <&pcie20m1_pins>;
++ bus-scan-delay-ms = <1000>;
++ status = "okay";
++};
++
+ &pinctrl {
+ ethernet {
+ eth_phy_rst: eth_phy_rst {
+@@ -555,7 +620,7 @@
+ };
+
+ &usb_host0_xhci {
+- extcon = <&usb2phy0>;
++ dr_mode = "host";
+ status = "okay";
+ };
+
+@@ -581,7 +646,7 @@
+ };
+
+ &usb2phy0_otg {
+- vbus-supply = <&vcc5v0_usb_otg>;
++ phy-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+ };
+
+@@ -590,12 +655,10 @@
+ };
+
+ &usb2phy1_host {
+- phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+ };
+
+ &usb2phy1_otg {
+- phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+ };
+
diff --git a/target/linux/rockchip/patches-5.19/0052-rockchip-add-FriendlyElec-NanoPi-R5S-rk3568-board.patch b/target/linux/rockchip/patches-5.19/0052-rockchip-add-FriendlyElec-NanoPi-R5S-rk3568-board.patch
new file mode 100644
index 00000000000000..bef12c6478a282
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0052-rockchip-add-FriendlyElec-NanoPi-R5S-rk3568-board.patch
@@ -0,0 +1,844 @@
+From 9303b0a0fa722689633cf2f09ba4f8fcaaff13c9 Mon Sep 17 00:00:00 2001
+From: Marty Jones <mj8263788@gmail.com>
+Date: Sun, 31 Jul 2022 02:31:59 -0400
+Subject: [PATCH] rockchip: add FriendlyElec NanoPi R5S rk3568 board
+
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 1 +
+ .../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 821 ++++++++++++++++++
+ 2 files changed, 822 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -65,4 +65,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+@@ -0,0 +1,821 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++
++/dts-v1/;
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
++#include "rk3568.dtsi"
++
++/ {
++ model = "FriendlyElec NanoPi R5S";
++ compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568";
++
++ aliases {
++ ethernet0 = &gmac0;
++ mmc0 = &sdmmc0;
++ mmc1 = &sdhci;
++ };
++
++ chosen: chosen {
++ stdout-path = "serial2:1500000n8";
++ };
++
++ fan: pwm-fan {
++ compatible = "pwm-fan";
++ cooling-levels = <0 18 102 170 255>;
++ #cooling-cells = <2>;
++ fan-supply = <&vcc5v0_sysp>;
++ pwms = <&pwm0 0 50000 0>;
++ };
++
++ firmware {
++ optee: optee {
++ compatible = "linaro,optee-tz";
++ method = "smc";
++ };
++ };
++
++ cspmu: cspmu@fd90c000 {
++ compatible = "rockchip,cspmu";
++ reg = <0x0 0xfd90c000 0x0 0x1000>,
++ <0x0 0xfd90d000 0x0 0x1000>,
++ <0x0 0xfd90e000 0x0 0x1000>,
++ <0x0 0xfd90f000 0x0 0x1000>;
++ };
++
++ gpio-key {
++ compatible = "gpio-key";
++ pinctrl-names = "default";
++ pinctrl-0 = <&key1_pin>;
++
++ button@1 {
++ debounce-interval = <50>;
++ gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
++ wakeup-source;
++ };
++ };
++
++ gpio-leds {
++ compatible = "gpio-leds";
++
++ sys_led: led-sys {
++ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
++ label = "red:power";
++ linux,default-trigger = "heartbeat";
++ pinctrl-names = "default";
++ pinctrl-0 = <&sys_led_pin>;
++ };
++
++ wan_led: led-wan {
++ gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
++ label = "green:wan";
++ pinctrl-names = "default";
++ pinctrl-0 = <&wan_led_pin>;
++ };
++
++ lan1_led: led-lan1 {
++ gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
++ label = "green:lan1";
++ pinctrl-names = "default";
++ pinctrl-0 = <&lan1_led_pin>;
++ };
++
++ lan2_led: led-lan2 {
++ gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
++ label = "green:lan2";
++ pinctrl-names = "default";
++ pinctrl-0 = <&lan2_led_pin>;
++ };
++ };
++
++ hdmi-con {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi_con_in: endpoint {
++ remote-endpoint = <&hdmi_out_con>;
++ };
++ };
++ };
++
++ vdd_usbc: vdd-usbc {
++ compatible = "regulator-fixed";
++ regulator-name = "vdd_usbc";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ vcc3v3_sys: vcc3v3-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v3_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vdd_usbc>;
++ };
++
++ vcc5v0_sys: vcc5v0-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vdd_usbc>;
++ };
++
++ pcie30_avdd0v9: pcie30-avdd0v9 {
++ compatible = "regulator-fixed";
++ regulator-name = "pcie30_avdd0v9";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <900000>;
++ vin-supply = <&vcc3v3_sys>;
++ };
++
++ pcie30_avdd1v8: pcie30-avdd1v8 {
++ compatible = "regulator-fixed";
++ regulator-name = "pcie30_avdd1v8";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ vin-supply = <&vcc3v3_sys>;
++ };
++
++ vcc3v3_pcie: vcc3v3-pcie-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v3_pcie";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ enable-active-high;
++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
++ startup-delay-us = <200000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc3v3_pcie: vcc3v3-pcie-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v3_pcie";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ enable-active-high;
++ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
++ startup-delay-us = <50000>;
++ vin-supply = <&vcc3v3_pcie>;
++ };
++
++ vcc3v3_ngff: vcc3v3-ngff-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v3_ngff";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ enable-active-high;
++ gpio = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>;
++ startup-delay-us = <50000>;
++ vin-supply = <&vcc3v3_pcie>;
++ };
++
++ vcc5v0_usb: vcc5v0_usb {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_usb";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vdd_usbc>;
++ };
++
++ vcc5v0_usb_host: vcc5v0-usb-host {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&vcc5v0_usb_host_en>;
++ regulator-name = "vcc5v0_usb_host";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc5v0_usb>;
++ };
++
++ vcc5v0_sysp: vcc5v0-sysp {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_sysp";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc3v3_sys>;
++ };
++
++ vcc5v0_usb_otg: vcc5v0-usb-otg {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&vcc5v0_usb_otg_en>;
++ regulator-name = "vcc5v0_usb_otg";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc5v0_usb>;
++ };
++};
++
++&combphy0 {
++ status = "okay";
++};
++
++&combphy1 {
++ status = "okay";
++};
++
++&combphy2 {
++ status = "okay";
++};
++
++&cpu0 {
++ cpu-supply = <&vdd_cpu>;
++};
++
++&cpu1 {
++ cpu-supply = <&vdd_cpu>;
++};
++
++&cpu2 {
++ cpu-supply = <&vdd_cpu>;
++};
++
++&cpu3 {
++ cpu-supply = <&vdd_cpu>;
++};
++
++&gmac0 {
++ phy-mode = "rgmii";
++ clock_in_out = "output";
++
++ snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
++ snps,reset-active-low;
++ /* Reset time is 20ms, 100ms for rtl8211f */
++ snps,reset-delays-us = <0 20000 100000>;
++
++ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
++ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
++
++ pinctrl-names = "default";
++ pinctrl-0 = <&gmac0_miim
++ &gmac0_tx_bus2
++ &gmac0_rx_bus2
++ &gmac0_rgmii_clk
++ &gmac0_rgmii_bus>;
++
++ tx_delay = <0x3c>;
++ rx_delay = <0x2f>;
++
++ phy-handle = <&rgmii_phy0>;
++ status = "okay";
++};
++
++
++&gpu {
++ mali-supply = <&vdd_gpu>;
++ status = "okay";
++};
++
++&hdmi {
++ avdd-0v9-supply = <&vdda0v9_image>;
++ avdd-1v8-supply = <&vcca1v8_image>;
++ status = "okay";
++};
++
++&hdmi_in {
++ hdmi_in_vp0: endpoint {
++ remote-endpoint = <&vp0_out_hdmi>;
++ };
++};
++
++&hdmi_out {
++ hdmi_out_con: endpoint {
++ remote-endpoint = <&hdmi_con_in>;
++ };
++};
++
++&hdmi_sound {
++ status = "okay";
++};
++
++&i2c0 {
++ status = "okay";
++
++ vdd_cpu: regulator@1c {
++ compatible = "tcs,tcs4525";
++ reg = <0x1c>;
++ fcs,suspend-voltage-selector = <1>;
++ regulator-name = "vdd_cpu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1150000>;
++ regulator-ramp-delay = <2300>;
++ vin-supply = <&vcc5v0_sys>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ rk809: pmic@20 {
++ compatible = "rockchip,rk809";
++ reg = <0x20>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
++ #clock-cells = <1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_int>;
++ rockchip,system-power-controller;
++ vcc1-supply = <&vcc3v3_sys>;
++ vcc2-supply = <&vcc3v3_sys>;
++ vcc3-supply = <&vcc3v3_sys>;
++ vcc4-supply = <&vcc3v3_sys>;
++ vcc5-supply = <&vcc3v3_sys>;
++ vcc6-supply = <&vcc3v3_sys>;
++ vcc7-supply = <&vcc3v3_sys>;
++ vcc8-supply = <&vcc3v3_sys>;
++ vcc9-supply = <&vcc3v3_sys>;
++ wakeup-source;
++
++ regulators {
++ vdd_logic: DCDC_REG1 {
++ regulator-name = "vdd_logic";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-init-microvolt = <900000>;
++ regulator-initial-mode = <0x2>;
++ regulator-min-microvolt = <500000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-ramp-delay = <6001>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_gpu: DCDC_REG2 {
++ regulator-name = "vdd_gpu";
++ regulator-always-on;
++ regulator-init-microvolt = <900000>;
++ regulator-initial-mode = <0x2>;
++ regulator-min-microvolt = <500000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-ramp-delay = <6001>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_ddr: DCDC_REG3 {
++ regulator-name = "vcc_ddr";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-initial-mode = <0x2>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vdd_npu: DCDC_REG4 {
++ regulator-name = "vdd_npu";
++ regulator-init-microvolt = <900000>;
++ regulator-initial-mode = <0x2>;
++ regulator-min-microvolt = <500000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-ramp-delay = <6001>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_1v8: DCDC_REG5 {
++ regulator-name = "vcc_1v8";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda0v9_image: LDO_REG1 {
++ regulator-name = "vdda0v9_image";
++ regulator-always-on;
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <900000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda_0v9: LDO_REG2 {
++ regulator-name = "vdda_0v9";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <900000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda0v9_pmu: LDO_REG3 {
++ regulator-name = "vdda0v9_pmu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <900000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <900000>;
++ };
++ };
++
++ vccio_acodec: LDO_REG4 {
++ regulator-name = "vccio_acodec";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vccio_sd: LDO_REG5 {
++ regulator-name = "vccio_sd";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc3v3_pmu: LDO_REG6 {
++ regulator-name = "vcc3v3_pmu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vcca_1v8: LDO_REG7 {
++ regulator-name = "vcca_1v8";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcca1v8_pmu: LDO_REG8 {
++ regulator-name = "vcca1v8_pmu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vcca1v8_image: LDO_REG9 {
++ regulator-name = "vcca1v8_image";
++ regulator-always-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_3v3: SWITCH_REG1 {
++ regulator-name = "vcc_3v3";
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc3v3_sd: SWITCH_REG2 {
++ regulator-name = "vcc3v3_sd";
++ regulator-always-on;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++ };
++ };
++};
++
++
++&i2c5 {
++ status = "okay";
++
++ hym8563: hym8563@51 {
++ compatible = "haoyu,hym8563";
++ reg = <0x51>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&rtc_int>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
++ wakeup-source;
++ };
++};
++
++&i2s0_8ch {
++ status = "okay";
++};
++
++&i2s1_8ch {
++ rockchip,trcm-sync-tx-only;
++ status = "okay";
++};
++
++
++&mdio0 {
++ rgmii_phy0: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <0x1>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&gmac_int>;
++ };
++};
++
++&pcie30phy {
++ data-lanes = <1 2>;
++ status = "okay";
++};
++
++&pcie3x1 {
++ num-lanes = <1>;
++ reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_ngff>;
++ status = "okay";
++};
++
++&pcie3x2 {
++ num-lanes = <1>;
++ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_pcie>;
++ status = "okay";
++};
++
++&pcie2x1 {
++ num-viewport = <4>;
++ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
++&pinctrl {
++ gpio-leds {
++
++ sys_led_pin: sys-led-pin {
++ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ wan_led_pin: wan-led-pin {
++ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ lan1_led_pin: lan1-led-pin {
++ rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ lan2_led_pin: lan2-led-pin {
++ rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ gmac {
++ gmac_int: gmac-int {
++ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ gpio-key {
++ key1_pin: key1-pin {
++ rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ pmic {
++ pmic_int: pmic_int {
++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ rtc {
++ rtc_int: rtc-int {
++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ usb {
++ vcc5v0_usb_host_en: vcc5v0-usb-host-en {
++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
++
++&pmu_io_domains {
++ pmuio1-supply = <&vcc3v3_pmu>;
++ pmuio2-supply = <&vcc3v3_pmu>;
++ vccio1-supply = <&vccio_acodec>;
++ vccio3-supply = <&vccio_sd>;
++ vccio4-supply = <&vcc_1v8>;
++ vccio5-supply = <&vcc_3v3>;
++ vccio6-supply = <&vcc_1v8>;
++ vccio7-supply = <&vcc_3v3>;
++ status = "okay";
++};
++
++&pwm0 {
++ status = "okay";
++};
++
++&pwm4 {
++ status = "disabled";
++};
++
++&pwm5 {
++ status = "disabled";
++};
++
++&pwm7 {
++ status = "disabled";
++};
++
++&saradc {
++ vref-supply = <&vcca_1v8>;
++ status = "okay";
++};
++
++&sata2 {
++ status = "disabled";
++};
++
++&sdhci {
++ bus-width = <8>;
++ no-sdio;
++ no-sd;
++ non-removable;
++ max-frequency = <200000000>;
++ status = "okay";
++};
++
++&sdmmc0 {
++ max-frequency = <150000000>;
++ no-sdio;
++ no-mmc;
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ cap-sd-highspeed;
++ disable-wp;
++ sd-uhs-sdr104;
++ vmmc-supply = <&vcc3v3_sd>;
++ vqmmc-supply = <&vccio_sd>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
++ status = "okay";
++};
++
++&spi3 {
++ pinctrl-0 = <&spi3m1_pins>;
++ status = "disabled";
++};
++
++&tsadc {
++ rockchip,hw-tshut-mode = <1>;
++ rockchip,hw-tshut-polarity = <0>;
++ status = "okay";
++};
++
++&uart0 {
++ status = "disabled";
++};
++
++&uart2 {
++ status = "okay";
++};
++
++&uart7 {
++ pinctrl-0 = <&uart7m1_xfer>;
++ status = "disabled";
++};
++
++&uart9 {
++ pinctrl-0 = <&uart9m1_xfer>;
++ status = "disabled";
++};
++
++&usb_host0_ehci {
++ status = "okay";
++};
++
++&usb_host0_ohci {
++ status = "okay";
++};
++
++&usb_host0_xhci {
++ dr_mode = "host";
++ status = "okay";
++};
++
++&usb_host1_ehci {
++ status = "okay";
++};
++
++&usb_host1_ohci {
++ status = "okay";
++};
++
++&usb_host1_xhci {
++ status = "okay";
++};
++
++&usb2phy0 {
++ status = "okay";
++};
++
++&usb2phy0_host {
++ phy-supply = <&vcc5v0_usb_host>;
++ status = "okay";
++};
++
++&usb2phy0_otg {
++ phy-supply = <&vcc5v0_usb_otg>;
++ status = "okay";
++};
++
++&usb2phy1 {
++ status = "okay";
++};
++
++&usb2phy1_host {
++ status = "okay";
++};
++
++&usb2phy1_otg {
++ status = "okay";
++};
++
++&vop {
++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++ status = "okay";
++};
++
++&vop_mmu {
++ status = "okay";
++};
++
++&vp0 {
++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++ remote-endpoint = <&hdmi_in_vp0>;
++ };
++};
diff --git a/target/linux/rockchip/patches-5.19/0053-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-5.19/0053-rockchip-use-system-LED-for-OpenWrt.patch
new file mode 100644
index 00000000000000..5ec7952bfeaf88
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0053-rockchip-use-system-LED-for-OpenWrt.patch
@@ -0,0 +1,31 @@
+From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Fri, 10 Jul 2020 21:38:20 +0200
+Subject: [PATCH] rockchip: use system LED for OpenWrt
+
+Use the SYS LED on the casing for showing system status.
+
+This patch is kept separate from the NanoPi R2S support patch, as i plan
+on submitting the device support upstream.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+@@ -18,6 +18,13 @@
+ mmc0 = &sdmmc;
+ };
+
++ aliases {
++ led-boot = &sys_led;
++ led-failsafe = &sys_led;
++ led-running = &sys_led;
++ led-upgrade = &sys_led;
++ };
++
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
diff --git a/target/linux/rockchip/patches-5.19/0054-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.19/0054-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch
new file mode 100644
index 00000000000000..06e593a5a2b1c3
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0054-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch
@@ -0,0 +1,24 @@
+From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Sun, 26 Jul 2020 13:32:59 +0200
+Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S
+
+This adds the OF node for the USB3 ethernet adapter on the FriendlyARM
+NanoPi R2S. Add the correct value for the RTL8153 LED configuration
+register to match the blink behavior of the other port on the device.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+@@ -404,6 +404,7 @@
+ rtl8153: device@2 {
+ compatible = "usbbda,8153";
+ reg = <2>;
++ realtek,led-data = <0x87>;
+ };
+ };
+
diff --git a/target/linux/rockchip/patches-5.19/111-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-N.patch b/target/linux/rockchip/patches-5.19/111-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-N.patch
new file mode 100644
index 00000000000000..f3ad8e18075cda
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/111-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-N.patch
@@ -0,0 +1,397 @@
+From ac8fa7a4d6e548cd4d4719f12cefb664191a41c2 Mon Sep 17 00:00:00 2001
+From: Marty Jones <mj8263788@gmail.com>
+Date: Wed, 12 May 2021 13:04:20 -0400
+Subject: [PATCH] rockchip: rk3328: add support for FriendlyARM NanoPi NEO3
+
+This patch adds support for FriendlyARM NanoPi NEO3
+
+Soc: RockChip RK3328
+RAM: 1GB/2GB DDR4
+LAN: 10/100/1000M Ethernet with unique MAC
+USB Host: 1x USB3.0 Type A and 2x USB2.0 on 2.54mm pin header
+MicroSD: x 1 for system boot and storage
+LED: Power LED x 1, System LED x 1
+Key: User Button x 1
+Fan: 2 Pin JST ZH 1.5mm Connector for 5V Fan
+GPIO: 26 pin-header, include I2C, UART, SPI, I2S, GPIO
+Power: 5V/1A, via Type-C or GPIO
+
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 1 +
+ .../boot/dts/rockchip/rk3328-nanopi-neo3.dts | 359 ++++++++++++++++++
+ 2 files changed, 360 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-neo3.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts
+@@ -0,0 +1,359 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/gpio/gpio.h>
++#include "rk3328.dtsi"
++
++/ {
++ model = "FriendlyElec NanoPi NEO3";
++ compatible = "friendlyarm,nanopi-neo3", "rockchip,rk3328";
++
++ chosen {
++ stdout-path = "serial2:1500000n8";
++ };
++
++ gmac_clk: gmac-clock {
++ compatible = "fixed-clock";
++ clock-frequency = <125000000>;
++ clock-output-names = "gmac_clkin";
++ #clock-cells = <0>;
++ };
++
++ keys {
++ compatible = "gpio-keys";
++ pinctrl-0 = <&reset_button_pin>;
++ pinctrl-names = "default";
++
++ reset {
++ label = "reset";
++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
++ linux,code = <KEY_RESTART>;
++ debounce-interval = <50>;
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-0 = <&stat_led_pin>;
++ pinctrl-names = "default";
++
++ stat_led: led-1 {
++ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
++ label = "nanopi-neo3:green:stat";
++ };
++ };
++
++ vcc_io_sdio: sdmmcio-regulator {
++ compatible = "regulator-gpio";
++ enable-active-high;
++ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
++ pinctrl-0 = <&sdio_vcc_pin>;
++ pinctrl-names = "default";
++ regulator-name = "vcc_io_sdio";
++ regulator-always-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-settling-time-us = <5000>;
++ regulator-type = "voltage";
++ startup-delay-us = <2000>;
++ states = <1800000 0x1>,
++ <3300000 0x0>;
++ vin-supply = <&vcc_io_33>;
++ };
++
++ vcc_sd: sdmmc-regulator {
++ compatible = "regulator-fixed";
++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
++ pinctrl-0 = <&sdmmc0m1_pin>;
++ pinctrl-names = "default";
++ regulator-name = "vcc_sd";
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc_io_33>;
++ };
++
++ vdd_5v: vdd-5v {
++ compatible = "regulator-fixed";
++ regulator-name = "vdd_5v";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++};
++
++&cpu0 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu1 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu2 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu3 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&display_subsystem {
++ status = "disabled";
++};
++
++&gmac2io {
++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
++ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
++ clock_in_out = "input";
++ phy-handle = <&rtl8211e>;
++ phy-mode = "rgmii";
++ phy-supply = <&vcc_io_33>;
++ pinctrl-0 = <&rgmiim1_pins>;
++ pinctrl-names = "default";
++ rx_delay = <0x18>;
++ snps,aal;
++ tx_delay = <0x24>;
++ status = "okay";
++
++ mdio {
++ compatible = "snps,dwmac-mdio";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ rtl8211e: ethernet-phy@1 {
++ reg = <1>;
++ pinctrl-0 = <ð_phy_reset_pin>;
++ pinctrl-names = "default";
++ reset-assert-us = <10000>;
++ reset-deassert-us = <50000>;
++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
++ };
++ };
++};
++
++&i2c1 {
++ status = "okay";
++
++ rk805: pmic@18 {
++ compatible = "rockchip,rk805";
++ reg = <0x18>;
++ interrupt-parent = <&gpio1>;
++ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
++ #clock-cells = <1>;
++ clock-output-names = "xin32k", "rk805-clkout2";
++ gpio-controller;
++ #gpio-cells = <2>;
++ pinctrl-0 = <&pmic_int_l>;
++ pinctrl-names = "default";
++ rockchip,system-power-controller;
++ wakeup-source;
++
++ vcc1-supply = <&vdd_5v>;
++ vcc2-supply = <&vdd_5v>;
++ vcc3-supply = <&vdd_5v>;
++ vcc4-supply = <&vdd_5v>;
++ vcc5-supply = <&vcc_io_33>;
++ vcc6-supply = <&vdd_5v>;
++
++ regulators {
++ vdd_log: DCDC_REG1 {
++ regulator-name = "vdd_log";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <712500>;
++ regulator-max-microvolt = <1450000>;
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1000000>;
++ };
++ };
++
++ vdd_arm: DCDC_REG2 {
++ regulator-name = "vdd_arm";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <712500>;
++ regulator-max-microvolt = <1450000>;
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <950000>;
++ };
++ };
++
++ vcc_ddr: DCDC_REG3 {
++ regulator-name = "vcc_ddr";
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vcc_io_33: DCDC_REG4 {
++ regulator-name = "vcc_io_33";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vcc_18: LDO_REG1 {
++ regulator-name = "vcc_18";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vcc18_emmc: LDO_REG2 {
++ regulator-name = "vcc18_emmc";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdd_10: LDO_REG3 {
++ regulator-name = "vdd_10";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <1000000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1000000>;
++ };
++ };
++ };
++ };
++};
++
++&io_domains {
++ pmuio-supply = <&vcc_io_33>;
++ vccio1-supply = <&vcc_io_33>;
++ vccio2-supply = <&vcc18_emmc>;
++ vccio3-supply = <&vcc_io_sdio>;
++ vccio4-supply = <&vcc_18>;
++ vccio5-supply = <&vcc_io_33>;
++ vccio6-supply = <&vcc_io_33>;
++ status = "okay";
++};
++
++&pinctrl {
++ button {
++ reset_button_pin: reset-button-pin {
++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ gmac2io {
++ eth_phy_reset_pin: eth-phy-reset-pin {
++ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
++ };
++ };
++
++ leds {
++ stat_led_pin: stat-led-pin {
++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pmic {
++ pmic_int_l: pmic-int-l {
++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ sd {
++ sdio_vcc_pin: sdio-vcc-pin {
++ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++};
++
++&pwm2 {
++ status = "okay";
++};
++
++&sdmmc {
++ bus-width = <4>;
++ cap-sd-highspeed;
++ disable-wp;
++ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
++ pinctrl-names = "default";
++ sd-uhs-sdr12;
++ sd-uhs-sdr25;
++ sd-uhs-sdr50;
++ sd-uhs-sdr104;
++ vmmc-supply = <&vcc_sd>;
++ vqmmc-supply = <&vcc_io_sdio>;
++ status = "okay";
++};
++
++&tsadc {
++ rockchip,hw-tshut-mode = <0>;
++ rockchip,hw-tshut-polarity = <0>;
++ status = "okay";
++};
++
++&u2phy {
++ status = "okay";
++};
++
++&u2phy_host {
++ status = "okay";
++};
++
++&u2phy_otg {
++ status = "okay";
++};
++
++&uart2 {
++ status = "okay";
++};
++
++&usb20_otg {
++ status = "okay";
++ dr_mode = "host";
++};
++
++&usb_host0_ehci {
++ status = "okay";
++};
++
++&usb_host0_ohci {
++ status = "okay";
++};
++
++&usbdrd3 {
++ dr_mode = "host";
++ status = "okay";
++};
From f861ce8a61cddfd44f873ad9a4c9c14381c9d080 Mon Sep 17 00:00:00 2001
From: coolsnowwolf <coolsowwolf@gmail.com>
Date: Fri, 5 Aug 2022 06:38:54 +0000
Subject: [PATCH 5/9] rockchip: refresh 5.19 patch
---
target/linux/rockchip/Makefile | 2 +-
...dd-support-for-FriendlyARM-NanoPi-N.patch} | 0
...add-driver-for-Motorcomm-YT85xx+PHYs.patch | 2243 +++++++++++++++
...ip-add-hardware-random-number-genera.patch | 50 +
...ip-add-devfreq-driver-for-rk3328-dmc.patch | 44 +
...setting-ddr-clock-via-SIP-Version-2-.patch | 210 ++
...eq-rockchip-dfi-add-more-soc-support.patch | 662 +++++
...m64-dts-rockchip-rk3328-add-dfi-node.patch | 27 +
...anopi-r2s-add-rk3328-dmc-relate-node.patch | 126 +
...drv-net-phy-add-JLSemi-jl2xxx-driver.patch | 702 +++++
.../0900-arm-boot-add-dts-files.patch | 34 +
...overclock-to-2.2-1.8-GHz-for-NanoPi4.patch | 21 +
...ip-add-more-cpu-operating-points-for.patch | 44 +
...o-rockchip-permit-to-pass-self-tests.patch | 2419 +++++++++++++++++
14 files changed, 6583 insertions(+), 1 deletion(-)
rename target/linux/rockchip/patches-5.19/{111-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-N.patch => 0055-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-N.patch} (100%)
create mode 100644 target/linux/rockchip/patches-5.19/0056-add-driver-for-Motorcomm-YT85xx+PHYs.patch
create mode 100644 target/linux/rockchip/patches-5.19/0057-arm64-dts-rockchip-add-hardware-random-number-genera.patch
create mode 100644 target/linux/rockchip/patches-5.19/0058-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch
create mode 100644 target/linux/rockchip/patches-5.19/0059-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch
create mode 100644 target/linux/rockchip/patches-5.19/0060-PM-devfreq-rockchip-dfi-add-more-soc-support.patch
create mode 100644 target/linux/rockchip/patches-5.19/0061-arm64-dts-rockchip-rk3328-add-dfi-node.patch
create mode 100644 target/linux/rockchip/patches-5.19/0062-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch
create mode 100644 target/linux/rockchip/patches-5.19/0063-drv-net-phy-add-JLSemi-jl2xxx-driver.patch
create mode 100644 target/linux/rockchip/patches-5.19/0900-arm-boot-add-dts-files.patch
create mode 100644 target/linux/rockchip/patches-5.19/0901-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch
create mode 100644 target/linux/rockchip/patches-5.19/0902-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch
create mode 100644 target/linux/rockchip/patches-5.19/0903-crypto-rockchip-permit-to-pass-self-tests.patch
diff --git a/target/linux/rockchip/Makefile b/target/linux/rockchip/Makefile
index e616ba05cbd241..82ac5ef9da12c8 100644
--- a/target/linux/rockchip/Makefile
+++ b/target/linux/rockchip/Makefile
@@ -8,7 +8,7 @@ FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-pa
SUBTARGETS:=armv8
KERNEL_PATCHVER=5.15
-KERNEL_TESTING_PATCHVER=5.4
+KERNEL_TESTING_PATCHVER=5.19
define Target/Description
Build firmware image for Rockchip SoC devices.
diff --git a/target/linux/rockchip/patches-5.19/111-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-N.patch b/target/linux/rockchip/patches-5.19/0055-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-N.patch
similarity index 100%
rename from target/linux/rockchip/patches-5.19/111-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-N.patch
rename to target/linux/rockchip/patches-5.19/0055-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-N.patch
diff --git a/target/linux/rockchip/patches-5.19/0056-add-driver-for-Motorcomm-YT85xx+PHYs.patch b/target/linux/rockchip/patches-5.19/0056-add-driver-for-Motorcomm-YT85xx+PHYs.patch
new file mode 100644
index 00000000000000..26227e020481cd
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0056-add-driver-for-Motorcomm-YT85xx+PHYs.patch
@@ -0,0 +1,2243 @@
+--- a/drivers/net/phy/motorcomm.c
++++ b/drivers/net/phy/motorcomm.c
+@@ -1,137 +1,1540 @@
+-// SPDX-License-Identifier: GPL-2.0+
+ /*
++ * drivers/net/phy/motorcomm.c
++ *
+ * Driver for Motorcomm PHYs
+ *
+- * Author: Peter Geis <pgwipeout@gmail.com>
++ * Author: Leilei Zhao <leilei.zhao@motorcomm.com>
++ *
++ * Copyright (c) 2019 Motorcomm, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * Support : Motorcomm Phys:
++ * Giga phys: yt8511, yt8521
++ * 100/10 Phys : yt8512, yt8512b, yt8510
++ * Automotive 100Mb Phys : yt8010
++ * Automotive 100/10 hyper range Phys: yt8510
+ */
+
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/phy.h>
++#include <linux/motorcomm_phy.h>
++#include <linux/of.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#ifndef LINUX_VERSION_CODE
++#include <linux/version.h>
++#else
++#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
++#endif
++/*for wol, 20210604*/
++#include <linux/netdevice.h>
++
++#include "yt8614-phy.h"
++
++/**** configuration section begin ***********/
++
++/* if system depends on ethernet packet to restore from sleep, please define this macro to 1
++ * otherwise, define it to 0.
++ */
++#define SYS_WAKEUP_BASED_ON_ETH_PKT 1
++
++/* to enable system WOL of phy, please define this macro to 1
++ * otherwise, define it to 0.
++ */
++#define YTPHY_ENABLE_WOL 0
++
++/* some GMAC need clock input from PHY, for eg., 125M, please enable this macro
++ * by degault, it is set to 0
++ * NOTE: this macro will need macro SYS_WAKEUP_BASED_ON_ETH_PKT to set to 1
++ */
++#define GMAC_CLOCK_INPUT_NEEDED 1
+
+-#define PHY_ID_YT8511 0x0000010a
+
+-#define YT8511_PAGE_SELECT 0x1e
+-#define YT8511_PAGE 0x1f
+-#define YT8511_EXT_CLK_GATE 0x0c
+-#define YT8511_EXT_DELAY_DRIVE 0x0d
+-#define YT8511_EXT_SLEEP_CTRL 0x27
+-
+-/* 2b00 25m from pll
+- * 2b01 25m from xtl *default*
+- * 2b10 62.m from pll
+- * 2b11 125m from pll
+- */
+-#define YT8511_CLK_125M (BIT(2) | BIT(1))
+-#define YT8511_PLLON_SLP BIT(14)
+-
+-/* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */
+-#define YT8511_DELAY_RX BIT(0)
+-
+-/* TX Gig-E Delay is bits 7:4, default 0x5
+- * TX Fast-E Delay is bits 15:12, default 0xf
+- * Delay = 150ps * N - 250ps
+- * On = 2000ps, off = 50ps
+- */
+-#define YT8511_DELAY_GE_TX_EN (0xf << 4)
+-#define YT8511_DELAY_GE_TX_DIS (0x2 << 4)
+-#define YT8511_DELAY_FE_TX_EN (0xf << 12)
+-#define YT8511_DELAY_FE_TX_DIS (0x2 << 12)
++#define YT8521_PHY_MODE_FIBER 1 //fiber mode only
++#define YT8521_PHY_MODE_UTP 2 //utp mode only
++#define YT8521_PHY_MODE_POLL 3 //fiber and utp, poll mode
+
+-static int yt8511_read_page(struct phy_device *phydev)
++/* please make choice according to system design
++ * for Fiber only system, please define YT8521_PHY_MODE_CURR 1
++ * for UTP only system, please define YT8521_PHY_MODE_CURR 2
++ * for combo system, please define YT8521_PHY_MODE_CURR 3
++ */
++#define YT8521_PHY_MODE_CURR 3
++
++/**** configuration section end ***********/
++
++
++/* no need to change below */
++
++#if (YTPHY_ENABLE_WOL)
++#undef SYS_WAKEUP_BASED_ON_ETH_PKT
++#define SYS_WAKEUP_BASED_ON_ETH_PKT 1
++#endif
++
++/* workaround for 8521 fiber 100m mode */
++static int link_mode_8521 = 0; //0: no link; 1: utp; 32: fiber. traced that 1000m fiber uses 32.
++static int link_mode_8614[4] = {0}; //0: no link; 1: utp; 32: fiber. traced that 1000m fiber uses 32.
++
++/* for multiple port phy, base phy address */
++static unsigned int yt_mport_base_phy_addr = 0xff; //0xff: invalid; for 8618
++static unsigned int yt_mport_base_phy_addr_8614 = 0xff; //0xff: invalid;
++
++int phy_yt8531_led_fixup(struct mii_bus *bus, int addr);
++int yt8511_config_out_125m(struct mii_bus *bus, int phy_id);
++
++#if ( LINUX_VERSION_CODE > KERNEL_VERSION(5,0,0) )
++int genphy_config_init(struct phy_device *phydev)
+ {
+- return __phy_read(phydev, YT8511_PAGE_SELECT);
+-};
++ int ret;
++
++ printk (KERN_INFO "yzhang..read phyaddr=%d, phyid=%08x\n",phydev->mdio.addr, phydev->phy_id);
+
+-static int yt8511_write_page(struct phy_device *phydev, int page)
++ if(phydev->phy_id == 0x4f51e91b)
++ {
++ printk (KERN_INFO "yzhang..get YT8511, abt to set 125m clk out, phyaddr=%d, phyid=%08x\n",phydev->mdio.addr, phydev->phy_id);
++ ret = yt8511_config_out_125m(phydev->mdio.bus, phydev->mdio.addr);
++ printk (KERN_INFO "yzhang..8511 set 125m clk out, reg=%#04x\n",phydev->mdio.bus->read(phydev->mdio.bus,phydev->mdio.addr,0x1f)/*double check as delay*/);
++ if (ret<0)
++ printk (KERN_INFO "yzhang..failed to set 125m clk out, ret=%d\n",ret);
++
++ phy_yt8531_led_fixup(phydev->mdio.bus, phydev->mdio.addr);
++ }
++ return genphy_read_abilities(phydev);
++}
++#endif
++
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++static int ytphy_config_init(struct phy_device *phydev)
+ {
+- return __phy_write(phydev, YT8511_PAGE_SELECT, page);
+-};
++ return 0;
++}
++#endif
++
++static int ytphy_read_ext(struct phy_device *phydev, u32 regnum)
++{
++ int ret;
++ int val;
++
++ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
++ if (ret < 0)
++ return ret;
++
++ val = phy_read(phydev, REG_DEBUG_DATA);
++
++ return val;
++}
++
++static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val)
++{
++ int ret;
++
++ ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
++ if (ret < 0)
++ return ret;
++
++ ret = phy_write(phydev, REG_DEBUG_DATA, val);
++
++ return ret;
++}
++
++static int yt8010_config_aneg(struct phy_device *phydev)
++{
++ phydev->speed = SPEED_100;
++ return 0;
++}
++
++static int yt8512_clk_init(struct phy_device *phydev)
++{
++ int ret;
++ int val;
++
++ val = ytphy_read_ext(phydev, YT8512_EXTREG_AFE_PLL);
++ if (val < 0)
++ return val;
++
++ val |= YT8512_CONFIG_PLL_REFCLK_SEL_EN;
++
++ ret = ytphy_write_ext(phydev, YT8512_EXTREG_AFE_PLL, val);
++ if (ret < 0)
++ return ret;
++
++ val = ytphy_read_ext(phydev, YT8512_EXTREG_EXTEND_COMBO);
++ if (val < 0)
++ return val;
++
++ val |= YT8512_CONTROL1_RMII_EN;
++
++ ret = ytphy_write_ext(phydev, YT8512_EXTREG_EXTEND_COMBO, val);
++ if (ret < 0)
++ return ret;
++
++ val = phy_read(phydev, MII_BMCR);
++ if (val < 0)
++ return val;
++
++ val |= YT_SOFTWARE_RESET;
++ ret = phy_write(phydev, MII_BMCR, val);
++
++ return ret;
++}
++
++static int yt8512_led_init(struct phy_device *phydev)
++{
++ int ret;
++ int val;
++ int mask;
++
++ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED0);
++ if (val < 0)
++ return val;
++
++ val |= YT8512_LED0_ACT_BLK_IND;
++
++ mask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN |
++ YT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN |
++ YT8512_LED0_BT_ON_EN;
++ val &= ~mask;
++
++ ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val);
++ if (ret < 0)
++ return ret;
++
++ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED1);
++ if (val < 0)
++ return val;
++
++ val |= YT8512_LED1_BT_ON_EN;
++
++ mask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN;
++ val &= ~mask;
++
++ ret = ytphy_write_ext(phydev, YT8512_LED1_BT_ON_EN, val);
++
++ return ret;
++}
++
++static int yt8512_config_init(struct phy_device *phydev)
++{
++ int ret;
++ int val;
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ ret = ytphy_config_init(phydev);
++#else
++ ret = genphy_config_init(phydev);
++#endif
++ if (ret < 0)
++ return ret;
++
++ ret = yt8512_clk_init(phydev);
++ if (ret < 0)
++ return ret;
++
++ ret = yt8512_led_init(phydev);
++
++ /* disable auto sleep */
++ val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1);
++ if (val < 0)
++ return val;
++
++ val &= (~BIT(YT8512_EN_SLEEP_SW_BIT));
++
++ ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val);
++ if (ret < 0)
++ return ret;
++
++ return ret;
++}
++
++static int yt8512_read_status(struct phy_device *phydev)
++{
++ int ret;
++ int val;
++ int speed, speed_mode, duplex;
++
++ ret = genphy_update_link(phydev);
++ if (ret)
++ return ret;
++
++ val = phy_read(phydev, REG_PHY_SPEC_STATUS);
++ if (val < 0)
++ return val;
++
++ duplex = (val & YT8512_DUPLEX) >> YT8512_DUPLEX_BIT;
++ speed_mode = (val & YT8512_SPEED_MODE) >> YT8512_SPEED_MODE_BIT;
++ switch (speed_mode) {
++ case 0:
++ speed = SPEED_10;
++ break;
++ case 1:
++ speed = SPEED_100;
++ break;
++ case 2:
++ case 3:
++ default:
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ speed = -1;
++#else
++ speed = SPEED_UNKNOWN;
++#endif
++ break;
++ }
++
++ phydev->speed = speed;
++ phydev->duplex = duplex;
++
++ return 0;
++}
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++#else
++#if 0
++int yt8521_soft_reset(struct phy_device *phydev)
++{
++ int ret;
++
++ ytphy_write_ext(phydev, 0xa000, 0);
++ ret = genphy_soft_reset(phydev);
++ if (ret < 0)
++ return ret;
++
++ ytphy_write_ext(phydev, 0xa000, 2);
++ ret = genphy_soft_reset(phydev);
++ if (ret < 0) {
++ ytphy_write_ext(phydev, 0xa000, 0);
++ return ret;
++ }
++
++ return 0;
++}
++#else
++/* qingsong feedback 2 genphy_soft_reset will cause problem.
++ * and this is the reduction version
++ */
++int yt8521_soft_reset(struct phy_device *phydev)
++{
++ int ret, val;
++
++ val = ytphy_read_ext(phydev, 0xa001);
++ ytphy_write_ext(phydev, 0xa001, (val & ~0x8000));
++
++ ret = genphy_soft_reset(phydev);
++ if (ret < 0)
++ return ret;
++
++ return 0;
++}
++#endif
++
++#endif
++
++#if GMAC_CLOCK_INPUT_NEEDED
++static int ytphy_mii_rd_ext(struct mii_bus *bus, int phy_id, u32 regnum)
++{
++ int ret;
++ int val;
++
++ ret = bus->write(bus, phy_id, REG_DEBUG_ADDR_OFFSET, regnum);
++ if (ret < 0)
++ return ret;
++
++ val = bus->read(bus, phy_id, REG_DEBUG_DATA);
++
++ return val;
++}
++
++static int ytphy_mii_wr_ext(struct mii_bus *bus, int phy_id, u32 regnum, u16 val)
++{
++ int ret;
++
++ ret = bus->write(bus, phy_id, REG_DEBUG_ADDR_OFFSET, regnum);
++ if (ret < 0)
++ return ret;
++
++ ret = bus->write(bus, phy_id, REG_DEBUG_DATA, val);
++
++ return ret;
++}
++
++int yt8511_config_dis_txdelay(struct mii_bus *bus, int phy_id)
++{
++ int ret;
++ int val;
++
++ /* disable auto sleep */
++ val = ytphy_mii_rd_ext(bus, phy_id, 0x27);
++ if (val < 0)
++ return val;
++
++ val &= (~BIT(15));
++
++ ret = ytphy_mii_wr_ext(bus, phy_id, 0x27, val);
++ if (ret < 0)
++ return ret;
++
++ /* enable RXC clock when no wire plug */
++ val = ytphy_mii_rd_ext(bus, phy_id, 0xc);
++ if (val < 0)
++ return val;
++
++ /* ext reg 0xc b[7:4]
++ Tx Delay time = 150ps * N - 250ps
++ */
++ val &= ~(0xf << 4);
++ ret = ytphy_mii_wr_ext(bus, phy_id, 0xc, val);
++ printk("yt8511_config_dis_txdelay..phy txdelay, val=%#08x\n",val);
++
++ return ret;
++}
++
++int phy_yt8531_led_fixup(struct mii_bus *bus, int addr)
++{
++ printk("%s in\n", __func__);
++
++ ytphy_mii_wr_ext(bus, addr, 0xa00d, 0x670);
++ ytphy_mii_wr_ext(bus, addr, 0xa00e, 0x2070);
++ ytphy_mii_wr_ext(bus, addr, 0xa00f, 0x7e);
++
++ return 0;
++}
++
++int yt8511_config_out_125m(struct mii_bus *bus, int addr)
++{
++ int ret;
++ int val;
++
++ mdelay(50);
++ ret = ytphy_mii_wr_ext(bus, addr, 0xa012, 0xd0);
++
++ mdelay(100);
++ val = ytphy_mii_rd_ext(bus, addr, 0xa012);
++
++ if(val != 0xd0)
++ {
++ printk("yt8511_config_out_125m error\n");
++ return -1;
++ }
++
++ /* disable auto sleep */
++ val = ytphy_mii_rd_ext(bus, addr, 0x27);
++ if (val < 0)
++ return val;
++
++ val &= (~BIT(15));
++
++ ret = ytphy_mii_wr_ext(bus, addr, 0x27, val);
++ if (ret < 0)
++ return ret;
++
++ /* enable RXC clock when no wire plug */
++ val = ytphy_mii_rd_ext(bus, addr, 0xc);
++ if (val < 0)
++ return val;
++
++ /* ext reg 0xc.b[2:1]
++ 00-----25M from pll;
++ 01---- 25M from xtl;(default)
++ 10-----62.5M from pll;
++ 11----125M from pll(here set to this value)
++ */
++ val |= (3 << 1);
++ ret = ytphy_mii_wr_ext(bus, addr, 0xc, val);
++ printk("yt8511_config_out_125m, phy clk out, val=%#08x\n",val);
++
++#if 0
++ /* for customer, please enable it based on demand.
++ * configure to master
++ */
++ val = bus->read(bus, phy_id, 0x9/*master/slave config reg*/);
++ val |= (0x3<<11); //to be manual config and force to be master
++ ret = bus->write(bus, phy_id, 0x9, val); //take effect until phy soft reset
++ if (ret < 0)
++ return ret;
++
++ printk("yt8511_config_out_125m, phy to be master, val=%#08x\n",val);
++#endif
++
++ return ret;
++}
++
++EXPORT_SYMBOL(yt8511_config_out_125m);
+
+ static int yt8511_config_init(struct phy_device *phydev)
+ {
+- int oldpage, ret = 0;
+- unsigned int ge, fe;
++ int ret;
++
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ ret = ytphy_config_init(phydev);
++#else
++ ret = genphy_config_init(phydev);
++#endif
++
++ return ret;
++}
++#endif /*GMAC_CLOCK_INPUT_NEEDED*/
++
++#if (YTPHY_ENABLE_WOL)
++static int ytphy_switch_reg_space(struct phy_device *phydev, int space)
++{
++ int ret;
++
++ if (space == YTPHY_REG_SPACE_UTP){
++ ret = ytphy_write_ext(phydev, 0xa000, 0);
++ }else{
++ ret = ytphy_write_ext(phydev, 0xa000, 2);
++ }
++
++ return ret;
++}
++
++static int ytphy_wol_en_cfg(struct phy_device *phydev, ytphy_wol_cfg_t wol_cfg)
++{
++ int ret=0;
++ int val=0;
++
++ val = ytphy_read_ext(phydev, YTPHY_WOL_CFG_REG);
++ if (val < 0)
++ return val;
++
++ if(wol_cfg.enable) {
++ val |= YTPHY_WOL_CFG_EN;
++
++ if(wol_cfg.type == YTPHY_WOL_TYPE_LEVEL) {
++ val &= ~YTPHY_WOL_CFG_TYPE;
++ val &= ~YTPHY_WOL_CFG_INTR_SEL;
++ } else if(wol_cfg.type == YTPHY_WOL_TYPE_PULSE) {
++ val |= YTPHY_WOL_CFG_TYPE;
++ val |= YTPHY_WOL_CFG_INTR_SEL;
++
++ if(wol_cfg.width == YTPHY_WOL_WIDTH_84MS) {
++ val &= ~YTPHY_WOL_CFG_WIDTH1;
++ val &= ~YTPHY_WOL_CFG_WIDTH2;
++ } else if(wol_cfg.width == YTPHY_WOL_WIDTH_168MS) {
++ val |= YTPHY_WOL_CFG_WIDTH1;
++ val &= ~YTPHY_WOL_CFG_WIDTH2;
++ } else if(wol_cfg.width == YTPHY_WOL_WIDTH_336MS) {
++ val &= ~YTPHY_WOL_CFG_WIDTH1;
++ val |= YTPHY_WOL_CFG_WIDTH2;
++ } else if(wol_cfg.width == YTPHY_WOL_WIDTH_672MS) {
++ val |= YTPHY_WOL_CFG_WIDTH1;
++ val |= YTPHY_WOL_CFG_WIDTH2;
++ }
++ }
++ } else {
++ val &= ~YTPHY_WOL_CFG_EN;
++ val &= ~YTPHY_WOL_CFG_INTR_SEL;
++ }
++
++ ret = ytphy_write_ext(phydev, YTPHY_WOL_CFG_REG, val);
++ if (ret < 0)
++ return ret;
++
++ return 0;
++}
++
++static void ytphy_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
++{
++ int val = 0;
++
++ wol->supported = WAKE_MAGIC;
++ wol->wolopts = 0;
++
++ val = ytphy_read_ext(phydev, YTPHY_WOL_CFG_REG);
++ if (val < 0)
++ return;
++
++ if (val & YTPHY_WOL_CFG_EN)
++ wol->wolopts |= WAKE_MAGIC;
++
++ return;
++}
++
++static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
++{
++ int ret, pre_page, val;
++ ytphy_wol_cfg_t wol_cfg;
++ struct net_device *p_attached_dev = phydev->attached_dev;
++
++ memset(&wol_cfg,0,sizeof(ytphy_wol_cfg_t));
++ pre_page = ytphy_read_ext(phydev, 0xa000);
++ if (pre_page < 0)
++ return pre_page;
++
++ /* Switch to phy UTP page */
++ ret = ytphy_switch_reg_space(phydev, YTPHY_REG_SPACE_UTP);
++ if (ret < 0)
++ return ret;
++
++ if (wol->wolopts & WAKE_MAGIC) {
++
++ /* Enable the WOL interrupt */
++ val = phy_read(phydev, YTPHY_UTP_INTR_REG);
++ val |= YTPHY_WOL_INTR;
++ ret = phy_write(phydev, YTPHY_UTP_INTR_REG, val);
++ if (ret < 0)
++ return ret;
++
++ /* Set the WOL config */
++ wol_cfg.enable = 1; //enable
++ wol_cfg.type= YTPHY_WOL_TYPE_PULSE;
++ wol_cfg.width= YTPHY_WOL_WIDTH_672MS;
++ ret = ytphy_wol_en_cfg(phydev, wol_cfg);
++ if (ret < 0)
++ return ret;
++
++ /* Store the device address for the magic packet */
++ ret = ytphy_write_ext(phydev, YTPHY_MAGIC_PACKET_MAC_ADDR2,
++ ((p_attached_dev->dev_addr[0] << 8) |
++ p_attached_dev->dev_addr[1]));
++ if (ret < 0)
++ return ret;
++ ret = ytphy_write_ext(phydev, YTPHY_MAGIC_PACKET_MAC_ADDR1,
++ ((p_attached_dev->dev_addr[2] << 8) |
++ p_attached_dev->dev_addr[3]));
++ if (ret < 0)
++ return ret;
++ ret = ytphy_write_ext(phydev, YTPHY_MAGIC_PACKET_MAC_ADDR0,
++ ((p_attached_dev->dev_addr[4] << 8) |
++ p_attached_dev->dev_addr[5]));
++ if (ret < 0)
++ return ret;
++ } else {
++ wol_cfg.enable = 0; //disable
++ wol_cfg.type= YTPHY_WOL_TYPE_MAX;
++ wol_cfg.width= YTPHY_WOL_WIDTH_MAX;
++ ret = ytphy_wol_en_cfg(phydev, wol_cfg);
++ if (ret < 0)
++ return ret;
++ }
++
++ /* Recover to previous register space page */
++ ret = ytphy_switch_reg_space(phydev, pre_page);
++ if (ret < 0)
++ return ret;
++
++ return 0;
++}
++
++#endif /*(YTPHY_ENABLE_WOL)*/
++
++static int yt8521_config_init(struct phy_device *phydev)
++{
++ int ret;
++ int val;
+
+- oldpage = phy_select_page(phydev, YT8511_EXT_CLK_GATE);
+- if (oldpage < 0)
+- goto err_restore_page;
++ phydev->irq = PHY_POLL;
+
+- /* set rgmii delay mode */
+- switch (phydev->interface) {
+- case PHY_INTERFACE_MODE_RGMII:
+- ge = YT8511_DELAY_GE_TX_DIS;
+- fe = YT8511_DELAY_FE_TX_DIS;
++ ytphy_write_ext(phydev, 0xa000, 0);
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ ret = ytphy_config_init(phydev);
++#else
++ ret = genphy_config_init(phydev);
++#endif
++ if (ret < 0)
++ return ret;
++
++ /* disable auto sleep */
++ val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);
++ if (val < 0)
++ return val;
++
++ val &= (~BIT(YT8521_EN_SLEEP_SW_BIT));
++
++ ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val);
++ if (ret < 0)
++ return ret;
++
++ /* enable RXC clock when no wire plug */
++ ret = ytphy_write_ext(phydev, 0xa000, 0);
++ if (ret < 0)
++ return ret;
++
++ val = ytphy_read_ext(phydev, 0xc);
++ if (val < 0)
++ return val;
++ val &= ~(1 << 12);
++ ret = ytphy_write_ext(phydev, 0xc, val);
++ if (ret < 0)
++ return ret;
++
++ printk (KERN_INFO "yt8521_config_init, 8521 init call out.\n");
++ return ret;
++}
++
++/*
++ * for fiber mode, there is no 10M speed mode and
++ * this function is for this purpose.
++ */
++static int yt8521_adjust_status(struct phy_device *phydev, int val, int is_utp)
++{
++ int speed_mode, duplex;
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ int speed = -1;
++#else
++ int speed = SPEED_UNKNOWN;
++#endif
++
++ duplex = (val & YT8512_DUPLEX) >> YT8521_DUPLEX_BIT;
++ speed_mode = (val & YT8521_SPEED_MODE) >> YT8521_SPEED_MODE_BIT;
++ switch (speed_mode) {
++ case 0:
++ if (is_utp)
++ speed = SPEED_10;
+ break;
+- case PHY_INTERFACE_MODE_RGMII_RXID:
+- ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_DIS;
+- fe = YT8511_DELAY_FE_TX_DIS;
++ case 1:
++ speed = SPEED_100;
+ break;
+- case PHY_INTERFACE_MODE_RGMII_TXID:
+- ge = YT8511_DELAY_GE_TX_EN;
+- fe = YT8511_DELAY_FE_TX_EN;
++ case 2:
++ speed = SPEED_1000;
+ break;
+- case PHY_INTERFACE_MODE_RGMII_ID:
+- ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN;
+- fe = YT8511_DELAY_FE_TX_EN;
++ case 3:
+ break;
+- default: /* do not support other modes */
+- ret = -EOPNOTSUPP;
+- goto err_restore_page;
++ default:
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ speed = -1;
++#else
++ speed = SPEED_UNKNOWN;
++#endif
++ break;
++ }
++
++ phydev->speed = speed;
++ phydev->duplex = duplex;
++ //printk (KERN_INFO "yt8521_adjust_status call out,regval=0x%04x,mode=%s,speed=%dm...\n", val,is_utp?"utp":"fiber", phydev->speed);
++
++ return 0;
++}
++
++/*
++ * for fiber mode, when speed is 100M, there is no definition for autonegotiation, and
++ * this function handles this case and return 1 per linux kernel's polling.
++ */
++int yt8521_aneg_done (struct phy_device *phydev)
++{
++
++ //printk("yt8521_aneg_done callin,speed=%dm,linkmoded=%d\n", phydev->speed,link_mode_8521);
++
++ if((32 == link_mode_8521) && (SPEED_100 == phydev->speed))
++ {
++ return 1/*link_mode_8521*/;
++ }
++
++#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) )
++ return genphy_aneg_done(phydev);
++#else
++ return 1;
++#endif
++}
++
++static int yt8521_read_status(struct phy_device *phydev)
++{
++ int ret;
++ volatile int val, yt8521_fiber_latch_val, yt8521_fiber_curr_val;
++ volatile int link;
++ int link_utp = 0, link_fiber = 0;
++
++#if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER)
++ /* reading UTP */
++ ret = ytphy_write_ext(phydev, 0xa000, 0);
++ if (ret < 0)
++ return ret;
++
++ val = phy_read(phydev, REG_PHY_SPEC_STATUS);
++ if (val < 0)
++ return val;
++
++ link = val & (BIT(YT8521_LINK_STATUS_BIT));
++ if (link) {
++ link_utp = 1;
++ link_mode_8521 = 1;
++ yt8521_adjust_status(phydev, val, 1);
++ } else {
++ link_utp = 0;
++ }
++#endif //(YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER)
++
++#if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP)
++ /* reading Fiber */
++ ret = ytphy_write_ext(phydev, 0xa000, 2);
++ if (ret < 0)
++ return ret;
++
++ val = phy_read(phydev, REG_PHY_SPEC_STATUS);
++ if (val < 0)
++ return val;
++
++ //note: below debug information is used to check multiple PHy ports.
++ //printk (KERN_INFO "yt8521_read_status, fiber status=%04x,macbase=0x%08lx\n", val,(unsigned long)phydev->attached_dev);
++
++ /* for fiber, from 1000m to 100m, there is not link down from 0x11, and check reg 1 to identify such case
++ * this is important for Linux kernel for that, missing linkdown event will cause problem.
++ */
++ yt8521_fiber_latch_val = phy_read(phydev, MII_BMSR);
++ yt8521_fiber_curr_val = phy_read(phydev, MII_BMSR);
++ link = val & (BIT(YT8521_LINK_STATUS_BIT));
++ if((link) && (yt8521_fiber_latch_val != yt8521_fiber_curr_val))
++ {
++ link = 0;
++ printk (KERN_INFO "yt8521_read_status, fiber link down detect,latch=%04x,curr=%04x\n", yt8521_fiber_latch_val,yt8521_fiber_curr_val);
++ }
++
++ if (link) {
++ link_fiber = 1;
++ yt8521_adjust_status(phydev, val, 0);
++ link_mode_8521 = 32; //fiber mode
++
++
++ } else {
++ link_fiber = 0;
++ }
++#endif //(YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP)
++
++ if (link_utp || link_fiber) {
++ phydev->link = 1;
++ } else {
++ phydev->link = 0;
++ link_mode_8521 = 0;
++ }
++
++#if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER)
++ if (link_utp) {
++ ytphy_write_ext(phydev, 0xa000, 0);
+ }
++#endif
+
+- ret = __phy_modify(phydev, YT8511_PAGE, (YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN), ge);
++ //printk (KERN_INFO "yzhang..8521 read status call out,link=%d,linkmode=%d\n", phydev->link, link_mode_8521 );
++ return 0;
++}
++
++int yt8521_suspend(struct phy_device *phydev)
++{
++#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)
++ int value;
++
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ mutex_lock(&phydev->lock);
++#else
++ /* no need lock in 4.19 */
++#endif
++
++ ytphy_write_ext(phydev, 0xa000, 0);
++ value = phy_read(phydev, MII_BMCR);
++ phy_write(phydev, MII_BMCR, value | BMCR_PDOWN);
++
++ ytphy_write_ext(phydev, 0xa000, 2);
++ value = phy_read(phydev, MII_BMCR);
++ phy_write(phydev, MII_BMCR, value | BMCR_PDOWN);
++
++ ytphy_write_ext(phydev, 0xa000, 0);
++
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ mutex_unlock(&phydev->lock);
++#else
++ /* no need lock/unlock in 4.19 */
++#endif
++#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/
++
++ return 0;
++}
++
++int yt8521_resume(struct phy_device *phydev)
++{
++#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)
++ int value;
++ int ret;
++
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ mutex_lock(&phydev->lock);
++#else
++ /* no need lock/unlock in 4.19 */
++#endif
++
++ ytphy_write_ext(phydev, 0xa000, 0);
++ value = phy_read(phydev, MII_BMCR);
++ phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
++
++ /* disable auto sleep */
++ value = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);
++ if (value < 0)
++ return value;
++
++ value &= (~BIT(YT8521_EN_SLEEP_SW_BIT));
++ ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, value);
+ if (ret < 0)
+- goto err_restore_page;
++ return ret;
+
+- /* set clock mode to 125mhz */
+- ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_CLK_125M);
++ /* enable RXC clock when no wire plug */
++ value = ytphy_read_ext(phydev, 0xc);
++ if (value < 0)
++ return value;
++ value &= ~(1 << 12);
++ ret = ytphy_write_ext(phydev, 0xc, value);
+ if (ret < 0)
+- goto err_restore_page;
++ return ret;
++
++ ytphy_write_ext(phydev, 0xa000, 2);
++ value = phy_read(phydev, MII_BMCR);
++ phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
++
++#if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER)
++ ytphy_write_ext(phydev, 0xa000, 0);
++#endif
++
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ mutex_unlock(&phydev->lock);
++#else
++ /* no need lock/unlock in 4.19 */
++#endif
++#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/
++
++ return 0;
++}
+
+- /* fast ethernet delay is in a separate page */
+- ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_DELAY_DRIVE);
++
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++#else
++int yt8618_soft_reset(struct phy_device *phydev)
++{
++ int ret;
++
++ ytphy_write_ext(phydev, 0xa000, 0);
++ ret = genphy_soft_reset(phydev);
+ if (ret < 0)
+- goto err_restore_page;
++ return ret;
+
+- ret = __phy_modify(phydev, YT8511_PAGE, YT8511_DELAY_FE_TX_EN, fe);
++ return 0;
++}
++
++int yt8614_soft_reset(struct phy_device *phydev)
++{
++ int ret;
++
++ /* utp */
++ ytphy_write_ext(phydev, 0xa000, 0);
++ ret = genphy_soft_reset(phydev);
+ if (ret < 0)
+- goto err_restore_page;
++ return ret;
++
++ /* qsgmii */
++ ytphy_write_ext(phydev, 0xa000, 2);
++ ret = genphy_soft_reset(phydev);
++ if (ret < 0) {
++ ytphy_write_ext(phydev, 0xa000, 0); //back to utp mode
++ return ret;
++ }
++
++ /* sgmii */
++ ytphy_write_ext(phydev, 0xa000, 3);
++ ret = genphy_soft_reset(phydev);
++ if (ret < 0) {
++ ytphy_write_ext(phydev, 0xa000, 0); //back to utp mode
++ return ret;
++ }
+
+- /* leave pll enabled in sleep */
+- ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_SLEEP_CTRL);
++ return 0;
++}
++
++#endif
++
++static int yt8618_config_init(struct phy_device *phydev)
++{
++ int ret;
++ int val;
++
++ phydev->irq = PHY_POLL;
++
++ if(0xff == yt_mport_base_phy_addr)
++ /* by default, we think the first phy should be the base phy addr. for mul */
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ {
++ yt_mport_base_phy_addr = phydev->addr;
++ }else if (yt_mport_base_phy_addr > phydev->addr) {
++ printk (KERN_INFO "yzhang..8618 init, phy address mismatch, base=%d, cur=%d\n", yt_mport_base_phy_addr, phydev->addr);
++ }
++#else
++ {
++ yt_mport_base_phy_addr = phydev->mdio.addr;
++ }else if (yt_mport_base_phy_addr > phydev->mdio.addr) {
++ printk (KERN_INFO "yzhang..8618 init, phy address mismatch, base=%d, cur=%d\n", yt_mport_base_phy_addr, phydev->mdio.addr);
++ }
++#endif
++
++ ytphy_write_ext(phydev, 0xa000, 0);
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ ret = ytphy_config_init(phydev);
++#else
++ ret = genphy_config_init(phydev);
++#endif
+ if (ret < 0)
+- goto err_restore_page;
++ return ret;
+
+- ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_PLLON_SLP);
++ /* for utp to optimize signal */
++ ret = ytphy_write_ext(phydev, 0x41, 0x33);
++ if (ret < 0)
++ return ret;
++ ret = ytphy_write_ext(phydev, 0x42, 0x66);
+ if (ret < 0)
+- goto err_restore_page;
++ return ret;
++ ret = ytphy_write_ext(phydev, 0x43, 0xaa);
++ if (ret < 0)
++ return ret;
++ ret = ytphy_write_ext(phydev, 0x44, 0xd0d);
++ if (ret < 0)
++ return ret;
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ if((phydev->addr > yt_mport_base_phy_addr) && ((2 == phydev->addr - yt_mport_base_phy_addr) || (5 == phydev->addr - yt_mport_base_phy_addr)))
++#else
++ if((phydev->mdio.addr > yt_mport_base_phy_addr) && ((2 == phydev->mdio.addr - yt_mport_base_phy_addr) || (5 == phydev->mdio.addr - yt_mport_base_phy_addr)))
++#endif
++ {
++ ret = ytphy_write_ext(phydev, 0x44, 0x2929);
++ if (ret < 0)
++ return ret;
++ }
++
++ val = phy_read(phydev, MII_BMCR);
++ phy_write(phydev, MII_BMCR, val | BMCR_RESET);
+
+-err_restore_page:
+- return phy_restore_page(phydev, oldpage, ret);
++ printk (KERN_INFO "yt8618_config_init call out.\n");
++ return ret;
+ }
+
+-static struct phy_driver motorcomm_phy_drvs[] = {
++static int yt8614_config_init(struct phy_device *phydev)
++{
++ int ret = 0;
++
++ phydev->irq = PHY_POLL;
++
++ if(0xff == yt_mport_base_phy_addr_8614)
++ /* by default, we think the first phy should be the base phy addr. for mul */
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
+ {
+- PHY_ID_MATCH_EXACT(PHY_ID_YT8511),
++ yt_mport_base_phy_addr_8614 = (unsigned int)phydev->addr;
++ }else if (yt_mport_base_phy_addr_8614 > (unsigned int)phydev->addr) {
++ printk (KERN_INFO "yzhang..8618 init, phy address mismatch, base=%u, cur=%d\n", yt_mport_base_phy_addr_8614, phydev->addr);
++ }
++#else
++ {
++ yt_mport_base_phy_addr_8614 = (unsigned int)phydev->mdio.addr;
++ }else if (yt_mport_base_phy_addr_8614 > (unsigned int)phydev->mdio.addr) {
++ printk (KERN_INFO "yzhang..8618 init, phy address mismatch, base=%u, cur=%d\n", yt_mport_base_phy_addr_8614, phydev->mdio.addr);
++ }
++#endif
++ return ret;
++}
++
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++#define yt8614_get_port_from_phydev(phydev) ((0xff == yt_mport_base_phy_addr_8614) && (yt_mport_base_phy_addr_8614 <= (phydev)->addr) ? 0 : (unsigned int)((phydev)->addr) - yt_mport_base_phy_addr_8614)
++#else
++#define yt8614_get_port_from_phydev(phydev) ((0xff == yt_mport_base_phy_addr_8614) && (yt_mport_base_phy_addr_8614 <= (phydev)->mdio.addr) ? 0 : (unsigned int)((phydev)->mdio.addr) - yt_mport_base_phy_addr_8614)
++#endif
++
++int yt8618_aneg_done (struct phy_device *phydev)
++{
++
++ return genphy_aneg_done(phydev);
++}
++
++int yt8614_aneg_done (struct phy_device *phydev)
++{
++ int port = yt8614_get_port_from_phydev(phydev);
++
++ /*it should be used for 8614 fiber*/
++ if((32 == link_mode_8614[port]) && (SPEED_100 == phydev->speed))
++ {
++ return 1;
++ }
++
++ return genphy_aneg_done(phydev);
++}
++
++static int yt8614_read_status(struct phy_device *phydev)
++{
++ //int i;
++ int ret;
++ volatile int val, yt8614_fiber_latch_val, yt8614_fiber_curr_val;
++ volatile int link;
++ int link_utp = 0, link_fiber = 0;
++ int port = yt8614_get_port_from_phydev(phydev);
++
++#if (YT8614_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER)
++ /* switch to utp and reading regs */
++ ret = ytphy_write_ext(phydev, 0xa000, 0);
++ if (ret < 0)
++ return ret;
++
++ val = phy_read(phydev, REG_PHY_SPEC_STATUS);
++ if (val < 0)
++ return val;
++
++ link = val & (BIT(YT8521_LINK_STATUS_BIT));
++ if (link) {
++ link_utp = 1;
++ // here is same as 8521 and re-use the function;
++ yt8521_adjust_status(phydev, val, 1);
++ } else {
++ link_utp = 0;
++ }
++#endif //(YT8614_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER)
++
++#if (YT8614_PHY_MODE_CURR != YT8521_PHY_MODE_UTP)
++ /* reading Fiber/sgmii */
++ ret = ytphy_write_ext(phydev, 0xa000, 3);
++ if (ret < 0)
++ return ret;
++
++ val = phy_read(phydev, REG_PHY_SPEC_STATUS);
++ if (val < 0)
++ return val;
++
++ //printk (KERN_INFO "yzhang..8614 read fiber status=%04x,macbase=0x%08lx\n", val,(unsigned long)phydev->attached_dev);
++
++ /* for fiber, from 1000m to 100m, there is not link down from 0x11, and check reg 1 to identify such case */
++ yt8614_fiber_latch_val = phy_read(phydev, MII_BMSR);
++ yt8614_fiber_curr_val = phy_read(phydev, MII_BMSR);
++ link = val & (BIT(YT8521_LINK_STATUS_BIT));
++ if((link) && (yt8614_fiber_latch_val != yt8614_fiber_curr_val))
++ {
++ link = 0;
++ printk (KERN_INFO "yt8614_read_status, fiber link down detect,latch=%04x,curr=%04x\n", yt8614_fiber_latch_val,yt8614_fiber_curr_val);
++ }
++
++ if (link) {
++ link_fiber = 1;
++ yt8521_adjust_status(phydev, val, 0);
++ link_mode_8614[port] = 32; //fiber mode
++
++
++ } else {
++ link_fiber = 0;
++ }
++#endif //(YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP)
++
++ if (link_utp || link_fiber) {
++ phydev->link = 1;
++ } else {
++ phydev->link = 0;
++ link_mode_8614[port] = 0;
++ }
++
++#if (YT8614_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER)
++ if (link_utp) {
++ ytphy_write_ext(phydev, 0xa000, 0);
++ }
++#endif
++ //printk (KERN_INFO "yt8614_read_status call out,link=%d,linkmode=%d\n", phydev->link, link_mode_8614[port] );
++
++ return 0;
++}
++
++static int yt8618_read_status(struct phy_device *phydev)
++{
++ int ret;
++ volatile int val; //maybe for 8614 yt8521_fiber_latch_val, yt8521_fiber_curr_val;
++ volatile int link;
++ int link_utp = 0, link_fiber = 0;
++
++ /* switch to utp and reading regs */
++ ret = ytphy_write_ext(phydev, 0xa000, 0);
++ if (ret < 0)
++ return ret;
++
++ val = phy_read(phydev, REG_PHY_SPEC_STATUS);
++ if (val < 0)
++ return val;
++
++ link = val & (BIT(YT8521_LINK_STATUS_BIT));
++ if (link) {
++ link_utp = 1;
++ yt8521_adjust_status(phydev, val, 1);
++ } else {
++ link_utp = 0;
++ }
++
++ if (link_utp || link_fiber) {
++ phydev->link = 1;
++ } else {
++ phydev->link = 0;
++ }
++
++ return 0;
++}
++
++int yt8618_suspend(struct phy_device *phydev)
++{
++#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)
++ int value;
++
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ mutex_lock(&phydev->lock);
++#else
++ /* no need lock in 4.19 */
++#endif
++
++ ytphy_write_ext(phydev, 0xa000, 0);
++ value = phy_read(phydev, MII_BMCR);
++ phy_write(phydev, MII_BMCR, value | BMCR_PDOWN);
++
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ mutex_unlock(&phydev->lock);
++#else
++ /* no need lock/unlock in 4.19 */
++#endif
++#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/
++
++ return 0;
++}
++
++int yt8618_resume(struct phy_device *phydev)
++{
++#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)
++ int value;
++
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ mutex_lock(&phydev->lock);
++#else
++ /* no need lock/unlock in 4.19 */
++#endif
++
++ ytphy_write_ext(phydev, 0xa000, 0);
++ value = phy_read(phydev, MII_BMCR);
++ phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
++
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ mutex_unlock(&phydev->lock);
++#else
++ /* no need lock/unlock in 4.19 */
++#endif
++#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/
++
++ return 0;
++}
++
++int yt8614_suspend(struct phy_device *phydev)
++{
++#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)
++ int value;
++
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ mutex_lock(&phydev->lock);
++#else
++ /* no need lock in 4.19 */
++#endif
++
++ ytphy_write_ext(phydev, 0xa000, 0);
++ value = phy_read(phydev, MII_BMCR);
++ phy_write(phydev, MII_BMCR, value | BMCR_PDOWN);
++
++ ytphy_write_ext(phydev, 0xa000, 3);
++ value = phy_read(phydev, MII_BMCR);
++ phy_write(phydev, MII_BMCR, value | BMCR_PDOWN);
++
++ ytphy_write_ext(phydev, 0xa000, 0);
++
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ mutex_unlock(&phydev->lock);
++#else
++ /* no need lock/unlock in 4.19 */
++#endif
++#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/
++
++ return 0;
++}
++
++int yt8614_resume(struct phy_device *phydev)
++{
++#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)
++ int value;
++
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ mutex_lock(&phydev->lock);
++#else
++ /* no need lock/unlock in 4.19 */
++#endif
++
++ ytphy_write_ext(phydev, 0xa000, 0);
++ value = phy_read(phydev, MII_BMCR);
++ phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
++
++ ytphy_write_ext(phydev, 0xa000, 3);
++ value = phy_read(phydev, MII_BMCR);
++ phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
++
++ ytphy_write_ext(phydev, 0xa000, 0);
++
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ mutex_unlock(&phydev->lock);
++#else
++ /* no need lock/unlock in 4.19 */
++#endif
++#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/
++
++ return 0;
++}
++
++
++static struct phy_driver ytphy_drvs[] = {
++ {
++ .phy_id = PHY_ID_YT8010,
++ .name = "YT8010 Automotive Ethernet",
++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )
++ .features = PHY_BASIC_FEATURES,
++ .flags = PHY_HAS_INTERRUPT,
++#endif
++ .config_aneg = yt8010_config_aneg,
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ .config_init = ytphy_config_init,
++#else
++ .config_init = genphy_config_init,
++#endif
++ .read_status = genphy_read_status,
++ }, {
++ .phy_id = PHY_ID_YT8510,
++ .name = "YT8510 100/10Mb Ethernet",
++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )
++ .features = PHY_BASIC_FEATURES,
++ .flags = PHY_HAS_INTERRUPT,
++#endif
++ .config_aneg = genphy_config_aneg,
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ .config_init = ytphy_config_init,
++#else
++ .config_init = genphy_config_init,
++#endif
++ .read_status = genphy_read_status,
++ }, {
++ .phy_id = PHY_ID_YT8511,
+ .name = "YT8511 Gigabit Ethernet",
++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )
++ .features = PHY_GBIT_FEATURES,
++ .flags = PHY_HAS_INTERRUPT,
++#endif
++ .config_aneg = genphy_config_aneg,
++#if GMAC_CLOCK_INPUT_NEEDED
+ .config_init = yt8511_config_init,
++#else
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ .config_init = ytphy_config_init,
++#else
++ .config_init = genphy_config_init,
++#endif
++#endif
++ .read_status = genphy_read_status,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+- .read_page = yt8511_read_page,
+- .write_page = yt8511_write_page,
+- },
++ }, {
++ .phy_id = PHY_ID_YT8512,
++ .name = "YT8512 Ethernet",
++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )
++ .features = PHY_BASIC_FEATURES,
++ .flags = PHY_HAS_INTERRUPT,
++#endif
++ .config_aneg = genphy_config_aneg,
++ .config_init = yt8512_config_init,
++ .read_status = yt8512_read_status,
++ .suspend = genphy_suspend,
++ .resume = genphy_resume,
++ }, {
++ .phy_id = PHY_ID_YT8512B,
++ .name = "YT8512B Ethernet",
++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )
++ .features = PHY_BASIC_FEATURES,
++ .flags = PHY_HAS_INTERRUPT,
++#endif
++ .config_aneg = genphy_config_aneg,
++ .config_init = yt8512_config_init,
++ .read_status = yt8512_read_status,
++ .suspend = genphy_suspend,
++ .resume = genphy_resume,
++ }, {
++ .phy_id = PHY_ID_YT8521,
++ .name = "YT8521 Ethernet",
++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )
++ .features = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES,
++#endif
++ .flags = PHY_POLL,
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++#else
++ .soft_reset = yt8521_soft_reset,
++#endif
++ .config_aneg = genphy_config_aneg,
++#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) )
++ .aneg_done = yt8521_aneg_done,
++#endif
++ .config_init = yt8521_config_init,
++ .read_status = yt8521_read_status,
++ .suspend = yt8521_suspend,
++ .resume = yt8521_resume,
++#if (YTPHY_ENABLE_WOL)
++ .get_wol = &ytphy_get_wol,
++ .set_wol = &ytphy_set_wol,
++#endif
++ },{
++ /* same as 8521 */
++ .phy_id = PHY_ID_YT8531S,
++ .name = "YT8531S Ethernet",
++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )
++ .features = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES,
++#endif
++ .flags = PHY_POLL,
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++#else
++ .soft_reset = yt8521_soft_reset,
++#endif
++ .config_aneg = genphy_config_aneg,
++#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) )
++ .aneg_done = yt8521_aneg_done,
++#endif
++ .config_init = yt8521_config_init,
++ .read_status = yt8521_read_status,
++ .suspend = yt8521_suspend,
++ .resume = yt8521_resume,
++#if (YTPHY_ENABLE_WOL)
++ .get_wol = &ytphy_get_wol,
++ .set_wol = &ytphy_set_wol,
++#endif
++ }, {
++ /* same as 8511 */
++ .phy_id = PHY_ID_YT8531,
++ .name = "YT8531 Gigabit Ethernet",
++ .phy_id_mask = MOTORCOMM_PHY_ID_MASK,
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )
++ .features = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES,
++ .flags = PHY_HAS_INTERRUPT,
++#endif
++ .config_aneg = genphy_config_aneg,
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++ .config_init = ytphy_config_init,
++#else
++ .config_init = genphy_config_init,
++#endif
++ .read_status = genphy_read_status,
++ .suspend = genphy_suspend,
++ .resume = genphy_resume,
++#if (YTPHY_ENABLE_WOL)
++ .get_wol = &ytphy_get_wol,
++ .set_wol = &ytphy_set_wol,
++#endif
++ }, {
++ .phy_id = PHY_ID_YT8618,
++ .name = "YT8618 Ethernet",
++ .phy_id_mask = MOTORCOMM_MPHY_ID_MASK,
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )
++ .features = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES,
++#endif
++ .flags = PHY_POLL,
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++#else
++ .soft_reset = yt8618_soft_reset,
++#endif
++ .config_aneg = genphy_config_aneg,
++#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) )
++ .aneg_done = yt8618_aneg_done,
++#endif
++ .config_init = yt8618_config_init,
++ .read_status = yt8618_read_status,
++ .suspend = yt8618_suspend,
++ .resume = yt8618_resume,
++ }, {
++ .phy_id = PHY_ID_YT8614,
++ .name = "YT8614 Ethernet",
++ .phy_id_mask = MOTORCOMM_MPHY_ID_MASK_8614,
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )
++ .features = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES,
++#endif
++ .flags = PHY_POLL,
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++#else
++ .soft_reset = yt8614_soft_reset,
++#endif
++ .config_aneg = genphy_config_aneg,
++#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) )
++ .aneg_done = yt8614_aneg_done,
++#endif
++ .config_init = yt8614_config_init,
++ .read_status = yt8614_read_status,
++ .suspend = yt8614_suspend,
++ .resume = yt8614_resume,
++ },
+ };
+
+-module_phy_driver(motorcomm_phy_drvs);
++#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )
++static int ytphy_drivers_register(struct phy_driver* phy_drvs, int size)
++{
++ int i, j;
++ int ret;
++
++ for (i = 0; i < size; i++) {
++ ret = phy_driver_register(&phy_drvs[i]);
++ if (ret)
++ goto err;
++ }
++
++ return 0;
++
++err:
++ for (j = 0; j < i; j++)
++ phy_driver_unregister(&phy_drvs[j]);
++
++ return ret;
++}
++
++static void ytphy_drivers_unregister(struct phy_driver* phy_drvs, int size)
++{
++ int i;
++
++ for (i = 0; i < size; i++) {
++ phy_driver_unregister(&phy_drvs[i]);
++ }
++}
++
++static int __init ytphy_init(void)
++{
++ printk("motorcomm phy register\n");
++ return ytphy_drivers_register(ytphy_drvs, ARRAY_SIZE(ytphy_drvs));
++}
++
++static void __exit ytphy_exit(void)
++{
++ printk("motorcomm phy unregister\n");
++ ytphy_drivers_unregister(ytphy_drvs, ARRAY_SIZE(ytphy_drvs));
++}
++
++module_init(ytphy_init);
++module_exit(ytphy_exit);
++#else
++/* for linux 4.x */
++module_phy_driver(ytphy_drvs);
++#endif
+
+ MODULE_DESCRIPTION("Motorcomm PHY driver");
+-MODULE_AUTHOR("Peter Geis");
++MODULE_AUTHOR("Leilei Zhao");
+ MODULE_LICENSE("GPL");
+
+-static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
+- { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) },
+- { /* sentinal */ }
++static struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
++ { PHY_ID_YT8010, MOTORCOMM_PHY_ID_MASK },
++ { PHY_ID_YT8510, MOTORCOMM_PHY_ID_MASK },
++ { PHY_ID_YT8511, MOTORCOMM_PHY_ID_MASK },
++ { PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK },
++ { PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK },
++ { PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK },
++ { PHY_ID_YT8531S, MOTORCOMM_PHY_ID_8531_MASK },
++ { PHY_ID_YT8531, MOTORCOMM_PHY_ID_8531_MASK },
++ { PHY_ID_YT8618, MOTORCOMM_MPHY_ID_MASK },
++ { PHY_ID_YT8614, MOTORCOMM_MPHY_ID_MASK_8614 },
++ { }
+ };
+
+ MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);
++
++
+--- /dev/null
++++ b/drivers/net/phy/yt8614-phy.h
+@@ -0,0 +1,491 @@
++#ifndef _PHY_H_
++#define _PHY_H_
++
++
++/* configuration for driver */
++
++#define YT8614_MAX_LPORT_ID 3
++
++#define YT8614_PHY_MODE_FIBER 1 //fiber mode only
++#define YT8614_PHY_MODE_UTP 2 //utp mode only
++#define YT8614_PHY_MODE_POLL 3 //fiber and utp, poll mode
++
++/* please make choice according to system design
++ * for Fiber only system, please define YT8614_PHY_MODE_CURR 1
++ * for UTP only system, please define YT8614_PHY_MODE_CURR 2
++ * for combo system, please define YT8614_PHY_MODE_CURR 3
++ */
++#define YT8614_PHY_MODE_CURR 3
++
++
++
++/* pls dont modify below lines */
++
++#define PHY_ID_YT8614 0x4F51E899 //serdes
++#define MOTORCOMM_MPHY_ID_MASK_8614 0xffffffff
++
++#ifndef BOOL
++#define BOOL unsigned int
++#endif
++
++#ifndef FALSE
++#define FALSE 0
++#endif
++
++#ifndef TRUE
++#define TRUE 1
++#endif
++
++#ifndef SPEED_1000M
++#define SPEED_1000M 2
++#endif
++#ifndef SPEED_100M
++#define SPEED_100M 1
++#endif
++#ifndef SPEED_10M
++#define SPEED_10M 0
++#endif
++
++#ifndef SPEED_UNKNOWN
++#define SPEED_UNKNOWN 0xffff
++#endif
++
++#ifndef DUPLEX_FULL
++#define DUPLEX_FULL 1
++#endif
++#ifndef DUPLEX_HALF
++#define DUPLEX_HALF 0
++#endif
++
++#ifndef BIT
++#define BIT(n) (0x1<<(n))
++#endif
++#ifndef s32
++typedef int s32;
++typedef unsigned int u32;
++typedef unsigned short u16;
++typedef unsigned char u8;
++#endif
++
++#ifndef REG_PHY_SPEC_STATUS
++#define REG_PHY_SPEC_STATUS 0x11
++#define REG_DEBUG_ADDR_OFFSET 0x1e
++#define REG_DEBUG_DATA 0x1f
++#endif
++
++/**********YT8614************************************************/
++
++#define YT8614_SMI_SEL_PHY 0x0
++#define YT8614_SMI_SEL_SDS_QSGMII 0x02
++#define YT8614_SMI_SEL_SDS_SGMII 0x03
++
++/* yt8614 register type */
++#define YT8614_TYPE_COMMON 0x01
++#define YT8614_TYPE_UTP_MII 0x02
++#define YT8614_TYPE_UTP_EXT 0x03
++#define YT8614_TYPE_LDS_MII 0x04
++#define YT8614_TYPE_UTP_MMD 0x05
++#define YT8614_TYPE_SDS_QSGMII_MII 0x06
++#define YT8614_TYPE_SDS_SGMII_MII 0x07
++#define YT8614_TYPE_SDS_QSGMII_EXT 0x08
++#define YT8614_TYPE_SDS_SGMII_EXT 0x09
++
++/* YT8614 extended common register */
++#define YT8614_REG_COM_SMI_MUX 0xA000
++#define YT8614_REG_COM_SLED_CFG0 0xA001
++#define YT8614_REG_COM_PHY_ID 0xA002
++#define YT8614_REG_COM_CHIP_VER 0xA003
++#define YT8614_REG_COM_SLED_CFG 0xA004
++#define YT8614_REG_COM_MODE_CHG_RESET 0xA005
++#define YT8614_REG_COM_SYNCE0_CFG 0xA006
++#define YT8614_REG_COM_CHIP_MODE 0xA007
++
++#define YT8614_REG_COM_HIDE_SPEED 0xA009
++
++#define YT8614_REG_COM_SYNCE1_CFG 0xA00E
++
++#define YT8614_REG_COM_HIDE_FIBER_MODE 0xA019
++
++
++#define YT8614_REG_COM_HIDE_SEL1 0xA054
++#define YT8614_REG_COM_HIDE_LED_CFG2 0xB8
++#define YT8614_REG_COM_HIDE_LED_CFG3 0xB9
++#define YT8614_REG_COM_HIDE_LED_CFG5 0xBB
++
++#define YT8614_REG_COM_HIDE_LED_CFG4 0xBA //not used currently
++
++#if 0
++#define YT8614_REG_COM_HIDE_LED12_CFG 0xA060 //not used currently
++#define YT8614_REG_COM_HIDE_LED13_CFG 0xA061
++#define YT8614_REG_COM_HIDE_LED14_CFG 0xA062
++#define YT8614_REG_COM_HIDE_LED15_CFG 0xA063
++#define YT8614_REG_COM_HIDE_LED16_CFG 0xA064
++#define YT8614_REG_COM_HIDE_LED17_CFG 0xA065
++#define YT8614_REG_COM_HIDE_LED18_CFG 0xA066
++#define YT8614_REG_COM_HIDE_LED19_CFG 0xA067
++#define YT8614_REG_COM_HIDE_LED20_CFG 0xA068
++#define YT8614_REG_COM_HIDE_LED21_CFG 0xA069
++#define YT8614_REG_COM_HIDE_LED22_CFG 0xA06A
++#define YT8614_REG_COM_HIDE_LED23_CFG 0xA06B
++#define YT8614_REG_COM_HIDE_LED24_CFG 0xA06C
++#define YT8614_REG_COM_HIDE_LED25_CFG 0xA06D
++#define YT8614_REG_COM_HIDE_LED26_CFG 0xA06E
++#define YT8614_REG_COM_HIDE_LED27_CFG 0xA06F
++#endif
++
++#define YT8614_REG_COM_HIDE_LED28_CFG 0xA070
++#define YT8614_REG_COM_HIDE_LED29_CFG 0xA071
++#define YT8614_REG_COM_HIDE_LED30_CFG 0xA072
++#define YT8614_REG_COM_HIDE_LED31_CFG 0xA073
++#define YT8614_REG_COM_HIDE_LED32_CFG 0xA074
++#define YT8614_REG_COM_HIDE_LED33_CFG 0xA075
++#define YT8614_REG_COM_HIDE_LED34_CFG 0xA076
++#define YT8614_REG_COM_HIDE_LED35_CFG 0xA077
++
++#define YT8614_REG_COM_PKG_CFG0 0xA0A0
++#define YT8614_REG_COM_PKG_CFG1 0xA0A1
++#define YT8614_REG_COM_PKG_CFG2 0xA0A2
++#define YT8614_REG_COM_PKG_RX_VALID0 0xA0A3
++#define YT8614_REG_COM_PKG_RX_VALID1 0xA0A4
++#define YT8614_REG_COM_PKG_RX_OS0 0xA0A5
++#define YT8614_REG_COM_PKG_RX_OS1 0xA0A6
++#define YT8614_REG_COM_PKG_RX_US0 0xA0A7
++#define YT8614_REG_COM_PKG_RX_US1 0xA0A8
++#define YT8614_REG_COM_PKG_RX_ERR 0xA0A9
++#define YT8614_REG_COM_PKG_RX_OS_BAD 0xA0AA
++#define YT8614_REG_COM_PKG_RX_FRAG 0xA0AB
++#define YT8614_REG_COM_PKG_RX_NOSFD 0xA0AC
++#define YT8614_REG_COM_PKG_TX_VALID0 0xA0AD
++#define YT8614_REG_COM_PKG_TX_VALID1 0xA0AE
++#define YT8614_REG_COM_PKG_TX_OS0 0xA0AF
++
++#define YT8614_REG_COM_PKG_TX_OS1 0xA0B0
++#define YT8614_REG_COM_PKG_TX_US0 0xA0B1
++#define YT8614_REG_COM_PKG_TX_US1 0xA0B2
++#define YT8614_REG_COM_PKG_TX_ERR 0xA0B3
++#define YT8614_REG_COM_PKG_TX_OS_BAD 0xA0B4
++#define YT8614_REG_COM_PKG_TX_FRAG 0xA0B5
++#define YT8614_REG_COM_PKG_TX_NOSFD 0xA0B6
++#define YT8614_REG_COM_PKG_CFG3 0xA0B7
++#define YT8614_REG_COM_PKG_AZ_CFG 0xA0B8
++#define YT8614_REG_COM_PKG_DA_SA_CFG3 0xA0B9
++
++#define YT8614_REG_COM_MANU_HW_RESET 0xA0C0
++
++/* YT8614 UTP MII register: same as generic phy register definitions */
++#define REG_MII_BMCR 0x00 /* Basic mode control register */
++#define REG_MII_BMSR 0x01 /* Basic mode status register */
++#define REG_MII_PHYSID1 0x02 /* PHYS ID 1 */
++#define REG_MII_PHYSID2 0x03 /* PHYS ID 2 */
++#define REG_MII_ADVERTISE 0x04 /* Advertisement control reg */
++#define REG_MII_LPA 0x05 /* Link partner ability reg */
++#define REG_MII_EXPANSION 0x06 /* Expansion register */
++#define REG_MII_NEXT_PAGE 0x07 /* Next page register */
++#define REG_MII_LPR_NEXT_PAGE 0x08 /* LPR next page register */
++#define REG_MII_CTRL1000 0x09 /* 1000BASE-T control */
++#define REG_MII_STAT1000 0x0A /* 1000BASE-T status */
++
++#define REG_MII_MMD_CTRL 0x0D /* MMD access control register */
++#define REG_MII_MMD_DATA 0x0E /* MMD access data register */
++
++#define REG_MII_ESTATUS 0x0F /* Extended Status */
++#define REG_MII_SPEC_CTRL 0x10 /* PHY specific func control */
++#define REG_MII_SPEC_STATUS 0x11 /* PHY specific status */
++#define REG_MII_INT_MASK 0x12 /* Interrupt mask register */
++#define REG_MII_INT_STATUS 0x13 /* Interrupt status register */
++#define REG_MII_DOWNG_CTRL 0x14 /* Speed auto downgrade control*/
++#define REG_MII_RERRCOUNTER 0x15 /* Receive error counter */
++
++#define REG_MII_EXT_ADDR 0x1E /* Extended reg's address */
++#define REG_MII_EXT_DATA 0x1F /* Extended reg's date */
++
++#ifndef MII_BMSR
++#define MII_BMSR REG_MII_BMSR
++#endif
++
++#ifndef YT8614_SPEED_MODE_BIT
++#define YT8614_SPEED_MODE 0xc000
++#define YT8614_DUPLEX 0x2000
++#define YT8614_SPEED_MODE_BIT 14
++#define YT8614_DUPLEX_BIT 13
++#define YT8614_LINK_STATUS_BIT 10
++
++#endif
++
++#define YT8614_REG_COM_HIDE_SPEED_CMB_PRI 0x2000
++
++/* YT8614 UTP MMD register */
++#define YT8614_REG_UTP_MMD_CTRL1 0x00 /* PCS control 1 register */
++#define YT8614_REG_UTP_MMD_STATUS1 0x01 /* PCS status 1 register */
++#define YT8614_REG_UTP_MMD_EEE_CTRL 0x14 /* EEE control and capability */
++#define YT8614_REG_UTP_MMD_EEE_WK_ERR_CNT 0x16 /* EEE wake error counter */
++#define YT8614_REG_UTP_MMD_EEE_LOCAL_ABI 0x3C /* local device EEE ability */
++#define YT8614_REG_UTP_MMD_EEE_LP_ABI 0x3D /* link partner EEE ability */
++#define YT8614_REG_UTP_MMD_EEE_AUTONEG_RES 0x8000 /* autoneg result of EEE */
++
++/* YT8614 UTP EXT register */
++#define YT8614_REG_UTP_EXT_LPBK 0x0A
++#define YT8614_REG_UTP_EXT_SLEEP_CTRL1 0x27
++#define YT8614_REG_UTP_EXT_DEBUG_MON1 0x5A
++#define YT8614_REG_UTP_EXT_DEBUG_MON2 0x5B
++#define YT8614_REG_UTP_EXT_DEBUG_MON3 0x5C
++#define YT8614_REG_UTP_EXT_DEBUG_MON4 0x5D
++
++/* YT8614 SDS(1.25G/5G) MII register: same as YT8521S */
++#define REG_SDS_BMCR 0x00 /* Basic mode control register */
++#define REG_SDS_BMSR 0x01 /* Basic mode status register */
++#define REG_SDS_PHYSID1 0x02 /* PHYS ID 1 */
++#define REG_SDS_PHYSID2 0x03 /* PHYS ID 2 */
++#define REG_SDS_ADVERTISE 0x04 /* Advertisement control reg */
++#define REG_SDS_LPA 0x05 /* Link partner ability reg */
++#define REG_SDS_EXPANSION 0x06 /* Expansion register */
++#define REG_SDS_NEXT_PAGE 0x07 /* Next page register */
++#define REG_SDS_LPR_NEXT_PAGE 0x08 /* LPR next page register */
++
++#define REG_SDS_ESTATUS 0x0F /* Extended Status */
++#define REG_SDS_SPEC_STATUS 0x11 /* SDS specific status */
++
++#define REG_SDS_100FX_CFG 0x14 /* 100fx cfg */
++#define REG_SDS_RERRCOUNTER 0x15 /* Receive error counter */
++#define REG_SDS_LINT_FAIL_CNT 0x16 /* Lint fail counter mon */
++
++/* YT8614 SDS(5G) EXT register */
++#define YT8614_REG_QSGMII_EXT_ANA_DIG_CFG 0x02 /* sds analog digital interface cfg */
++#define YT8614_REG_QSGMII_EXT_PRBS_CFG1 0x05 /* sds prbs cfg1 */
++#define YT8614_REG_QSGMII_EXT_PRBS_CFG2_1 0x06 /* sds prbs cfg2 */
++#define YT8614_REG_QSGMII_EXT_PRBS_CFG2_2 0x07 /* sds prbs cfg2 */
++#define YT8614_REG_QSGMII_EXT_PRBS_MON1 0x08 /* sds prbs mon1 */
++#define YT8614_REG_QSGMII_EXT_PRBS_MON2 0x09 /* sds prbs mon2 */
++#define YT8614_REG_QSGMII_EXT_PRBS_MON3 0x0A /* sds prbs mon3 */
++#define YT8614_REG_QSGMII_EXT_PRBS_MON4 0x0B /* sds prbs mon4 */
++#define YT8614_REG_QSGMII_EXT_PRBS_MON5 0x0C /* sds prbs mon5 */
++#define YT8614_REG_QSGMII_EXT_ANA_CFG2 0xA1 /* Analog cfg2 */
++
++/* YT8614 SDS(1.25G) EXT register */
++#define YT8614_REG_SGMII_EXT_PRBS_CFG1 0x05 /* sds prbs cfg1 */
++#define YT8614_REG_SGMII_EXT_PRBS_CFG2 0x06 /* sds prbs cfg2 */
++#define YT8614_REG_SGMII_EXT_PRBS_MON1 0x08 /* sds prbs mon1 */
++#define YT8614_REG_SGMII_EXT_PRBS_MON2 0x09 /* sds prbs mon2 */
++#define YT8614_REG_SGMII_EXT_PRBS_MON3 0x0A /* sds prbs mon3 */
++#define YT8614_REG_SGMII_EXT_PRBS_MON4 0x0B /* sds prbs mon4 */
++#define YT8614_REG_SGMII_EXT_PRBS_MON5 0x0C /* sds prbs mon5 */
++#define YT8614_REG_SGMII_EXT_ANA_CFG2 0xA1 /* Analog cfg2 */
++#define YT8614_REG_SGMII_EXT_HIDE_AUTO_SEN 0xA5 /* Fiber auto sensing */
++
++////////////////////////////////////////////////////////////////////
++#define YT8614_MMD_DEV_ADDR1 0x1
++#define YT8614_MMD_DEV_ADDR3 0x3
++#define YT8614_MMD_DEV_ADDR7 0x7
++#define YT8614_MMD_DEV_ADDR_NONE 0xFF
++
++/**********YT8521S************************************************/
++/* Basic mode control register(0x00) */
++#define BMCR_RESV 0x003f /* Unused... */
++#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
++#define BMCR_CTST 0x0080 /* Collision test */
++#define BMCR_FULLDPLX 0x0100 /* Full duplex */
++#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
++#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
++#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
++#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
++#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
++#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
++#define BMCR_RESET 0x8000 /* Reset the DP83840 */
++
++/* Basic mode status register(0x01) */
++#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
++#define BMSR_JCD 0x0002 /* Jabber detected */
++#define BMSR_LSTATUS 0x0004 /* Link status */
++#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
++#define BMSR_RFAULT 0x0010 /* Remote fault detected */
++#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
++#define BMSR_RESV 0x00c0 /* Unused... */
++#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
++#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
++#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
++#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
++#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
++#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
++#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
++#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
++
++/* Advertisement control register(0x04) */
++#define ADVERTISE_SLCT 0x001f /* Selector bits */
++#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
++#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
++#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
++#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
++#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
++#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
++#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
++#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
++#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
++#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
++#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
++#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
++#define ADVERTISE_RESV 0x1000 /* Unused... */
++#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
++#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
++#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
++
++#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA)
++#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
++ ADVERTISE_100HALF | ADVERTISE_100FULL)
++
++/* Link partner ability register(0x05) */
++#define LPA_SLCT 0x001f /* Same as advertise selector */
++#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
++#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
++#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
++#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
++#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
++#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
++#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
++#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym */
++#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
++#define LPA_PAUSE_CAP 0x0400 /* Can pause */
++#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
++#define LPA_RESV 0x1000 /* Unused... */
++#define LPA_RFAULT 0x2000 /* Link partner faulted */
++#define LPA_LPACK 0x4000 /* Link partner acked us */
++#define LPA_NPAGE 0x8000 /* Next page bit */
++
++/* 1000BASE-T Control register(0x09) */
++#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
++#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
++#define CTL1000_AS_MASTER 0x0800
++#define CTL1000_ENABLE_MASTER 0x1000
++
++/* 1000BASE-T Status register(0x0A) */
++#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
++#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
++#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
++#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
++
++/**********YT8614************************************************/
++/* Basic mode control register(0x00) */
++#define FIBER_BMCR_RESV 0x001f /* b[4:0] Unused... */
++#define FIBER_BMCR_EN_UNIDIR 0x0020 /* b[5] Valid when bit 0.12 is zero and bit 0.8 is one */
++#define FIBER_BMCR_SPEED1000 0x0040 /* b[6] MSB of Speed (1000) */
++#define FIBER_BMCR_CTST 0x0080 /* b[7] Collision test */
++#define FIBER_BMCR_DUPLEX_MODE 0x0100 /* b[8] Duplex mode */
++#define FIBER_BMCR_ANRESTART 0x0200 /* b[9] Auto negotiation restart */
++#define FIBER_BMCR_ISOLATE 0x0400 /* b[10] Isolate phy from RGMII/SGMII/FIBER */
++#define FIBER_BMCR_PDOWN 0x0800 /* b[11] 1: Power down */
++#define FIBER_BMCR_ANENABLE 0x1000 /* b[12] Enable auto negotiation */
++#define FIBER_BMCR_SPEED100 0x2000 /* b[13] LSB of Speed (100) */
++#define FIBER_BMCR_LOOPBACK 0x4000 /* b[14] Internal loopback control */
++#define FIBER_BMCR_RESET 0x8000 /* b[15] PHY Software Reset(self-clear) */
++
++/* Sds specific status register(0x11) */
++#define FIBER_SSR_ERCAP 0x0001 /* b[0] realtime syncstatus */
++#define FIBER_SSR_XMIT 0x000E /* b[3:1] realtime transmit statemachine.
++ 001: Xmit Idle;
++ 010: Xmit Config;
++ 100: Xmit Data. */
++#define FIBER_SSR_SER_MODE_CFG 0x0030 /* b[5:4] realtime serdes working mode.
++ 00: SG_MAC;
++ 01: SG_PHY;
++ 10: FIB_1000;
++ 11: FIB_100. */
++#define FIBER_SSR_EN_FLOWCTRL_TX 0x0040 /* b[6] realtime en_flowctrl_tx */
++#define FIBER_SSR_EN_FLOWCTRL_RX 0x0080 /* b[7] realtime en_flowctrl_rx */
++#define FIBER_SSR_DUPLEX_ERROR 0x0100 /* b[8] realtime deplex error */
++#define FIBER_SSR_RX_LPI_ACTIVE 0x0200 /* b[9] rx lpi is active */
++#define FIBER_SSR_LSTATUS 0x0400 /* b[10] Link status real-time */
++#define FIBER_SSR_PAUSE 0x1800 /* b[12:11] Pause to mac */
++#define FIBER_SSR_DUPLEX 0x2000 /* b[13] This status bit is valid only when bit10 is 1.
++ 1: full duplex
++ 0: half duplex */
++#define FIBER_SSR_SPEED_MODE 0xC000 /* b[15:14] These status bits are valid only when bit10 is 1.
++ 10---1000M
++ 01---100M */
++
++/* SLED cfg0 (ext 0xA001) */
++#define FIBER_SLED_CFG0_EN_CTRL 0x00FF /* b[7:0] Control to enable the eight ports' SLED */
++#define FIBER_SLED_CFG0_BIT_MASK 0x0700 /* b[10:8] 1: enable the pin output */
++#define FIBER_SLED_CFG0_ACT_LOW 0x0800 /* b[11] control SLED's polarity. 1: active low; 0: active high */
++#define FIBER_SLED_CFG0_MANU_ST 0x7000 /* b[14:12] SLEDs' manul status, corresponding to each port's 3 SLEDs */
++#define FIBER_SLED_CFG0_MANU_EN 0x8000 /* b[15] to control serial LEDs status manually */
++
++/**********YT8614************************************************/
++/* Fiber auto sensing(sgmii ext 0xA5) */
++#define FIBER_AUTO_SEN_ENABLE 0x8000 /* b[15] Enable fiber auto sensing */
++
++/* Fiber force speed(common ext 0xA009) */
++#define FIBER_FORCE_1000M 0x0001 /* b[0] 1:1000BX 0:100FX */
++
++#ifndef NULL
++#define NULL 0
++#endif
++
++/* errno */
++enum ytphy_8614_errno_e
++{
++ SYS_E_NONE,
++ SYS_E_PARAM,
++ SYS_E_MAX
++};
++
++/* errno */
++enum ytphy_8614_combo_speed_e
++{
++ YT8614_COMBO_FIBER_1000M,
++ YT8614_COMBO_FIBER_100M,
++ YT8614_COMBO_UTP_ONLY,
++ YT8614_COMBO_SPEED_MAX
++};
++
++/* definition for porting */
++/* phy registers access */
++typedef struct
++{
++ u16 reg; /* the offset of the phy internal address */
++ u16 val; /* the value of the register */
++ u8 regType; /* register type */
++} phy_data_s;
++
++/* for porting use.
++ * pls over-write member function read/write for mdio access
++ */
++typedef struct phy_info_str
++{
++#if 0
++ struct phy_device *phydev;
++ int mdio_base;
++#endif
++ unsigned int lport;
++ unsigned int bus_id;
++ unsigned int phy_addr;
++
++ s32 (*read)(struct phy_info_str *info, phy_data_s *param);
++ s32 (*write)(struct phy_info_str *info, phy_data_s *param);
++}phy_info_s;
++
++/* get phy access method */
++s32 yt8614_read_reg(struct phy_info_str *info, phy_data_s *param);
++s32 yt8614_write_reg(struct phy_info_str *info, phy_data_s *param);
++s32 yt8614_phy_soft_reset(u32 lport);
++s32 yt8614_phy_init(u32 lport);
++s32 yt8614_fiber_enable(u32 lport, BOOL enable);
++s32 yt8614_utp_enable(u32 lport, BOOL enable);
++s32 yt8614_fiber_unidirection_set(u32 lport, int speed, BOOL enable);
++s32 yt8614_fiber_autosensing_set(u32 lport, BOOL enable);
++s32 yt8614_fiber_speed_set(u32 lport, int fiber_speed);
++s32 yt8614_qsgmii_autoneg_set(u32 lport, BOOL enable);
++s32 yt8614_sgmii_autoneg_set(u32 lport, BOOL enable);
++s32 yt8614_qsgmii_sgmii_link_status_get(u32 lport, BOOL *enable, BOOL if_qsgmii);
++int yt8614_combo_media_priority_set (u32 lport, int fiber);
++int yt8614_combo_media_priority_get (u32 lport, int *fiber);
++s32 yt8614_utp_autoneg_set(u32 lport, BOOL enable);
++s32 yt8614_utp_autoneg_get(u32 lport, BOOL *enable);
++s32 yt8614_utp_autoneg_ability_set(u32 lport, unsigned int cap_mask);
++s32 yt8614_utp_autoneg_ability_get(u32 lport, unsigned int *cap_mask);
++s32 yt8614_utp_force_duplex_set(u32 lport, BOOL full);
++s32 yt8614_utp_force_duplex_get(u32 lport, BOOL *full);
++s32 yt8614_utp_force_speed_set(u32 lport, unsigned int speed);
++s32 yt8614_utp_force_speed_get(u32 lport, unsigned int *speed);
++int yt8614_autoneg_done_get (u32 lport, int speed, int *aneg);
++int yt8614_media_status_get(u32 lport, int* speed, int* duplex, int* ret_link, int *media);
++
++#endif
+--- /dev/null
++++ b/include/linux/motorcomm_phy.h
+@@ -0,0 +1,119 @@
++/*
++ * include/linux/motorcomm_phy.h
++ *
++ * Motorcomm PHY IDs
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ */
++
++#ifndef _MOTORCOMM_PHY_H
++#define _MOTORCOMM_PHY_H
++
++#define MOTORCOMM_PHY_ID_MASK 0x00000fff
++#define MOTORCOMM_PHY_ID_8531_MASK 0xffffffff
++#define MOTORCOMM_MPHY_ID_MASK 0x0000ffff
++
++#define PHY_ID_YT8010 0x00000309
++#define PHY_ID_YT8510 0x00000109
++#define PHY_ID_YT8511 0x0000010a
++#define PHY_ID_YT8512 0x00000118
++#define PHY_ID_YT8512B 0x00000128
++#define PHY_ID_YT8521 0x0000011a
++#define PHY_ID_YT8531S 0x4f51e91a
++#define PHY_ID_YT8531 0x4f51e91b
++//#define PHY_ID_YT8614 0x0000e899
++#define PHY_ID_YT8618 0x0000e889
++
++#define REG_PHY_SPEC_STATUS 0x11
++#define REG_DEBUG_ADDR_OFFSET 0x1e
++#define REG_DEBUG_DATA 0x1f
++
++#define YT8512_EXTREG_AFE_PLL 0x50
++#define YT8512_EXTREG_EXTEND_COMBO 0x4000
++#define YT8512_EXTREG_LED0 0x40c0
++#define YT8512_EXTREG_LED1 0x40c3
++
++#define YT8512_EXTREG_SLEEP_CONTROL1 0x2027
++
++#define YT_SOFTWARE_RESET 0x8000
++
++#define YT8512_CONFIG_PLL_REFCLK_SEL_EN 0x0040
++#define YT8512_CONTROL1_RMII_EN 0x0001
++#define YT8512_LED0_ACT_BLK_IND 0x1000
++#define YT8512_LED0_DIS_LED_AN_TRY 0x0001
++#define YT8512_LED0_BT_BLK_EN 0x0002
++#define YT8512_LED0_HT_BLK_EN 0x0004
++#define YT8512_LED0_COL_BLK_EN 0x0008
++#define YT8512_LED0_BT_ON_EN 0x0010
++#define YT8512_LED1_BT_ON_EN 0x0010
++#define YT8512_LED1_TXACT_BLK_EN 0x0100
++#define YT8512_LED1_RXACT_BLK_EN 0x0200
++#define YT8512_SPEED_MODE 0xc000
++#define YT8512_DUPLEX 0x2000
++
++#define YT8512_SPEED_MODE_BIT 14
++#define YT8512_DUPLEX_BIT 13
++#define YT8512_EN_SLEEP_SW_BIT 15
++
++#define YT8521_EXTREG_SLEEP_CONTROL1 0x27
++#define YT8521_EN_SLEEP_SW_BIT 15
++
++#define YT8521_SPEED_MODE 0xc000
++#define YT8521_DUPLEX 0x2000
++#define YT8521_SPEED_MODE_BIT 14
++#define YT8521_DUPLEX_BIT 13
++#define YT8521_LINK_STATUS_BIT 10
++
++/* based on yt8521 wol config register */
++#define YTPHY_UTP_INTR_REG 0x12
++/* WOL Event Interrupt Enable */
++#define YTPHY_WOL_INTR BIT(6)
++
++/* Magic Packet MAC address registers */
++#define YTPHY_MAGIC_PACKET_MAC_ADDR2 0xa007
++#define YTPHY_MAGIC_PACKET_MAC_ADDR1 0xa008
++#define YTPHY_MAGIC_PACKET_MAC_ADDR0 0xa009
++
++#define YTPHY_WOL_CFG_REG 0xa00a
++#define YTPHY_WOL_CFG_TYPE BIT(0) /* WOL TYPE */
++#define YTPHY_WOL_CFG_EN BIT(3) /* WOL Enable */
++#define YTPHY_WOL_CFG_INTR_SEL BIT(6) /* WOL Event Interrupt Enable */
++#define YTPHY_WOL_CFG_WIDTH1 BIT(1) /* WOL Pulse Width */
++#define YTPHY_WOL_CFG_WIDTH2 BIT(2)
++
++#define YTPHY_REG_SPACE_UTP 0
++#define YTPHY_REG_SPACE_FIBER 2
++
++enum ytphy_wol_type_e
++{
++ YTPHY_WOL_TYPE_LEVEL,
++ YTPHY_WOL_TYPE_PULSE,
++ YTPHY_WOL_TYPE_MAX
++};
++typedef enum ytphy_wol_type_e ytphy_wol_type_t;
++
++enum ytphy_wol_width_e
++{
++ YTPHY_WOL_WIDTH_84MS,
++ YTPHY_WOL_WIDTH_168MS,
++ YTPHY_WOL_WIDTH_336MS,
++ YTPHY_WOL_WIDTH_672MS,
++ YTPHY_WOL_WIDTH_MAX
++};
++typedef enum ytphy_wol_width_e ytphy_wol_width_t;
++
++struct ytphy_wol_cfg_s
++{
++ int enable;
++ int type;
++ int width;
++};
++typedef struct ytphy_wol_cfg_s ytphy_wol_cfg_t;
++
++#endif /* _MOTORCOMM_PHY_H */
++
++
diff --git a/target/linux/rockchip/patches-5.19/0057-arm64-dts-rockchip-add-hardware-random-number-genera.patch b/target/linux/rockchip/patches-5.19/0057-arm64-dts-rockchip-add-hardware-random-number-genera.patch
new file mode 100644
index 00000000000000..266b8b28dec86e
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0057-arm64-dts-rockchip-add-hardware-random-number-genera.patch
@@ -0,0 +1,50 @@
+From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001
+From: wevsty <ty@wevs.org>
+Date: Mon, 24 Aug 2020 02:27:11 +0800
+Subject: [PATCH] arm64: dts: rockchip: add hardware random number generator
+ for RK3328 and RK3399
+
+Adding Hardware Random Number Generator Resources to the RK3328 and RK3399.
+
+Signed-off-by: wevsty <ty@wevs.org>
+---
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -279,6 +279,17 @@
+ status = "disabled";
+ };
+
++ rng: rng@ff060000 {
++ compatible = "rockchip,cryptov1-rng";
++ reg = <0x0 0xff060000 0x0 0x4000>;
++
++ clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
++ clock-names = "clk_crypto", "hclk_crypto";
++ assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
++ assigned-clock-rates = <150000000>, <100000000>;
++ status = "disabled";
++ };
++
+ grf: syscon@ff100000 {
+ compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xff100000 0x0 0x1000>;
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -2017,6 +2017,16 @@
+ };
+ };
+
++ rng: rng@ff8b8000 {
++ compatible = "rockchip,cryptov1-rng";
++ reg = <0x0 0xff8b8000 0x0 0x1000>;
++ clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;
++ clock-names = "clk_crypto", "hclk_crypto";
++ assigned-clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;
++ assigned-clock-rates = <150000000>, <100000000>;
++ status = "okay";
++ };
++
+ gpu: gpu@ff9a0000 {
+ compatible = "rockchip,rk3399-mali", "arm,mali-t860";
+ reg = <0x0 0xff9a0000 0x0 0x10000>;
diff --git a/target/linux/rockchip/patches-5.19/0058-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch b/target/linux/rockchip/patches-5.19/0058-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch
new file mode 100644
index 00000000000000..643c994f2fa91f
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0058-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch
@@ -0,0 +1,44 @@
+From fcd9629c05f373771e85920e1c1d0ab252617878 Mon Sep 17 00:00:00 2001
+From: hmz007 <hmz007@gmail.com>
+Date: Tue, 19 Nov 2019 13:53:25 +0800
+Subject: [PATCH] PM / devfreq: rockchip: add devfreq driver for rk3328 dmc
+
+Signed-off-by: hmz007 <hmz007@gmail.com>
+---
+ drivers/devfreq/Kconfig | 18 +-
+ drivers/devfreq/Makefile | 1 +
+ drivers/devfreq/rk3328_dmc.c | 846 +++++++++++++++++++++++++++++++++++
+ 3 files changed, 862 insertions(+), 3 deletions(-)
+ create mode 100644 drivers/devfreq/rk3328_dmc.c
+
+--- a/drivers/devfreq/Kconfig
++++ b/drivers/devfreq/Kconfig
+@@ -120,6 +120,18 @@ config ARM_TEGRA_DEVFREQ
+ It reads ACTMON counters of memory controllers and adjusts the
+ operating frequencies and voltages with OPP support.
+
++config ARM_RK3328_DMC_DEVFREQ
++ tristate "ARM RK3328 DMC DEVFREQ Driver"
++ depends on ARCH_ROCKCHIP
++ select DEVFREQ_EVENT_ROCKCHIP_DFI
++ select DEVFREQ_GOV_SIMPLE_ONDEMAND
++ select PM_DEVFREQ_EVENT
++ select PM_OPP
++ help
++ This adds the DEVFREQ driver for the RK3328 DMC(Dynamic Memory Controller).
++ It sets the frequency for the memory controller and reads the usage counts
++ from hardware.
++
+ config ARM_RK3399_DMC_DEVFREQ
+ tristate "ARM RK3399 DMC DEVFREQ Driver"
+ depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
+--- a/drivers/devfreq/Makefile
++++ b/drivers/devfreq/Makefile
+@@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += gov
+ obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
+ obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
+ obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
++obj-$(CONFIG_ARM_RK3328_DMC_DEVFREQ) += rk3328_dmc.o
+ obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
+ obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
+ obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
diff --git a/target/linux/rockchip/patches-5.19/0059-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch b/target/linux/rockchip/patches-5.19/0059-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch
new file mode 100644
index 00000000000000..0408a0a73ac8a5
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0059-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch
@@ -0,0 +1,210 @@
+From ce6d3614888e6358466f0e84e248177a6bca5258 Mon Sep 17 00:00:00 2001
+From: Tang Yun ping <typ@rock-chips.com>
+Date: Thu, 4 May 2017 20:49:58 +0800
+Subject: [PATCH] clk: rockchip: support setting ddr clock via SIP Version 2
+ APIs
+
+commit 764e893ee82321938fc6f4349e9e7caf06a04410 rockchip.
+
+Signed-off-by: Tang Yun ping <typ@rock-chips.com>
+Signed-off-by: hmz007 <hmz007@gmail.com>
+---
+ drivers/clk/rockchip/clk-ddr.c | 130 ++++++++++++++++++++++++++++
+ drivers/clk/rockchip/clk-rk3328.c | 7 +-
+ drivers/clk/rockchip/clk.h | 3 +-
+ include/soc/rockchip/rockchip_sip.h | 11 +++
+ 4 files changed, 147 insertions(+), 4 deletions(-)
+
+--- a/drivers/clk/rockchip/clk-ddr.c
++++ b/drivers/clk/rockchip/clk-ddr.c
+@@ -87,6 +87,133 @@ static const struct clk_ops rockchip_ddr
+ .get_parent = rockchip_ddrclk_get_parent,
+ };
+
++/* See v4.4/include/dt-bindings/display/rk_fb.h */
++#define SCREEN_NULL 0
++#define SCREEN_HDMI 6
++
++static inline int rk_drm_get_lcdc_type(void)
++{
++ return SCREEN_NULL;
++}
++
++struct share_params {
++ u32 hz;
++ u32 lcdc_type;
++ u32 vop;
++ u32 vop_dclk_mode;
++ u32 sr_idle_en;
++ u32 addr_mcu_el3;
++ /*
++ * 1: need to wait flag1
++ * 0: never wait flag1
++ */
++ u32 wait_flag1;
++ /*
++ * 1: need to wait flag1
++ * 0: never wait flag1
++ */
++ u32 wait_flag0;
++ u32 complt_hwirq;
++ /* if need, add parameter after */
++};
++
++struct rockchip_ddrclk_data {
++ u32 inited_flag;
++ void __iomem *share_memory;
++};
++
++static struct rockchip_ddrclk_data ddr_data;
++
++static void rockchip_ddrclk_data_init(void)
++{
++ struct arm_smccc_res res;
++
++ arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,
++ 1, SHARE_PAGE_TYPE_DDR, 0,
++ 0, 0, 0, 0, &res);
++
++ if (!res.a0) {
++ ddr_data.share_memory = (void __iomem *)ioremap(res.a1, 1<<12);
++ ddr_data.inited_flag = 1;
++ }
++}
++
++static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw,
++ unsigned long drate,
++ unsigned long prate)
++{
++ struct share_params *p;
++ struct arm_smccc_res res;
++
++ if (!ddr_data.inited_flag)
++ rockchip_ddrclk_data_init();
++
++ p = (struct share_params *)ddr_data.share_memory;
++
++ p->hz = drate;
++ p->lcdc_type = rk_drm_get_lcdc_type();
++ p->wait_flag1 = 1;
++ p->wait_flag0 = 1;
++
++ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
++ SHARE_PAGE_TYPE_DDR, 0,
++ ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,
++ 0, 0, 0, 0, &res);
++
++ if ((int)res.a1 == -6) {
++ pr_err("%s: timeout, drate = %lumhz\n", __func__, drate/1000000);
++ /* TODO: rockchip_dmcfreq_wait_complete(); */
++ }
++
++ return res.a0;
++}
++
++static unsigned long rockchip_ddrclk_sip_recalc_rate_v2
++ (struct clk_hw *hw, unsigned long parent_rate)
++{
++ struct arm_smccc_res res;
++
++ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
++ SHARE_PAGE_TYPE_DDR, 0,
++ ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,
++ 0, 0, 0, 0, &res);
++ if (!res.a0)
++ return res.a1;
++ else
++ return 0;
++}
++
++static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw,
++ unsigned long rate,
++ unsigned long *prate)
++{
++ struct share_params *p;
++ struct arm_smccc_res res;
++
++ if (!ddr_data.inited_flag)
++ rockchip_ddrclk_data_init();
++
++ p = (struct share_params *)ddr_data.share_memory;
++
++ p->hz = rate;
++
++ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
++ SHARE_PAGE_TYPE_DDR, 0,
++ ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,
++ 0, 0, 0, 0, &res);
++ if (!res.a0)
++ return res.a1;
++ else
++ return 0;
++}
++
++static const struct clk_ops rockchip_ddrclk_sip_ops_v2 = {
++ .recalc_rate = rockchip_ddrclk_sip_recalc_rate_v2,
++ .set_rate = rockchip_ddrclk_sip_set_rate_v2,
++ .round_rate = rockchip_ddrclk_sip_round_rate_v2,
++ .get_parent = rockchip_ddrclk_get_parent,
++};
++
+ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
+ const char *const *parent_names,
+ u8 num_parents, int mux_offset,
+@@ -114,6 +241,9 @@ struct clk *rockchip_clk_register_ddrclk
+ case ROCKCHIP_DDRCLK_SIP:
+ init.ops = &rockchip_ddrclk_sip_ops;
+ break;
++ case ROCKCHIP_DDRCLK_SIP_V2:
++ init.ops = &rockchip_ddrclk_sip_ops_v2;
++ break;
+ default:
+ pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
+ kfree(ddrclk);
+--- a/drivers/clk/rockchip/clk-rk3328.c
++++ b/drivers/clk/rockchip/clk-rk3328.c
+@@ -315,9 +315,10 @@ static struct rockchip_clk_branch rk3328
+ RK3328_CLKGATE_CON(14), 1, GFLAGS),
+
+ /* PD_DDR */
+- COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED,
+- RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
+- RK3328_CLKGATE_CON(0), 4, GFLAGS),
++ COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
++ RK3328_CLKSEL_CON(3), 8, 2, 0, 3,
++ ROCKCHIP_DDRCLK_SIP_V2),
++
+ GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
+ RK3328_CLKGATE_CON(18), 6, GFLAGS),
+ GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -399,7 +399,8 @@ struct clk *rockchip_clk_register_mmc(co
+ * DDRCLK flags, including method of setting the rate
+ * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
+ */
+-#define ROCKCHIP_DDRCLK_SIP BIT(0)
++#define ROCKCHIP_DDRCLK_SIP 0x01
++#define ROCKCHIP_DDRCLK_SIP_V2 0x03
+
+ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
+ const char *const *parent_names,
+--- a/include/soc/rockchip/rockchip_sip.h
++++ b/include/soc/rockchip/rockchip_sip.h
+@@ -16,5 +16,16 @@
+ #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06
+ #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07
+ #define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08
++#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION 0x08
++
++#define ROCKCHIP_SIP_SHARE_MEM 0x82000009
++
++/* Share mem page types */
++typedef enum {
++ SHARE_PAGE_TYPE_INVALID = 0,
++ SHARE_PAGE_TYPE_UARTDBG,
++ SHARE_PAGE_TYPE_DDR,
++ SHARE_PAGE_TYPE_MAX,
++} share_page_type_t;
+
+ #endif
diff --git a/target/linux/rockchip/patches-5.19/0060-PM-devfreq-rockchip-dfi-add-more-soc-support.patch b/target/linux/rockchip/patches-5.19/0060-PM-devfreq-rockchip-dfi-add-more-soc-support.patch
new file mode 100644
index 00000000000000..283e4abd2f8b5a
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0060-PM-devfreq-rockchip-dfi-add-more-soc-support.patch
@@ -0,0 +1,662 @@
+From 4db93c6dad0c71750b86163df2fdb21c35f00d9a Mon Sep 17 00:00:00 2001
+From: hmz007 <hmz007@gmail.com>
+Date: Tue, 19 Nov 2019 12:49:48 +0800
+Subject: [PATCH] PM / devfreq: rockchip-dfi: add more soc support
+
+Signed-off-by: hmz007 <hmz007@gmail.com>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 554 ++++++++++++++++++++++++---
+ 1 file changed, 505 insertions(+), 49 deletions(-)
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -18,25 +18,66 @@
+ #include <linux/list.h>
+ #include <linux/of.h>
+
+-#include <soc/rockchip/rk3399_grf.h>
+-
+-#define RK3399_DMC_NUM_CH 2
++#define PX30_PMUGRF_OS_REG2 0x208
+
++#define RK3128_GRF_SOC_CON0 0x140
++#define RK3128_GRF_OS_REG1 0x1cc
++#define RK3128_GRF_DFI_WRNUM 0x220
++#define RK3128_GRF_DFI_RDNUM 0x224
++#define RK3128_GRF_DFI_TIMERVAL 0x22c
++#define RK3128_DDR_MONITOR_EN ((1 << (16 + 6)) + (1 << 6))
++#define RK3128_DDR_MONITOR_DISB ((1 << (16 + 6)) + (0 << 6))
++
++#define RK3288_PMU_SYS_REG2 0x9c
++#define RK3288_GRF_SOC_CON4 0x254
++#define RK3288_GRF_SOC_STATUS(n) (0x280 + (n) * 4)
++#define RK3288_DFI_EN (0x30003 << 14)
++#define RK3288_DFI_DIS (0x30000 << 14)
++#define RK3288_LPDDR_SEL (0x10001 << 13)
++#define RK3288_DDR3_SEL (0x10000 << 13)
++
++#define RK3328_GRF_OS_REG2 0x5d0
++
++#define RK3368_GRF_DDRC0_CON0 0x600
++#define RK3368_GRF_SOC_STATUS5 0x494
++#define RK3368_GRF_SOC_STATUS6 0x498
++#define RK3368_GRF_SOC_STATUS8 0x4a0
++#define RK3368_GRF_SOC_STATUS9 0x4a4
++#define RK3368_GRF_SOC_STATUS10 0x4a8
++#define RK3368_DFI_EN (0x30003 << 5)
++#define RK3368_DFI_DIS (0x30000 << 5)
++
++#define MAX_DMC_NUM_CH 2
++#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7)
++#define READ_CH_INFO(n) (((n) >> 28) & 0x3)
+ /* DDRMON_CTRL */
+-#define DDRMON_CTRL 0x04
+-#define CLR_DDRMON_CTRL (0x1f0000 << 0)
+-#define LPDDR4_EN (0x10001 << 4)
+-#define HARDWARE_EN (0x10001 << 3)
+-#define LPDDR3_EN (0x10001 << 2)
+-#define SOFTWARE_EN (0x10001 << 1)
+-#define SOFTWARE_DIS (0x10000 << 1)
+-#define TIME_CNT_EN (0x10001 << 0)
++#define DDRMON_CTRL 0x04
++#define CLR_DDRMON_CTRL (0x3f0000 << 0)
++#define DDR4_EN (0x10001 << 5)
++#define LPDDR4_EN (0x10001 << 4)
++#define HARDWARE_EN (0x10001 << 3)
++#define LPDDR2_3_EN (0x10001 << 2)
++#define SOFTWARE_EN (0x10001 << 1)
++#define SOFTWARE_DIS (0x10000 << 1)
++#define TIME_CNT_EN (0x10001 << 0)
+
+ #define DDRMON_CH0_COUNT_NUM 0x28
+ #define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
+ #define DDRMON_CH1_COUNT_NUM 0x3c
+ #define DDRMON_CH1_DFI_ACCESS_NUM 0x40
+
++/* pmu grf */
++#define PMUGRF_OS_REG2 0x308
++
++enum {
++ DDR4 = 0,
++ DDR3 = 3,
++ LPDDR2 = 5,
++ LPDDR3 = 6,
++ LPDDR4 = 7,
++ UNUSED = 0xFF
++};
++
+ struct dmc_usage {
+ u32 access;
+ u32 total;
+@@ -50,33 +91,261 @@ struct dmc_usage {
+ struct rockchip_dfi {
+ struct devfreq_event_dev *edev;
+ struct devfreq_event_desc *desc;
+- struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
++ struct dmc_usage ch_usage[MAX_DMC_NUM_CH];
+ struct device *dev;
+ void __iomem *regs;
+ struct regmap *regmap_pmu;
++ struct regmap *regmap_grf;
++ struct regmap *regmap_pmugrf;
+ struct clk *clk;
++ u32 dram_type;
++ /*
++ * available mask, 1: available, 0: not available
++ * each bit represent a channel
++ */
++ u32 ch_msk;
++};
++
++static void rk3128_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
++{
++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
++
++ regmap_write(info->regmap_grf,
++ RK3128_GRF_SOC_CON0,
++ RK3128_DDR_MONITOR_EN);
++}
++
++static void rk3128_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
++{
++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
++
++ regmap_write(info->regmap_grf,
++ RK3128_GRF_SOC_CON0,
++ RK3128_DDR_MONITOR_DISB);
++}
++
++static int rk3128_dfi_disable(struct devfreq_event_dev *edev)
++{
++ rk3128_dfi_stop_hardware_counter(edev);
++
++ return 0;
++}
++
++static int rk3128_dfi_enable(struct devfreq_event_dev *edev)
++{
++ rk3128_dfi_start_hardware_counter(edev);
++
++ return 0;
++}
++
++static int rk3128_dfi_set_event(struct devfreq_event_dev *edev)
++{
++ return 0;
++}
++
++static int rk3128_dfi_get_event(struct devfreq_event_dev *edev,
++ struct devfreq_event_data *edata)
++{
++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
++ unsigned long flags;
++ u32 dfi_wr, dfi_rd, dfi_timer;
++
++ local_irq_save(flags);
++
++ rk3128_dfi_stop_hardware_counter(edev);
++
++ regmap_read(info->regmap_grf, RK3128_GRF_DFI_WRNUM, &dfi_wr);
++ regmap_read(info->regmap_grf, RK3128_GRF_DFI_RDNUM, &dfi_rd);
++ regmap_read(info->regmap_grf, RK3128_GRF_DFI_TIMERVAL, &dfi_timer);
++
++ edata->load_count = (dfi_wr + dfi_rd) * 4;
++ edata->total_count = dfi_timer;
++
++ rk3128_dfi_start_hardware_counter(edev);
++
++ local_irq_restore(flags);
++
++ return 0;
++}
++
++static const struct devfreq_event_ops rk3128_dfi_ops = {
++ .disable = rk3128_dfi_disable,
++ .enable = rk3128_dfi_enable,
++ .get_event = rk3128_dfi_get_event,
++ .set_event = rk3128_dfi_set_event,
++};
++
++static void rk3288_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
++{
++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
++
++ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_EN);
++}
++
++static void rk3288_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
++{
++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
++
++ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_DIS);
++}
++
++static int rk3288_dfi_disable(struct devfreq_event_dev *edev)
++{
++ rk3288_dfi_stop_hardware_counter(edev);
++
++ return 0;
++}
++
++static int rk3288_dfi_enable(struct devfreq_event_dev *edev)
++{
++ rk3288_dfi_start_hardware_counter(edev);
++
++ return 0;
++}
++
++static int rk3288_dfi_set_event(struct devfreq_event_dev *edev)
++{
++ return 0;
++}
++
++static int rk3288_dfi_get_busier_ch(struct devfreq_event_dev *edev)
++{
++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
++ u32 tmp, max = 0;
++ u32 i, busier_ch = 0;
++ u32 rd_count, wr_count, total_count;
++
++ rk3288_dfi_stop_hardware_counter(edev);
++
++ /* Find out which channel is busier */
++ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
++ if (!(info->ch_msk & BIT(i)))
++ continue;
++ regmap_read(info->regmap_grf,
++ RK3288_GRF_SOC_STATUS(11 + i * 4), &wr_count);
++ regmap_read(info->regmap_grf,
++ RK3288_GRF_SOC_STATUS(12 + i * 4), &rd_count);
++ regmap_read(info->regmap_grf,
++ RK3288_GRF_SOC_STATUS(14 + i * 4), &total_count);
++ info->ch_usage[i].access = (wr_count + rd_count) * 4;
++ info->ch_usage[i].total = total_count;
++ tmp = info->ch_usage[i].access;
++ if (tmp > max) {
++ busier_ch = i;
++ max = tmp;
++ }
++ }
++ rk3288_dfi_start_hardware_counter(edev);
++
++ return busier_ch;
++}
++
++static int rk3288_dfi_get_event(struct devfreq_event_dev *edev,
++ struct devfreq_event_data *edata)
++{
++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
++ int busier_ch;
++ unsigned long flags;
++
++ local_irq_save(flags);
++ busier_ch = rk3288_dfi_get_busier_ch(edev);
++ local_irq_restore(flags);
++
++ edata->load_count = info->ch_usage[busier_ch].access;
++ edata->total_count = info->ch_usage[busier_ch].total;
++
++ return 0;
++}
++
++static const struct devfreq_event_ops rk3288_dfi_ops = {
++ .disable = rk3288_dfi_disable,
++ .enable = rk3288_dfi_enable,
++ .get_event = rk3288_dfi_get_event,
++ .set_event = rk3288_dfi_set_event,
++};
++
++static void rk3368_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
++{
++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
++
++ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_EN);
++}
++
++static void rk3368_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
++{
++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
++
++ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_DIS);
++}
++
++static int rk3368_dfi_disable(struct devfreq_event_dev *edev)
++{
++ rk3368_dfi_stop_hardware_counter(edev);
++
++ return 0;
++}
++
++static int rk3368_dfi_enable(struct devfreq_event_dev *edev)
++{
++ rk3368_dfi_start_hardware_counter(edev);
++
++ return 0;
++}
++
++static int rk3368_dfi_set_event(struct devfreq_event_dev *edev)
++{
++ return 0;
++}
++
++static int rk3368_dfi_get_event(struct devfreq_event_dev *edev,
++ struct devfreq_event_data *edata)
++{
++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
++ unsigned long flags;
++ u32 dfi0_wr, dfi0_rd, dfi1_wr, dfi1_rd, dfi_timer;
++
++ local_irq_save(flags);
++
++ rk3368_dfi_stop_hardware_counter(edev);
++
++ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS5, &dfi0_wr);
++ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS6, &dfi0_rd);
++ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS9, &dfi1_wr);
++ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS10, &dfi1_rd);
++ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS8, &dfi_timer);
++
++ edata->load_count = (dfi0_wr + dfi0_rd + dfi1_wr + dfi1_rd) * 2;
++ edata->total_count = dfi_timer;
++
++ rk3368_dfi_start_hardware_counter(edev);
++
++ local_irq_restore(flags);
++
++ return 0;
++}
++
++static const struct devfreq_event_ops rk3368_dfi_ops = {
++ .disable = rk3368_dfi_disable,
++ .enable = rk3368_dfi_enable,
++ .get_event = rk3368_dfi_get_event,
++ .set_event = rk3368_dfi_set_event,
+ };
+
+ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
+ {
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+ void __iomem *dfi_regs = info->regs;
+- u32 val;
+- u32 ddr_type;
+-
+- /* get ddr type */
+- regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
+- ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
+- RK3399_PMUGRF_DDRTYPE_MASK;
+
+ /* clear DDRMON_CTRL setting */
+ writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
+
+ /* set ddr type to dfi */
+- if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
+- writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
+- else if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
++ if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2)
++ writel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL);
++ else if (info->dram_type == LPDDR4)
+ writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
++ else if (info->dram_type == DDR4)
++ writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL);
+
+ /* enable count, use software mode */
+ writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
+@@ -100,12 +369,22 @@ static int rockchip_dfi_get_busier_ch(st
+ rockchip_dfi_stop_hardware_counter(edev);
+
+ /* Find out which channel is busier */
+- for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
+- info->ch_usage[i].access = readl_relaxed(dfi_regs +
+- DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
++ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
++ if (!(info->ch_msk & BIT(i)))
++ continue;
++
+ info->ch_usage[i].total = readl_relaxed(dfi_regs +
+ DDRMON_CH0_COUNT_NUM + i * 20);
+- tmp = info->ch_usage[i].access;
++
++ /* LPDDR4 BL = 16,other DDR type BL = 8 */
++ tmp = readl_relaxed(dfi_regs +
++ DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
++ if (info->dram_type == LPDDR4)
++ tmp *= 8;
++ else
++ tmp *= 4;
++ info->ch_usage[i].access = tmp;
++
+ if (tmp > max) {
+ busier_ch = i;
+ max = tmp;
+@@ -121,7 +400,8 @@ static int rockchip_dfi_disable(struct d
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+
+ rockchip_dfi_stop_hardware_counter(edev);
+- clk_disable_unprepare(info->clk);
++ if (info->clk)
++ clk_disable_unprepare(info->clk);
+
+ return 0;
+ }
+@@ -131,10 +411,13 @@ static int rockchip_dfi_enable(struct de
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+ int ret;
+
+- ret = clk_prepare_enable(info->clk);
+- if (ret) {
+- dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
+- return ret;
++ if (info->clk) {
++ ret = clk_prepare_enable(info->clk);
++ if (ret) {
++ dev_err(&edev->dev, "failed to enable dfi clk: %d\n",
++ ret);
++ return ret;
++ }
+ }
+
+ rockchip_dfi_start_hardware_counter(edev);
+@@ -151,8 +434,11 @@ static int rockchip_dfi_get_event(struct
+ {
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+ int busier_ch;
++ unsigned long flags;
+
++ local_irq_save(flags);
+ busier_ch = rockchip_dfi_get_busier_ch(edev);
++ local_irq_restore(flags);
+
+ edata->load_count = info->ch_usage[busier_ch].access;
+ edata->total_count = info->ch_usage[busier_ch].total;
+@@ -167,22 +453,116 @@ static const struct devfreq_event_ops ro
+ .set_event = rockchip_dfi_set_event,
+ };
+
+-static const struct of_device_id rockchip_dfi_id_match[] = {
+- { .compatible = "rockchip,rk3399-dfi" },
+- { },
+-};
+-MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
++static __init int px30_dfi_init(struct platform_device *pdev,
++ struct rockchip_dfi *data,
++ struct devfreq_event_desc *desc)
++{
++ struct device_node *np = pdev->dev.of_node, *node;
++ struct resource *res;
++ u32 val;
+
+-static int rockchip_dfi_probe(struct platform_device *pdev)
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ data->regs = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(data->regs))
++ return PTR_ERR(data->regs);
++
++ node = of_parse_phandle(np, "rockchip,pmugrf", 0);
++ if (node) {
++ data->regmap_pmugrf = syscon_node_to_regmap(node);
++ if (IS_ERR(data->regmap_pmugrf))
++ return PTR_ERR(data->regmap_pmugrf);
++ }
++
++ regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val);
++ data->dram_type = READ_DRAMTYPE_INFO(val);
++ data->ch_msk = 1;
++ data->clk = NULL;
++
++ desc->ops = &rockchip_dfi_ops;
++
++ return 0;
++}
++
++static __init int rk3128_dfi_init(struct platform_device *pdev,
++ struct rockchip_dfi *data,
++ struct devfreq_event_desc *desc)
+ {
+- struct device *dev = &pdev->dev;
+- struct rockchip_dfi *data;
+- struct devfreq_event_desc *desc;
+ struct device_node *np = pdev->dev.of_node, *node;
+
+- data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
+- if (!data)
+- return -ENOMEM;
++ node = of_parse_phandle(np, "rockchip,grf", 0);
++ if (node) {
++ data->regmap_grf = syscon_node_to_regmap(node);
++ if (IS_ERR(data->regmap_grf))
++ return PTR_ERR(data->regmap_grf);
++ }
++
++ desc->ops = &rk3128_dfi_ops;
++
++ return 0;
++}
++
++static __init int rk3288_dfi_init(struct platform_device *pdev,
++ struct rockchip_dfi *data,
++ struct devfreq_event_desc *desc)
++{
++ struct device_node *np = pdev->dev.of_node, *node;
++ u32 val;
++
++ node = of_parse_phandle(np, "rockchip,pmu", 0);
++ if (node) {
++ data->regmap_pmu = syscon_node_to_regmap(node);
++ if (IS_ERR(data->regmap_pmu))
++ return PTR_ERR(data->regmap_pmu);
++ }
++
++ node = of_parse_phandle(np, "rockchip,grf", 0);
++ if (node) {
++ data->regmap_grf = syscon_node_to_regmap(node);
++ if (IS_ERR(data->regmap_grf))
++ return PTR_ERR(data->regmap_grf);
++ }
++
++ regmap_read(data->regmap_pmu, RK3288_PMU_SYS_REG2, &val);
++ data->dram_type = READ_DRAMTYPE_INFO(val);
++ data->ch_msk = READ_CH_INFO(val);
++
++ if (data->dram_type == DDR3)
++ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
++ RK3288_DDR3_SEL);
++ else
++ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
++ RK3288_LPDDR_SEL);
++
++ desc->ops = &rk3288_dfi_ops;
++
++ return 0;
++}
++
++static __init int rk3368_dfi_init(struct platform_device *pdev,
++ struct rockchip_dfi *data,
++ struct devfreq_event_desc *desc)
++{
++ struct device *dev = &pdev->dev;
++
++ if (!dev->parent || !dev->parent->of_node)
++ return -EINVAL;
++
++ data->regmap_grf = syscon_node_to_regmap(dev->parent->of_node);
++ if (IS_ERR(data->regmap_grf))
++ return PTR_ERR(data->regmap_grf);
++
++ desc->ops = &rk3368_dfi_ops;
++
++ return 0;
++}
++
++static __init int rockchip_dfi_init(struct platform_device *pdev,
++ struct rockchip_dfi *data,
++ struct devfreq_event_desc *desc)
++{
++ struct device *dev = &pdev->dev;
++ struct device_node *np = pdev->dev.of_node, *node;
++ u32 val;
+
+ data->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(data->regs))
+@@ -202,21 +582,97 @@ static int rockchip_dfi_probe(struct pla
+ if (IS_ERR(data->regmap_pmu))
+ return PTR_ERR(data->regmap_pmu);
+ }
+- data->dev = dev;
++
++ regmap_read(data->regmap_pmu, PMUGRF_OS_REG2, &val);
++ data->dram_type = READ_DRAMTYPE_INFO(val);
++ data->ch_msk = READ_CH_INFO(val);
++
++ desc->ops = &rockchip_dfi_ops;
++
++ return 0;
++}
++
++static __init int rk3328_dfi_init(struct platform_device *pdev,
++ struct rockchip_dfi *data,
++ struct devfreq_event_desc *desc)
++{
++ struct device_node *np = pdev->dev.of_node, *node;
++ struct resource *res;
++ u32 val;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ data->regs = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(data->regs))
++ return PTR_ERR(data->regs);
++
++ node = of_parse_phandle(np, "rockchip,grf", 0);
++ if (node) {
++ data->regmap_grf = syscon_node_to_regmap(node);
++ if (IS_ERR(data->regmap_grf))
++ return PTR_ERR(data->regmap_grf);
++ }
++
++ regmap_read(data->regmap_grf, RK3328_GRF_OS_REG2, &val);
++ data->dram_type = READ_DRAMTYPE_INFO(val);
++ data->ch_msk = 1;
++ data->clk = NULL;
++
++ desc->ops = &rockchip_dfi_ops;
++
++ return 0;
++}
++
++static const struct of_device_id rockchip_dfi_id_match[] = {
++ { .compatible = "rockchip,px30-dfi", .data = px30_dfi_init },
++ { .compatible = "rockchip,rk1808-dfi", .data = px30_dfi_init },
++ { .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init },
++ { .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
++ { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
++ { .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
++ { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
++ { },
++};
++MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
++
++static int rockchip_dfi_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct rockchip_dfi *data;
++ struct devfreq_event_desc *desc;
++ struct device_node *np = pdev->dev.of_node;
++ const struct of_device_id *match;
++ int (*init)(struct platform_device *pdev, struct rockchip_dfi *data,
++ struct devfreq_event_desc *desc);
++
++ data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
++ if (!data)
++ return -ENOMEM;
+
+ desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
+
+- desc->ops = &rockchip_dfi_ops;
++ match = of_match_node(rockchip_dfi_id_match, pdev->dev.of_node);
++ if (match) {
++ init = match->data;
++ if (init) {
++ if (init(pdev, data, desc))
++ return -EINVAL;
++ } else {
++ return 0;
++ }
++ } else {
++ return 0;
++ }
++
+ desc->driver_data = data;
+ desc->name = np->name;
+ data->desc = desc;
++ data->dev = dev;
+
+- data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
++ data->edev = devm_devfreq_event_add_edev(dev, desc);
+ if (IS_ERR(data->edev)) {
+- dev_err(&pdev->dev,
+- "failed to add devfreq-event device\n");
++ dev_err(dev, "failed to add devfreq-event device\n");
+ return PTR_ERR(data->edev);
+ }
+
diff --git a/target/linux/rockchip/patches-5.19/0061-arm64-dts-rockchip-rk3328-add-dfi-node.patch b/target/linux/rockchip/patches-5.19/0061-arm64-dts-rockchip-rk3328-add-dfi-node.patch
new file mode 100644
index 00000000000000..2ab20487a0fe98
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0061-arm64-dts-rockchip-rk3328-add-dfi-node.patch
@@ -0,0 +1,27 @@
+From f9ae6e992d3d9e80357fee7d65ba0fe2dd37ae1f Mon Sep 17 00:00:00 2001
+From: hmz007 <hmz007@gmail.com>
+Date: Tue, 19 Nov 2019 14:21:51 +0800
+Subject: [PATCH] arm64: dts: rockchip: rk3328: add dfi node
+
+Signed-off-by: hmz007 <hmz007@gmail.com>
+[adjusted commit title]
+Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
+---
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 7 +++++++
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -1005,6 +1005,13 @@
+ status = "disabled";
+ };
+
++ dfi: dfi@ff790000 {
++ reg = <0x00 0xff790000 0x00 0x400>;
++ compatible = "rockchip,rk3328-dfi";
++ rockchip,grf = <&grf>;
++ status = "disabled";
++ };
++
+ gic: interrupt-controller@ff811000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
diff --git a/target/linux/rockchip/patches-5.19/0062-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch b/target/linux/rockchip/patches-5.19/0062-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch
new file mode 100644
index 00000000000000..2e36792accd22c
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0062-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch
@@ -0,0 +1,126 @@
+From f9ae6e992d3d9e80357fee7d65ba0fe2dd37ae1f Mon Sep 17 00:00:00 2001
+From: hmz007 <hmz007@gmail.com>
+Date: Tue, 19 Nov 2019 14:21:51 +0800
+Subject: [PATCH] arm64: dts: nanopi-r2: add rk3328-dmc relate node
+
+Signed-off-by: hmz007 <hmz007@gmail.com>
+---
+ .../rockchip/rk3328-dram-default-timing.dtsi | 311 ++++++++++++++++++
+ .../dts/rockchip/rk3328-nanopi-r2-common.dtsi | 85 ++++-
+ include/dt-bindings/clock/rockchip-ddr.h | 63 ++++
+ include/dt-bindings/memory/rk3328-dram.h | 159 +++++++++
+ 4 files changed, 617 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi
+ create mode 100644 include/dt-bindings/clock/rockchip-ddr.h
+ create mode 100644 include/dt-bindings/memory/rk3328-dram.h
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+@@ -7,6 +7,7 @@
+
+ #include <dt-bindings/input/input.h>
+ #include <dt-bindings/gpio/gpio.h>
++#include "rk3328-dram-nanopi2-timing.dtsi"
+ #include "rk3328.dtsi"
+
+ / {
+@@ -121,6 +122,72 @@
+ regulator-boot-on;
+ vin-supply = <&vdd_5v>;
+ };
++
++ dmc: dmc {
++ compatible = "rockchip,rk3328-dmc";
++ devfreq-events = <&dfi>;
++ center-supply = <&vdd_log>;
++ clocks = <&cru SCLK_DDRCLK>;
++ clock-names = "dmc_clk";
++ operating-points-v2 = <&dmc_opp_table>;
++ ddr_timing = <&ddr_timing>;
++ upthreshold = <40>;
++ downdifferential = <20>;
++ auto-min-freq = <786000>;
++ auto-freq-en = <0>;
++ #cooling-cells = <2>;
++ status = "okay";
++
++ ddr_power_model: ddr_power_model {
++ compatible = "ddr_power_model";
++ dynamic-power-coefficient = <120>;
++ static-power-coefficient = <200>;
++ ts = <32000 4700 (-80) 2>;
++ thermal-zone = "soc-thermal";
++ };
++ };
++
++ dmc_opp_table: dmc-opp-table {
++ compatible = "operating-points-v2";
++
++ rockchip,leakage-voltage-sel = <
++ 1 10 0
++ 11 254 1
++ >;
++ nvmem-cells = <&logic_leakage>;
++ nvmem-cell-names = "ddr_leakage";
++
++ opp-786000000 {
++ opp-hz = /bits/ 64 <786000000>;
++ opp-microvolt = <1075000>;
++ opp-microvolt-L0 = <1075000>;
++ opp-microvolt-L1 = <1050000>;
++ };
++ opp-798000000 {
++ opp-hz = /bits/ 64 <798000000>;
++ opp-microvolt = <1075000>;
++ opp-microvolt-L0 = <1075000>;
++ opp-microvolt-L1 = <1050000>;
++ };
++ opp-840000000 {
++ opp-hz = /bits/ 64 <840000000>;
++ opp-microvolt = <1075000>;
++ opp-microvolt-L0 = <1075000>;
++ opp-microvolt-L1 = <1050000>;
++ };
++ opp-924000000 {
++ opp-hz = /bits/ 64 <924000000>;
++ opp-microvolt = <1100000>;
++ opp-microvolt-L0 = <1100000>;
++ opp-microvolt-L1 = <1075000>;
++ };
++ opp-1056000000 {
++ opp-hz = /bits/ 64 <1056000000>;
++ opp-microvolt = <1175000>;
++ opp-microvolt-L0 = <1175000>;
++ opp-microvolt-L1 = <1150000>;
++ };
++ };
+ };
+
+ &cpu0 {
+@@ -139,6 +206,10 @@
+ cpu-supply = <&vdd_arm>;
+ };
+
++&dfi {
++ status = "okay";
++};
++
+ &display_subsystem {
+ status = "disabled";
+ };
+@@ -202,6 +273,7 @@
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
++ regulator-init-microvolt = <1075000>;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-ramp-delay = <12500>;
+@@ -216,6 +288,7 @@
+ regulator-name = "vdd_arm";
+ regulator-always-on;
+ regulator-boot-on;
++ regulator-init-microvolt = <1225000>;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-ramp-delay = <12500>;
diff --git a/target/linux/rockchip/patches-5.19/0063-drv-net-phy-add-JLSemi-jl2xxx-driver.patch b/target/linux/rockchip/patches-5.19/0063-drv-net-phy-add-JLSemi-jl2xxx-driver.patch
new file mode 100644
index 00000000000000..e2fb70694228e1
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0063-drv-net-phy-add-JLSemi-jl2xxx-driver.patch
@@ -0,0 +1,702 @@
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -260,6 +260,11 @@ config INTEL_XWAY_PHY
+ PEF 7061, PEF 7071 and PEF 7072 or integrated into the Intel
+ SoCs xRX200, xRX300, xRX330, xRX350 and xRX550.
+
++config JLSEMI_JL2XX1_PHY
++ tristate "JLSemi JL2XX1 PHYs"
++ help
++ Currently supports the JLSemi jl2xx1 PHYs.
++
+ config LSI_ET1011C_PHY
+ tristate "LSI ET1011C PHY"
+ help
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -72,6 +72,8 @@ obj-$(CONFIG_DP83TC811_PHY) += dp83tc811
+ obj-$(CONFIG_FIXED_PHY) += fixed_phy.o
+ obj-$(CONFIG_ICPLUS_PHY) += icplus.o
+ obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o
++obj-$(CONFIG_JLSEMI_JL2XX1_PHY) += jl2xx1.o
++jl2xx1-objs := jl2xxx.o jl2xxx-core.o
+ obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o
+ obj-$(CONFIG_LXT_PHY) += lxt.o
+ obj-$(CONFIG_MARVELL_10G_PHY) += marvell10g.o
+--- /dev/null
++++ b/drivers/net/phy/jl2xxx-core.c
+@@ -0,0 +1,438 @@
++/*
++ * Copyright (C) 2021 JLSemi Corporation
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation version 2.
++ *
++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
++ * kind, whether express or implied; without even the implied warranty
++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ */
++#include "jl2xxx-core.h"
++#include <linux/phy.h>
++#include <linux/module.h>
++#include <linux/version.h>
++#include <linux/netdevice.h>
++
++#define RGMII_CTRL_PAGE 171
++#define RGMII_CTRL_REG 17
++#define RGMII_TX_SW_RSTN BIT(14)
++#define RGMII_ERR_STAS BIT(3)
++#define RGMII_TX_CTR_EN BIT(1)
++
++#define RGMII_STATUS_PAGE 166
++#define RGMII_STATUS_REG 18
++
++#define BASIC_PAGE 0
++#define BMCR_REG 0
++#define SOFT_RESET BIT(15)
++#define SPEED_LSB BIT(13)
++#define AUTONEG_EN BIT(12)
++#define SPEED_MSB BIT(6)
++
++#define DIG_PAGE 201
++#define DIG_REG 17
++#define CLK_10M_EN BIT(15)
++#define DAC_OUT_SEL_MSB BIT(1)
++#define DAC_OUT_SEL_LSB BIT(0)
++
++/************************* Configuration section *************************/
++
++
++/************************* JLSemi iteration code *************************/
++
++/* Patch for version: def2 */
++uint32_t init_data[] = {
++ 0x1f00a0, 0x1903f3, 0x1f0012, 0x150100, 0x1f00ad, 0x100000, 0x11e0c6, 0x1f00a0, 0x1903fb, 0x1903fb,
++ 0x1903fb, 0x1903fb, 0x1903fb, 0x1903fb, 0x1903fb, 0x1903fb, 0x1f00ad, 0x110000, 0x120400, 0x130093,
++ 0x140000, 0x150193, 0x160000, 0x170213, 0x180000, 0x12040c, 0x130293, 0x140000, 0x150313, 0x160000,
++ 0x170393, 0x180000, 0x120418, 0x130413, 0x140000, 0x150493, 0x160000, 0x170513, 0x180000, 0x120424,
++ 0x130593, 0x140000, 0x150613, 0x160000, 0x170693, 0x180000, 0x120430, 0x130713, 0x140000, 0x150793,
++ 0x160000, 0x171137, 0x180000, 0x12043c, 0x13006f, 0x140060, 0x15a001, 0x160113, 0x17fd41, 0x18d026,
++ 0x120448, 0x13d406, 0x14d222, 0x1517b7, 0x160800, 0x17aa23, 0x189407, 0x120454, 0x130713, 0x1430f0,
++ 0x1567b7, 0x160800, 0x17a423, 0x1846e7, 0x120460, 0x13a703, 0x14a587, 0x156685, 0x168f55, 0x17ac23,
++ 0x18a4e7, 0x12046c, 0x1367b9, 0x145737, 0x150800, 0x168793, 0x17ef27, 0x182023, 0x120478, 0x1374f7,
++ 0x1407b7, 0x150800, 0x165bfc, 0x17d493, 0x180037, 0x120484, 0x13f493, 0x141f04, 0x15f793, 0x1607f7,
++ 0x178fc5, 0x18c03e, 0x120490, 0x134702, 0x140793, 0x150210, 0x160763, 0x1700f7, 0x180793, 0x12049c,
++ 0x130270, 0x140c63, 0x1530f7, 0x16a001, 0x1707b7, 0x180002, 0x1204a8, 0x138793, 0x146967, 0x15c83e,
++ 0x1617b7, 0x170002, 0x188793, 0x1204b4, 0x13e567, 0x14c43e, 0x1537b7, 0x160002, 0x178793, 0x186867,
++ 0x1204c0, 0x13c23e, 0x1447b7, 0x150002, 0x168793, 0x17e9a7, 0x1866b7, 0x1204cc, 0x130800, 0x14ca3e,
++ 0x15a783, 0x166d86, 0x1775c1, 0x188713, 0x1204d8, 0x130ff5, 0x148ff9, 0x156735, 0x160713, 0x178007,
++ 0x188fd9, 0x1204e4, 0x13ac23, 0x146cf6, 0x15a783, 0x1665c6, 0x175737, 0x180800, 0x1204f0, 0x136611,
++ 0x14f793, 0x15f0f7, 0x16e793, 0x170807, 0x18ae23, 0x1204fc, 0x1364f6, 0x142783, 0x155c47, 0x169bf5,
++ 0x172223, 0x185cf7, 0x120508, 0x13a703, 0x14f5c6, 0x158f51, 0x16ae23, 0x17f4e6, 0x180737, 0x120514,
++ 0x130809, 0x14433c, 0x158fd1, 0x16c33c, 0x170637, 0x180800, 0x120520, 0x134a74, 0x14679d, 0x158793,
++ 0x160e07, 0x179ae1, 0x18e693, 0x12052c, 0x130036, 0x14ca74, 0x154678, 0x1676e1, 0x178693, 0x185006,
++ 0x120538, 0x138ff9, 0x148fd5, 0x1507c2, 0x168f6d, 0x1783c1, 0x188fd9, 0x120544, 0x13c67c, 0x140713,
++ 0x151000, 0x160793, 0x170000, 0x189c23, 0x120550, 0x1324e7, 0x140713, 0x151010, 0x169123, 0x1726e7,
++ 0x18470d, 0x12055c, 0x13c63a, 0x144702, 0x158d23, 0x162407, 0x17a223, 0x182607, 0x120568, 0x130793,
++ 0x140270, 0x150413, 0x160000, 0x171463, 0x1800f7, 0x120574, 0x134789, 0x14c63e, 0x154709, 0x16cc3a,
++ 0x174702, 0x180793, 0x120580, 0x130270, 0x141463, 0x1500f7, 0x16478d, 0x17cc3e, 0x180513, 0x12058c,
++ 0x130000, 0x144792, 0x154581, 0x164485, 0x179782, 0x184018, 0x120598, 0x131775, 0x14e563, 0x1502e4,
++ 0x162703, 0x170a04, 0x181163, 0x1205a4, 0x130297, 0x144818, 0x150563, 0x160097, 0x1747a2, 0x18c804,
++ 0x1205b0, 0x139782, 0x1466b7, 0x150800, 0x16a703, 0x174c46, 0x189b71, 0x1205bc, 0x136713, 0x140027,
++ 0x15a223, 0x164ce6, 0x174783, 0x180fd4, 0x1205c8, 0x13c7b9, 0x142683, 0x151004, 0x164745, 0x179763,
++ 0x1820e6, 0x1205d4, 0x133737, 0x140822, 0x152683, 0x163007, 0x177645, 0x18167d, 0x1205e0, 0x138ef1,
++ 0x142023, 0x1530d7, 0x162683, 0x172807, 0x18e693, 0x1205ec, 0x131006, 0x142023, 0x1528d7, 0x162683,
++ 0x173807, 0x18e693, 0x1205f8, 0x131006, 0x142023, 0x1538d7, 0x162683, 0x174007, 0x18e693, 0x120604,
++ 0x131006, 0x142023, 0x1540d7, 0x162683, 0x174807, 0x18e693, 0x120610, 0x131006, 0x142023, 0x1548d7,
++ 0x1656b7, 0x170800, 0x18a703, 0x12061c, 0x133486, 0x14830d, 0x158b05, 0x16cf01, 0x17a703, 0x185c46,
++ 0x120628, 0x137671, 0x14167d, 0x158f71, 0x166611, 0x17a223, 0x185ce6, 0x120634, 0x138f51, 0x14a223,
++ 0x155ce6, 0x162703, 0x171084, 0x1846b2, 0x120640, 0x131c63, 0x1402d7, 0x153737, 0x160822, 0x172683,
++ 0x182807, 0x12064c, 0x13e693, 0x140016, 0x152023, 0x1628d7, 0x172683, 0x183807, 0x120658, 0x13e693,
++ 0x140016, 0x152023, 0x1638d7, 0x172683, 0x184007, 0x120664, 0x13e693, 0x140016, 0x152023, 0x1640d7,
++ 0x172683, 0x184807, 0x120670, 0x13e693, 0x140016, 0x152023, 0x1648d7, 0x172703, 0x181004, 0x12067c,
++ 0x1346b2, 0x149c63, 0x151ae6, 0x160737, 0x170800, 0x184b78, 0x120688, 0x130693, 0x140ff0, 0x15463d,
++ 0x168b1d, 0x17ce3a, 0x1852b7, 0x120694, 0x130800, 0x144701, 0x154389, 0x16408d, 0x174311, 0x180537,
++ 0x1206a0, 0x130820, 0x141593, 0x150077, 0x1695aa, 0x17418c, 0x184572, 0x1206ac, 0x1305c2, 0x1481c1,
++ 0x1581a9, 0x167763, 0x1700b5, 0x189533, 0x1206b8, 0x1300e4, 0x144513, 0x15fff5, 0x168e69, 0x170537,
++ 0x180800, 0x1206c4, 0x134568, 0x148121, 0x15893d, 0x167463, 0x1702b5, 0x18a583, 0x1206d0, 0x1306c2,
++ 0x140763, 0x151277, 0x160a63, 0x171217, 0x1805c2, 0x1206dc, 0x1381c1, 0x14818d, 0x150d63, 0x161097,
++ 0x178985, 0x180586, 0x1206e8, 0x1395b3, 0x1400b4, 0x15c593, 0x16fff5, 0x178eed, 0x180705, 0x1206f4,
++ 0x1315e3, 0x14fa67, 0x1535b7, 0x160822, 0x17a703, 0x183005, 0x120700, 0x13757d, 0x148a3d, 0x150513,
++ 0x160ff5, 0x178f69, 0x180622, 0x12070c, 0x138e59, 0x14a023, 0x1530c5, 0x168637, 0x170800, 0x185a38,
++ 0x120718, 0x1375c1, 0x14f693, 0x150ff6, 0x168593, 0x170ff5, 0x188f6d, 0x120724, 0x1306a2, 0x148ed9,
++ 0x15da34, 0x164682, 0x170713, 0x180210, 0x120730, 0x139163, 0x140ee6, 0x154711, 0x16e391, 0x17471d,
++ 0x182023, 0x12073c, 0x1310e4, 0x142683, 0x150a04, 0x16471d, 0x179e63, 0x1800e6, 0x120748, 0x136737,
++ 0x140800, 0x152703, 0x164cc7, 0x170693, 0x184000, 0x120754, 0x137713, 0x144807, 0x151463, 0x1600d7,
++ 0x172223, 0x180e04, 0x120760, 0x134018, 0x141163, 0x150497, 0x165703, 0x1700c4, 0x181793, 0x12076c,
++ 0x130117, 0x14db63, 0x150207, 0x168737, 0x170800, 0x184778, 0x120778, 0x137713, 0x140807, 0x15e705,
++ 0x160513, 0x170000, 0x184792, 0x120784, 0x134581, 0x149782, 0x1547a2, 0x164711, 0x17c818, 0x18c004,
++ 0x120790, 0x130d23, 0x140094, 0x150ca3, 0x160004, 0x179782, 0x1856b7, 0x12079c, 0x130800, 0x1442b8,
++ 0x159b71, 0x16c2b8, 0x170513, 0x180000, 0x1207a8, 0x1347d2, 0x149782, 0x154703, 0x162684, 0x1703e3,
++ 0x18de07, 0x1207b4, 0x13bbd9, 0x1407b7, 0x150002, 0x168793, 0x1765c7, 0x18c83e, 0x1207c0, 0x1327b7,
++ 0x140002, 0x158793, 0x16dae7, 0x17c43e, 0x1847b7, 0x1207cc, 0x130002, 0x148793, 0x151427, 0x16c23e,
++ 0x1757b7, 0x180002, 0x1207d8, 0x138793, 0x149867, 0x15b1fd, 0x162683, 0x171504, 0x184709, 0x1207e4,
++ 0x1399e3, 0x14e2e6, 0x1536b7, 0x160822, 0x17a703, 0x183006, 0x1207f0, 0x13663d, 0x148f51, 0x15a023,
++ 0x1630e6, 0x17bd39, 0x18c593, 0x1207fc, 0x130015, 0x14b5dd, 0x158991, 0x1635b3, 0x1700b0, 0x180589,
++ 0x120808, 0x13bdf9, 0x148991, 0x15b593, 0x160015, 0x17bfdd, 0x180737, 0x120814, 0x130800, 0x144f28,
++ 0x15cf89, 0x1647c2, 0x17893d, 0x189782, 0x120820, 0x1347e2, 0x140713, 0x151000, 0x162223, 0x1710e4,
++ 0x182423, 0x12082c, 0x1310f4, 0x14474d, 0x15b729, 0x168111, 0x17b7dd, 0x1814e3, 0x120838, 0x13f097,
++ 0x140737, 0x150800, 0x164770, 0x171713, 0x180106, 0x120844, 0x135d63, 0x140607, 0x1585b7, 0x160800,
++ 0x17a683, 0x180d05, 0x120850, 0x1372c5, 0x147313, 0x1500f6, 0x1612fd, 0x17a703, 0x180d45, 0x12085c,
++ 0x131513, 0x1400c3, 0x15f6b3, 0x160056, 0x178ec9, 0x18757d, 0x120868, 0x130393, 0x140ff5, 0x151293,
++ 0x160083, 0x17f6b3, 0x180076, 0x120874, 0x139b41, 0x148211, 0x15e2b3, 0x160056, 0x171093, 0x180043,
++ 0x120880, 0x137693, 0x140016, 0x156333, 0x160067, 0x170613, 0x187ff5, 0x12088c, 0x139713, 0x1400b6,
++ 0x157633, 0x1600c3, 0x178e59, 0x189513, 0x120898, 0x1300a6, 0x147613, 0x159ff6, 0x169713, 0x170096,
++ 0x188e49, 0x1208a4, 0x13f293, 0x14f0f2, 0x158e59, 0x16e2b3, 0x170012, 0x1806a2, 0x1208b0, 0x137613,
++ 0x14eff6, 0x158e55, 0x16a823, 0x170c55, 0x18aa23, 0x1208bc, 0x130cc5, 0x1480e3, 0x15e807, 0x1646b7,
++ 0x170822, 0x18a703, 0x1208c8, 0x13f006, 0x149b61, 0x156713, 0x160027, 0x17a023, 0x18f0e6, 0x1208d4,
++ 0x13b5ad, 0x140000, 0x150000, 0x160000, 0x170000, 0x180000, 0x110000, 0x120400, 0x104000, 0x1f0000,
++};
++
++int jl2xxx_pre_init(struct phy_device *phydev)
++{
++ int i, j;
++ int regaddr, val;
++ int length = sizeof(init_data)/sizeof(init_data[0]);
++
++ for (i = 0; i < length; i++) {
++ regaddr = ((init_data[i] >> 16) & 0xff);
++ val = (init_data[i] & 0xffff);
++ phy_write(phydev, regaddr, val);
++ if (regaddr == 0x18) {
++ phy_write(phydev, 0x10, 0x8006);
++ for (j = 0; j < 8; j++) {
++ if (phy_read(phydev, 0x10) == 0) {
++ break;
++ }
++ }
++ }
++ }
++
++ return 0;
++}
++
++int enable_wol(struct phy_device *phydev)
++{
++ jlsemi_set_bits(phydev, WOL_CTL_PAGE,
++ WOL_CTL_REG, WOL_EN);
++
++ jlsemi_clear_bits(phydev, WOL_CTL_STAS_PAGE,
++ WOL_CTL_STAS_REG, WOL_CTL_EN);
++
++ return 0;
++}
++
++int disable_wol(struct phy_device *phydev)
++{
++ jlsemi_clear_bits(phydev, WOL_CTL_PAGE,
++ WOL_CTL_REG, WOL_EN);
++
++ jlsemi_set_bits(phydev, BASIC_PAGE, BMCR_REG, SOFT_RESET);
++ /* wait soft reset complete*/
++ msleep(20);
++
++ return 0;
++}
++
++int setup_wol_low_polarity(struct phy_device *phydev)
++{
++ jlsemi_clear_bits(phydev, WOL_CTL_STAS_PAGE,
++ WOL_CTL_STAS_REG, WOL_POLARITY);
++ return 0;
++}
++
++int setup_wol_high_polarity(struct phy_device *phydev)
++{
++ jlsemi_set_bits(phydev, WOL_CTL_STAS_PAGE,
++ WOL_CTL_STAS_REG, WOL_POLARITY);
++ return 0;
++}
++
++int clear_wol_event(struct phy_device *phydev)
++{
++ jlsemi_set_bits(phydev, WOL_CTL_STAS_PAGE,
++ WOL_CTL_STAS_REG, WOL_EVENT);
++
++ jlsemi_clear_bits(phydev, WOL_CTL_STAS_PAGE,
++ WOL_CTL_STAS_REG, WOL_EVENT);
++ return 0;
++}
++
++int store_mac_addr(struct phy_device *phydev)
++{
++ int err;
++
++ jlsemi_write_page(phydev, WOL_CTL_STAS_PAGE);
++
++ /* Store the device address for the magic packet */
++ err = phy_write(phydev, WOL_MAC_ADDR2_REG,
++ ((phydev->attached_dev->dev_addr[0] << 8) |
++ phydev->attached_dev->dev_addr[1]));
++ if (err < 0)
++ return err;
++ err = phy_write(phydev, WOL_MAC_ADDR1_REG,
++ ((phydev->attached_dev->dev_addr[2] << 8) |
++ phydev->attached_dev->dev_addr[3]));
++ if (err < 0)
++ return err;
++ err = phy_write(phydev, WOL_MAC_ADDR0_REG,
++ ((phydev->attached_dev->dev_addr[4] << 8) |
++ phydev->attached_dev->dev_addr[5]));
++ if (err < 0)
++ return err;
++
++ /* change page to 0 */
++ jlsemi_write_page(phydev, BASIC_PAGE);
++
++ return 0;
++}
++
++int config_phy_info(struct phy_device *phydev,
++ struct jl2xx1_priv *jl2xx1)
++{
++ int val, major, minor;
++
++ val = phy_read(phydev, 29);
++ if (val < 0)
++ return val;
++
++ major = (val >> 7) & 0x1f;
++ minor = (val >> 0) & 0x7f;
++ /* major enlarge 10 */
++ jl2xx1->sw_info = major * 10 + minor;
++
++ return 0;
++}
++
++/********************** Convenience function for phy **********************/
++
++/**
++ * jlsemi_write_page() - write the page register
++ * @phydev: a pointer to a &struct phy_device
++ * @page: page values
++ */
++int jlsemi_write_page(struct phy_device *phydev, int page)
++{
++ return phy_write(phydev, MII_JLSEMI_PHY_PAGE, page);
++}
++
++/**
++ * jlsemi_read_page() - write the page register
++ * @phydev: a pointer to a &struct phy_device
++ *
++ * Return: get page values at present
++ */
++int jlsemi_read_page(struct phy_device *phydev)
++{
++ return phy_read(phydev, MII_JLSEMI_PHY_PAGE);
++}
++
++/**
++ * __jlsemi_save_page() - save the page value
++ *@phydev: a pointer to a &struct phy_device
++ *
++ * Return: save page value
++ */
++static inline int __jlsemi_save_page(struct phy_device *phydev)
++{
++ return jlsemi_read_page(phydev);
++}
++
++/**
++ * __jlsemi_select_page() - restore the page register
++ * @phydev: a pointer to a &struct phy_device
++ * @page: the page
++ *
++ * Return:
++ * @oldpgae: this is last page value
++ * @ret: if page is change it will return new page value
++ */
++static inline int __jlsemi_select_page(struct phy_device *phydev, int page)
++{
++ int ret, oldpage;
++
++ oldpage = ret = __jlsemi_save_page(phydev);
++ if (ret < 0)
++ return ret;
++
++ if (oldpage != page) {
++ ret = jlsemi_write_page(phydev, page);
++ if (ret < 0)
++ return ret;
++ }
++
++ return oldpage;
++}
++
++/**
++ * __jlsemi_restore_page() - restore the page register
++ * @phydev: a pointer to a &struct phy_device
++ * @oldpage: the old page, return value from __jlsemi_save_page() or
++ * __jlsemi_select_page()
++ * @ret: operation's return code
++ *
++ * Returns:
++ * @oldpage if it was a negative value, otherwise
++ * @ret if it was a negative errno value, otherwise
++ * phy_write_page()'s negative value if it were in error, otherwise
++ * @ret
++ */
++static inline int __jlsemi_restore_page(struct phy_device *phydev,
++ int oldpage, int ret)
++{
++ int r;
++
++ if (oldpage >= 0) {
++ r = jlsemi_write_page(phydev, oldpage);
++
++ /* Propagate the operation return code if the page write
++ * was successful.
++ */
++ if (ret >= 0 && r < 0)
++ ret = r;
++ } else {
++ /* Propagate the phy page selection error code */
++ ret = oldpage;
++ }
++
++ return ret;
++}
++
++/**
++ * __jlsemi_modify_reg() - Convenience function for modifying a PHY register
++ * @phydev: a pointer to a &struct phy_device
++ * @regnum: register number
++ * @mask: bit mask of bits to clear
++ * @set: bit mask of bits to set
++ *
++ * Returns negative errno, 0 if there was no change, and 1 in case of change
++ */
++static inline int __jlsemi_modify_reg(struct phy_device *phydev,
++ u32 regnum, u16 mask, u16 set)
++{
++ int newval, ret;
++
++ ret = phy_read(phydev, regnum);
++ if (ret < 0)
++ return ret;
++
++ newval = (ret & ~mask) | set;
++ if (newval == ret)
++ return 0;
++
++ ret = phy_write(phydev, regnum, newval);
++
++ return ret < 0 ? ret : 1;
++}
++
++/**
++ * jlsemi_modify_paged_reg() - Function for modifying a paged register
++ * @phydev: a pointer to a &struct phy_device
++ * @page: the page for the phy
++ * @regnum: register number
++ * @mask: bit mask of bits to clear
++ * @set: bit mask of bits to set
++ *
++ * Returns negative errno, 0 if there was no change, and 1 in case of change
++ */
++int jlsemi_modify_paged_reg(struct phy_device *phydev,
++ int page, u32 regnum,
++ u16 mask, u16 set)
++{
++ int ret = 0, oldpage;
++
++ oldpage = __jlsemi_select_page(phydev, page);
++ if (oldpage >= 0)
++ ret = __jlsemi_modify_reg(phydev, regnum, mask, set);
++
++ return __jlsemi_restore_page(phydev, oldpage, ret);
++}
++
++/**
++ * jlsemi_set_bits() - Convenience function for setting bits in a PHY register
++ * @phydev: a pointer to a &struct phy_device
++ * @page: the page for the phy
++ * @regnum: register number to write
++ * @val: bits to set
++ */
++int jlsemi_set_bits(struct phy_device *phydev,
++ int page, u32 regnum, u16 val)
++{
++ return jlsemi_modify_paged_reg(phydev, page, regnum, 0, val);
++}
++
++/**
++ * jlsemi_clear_bits - Convenience function for clearing bits in a PHY register
++ * @phydev: the phy_device struct
++ * @page: the page for the phy
++ * @regnum: register number to write
++ * @val: bits to clear
++ */
++int jlsemi_clear_bits(struct phy_device *phydev,
++ int page, u32 regnum, u16 val)
++{
++ return jlsemi_modify_paged_reg(phydev, page, regnum, val, 0);
++}
++
++/**
++ * jlsemi_get_bit() - Convenience function for setting bits in a PHY register
++ * @phydev: a pointer to a &struct phy_device
++ * @page: the page for the phy
++ * @regnum: register number to write
++ * @val: bit to get
++ *
++ * Note:
++ * you only get one bit at meanwhile
++ *
++ */
++int jlsemi_get_bit(struct phy_device *phydev,
++ int page, u32 regnum, u16 val)
++{
++ int ret = 0, oldpage;
++
++ oldpage = __jlsemi_select_page(phydev, page);
++ if (oldpage >= 0)
++ {
++ ret = phy_read(phydev, regnum);
++ if (ret < 0)
++ return ret;
++ ret = ((ret & val) == val) ? 1 : 0;
++ }
++
++ return __jlsemi_restore_page(phydev, oldpage, ret);
++}
+--- /dev/null
++++ b/drivers/net/phy/jl2xxx-core.h
+@@ -0,0 +1,104 @@
++/*
++ * Copyright (C) 2021 JLSemi Corporation
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation version 2.
++ *
++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
++ * kind, whether express or implied; without even the implied warranty
++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ */
++#ifndef _JLSEMI_CORE_H
++#define _JLSEMI_CORE_H
++
++#include <linux/phy.h>
++#include <linux/version.h>
++#include <linux/kernel.h>
++
++#define JL2XX1_PHY_ID 0x937c4030
++#define JLSEMI_PHY_ID_MASK 0xfffffff0
++
++#define JL2101_PHY_ID 0x937c4032
++
++#define MII_JLSEMI_PHY_PAGE 0x1f
++
++#define WOL_CTL_PAGE 18
++#define WOL_CTL_REG 21
++#define WOL_CTL_STAS_PAGE 4608
++#define WOL_CTL_STAS_REG 16
++#define WOL_MAC_ADDR2_REG 17
++#define WOL_MAC_ADDR1_REG 18
++#define WOL_MAC_ADDR0_REG 19
++#define WOL_EVENT BIT(1)
++#define WOL_POLARITY BIT(14)
++#define WOL_EN BIT(6)
++#define WOL_CTL_EN BIT(15)
++
++
++/************************* Configuration section *************************/
++
++#define JLSEMI_WOL_EN 0
++
++
++/************************* JLSemi iteration code *************************/
++struct jl2xx1_priv {
++ u16 sw_info;
++};
++
++int jl2xxx_pre_init(struct phy_device *phydev);
++
++int config_phy_info(struct phy_device *phydev,
++ struct jl2xx1_priv *jl2xx1);
++
++int check_rgmii(struct phy_device *phydev);
++
++int dis_rgmii_tx_ctrl(struct phy_device *phydev);
++
++int config_suspend(struct phy_device *phydev);
++
++int config_resume(struct phy_device *phydev);
++
++int enable_wol(struct phy_device *phydev);
++
++int disable_wol(struct phy_device *phydev);
++
++int setup_wol_low_polarity(struct phy_device *phydev);
++
++int setup_wol_high_polarity(struct phy_device *phydev);
++
++int clear_wol_event(struct phy_device *phydev);
++
++int store_mac_addr(struct phy_device *phydev);
++
++int software_version(struct phy_device *phydev);
++
++
++/********************** Convenience function for phy **********************/
++
++/* Notice: You should change page 0 when you When you call it after*/
++int jlsemi_write_page(struct phy_device *phydev, int page);
++
++int jlsemi_read_page(struct phy_device *phydev);
++
++int jlsemi_modify_paged_reg(struct phy_device *phydev,
++ int page, u32 regnum,
++ u16 mask, u16 set);
++
++int jlsemi_set_bits(struct phy_device *phydev,
++ int page, u32 regnum, u16 val);
++
++int jlsemi_clear_bits(struct phy_device *phydev,
++ int page, u32 regnum, u16 val);
++
++int jlsemi_get_bit(struct phy_device *phydev,
++ int page, u32 regnum, u16 val);
++
++int jlsemi_drivers_register(struct phy_driver *phydrvs, int size);
++
++void jlsemi_drivers_unregister(struct phy_driver *phydrvs, int size);
++
++#endif /* _JLSEMI_CORE_H */
++
+--- /dev/null
++++ b/drivers/net/phy/jl2xxx.c
+@@ -0,0 +1,126 @@
++/*
++ * drivers/net/phy/jlsemi.c
++ *
++ * Driver for JLSemi PHYs
++ *
++ * Author: Gangqiao Kuang <gqkuang@jlsemi.com>
++ *
++ * Copyright (c) 2021 JingLue Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ */
++#include "jl2xxx-core.h"
++#include <linux/phy.h>
++#include <linux/module.h>
++#include <linux/netdevice.h>
++
++
++MODULE_DESCRIPTION("JLSemi PHY driver");
++MODULE_AUTHOR("Gangqiao Kuang");
++MODULE_LICENSE("GPL");
++
++static int jlsemi_probe(struct phy_device *phydev)
++{
++ int err;
++
++ err = jl2xxx_pre_init(phydev);
++
++ /* wait load complete*/
++ msleep(20);
++
++ return (err < 0) ? err : 0;
++}
++
++#if JLSEMI_WOL_EN
++static void jlsemi_get_wol(struct phy_device *phydev,
++ struct ethtool_wolinfo *wol)
++{
++ int wol_en;
++
++ wol->supported = WAKE_MAGIC;
++ wol->wolopts = 0;
++
++ wol_en = jlsemi_get_bit(phydev, WOL_CTL_PAGE,
++ WOL_CTL_REG, WOL_EN);
++
++ if (wol_en)
++ wol->wolopts |= WAKE_MAGIC;
++}
++
++static int jlsemi_set_wol(struct phy_device *phydev,
++ struct ethtool_wolinfo *wol)
++{
++ int err;
++
++ if (wol->wolopts & WAKE_MAGIC) {
++ err = enable_wol(phydev);
++ if (err < 0)
++ return err;
++
++ err = clear_wol_event(phydev);
++ if (err < 0)
++ return err;
++
++ err = setup_wol_high_polarity(phydev);
++ if (err < 0)
++ return err;
++
++ err = store_mac_addr(phydev);
++ if (err < 0)
++ return err;
++ } else {
++ err = disable_wol(phydev);
++ if (err < 0)
++ return err;
++
++ err = setup_wol_high_polarity(phydev);
++ if (err < 0)
++ return err;
++
++ err = clear_wol_event(phydev);
++ if (err < 0)
++ return err;
++ }
++
++ return 0;
++}
++#endif
++
++static struct phy_driver jlsemi_driver[] = {
++ {
++ PHY_ID_MATCH_EXACT(JL2101_PHY_ID),
++ .name = "JL2101 Gigabit Ethernet",
++ /* PHY_BASIC_FEATURES */
++ .features = PHY_GBIT_FEATURES,
++ .probe = jlsemi_probe,
++ #if JLSEMI_WOL_EN
++ .get_wol = jlsemi_get_wol,
++ .set_wol = jlsemi_set_wol,
++ #endif
++ },
++ {
++ PHY_ID_MATCH_MODEL(JL2XX1_PHY_ID),
++ .name = "JL2xx1 Gigabit Ethernet",
++ /* PHY_BASIC_FEATURES */
++ .features = PHY_GBIT_FEATURES,
++ .probe = jlsemi_probe,
++ #if JLSEMI_WOL_EN
++ .get_wol = jlsemi_get_wol,
++ .set_wol = jlsemi_set_wol,
++ #endif
++ },
++};
++
++module_phy_driver(jlsemi_driver);
++
++static struct mdio_device_id __maybe_unused jlsemi_tbl[] = {
++ { PHY_ID_MATCH_EXACT(JL2101_PHY_ID) },
++ { PHY_ID_MATCH_MODEL(JL2XX1_PHY_ID) },
++ { }
++};
++
++MODULE_DEVICE_TABLE(mdio, jlsemi_tbl);
diff --git a/target/linux/rockchip/patches-5.19/0900-arm-boot-add-dts-files.patch b/target/linux/rockchip/patches-5.19/0900-arm-boot-add-dts-files.patch
new file mode 100644
index 00000000000000..eb2b744dca05b3
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0900-arm-boot-add-dts-files.patch
@@ -0,0 +1,34 @@
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -9,8 +9,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-doornet1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-neo3.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
+@@ -22,6 +26,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-or
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-doornet2.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-doornet2-4gb.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb
+@@ -40,6 +46,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-na
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4b.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4se.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-guangmiao-g4c.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
diff --git a/target/linux/rockchip/patches-5.19/0901-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch b/target/linux/rockchip/patches-5.19/0901-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch
new file mode 100644
index 00000000000000..87176a05385886
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0901-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch
@@ -0,0 +1,21 @@
+--- a/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi
+@@ -3,6 +3,7 @@
+ /dts-v1/;
+ #include <dt-bindings/input/linux-event-codes.h>
+ #include "rk3399.dtsi"
++#include "rk3399-nanopi4-opp.dtsi"
+
+ / {
+ chosen {
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+@@ -14,7 +14,7 @@
+ /dts-v1/;
+ #include <dt-bindings/input/linux-event-codes.h>
+ #include "rk3399.dtsi"
+-#include "rk3399-opp.dtsi"
++#include "rk3399-nanopi4-opp.dtsi"
+
+ / {
+ aliases {
diff --git a/target/linux/rockchip/patches-5.19/0902-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch b/target/linux/rockchip/patches-5.19/0902-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch
new file mode 100644
index 00000000000000..d9145299e8769a
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0902-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch
@@ -0,0 +1,44 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Leonidas P. Papadakos <papadakospan@gmail.com>
+Date: Fri, 1 Mar 2019 21:55:53 +0200
+Subject: [PATCH v2] arm64: dts: rockchip: add more cpu operating points for
+ RK3328
+
+This allows for greater max frequency on rk3328 boards,
+increasing performance.
+
+It has been included in Armbian (a linux distibution for ARM boards)
+for a while now without any reported issues
+
+https://github.com/armbian/build/blob/master/patch/kernel/rockchip64-default/enable-1392mhz-opp.patch
+https://github.com/armbian/build/blob/master/patch/kernel/rockchip64-default/enable-1512mhz-opp.patch
+
+Signed-off-by: Leonidas P. Papadakos <papadakospan@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 15 +++++++++++++++
+ 1 files changed, 15 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -140,6 +140,21 @@
+ opp-microvolt = <1300000>;
+ clock-latency-ns = <40000>;
+ };
++ opp-1392000000 {
++ opp-hz = /bits/ 64 <1392000000>;
++ opp-microvolt = <1350000>;
++ clock-latency-ns = <40000>;
++ };
++ opp-1512000000 {
++ opp-hz = /bits/ 64 <1512000000>;
++ opp-microvolt = <1400000>;
++ clock-latency-ns = <40000>;
++ };
++ opp-1608000000 {
++ opp-hz = /bits/ 64 <1608000000>;
++ opp-microvolt = <1450000>;
++ clock-latency-ns = <40000>;
++ };
+ };
+
+ analog_sound: analog-sound {
diff --git a/target/linux/rockchip/patches-5.19/0903-crypto-rockchip-permit-to-pass-self-tests.patch b/target/linux/rockchip/patches-5.19/0903-crypto-rockchip-permit-to-pass-self-tests.patch
new file mode 100644
index 00000000000000..af346f09d6bed5
--- /dev/null
+++ b/target/linux/rockchip/patches-5.19/0903-crypto-rockchip-permit-to-pass-self-tests.patch
@@ -0,0 +1,2419 @@
+From patchwork Wed Jul 6 09:03:40 2022
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: LABBE Corentin <clabbe@baylibre.com>
+X-Patchwork-Id: 12907886
+Return-Path:
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+ by smtp.lore.kernel.org (Postfix) with ESMTPS id 80701C43334
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+ Wed, 06 Jul 2022 02:04:33 -0700 (PDT)
+From: Corentin Labbe <clabbe@baylibre.com>
+To: heiko@sntech.de,
+ herbert@gondor.apana.org.au,
+ krzysztof.kozlowski+dt@linaro.org,
+ mturquette@baylibre.com,
+ p.zabel@pengutronix.de,
+ robh+dt@kernel.org,
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+Cc: linux-rockchip@lists.infradead.org,
+ devicetree@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org,
+ linux-clk@vger.kernel.org,
+ linux-crypto@vger.kernel.org,
+ linux-kernel@vger.kernel.org,
+ john@metanate.com,
+ didi.debian@cknow.org,
+ Corentin Labbe <clabbe@baylibre.com>
+Subject: [PATCH v8 01/33] crypto: rockchip: use dev_err for error message
+ about interrupt
+Date: Wed, 6 Jul 2022 09:03:40 +0000
+Message-Id: <20220706090412.806101-2-clabbe@baylibre.com>
+X-Mailer: git-send-email 2.25.1
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+References: <20220706090412.806101-1-clabbe@baylibre.com>
+MIME-Version: 1.0
+X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3
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+List-Id: Upstream kernel work for Rockchip platforms
+ <linux-rockchip.lists.infradead.org>
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+
+Interrupt is mandatory so the message should be printed as error.
+
+Reviewed-by: John Keeping <john@metanate.com>
+Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+---
+ drivers/crypto/rockchip/rk3288_crypto.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/crypto/rockchip/rk3288_crypto.c
++++ b/drivers/crypto/rockchip/rk3288_crypto.c
+@@ -14,235 +14,162 @@
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/of.h>
++#include <linux/of_device.h>
+ #include <linux/clk.h>
+ #include <linux/crypto.h>
+ #include <linux/reset.h>
+
+-static int rk_crypto_enable_clk(struct rk_crypto_info *dev)
++static struct rockchip_ip rocklist = {
++ .dev_list = LIST_HEAD_INIT(rocklist.dev_list),
++ .lock = __SPIN_LOCK_UNLOCKED(rocklist.lock),
++};
++
++struct rk_crypto_info *get_rk_crypto(void)
+ {
+- int err;
++ struct rk_crypto_info *first;
+
+- err = clk_prepare_enable(dev->sclk);
+- if (err) {
+- dev_err(dev->dev, "[%s:%d], Couldn't enable clock sclk\n",
+- __func__, __LINE__);
+- goto err_return;
+- }
+- err = clk_prepare_enable(dev->aclk);
+- if (err) {
+- dev_err(dev->dev, "[%s:%d], Couldn't enable clock aclk\n",
+- __func__, __LINE__);
+- goto err_aclk;
++ spin_lock(&rocklist.lock);
++ first = list_first_entry_or_null(&rocklist.dev_list,
++ struct rk_crypto_info, list);
++ list_rotate_left(&rocklist.dev_list);
++ spin_unlock(&rocklist.lock);
++ return first;
++}
++
++static const struct rk_variant rk3288_variant = {
++ .num_clks = 4,
++ .rkclks = {
++ { "sclk", 150000000},
+ }
+- err = clk_prepare_enable(dev->hclk);
+- if (err) {
+- dev_err(dev->dev, "[%s:%d], Couldn't enable clock hclk\n",
+- __func__, __LINE__);
+- goto err_hclk;
+- }
+- err = clk_prepare_enable(dev->dmaclk);
+- if (err) {
+- dev_err(dev->dev, "[%s:%d], Couldn't enable clock dmaclk\n",
+- __func__, __LINE__);
+- goto err_dmaclk;
+- }
+- return err;
+-err_dmaclk:
+- clk_disable_unprepare(dev->hclk);
+-err_hclk:
+- clk_disable_unprepare(dev->aclk);
+-err_aclk:
+- clk_disable_unprepare(dev->sclk);
+-err_return:
+- return err;
+-}
++};
+
+-static void rk_crypto_disable_clk(struct rk_crypto_info *dev)
+-{
+- clk_disable_unprepare(dev->dmaclk);
+- clk_disable_unprepare(dev->hclk);
+- clk_disable_unprepare(dev->aclk);
+- clk_disable_unprepare(dev->sclk);
+-}
+-
+-static int check_alignment(struct scatterlist *sg_src,
+- struct scatterlist *sg_dst,
+- int align_mask)
+-{
+- int in, out, align;
+-
+- in = IS_ALIGNED((uint32_t)sg_src->offset, 4) &&
+- IS_ALIGNED((uint32_t)sg_src->length, align_mask);
+- if (!sg_dst)
+- return in;
+- out = IS_ALIGNED((uint32_t)sg_dst->offset, 4) &&
+- IS_ALIGNED((uint32_t)sg_dst->length, align_mask);
+- align = in && out;
+-
+- return (align && (sg_src->length == sg_dst->length));
+-}
+-
+-static int rk_load_data(struct rk_crypto_info *dev,
+- struct scatterlist *sg_src,
+- struct scatterlist *sg_dst)
+-{
+- unsigned int count;
+-
+- dev->aligned = dev->aligned ?
+- check_alignment(sg_src, sg_dst, dev->align_size) :
+- dev->aligned;
+- if (dev->aligned) {
+- count = min(dev->left_bytes, sg_src->length);
+- dev->left_bytes -= count;
+-
+- if (!dma_map_sg(dev->dev, sg_src, 1, DMA_TO_DEVICE)) {
+- dev_err(dev->dev, "[%s:%d] dma_map_sg(src) error\n",
+- __func__, __LINE__);
+- return -EINVAL;
+- }
+- dev->addr_in = sg_dma_address(sg_src);
++static const struct rk_variant rk3328_variant = {
++ .num_clks = 3,
++};
+
+- if (sg_dst) {
+- if (!dma_map_sg(dev->dev, sg_dst, 1, DMA_FROM_DEVICE)) {
+- dev_err(dev->dev,
+- "[%s:%d] dma_map_sg(dst) error\n",
+- __func__, __LINE__);
+- dma_unmap_sg(dev->dev, sg_src, 1,
+- DMA_TO_DEVICE);
+- return -EINVAL;
+- }
+- dev->addr_out = sg_dma_address(sg_dst);
+- }
+- } else {
+- count = (dev->left_bytes > PAGE_SIZE) ?
+- PAGE_SIZE : dev->left_bytes;
+-
+- if (!sg_pcopy_to_buffer(dev->first, dev->src_nents,
+- dev->addr_vir, count,
+- dev->total - dev->left_bytes)) {
+- dev_err(dev->dev, "[%s:%d] pcopy err\n",
+- __func__, __LINE__);
+- return -EINVAL;
+- }
+- dev->left_bytes -= count;
+- sg_init_one(&dev->sg_tmp, dev->addr_vir, count);
+- if (!dma_map_sg(dev->dev, &dev->sg_tmp, 1, DMA_TO_DEVICE)) {
+- dev_err(dev->dev, "[%s:%d] dma_map_sg(sg_tmp) error\n",
+- __func__, __LINE__);
+- return -ENOMEM;
+- }
+- dev->addr_in = sg_dma_address(&dev->sg_tmp);
++static const struct rk_variant rk3399_variant = {
++ .num_clks = 3,
++};
++
++static int rk_crypto_get_clks(struct rk_crypto_info *dev)
++{
++ int i, j, err;
++ unsigned long cr;
+
+- if (sg_dst) {
+- if (!dma_map_sg(dev->dev, &dev->sg_tmp, 1,
+- DMA_FROM_DEVICE)) {
+- dev_err(dev->dev,
+- "[%s:%d] dma_map_sg(sg_tmp) error\n",
+- __func__, __LINE__);
+- dma_unmap_sg(dev->dev, &dev->sg_tmp, 1,
+- DMA_TO_DEVICE);
+- return -ENOMEM;
++ dev->num_clks = devm_clk_bulk_get_all(dev->dev, &dev->clks);
++ if (dev->num_clks < dev->variant->num_clks) {
++ dev_err(dev->dev, "Missing clocks, got %d instead of %d\n",
++ dev->num_clks, dev->variant->num_clks);
++ return -EINVAL;
++ }
++
++ for (i = 0; i < dev->num_clks; i++) {
++ cr = clk_get_rate(dev->clks[i].clk);
++ for (j = 0; j < ARRAY_SIZE(dev->variant->rkclks); j++) {
++ if (dev->variant->rkclks[j].max == 0)
++ continue;
++ if (strcmp(dev->variant->rkclks[j].name, dev->clks[i].id))
++ continue;
++ if (cr > dev->variant->rkclks[j].max) {
++ err = clk_set_rate(dev->clks[i].clk,
++ dev->variant->rkclks[j].max);
++ if (err)
++ dev_err(dev->dev, "Fail downclocking %s from %lu to %lu\n",
++ dev->variant->rkclks[j].name, cr,
++ dev->variant->rkclks[j].max);
++ else
++ dev_info(dev->dev, "Downclocking %s from %lu to %lu\n",
++ dev->variant->rkclks[j].name, cr,
++ dev->variant->rkclks[j].max);
+ }
+- dev->addr_out = sg_dma_address(&dev->sg_tmp);
+ }
+ }
+- dev->count = count;
+ return 0;
+ }
+
+-static void rk_unload_data(struct rk_crypto_info *dev)
++static int rk_crypto_enable_clk(struct rk_crypto_info *dev)
+ {
+- struct scatterlist *sg_in, *sg_out;
++ int err;
+
+- sg_in = dev->aligned ? dev->sg_src : &dev->sg_tmp;
+- dma_unmap_sg(dev->dev, sg_in, 1, DMA_TO_DEVICE);
++ err = clk_bulk_prepare_enable(dev->num_clks, dev->clks);
++ if (err)
++ dev_err(dev->dev, "Could not enable clock clks\n");
+
+- if (dev->sg_dst) {
+- sg_out = dev->aligned ? dev->sg_dst : &dev->sg_tmp;
+- dma_unmap_sg(dev->dev, sg_out, 1, DMA_FROM_DEVICE);
+- }
++ return err;
+ }
+
+-static irqreturn_t rk_crypto_irq_handle(int irq, void *dev_id)
++static void rk_crypto_disable_clk(struct rk_crypto_info *dev)
+ {
+- struct rk_crypto_info *dev = platform_get_drvdata(dev_id);
+- u32 interrupt_status;
++ clk_bulk_disable_unprepare(dev->num_clks, dev->clks);
++}
+
+- spin_lock(&dev->lock);
+- interrupt_status = CRYPTO_READ(dev, RK_CRYPTO_INTSTS);
+- CRYPTO_WRITE(dev, RK_CRYPTO_INTSTS, interrupt_status);
++/*
++ * Power management strategy: The device is suspended until a request
++ * is handled. For avoiding suspend/resume yoyo, the autosuspend is set to 2s.
++ */
++static int rk_crypto_pm_suspend(struct device *dev)
++{
++ struct rk_crypto_info *rkdev = dev_get_drvdata(dev);
+
+- if (interrupt_status & 0x0a) {
+- dev_warn(dev->dev, "DMA Error\n");
+- dev->err = -EFAULT;
+- }
+- tasklet_schedule(&dev->done_task);
++ rk_crypto_disable_clk(rkdev);
++ reset_control_assert(rkdev->rst);
+
+- spin_unlock(&dev->lock);
+- return IRQ_HANDLED;
++ return 0;
+ }
+
+-static int rk_crypto_enqueue(struct rk_crypto_info *dev,
+- struct crypto_async_request *async_req)
++static int rk_crypto_pm_resume(struct device *dev)
+ {
+- unsigned long flags;
++ struct rk_crypto_info *rkdev = dev_get_drvdata(dev);
+ int ret;
+
+- spin_lock_irqsave(&dev->lock, flags);
+- ret = crypto_enqueue_request(&dev->queue, async_req);
+- if (dev->busy) {
+- spin_unlock_irqrestore(&dev->lock, flags);
++ ret = rk_crypto_enable_clk(rkdev);
++ if (ret)
+ return ret;
+- }
+- dev->busy = true;
+- spin_unlock_irqrestore(&dev->lock, flags);
+- tasklet_schedule(&dev->queue_task);
+
+- return ret;
+-}
++ reset_control_deassert(rkdev->rst);
++ return 0;
+
+-static void rk_crypto_queue_task_cb(unsigned long data)
+-{
+- struct rk_crypto_info *dev = (struct rk_crypto_info *)data;
+- struct crypto_async_request *async_req, *backlog;
+- unsigned long flags;
+- int err = 0;
++}
+
+- dev->err = 0;
+- spin_lock_irqsave(&dev->lock, flags);
+- backlog = crypto_get_backlog(&dev->queue);
+- async_req = crypto_dequeue_request(&dev->queue);
++static const struct dev_pm_ops rk_crypto_pm_ops = {
++ SET_RUNTIME_PM_OPS(rk_crypto_pm_suspend, rk_crypto_pm_resume, NULL)
++};
+
+- if (!async_req) {
+- dev->busy = false;
+- spin_unlock_irqrestore(&dev->lock, flags);
+- return;
+- }
+- spin_unlock_irqrestore(&dev->lock, flags);
++static int rk_crypto_pm_init(struct rk_crypto_info *rkdev)
++{
++ int err;
+
+- if (backlog) {
+- backlog->complete(backlog, -EINPROGRESS);
+- backlog = NULL;
+- }
++ pm_runtime_use_autosuspend(rkdev->dev);
++ pm_runtime_set_autosuspend_delay(rkdev->dev, 2000);
+
+- dev->async_req = async_req;
+- err = dev->start(dev);
++ err = pm_runtime_set_suspended(rkdev->dev);
+ if (err)
+- dev->complete(dev->async_req, err);
++ return err;
++ pm_runtime_enable(rkdev->dev);
++ return err;
+ }
+
+-static void rk_crypto_done_task_cb(unsigned long data)
++static void rk_crypto_pm_exit(struct rk_crypto_info *rkdev)
++{
++ pm_runtime_disable(rkdev->dev);
++}
++
++static irqreturn_t rk_crypto_irq_handle(int irq, void *dev_id)
+ {
+- struct rk_crypto_info *dev = (struct rk_crypto_info *)data;
++ struct rk_crypto_info *dev = platform_get_drvdata(dev_id);
++ u32 interrupt_status;
++
++ interrupt_status = CRYPTO_READ(dev, RK_CRYPTO_INTSTS);
++ CRYPTO_WRITE(dev, RK_CRYPTO_INTSTS, interrupt_status);
+
+- if (dev->err) {
+- dev->complete(dev->async_req, dev->err);
+- return;
++ dev->status = 1;
++ if (interrupt_status & 0x0a) {
++ dev_warn(dev->dev, "DMA Error\n");
++ dev->status = 0;
+ }
++ complete(&dev->complete);
+
+- dev->err = dev->update(dev);
+- if (dev->err)
+- dev->complete(dev->async_req, dev->err);
++ return IRQ_HANDLED;
+ }
+
+ static struct rk_crypto_tmp *rk_cipher_algs[] = {
+@@ -257,6 +184,62 @@ static struct rk_crypto_tmp *rk_cipher_a
+ &rk_ahash_md5,
+ };
+
++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG
++static int rk_crypto_debugfs_show(struct seq_file *seq, void *v)
++{
++ struct rk_crypto_info *dd;
++ unsigned int i;
++
++ spin_lock(&rocklist.lock);
++ list_for_each_entry(dd, &rocklist.dev_list, list) {
++ seq_printf(seq, "%s %s requests: %lu\n",
++ dev_driver_string(dd->dev), dev_name(dd->dev),
++ dd->nreq);
++ }
++ spin_unlock(&rocklist.lock);
++
++ for (i = 0; i < ARRAY_SIZE(rk_cipher_algs); i++) {
++ if (!rk_cipher_algs[i]->dev)
++ continue;
++ switch (rk_cipher_algs[i]->type) {
++ case CRYPTO_ALG_TYPE_SKCIPHER:
++ seq_printf(seq, "%s %s reqs=%lu fallback=%lu\n",
++ rk_cipher_algs[i]->alg.skcipher.base.cra_driver_name,
++ rk_cipher_algs[i]->alg.skcipher.base.cra_name,
++ rk_cipher_algs[i]->stat_req, rk_cipher_algs[i]->stat_fb);
++ seq_printf(seq, "\tfallback due to length: %lu\n",
++ rk_cipher_algs[i]->stat_fb_len);
++ seq_printf(seq, "\tfallback due to alignment: %lu\n",
++ rk_cipher_algs[i]->stat_fb_align);
++ seq_printf(seq, "\tfallback due to SGs: %lu\n",
++ rk_cipher_algs[i]->stat_fb_sgdiff);
++ break;
++ case CRYPTO_ALG_TYPE_AHASH:
++ seq_printf(seq, "%s %s reqs=%lu fallback=%lu\n",
++ rk_cipher_algs[i]->alg.hash.halg.base.cra_driver_name,
++ rk_cipher_algs[i]->alg.hash.halg.base.cra_name,
++ rk_cipher_algs[i]->stat_req, rk_cipher_algs[i]->stat_fb);
++ break;
++ }
++ }
++ return 0;
++}
++
++DEFINE_SHOW_ATTRIBUTE(rk_crypto_debugfs);
++#endif
++
++static void register_debugfs(struct rk_crypto_info *crypto_info)
++{
++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG
++ /* Ignore error of debugfs */
++ rocklist.dbgfs_dir = debugfs_create_dir("rk3288_crypto", NULL);
++ rocklist.dbgfs_stats = debugfs_create_file("stats", 0444,
++ rocklist.dbgfs_dir,
++ &rocklist,
++ &rk_crypto_debugfs_fops);
++#endif
++}
++
+ static int rk_crypto_register(struct rk_crypto_info *crypto_info)
+ {
+ unsigned int i, k;
+@@ -264,12 +247,22 @@ static int rk_crypto_register(struct rk_
+
+ for (i = 0; i < ARRAY_SIZE(rk_cipher_algs); i++) {
+ rk_cipher_algs[i]->dev = crypto_info;
+- if (rk_cipher_algs[i]->type == ALG_TYPE_CIPHER)
+- err = crypto_register_skcipher(
+- &rk_cipher_algs[i]->alg.skcipher);
+- else
+- err = crypto_register_ahash(
+- &rk_cipher_algs[i]->alg.hash);
++ switch (rk_cipher_algs[i]->type) {
++ case CRYPTO_ALG_TYPE_SKCIPHER:
++ dev_info(crypto_info->dev, "Register %s as %s\n",
++ rk_cipher_algs[i]->alg.skcipher.base.cra_name,
++ rk_cipher_algs[i]->alg.skcipher.base.cra_driver_name);
++ err = crypto_register_skcipher(&rk_cipher_algs[i]->alg.skcipher);
++ break;
++ case CRYPTO_ALG_TYPE_AHASH:
++ dev_info(crypto_info->dev, "Register %s as %s\n",
++ rk_cipher_algs[i]->alg.hash.halg.base.cra_name,
++ rk_cipher_algs[i]->alg.hash.halg.base.cra_driver_name);
++ err = crypto_register_ahash(&rk_cipher_algs[i]->alg.hash);
++ break;
++ default:
++ dev_err(crypto_info->dev, "unknown algorithm\n");
++ }
+ if (err)
+ goto err_cipher_algs;
+ }
+@@ -277,7 +270,7 @@ static int rk_crypto_register(struct rk_
+
+ err_cipher_algs:
+ for (k = 0; k < i; k++) {
+- if (rk_cipher_algs[i]->type == ALG_TYPE_CIPHER)
++ if (rk_cipher_algs[i]->type == CRYPTO_ALG_TYPE_SKCIPHER)
+ crypto_unregister_skcipher(&rk_cipher_algs[k]->alg.skcipher);
+ else
+ crypto_unregister_ahash(&rk_cipher_algs[i]->alg.hash);
+@@ -290,22 +283,23 @@ static void rk_crypto_unregister(void)
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(rk_cipher_algs); i++) {
+- if (rk_cipher_algs[i]->type == ALG_TYPE_CIPHER)
++ if (rk_cipher_algs[i]->type == CRYPTO_ALG_TYPE_SKCIPHER)
+ crypto_unregister_skcipher(&rk_cipher_algs[i]->alg.skcipher);
+ else
+ crypto_unregister_ahash(&rk_cipher_algs[i]->alg.hash);
+ }
+ }
+
+-static void rk_crypto_action(void *data)
+-{
+- struct rk_crypto_info *crypto_info = data;
+-
+- reset_control_assert(crypto_info->rst);
+-}
+-
+ static const struct of_device_id crypto_of_id_table[] = {
+- { .compatible = "rockchip,rk3288-crypto" },
++ { .compatible = "rockchip,rk3288-crypto",
++ .data = &rk3288_variant,
++ },
++ { .compatible = "rockchip,rk3328-crypto",
++ .data = &rk3328_variant,
++ },
++ { .compatible = "rockchip,rk3399-crypto",
++ .data = &rk3399_variant,
++ },
+ {}
+ };
+ MODULE_DEVICE_TABLE(of, crypto_of_id_table);
+@@ -313,7 +307,7 @@ MODULE_DEVICE_TABLE(of, crypto_of_id_tab
+ static int rk_crypto_probe(struct platform_device *pdev)
+ {
+ struct device *dev = &pdev->dev;
+- struct rk_crypto_info *crypto_info;
++ struct rk_crypto_info *crypto_info, *first;
+ int err = 0;
+
+ crypto_info = devm_kzalloc(&pdev->dev,
+@@ -323,7 +317,16 @@ static int rk_crypto_probe(struct platfo
+ goto err_crypto;
+ }
+
+- crypto_info->rst = devm_reset_control_get(dev, "crypto-rst");
++ crypto_info->dev = &pdev->dev;
++ platform_set_drvdata(pdev, crypto_info);
++
++ crypto_info->variant = of_device_get_match_data(&pdev->dev);
++ if (!crypto_info->variant) {
++ dev_err(&pdev->dev, "Missing variant\n");
++ return -EINVAL;
++ }
++
++ crypto_info->rst = devm_reset_control_array_get_exclusive(dev);
+ if (IS_ERR(crypto_info->rst)) {
+ err = PTR_ERR(crypto_info->rst);
+ goto err_crypto;
+@@ -333,46 +336,19 @@ static int rk_crypto_probe(struct platfo
+ usleep_range(10, 20);
+ reset_control_deassert(crypto_info->rst);
+
+- err = devm_add_action_or_reset(dev, rk_crypto_action, crypto_info);
+- if (err)
+- goto err_crypto;
+-
+- spin_lock_init(&crypto_info->lock);
+-
+ crypto_info->reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(crypto_info->reg)) {
+ err = PTR_ERR(crypto_info->reg);
+ goto err_crypto;
+ }
+
+- crypto_info->aclk = devm_clk_get(&pdev->dev, "aclk");
+- if (IS_ERR(crypto_info->aclk)) {
+- err = PTR_ERR(crypto_info->aclk);
+- goto err_crypto;
+- }
+-
+- crypto_info->hclk = devm_clk_get(&pdev->dev, "hclk");
+- if (IS_ERR(crypto_info->hclk)) {
+- err = PTR_ERR(crypto_info->hclk);
+- goto err_crypto;
+- }
+-
+- crypto_info->sclk = devm_clk_get(&pdev->dev, "sclk");
+- if (IS_ERR(crypto_info->sclk)) {
+- err = PTR_ERR(crypto_info->sclk);
+- goto err_crypto;
+- }
+-
+- crypto_info->dmaclk = devm_clk_get(&pdev->dev, "apb_pclk");
+- if (IS_ERR(crypto_info->dmaclk)) {
+- err = PTR_ERR(crypto_info->dmaclk);
++ err = rk_crypto_get_clks(crypto_info);
++ if (err)
+ goto err_crypto;
+- }
+
+ crypto_info->irq = platform_get_irq(pdev, 0);
+ if (crypto_info->irq < 0) {
+- dev_warn(crypto_info->dev,
+- "control Interrupt is not available.\n");
++ dev_err(&pdev->dev, "control Interrupt is not available.\n");
+ err = crypto_info->irq;
+ goto err_crypto;
+ }
+@@ -382,49 +358,64 @@ static int rk_crypto_probe(struct platfo
+ "rk-crypto", pdev);
+
+ if (err) {
+- dev_err(crypto_info->dev, "irq request failed.\n");
++ dev_err(&pdev->dev, "irq request failed.\n");
+ goto err_crypto;
+ }
+
+- crypto_info->dev = &pdev->dev;
+- platform_set_drvdata(pdev, crypto_info);
++ crypto_info->engine = crypto_engine_alloc_init(&pdev->dev, true);
++ crypto_engine_start(crypto_info->engine);
++ init_completion(&crypto_info->complete);
+
+- tasklet_init(&crypto_info->queue_task,
+- rk_crypto_queue_task_cb, (unsigned long)crypto_info);
+- tasklet_init(&crypto_info->done_task,
+- rk_crypto_done_task_cb, (unsigned long)crypto_info);
+- crypto_init_queue(&crypto_info->queue, 50);
+-
+- crypto_info->enable_clk = rk_crypto_enable_clk;
+- crypto_info->disable_clk = rk_crypto_disable_clk;
+- crypto_info->load_data = rk_load_data;
+- crypto_info->unload_data = rk_unload_data;
+- crypto_info->enqueue = rk_crypto_enqueue;
+- crypto_info->busy = false;
++ err = rk_crypto_pm_init(crypto_info);
++ if (err)
++ goto err_pm;
+
+- err = rk_crypto_register(crypto_info);
+- if (err) {
+- dev_err(dev, "err in register alg");
+- goto err_register_alg;
++ spin_lock(&rocklist.lock);
++ first = list_first_entry_or_null(&rocklist.dev_list,
++ struct rk_crypto_info, list);
++ list_add_tail(&crypto_info->list, &rocklist.dev_list);
++ spin_unlock(&rocklist.lock);
++
++ if (!first) {
++ err = rk_crypto_register(crypto_info);
++ if (err) {
++ dev_err(dev, "Fail to register crypto algorithms");
++ goto err_register_alg;
++ }
++
++ register_debugfs(crypto_info);
+ }
+
+- dev_info(dev, "Crypto Accelerator successfully registered\n");
+ return 0;
+
+ err_register_alg:
+- tasklet_kill(&crypto_info->queue_task);
+- tasklet_kill(&crypto_info->done_task);
++ rk_crypto_pm_exit(crypto_info);
++err_pm:
++ crypto_engine_exit(crypto_info->engine);
+ err_crypto:
++ dev_err(dev, "Crypto Accelerator not successfully registered\n");
+ return err;
+ }
+
+ static int rk_crypto_remove(struct platform_device *pdev)
+ {
+ struct rk_crypto_info *crypto_tmp = platform_get_drvdata(pdev);
++ struct rk_crypto_info *first;
+
+- rk_crypto_unregister();
+- tasklet_kill(&crypto_tmp->done_task);
+- tasklet_kill(&crypto_tmp->queue_task);
++ spin_lock_bh(&rocklist.lock);
++ list_del(&crypto_tmp->list);
++ first = list_first_entry_or_null(&rocklist.dev_list,
++ struct rk_crypto_info, list);
++ spin_unlock_bh(&rocklist.lock);
++
++ if (!first) {
++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG
++ debugfs_remove_recursive(rocklist.dbgfs_dir);
++#endif
++ rk_crypto_unregister();
++ }
++ rk_crypto_pm_exit(crypto_tmp);
++ crypto_engine_exit(crypto_tmp->engine);
+ return 0;
+ }
+
+@@ -433,6 +424,7 @@ static struct platform_driver crypto_dri
+ .remove = rk_crypto_remove,
+ .driver = {
+ .name = "rk3288-crypto",
++ .pm = &rk_crypto_pm_ops,
+ .of_match_table = crypto_of_id_table,
+ },
+ };
+--- a/drivers/crypto/rockchip/rk3288_crypto.h
++++ b/drivers/crypto/rockchip/rk3288_crypto.h
+@@ -5,9 +5,13 @@
+ #include <crypto/aes.h>
+ #include <crypto/internal/des.h>
+ #include <crypto/algapi.h>
++#include <linux/dma-mapping.h>
+ #include <linux/interrupt.h>
++#include <linux/debugfs.h>
+ #include <linux/delay.h>
++#include <linux/pm_runtime.h>
+ #include <linux/scatterlist.h>
++#include <crypto/engine.h>
+ #include <crypto/internal/hash.h>
+ #include <crypto/internal/skcipher.h>
+
+@@ -184,85 +188,91 @@
+ #define CRYPTO_WRITE(dev, offset, val) \
+ writel_relaxed((val), ((dev)->reg + (offset)))
+
++#define RK_MAX_CLKS 4
++
++/*
++ * struct rockchip_ip - struct for managing a list of RK crypto instance
++ * @dev_list: Used for doing a list of rk_crypto_info
++ * @lock: Control access to dev_list
++ * @dbgfs_dir: Debugfs dentry for statistic directory
++ * @dbgfs_stats: Debugfs dentry for statistic counters
++ */
++struct rockchip_ip {
++ struct list_head dev_list;
++ spinlock_t lock; /* Control access to dev_list */
++ struct dentry *dbgfs_dir;
++ struct dentry *dbgfs_stats;
++};
++
++struct rk_clks {
++ const char *name;
++ unsigned long max;
++};
++
++struct rk_variant {
++ int num_clks;
++ struct rk_clks rkclks[RK_MAX_CLKS];
++};
++
+ struct rk_crypto_info {
++ struct list_head list;
+ struct device *dev;
+- struct clk *aclk;
+- struct clk *hclk;
+- struct clk *sclk;
+- struct clk *dmaclk;
++ struct clk_bulk_data *clks;
++ int num_clks;
+ struct reset_control *rst;
+ void __iomem *reg;
+ int irq;
+- struct crypto_queue queue;
+- struct tasklet_struct queue_task;
+- struct tasklet_struct done_task;
+- struct crypto_async_request *async_req;
+- int err;
+- /* device lock */
+- spinlock_t lock;
+-
+- /* the public variable */
+- struct scatterlist *sg_src;
+- struct scatterlist *sg_dst;
+- struct scatterlist sg_tmp;
+- struct scatterlist *first;
+- unsigned int left_bytes;
+- void *addr_vir;
+- int aligned;
+- int align_size;
+- size_t src_nents;
+- size_t dst_nents;
+- unsigned int total;
+- unsigned int count;
+- dma_addr_t addr_in;
+- dma_addr_t addr_out;
+- bool busy;
+- int (*start)(struct rk_crypto_info *dev);
+- int (*update)(struct rk_crypto_info *dev);
+- void (*complete)(struct crypto_async_request *base, int err);
+- int (*enable_clk)(struct rk_crypto_info *dev);
+- void (*disable_clk)(struct rk_crypto_info *dev);
+- int (*load_data)(struct rk_crypto_info *dev,
+- struct scatterlist *sg_src,
+- struct scatterlist *sg_dst);
+- void (*unload_data)(struct rk_crypto_info *dev);
+- int (*enqueue)(struct rk_crypto_info *dev,
+- struct crypto_async_request *async_req);
++ const struct rk_variant *variant;
++ unsigned long nreq;
++ struct crypto_engine *engine;
++ struct completion complete;
++ int status;
+ };
+
+ /* the private variable of hash */
+ struct rk_ahash_ctx {
+- struct rk_crypto_info *dev;
++ struct crypto_engine_ctx enginectx;
+ /* for fallback */
+ struct crypto_ahash *fallback_tfm;
+ };
+
+-/* the privete variable of hash for fallback */
++/* the private variable of hash for fallback */
+ struct rk_ahash_rctx {
++ struct rk_crypto_info *dev;
+ struct ahash_request fallback_req;
+ u32 mode;
++ int nrsg;
+ };
+
+ /* the private variable of cipher */
+ struct rk_cipher_ctx {
+- struct rk_crypto_info *dev;
++ struct crypto_engine_ctx enginectx;
+ unsigned int keylen;
+- u32 mode;
++ u8 key[AES_MAX_KEY_SIZE];
+ u8 iv[AES_BLOCK_SIZE];
++ struct crypto_skcipher *fallback_tfm;
+ };
+
+-enum alg_type {
+- ALG_TYPE_HASH,
+- ALG_TYPE_CIPHER,
++struct rk_cipher_rctx {
++ struct rk_crypto_info *dev;
++ u8 backup_iv[AES_BLOCK_SIZE];
++ u32 mode;
++ struct skcipher_request fallback_req; // keep at the end
+ };
+
+ struct rk_crypto_tmp {
+- struct rk_crypto_info *dev;
++ u32 type;
++ struct rk_crypto_info *dev;
+ union {
+ struct skcipher_alg skcipher;
+ struct ahash_alg hash;
+ } alg;
+- enum alg_type type;
++ unsigned long stat_req;
++ unsigned long stat_fb;
++ unsigned long stat_fb_len;
++ unsigned long stat_fb_sglen;
++ unsigned long stat_fb_align;
++ unsigned long stat_fb_sgdiff;
+ };
+
+ extern struct rk_crypto_tmp rk_ecb_aes_alg;
+@@ -276,4 +286,5 @@ extern struct rk_crypto_tmp rk_ahash_sha
+ extern struct rk_crypto_tmp rk_ahash_sha256;
+ extern struct rk_crypto_tmp rk_ahash_md5;
+
++struct rk_crypto_info *get_rk_crypto(void);
+ #endif
+--- a/drivers/crypto/rockchip/rk3288_crypto_ahash.c
++++ b/drivers/crypto/rockchip/rk3288_crypto_ahash.c
+@@ -9,6 +9,8 @@
+ * Some ideas are from marvell/cesa.c and s5p-sss.c driver.
+ */
+ #include <linux/device.h>
++#include <asm/unaligned.h>
++#include <linux/iopoll.h>
+ #include "rk3288_crypto.h"
+
+ /*
+@@ -16,6 +18,44 @@
+ * so we put the fixed hash out when met zero message.
+ */
+
++static bool rk_ahash_need_fallback(struct ahash_request *req)
++{
++ struct scatterlist *sg;
++
++ sg = req->src;
++ while (sg) {
++ if (!IS_ALIGNED(sg->offset, sizeof(u32))) {
++ return true;
++ }
++ if (sg->length % 4) {
++ return true;
++ }
++ sg = sg_next(sg);
++ }
++ return false;
++}
++
++static int rk_ahash_digest_fb(struct ahash_request *areq)
++{
++ struct rk_ahash_rctx *rctx = ahash_request_ctx(areq);
++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
++ struct rk_ahash_ctx *tfmctx = crypto_ahash_ctx(tfm);
++ struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg);
++ struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.hash);
++
++ algt->stat_fb++;
++
++ ahash_request_set_tfm(&rctx->fallback_req, tfmctx->fallback_tfm);
++ rctx->fallback_req.base.flags = areq->base.flags &
++ CRYPTO_TFM_REQ_MAY_SLEEP;
++
++ rctx->fallback_req.nbytes = areq->nbytes;
++ rctx->fallback_req.src = areq->src;
++ rctx->fallback_req.result = areq->result;
++
++ return crypto_ahash_digest(&rctx->fallback_req);
++}
++
+ static int zero_message_process(struct ahash_request *req)
+ {
+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
+@@ -38,15 +78,9 @@ static int zero_message_process(struct a
+ return 0;
+ }
+
+-static void rk_ahash_crypto_complete(struct crypto_async_request *base, int err)
+-{
+- if (base->complete)
+- base->complete(base, err);
+-}
+-
+-static void rk_ahash_reg_init(struct rk_crypto_info *dev)
++static void rk_ahash_reg_init(struct ahash_request *req,
++ struct rk_crypto_info *dev)
+ {
+- struct ahash_request *req = ahash_request_cast(dev->async_req);
+ struct rk_ahash_rctx *rctx = ahash_request_ctx(req);
+ int reg_status;
+
+@@ -74,7 +108,7 @@ static void rk_ahash_reg_init(struct rk_
+ RK_CRYPTO_BYTESWAP_BRFIFO |
+ RK_CRYPTO_BYTESWAP_BTFIFO);
+
+- CRYPTO_WRITE(dev, RK_CRYPTO_HASH_MSG_LEN, dev->total);
++ CRYPTO_WRITE(dev, RK_CRYPTO_HASH_MSG_LEN, req->nbytes);
+ }
+
+ static int rk_ahash_init(struct ahash_request *req)
+@@ -164,51 +198,80 @@ static int rk_ahash_export(struct ahash_
+
+ static int rk_ahash_digest(struct ahash_request *req)
+ {
+- struct rk_ahash_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
+- struct rk_crypto_info *dev = tctx->dev;
++ struct rk_ahash_rctx *rctx = ahash_request_ctx(req);
++ struct rk_crypto_info *dev;
++ struct crypto_engine *engine;
++
++ if (rk_ahash_need_fallback(req))
++ return rk_ahash_digest_fb(req);
+
+ if (!req->nbytes)
+ return zero_message_process(req);
+- else
+- return dev->enqueue(dev, &req->base);
++
++ dev = get_rk_crypto();
++
++ rctx->dev = dev;
++ engine = dev->engine;
++
++ return crypto_transfer_hash_request_to_engine(engine, req);
+ }
+
+-static void crypto_ahash_dma_start(struct rk_crypto_info *dev)
++static void crypto_ahash_dma_start(struct rk_crypto_info *dev, struct scatterlist *sg)
+ {
+- CRYPTO_WRITE(dev, RK_CRYPTO_HRDMAS, dev->addr_in);
+- CRYPTO_WRITE(dev, RK_CRYPTO_HRDMAL, (dev->count + 3) / 4);
++ CRYPTO_WRITE(dev, RK_CRYPTO_HRDMAS, sg_dma_address(sg));
++ CRYPTO_WRITE(dev, RK_CRYPTO_HRDMAL, sg_dma_len(sg) / 4);
+ CRYPTO_WRITE(dev, RK_CRYPTO_CTRL, RK_CRYPTO_HASH_START |
+ (RK_CRYPTO_HASH_START << 16));
+ }
+
+-static int rk_ahash_set_data_start(struct rk_crypto_info *dev)
++static int rk_hash_prepare(struct crypto_engine *engine, void *breq)
++{
++ struct ahash_request *areq = container_of(breq, struct ahash_request, base);
++ struct rk_ahash_rctx *rctx = ahash_request_ctx(areq);
++ struct rk_crypto_info *rkc = rctx->dev;
++ int ret;
++
++ ret = dma_map_sg(rkc->dev, areq->src, sg_nents(areq->src), DMA_TO_DEVICE);
++ if (ret <= 0)
++ return -EINVAL;
++
++ rctx->nrsg = ret;
++
++ return 0;
++}
++
++static int rk_hash_unprepare(struct crypto_engine *engine, void *breq)
++{
++ struct ahash_request *areq = container_of(breq, struct ahash_request, base);
++ struct rk_ahash_rctx *rctx = ahash_request_ctx(areq);
++ struct rk_crypto_info *rkc = rctx->dev;
++
++ dma_unmap_sg(rkc->dev, areq->src, rctx->nrsg, DMA_TO_DEVICE);
++ return 0;
++}
++
++static int rk_hash_run(struct crypto_engine *engine, void *breq)
+ {
+- int err;
++ struct ahash_request *areq = container_of(breq, struct ahash_request, base);
++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
++ struct rk_ahash_rctx *rctx = ahash_request_ctx(areq);
++ struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg);
++ struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.hash);
++ struct scatterlist *sg = areq->src;
++ struct rk_crypto_info *rkc = rctx->dev;
++ int err = 0;
++ int i;
++ u32 v;
++
++ err = pm_runtime_resume_and_get(rkc->dev);
++ if (err)
++ return err;
+
+- err = dev->load_data(dev, dev->sg_src, NULL);
+- if (!err)
+- crypto_ahash_dma_start(dev);
+- return err;
+-}
+-
+-static int rk_ahash_start(struct rk_crypto_info *dev)
+-{
+- struct ahash_request *req = ahash_request_cast(dev->async_req);
+- struct crypto_ahash *tfm;
+- struct rk_ahash_rctx *rctx;
+-
+- dev->total = req->nbytes;
+- dev->left_bytes = req->nbytes;
+- dev->aligned = 0;
+- dev->align_size = 4;
+- dev->sg_dst = NULL;
+- dev->sg_src = req->src;
+- dev->first = req->src;
+- dev->src_nents = sg_nents(req->src);
+- rctx = ahash_request_ctx(req);
+ rctx->mode = 0;
+
+- tfm = crypto_ahash_reqtfm(req);
++ algt->stat_req++;
++ rkc->nreq++;
++
+ switch (crypto_ahash_digestsize(tfm)) {
+ case SHA1_DIGEST_SIZE:
+ rctx->mode = RK_CRYPTO_HASH_SHA1;
+@@ -220,100 +283,88 @@ static int rk_ahash_start(struct rk_cryp
+ rctx->mode = RK_CRYPTO_HASH_MD5;
+ break;
+ default:
+- return -EINVAL;
++ err = -EINVAL;
++ goto theend;
+ }
+
+- rk_ahash_reg_init(dev);
+- return rk_ahash_set_data_start(dev);
+-}
+-
+-static int rk_ahash_crypto_rx(struct rk_crypto_info *dev)
+-{
+- int err = 0;
+- struct ahash_request *req = ahash_request_cast(dev->async_req);
+- struct crypto_ahash *tfm;
++ rk_ahash_reg_init(areq, rkc);
+
+- dev->unload_data(dev);
+- if (dev->left_bytes) {
+- if (dev->aligned) {
+- if (sg_is_last(dev->sg_src)) {
+- dev_warn(dev->dev, "[%s:%d], Lack of data\n",
+- __func__, __LINE__);
+- err = -ENOMEM;
+- goto out_rx;
+- }
+- dev->sg_src = sg_next(dev->sg_src);
++ while (sg) {
++ reinit_completion(&rkc->complete);
++ rkc->status = 0;
++ crypto_ahash_dma_start(rkc, sg);
++ wait_for_completion_interruptible_timeout(&rkc->complete,
++ msecs_to_jiffies(2000));
++ if (!rkc->status) {
++ dev_err(rkc->dev, "DMA timeout\n");
++ err = -EFAULT;
++ goto theend;
+ }
+- err = rk_ahash_set_data_start(dev);
+- } else {
+- /*
+- * it will take some time to process date after last dma
+- * transmission.
+- *
+- * waiting time is relative with the last date len,
+- * so cannot set a fixed time here.
+- * 10us makes system not call here frequently wasting
+- * efficiency, and make it response quickly when dma
+- * complete.
+- */
+- while (!CRYPTO_READ(dev, RK_CRYPTO_HASH_STS))
+- udelay(10);
+-
+- tfm = crypto_ahash_reqtfm(req);
+- memcpy_fromio(req->result, dev->reg + RK_CRYPTO_HASH_DOUT_0,
+- crypto_ahash_digestsize(tfm));
+- dev->complete(dev->async_req, 0);
+- tasklet_schedule(&dev->queue_task);
++ sg = sg_next(sg);
++ }
++
++ /*
++ * it will take some time to process date after last dma
++ * transmission.
++ *
++ * waiting time is relative with the last date len,
++ * so cannot set a fixed time here.
++ * 10us makes system not call here frequently wasting
++ * efficiency, and make it response quickly when dma
++ * complete.
++ */
++ readl_poll_timeout(rkc->reg + RK_CRYPTO_HASH_STS, v, v == 0, 10, 1000);
++
++ for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++) {
++ v = readl(rkc->reg + RK_CRYPTO_HASH_DOUT_0 + i * 4);
++ put_unaligned_le32(v, areq->result + i * 4);
+ }
+
+-out_rx:
+- return err;
++theend:
++ pm_runtime_put_autosuspend(rkc->dev);
++
++ local_bh_disable();
++ crypto_finalize_hash_request(engine, breq, err);
++ local_bh_enable();
++
++ return 0;
+ }
+
+ static int rk_cra_hash_init(struct crypto_tfm *tfm)
+ {
+ struct rk_ahash_ctx *tctx = crypto_tfm_ctx(tfm);
+- struct rk_crypto_tmp *algt;
+- struct ahash_alg *alg = __crypto_ahash_alg(tfm->__crt_alg);
+-
+ const char *alg_name = crypto_tfm_alg_name(tfm);
+-
+- algt = container_of(alg, struct rk_crypto_tmp, alg.hash);
+-
+- tctx->dev = algt->dev;
+- tctx->dev->addr_vir = (void *)__get_free_page(GFP_KERNEL);
+- if (!tctx->dev->addr_vir) {
+- dev_err(tctx->dev->dev, "failed to kmalloc for addr_vir\n");
+- return -ENOMEM;
+- }
+- tctx->dev->start = rk_ahash_start;
+- tctx->dev->update = rk_ahash_crypto_rx;
+- tctx->dev->complete = rk_ahash_crypto_complete;
++ struct ahash_alg *alg = __crypto_ahash_alg(tfm->__crt_alg);
++ struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.hash);
+
+ /* for fallback */
+ tctx->fallback_tfm = crypto_alloc_ahash(alg_name, 0,
+- CRYPTO_ALG_NEED_FALLBACK);
++ CRYPTO_ALG_NEED_FALLBACK);
+ if (IS_ERR(tctx->fallback_tfm)) {
+- dev_err(tctx->dev->dev, "Could not load fallback driver.\n");
++ dev_err(algt->dev->dev, "Could not load fallback driver.\n");
+ return PTR_ERR(tctx->fallback_tfm);
+ }
++
+ crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
+ sizeof(struct rk_ahash_rctx) +
+ crypto_ahash_reqsize(tctx->fallback_tfm));
+
+- return tctx->dev->enable_clk(tctx->dev);
++ tctx->enginectx.op.do_one_request = rk_hash_run;
++ tctx->enginectx.op.prepare_request = rk_hash_prepare;
++ tctx->enginectx.op.unprepare_request = rk_hash_unprepare;
++
++ return 0;
+ }
+
+ static void rk_cra_hash_exit(struct crypto_tfm *tfm)
+ {
+ struct rk_ahash_ctx *tctx = crypto_tfm_ctx(tfm);
+
+- free_page((unsigned long)tctx->dev->addr_vir);
+- return tctx->dev->disable_clk(tctx->dev);
++ crypto_free_ahash(tctx->fallback_tfm);
+ }
+
+ struct rk_crypto_tmp rk_ahash_sha1 = {
+- .type = ALG_TYPE_HASH,
++ .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .init = rk_ahash_init,
+ .update = rk_ahash_update,
+@@ -337,13 +388,13 @@ struct rk_crypto_tmp rk_ahash_sha1 = {
+ .cra_init = rk_cra_hash_init,
+ .cra_exit = rk_cra_hash_exit,
+ .cra_module = THIS_MODULE,
+- }
+- }
++ }
++ }
+ }
+ };
+
+ struct rk_crypto_tmp rk_ahash_sha256 = {
+- .type = ALG_TYPE_HASH,
++ .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .init = rk_ahash_init,
+ .update = rk_ahash_update,
+@@ -367,13 +418,13 @@ struct rk_crypto_tmp rk_ahash_sha256 = {
+ .cra_init = rk_cra_hash_init,
+ .cra_exit = rk_cra_hash_exit,
+ .cra_module = THIS_MODULE,
+- }
+- }
++ }
++ }
+ }
+ };
+
+ struct rk_crypto_tmp rk_ahash_md5 = {
+- .type = ALG_TYPE_HASH,
++ .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .init = rk_ahash_init,
+ .update = rk_ahash_update,
+@@ -397,7 +448,7 @@ struct rk_crypto_tmp rk_ahash_md5 = {
+ .cra_init = rk_cra_hash_init,
+ .cra_exit = rk_cra_hash_exit,
+ .cra_module = THIS_MODULE,
+- }
+ }
++ }
+ }
+ };
+--- a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c
++++ b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c
+@@ -9,23 +9,94 @@
+ * Some ideas are from marvell-cesa.c and s5p-sss.c driver.
+ */
+ #include <linux/device.h>
++#include <crypto/scatterwalk.h>
+ #include "rk3288_crypto.h"
+
+ #define RK_CRYPTO_DEC BIT(0)
+
+-static void rk_crypto_complete(struct crypto_async_request *base, int err)
++static int rk_cipher_need_fallback(struct skcipher_request *req)
+ {
+- if (base->complete)
+- base->complete(base, err);
++ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
++ struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
++ struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.skcipher);
++ struct scatterlist *sgs, *sgd;
++ unsigned int stodo, dtodo, len;
++ unsigned int bs = crypto_skcipher_blocksize(tfm);
++
++ if (!req->cryptlen)
++ return true;
++
++ len = req->cryptlen;
++ sgs = req->src;
++ sgd = req->dst;
++ while (sgs && sgd) {
++ if (!IS_ALIGNED(sgs->offset, sizeof(u32))) {
++ algt->stat_fb_align++;
++ return true;
++ }
++ if (!IS_ALIGNED(sgd->offset, sizeof(u32))) {
++ algt->stat_fb_align++;
++ return true;
++ }
++ stodo = min(len, sgs->length);
++ if (stodo % bs) {
++ algt->stat_fb_len++;
++ return true;
++ }
++ dtodo = min(len, sgd->length);
++ if (dtodo % bs) {
++ algt->stat_fb_len++;
++ return true;
++ }
++ if (stodo != dtodo) {
++ algt->stat_fb_sgdiff++;
++ return true;
++ }
++ len -= stodo;
++ sgs = sg_next(sgs);
++ sgd = sg_next(sgd);
++ }
++ return false;
+ }
+
+-static int rk_handle_req(struct rk_crypto_info *dev,
+- struct skcipher_request *req)
++static int rk_cipher_fallback(struct skcipher_request *areq)
+ {
+- if (!IS_ALIGNED(req->cryptlen, dev->align_size))
+- return -EINVAL;
++ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq);
++ struct rk_cipher_ctx *op = crypto_skcipher_ctx(tfm);
++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(areq);
++ struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
++ struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.skcipher);
++ int err;
++
++ algt->stat_fb++;
++
++ skcipher_request_set_tfm(&rctx->fallback_req, op->fallback_tfm);
++ skcipher_request_set_callback(&rctx->fallback_req, areq->base.flags,
++ areq->base.complete, areq->base.data);
++ skcipher_request_set_crypt(&rctx->fallback_req, areq->src, areq->dst,
++ areq->cryptlen, areq->iv);
++ if (rctx->mode & RK_CRYPTO_DEC)
++ err = crypto_skcipher_decrypt(&rctx->fallback_req);
+ else
+- return dev->enqueue(dev, &req->base);
++ err = crypto_skcipher_encrypt(&rctx->fallback_req);
++ return err;
++}
++
++static int rk_cipher_handle_req(struct skcipher_request *req)
++{
++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req);
++ struct rk_crypto_info *rkc;
++ struct crypto_engine *engine;
++
++ if (rk_cipher_need_fallback(req))
++ return rk_cipher_fallback(req);
++
++ rkc = get_rk_crypto();
++
++ engine = rkc->engine;
++ rctx->dev = rkc;
++
++ return crypto_transfer_skcipher_request_to_engine(engine, req);
+ }
+
+ static int rk_aes_setkey(struct crypto_skcipher *cipher,
+@@ -38,8 +109,9 @@ static int rk_aes_setkey(struct crypto_s
+ keylen != AES_KEYSIZE_256)
+ return -EINVAL;
+ ctx->keylen = keylen;
+- memcpy_toio(ctx->dev->reg + RK_CRYPTO_AES_KEY_0, key, keylen);
+- return 0;
++ memcpy(ctx->key, key, keylen);
++
++ return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen);
+ }
+
+ static int rk_des_setkey(struct crypto_skcipher *cipher,
+@@ -53,8 +125,9 @@ static int rk_des_setkey(struct crypto_s
+ return err;
+
+ ctx->keylen = keylen;
+- memcpy_toio(ctx->dev->reg + RK_CRYPTO_TDES_KEY1_0, key, keylen);
+- return 0;
++ memcpy(ctx->key, key, keylen);
++
++ return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen);
+ }
+
+ static int rk_tdes_setkey(struct crypto_skcipher *cipher,
+@@ -68,161 +141,136 @@ static int rk_tdes_setkey(struct crypto_
+ return err;
+
+ ctx->keylen = keylen;
+- memcpy_toio(ctx->dev->reg + RK_CRYPTO_TDES_KEY1_0, key, keylen);
+- return 0;
++ memcpy(ctx->key, key, keylen);
++
++ return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen);
+ }
+
+ static int rk_aes_ecb_encrypt(struct skcipher_request *req)
+ {
+- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
+- struct rk_crypto_info *dev = ctx->dev;
++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req);
+
+- ctx->mode = RK_CRYPTO_AES_ECB_MODE;
+- return rk_handle_req(dev, req);
++ rctx->mode = RK_CRYPTO_AES_ECB_MODE;
++ return rk_cipher_handle_req(req);
+ }
+
+ static int rk_aes_ecb_decrypt(struct skcipher_request *req)
+ {
+- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
+- struct rk_crypto_info *dev = ctx->dev;
++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req);
+
+- ctx->mode = RK_CRYPTO_AES_ECB_MODE | RK_CRYPTO_DEC;
+- return rk_handle_req(dev, req);
++ rctx->mode = RK_CRYPTO_AES_ECB_MODE | RK_CRYPTO_DEC;
++ return rk_cipher_handle_req(req);
+ }
+
+ static int rk_aes_cbc_encrypt(struct skcipher_request *req)
+ {
+- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
+- struct rk_crypto_info *dev = ctx->dev;
++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req);
+
+- ctx->mode = RK_CRYPTO_AES_CBC_MODE;
+- return rk_handle_req(dev, req);
++ rctx->mode = RK_CRYPTO_AES_CBC_MODE;
++ return rk_cipher_handle_req(req);
+ }
+
+ static int rk_aes_cbc_decrypt(struct skcipher_request *req)
+ {
+- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
+- struct rk_crypto_info *dev = ctx->dev;
++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req);
+
+- ctx->mode = RK_CRYPTO_AES_CBC_MODE | RK_CRYPTO_DEC;
+- return rk_handle_req(dev, req);
++ rctx->mode = RK_CRYPTO_AES_CBC_MODE | RK_CRYPTO_DEC;
++ return rk_cipher_handle_req(req);
+ }
+
+ static int rk_des_ecb_encrypt(struct skcipher_request *req)
+ {
+- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
+- struct rk_crypto_info *dev = ctx->dev;
++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req);
+
+- ctx->mode = 0;
+- return rk_handle_req(dev, req);
++ rctx->mode = 0;
++ return rk_cipher_handle_req(req);
+ }
+
+ static int rk_des_ecb_decrypt(struct skcipher_request *req)
+ {
+- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
+- struct rk_crypto_info *dev = ctx->dev;
++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req);
+
+- ctx->mode = RK_CRYPTO_DEC;
+- return rk_handle_req(dev, req);
++ rctx->mode = RK_CRYPTO_DEC;
++ return rk_cipher_handle_req(req);
+ }
+
+ static int rk_des_cbc_encrypt(struct skcipher_request *req)
+ {
+- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
+- struct rk_crypto_info *dev = ctx->dev;
++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req);
+
+- ctx->mode = RK_CRYPTO_TDES_CHAINMODE_CBC;
+- return rk_handle_req(dev, req);
++ rctx->mode = RK_CRYPTO_TDES_CHAINMODE_CBC;
++ return rk_cipher_handle_req(req);
+ }
+
+ static int rk_des_cbc_decrypt(struct skcipher_request *req)
+ {
+- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
+- struct rk_crypto_info *dev = ctx->dev;
++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req);
+
+- ctx->mode = RK_CRYPTO_TDES_CHAINMODE_CBC | RK_CRYPTO_DEC;
+- return rk_handle_req(dev, req);
++ rctx->mode = RK_CRYPTO_TDES_CHAINMODE_CBC | RK_CRYPTO_DEC;
++ return rk_cipher_handle_req(req);
+ }
+
+ static int rk_des3_ede_ecb_encrypt(struct skcipher_request *req)
+ {
+- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
+- struct rk_crypto_info *dev = ctx->dev;
++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req);
+
+- ctx->mode = RK_CRYPTO_TDES_SELECT;
+- return rk_handle_req(dev, req);
++ rctx->mode = RK_CRYPTO_TDES_SELECT;
++ return rk_cipher_handle_req(req);
+ }
+
+ static int rk_des3_ede_ecb_decrypt(struct skcipher_request *req)
+ {
+- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
+- struct rk_crypto_info *dev = ctx->dev;
++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req);
+
+- ctx->mode = RK_CRYPTO_TDES_SELECT | RK_CRYPTO_DEC;
+- return rk_handle_req(dev, req);
++ rctx->mode = RK_CRYPTO_TDES_SELECT | RK_CRYPTO_DEC;
++ return rk_cipher_handle_req(req);
+ }
+
+ static int rk_des3_ede_cbc_encrypt(struct skcipher_request *req)
+ {
+- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
+- struct rk_crypto_info *dev = ctx->dev;
++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req);
+
+- ctx->mode = RK_CRYPTO_TDES_SELECT | RK_CRYPTO_TDES_CHAINMODE_CBC;
+- return rk_handle_req(dev, req);
++ rctx->mode = RK_CRYPTO_TDES_SELECT | RK_CRYPTO_TDES_CHAINMODE_CBC;
++ return rk_cipher_handle_req(req);
+ }
+
+ static int rk_des3_ede_cbc_decrypt(struct skcipher_request *req)
+ {
+- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
+- struct rk_crypto_info *dev = ctx->dev;
++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req);
+
+- ctx->mode = RK_CRYPTO_TDES_SELECT | RK_CRYPTO_TDES_CHAINMODE_CBC |
++ rctx->mode = RK_CRYPTO_TDES_SELECT | RK_CRYPTO_TDES_CHAINMODE_CBC |
+ RK_CRYPTO_DEC;
+- return rk_handle_req(dev, req);
++ return rk_cipher_handle_req(req);
+ }
+
+-static void rk_ablk_hw_init(struct rk_crypto_info *dev)
++static void rk_cipher_hw_init(struct rk_crypto_info *dev, struct skcipher_request *req)
+ {
+- struct skcipher_request *req =
+- skcipher_request_cast(dev->async_req);
+ struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(req);
+ struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher);
++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req);
+ struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(cipher);
+- u32 ivsize, block, conf_reg = 0;
++ u32 block, conf_reg = 0;
+
+ block = crypto_tfm_alg_blocksize(tfm);
+- ivsize = crypto_skcipher_ivsize(cipher);
+
+ if (block == DES_BLOCK_SIZE) {
+- ctx->mode |= RK_CRYPTO_TDES_FIFO_MODE |
++ rctx->mode |= RK_CRYPTO_TDES_FIFO_MODE |
+ RK_CRYPTO_TDES_BYTESWAP_KEY |
+ RK_CRYPTO_TDES_BYTESWAP_IV;
+- CRYPTO_WRITE(dev, RK_CRYPTO_TDES_CTRL, ctx->mode);
+- memcpy_toio(dev->reg + RK_CRYPTO_TDES_IV_0, req->iv, ivsize);
++ CRYPTO_WRITE(dev, RK_CRYPTO_TDES_CTRL, rctx->mode);
++ memcpy_toio(dev->reg + RK_CRYPTO_TDES_KEY1_0, ctx->key, ctx->keylen);
+ conf_reg = RK_CRYPTO_DESSEL;
+ } else {
+- ctx->mode |= RK_CRYPTO_AES_FIFO_MODE |
++ rctx->mode |= RK_CRYPTO_AES_FIFO_MODE |
+ RK_CRYPTO_AES_KEY_CHANGE |
+ RK_CRYPTO_AES_BYTESWAP_KEY |
+ RK_CRYPTO_AES_BYTESWAP_IV;
+ if (ctx->keylen == AES_KEYSIZE_192)
+- ctx->mode |= RK_CRYPTO_AES_192BIT_key;
++ rctx->mode |= RK_CRYPTO_AES_192BIT_key;
+ else if (ctx->keylen == AES_KEYSIZE_256)
+- ctx->mode |= RK_CRYPTO_AES_256BIT_key;
+- CRYPTO_WRITE(dev, RK_CRYPTO_AES_CTRL, ctx->mode);
+- memcpy_toio(dev->reg + RK_CRYPTO_AES_IV_0, req->iv, ivsize);
++ rctx->mode |= RK_CRYPTO_AES_256BIT_key;
++ CRYPTO_WRITE(dev, RK_CRYPTO_AES_CTRL, rctx->mode);
++ memcpy_toio(dev->reg + RK_CRYPTO_AES_KEY_0, ctx->key, ctx->keylen);
+ }
+ conf_reg |= RK_CRYPTO_BYTESWAP_BTFIFO |
+ RK_CRYPTO_BYTESWAP_BRFIFO;
+@@ -231,189 +279,196 @@ static void rk_ablk_hw_init(struct rk_cr
+ RK_CRYPTO_BCDMA_ERR_ENA | RK_CRYPTO_BCDMA_DONE_ENA);
+ }
+
+-static void crypto_dma_start(struct rk_crypto_info *dev)
+-{
+- CRYPTO_WRITE(dev, RK_CRYPTO_BRDMAS, dev->addr_in);
+- CRYPTO_WRITE(dev, RK_CRYPTO_BRDMAL, dev->count / 4);
+- CRYPTO_WRITE(dev, RK_CRYPTO_BTDMAS, dev->addr_out);
++static void crypto_dma_start(struct rk_crypto_info *dev,
++ struct scatterlist *sgs,
++ struct scatterlist *sgd, unsigned int todo)
++{
++ CRYPTO_WRITE(dev, RK_CRYPTO_BRDMAS, sg_dma_address(sgs));
++ CRYPTO_WRITE(dev, RK_CRYPTO_BRDMAL, todo);
++ CRYPTO_WRITE(dev, RK_CRYPTO_BTDMAS, sg_dma_address(sgd));
+ CRYPTO_WRITE(dev, RK_CRYPTO_CTRL, RK_CRYPTO_BLOCK_START |
+ _SBF(RK_CRYPTO_BLOCK_START, 16));
+ }
+
+-static int rk_set_data_start(struct rk_crypto_info *dev)
++static int rk_cipher_run(struct crypto_engine *engine, void *async_req)
+ {
+- int err;
+- struct skcipher_request *req =
+- skcipher_request_cast(dev->async_req);
+- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
+- u32 ivsize = crypto_skcipher_ivsize(tfm);
+- u8 *src_last_blk = page_address(sg_page(dev->sg_src)) +
+- dev->sg_src->offset + dev->sg_src->length - ivsize;
+-
+- /* Store the iv that need to be updated in chain mode.
+- * And update the IV buffer to contain the next IV for decryption mode.
+- */
+- if (ctx->mode & RK_CRYPTO_DEC) {
+- memcpy(ctx->iv, src_last_blk, ivsize);
+- sg_pcopy_to_buffer(dev->first, dev->src_nents, req->iv,
+- ivsize, dev->total - ivsize);
+- }
+-
+- err = dev->load_data(dev, dev->sg_src, dev->sg_dst);
+- if (!err)
+- crypto_dma_start(dev);
+- return err;
+-}
+-
+-static int rk_ablk_start(struct rk_crypto_info *dev)
+-{
+- struct skcipher_request *req =
+- skcipher_request_cast(dev->async_req);
+- unsigned long flags;
++ struct skcipher_request *areq = container_of(async_req, struct skcipher_request, base);
++ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq);
++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(areq);
++ struct scatterlist *sgs, *sgd;
+ int err = 0;
++ int ivsize = crypto_skcipher_ivsize(tfm);
++ int offset;
++ u8 iv[AES_BLOCK_SIZE];
++ u8 biv[AES_BLOCK_SIZE];
++ u8 *ivtouse = areq->iv;
++ unsigned int len = areq->cryptlen;
++ unsigned int todo;
++ struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
++ struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.skcipher);
++ struct rk_crypto_info *rkc = rctx->dev;
+
+- dev->left_bytes = req->cryptlen;
+- dev->total = req->cryptlen;
+- dev->sg_src = req->src;
+- dev->first = req->src;
+- dev->src_nents = sg_nents(req->src);
+- dev->sg_dst = req->dst;
+- dev->dst_nents = sg_nents(req->dst);
+- dev->aligned = 1;
+-
+- spin_lock_irqsave(&dev->lock, flags);
+- rk_ablk_hw_init(dev);
+- err = rk_set_data_start(dev);
+- spin_unlock_irqrestore(&dev->lock, flags);
+- return err;
+-}
++ err = pm_runtime_resume_and_get(rkc->dev);
++ if (err)
++ return err;
+
+-static void rk_iv_copyback(struct rk_crypto_info *dev)
+-{
+- struct skcipher_request *req =
+- skcipher_request_cast(dev->async_req);
+- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
+- u32 ivsize = crypto_skcipher_ivsize(tfm);
++ algt->stat_req++;
++ rkc->nreq++;
+
+- /* Update the IV buffer to contain the next IV for encryption mode. */
+- if (!(ctx->mode & RK_CRYPTO_DEC)) {
+- if (dev->aligned) {
+- memcpy(req->iv, sg_virt(dev->sg_dst) +
+- dev->sg_dst->length - ivsize, ivsize);
+- } else {
+- memcpy(req->iv, dev->addr_vir +
+- dev->count - ivsize, ivsize);
++ ivsize = crypto_skcipher_ivsize(tfm);
++ if (areq->iv && crypto_skcipher_ivsize(tfm) > 0) {
++ if (rctx->mode & RK_CRYPTO_DEC) {
++ offset = areq->cryptlen - ivsize;
++ scatterwalk_map_and_copy(rctx->backup_iv, areq->src,
++ offset, ivsize, 0);
+ }
+ }
+-}
+
+-static void rk_update_iv(struct rk_crypto_info *dev)
+-{
+- struct skcipher_request *req =
+- skcipher_request_cast(dev->async_req);
+- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+- struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
+- u32 ivsize = crypto_skcipher_ivsize(tfm);
+- u8 *new_iv = NULL;
++ sgs = areq->src;
++ sgd = areq->dst;
+
+- if (ctx->mode & RK_CRYPTO_DEC) {
+- new_iv = ctx->iv;
+- } else {
+- new_iv = page_address(sg_page(dev->sg_dst)) +
+- dev->sg_dst->offset + dev->sg_dst->length - ivsize;
++ while (sgs && sgd && len) {
++ if (!sgs->length) {
++ sgs = sg_next(sgs);
++ sgd = sg_next(sgd);
++ continue;
++ }
++ if (rctx->mode & RK_CRYPTO_DEC) {
++ /* we backup last block of source to be used as IV at next step */
++ offset = sgs->length - ivsize;
++ scatterwalk_map_and_copy(biv, sgs, offset, ivsize, 0);
++ }
++ if (sgs == sgd) {
++ err = dma_map_sg(rkc->dev, sgs, 1, DMA_BIDIRECTIONAL);
++ if (err <= 0) {
++ err = -EINVAL;
++ goto theend_iv;
++ }
++ } else {
++ err = dma_map_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE);
++ if (err <= 0) {
++ err = -EINVAL;
++ goto theend_iv;
++ }
++ err = dma_map_sg(rkc->dev, sgd, 1, DMA_FROM_DEVICE);
++ if (err <= 0) {
++ err = -EINVAL;
++ goto theend_sgs;
++ }
++ }
++ err = 0;
++ rk_cipher_hw_init(rkc, areq);
++ if (ivsize) {
++ if (ivsize == DES_BLOCK_SIZE)
++ memcpy_toio(rkc->reg + RK_CRYPTO_TDES_IV_0, ivtouse, ivsize);
++ else
++ memcpy_toio(rkc->reg + RK_CRYPTO_AES_IV_0, ivtouse, ivsize);
++ }
++ reinit_completion(&rkc->complete);
++ rkc->status = 0;
++
++ todo = min(sg_dma_len(sgs), len);
++ len -= todo;
++ crypto_dma_start(rkc, sgs, sgd, todo / 4);
++ wait_for_completion_interruptible_timeout(&rkc->complete,
++ msecs_to_jiffies(2000));
++ if (!rkc->status) {
++ dev_err(rkc->dev, "DMA timeout\n");
++ err = -EFAULT;
++ goto theend;
++ }
++ if (sgs == sgd) {
++ dma_unmap_sg(rkc->dev, sgs, 1, DMA_BIDIRECTIONAL);
++ } else {
++ dma_unmap_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE);
++ dma_unmap_sg(rkc->dev, sgd, 1, DMA_FROM_DEVICE);
++ }
++ if (rctx->mode & RK_CRYPTO_DEC) {
++ memcpy(iv, biv, ivsize);
++ ivtouse = iv;
++ } else {
++ offset = sgd->length - ivsize;
++ scatterwalk_map_and_copy(iv, sgd, offset, ivsize, 0);
++ ivtouse = iv;
++ }
++ sgs = sg_next(sgs);
++ sgd = sg_next(sgd);
+ }
+
+- if (ivsize == DES_BLOCK_SIZE)
+- memcpy_toio(dev->reg + RK_CRYPTO_TDES_IV_0, new_iv, ivsize);
+- else if (ivsize == AES_BLOCK_SIZE)
+- memcpy_toio(dev->reg + RK_CRYPTO_AES_IV_0, new_iv, ivsize);
+-}
++ if (areq->iv && ivsize > 0) {
++ offset = areq->cryptlen - ivsize;
++ if (rctx->mode & RK_CRYPTO_DEC) {
++ memcpy(areq->iv, rctx->backup_iv, ivsize);
++ memzero_explicit(rctx->backup_iv, ivsize);
++ } else {
++ scatterwalk_map_and_copy(areq->iv, areq->dst, offset,
++ ivsize, 0);
++ }
++ }
+
+-/* return:
+- * true some err was occurred
+- * fault no err, continue
+- */
+-static int rk_ablk_rx(struct rk_crypto_info *dev)
+-{
+- int err = 0;
+- struct skcipher_request *req =
+- skcipher_request_cast(dev->async_req);
++theend:
++ pm_runtime_put_autosuspend(rkc->dev);
+
+- dev->unload_data(dev);
+- if (!dev->aligned) {
+- if (!sg_pcopy_from_buffer(req->dst, dev->dst_nents,
+- dev->addr_vir, dev->count,
+- dev->total - dev->left_bytes -
+- dev->count)) {
+- err = -EINVAL;
+- goto out_rx;
+- }
+- }
+- if (dev->left_bytes) {
+- rk_update_iv(dev);
+- if (dev->aligned) {
+- if (sg_is_last(dev->sg_src)) {
+- dev_err(dev->dev, "[%s:%d] Lack of data\n",
+- __func__, __LINE__);
+- err = -ENOMEM;
+- goto out_rx;
+- }
+- dev->sg_src = sg_next(dev->sg_src);
+- dev->sg_dst = sg_next(dev->sg_dst);
+- }
+- err = rk_set_data_start(dev);
++ local_bh_disable();
++ crypto_finalize_skcipher_request(engine, areq, err);
++ local_bh_enable();
++ return 0;
++
++theend_sgs:
++ if (sgs == sgd) {
++ dma_unmap_sg(rkc->dev, sgs, 1, DMA_BIDIRECTIONAL);
+ } else {
+- rk_iv_copyback(dev);
+- /* here show the calculation is over without any err */
+- dev->complete(dev->async_req, 0);
+- tasklet_schedule(&dev->queue_task);
++ dma_unmap_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE);
++ dma_unmap_sg(rkc->dev, sgd, 1, DMA_FROM_DEVICE);
+ }
+-out_rx:
++theend_iv:
+ return err;
+ }
+
+-static int rk_ablk_init_tfm(struct crypto_skcipher *tfm)
++static int rk_cipher_tfm_init(struct crypto_skcipher *tfm)
+ {
+ struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
++ const char *name = crypto_tfm_alg_name(&tfm->base);
+ struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
+- struct rk_crypto_tmp *algt;
++ struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.skcipher);
+
+- algt = container_of(alg, struct rk_crypto_tmp, alg.skcipher);
++ ctx->fallback_tfm = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
++ if (IS_ERR(ctx->fallback_tfm)) {
++ dev_err(algt->dev->dev, "ERROR: Cannot allocate fallback for %s %ld\n",
++ name, PTR_ERR(ctx->fallback_tfm));
++ return PTR_ERR(ctx->fallback_tfm);
++ }
++
++ tfm->reqsize = sizeof(struct rk_cipher_rctx) +
++ crypto_skcipher_reqsize(ctx->fallback_tfm);
+
+- ctx->dev = algt->dev;
+- ctx->dev->align_size = crypto_tfm_alg_alignmask(crypto_skcipher_tfm(tfm)) + 1;
+- ctx->dev->start = rk_ablk_start;
+- ctx->dev->update = rk_ablk_rx;
+- ctx->dev->complete = rk_crypto_complete;
+- ctx->dev->addr_vir = (char *)__get_free_page(GFP_KERNEL);
++ ctx->enginectx.op.do_one_request = rk_cipher_run;
+
+- return ctx->dev->addr_vir ? ctx->dev->enable_clk(ctx->dev) : -ENOMEM;
++ return 0;
+ }
+
+-static void rk_ablk_exit_tfm(struct crypto_skcipher *tfm)
++static void rk_cipher_tfm_exit(struct crypto_skcipher *tfm)
+ {
+ struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
+
+- free_page((unsigned long)ctx->dev->addr_vir);
+- ctx->dev->disable_clk(ctx->dev);
++ memzero_explicit(ctx->key, ctx->keylen);
++ crypto_free_skcipher(ctx->fallback_tfm);
+ }
+
+ struct rk_crypto_tmp rk_ecb_aes_alg = {
+- .type = ALG_TYPE_CIPHER,
++ .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "ecb(aes)",
+ .base.cra_driver_name = "ecb-aes-rk",
+ .base.cra_priority = 300,
+- .base.cra_flags = CRYPTO_ALG_ASYNC,
++ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
+ .base.cra_blocksize = AES_BLOCK_SIZE,
+ .base.cra_ctxsize = sizeof(struct rk_cipher_ctx),
+ .base.cra_alignmask = 0x0f,
+ .base.cra_module = THIS_MODULE,
+
+- .init = rk_ablk_init_tfm,
+- .exit = rk_ablk_exit_tfm,
++ .init = rk_cipher_tfm_init,
++ .exit = rk_cipher_tfm_exit,
+ .min_keysize = AES_MIN_KEY_SIZE,
+ .max_keysize = AES_MAX_KEY_SIZE,
+ .setkey = rk_aes_setkey,
+@@ -423,19 +478,19 @@ struct rk_crypto_tmp rk_ecb_aes_alg = {
+ };
+
+ struct rk_crypto_tmp rk_cbc_aes_alg = {
+- .type = ALG_TYPE_CIPHER,
++ .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "cbc(aes)",
+ .base.cra_driver_name = "cbc-aes-rk",
+ .base.cra_priority = 300,
+- .base.cra_flags = CRYPTO_ALG_ASYNC,
++ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
+ .base.cra_blocksize = AES_BLOCK_SIZE,
+ .base.cra_ctxsize = sizeof(struct rk_cipher_ctx),
+ .base.cra_alignmask = 0x0f,
+ .base.cra_module = THIS_MODULE,
+
+- .init = rk_ablk_init_tfm,
+- .exit = rk_ablk_exit_tfm,
++ .init = rk_cipher_tfm_init,
++ .exit = rk_cipher_tfm_exit,
+ .min_keysize = AES_MIN_KEY_SIZE,
+ .max_keysize = AES_MAX_KEY_SIZE,
+ .ivsize = AES_BLOCK_SIZE,
+@@ -446,19 +501,19 @@ struct rk_crypto_tmp rk_cbc_aes_alg = {
+ };
+
+ struct rk_crypto_tmp rk_ecb_des_alg = {
+- .type = ALG_TYPE_CIPHER,
++ .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "ecb(des)",
+ .base.cra_driver_name = "ecb-des-rk",
+ .base.cra_priority = 300,
+- .base.cra_flags = CRYPTO_ALG_ASYNC,
++ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
+ .base.cra_blocksize = DES_BLOCK_SIZE,
+ .base.cra_ctxsize = sizeof(struct rk_cipher_ctx),
+ .base.cra_alignmask = 0x07,
+ .base.cra_module = THIS_MODULE,
+
+- .init = rk_ablk_init_tfm,
+- .exit = rk_ablk_exit_tfm,
++ .init = rk_cipher_tfm_init,
++ .exit = rk_cipher_tfm_exit,
+ .min_keysize = DES_KEY_SIZE,
+ .max_keysize = DES_KEY_SIZE,
+ .setkey = rk_des_setkey,
+@@ -468,19 +523,19 @@ struct rk_crypto_tmp rk_ecb_des_alg = {
+ };
+
+ struct rk_crypto_tmp rk_cbc_des_alg = {
+- .type = ALG_TYPE_CIPHER,
++ .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "cbc(des)",
+ .base.cra_driver_name = "cbc-des-rk",
+ .base.cra_priority = 300,
+- .base.cra_flags = CRYPTO_ALG_ASYNC,
++ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
+ .base.cra_blocksize = DES_BLOCK_SIZE,
+ .base.cra_ctxsize = sizeof(struct rk_cipher_ctx),
+ .base.cra_alignmask = 0x07,
+ .base.cra_module = THIS_MODULE,
+
+- .init = rk_ablk_init_tfm,
+- .exit = rk_ablk_exit_tfm,
++ .init = rk_cipher_tfm_init,
++ .exit = rk_cipher_tfm_exit,
+ .min_keysize = DES_KEY_SIZE,
+ .max_keysize = DES_KEY_SIZE,
+ .ivsize = DES_BLOCK_SIZE,
+@@ -491,19 +546,19 @@ struct rk_crypto_tmp rk_cbc_des_alg = {
+ };
+
+ struct rk_crypto_tmp rk_ecb_des3_ede_alg = {
+- .type = ALG_TYPE_CIPHER,
++ .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "ecb(des3_ede)",
+ .base.cra_driver_name = "ecb-des3-ede-rk",
+ .base.cra_priority = 300,
+- .base.cra_flags = CRYPTO_ALG_ASYNC,
++ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
+ .base.cra_blocksize = DES_BLOCK_SIZE,
+ .base.cra_ctxsize = sizeof(struct rk_cipher_ctx),
+ .base.cra_alignmask = 0x07,
+ .base.cra_module = THIS_MODULE,
+
+- .init = rk_ablk_init_tfm,
+- .exit = rk_ablk_exit_tfm,
++ .init = rk_cipher_tfm_init,
++ .exit = rk_cipher_tfm_exit,
+ .min_keysize = DES3_EDE_KEY_SIZE,
+ .max_keysize = DES3_EDE_KEY_SIZE,
+ .setkey = rk_tdes_setkey,
+@@ -513,19 +568,19 @@ struct rk_crypto_tmp rk_ecb_des3_ede_alg
+ };
+
+ struct rk_crypto_tmp rk_cbc_des3_ede_alg = {
+- .type = ALG_TYPE_CIPHER,
++ .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "cbc(des3_ede)",
+ .base.cra_driver_name = "cbc-des3-ede-rk",
+ .base.cra_priority = 300,
+- .base.cra_flags = CRYPTO_ALG_ASYNC,
++ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
+ .base.cra_blocksize = DES_BLOCK_SIZE,
+ .base.cra_ctxsize = sizeof(struct rk_cipher_ctx),
+ .base.cra_alignmask = 0x07,
+ .base.cra_module = THIS_MODULE,
+
+- .init = rk_ablk_init_tfm,
+- .exit = rk_ablk_exit_tfm,
++ .init = rk_cipher_tfm_init,
++ .exit = rk_cipher_tfm_exit,
+ .min_keysize = DES3_EDE_KEY_SIZE,
+ .max_keysize = DES3_EDE_KEY_SIZE,
+ .ivsize = DES_BLOCK_SIZE,
+--- a/drivers/crypto/Kconfig
++++ b/drivers/crypto/Kconfig
+@@ -784,7 +784,12 @@ config CRYPTO_DEV_IMGTEC_HASH
+ config CRYPTO_DEV_ROCKCHIP
+ tristate "Rockchip's Cryptographic Engine driver"
+ depends on OF && ARCH_ROCKCHIP
++ depends on PM
++ select CRYPTO_ECB
++ select CRYPTO_CBC
++ select CRYPTO_DES
+ select CRYPTO_AES
++ select CRYPTO_ENGINE
+ select CRYPTO_LIB_DES
+ select CRYPTO_MD5
+ select CRYPTO_SHA1
+@@ -796,6 +801,16 @@ config CRYPTO_DEV_ROCKCHIP
+ This driver interfaces with the hardware crypto accelerator.
+ Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode.
+
++config CRYPTO_DEV_ROCKCHIP_DEBUG
++ bool "Enable Rockchip crypto stats"
++ depends on CRYPTO_DEV_ROCKCHIP
++ depends on DEBUG_FS
++ help
++ Say y to enable Rockchip crypto debug stats.
++ This will create /sys/kernel/debug/rk3288_crypto/stats for displaying
++ the number of requests per algorithm and other internal stats.
++
++
+ config CRYPTO_DEV_ZYNQMP_AES
+ tristate "Support for Xilinx ZynqMP AES hw accelerator"
+ depends on ZYNQMP_FIRMWARE || COMPILE_TEST
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -16972,6 +16972,13 @@ F: Documentation/ABI/*/sysfs-driver-hid-
+ F: drivers/hid/hid-roccat*
+ F: include/linux/hid-roccat*
+
++ROCKCHIP CRYPTO DRIVERS
++M: Corentin Labbe <clabbe@baylibre.com>
++L: linux-crypto@vger.kernel.org
++S: Maintained
++F: Documentation/devicetree/bindings/crypto/rockchip,rk3288-crypto.yaml
++F: drivers/crypto/rockchip/
++
+ ROCKCHIP I2S TDM DRIVER
+ M: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+ L: linux-rockchip@lists.infradead.org
+--- /dev/null
++++ b/Documentation/devicetree/bindings/crypto/rockchip,rk3288-crypto.yaml
+@@ -0,0 +1,133 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/crypto/rockchip,rk3288-crypto.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip Electronics Security Accelerator
++
++maintainers:
++ - Heiko Stuebner <heiko@sntech.de>
++
++properties:
++ compatible:
++ enum:
++ - rockchip,rk3288-crypto
++ - rockchip,rk3328-crypto
++ - rockchip,rk3399-crypto
++
++ reg:
++ maxItems: 1
++
++ interrupts:
++ maxItems: 1
++
++ clocks:
++ minItems: 3
++ maxItems: 4
++
++ clock-names:
++ minItems: 3
++ maxItems: 4
++
++ resets:
++ minItems: 1
++ maxItems: 3
++
++ reset-names:
++ minItems: 1
++ maxItems: 3
++
++allOf:
++ - if:
++ properties:
++ compatible:
++ contains:
++ const: rockchip,rk3288-crypto
++ then:
++ properties:
++ clocks:
++ minItems: 4
++ clock-names:
++ items:
++ - const: aclk
++ - const: hclk
++ - const: sclk
++ - const: apb_pclk
++ minItems: 4
++ resets:
++ maxItems: 1
++ reset-names:
++ items:
++ - const: crypto-rst
++ maxItems: 1
++ - if:
++ properties:
++ compatible:
++ contains:
++ const: rockchip,rk3328-crypto
++ then:
++ properties:
++ clocks:
++ maxItems: 3
++ clock-names:
++ items:
++ - const: hclk_master
++ - const: hclk_slave
++ - const: sclk
++ maxItems: 3
++ resets:
++ maxItems: 1
++ reset-names:
++ items:
++ - const: crypto-rst
++ maxItems: 1
++ - if:
++ properties:
++ compatible:
++ contains:
++ const: rockchip,rk3399-crypto
++ then:
++ properties:
++ clocks:
++ maxItems: 3
++ clock-names:
++ items:
++ - const: hclk_master
++ - const: hclk_slave
++ - const: sclk
++ maxItems: 3
++ resets:
++ minItems: 3
++ reset-names:
++ items:
++ - const: rst_master
++ - const: rst_slave
++ - const: crypto-rst
++ minItems: 3
++
++required:
++ - compatible
++ - reg
++ - interrupts
++ - clocks
++ - clock-names
++ - resets
++ - reset-names
++
++additionalProperties: false
++
++examples:
++ - |
++ #include <dt-bindings/interrupt-controller/arm-gic.h>
++ #include <dt-bindings/clock/rk3288-cru.h>
++ crypto@ff8a0000 {
++ compatible = "rockchip,rk3288-crypto";
++ reg = <0xff8a0000 0x4000>;
++ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
++ <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
++ clock-names = "aclk", "hclk", "sclk", "apb_pclk";
++ resets = <&cru SRST_CRYPTO>;
++ reset-names = "crypto-rst";
++ };
+--- a/Documentation/devicetree/bindings/crypto/rockchip-crypto.txt
++++ /dev/null
+@@ -1,28 +0,0 @@
+-Rockchip Electronics And Security Accelerator
+-
+-Required properties:
+-- compatible: Should be "rockchip,rk3288-crypto"
+-- reg: Base physical address of the engine and length of memory mapped
+- region
+-- interrupts: Interrupt number
+-- clocks: Reference to the clocks about crypto
+-- clock-names: "aclk" used to clock data
+- "hclk" used to clock data
+- "sclk" used to clock crypto accelerator
+- "apb_pclk" used to clock dma
+-- resets: Must contain an entry for each entry in reset-names.
+- See ../reset/reset.txt for details.
+-- reset-names: Must include the name "crypto-rst".
+-
+-Examples:
+-
+- crypto: cypto-controller@ff8a0000 {
+- compatible = "rockchip,rk3288-crypto";
+- reg = <0xff8a0000 0x4000>;
+- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
+- <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
+- clock-names = "aclk", "hclk", "sclk", "apb_pclk";
+- resets = <&cru SRST_CRYPTO>;
+- reset-names = "crypto-rst";
+- };
+--- a/include/dt-bindings/clock/rk3399-cru.h
++++ b/include/dt-bindings/clock/rk3399-cru.h
+@@ -547,8 +547,8 @@
+ #define SRST_H_PERILP0 171
+ #define SRST_H_PERILP0_NOC 172
+ #define SRST_ROM 173
+-#define SRST_CRYPTO_S 174
+-#define SRST_CRYPTO_M 175
++#define SRST_CRYPTO0_S 174
++#define SRST_CRYPTO0_M 175
+
+ /* cru_softrst_con11 */
+ #define SRST_P_DCF 176
+@@ -556,7 +556,7 @@
+ #define SRST_CM0S 178
+ #define SRST_CM0S_DBG 179
+ #define SRST_CM0S_PO 180
+-#define SRST_CRYPTO 181
++#define SRST_CRYPTO0 181
+ #define SRST_P_PERILP1_SGRF 182
+ #define SRST_P_PERILP1_GRF 183
+ #define SRST_CRYPTO1_S 184
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -1040,6 +1040,17 @@
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
++ crypto: crypto@ff060000 {
++ compatible = "rockchip,rk3328-crypto";
++ reg = <0x0 0xff060000 0x0 0x4000>;
++ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>,
++ <&cru SCLK_CRYPTO>;
++ clock-names = "hclk_master", "hclk_slave", "sclk";
++ resets = <&cru SRST_CRYPTO>;
++ reset-names = "crypto-rst";
++ };
++
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3328-pinctrl";
+ rockchip,grf = <&grf>;
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -573,6 +573,26 @@
+ status = "disabled";
+ };
+
++ crypto0: crypto@ff8b0000 {
++ compatible = "rockchip,rk3399-crypto";
++ reg = <0x0 0xff8b0000 0x0 0x4000>;
++ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>;
++ clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>;
++ clock-names = "hclk_master", "hclk_slave", "sclk";
++ resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>;
++ reset-names = "rst_master", "rst_slave", "crypto-rst";
++ };
++
++ crypto1: crypto@ff8b8000 {
++ compatible = "rockchip,rk3399-crypto";
++ reg = <0x0 0xff8b8000 0x0 0x4000>;
++ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
++ clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>;
++ clock-names = "hclk_master", "hclk_slave", "sclk";
++ resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>;
++ reset-names = "rst_master", "rst_slave", "crypto-rst";
++ };
++
+ i2c1: i2c@ff110000 {
+ compatible = "rockchip,rk3399-i2c";
+ reg = <0x0 0xff110000 0x0 0x1000>;
From 2e53ea674178254f86f9537bed965fd3c79fb303 Mon Sep 17 00:00:00 2001
From: cuiyf5516 <48861298+cuiyf5516@users.noreply.github.com>
Date: Sat, 6 Aug 2022 00:21:54 +0800
Subject: [PATCH 6/9] rockchip: 5.19: disable ntfs option (#9889)
---
target/linux/rockchip/armv8/config-5.19 | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/linux/rockchip/armv8/config-5.19 b/target/linux/rockchip/armv8/config-5.19
index 1591ae509a122e..e15fef802dbc48 100644
--- a/target/linux/rockchip/armv8/config-5.19
+++ b/target/linux/rockchip/armv8/config-5.19
@@ -513,8 +513,6 @@ CONFIG_NLS_ISO8859_1=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
-CONFIG_NTFS_FS=y
-CONFIG_NTFS_RW=y
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_NVME_CORE=y
From e99155a6e1fd2e63511d5ea0e3e06175d6ccd727 Mon Sep 17 00:00:00 2001
From: aakkll <94471752+aakkll@users.noreply.github.com>
Date: Sat, 6 Aug 2022 00:22:41 +0800
Subject: [PATCH 7/9] kernel: refresh 5.19 patch (#9890)
Signed-off-by: aakkll <94471752+aakkll@users.noreply.github.com>
---
.../generic/hack-5.19/902-debloat_proc.patch | 4 ++--
.../generic/hack-5.19/904-debloat_dma_buf.patch | 4 ++--
...rack-events-support-multiple-registrant.patch | 16 ++++++++--------
...tch-linux-kernel-to-support-shortcut-fe.patch | 14 +++++++-------
...node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch | 2 +-
...cting-with-source-address-failed-policy.patch | 2 +-
...kchip-add-hardware-random-number-genera.patch | 2 +-
...-arm64-dts-rockchip-rk3328-add-dfi-node.patch | 2 +-
...63-drv-net-phy-add-JLSemi-jl2xxx-driver.patch | 4 ++--
.../0900-arm-boot-add-dts-files.patch | 6 +++---
...ypto-rockchip-permit-to-pass-self-tests.patch | 10 +++++-----
11 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/target/linux/generic/hack-5.19/902-debloat_proc.patch b/target/linux/generic/hack-5.19/902-debloat_proc.patch
index a2b60e02d094ad..769cb67d7e80e3 100644
--- a/target/linux/generic/hack-5.19/902-debloat_proc.patch
+++ b/target/linux/generic/hack-5.19/902-debloat_proc.patch
@@ -341,7 +341,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/net/ipv4/fib_trie.c
+++ b/net/ipv4/fib_trie.c
-@@ -3026,11 +3026,13 @@ static const struct seq_operations fib_r
+@@ -3029,11 +3029,13 @@ static const struct seq_operations fib_r
int __net_init fib_proc_init(struct net *net)
{
@@ -357,7 +357,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
fib_triestat_seq_show, NULL))
goto out2;
-@@ -3041,17 +3043,21 @@ int __net_init fib_proc_init(struct net
+@@ -3044,17 +3046,21 @@ int __net_init fib_proc_init(struct net
return 0;
out3:
diff --git a/target/linux/generic/hack-5.19/904-debloat_dma_buf.patch b/target/linux/generic/hack-5.19/904-debloat_dma_buf.patch
index e2803e15a209c2..5163d5f3825871 100644
--- a/target/linux/generic/hack-5.19/904-debloat_dma_buf.patch
+++ b/target/linux/generic/hack-5.19/904-debloat_dma_buf.patch
@@ -64,7 +64,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
+dma-shared-buffer-objs := $(dma-buf-objs-y)
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
-@@ -1459,4 +1459,5 @@ static void __exit dma_buf_deinit(void)
+@@ -1473,4 +1473,5 @@ static void __exit dma_buf_deinit(void)
kern_unmount(dma_buf_mnt);
dma_buf_uninit_sysfs_statistics();
}
@@ -73,7 +73,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
+MODULE_LICENSE("GPL");
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
-@@ -4287,6 +4287,7 @@ int wake_up_state(struct task_struct *p,
+@@ -4284,6 +4284,7 @@ int wake_up_state(struct task_struct *p,
{
return try_to_wake_up(p, state, 0);
}
diff --git a/target/linux/generic/hack-5.19/952-add-net-conntrack-events-support-multiple-registrant.patch b/target/linux/generic/hack-5.19/952-add-net-conntrack-events-support-multiple-registrant.patch
index acf8deb7d2ab4c..abb339c03a882d 100644
--- a/target/linux/generic/hack-5.19/952-add-net-conntrack-events-support-multiple-registrant.patch
+++ b/target/linux/generic/hack-5.19/952-add-net-conntrack-events-support-multiple-registrant.patch
@@ -22,7 +22,7 @@ Signed-off-by: Zhi Chen <zhichen@codeaurora.org>
--- a/include/net/netfilter/nf_conntrack_ecache.h
+++ b/include/net/netfilter/nf_conntrack_ecache.h
-@@ -81,9 +81,14 @@ struct nf_ct_event_notifier {
+@@ -65,9 +65,14 @@ struct nf_ct_event_notifier {
int (*exp_event)(unsigned int events, const struct nf_exp_event *item);
};
@@ -38,7 +38,7 @@ Signed-off-by: Zhi Chen <zhichen@codeaurora.org>
void nf_ct_deliver_cached_events(struct nf_conn *ct);
int nf_conntrack_eventmask_report(unsigned int eventmask, struct nf_conn *ct,
-@@ -109,11 +114,13 @@ static inline void
+@@ -98,11 +103,13 @@ static inline void
nf_conntrack_event_cache(enum ip_conntrack_events event, struct nf_conn *ct)
{
#ifdef CONFIG_NF_CONNTRACK_EVENTS
@@ -53,7 +53,7 @@ Signed-off-by: Zhi Chen <zhichen@codeaurora.org>
e = nf_ct_ecache_find(ct);
if (e == NULL)
-@@ -117,20 +124,24 @@
+@@ -117,20 +124,24 @@ nf_conntrack_event_report(enum ip_conntr
u32 portid, int report)
{
#ifdef CONFIG_NF_CONNTRACK_EVENTS
@@ -80,9 +80,9 @@ Signed-off-by: Zhi Chen <zhichen@codeaurora.org>
#ifdef CONFIG_NF_CONNTRACK_EVENTS
--- a/include/net/netns/conntrack.h
+++ b/include/net/netns/conntrack.h
-@@ -112,6 +112,9 @@ struct netns_ct {
+@@ -107,6 +107,9 @@ struct netns_ct {
+ u8 sysctl_checksum;
- struct ct_pcpu __percpu *pcpu_lists;
struct ip_conntrack_stat __percpu *stat;
+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
+ struct atomic_notifier_head nf_conntrack_chain;
@@ -109,7 +109,7 @@ Signed-off-by: Zhi Chen <zhichen@codeaurora.org>
depends on NETFILTER_ADVANCED
--- a/net/netfilter/nf_conntrack_core.c
+++ b/net/netfilter/nf_conntrack_core.c
-@@ -2837,6 +2837,10 @@ int nf_conntrack_init_net(struct net *ne
+@@ -2802,6 +2802,10 @@ int nf_conntrack_init_net(struct net *ne
nf_conntrack_helper_pernet_init(net);
nf_conntrack_proto_pernet_init(net);
@@ -305,7 +305,7 @@ Signed-off-by: Zhi Chen <zhichen@codeaurora.org>
struct nf_conn *ct = item->ct;
struct sk_buff *skb;
unsigned int type;
-@@ -3825,11 +3832,17 @@ static int ctnetlink_stat_exp_cpu(struct
+@@ -3791,11 +3798,17 @@ static int ctnetlink_stat_exp_cpu(struct
}
#ifdef CONFIG_NF_CONNTRACK_EVENTS
@@ -323,7 +323,7 @@ Signed-off-by: Zhi Chen <zhichen@codeaurora.org>
static const struct nfnl_callback ctnl_cb[IPCTNL_MSG_MAX] = {
[IPCTNL_MSG_CT_NEW] = {
-@@ -3928,8 +3941,12 @@ static int __net_init ctnetlink_net_init
+@@ -3894,8 +3907,12 @@ static int __net_init ctnetlink_net_init
static void ctnetlink_net_pre_exit(struct net *net)
{
#ifdef CONFIG_NF_CONNTRACK_EVENTS
diff --git a/target/linux/generic/hack-5.19/953-net-patch-linux-kernel-to-support-shortcut-fe.patch b/target/linux/generic/hack-5.19/953-net-patch-linux-kernel-to-support-shortcut-fe.patch
index c7346c36a84f49..1d50ba2d2d737d 100644
--- a/target/linux/generic/hack-5.19/953-net-patch-linux-kernel-to-support-shortcut-fe.patch
+++ b/target/linux/generic/hack-5.19/953-net-patch-linux-kernel-to-support-shortcut-fe.patch
@@ -12,7 +12,7 @@
struct list_head *br_ip_list);
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
-@@ -1022,6 +1022,10 @@ struct sk_buff {
+@@ -1146,6 +1146,10 @@ struct sk_buff {
__u8 slow_gro:1;
__u8 csum_not_inet:1;
@@ -38,7 +38,7 @@
#endif
--- a/include/net/netfilter/nf_conntrack_ecache.h
+++ b/include/net/netfilter/nf_conntrack_ecache.h
-@@ -84,6 +84,8 @@ struct nf_ct_event_notifier {
+@@ -68,6 +68,8 @@ struct nf_ct_event_notifier {
#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
extern int nf_conntrack_register_notifier(struct net *net, struct notifier_block *nb);
extern int nf_conntrack_unregister_notifier(struct net *net, struct notifier_block *nb);
@@ -92,7 +92,7 @@
struct net_bridge_port *p;
--- a/net/core/dev.c
+++ b/net/core/dev.c
-@@ -3532,9 +3532,17 @@ static int xmit_one(struct sk_buff *skb,
+@@ -3581,9 +3581,17 @@ static int xmit_one(struct sk_buff *skb,
{
unsigned int len;
int rc;
@@ -110,8 +110,8 @@
+#endif
len = skb->len;
- PRANDOM_ADD_NOISE(skb, dev, txq, len + jiffies);
-@@ -5161,6 +5169,11 @@ void netdev_rx_handler_unregister(struct
+ trace_net_dev_start_xmit(skb, dev);
+@@ -5232,6 +5240,11 @@ void netdev_rx_handler_unregister(struct
}
EXPORT_SYMBOL_GPL(netdev_rx_handler_unregister);
@@ -123,7 +123,7 @@
/*
* Limit the use of PFMEMALLOC reserves to those protocols that implement
* the special handling of PFMEMALLOC skbs.
-@@ -5209,6 +5222,10 @@ static int __netif_receive_skb_core(stru
+@@ -5280,6 +5293,10 @@ static int __netif_receive_skb_core(stru
int ret = NET_RX_DROP;
__be16 type;
@@ -134,7 +134,7 @@
net_timestamp_check(!netdev_tstamp_prequeue, skb);
trace_netif_receive_skb(skb);
-@@ -5246,6 +5263,15 @@ another_round:
+@@ -5317,6 +5334,15 @@ another_round:
goto out;
}
diff --git a/target/linux/generic/pending-5.19/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch b/target/linux/generic/pending-5.19/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch
index 7adb2c7be3e1e0..3bdfb9baa9f482 100644
--- a/target/linux/generic/pending-5.19/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch
+++ b/target/linux/generic/pending-5.19/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch
@@ -71,7 +71,7 @@ Signed-off-by: Tobias Wolf <dev-NTEO@vplace.de>
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
-@@ -7698,7 +7698,7 @@ static void __init alloc_node_mem_map(st
+@@ -7702,7 +7702,7 @@ static void __init alloc_node_mem_map(st
if (pgdat == NODE_DATA(0)) {
mem_map = NODE_DATA(0)->node_mem_map;
if (page_to_pfn(mem_map) != pgdat->node_start_pfn)
diff --git a/target/linux/generic/pending-5.19/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/pending-5.19/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
index bb7eef0b20dde9..c3980518aa07c2 100644
--- a/target/linux/generic/pending-5.19/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
+++ b/target/linux/generic/pending-5.19/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
@@ -66,7 +66,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
static void rt_fibinfo_free(struct rtable __rcu **rtp)
--- a/net/ipv4/fib_trie.c
+++ b/net/ipv4/fib_trie.c
-@@ -2773,6 +2773,7 @@ static const char *const rtn_type_names[
+@@ -2776,6 +2776,7 @@ static const char *const rtn_type_names[
[RTN_THROW] = "THROW",
[RTN_NAT] = "NAT",
[RTN_XRESOLVE] = "XRESOLVE",
diff --git a/target/linux/rockchip/patches-5.19/0057-arm64-dts-rockchip-add-hardware-random-number-genera.patch b/target/linux/rockchip/patches-5.19/0057-arm64-dts-rockchip-add-hardware-random-number-genera.patch
index 266b8b28dec86e..4e9be328ee462c 100644
--- a/target/linux/rockchip/patches-5.19/0057-arm64-dts-rockchip-add-hardware-random-number-genera.patch
+++ b/target/linux/rockchip/patches-5.19/0057-arm64-dts-rockchip-add-hardware-random-number-genera.patch
@@ -31,7 +31,7 @@ Signed-off-by: wevsty <ty@wevs.org>
reg = <0x0 0xff100000 0x0 0x1000>;
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-@@ -2017,6 +2017,16 @@
+@@ -2042,6 +2042,16 @@
};
};
diff --git a/target/linux/rockchip/patches-5.19/0061-arm64-dts-rockchip-rk3328-add-dfi-node.patch b/target/linux/rockchip/patches-5.19/0061-arm64-dts-rockchip-rk3328-add-dfi-node.patch
index 2ab20487a0fe98..6d8ce8da4ab433 100644
--- a/target/linux/rockchip/patches-5.19/0061-arm64-dts-rockchip-rk3328-add-dfi-node.patch
+++ b/target/linux/rockchip/patches-5.19/0061-arm64-dts-rockchip-rk3328-add-dfi-node.patch
@@ -11,7 +11,7 @@ Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-@@ -1005,6 +1005,13 @@
+@@ -1023,6 +1023,13 @@
status = "disabled";
};
diff --git a/target/linux/rockchip/patches-5.19/0063-drv-net-phy-add-JLSemi-jl2xxx-driver.patch b/target/linux/rockchip/patches-5.19/0063-drv-net-phy-add-JLSemi-jl2xxx-driver.patch
index e2fb70694228e1..c879e16b056397 100644
--- a/target/linux/rockchip/patches-5.19/0063-drv-net-phy-add-JLSemi-jl2xxx-driver.patch
+++ b/target/linux/rockchip/patches-5.19/0063-drv-net-phy-add-JLSemi-jl2xxx-driver.patch
@@ -1,6 +1,6 @@
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
-@@ -260,6 +260,11 @@ config INTEL_XWAY_PHY
+@@ -267,6 +267,11 @@ config INTEL_XWAY_PHY
PEF 7061, PEF 7071 and PEF 7072 or integrated into the Intel
SoCs xRX200, xRX300, xRX330, xRX350 and xRX550.
@@ -14,7 +14,7 @@
help
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
-@@ -72,6 +72,8 @@ obj-$(CONFIG_DP83TC811_PHY) += dp83tc811
+@@ -74,6 +74,8 @@ obj-$(CONFIG_DP83TD510_PHY) += dp83td510
obj-$(CONFIG_FIXED_PHY) += fixed_phy.o
obj-$(CONFIG_ICPLUS_PHY) += icplus.o
obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o
diff --git a/target/linux/rockchip/patches-5.19/0900-arm-boot-add-dts-files.patch b/target/linux/rockchip/patches-5.19/0900-arm-boot-add-dts-files.patch
index eb2b744dca05b3..4ccb5cd31afaec 100644
--- a/target/linux/rockchip/patches-5.19/0900-arm-boot-add-dts-files.patch
+++ b/target/linux/rockchip/patches-5.19/0900-arm-boot-add-dts-files.patch
@@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -9,8 +9,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
+@@ -10,8 +10,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
@@ -13,7 +13,7 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
-@@ -22,6 +26,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-or
+@@ -23,6 +27,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-or
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
@@ -22,7 +22,7 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb
-@@ -40,6 +46,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-na
+@@ -41,6 +47,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-na
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb
diff --git a/target/linux/rockchip/patches-5.19/0903-crypto-rockchip-permit-to-pass-self-tests.patch b/target/linux/rockchip/patches-5.19/0903-crypto-rockchip-permit-to-pass-self-tests.patch
index af346f09d6bed5..5be8c13e21ca90 100644
--- a/target/linux/rockchip/patches-5.19/0903-crypto-rockchip-permit-to-pass-self-tests.patch
+++ b/target/linux/rockchip/patches-5.19/0903-crypto-rockchip-permit-to-pass-self-tests.patch
@@ -2133,7 +2133,7 @@ Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
.ivsize = DES_BLOCK_SIZE,
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
-@@ -784,7 +784,12 @@ config CRYPTO_DEV_IMGTEC_HASH
+@@ -669,7 +669,12 @@ config CRYPTO_DEV_IMGTEC_HASH
config CRYPTO_DEV_ROCKCHIP
tristate "Rockchip's Cryptographic Engine driver"
depends on OF && ARCH_ROCKCHIP
@@ -2146,7 +2146,7 @@ Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
select CRYPTO_LIB_DES
select CRYPTO_MD5
select CRYPTO_SHA1
-@@ -796,6 +801,16 @@ config CRYPTO_DEV_ROCKCHIP
+@@ -681,6 +686,16 @@ config CRYPTO_DEV_ROCKCHIP
This driver interfaces with the hardware crypto accelerator.
Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode.
@@ -2165,7 +2165,7 @@ Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
depends on ZYNQMP_FIRMWARE || COMPILE_TEST
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -16972,6 +16972,13 @@ F: Documentation/ABI/*/sysfs-driver-hid-
+@@ -17300,6 +17300,13 @@ F: Documentation/ABI/*/sysfs-driver-hid-
F: drivers/hid/hid-roccat*
F: include/linux/hid-roccat*
@@ -2370,7 +2370,7 @@ Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
#define SRST_CRYPTO1_S 184
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-@@ -1040,6 +1040,17 @@
+@@ -1058,6 +1058,17 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
@@ -2390,7 +2390,7 @@ Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
rockchip,grf = <&grf>;
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-@@ -573,6 +573,26 @@
+@@ -582,6 +582,26 @@
status = "disabled";
};
From dad62d5fb53d163926b971e824b39e57e7c8a673 Mon Sep 17 00:00:00 2001
From: aakkll <94471752+aakkll@users.noreply.github.com>
Date: Sat, 6 Aug 2022 00:23:05 +0800
Subject: [PATCH 8/9] kernel: bump 5.15 to 5.15.59 (#9891)
Signed-off-by: aakkll <94471752+aakkll@users.noreply.github.com>
---
include/kernel-5.15 | 4 ++--
.../ath79/patches-5.15/910-unaligned_access_hacks.patch | 8 ++++----
target/linux/generic/hack-5.15/902-debloat_proc.patch | 4 ++--
...ix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch | 2 +-
...llow-rejecting-with-source-address-failed-policy.patch | 2 +-
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/include/kernel-5.15 b/include/kernel-5.15
index 5bbf12d6f44687..716bcddf805028 100644
--- a/include/kernel-5.15
+++ b/include/kernel-5.15
@@ -1,2 +1,2 @@
-LINUX_VERSION-5.15 = .58
-LINUX_KERNEL_HASH-5.15.58 = d75bd9579c4b318e6162e21c591878fd37efda0f79c5cdd0dc4eb9ea9dfc4fa8
+LINUX_VERSION-5.15 = .59
+LINUX_KERNEL_HASH-5.15.59 = e6ddc642057340db06b3b921c2b31bfed2c611359e8f144c3e5cf9c3ac33bccb
diff --git a/target/linux/ath79/patches-5.15/910-unaligned_access_hacks.patch b/target/linux/ath79/patches-5.15/910-unaligned_access_hacks.patch
index ef9dab550837cf..1eaeefef00ce0a 100644
--- a/target/linux/ath79/patches-5.15/910-unaligned_access_hacks.patch
+++ b/target/linux/ath79/patches-5.15/910-unaligned_access_hacks.patch
@@ -305,7 +305,7 @@
list_for_each_entry(p, head, list) {
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
-@@ -613,48 +613,53 @@ static void tcp_options_write(__be32 *pt
+@@ -610,48 +610,53 @@ static void tcp_options_write(__be32 *pt
u16 options = opts->options; /* mungable copy */
if (unlikely(OPTION_MD5 & options)) {
@@ -382,7 +382,7 @@
}
if (unlikely(opts->num_sack_blocks)) {
-@@ -662,16 +667,17 @@ static void tcp_options_write(__be32 *pt
+@@ -659,16 +664,17 @@ static void tcp_options_write(__be32 *pt
tp->duplicate_sack : tp->selective_acks;
int this_sack;
@@ -406,7 +406,7 @@
}
tp->rx_opt.dsack = 0;
-@@ -684,13 +690,14 @@ static void tcp_options_write(__be32 *pt
+@@ -681,13 +687,14 @@ static void tcp_options_write(__be32 *pt
if (foc->exp) {
len = TCPOLEN_EXP_FASTOPEN_BASE + foc->len;
@@ -706,7 +706,7 @@
EXPORT_SYMBOL(xfrm_parse_spi);
--- a/net/ipv4/tcp_input.c
+++ b/net/ipv4/tcp_input.c
-@@ -4138,14 +4138,16 @@ static bool tcp_parse_aligned_timestamp(
+@@ -4140,14 +4140,16 @@ static bool tcp_parse_aligned_timestamp(
{
const __be32 *ptr = (const __be32 *)(th + 1);
diff --git a/target/linux/generic/hack-5.15/902-debloat_proc.patch b/target/linux/generic/hack-5.15/902-debloat_proc.patch
index fef28464bc0e1a..33d637f13eae91 100644
--- a/target/linux/generic/hack-5.15/902-debloat_proc.patch
+++ b/target/linux/generic/hack-5.15/902-debloat_proc.patch
@@ -341,7 +341,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/net/ipv4/fib_trie.c
+++ b/net/ipv4/fib_trie.c
-@@ -3019,11 +3019,13 @@ static const struct seq_operations fib_r
+@@ -3022,11 +3022,13 @@ static const struct seq_operations fib_r
int __net_init fib_proc_init(struct net *net)
{
@@ -357,7 +357,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
fib_triestat_seq_show, NULL))
goto out2;
-@@ -3034,17 +3036,21 @@ int __net_init fib_proc_init(struct net
+@@ -3037,17 +3039,21 @@ int __net_init fib_proc_init(struct net
return 0;
out3:
diff --git a/target/linux/generic/pending-5.15/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch b/target/linux/generic/pending-5.15/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch
index 30c70a6be995df..4e347a46710425 100644
--- a/target/linux/generic/pending-5.15/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch
+++ b/target/linux/generic/pending-5.15/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch
@@ -71,7 +71,7 @@ Signed-off-by: Tobias Wolf <dev-NTEO@vplace.de>
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
-@@ -7552,7 +7552,7 @@ static void __init alloc_node_mem_map(st
+@@ -7556,7 +7556,7 @@ static void __init alloc_node_mem_map(st
if (pgdat == NODE_DATA(0)) {
mem_map = NODE_DATA(0)->node_mem_map;
if (page_to_pfn(mem_map) != pgdat->node_start_pfn)
diff --git a/target/linux/generic/pending-5.15/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/pending-5.15/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
index 68960765bb051c..ac4396209efb4b 100644
--- a/target/linux/generic/pending-5.15/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
+++ b/target/linux/generic/pending-5.15/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
@@ -66,7 +66,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
static void rt_fibinfo_free(struct rtable __rcu **rtp)
--- a/net/ipv4/fib_trie.c
+++ b/net/ipv4/fib_trie.c
-@@ -2767,6 +2767,7 @@ static const char *const rtn_type_names[
+@@ -2770,6 +2770,7 @@ static const char *const rtn_type_names[
[RTN_THROW] = "THROW",
[RTN_NAT] = "NAT",
[RTN_XRESOLVE] = "XRESOLVE",
From 3c316115f97fbfd68e64aad50a87de6e80b20cd4 Mon Sep 17 00:00:00 2001
From: aakkll <94471752+aakkll@users.noreply.github.com>
Date: Sat, 6 Aug 2022 00:23:26 +0800
Subject: [PATCH 9/9] kernel: bump 5.18 to 5.18.16 (#9892)
Signed-off-by: aakkll <94471752+aakkll@users.noreply.github.com>
---
include/kernel-5.18 | 4 ++--
target/linux/generic/hack-5.18/902-debloat_proc.patch | 4 ++--
...20-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch | 2 +-
...v6-allow-rejecting-with-source-address-failed-policy.patch | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/include/kernel-5.18 b/include/kernel-5.18
index 554292138fdce4..532f60fb7bd95b 100644
--- a/include/kernel-5.18
+++ b/include/kernel-5.18
@@ -1,2 +1,2 @@
-LINUX_VERSION-5.18 = .15
-LINUX_KERNEL_HASH-5.18.15 = 69804febdc388a69dfb64493b7b58d402853de3a14144ea8db7fd67c30dcbe3c
+LINUX_VERSION-5.18 = .16
+LINUX_KERNEL_HASH-5.18.16 = f1f586251e63de14c86e5f95b96beb15a0434f1e6e21df788d123564af0d11ce
diff --git a/target/linux/generic/hack-5.18/902-debloat_proc.patch b/target/linux/generic/hack-5.18/902-debloat_proc.patch
index 5f96b0668e3f17..f9ddf5a093bef1 100644
--- a/target/linux/generic/hack-5.18/902-debloat_proc.patch
+++ b/target/linux/generic/hack-5.18/902-debloat_proc.patch
@@ -341,7 +341,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/net/ipv4/fib_trie.c
+++ b/net/ipv4/fib_trie.c
-@@ -3026,11 +3026,13 @@ static const struct seq_operations fib_r
+@@ -3029,11 +3029,13 @@ static const struct seq_operations fib_r
int __net_init fib_proc_init(struct net *net)
{
@@ -357,7 +357,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
fib_triestat_seq_show, NULL))
goto out2;
-@@ -3041,17 +3043,21 @@ int __net_init fib_proc_init(struct net
+@@ -3044,17 +3046,21 @@ int __net_init fib_proc_init(struct net
return 0;
out3:
diff --git a/target/linux/generic/pending-5.18/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch b/target/linux/generic/pending-5.18/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch
index f9a7d0cbed6d2f..0d36a85926c770 100644
--- a/target/linux/generic/pending-5.18/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch
+++ b/target/linux/generic/pending-5.18/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch
@@ -71,7 +71,7 @@ Signed-off-by: Tobias Wolf <dev-NTEO@vplace.de>
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
-@@ -7668,7 +7668,7 @@ static void __init alloc_node_mem_map(st
+@@ -7672,7 +7672,7 @@ static void __init alloc_node_mem_map(st
if (pgdat == NODE_DATA(0)) {
mem_map = NODE_DATA(0)->node_mem_map;
if (page_to_pfn(mem_map) != pgdat->node_start_pfn)
diff --git a/target/linux/generic/pending-5.18/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/pending-5.18/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
index cc261ab98073da..534cd5a9d12571 100644
--- a/target/linux/generic/pending-5.18/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
+++ b/target/linux/generic/pending-5.18/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
@@ -66,7 +66,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
static void rt_fibinfo_free(struct rtable __rcu **rtp)
--- a/net/ipv4/fib_trie.c
+++ b/net/ipv4/fib_trie.c
-@@ -2773,6 +2773,7 @@ static const char *const rtn_type_names[
+@@ -2776,6 +2776,7 @@ static const char *const rtn_type_names[
[RTN_THROW] = "THROW",
[RTN_NAT] = "NAT",
[RTN_XRESOLVE] = "XRESOLVE",