[help] jt12 interface spec & considerations for migrating from real ICs

[planetarian]

Hello. As a preamble, I'm a beginner in Verilog (and FPGAs in general) though I've worked plenty with physical YM2612/3438 chips in the past. So I have a surface familiarity with the general function of the chip, but not so well-versed in the gritty inner workings (though recently I have found myself learning a lot!).

I tried using jt12 in the past but my familiarity with the development environment was zero back then, so I really had no idea what I was doing at the time and kinda gave up. Lately, after a burst of newfound motivation, I came back to this project and was successful implementing and making sound with Nuked-OPN2, but I found it's a bit too heavy for my purposes -- I need to be able to create multiple instances of the chip, and the whopping 6500 registers per instance of Nuked starves my Tang Primer 25K of resources rather quickly. So I decided to give jt12 another shot, having become more familiar with the platform since my previous attempt. The resource consumption is far better, but I'm trying to wrap my head around interfacing with the jt12 module and I'm still having trouble getting it to actually do anything (or show any signs of life, for that matter).

So I thought I'd ask for some clarification on some matters i've been uncertain of that might help point me in the right direction.

1. The wiki page claims that the jt12 module requires a CPU clock and an FM clock, but the jt12 module only appears to accept a single clk signal. Has the design changed since the wiki description was written? What is the frequency expected for the clk signal?
   While I was looking through the code, I noticed a clock signal that expects to be operated at 666khz, and it seemed to be based on clk with a divisor of 15, which suggested to me that clk operates around the YM stock 7.67/8MHz -- but comments refer to it as CPU clock, a term the wiki uses to refer to the clock that must be divided by 6 to get the FM clock, so I'm a bit confused and might've misread the code. I tried 46MHz as well (7.67*6) with no success.

2. Are there any differences regarding the standard interface "pins"? I notice rst appears to be active-high rather than the active-low of IC; are there differences with regard to usage of e.g. CS/WR etc? Are the timings for setting inputs similar to real hardware?

3. I notice there is no RD input; that in mind, are there any considerations to using dout, or does it simply Just Work?

4. What is the effect of en_hifi_pcm, and is it relevant for the purposes of emulating a YM2612/3438?

5. What is snd_sample? It's probably too early to ask about this one, but I thought I'd ask. At first glance doesn't appear to be like Nuked's PDM outputs since there's just the single output, but I haven't dug that deeply on this yet.

6. I suppose it should probably be obvious given the other issues mentioning the matter, but just for 100% clarity, is there really no reproduction of the YM2612's ladder distortion?

I tried to look for comments and documentation for these matters wherever I possibly could, but it's possible I missed something, so don't be afraid to tell me to RTFM if I missed something obvious.

Also, I have a 32-input logic analyzer that I've been using to monitor communication, so if you have any tips on signals I could monitor as part of the debug process, I'm all ears.

Thanks in advance!