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Integrate LLVM at llvm/llvm-project@b0329206 #18102

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merged 3 commits into from
Aug 6, 2024
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Integrate LLVM at llvm/llvm-project@b0329206 #18102

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410a2d7
Integrate LLVM at llvm/llvm-project@b0329206
hanhanW Aug 5, 2024
4bc6d1c
Fixes for https://github.com/llvm/llvm-project/commit/0d9b4394081df95…
hanhanW Aug 5, 2024
e5b2f8e
Add missing layout to descriptor set layout
hanhanW Aug 5, 2024
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26 changes: 13 additions & 13 deletions compiler/src/iree/compiler/Codegen/Common/ConvertBf16ToUInt16Buffers.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -288,19 +288,19 @@ struct ConvertBf16ToUInt16BuffersPass final
vector::BroadcastOp, vector::ShuffleOp, vector::ExtractElementOp,
vector::ExtractOp, vector::InsertElementOp, vector::InsertOp,
vector::ScalableInsertOp, vector::ScalableExtractOp,
vector::InsertStridedSliceOp, vector::ReshapeOp,
vector::ExtractStridedSliceOp, vector::TransferReadOp,
vector::TransferWriteOp, vector::LoadOp, vector::StoreOp,
vector::MaskedLoadOp, vector::MaskedStoreOp, vector::GatherOp,
vector::ScatterOp, vector::ExpandLoadOp, vector::CompressStoreOp,
vector::ShapeCastOp, vector::ConstantMaskOp, vector::CreateMaskOp,
vector::MaskOp, vector::TransposeOp, vector::FlatTransposeOp,
vector::SplatOp, vector::YieldOp>([&typeConverter](Operation *op) {
bool legal = typeConverter.isLegal(op);
LLVM_DEBUG(if (!legal) llvm::dbgs()
<< "Bf16Emulation: illegal op: " << *op << "\n");
return legal;
});
vector::InsertStridedSliceOp, vector::ExtractStridedSliceOp,
vector::TransferReadOp, vector::TransferWriteOp, vector::LoadOp,
vector::StoreOp, vector::MaskedLoadOp, vector::MaskedStoreOp,
vector::GatherOp, vector::ScatterOp, vector::ExpandLoadOp,
vector::CompressStoreOp, vector::ShapeCastOp, vector::ConstantMaskOp,
vector::CreateMaskOp, vector::MaskOp, vector::TransposeOp,
vector::FlatTransposeOp, vector::SplatOp, vector::YieldOp>(
[&typeConverter](Operation *op) {
bool legal = typeConverter.isLegal(op);
LLVM_DEBUG(if (!legal) llvm::dbgs()
<< "Bf16Emulation: illegal op: " << *op << "\n");
return legal;
});

RewritePatternSet patterns(ctx);
populateIreeBf16EmulationPatterns(patterns, typeConverter);
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3 changes: 2 additions & 1 deletion samples/custom_dispatch/cpu/embedded/example_hal.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,8 @@
#pipeline_layout = #hal.pipeline.layout<push_constants = 1, sets = [
<0, bindings = [
<0, storage_buffer, ReadOnly>,
<1, storage_buffer>
<1, storage_buffer, ReadOnly>,
<2, storage_buffer>
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I don't know which commit breaks it, but the fix is reasonable to me. It is required by l.183, which has binding(2) while ordinal 2 not present in descriptor set layout. So the fix is adding one more storage_buffer to the set.

          // Bindings are accessed by reference.
          %binding0 = hal.interface.binding.subspan layout(#pipeline_layout) set(0) binding(0) alignment(64) offset(%c0) : memref<?xf32>{%dim}
          %binding1 = hal.interface.binding.subspan layout(#pipeline_layout) set(0) binding(1) alignment(64) offset(%c0) : memref<?xf32>{%dim}
          %binding2 = hal.interface.binding.subspan layout(#pipeline_layout) set(0) binding(2) alignment(64) offset(%c0) : memref<?xf32>{%dim}

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Likely unrelated to this LLVM integrate. I thought I had the ASan job running on all (relevant) PRs and commits, but I had a bug. Fix: #18108

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2 changes: 1 addition & 1 deletion third_party/llvm-project
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Submodule llvm-project updated 820 files
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